STW24N60M6
Datasheet
N-channel 600 V, 162 mΩ typ., 17 A, MDmesh™ M6 Power MOSFET in a TO-247 package
G(1)
TO-247
1
2
3
D(2)
S(3)
Product status link
STW24N60M6
Product summary
Order code STW24N60M6
Marking
Package
Packing
24N60M6
TO-247
Tube
NG1D2S3Z
Features
Order code
STW24N60M6
V
DS
600 V
• Reduced switching losses
• Lower R
DS(on)
per area vs previous generation
• Low gate input resistance
• 100% avalanche tested
• Zener-protected
R
DS(on)
max.
190 mΩ
I
D
17 A
Applications
• Switching applications
• LLC converters
• Boost PFC converters
Description
The new MDmesh™ M6 technology incorporates the most recent advancements to the well-known and consolidated MDmesh family of SJ MOSFETs.
STMicroelectronics builds on the previous generation of MDmesh devices through its new M6 technology, which combines excellent R
DS(on)
per area improvement with one of the most effective switching behaviors available, as well as a user-friendly experience for maximum end-application efficiency.
DS12730 - Rev 1 - August 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
STW24N60M6
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
V
GS
Gate-source voltage
Parameter
I
D
Drain current (continuous) at T case
= 25 °C
Drain current (continuous) at T case
= 100 °C
Drain current (pulsed) I
DM
(1)
P
TOT
dv/dt (2)
Total dissipation at T case
= 25 °C
dv/dt (3)
T stg
T j
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Storage temperature range
Operating junction temperature range
1. Pulse width is limited by safe operating area.
2. I
SD
≤ 17 A, di/dt = 400 A/μs, V
DS
< V
(BR)DSS
, V
DD
= 400 V
3. V
DS
≤ 480 V
Symbol
R thj-case
R thj-amb
Table 2. Thermal data
Thermal resistance junction-case
Parameter
Thermal resistance junction-ambient
Symbol
I
AR
E
AS
Table 3. Avalanche characteristics
Parameter
Avalanche current, repetitive or non-repetitive
(pulse width limited by T
Jmax
)
Single pulse avalanche energy
(starting T j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Value
±25
17
10.7
52.5
130
15
50
-55 to 150
Unit
V
A
A
W
V/ns
°C
Value
0.96
50
Unit
°C/W
°C/W
Value
3.2
250
Unit
A mJ
DS12730 - Rev 1 page 2/13
2
STW24N60M6
Electrical characteristics
Electrical characteristics
(T case
= 25 °C unless otherwise specified).
Table 4. On/off states
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Parameter Test conditions
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 600 V
Zero gate voltage drain current
Gate-body leakage current
V
GS
= 0 V, V
DS
= 600 V,
T case
= 125 °C (1)
V
DS
= 0 V, V
GS
= ±25 V
Gate threshold voltage V
DS
= V
GS
, I
D
= 250 µA
Static drain-source on-resistance I
D
= 8.5 A, V
GS
= 10 V
1. Defined by design, not subject to production test.
Min.
600
3.25
Typ.
Max.
Unit
V
1
µA
100
4
162
±5
4.75
190
µA
V mΩ
Table 5. Dynamic
Symbol
C iss
C oss
C rss
C oss eq.
(1)
R
Q
Q
Q
G g gs gd
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent output capacitance
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
Test conditions
= 100 V, f = 1 MHz, V
GS
= 0 V
V
DS
= 0 to 480 V, V
GS
= 0 V f = 1 MHz, I
D
= 0 A
V
DD
= 480 V, I
D
= 17 A,
V
GS
= 0 to 10 V
(see
Figure 14. Test circuit for gate charge behavior
)
Min.
-
-
-
-
-
-
-
-
Typ.
960
76
4.5
181
5
23
4.8
12.8
Max.
-
-
-
-
-
-
-
-
Unit pF pF
Ω nC
1. C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss to 80% V
DSS
.
when V
DS
increases from 0
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 6. Switching times
Test conditions
V
DD
= 300 V, I
D
= 8.5 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see
Figure 13. Test circuit for resistive load switching times and
Figure 18. Switching time waveform
)
Min.
-
-
-
-
Typ.
17.7
32
38.3
9
Max.
-
-
-
-
Unit ns
DS12730 - Rev 1 page 3/13
STW24N60M6
Electrical characteristics
Symbol
I
SD
I
SDM
(1)
V
SD
(2)
t rr
Q rr
I
RRM t rr
Q rr
I
RRM
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Table 7. Source-drain diode
Test conditions
I
SD
= 17 A, V
GS
= 0 V
I
SD
= 17 A, di/dt = 100 A/µs,
V
DD
= 60 V
(see
Figure 15. Test circuit for inductive load switching and diode recovery times
)
I
SD
= 17 A, di/dt = 100 A/µs,
V
DD
= 60 V,
T j
= 150 °C
(see
Figure 15. Test circuit for inductive load switching and diode recovery times
)
1. Pulse width is limited by safe operating area.
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Min.
-
-
-
-
-
-
-
-
-
25.1
Typ.
Max.
17
52.5
1.6
225
2.3
Unit
A
A
V ns
µC
20.4
387
3.85
A ns
µC
A
DS12730 - Rev 1 page 4/13
STW24N60M6
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
I
D
(A)
Figure 1. Safe operating area
GADG060820181510SOA
10 1 t p
= 10µs t p
= 100µs t p
= 1ms t p
= 10ms
10 0
Operation in this area is limited by R
DS(on)
10 -1
10 -2
10 -1 10 0
T j
≤150 °C
T c
= 25°C single pulse
10 1 10 2
V
DS
(V)
I
D
(A)
50
Figure 3. Output characteristics
GADG200720180952OCH
V
GS
= 9, 10 V
V
GS
= 8 V
40
30
V
GS
= 7 V
20
10
V
GS
= 6 V
0
0 2 4 6 8 10 12 14 16 V
DS
(V)
Figure 5. Gate charge vs gate-source voltage
V
GS
(V)
12
GADG200720180952QVG V
DS
(V)
600
V
DS
10 500
8
V
DD
= 480 V
I
D
= 17 A
400
6 300
4
2
0
0 4 8 12 16 20 24
200
100
Q
0 g
(nC)
Figure 2. Thermal impedance
I
D
(A)
50
Figure 4. Transfer characteristics
GADG200720180952TCH
V
DS
= 16 V 40
30
20
10
0
2 3 4 5 6 7 8 9 V
GS
(V)
Figure 6. Static drain-source on-resistance
R
DS(on)
(mΩ)
178
174
170
166
162
V
GS
= 10V
GADG010820181133RID
158
154
150
0 2 4 6 8 10 12 14 16 I
D
(A)
DS12730 - Rev 1 page 5/13
C
(pF)
Figure 7. Capacitance variations
GADG190720181455CVR
10 3 C
ISS
10 2
10 1 f = 1 MHz
C
OSS
C
RSS
10 0
10 -1 10 0 10 1 10 2
V
DS
(V)
Figure 9. Normalized gate threshold voltage vs temperature
V
GS(th)
(norm.)
GADG190720181456VTH
1.1
I
D
= 250 µA
1.0
0.9
0.8
0.7
0.6
-75 -25 25 75 125 T j
(°C)
Figure 11. Normalized V
(BR)DSS
vs temperature
V
(BR)DSS
(norm.)
GADG190720181457BDV
1.08
I
D
= 1 mA
1.04
1.00
0.96
0.92
0.88
-75 -25 25 75 125 T j
(°C)
STW24N60M6
Electrical characteristics (curves)
Figure 8. Output capacitance stored energy
E
OSS
(µJ)
10
9
8
5
4
7
6
GADG190720181457EOS
3
2
1
0
0 100 200 300 400 500 600 V
DS
(V)
Figure 10. Normalized on-resistance vs temperature
R
DS(on)
(norm.)
GADG190720181456RON
2.2
V
GS
= 10 V
1.8
1.4
1
0.6
0.2
-75 -25 25 75 125 T j
(°C)
Figure 12. Source-drain diode forward characteristics
V
SD
(V)
1.1
GADG010820181135SDF
T j
= -50 °C
1
0.9
0.8
0.7
T j
= 25 °C
T j
= 150 °C
0.6
0.5
0 2 4 6 8 10 12 14 16 I
SD
(A)
DS12730 - Rev 1 page 6/13
STW24N60M6
Test circuits
3
Test circuits
Figure 13. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF V
DD
D.U.T.
Figure 14. Test circuit for gate charge behavior
V
DD
RL
V
GS pulse width
2200
μF
+
I
G
= CONST
2.7 kΩ
47 kΩ
1 kΩ
100 Ω D.U.T.
V
G
AM01469v10
AM01468v1
Figure 15. Test circuit for inductive load switching and diode recovery times
Figure 16. Unclamped inductive load test circuit
G
25 Ω
D
A
D.U.T.
S
B
A A fast diode
B
B
G
+
_
R
G
100 µH
D
D.U.T.
S
3.3
µF
+
1000
µF
V
DD
AM01470v1
Figure 17. Unclamped inductive waveform
V
(BR)DSS
V
D
I
DM
I
D
V
DD
V
DD
AM01472v1
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF
V
DD
D.U.T.
AM01471v1
0
Figure 18. Switching time waveform t d(on) t on t r t d(off) t off t f
90% 90%
10%
V
GS
V
DS
90%
10%
0 10%
AM01473v1
DS12730 - Rev 1 page 7/13
4
STW24N60M6
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
DS12730 - Rev 1 page 8/13
4.1
TO-247 package information
Figure 19. TO-247 package outline
STW24N60M6
TO-247 package information
DS12730 - Rev 1
0075325_9 page 9/13
Dim.
e
L
L1
D
E
A
A1 b b1 b2 c
L2
ØP
ØR
S
Table 8. TO-247 package mechanical data mm
Typ.
Min.
4.85
2.20
1.0
2.0
3.0
0.40
19.85
15.45
5.30
14.20
3.70
5.45
18.50
3.55
4.50
5.30
5.50
STW24N60M6
TO-247 package information
Max.
5.15
2.60
1.40
2.40
3.40
0.80
20.15
15.75
5.60
14.80
4.30
3.65
5.50
5.70
DS12730 - Rev 1 page 10/13
Revision history
Date
06-Aug-2018
Version
1
Table 9. Document revision history
Changes
Initial release.
STW24N60M6
DS12730 - Rev 1 page 11/13
STW24N60M6
Contents
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
TO-247 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
DS12730 - Rev 1 page 12/13
STW24N60M6
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STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS12730 - Rev 1 page 13/13
