STW65N80K5
N-channel 800 V, 0.07
Ω typ., 46 A MDmesh™ K5
Power MOSFET in a TO-247 package
Datasheet - production data
1
2
3
Features
Order code V
DS
R
DS(on)
max. I
D
P
TOT
STW65N80K5 800 V 0.08 Ω 46 A 446 W
Industry’s lowest R
DS(on)
x area
Industry’s best figure of merit (FoM)
Ultra low gate charge
100% avalanche tested
Zener-protected
TO-247
Applications
Switching applications
Figure 1: Internal schematic diagram
Order code
STW65N80K5
Description
This very high voltage N-channel Power
MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency.
Table 1: Device summary
Marking Package
65N80K5 TO-247
Packing
Tube
October 2015 DocID027717 Rev 2
This is information on a product in full production.
1/12 www.st.com
Contents
Contents
STW65N80K5
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
TO-247 package information ............................................................. 9
5 Revision history ............................................................................ 11
2/12 DocID027717 Rev 2
STW65N80K5
1 Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
GS
I
D
I
DM
(1)
P
TOT
dv/dt (2) dv/dt (3)
T stg
T j
Gate-source voltage
Drain current (continuous) at T case
= 25 °C
Drain current (continuous) at T case
= 100 °C
Drain current (pulsed)
Total dissipation at T case
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Storage temperature
Operating junction temperature
Notes:
(1)
Pulse width is limited by safe operating area.
(2)
I
SD
≤ 46 A, di/dt=100 A/μs; V
DS
peak < V
(BR)DSS
, V
DD
= 80% V
(BR)DSS
.
(3)
V
DS
≤ 640 V
Symbol
Table 3: Thermal data
Parameter
R thj-case
R thj-amb
Thermal resistance junction-case
Thermal resistance junction-ambient
Symbol
I
AR
(1)
E
AS
(2)
Table 4: Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive
Single pulse avalanche energy
Notes:
(1)
Pulse width limited by T jmax
.
(2)
starting T j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V.
Electrical ratings
Value
±30
46
30
184
446
4.5
50
-55 to 150
Unit
V
A
A
W
V/ns
°C
Value
0.28
50
Unit
°C/W
Value
16
700
Unit
A mJ
DocID027717 Rev 2 3/12
Electrical characteristics
2 Electrical characteristics
(T case
= 25 °C unless otherwise specified)
Symbol Parameter
Table 5: Static
Test conditions
V
(BR)DSS
I
DSS
I
GSS
Drain-source breakdown voltage
V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 800 V
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 800 V,
T case
= 125 °C
Gate-body leakage current V
DS
= 0 V, V
GS
= ±20 V
V
DS
= V
GS
, I
D
= 100 µA V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source onresistance
V
GS
= 10 V, I
D
= 23 A
Symbol Parameter
Table 6: Dynamic
Test conditions
C
C
C iss oss rss
Input capacitance
Output capacitance
Reverse transfer capacitance
C
oss(eq)
(1)
Equivalent output capacitance
R
G
Q g
Q gs
Intrinsic gate resistance
Total gate charge
Gate-source charge
Q gd
Gate-drain charge
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
V
DS
= 0 to 640 V, V
GS
= 0 V f = 1 MHz, I
D
= 0 A
V
DD
= 640 V, I
D
= 46 A,
V
GS
= 10 V (see Figure 14:
"Test circuit for gate charge behavior" )
-
-
-
-
-
STW65N80K5
Min. Typ. Max. Unit
800 V
1
µA
50
4
±10 µA
5 V
0.07 0.08 Ω
3
Min. Typ. Max. Unit
-
-
3230
310
-
- pF
- 3 -
734
1.9
92
18
65
-
-
-
-
- pF
Ω nC
Notes:
(1)
C oss(eq)
is defined as a constant equivalent capacitance giving the same charging time as C
OSS
when V
DS increases from 0 to 80% V
DSS
.
Symbol Parameter
Table 7: Switching times
Test conditions Min. Typ. Max. Unit t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time t f
Fall time
V
DD
= 400 V, I
D
= 23 A
R
G
= 4.7
Ω, V
GS
= 10 V (see
Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform" )
-
-
-
-
34
30
90
10
-
-
-
- ns
4/12 DocID027717 Rev 2
STW65N80K5
Symbol
I
SD
Source-drain current
I
SDM
(1)
Source-drain current
(pulsed)
V
SD
(2)
Forward on voltage t rr
Q rr
Reverse recovery time
Reverse recovery charge
I
I
RRM t
Q rr rr
RRM
Parameter
Reverse recovery current
Reverse recovery time
Table 8: Source-drain diode
Test conditions
Reverse recovery charge
Reverse recovery current
V
GS
= 0 V, I
SD
= 46 A
I
SD
= 46 A, di/dt = 100 A/µs,
V
DD
= 60 V (see Figure 15:
"Test circuit for inductive load switching and diode recovery times" )
I
SD
= 46 A, di/dt = 100 A/µs,
V
DD
= 60 V, T j
= 150 °C (see
Figure 15: "Test circuit for inductive load switching and diode recovery times" )
Electrical characteristics
Min. Typ. Max. Unit
- 46 A
- 184 A
-
-
-
650
20
1.5 V ns
µC
-
-
-
-
60
845
28
66
A ns
µC
A
Notes:
(1)
Pulse width is limited by safe operating area.
(2)
Pulse test: pulse duration = 300 µs, duty cycle 1.5%.
Symbol
Table 9: Gate-source Zener diode
Parameter Test conditions Min. Typ. Max. Unit
V
(BR)GSO
Gate-source breakdown voltage I
GS
= ±1 mA, I
D
= 0 A ±30 - - V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry.
DocID027717 Rev 2 5/12
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STW65N80K5
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
6/12 DocID027717 Rev 2
STW65N80K5
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs temperature
Figure 10: Normalized on-resistance vs temperature
Figure 11: Normalized V(BR)DSS vs temperature
Figure 12: Maximum avalanche energy vs temperature
DocID027717 Rev 2 7/12
Test circuits
3 Test circuits
Figure 13: Test circuit for resistive load switching times
STW65N80K5
Figure 14: Test circuit for gate charge behavior
Figure 15: Test circuit for inductive load switching and diode recovery times
Figure 16: Unclamped inductive load test circuit
Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform
8/12 DocID027717 Rev 2
STW65N80K5
4
4.1
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
TO-247 package information
Figure 19: TO-247 package outline
DocID027717 Rev 2 9/12
Package information
Dim. e
L
L1
L2
ØP
ØR
S b2 c
D
E
A
A1 b b1
Table 10: TO-247 package mechanical data mm.
Min. Typ.
4.85
2.20
1.0
2.0
3.0
0.40
19.85
15.45
5.30
14.20
3.70
3.55
4.50
5.30
5.45
18.50
5.50
STW65N80K5
Max.
5.15
2.60
1.40
2.40
3.40
0.80
20.15
15.75
5.60
14.80
4.30
3.65
5.50
5.70
10/12 DocID027717 Rev 2
STW65N80K5
5
Revision history
Revision history
Date Revision
Table 11: Document revision history
Changes
21-May-2015
02-Oct-2015
1
2
First release.
Text and formatting changes throughout document.
Datasheet status promoted from preliminary to production data.
On cover page:
- updated title description and Features table.
Updated sections - Electrical ratings and Electrical characteristics.
Added section - Electrical characteristics (curves).
DocID027717 Rev 2 11/12
STW65N80K5
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12/12 DocID027717 Rev 2
