STI18N65M2, STP18N65M2
N-channel 650 V, 0.275 Ω typ., 12 A MDmesh™ M2
Power MOSFET in I²PAK and TO-220 packages
Datasheet - production data
Features
Order code
VDS
RDS(on) max
ID
650V
0.33Ω
12 A
TAB
TAB
STI18N65M2
STP18N65M2
3
12
I2PAK
3
1
2
• Extremely low gate charge
TO-220
• Excellent output capacitance (Coss) profile
• 100% avalanche tested
• Zener-protected
Figure 1. Internal schematic diagram
, TAB
Applications
• Switching applications
• LLC converters, resonant converters
Description
These devices are N-channel Power MOSFETs
developed using MDmesh™ M2 technology.
Thanks to their strip layout and improved vertical
structure, the devices exhibit low on-resistance
and optimized switching characteristics, rendering
them suitable for the most demanding high
efficiency converters.
AM15572v1
Table 1. Device summary
Order code
Marking
Package
STI18N65M2
I
Tube
18N65M2
STP18N65M2
January 2015
This is information on a product in full production.
Packaging
2PAK
TO-220
DocID026870 Rev 2
1/15
www.st.com
Contents
STI18N65M2, STP18N65M2
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2/15
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DocID026870 Rev 2
STI18N65M2, STP18N65M2
1
Electrical ratings
Electrical ratings
Table 2. Absolute maximum ratings
Symbol
VGS
Value
Unit
± 25
V
Gate-source voltage
ID
Drain current (continuous) at TC = 25 °C
12
A
ID
Drain current (continuous) at TC = 100 °C
8
A
IDM(1)
Drain current (pulsed)
48
A
PTOT
Total dissipation at TC = 25 °C
110
W
Peak diode recovery voltage slope
15
V/ns
MOSFET dv/dt ruggedness
50
V/ns
dv/dt
(2)
dv/dt(3)
Tstg
Tj
1.
Parameter
Storage temperature
- 55 to 150
°C
Max. operating junction temperature
150
Pulse width limited by safe operating area
2. ISD ≤ 12 A, di/dt ≤ 400 A/µs; VDS peak < V(BR)DSS, VDD=400 V.
3. VDS ≤ 520V
Table 3. Thermal data
Symbol
Parameter
Value
Rthj-case Thermal resistance junction-case max
1.14
Rthj-amb Thermal resistance junction-ambient max
62.5
Unit
°C/W
Table 4. Avalanche characteristics
Symbol
Parameter
IAR
Avalanche current, repetitive or not
repetitive (pulse width limited by Tjmax)
EAS
Single pulse avalanche energy
(starting Tj = 25 °C, ID = IAR; VDD = 50 V)
DocID026870 Rev 2
Value
Unit
2
A
450
mJ
3/15
15
Electrical characteristics
2
STI18N65M2, STP18N65M2
Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 5. On /off states
Symbol
V(BR)DSS
Parameter
Drain-source
breakdown voltage
Test conditions
ID = 1 mA, VGS = 0 V
IDSS
VDS = 650 V
Zero gate voltage
drain current (VGS = 0) VDS = 650 V, TC = 125 °C
IGSS
Gate-body leakage
current (VDS = 0)
Min.
Typ.
Gate threshold voltage VDS = VGS, ID = 250 µA
RDS(on)
Static drain-source
on-resistance
Unit
650
V
1
µA
100
µA
±10
µA
3
4
V
0.275
0.33
Ω
Min.
Typ.
Max.
Unit
-
770
-
pF
-
35
-
pF
-
1.2
-
pF
VGS = ± 25 V
VGS(th)
Max.
2
VGS = 10 V, ID = 6 A
Table 6. Dynamic
Symbol
Ciss
Parameter
Test conditions
Input capacitance
VDS = 100 V, f = 1 MHz,
VGS = 0 V
Coss
Output capacitance
Crss
Reverse transfer
capacitance
Coss eq.(1)
Equivalent output
capacitance
VDS = 0 to 480 V, VGS = 0 V
-
175
-
pF
RG
Intrinsic gate
resistance
f = 1 MHz, ID = 0 A
-
6.1
-
Ω
Qg
Total gate charge
-
20
-
nC
-
3.6
-
nC
-
8.5
-
nC
Qgs
Gate-source charge
Qgd
Gate-drain charge
VDD = 520 V, ID = 12 A,
VGS = 10 V (see Figure 15)
1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS
Table 7. Switching times
Symbol
td(on)
tr
td(off)
tf
4/15
Parameter
Test conditions
Turn-on delay time
Rise time
Turn-off delay time
VDD = 325 V, ID = 6 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 14 and Figure 19)
Fall time
DocID026870 Rev 2
Min.
Typ.
Max.
Unit
-
11
-
ns
-
7.5
-
ns
-
46
-
ns
-
12.5
-
ns
STI18N65M2, STP18N65M2
Electrical characteristics
Table 8. Source drain diode
Symbol
Parameter
Test conditions
Min.
Typ.
Max. Unit
Source-drain current
-
12
A
ISDM
(1)
Source-drain current (pulsed)
-
48
A
VSD
(2)
Forward on voltage
-
1.6
V
ISD
trr
ISD = 12 A, VGS = 0 V
Reverse recovery time
Qrr
Reverse recovery charge
IRRM
Reverse recovery current
trr
Reverse recovery time
Qrr
Reverse recovery charge
IRRM
Reverse recovery current
ISD = 12 A, di/dt = 100 A/µs
VDD = 60 V (see Figure 16)
ISD = 12 A, di/dt = 100 A/µs
VDD = 60 V, Tj = 150 °C
(see Figure 16)
-
331
ns
-
3.4
µC
-
20.5
A
-
462
ns
-
4.6
µC
-
20
A
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
DocID026870 Rev 2
5/15
15
Electrical characteristics
2.1
STI18N65M2, STP18N65M2
Electrical characteristics (curves)
Figure 2. Safe operating area
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Figure 3. Thermal impedance
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Figure 4. Output characteristics
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Figure 6. Gate charge vs gate-source voltage
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Figure 7. Static drain-source on-resistance
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Figure 5. Transfer characteristics
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DocID026870 Rev 2
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STI18N65M2, STP18N65M2
Electrical characteristics
Figure 8. Capacitance variations
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Figure 9. Output capacitance stored energy
(266
-
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Figure 10. Normalized gate threshold voltage vs
temperature
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Figure 12. Source-drain diode forward
characteristics
96'
9
9'6 9
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Figure 11. Normalized on-resistance vs
temperature
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Figure 13. Normalized V(BR)DSS vs temperature
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DocID026870 Rev 2
7- &
7/15
15
Test circuits
3
STI18N65M2, STP18N65M2
Test circuits
Figure 14. Switching times test circuit for
resistive load
Figure 15. Gate charge test circuit
9''
9
μF
VDD
VD
VGS
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Figure 16. Test circuit for inductive load
switching and diode recovery times
A
A
Figure 17. Unclamped inductive load test circuit
L
A
D
G
D.U.T.
FAST
DIODE
B
B
S
VD
L=100μH
3.3
μF
B
25 Ω
1000
μF
D
VDD
2200
μF
3.3
μF
VDD
ID
G
RG
S
Vi
D.U.T.
Pw
AM01470v1
AM01471v1
Figure 18. Unclamped inductive waveform
Figure 19. Switching time waveform
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DocID026870 Rev 2
9'6
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STI18N65M2, STP18N65M2
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
DocID026870 Rev 2
9/15
15
Package mechanical data
STI18N65M2, STP18N65M2
Figure 20. I²PAK (TO-262) drawing
0004982_Rev_H
10/15
DocID026870 Rev 2
STI18N65M2, STP18N65M2
Package mechanical data
Table 9. I²PAK (TO-262) mechanical data
mm.
DIM.
min.
typ
max.
A
4.40
4.60
A1
2.40
2.72
b
0.61
0.88
b1
1.14
1.70
c
0.49
0.70
c2
1.23
1.32
D
8.95
9.35
e
2.40
2.70
e1
4.95
5.15
E
10
10.40
L
13
14
L1
3.50
3.93
L2
1.27
1.40
DocID026870 Rev 2
11/15
15
Package mechanical data
STI18N65M2, STP18N65M2
Figure 21. TO-220 type A drawing
BW\SH$B5HYB7
12/15
DocID026870 Rev 2
STI18N65M2, STP18N65M2
Package mechanical data
Table 10. TO-220 type A mechanical data
mm
Dim.
Min.
Typ.
Max.
A
4.40
4.60
b
0.61
0.88
b1
1.14
1.70
c
0.48
0.70
D
15.25
15.75
D1
1.27
E
10
10.40
e
2.40
2.70
e1
4.95
5.15
F
1.23
1.32
H1
6.20
6.60
J1
2.40
2.72
L
13
14
L1
3.50
3.93
L20
16.40
L30
28.90
∅P
3.75
3.85
Q
2.65
2.95
DocID026870 Rev 2
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Revision history
5
STI18N65M2, STP18N65M2
Revision history
Table 11. Document revision history
14/15
Date
Revision
Changes
16-Dec-2014
1
First release.
09-Jan-2015
2
Text edits throughout document
Updated Figure 6: Gate charge vs gate-source voltage
DocID026870 Rev 2
STI18N65M2, STP18N65M2
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