STL8N80K5
N-channel 800 V, 0.80 Ω typ., 4.5 A Zener-protected SuperMESH™ 5
Power MOSFET in a PowerFLAT™ 5x6 VHV package
Datasheet
−
production data
1
2
3
4
PowerFLAT™ 5x6 VHV
Features
Order code
STL8N80K5
V
DS
800 V
R
DS(on)max.
0.95 Ω
• Outstanding R
DS(on)
*area
• Worldwide best FOM (figure of merit)
• Ultra low gate charge
• 100% avalanche tested
• Zener protected
I
D
4.5 A
Applications
•
Switching applications Figure 1. Internal schematic diagram
D(5, 6, 7, 8)
8 7 6 5
G(4)
Description
This N-channel Zener-protected Power MOSFET is designed using ST's revolutionary avalancherugged very high voltage SuperMESH™ 5 technology, based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance, and ultra-low gate charge for applications which require superior power density and high efficiency.
S(1, 2, 3)
1 2 3 4
Top View
AM15540v1
Order code
STL8N80K5
Table 1. Device summary
Marking
8N80K5 PowerFLAT™ 5x6 VHV
November 2013
This is information on a product in full production.
DocID024079 Rev 3
Package Packaging
Tape and reel
1/17 www.st.com
17
5
6
3
4
1
2
Contents
Contents
STL8N80K5
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17 DocID024079 Rev 3
STL8N80K5 Electrical ratings
Symbol
Table 2. Absolute maximum ratings
Parameter
V
GS
I
D
(1)
I
D
(1)
I
DM
(1),(2)
P
TOT
(1)
Gate-source voltage
Drain current (continuous) at T
Drain current (continuous) at T
Drain current (pulsed)
C
C
= 25 °C
= 100 °C
I
E
AR
(3)
AS
(4) dv/dt
(5) dv/dt
(6)
Total dissipation at T
C
= 25 °C
Avalanche current, repetitive or notrepetitive (pulse width limited by T j
max)
Single pulse avalanche energy
(starting T j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
T stg
T j
Storage temperature
Max. operating junction temperature
1.
The value is rated according to R thj-case and limited by package.
2.
Pulse width limited by safe operating area.
3.
Pulse width limited by T jmax
4.
Starting T j
=25 °C, I
D
=I
AR
, V
DD
=50 V
5.
I
SD
≤
4.5 A, di/dt
≤
100 A/µs, V
DS(peak)
≤
V
(BR)DSS
6.
V
DS
≤
640 V
Value
± 30
4.5
3
18
42
2
114
4.5
50
- 55 to 150
Table 3. Thermal data
Parameter Symbol
R thj-case
R thj-amb
(1)
Thermal resistance junction-case max
Thermal resistance junction-amb max
1.
When mounted on 1inch² FR-4 board, 2 oz Cu.
Value
3
59
Unit
°C/W
°C/W mJ
V/ns
V/ns
°C
°C
Unit
A
W
V
A
A
A
DocID024079 Rev 3 3/17
Electrical characteristics STL8N80K5
(T
C
= 25 °C unless otherwise specified)
Symbol Parameter
Table 4. On /off states
Test conditions
V
(BR)DSS
V
R
I
I
DSS
GSS
GS(th)
DS(on)
Drain-source breakdown voltage
(V
GS
= 0)
I
D
= 1 mA
Zero gate voltage drain current (V
GS
= 0)
V
DS
= 800 V
V
DS
= 800 V, T
C
=125 °C
Gate-body leakage current (V
DS
= 0)
V
GS
= ± 20 V
Gate threshold voltage V
DS
= V
GS
, I
D
= 100 µA
Static drain-source on- resistance
V
GS
= 10 V, I
D
= 3 A
Min.
Typ.
Max.
Unit
800
3
V
4
0.80
1
50
µA
µA
± 10 µA
5
0.95
V
Ω
Symbol Parameter
Table 5. Dynamic
Test conditions Min.
Typ.
Max.
Unit
C iss
C oss
C rss
Input capacitance
Output capacitance V
DS
= 100 V, f = 1 MHz,
V
GS
= 0
-
450
50 -
pF pF
C
C o(tr)
(1) o(er)
(2)
R
G
Reverse transfer capacitance
Equivalent capacitance time related
Equivalent capacitance energy related
Intrinsic gate resistance
V
DS
= 0 to 640 V, V f = 1 MHz, I
D
=0
GS
= 0
-
-
-
1
57
24
6 -
-
-
pF pF pF
Ω
Q g
Q gs
Q gd
Total gate charge
Gate-source charge
Gate-drain charge
V
DD
V
GS
= 640 V, I
D
= 10 V
(see
Figure 16 )
= 6 A,
-
-
16.5
3.2
11 -
-
nC nC nC
1. C oss eq.
time related is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS
increases from 0 to 80% V
DSS
2. C oss eq.
energy related is defined as a constant equivalent capacitance giving the same stored energy as C oss
when V
DS
increases from 0 to 80% V
DSS
4/17 DocID024079 Rev 3
STL8N80K5 Electrical characteristics
Symbol t d(on) t r t d(off) t f
Parameter
Rise time
Turn-off delay time
Fall time
Table 6. Switching times
Test conditions
V
DD
= 400 V, I
D
= 3 A,
R
G
= 4.7 W, V
GS
= 10 V
(see Figure 15
),
(see Figure 20
)
Min.
Typ.
Max Unit
-
-
-
-
12
14
32
20
-
-
-
ns ns ns ns
Symbol Parameter
Table 7. Source drain diode
Test conditions
I
SD
I
SDM
V
SD
(1) t rr
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
I
SD
= 6 A, V
GS
= 0
Q rr
I
RRM t
Q rr rr
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
I
SD
V
= 6 A, di/dt = 100 A/µs
DD
= 60 V (see
I
RRM
Reverse recovery current
1. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Figure 17
I
SD
= 6 A, di/dt = 100 A/µs
V
DD
= 60 V, T j
= 150 °C
(see
Figure 17 )
)
-
-
-
-
-
-
-
-
-
Min.
Typ.
Max.
Unit
4.5
18
1.5
300
3
20
415
3.8
18
A
A
V ns
µC
A ns
µC
A
Table 8. Gate-source Zener diode
Parameter Test conditions Symbol
V
(BR)GSO
Gate-source breakdown voltage I
GS
= ± 1mA, I
D
=0
Min Typ.
Max Unit
30 V
The built-in back-to-back Zener diodes have been specifically designed to enhance not only the device's ESD capability, but also to make them capable of safely absorbing any voltage transients that may occasionally be applied from gate to source. In this respect, the Zener voltage is appropriate to achieve efficient and cost-effective protection of device integrity.
The integrated Zener diodes thus eliminate the need for external components.
DocID024079 Rev 3 5/17
Electrical characteristics STL8N80K5
I
D
(A)
Figure 2. Safe operating area
AM15762v1
10
1 y max R
Operation in this ar
Limit ed b ea is
DS(on)
0.1
10µs
100µs
1ms
10ms
K
Figure 3. Thermal impedance
ZthPowerFlat_5x6_27
δ
=0.5
10
-1
0.2
0.05
0.02
0.01
0.1
pcb
10
-2
Single pulse
Tj=150°C
Tc=25°C
Single pulse
0.01
0.1
1 10 100 V
DS
(V)
Figure 4. Output characteristics
AM15633v1
I
D
(A)
V
GS
=10, 11V
12
9V
10
10
-3
10
-5
10
-4
10
-3 10
-2
10
-1
10
0
10
1 t p
(s)
Figure 5. Transfer characteristics
AM15634v1
I
D
(A)
12
V
DS
=20V
10
8
6
4
2
0
0
8V
7V
8
6
4
2
0
5 4 8 12 16
6V
V
DS
(V) 6 7 8 9 10 V
GS
(V)
Figure 6. Gate charge vs gate-source voltage
V
GS
(V)
12
V
DS V
DD
=640V
I
D
=6A
AM15635v1
V
DS
(V)
600
Figure 7. Static drain-source on-resistance
AM15636v1
R
DS(on)
(
Ω
)
V
GS
=10V
1.6
10 500
1.2
8 400
6 300
0.8
200 4
2
0
0 4 8 12 16
100
0
Q g
(nC)
0.4
0
1 2 3 4 5 6 I
D
(A)
6/17 DocID024079 Rev 3
STL8N80K5 Electrical characteristics
Figure 8. Capacitance variations
AM15637v1
C
(pF)
Figure 9. Output capacitance stored energy
E oss
(µJ)
AM15638v1
1000 6
Ciss
100 4
Coss
10
Crss
1
0.1
1 10 100 V
DS
(V)
Figure 10. Normalized gate threshold voltage vs. temperature
AM15639v1 V
GS(th)
(norm)
I
D
=100µA
V
DS
=V
GS
1
2
0
0 200 400 600 V
DS
(V)
Figure 11. Normalized on-resistance vs. temperature
AM15640v1
R
DS(on)
(norm)
2.4
V
GS
=10V
I
D
=3 A
2
0.8
1.6
1.2
0.6
0.8
0.4
-50 0 50 100 T
J
(°C)
0.4
-50 0 50 100 T
J
(°C)
Figure 12. Drain-source diode forward characteristics
AM15641v1
V
SD
(V)
T
J
=-50°C
Figure 13. Normalized V
DS
vs. temperature
V
DS
(norm)
AM15642v1
1.1
0.9
I
D
= 1mA
1.06
T
J
=25°C
0.8
1.02
0.7
0.98
T
J
=150°C
0.6
0.94
0.5
1 2 3 4 5 I
SD
(A)
0.9
-50 0 50 100 T
J
(°C)
DocID024079 Rev 3 7/17
Electrical characteristics
Figure 14. Maximum avalanche energy vs. starting T
J
AM15643v1
E
AS
(mJ)
V
DD
=50V
I
D
=2A
100
80
60
40
20
0
0 40 80 120 T
J
(°C)
STL8N80K5
8/17 DocID024079 Rev 3
STL8N80K5
3 Test circuits
Test circuits
Figure 15. Switching times test circuit for resistive load
Figure 16. Gate charge test circuit
V
DD
12V
47k
Ω
100nF
1k Ω
V
GS
V
D
R
G
R
L
D.U.T.
2200
μ
F
3.3
μ
F
V
DD
V i
=20V=V
GMAX
2200
μ F
I
G
=CONST
2.7k
Ω
100 Ω
D.U.T.
V
G
P
W
AM01468v1
Figure 17. Test circuit for inductive load switching and diode recovery times
47k
Ω
P
W
1k
Ω
AM01469v1
Figure 18. Unclamped inductive load test circuit
25 Ω
G
D
A
D.U.T.
S
B
R
G
A
FAST
DIODE
A
B
B
G
D
S
L=100 μ H
3.3
μ F
1000
μ F
V
DD
V i
AM01470v1
Figure 19. Unclamped inductive waveform
V
(BR)DSS
V
D
V
D
I
D
L
2200
μ F
3.3
μ F
V
DD
D.U.T.
P w
AM01471v1
Figure 20. Switching time waveform t on td on t r t off td off t f
I
DM
90%
90%
10%
I
D 0
10% V
DS
V
DD
V
DD
90%
V
GS
AM01472v1
0
10%
AM01473v1
DocID024079 Rev 3 9/17
Package mechanical data
4 Package mechanical data
STL8N80K5
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
10/17 DocID024079 Rev 3
STL8N80K5 Package mechanical data
Table 9. PowerFLAT™ 5x6 VHV mechanical data mm.
DIM min.
typ.
A 0.80
A1 0.02
A2 0.25
b 0.30
D 5.00
E 5.95
D2 4.30
5.20
6.15
4.40
E2 2.40
2.50
e 1.27
L 0.50
0.55
K 2.60
2.70
aaa 0.15
bbb 0.15
ccc 0.10
eee 0.10
max.
1.00
0.05
0.50
5.40
6.35
4.50
2.60
0.60
2.80
DocID024079 Rev 3 11/17
Package mechanical data STL8N80K5
Figure 21. PowerFLAT™ 5x6 VHV
Bottom view
Side view
12/17 DocID024079 Rev 3
Top view
8368144_REV_B
STL8N80K5 Package mechanical data
Figure 22. PowerFLAT™ 5x6 VHV (dimensions are in mm)
8368144_REV_B_footprint
DocID024079 Rev 3 13/17
Packaging mechanical data
5 Packaging mechanical data
Figure 23. PowerFLAT™ 5x6 tape
T
(0.30 ±0.05)
Do
Ø1.55±0.05
D1
Ø1.5 MIN.
Y
P 2
2.0±0.1 (I)
REF 0.20
P 0
4.0±0.1 (II)
STL8N80K5
E 1
1.75±0.1
REF
.R0.50
Y
P1(8.00±0.1) Ao(6.30±0.1)
SECTION Y-Y
Ko (1.20±0.1)
(I)
(II)
Measured from centerline of sprocket hole to centerline of pocket.
Cumulative tolerance of 10 sprocket holes is ± 0.20 .
(III) Measured from centerline of sprocket hole to centerline of pocket.
Base and bulk quantity 3000 pcs
All dimensions are in millimeters
8234350_Tape_rev_C
Figure 24. PowerFLAT™ 5x6 package orientation in carrier tape.
Pin 1 identification
14/17 DocID024079 Rev 3
STL8N80K5
PART NO.
PS
06
2.50
Packaging mechanical data
Figure 25. PowerFLAT™ 5x6 reel
R0.60
W3
11.9/15.4
1.90
2.50
W2
18.4 (max)
R25.00
4.00
77
128
ØA
ØN
178(±2.0)
W1
12.4 (+2/-0)
ESD LOGO
A
330 (+0/-4.0)
Ø21.2
R1.10
13.00
CORE DETAIL
All dimensions are in millimeters
8234350_Reel_rev_C
DocID024079 Rev 3 15/17
Revision history STL8N80K5
Date
18-Dec-2012
22-Apr-2013
19-Nov-2013
Revision
Table 10. Document revision history
Changes
1
2
3
First release.
– Deleted: V
DS
, drain current (continuous) at T amb
= 25 °C and
T amb
= 100 °C, total dissipation at T amb
= 25 °C in Table 2
– Modified: P
TOT
, I
AR
and E
AS
values in Table 2
– Added: MOSFET dv/dt ruggedness parameter and
note 6 in
Table 2
– Modified: values in
Table 3 , R
DS(on)
typ in
Table 4
, the entire typical values in
Table 5
,
6 and 7
– Inserted:
Section 2.1: Electrical characteristics (curves)
– Modified:
Figure 3 ,
15 , 16
,
17 and 18
– Minor text changes
16/17 DocID024079 Rev 3
STL8N80K5
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DocID024079 Rev 3 17/17
