STMicroelectronics TSX7191A Datasheet
Iklan
Iklan
TSX7191, TSX7191A
Low-power, precision, rail-to-rail, 9.0 MHz, 16 V operational amplifier
Datasheet - production data
Features
Low input offset voltage: 200 µV max.
Rail-to-rail input and output
Low current consumption: 850 µA max.
Gain bandwidth product: 9 MHz
Low supply voltage: 2.7 - 16 V
Stable when used with Gain ≥ 10
Low input bias current: 50 pA max.
High ESD tolerance: 4 kV HBM
Extended temp. range: -40 °C to +125 °C
Automotive qualification
Related products
See the TSX711 for lower speeds with similar precision
See the TSX561 for low-power features
See the TSX631 for micro-power features
See the TSX921 for higher speeds
Applications
Battery-powered instrumentation
Instrumentation amplifier
Active filtering
High-impedance sensor interface
Current sensing (high and low side)
Description
The TSX7191, TSX7191A single, operational amplifier (op amp) offers high precision functioning with low input offset voltage down to a maximum of 200 µV at 25 °C. In addition, its railto-rail input and output functionality allows this product to be used on full range input and output without limitation. This is particularly useful for a low-voltage supply such as 2.7 V that the
TSX7191, TSX7191A is able to operate with.
Thus, the TSX7191, TSX7191A has the great advantage of offering a large span of supply voltages, ranging from 2.7 V to 16 V. It can be used in multiple applications with a unique reference.
Low input bias current performance makes the
TSX7191, TSX7191A perfect when used for signal conditioning in sensor interface applications. In addition, low-side and high-side current measurements can be easily made thanks to rail-to-rail functionality. The TSX7191,
TSX7191A is a decompensated amplifier and must be used with a gain greater than 10 to ensure stability.
High ESD tolerance (4 kV HBM) and a wide temperature range are also good arguments to use the TSX7191, TSX7191A in the automotive market segment.
March 2017 DocID026747 Rev 3
This is information on a product in full production.
1/25 www.st.com
Contents TSX7191, TSX7191A
Contents
1 Package pin connections ................................................................ 3
2 Absolute maximum ratings and operating conditions ................. 4
3 Electrical characteristics ................................................................ 5
4 Application information ................................................................ 16
Operating voltages .......................................................................... 16
Input pin voltage ranges .................................................................. 16
Rail-to-rail output ............................................................................. 16
Input offset voltage drift over temperature ....................................... 17
Long term input offset voltage drift .................................................. 17
High values of input differential voltage ........................................... 18
Capacitive load ................................................................................ 19
PCB layout recommendations ......................................................... 20
Optimized application recommendation .......................................... 20
5 Package information ..................................................................... 21
SOT23-5 package information ........................................................ 22
6 Ordering information ..................................................................... 23
7 Revision history ............................................................................ 24
2/25 DocID026747 Rev 3
TSX7191, TSX7191A
1 Package pin connections
Figure 1: Pin connections (top view)
Package pin connections
DocID026747 Rev 3 3/25
Absolute maximum ratings and operating conditions
2
TSX7191, TSX7191A
Absolute maximum ratings and operating conditions
Symbol
V
CC
V id
Table 1: Absolute maximum ratings (AMR)
Parameter
Differential input voltage (2)
Value
18
±V
CC
Unit
V mV
V in
I in
T stg
R thja
T j
ESD
Input voltage
Storage temperature
Thermal resistance junction to ambient (4) (5)
Maximum junction temperature
Latch-up immunity
V
CC-
- 0.2 to V
CC+
+ 0.2
10
-65 to +150
250
150
4000
100
1500
200
V mA
Notes:
(1)
All voltage values, except the differential voltage are with respect to the network ground terminal.
(2)
for the precautions to follow when using the TSX711 with a high differential input voltage.
(3)
Input current must be limited by a resistor in series with the inputs.
(4)
R th
are typical values.
(5)
Short-circuits can cause excessive heating and destructive dissipation.
(6)
According to JEDEC standard JESD22-A114F.
(7)
According to JEDEC standard JESD22-A115A.
(8)
According to ANSI/ESD STM5.3.1
Symbol
Table 2: Operating conditions
Parameter Value Unit
V
CC
V icm
T oper
Supply voltage
Common mode input voltage range
Operating free air temperature range
2.7 to 16
V
CC-
- 0.1 to V
CC+
+ 0.1
-40 to +125
V
°C
V mA
°C
°C/W
°C
4/25 DocID026747 Rev 3
TSX7191, TSX7191A Electrical characteristics
3
Symbol
V io
Electrical characteristics
Table 3: Electrical characteristics at V
CC+
= +4 V with V
CC-
= 0 V, V icm
= V
CC
/2, T amb
= 25 ° C, and
R
L
> 10 kΩ connected to V
CC
/2 (unless otherwise specified)
Parameter Conditions Min. Typ. Max. Unit
Input offset voltage
ΔV io
/ΔT Input offset voltage drift (1)
TSX7191, V icm
= V
CC
/2
T min
< T op
< +85 °C
T min
< T op
< +125 °C
TSX7191A, V icm
= V
CC
/2
T min
< T op
< +85 °C
T min
< T op
< +125 °C
200
365
450
100
265
350
2.5
μV
µV/°C
ΔV io
Long term input offset
T = 25 °C 1 nV
--------------------------month
I ib
I io
R
IN
C
IN
Input resistance
Input capacitance
CMRR
Common mode rejection ratio 20 log (ΔV ic
/ΔV io
)
A vd
Large signal voltage gain
V
OH
High level output voltage
(voltage drop from V
CC+
)
V
OL
Low level output voltage
V out
= V
CC
/2
T min
< T op
< T max
V out
= V
CC
/2
T min
< T op
< T max
V icm
= -0.1 to 4.1 V, V out
= V
CC
/2
T min
< T op
< T max
V icm
= -0.1 to 2 V, V out
= V
CC
/2
T min
< T op
< T max
R
L
= 2 kΩ, V out
= 0.3 to 3.7 V
T min
< T op
< T max
R
L
= 10 kΩ, V out
= 0.2 to 3.8 V
T min
< T op
< T max
R
L
= 2 kΩ to V
CC
/2
T min
< T op
< T max
R
L
= 10 kΩ tο V
CC
/2
T min
< T op
< T max
R
L
= 2 kΩ tο V
CC
/2
T min
< T op
< T max
R
L
= 10 kΩ tο V
CC
/2
T min
< T op
< T max
28
6
23
5
122
136
140
1
1
1
12.5
102
100
94
110
96
110
96
84
83
50
60
15
20
50
60
15
20
50
200
50
200 pA
TΩ pF dB mV
DocID026747 Rev 3 5/25
Electrical characteristics
Symbol
I
I out
CC e n
GBP ɸm
SRn
SRp
I
I sink source
Parameter
Supply current per amplifier
Gain bandwidth product
Phase margin
Negative slew rate
Positive slew rate
Equivalent input noise voltage
Conditions
V out
= V
CC
T min
< T op
< T max
V out
= 0 V
T min
< T op
< T max
No load, V out
= V
CC
/2
T min
< T op
< T max
R
L
= 10 kΩ, C
L
= 100 pF
Gain = 10, R
L
= 10 kΩ,
C
L
= 100 pF
Av = 10, V out
= 3 V
PP
, 10 % to
90 %
T min
< T op
< T max
Av = 10, V out
= 3 V
PP
, 10 % to
90 %
T min
< T op
< T max f = 1 kHz f = 10 kHz
TSX7191, TSX7191A
Min. Typ. Max.
35 45
20
35
20
5
45
570
7.7
800
900
42
Unit mA
μA
MHz
Degrees
1.3 2.3
1.0
1.5 2.5
V/μs
1.1
22
Hz
19
THD+N
Total harmonic distortion + noise f =1 kHz, Av = 10, R
L
= 10 kΩ,
BW = 22 kHz, V out
= 3V
PP
0.003
Notes:
(1)
Maximum values are guaranteed by design.
(2)
Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and
%
6/25 DocID026747 Rev 3
TSX7191, TSX7191A Electrical characteristics
Table 4: Electrical characteristics at V
CC+
= +10 V with V
CC-
= 0 V, V icm
= V
CC
/2, T amb
= 25 °C, and
R
L
> 10 kΩ connected to V
CC
/2 (unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit
V io
Input offset voltage
ΔV io
/ΔT Input offset voltage drift (1)
TSX7191, V icm
= V
CC
/2
T min
< T op
< +85 °C
T min
< T op
< +125 °C
TSX7191A, V icm
= V
CC
/2
T min
< T op
< +85 °C
T min
< T op
< +125 °C
200
365
450
100
265
350
2.5
μV
μV/°C
ΔV io
Long term input offset
T = 25 °C 25 nV
--------------------------month
I ib
I io
R
IN
C
IN
Input resistance
Input capacitance
A vd
Large signal voltage gain
V
OL
Low level output voltage
I out
CMRR
Common mode rejection ratio 20 log (ΔV ic
/ΔV io
)
V
OH
High level output voltage
(voltage drop from V
CC+
)
I sink
I source
V out
= V
CC
/2
T min
< T op
< T max
V out
= V
CC
/2
T min
< T op
< T max
V icm
= -0.1 to 10.1 V, V out
= V
CC
/2
T min
< T op
< T max
V icm
= -0.1 to 8 V, V out
= V
CC
/2
T min
< T op
< T max
R
L
= 2 kΩ, V out
= 0.3 to 9.7 V
T min
< T op
< T max
R
L
= 10 kΩ, V out
= 0.2 to 9.8 V
T min
< T op
< T max
R
L
= 2 kΩ tο V
CC
/2
T min
< T op
< T max
R
L
= 10 kΩ tο V
CC
/2
T min
< T op
< T max
R
L
= 2 kΩ tο V
CC
/2
T min
< T op
< T max
R
L
= 10 kΩ tο V
CC
/2
T min
< T op
< T max
V out
= V
CC
T min
< T op
< T max
V out
= 0 V
T min
< T op
< T max
9
70
10
42
69
117
140
45
1
1
1
12.5
102
50
40
50
40
90
86
105
95
110
100
110
100
70
80
30
40
70
80
30
40
50
200
50
200 pA
TΩ pF dB mV mA
DocID026747 Rev 3 7/25
Electrical characteristics
Symbol
I
CC e n
GBP ɸm
SRn
SRp
Parameter
Supply current per amplifier
Gain bandwidth product
Phase margin
Negative slew rate
Positive slew rate
Equivalent input noise voltage
Conditions
No load, V out
= V
CC
/2
T min
< T op
< T max
R
L
= 10 kΩ, C
L
= 100 pF
G = 10, R
L
= 10 kΩ, C
L
= 100 pF
Av = 10, V out
= 8 V
PP
, 10 % to
90 %
T min
< T op
< T max
Av = 10, V out
= 8 V
PP
, 10 % to
90 %
T min
< T op
< T max f = 1 kHz f = 10 kHz
TSX7191, TSX7191A
Min. Typ. Max.
630 850
5 9
48
1000
1.3 2.3
1.0
1.5 2.5
1.1
22
Unit
μA
MHz
Degrees
V/μs
Hz
19
THD+N
Total harmonic distortion + noise f = 1 kHz, Av = 10, R
L
= 10 kΩ,
BW = 22 kHz, V out
= 9 V
PP
0.0001
Notes:
(1)
Maximum values are guaranteed by design.
(2)
Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and
%
8/25 DocID026747 Rev 3
TSX7191, TSX7191A Electrical characteristics
Table 5: Electrical characteristics at V
CC+
= +16 V with V
CC-
= 0 V, V icm
= V
CC
/2, T amb
= 25 °C, and
R
L
> 10 kΩ connected to V
CC
/2 (unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit
V io
Input offset voltage
ΔV io
/ΔT Input offset voltage drift (1)
TSX7191, V icm
= V
CC
/2
T min
< T op
< +85 °C
T min
< T op
< +125 °C
TSX7191A, V icm
= V
CC
/2
T min
< T op
< +85 °C
T min
< T op
< +125 °C
200
365
450
100
265
350
2.5
μV
μV/°C
ΔV io
Long term input offset
T = 25 °C 500 nV
--------------------------month
I ib
I io
R
IN
C
IN
Input resistance
Input capacitance
CMRR
Common mode rejection ratio 20 log (ΔV icm
/ΔV io
)
SVRR
Supply voltage rejection ratio 20 log (ΔV cc
/ΔV io
)
A vd
Large signal voltage gain
V
OH
High level output voltage
(voltage drop from V
CC+
)
V
OL
Low level output voltage
V out
= V
CC
/2
T min
< T op
< T max
V out
= V
CC
/2
T min
< T op
< T max
V icm
= -0.1 to 16.1 V, V out
= V
CC
/2
T min
< T op
< T max
V icm
= -0.1 to 14 V, V out
= V
CC
/2
T min
< T op
< T max
V cc
= 4 to 16 V
T min
< T op
< T max
R
L
= 2 kΩ, V out
= 0.3 to 15.7 V
T min
< T op
< T max
R
L
= 10 kΩ, V out
= 0.2 to 15.8 V
T min
< T op
< T max
R
L
= 2 kΩ
T min
< T op
< T max
R
L
= 10 kΩ
T min
< T op
< T max
R
L
= 2 kΩ
T min
< T op
< T max
R
L
= 10 kΩ
T min
< T op
< T max
116
131
146
149
1
1
1
12.5
113
100
16
70
15
94
90
110
96
100
90
110
100
110
100
50
200
50
200
130
150
40
50
130
150
40
50 pA
TΩ pF dB mV
DocID026747 Rev 3 9/25
Electrical characteristics
Symbol
I
I out
CC e n
GBP ɸm
SRn
SRp
I
I sink source
Parameter
Supply current per amplifier
Gain bandwidth product
Phase margin
Negative slew rate
Positive slew rate
Equivalent input noise voltage
Conditions
V out
= V
CC
T min
< T op
< T max
V out
= 0 V
T min
< T op
< T max
No load, V out
= V
CC
/2
T min
< T op
< T max
R
L
= 10 kΩ, C
L
= 100 pF
G = 10, R
L
= 10 kΩ, C
L
= 100 pF
Av = 10, V out
= 10 V
PP
, 10 % to
90 %
T min
< T op
< T max
Av = 10, V out
= 10 V
PP
, 10 % to
90 %
T min
< T op
< T max f = 1 kHz f = 10 kHz
TSX7191, TSX7191A
Min. Typ. Max.
50 71
45
50
45
5
68
660
8.5
51
900
1000
1.5 2.4
1.1
1.5 2.5
1.1
22
Unit mA
μA
MHz
Degrees
V/μs
Hz
19
THD+N
Total harmonic distortion +
Noise f = 1 kHz, Av = 10, R
L
= 10 kΩ,
BW = 22 kHz, V out
= 10 V
PP
0.0001
Notes:
(1)
Maximum values are guaranteed by design.
(2)
Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and
%
10/25 DocID026747 Rev 3
TSX7191, TSX7191A
Figure 2: Supply current vs. supply voltage
Electrical characteristics
Figure 3: Input offset voltage distribution at V
CC
= 16 V
Figure 4: Input offset voltage distribution at V
CC
= 4 V
Figure 6: Input offset voltage drift population
Figure 5: Input offset voltage vs. temperature at
V
CC
= 16 V
600
400
200
0
-200
-400
-600
-40 -20 0
Vio limit
Vcc=16V
Vicm=8V
20 40 60
Temperature (°C)
80 100 120
Figure 7: Input offset voltage vs. supply voltage at
V
ICM
= 0 V
DocID026747 Rev 3 11/25
Electrical characteristics
Figure 8: Input offset voltage vs. common mode voltage at V
CC
= 2.7 V
TSX7191, TSX7191A
Figure 9: Input offset voltage vs. common mode voltage at V
CC
= 16 V
Figure 10: Output current vs. output voltage at
V
CC
= 2.7 V
Figure 11: Output current vs. output voltage at
V
CC
= 16 V
Figure 12: Output low voltage vs. supply voltage Figure 13: Output high voltage (drop from V
CC+
) vs. supply voltage
12/25 DocID026747 Rev 3
TSX7191, TSX7191A
Figure 14: Output voltage vs. input voltage close to the rail at V
CC
= 16 V
Electrical characteristics
Figure 15: Slew rate vs. supply voltage
3.0
Vcc=16V
Gain=10
2.0
1.0
0.0
T=-40°C
-1.0
-2.0
-3.0
T=25°C
T=125°C
Vicm=Vcc/2
Vload=Vcc/2
Gain=10
Rl=10k Ω
Cl=100pF
Input voltage (V)
Supply Voltage (V)
Figure 16: Negative slew rate at V
CC
= 16 V
0
T=-40°C
2
T=25°C
T=125°C
Vcc=16V
Vicm=Vcc/2
Gain=11
Rl=10k Ω
Cl=100pF
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
4
Time (µs)
6 8
Figure 18: Response to a small input voltage step
Figure 17: Positive slew rate at V
CC
= 16 V
0
T=-40°C
2
T=25°C
4
Time (µs)
T=125°C
6
0.0
-0.2
Vcc=16V
Vicm=Vcc/2
Gain=11
Rl=10k Ω
Cl=100pF
-0.4
-0.6
-0.8
-1.0
8
1.0
0.8
0.6
0.4
0.2
Figure 19: Recovery behavior after a negative step on the input
0 2 4 6
Time (µs)
8
100
Vcc=16V
Vicm=8V
Rl=10k Ω
Cl=100pF
Gain=10
T=25°C
50
0
10
-50
12
-100
-10 0 10
Vin
Vcc=±8V
Vcc=±1.35V
0.20
Gain=101
Rl=10k Ω
Cl=100pF
T=25°C
0.16
0.12
0.08
0.04
30
0.00
40
-0.04
Time (µs)
20
DocID026747 Rev 3 13/25
Electrical characteristics
Figure 20: Recovery behavior after a positive step on the input
0.04
0.00
Vcc=±1.35V
-0.04
-0.08
Vcc=±8V
Vin
-0.12
Gain=101
Rl=10k Ω
Cl=100pF
T=25°C
30
-0.16
40
-0.20
-10 0 10
Time (µs)
20
Figure 22: Bode diagram at V
CC
= 16 V
TSX7191, TSX7191A
Figure 21: Bode diagram at V
CC
= 2.7 V
50
40
30
Gain
20
10
0
Phase
-10
-20
-30
-40
1k
Vcc=2.7V
Vicm=1.35V
Rl=10k Ω
Cl=100pF
Gain=101
10k
T=-40°C
T=25°C
T=125°C
100k
Frequency (Hz)
1M
300
240
180
120
60
0
-60
-120
-180
-240
10M
50
40
30
Gain
20
10
Phase
0
-10
-20
-30
-40
1k
Vcc=16V
Vicm=8V
Rl=10k Ω
Cl=100pF
Gain=101
10k
T=-40°C
100k
T=125°C
1M
Frequency (Hz)
T=25°C
300
240
180
120
60
0
-60
-120
-180
-240
10M
Figure 24: Output overshoot vs. capacitive load
100
75
Vcc=16V
Vicm=Vcc/2
Rl=10k Ω
Vin=10mVpp
Gain=10
T=25°C
50
Rf=91k Ω
Rf=9.1k
Ω
25
Unstable
Figure 23: Power supply rejection ratio (PSRR) vs. frequency
100
PSRR
+
80
60
40
20
0
10
Vcc=16V
Vicm=8V
Gain=10
Rl=10k Ω
Cl=100pF
Vosc=20mV
PP
T=25°C
100
PSRR
-
1k
Frequency (Hz)
10k 100k
Figure 25: Output impedance vs. frequency in closed loop configuration
10000
1000
Vicm=Vcc/2
Gain=1
Vosc=30mV
RMS
T=25°C
100
Vcc=16V
10
Vcc=2.7V
1
0
10 100
Cload (pF)
1000
0.1
1k 10k 100k
Frequency (Hz)
1M 10M
14/25 DocID026747 Rev 3
TSX7191, TSX7191A
Figure 26: THD + N vs. frequency
1
0.1
Vcc=16V
Vicm=8V
Gain=10
Vout=10Vpp
BW=80kHz
T=25°C
Rl=2k Ω
0.01
Rl=10k Ω
Rl=100k Ω
1E-3
100 1000
Frequency (Hz)
Figure 28: Noise vs. frequency
10000
Vcc=16V
Vicm=Vcc/2
T=25°C
10 100 1k
Frequency (Hz)
10k
Electrical characteristics
Figure 27: THD + N vs. output voltage
1
Rl=2k Ω
0.1
Rl=10k Ω
0.01
1E-3
Vcc=16V
Vicm=8V
Gain=10 f=1kHz
1E-4
0.01
BW=22kHz
T=25°C
0.1
1
Output Voltage (Vpp)
Rl=100k Ω
10
0
-2
-4
-6
0
Figure 29: 0.1 to 10Hz noise
6
4
Vcc=16V
Vicm=8V
T=25°C
2
2 4
Time (s)
6 8 10
DocID026747 Rev 3 15/25
Application information
4
4.1
4.2
Application information
TSX7191, TSX7191A
Operating voltages
The TSX7191, TSX7191A device can operate from 2.7 to 16 V. The parameters are fully specified for 4 V, 10 V, and 16 V power supplies. However, the parameters are very stable in the full V
CC
range. Additionally, the main specifications are guaranteed in extended temperature ranges from -40 to +125 °C.
Input pin voltage ranges
The TSX7191, TSX7191A device has internal ESD diode protection on the inputs. These diodes are connected between the input and each supply rail to protect the input MOSFETs from electrical discharge.
If the input pin voltage exceeds the power supply by 0.5 V, the ESD diodes become conductive and excessive current can flow through them. Without limitation this over current can damage the device.
In this case, it is important to limit the current to 10 mA, by adding resistance on the input
pin, as described in Figure 30 .
Figure 30: Input current limitation
9R
2
4.3
4.4
Vcc
R
2
R
1
Vin
Rail-to-rail input
The TSX7191, TSX7191A device has a rail-to-rail input, and the input common mode range is extended from V
CC-
- 0.1 V to V
CC+
+ 0.1 V.
Rail-to-rail output
The operational amplifier output levels can go close to the rails: to a maximum of 30 mV above and below the rail when connected to a 10 kΩ resistive load to V
CC
/2.
16/25 DocID026747 Rev 3
TSX7191, TSX7191A
4.5
4.6
Application information
Input offset voltage drift over temperature
The maximum input voltage drift variation over temperature is defined as the offset variation related to the offset value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum input voltage drift over temperature enables the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift over temperature is computed using Equation 1 .
Equation 1
∆V io
∆T
= ma x
V io
T – V io
25
T – 25 °C
°C
Where T = -40 °C and 125 °C.
The TSX7191, TSX7191A datasheet maximum value is guaranteed by measurements on a representative sample size ensuring a C pk
(process capability index) greater than 1.3.
Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
Voltage acceleration, by changing the applied voltage
Temperature acceleration, by changing the die temperature (below the maximum junction temperature allowed by the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using
Equation 2
S
– V
U A
FV
= e
Where:
A
FV
is the voltage acceleration factor
β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1)
V
S
is the stress voltage used for the accelerated test
V
U
is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined in
Equation 3
A
FT
= e
E a
.
1
T
U
–
1
T
S
Where:
A
FT
is the temperature acceleration factor
E a
is the activation energy of the technology based on the failure rate
DocID026747 Rev 3 17/25
Application information k is the Boltzmann constant (8.6173 x 10 -5 eV.K
-1 )
TSX7191, TSX7191A
T
U
is the temperature of the die when V
U
is used (K)
T
S
is the temperature of the die under temperature stress (K)
The final acceleration factor, A
F
, is the multiplication of the voltage acceleration factor and
the temperature acceleration factor ( Equation 4 ).
Equation 4
A
F
= A
FT
× A
FV
A
F is calculated using the temperature and voltage defined in the mission profile of the product. The A
F
value can then be used in Equation 5 to calculate the number of months of
use equivalent to 1000 hours of reliable stress duration.
Equation 5
Months = A
F
× 1000 h × 12 months / 24 h × 365.25 days
To evaluate the op amp reliability, a follower stress condition is used where V
CC
is defined as a function of the maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules).
The V io
drift (in µV) of the product after 1000 h of stress is tracked with parameters at
different measurement conditions (see Equation 6 ).
Equation 6
V
CC
= maxV op with V icm
= V
CC
2
The long term drift parameter (ΔV io
), estimating the reliability performance of the product, is obtained using the ratio of the V io
(input offset voltage value) drift over the square root of
the calculated number of months ( Equation 7 ).
Equation 7
∆V io
=
V io dr ift month s
Where V io
drift is the measured drift value in the specified test conditions after 1000 h stress duration.
4.7 High values of input differential voltage
In a closed loop configuration, which represents the typical use of an op amp, the input differential voltage is low (close to V io
). However, some specific conditions can lead to higher input differential values, such as: operation in an output saturation state operation at speeds higher than the device bandwidth, with output voltage dynamics limited by slew rate. use of the amplifier in a comparator configuration, hence in open loop
Use of the TSX7191, TSX7191A in comparator configuration, especially combined with high temperature and long duration can create a permanent drift of V io
.
18/25 DocID026747 Rev 3
TSX7191, TSX7191A
4.8
Application information
Capacitive load
Driving large capacitive loads can cause stability problems. Increasing the load capacitance produces gain peaking in the frequency response, with overshoot and ringing in the step response. It is usually considered that with a gain peaking higher than 2.3 dB an op amp might become unstable.
Generally, the unity gain configuration is the worst case for stability and the ability to drive large capacitive loads.
Figure 31: Stability criteria with a serial resistor at different supply voltages
Figure 32: Test configuration for Riso
11k
Ω
Vin
100k Ω
Vcc+
Vcc-
Riso
Cl
Vout
10k
Ω
DocID026747 Rev 3 19/25
Application information TSX7191, TSX7191A
4.9 PCB layout recommendations
Particular attention must be paid to the layout of the PCB, tracks connected to the amplifier, load, and power supply. The power and ground traces are critical as they must provide adequate energy and grounding for all circuits. The best practice is to use short and wide
PCB traces to minimize voltage drops and parasitic inductance.
In addition, to minimize parasitic impedance over the entire surface, a multi-via technique that connects the bottom and top layer ground planes together in many locations is often used.
The copper traces that connect the output pins to the load and supply pins should be as wide as possible to minimize trace resistance.
4.10 Optimized application recommendation
It is recommended to place a 22 nF capacitor as close as possible to the supply pin. A good decoupling will help to reduce electromagnetic interference impact.
20/25 DocID026747 Rev 3
TSX7191, TSX7191A
5 Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
DocID026747 Rev 3 21/25
Package information
5.1 SOT23-5 package information
Figure 33: SOT23-5 package outline
TSX7191, TSX7191A
22/25 e
E
F
L
K
A
A1
A2
B
C
D
D1
Ref.
Min.
0.90
0.90
0.35
0.09
2.80
2.60
1.50
0.10
0 degrees
1.05
0.40
0.15
2.90
1.90
0.95
2.80
1.60
0.35
Table 6: SOT23-5 mechanical data
Dimensions
Millimeters
Typ.
1.20
Min.
0.035
Max.
1.45
0.15
1.30
0.50
0.20
3.00
0.035
0.014
0.004
0.110
3.00
1.75
0.60
10 degrees
0.102
0.059
0.004
0 degrees
Inches
Typ.
0.047
0.041
0.016
0.006
0.114
0.075
0.037
0.110
0.063
0.014
Max.
0.057
0.006
0.051
0.020
0.008
0.118
0.118
0.069
0.024
10 degrees
DocID026747 Rev 3
TSX7191, TSX7191A Ordering information
6 Ordering information
Table 7: Order codes
Order code
Temperature range
Package
TSX7191ILT
TSX7191AILT
-40 to +125 °C
SΟΤ23-5
Packaging
Tape and reel
Marking
K34
K196
K199
K200
Notes:
(1)
Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001
& Q 002 or equivalent are on-going.
DocID026747 Rev 3 23/25
Revision history
7
TSX7191, TSX7191A
Revision history
Date
Table 8: Document revision history
Revision Changes
29-Sep-2014
06-Jan-2015
17-Mar-2017
1
2
3
Initial release
Features: updated "stable when used with gain" feature.
Applications: removed "DAC buffer"
Electrical characteristics: replaced Figure 14
Added part number TSX7191A
24/25 DocID026747 Rev 3
TSX7191, TSX7191A
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics
– All rights reserved
DocID026747 Rev 3 25/25
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