STMicroelectronics TSX920 Datasheet
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TSX920, TSX921, TSX922,
TSX923
10 MHz rail-to-rail CMOS 16 V operational amplifiers
Datasheet - production data
Features
Rail-to-rail input and output
Wide supply voltage: 4 V - 16 V
Gain bandwidth product: 10 MHz typ at 16 V
Low power consumption: 2.8 mA typ per amplifier at 16 V
Unity gain stable
Low input bias current: 10 pA typ
High tolerance to ESD: 4 kV HBM
Extended temperature range:
-40 °C to 125 °C
Automotive qualification
Related products
See the TSX5 series for low-power features
See the TSX6 series for micro-power features
See the TSX929 series for higher speeds
See the TSV9 series for lower voltages
Applications
Communications
Process control
Test equipment
Description
The TSX92x single and dual operational amplifiers (op amps) offer excellent AC characteristics such as 10 MHz gain bandwidth,
17 V/ms slew rate, and 0.0003 % THD+N. These features make the TSX92x family particularly well-adapted for communications, I/V amplifiers for ADCs, and active filtering applications.
Their rail-to-rail input and output capability, while operating on a wide supply voltage range of 4 V to 16 V, allows these devices to be used in a wide range of applications. Automotive qualification is available as these devices can be used in this market segment.
Shutdown mode is available on the single
(TSX920) and dual (TSX923) versions enabling an important current consumption reduction while this function is active.
The TSX92x family is available in SMD packages featuring a high level of integration. The DFN8 package, used in the TSX922, with a typical size of 2x2 mm and a maximum height of 0.8 mm offers even greater package size reduction.
Op-amp version
Table 1: Device summary
With shutdown mode
Without shutdown mode
Single
Dual
TSX920
TSX923
TSX921
TSX922
January 2016 DocID024310 Rev 4
This is information on a product in full production.
1/32 www.st.com
Contents TSX920, TSX921, TSX922, TSX923
Contents
1 Package pin connections ................................................................ 3
2 Absolute maximum ratings and operating conditions ................. 4
3 Electrical characteristics ................................................................ 5
4 Electrical characteristic curves .................................................... 11
5 Application information ................................................................ 17
Operating voltages .......................................................................... 17
Input pin voltage range .................................................................... 17
Input offset voltage drift over temperature ....................................... 18
Long term input offset voltage drift .................................................. 18
Capacitive load ................................................................................ 20
High-side current sensing ............................................................... 21
High-speed photodiode ................................................................... 22
6 Package information ..................................................................... 23
SOT23-5 package information ........................................................ 24
SOT23-6 package information ........................................................ 25
MiniSO8 package information ......................................................... 26
SO8 package information ................................................................ 27
DFN8 2x2 package information ....................................................... 28
MiniSO10 package information ....................................................... 29
7 Ordering information ..................................................................... 30
8 Revision history ............................................................................ 31
2/32 DocID024310 Rev 4
TSX920, TSX921, TSX922, TSX923
1 Package pin connections
Figure 1: Pin connections (top view)
Package pin connections
DocID024310 Rev 4 3/32
Absolute maximum ratings and operating conditions
2
TSX920, TSX921, TSX922, TSX923
Absolute maximum ratings and operating conditions
Symbol
V
CC
V id
V in
I in
Input voltage
Table 2: Absolute maximum ratings (AMR)
Parameter
(V
CC-
Value
18
±V
CC
)- 0.2 to (V
10
CC+
) + 0.2
T stg
T j
Storage temperature
Maximum junction temperature
R thja
Thermal resistance junction to
SOT23-5
SOT23-6
MiniSO8
SO8
DFN8 2x2
-65 to 150
150
250
240
190
125
57
ESD
Latch-up immunity
MiniSO10 113
4000
100
1500
200
Notes:
(1)
All voltage values, except the differential voltage are with respect to network ground terminal.
(2)
The differential voltage is the non-inverting input terminal with respect to the inverting input terminal.
(3)
Input current must be limited by a resistor in series with the inputs.
(4)
R th
are typical values.
(5)
Short-circuits can cause excessive heating and destructive dissipation.
(6)
According to JEDEC standard JESD22-A114F
(7)
According to JEDEC standard JESD22-A115A
(8)
According to ANSI/ESD STM5.3.1
Symbol
Table 3: Operating conditions
Parameter Value
Unit
V mV
V mA
°C
°C/W
V mA
Unit
V
CC
V icm
T oper
Supply voltage
Common mode input voltage range
Operating free air temperature range
4 to 16
(V
CC-
) - 0.1 to (V
CC+
) + 0.1
-40 to 125
V
°C
4/32 DocID024310 Rev 4
TSX920, TSX921, TSX922, TSX923 Electrical characteristics
3
Symbol
V io
Electrical characteristics
Table 4: Electrical characteristics at VCC+ = 4.5 V with VCC- = 0 V, Vicm = VCC/2,
Tamb = 25 °C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified)
Parameter Conditions Min. Typ. Max. Unit
Input offset voltage
∆V io
/∆T Input offset voltage drift
∆V io
I ib
I io
R
IN
C
IN
CMRR
A vd
V
OH
V
OL
Long-term input offset
Input bias current
Input offset current
Input resistance
Input capacitance
Common mode rejection ratio 20 log (ΔV ic
/ΔV io
)
Large signal voltage gain
High level output voltage
Low level output voltage
V icm
= 2 V (all order codes except
TSX922IYST and TSX922IYDT)
T min
< T op
< T max
V icm
= 2 V (TSX922IYST,
TSX922IYDT order codes only)
T min
< T op
< T max
All order codes except TSX922IYST and TSX922IYDT
TSX922IYST and TSX922IYDT order codes only
TSX920/TSX921
TSX922/TSX923
V out
= V
CC
/2
T min
< T op
< T max
V out
= V
CC
/2
T min
< T op
< T max
V icm
= -0.1 V to 2 V, V
OUT
= V
CC
/2
T min
< T op
< T max
V icm
= -0.1 V to 4.6 V, V
OUT
= V
CC
/2
T min
< T op
< T max
R
L
= 2 kΩ, V out
= 0.3 V to 4.2 V
T min
< T op
< T max
R
L
= 10 kΩ, V out
= 0.2 V to 4.3 V
T min
< T op
< T max
R
L
= 2 kΩ tο V
CC
/2
T min
< T op
< T max
R
L
= 10 kΩ tο V
CC
/2
T min
< T op
< T max
R
L
= 2 kΩ tο V
CC
/2
T min
< T op
< T max
R
L
= 10 kΩ tο V
CC
/2
T min
< T op
< T max
2
2
6
9
10
61
10
1
8
82
59
59 72
57
100 108
90
100 112
90
50
10
42
9
4
5
5
6.5
10
15
100
200
100
200 mV
μV/°C nV/√month pA
TΩ pF dB mV from
V
CC
+ mV
80
100
16
20
80
100
16
20
DocID024310 Rev 4 5/32
Electrical characteristics
Symbol Parameter Conditions
TSX920, TSX921, TSX922, TSX923
Min. Typ. Max. Unit
I out
I
CC
I sink
I source
Supply current
(per amplifier)
V out
= 4.5 V
T min
< T op
< T max
V out
= 0 V
T min
< T op
< T max
No load, V out
= V
CC
/2
T min
< T op
< T max
R
L
= 10 kΩ, C
L
= 20 pF, G = 20 dB
16
13
16
13
21
21
2.9 3.4 mA
GBP Gain bandwidth product
F
U ɸm
Unity gain frequency
Phase margin
G m
Gain margin
9
9.3
60
3.5
MHz
R
L
= 10 kΩ, C
L
= 20 pF
6.7
Degrees dB
SR+ Positive slew rate
Av = 1, V out
= 0.5 to 4.0 V, measured between 10 % to 90 %
14.7
SR- Negative slew rate
Av = 1, V out
= 4.0 to 0.5 V, measured between 90 % to 10 % f = 10 kHz e n
Equivalent input noise voltage
Amplifier turn-on time
Amplifier turn-off time f = 100 kHz
∫e n
Low-frequency peak-topeak input noise
Bandwidth: f = 0.1 to 10 Hz
THD+N
Total harmonic distortion
+ noise f = 1 kHz, Av = 1, R
L
= 10 kΩ,
V out
= 2 V rms
Shutdown characteristics (TSX920 and TSX923 only)
I
CC_shdn
Supply current in shutdown mode
(per amplifier)
SHDN
= V
CC-
T min
< T op
< T max t on t off
17.2
17.9
12.9
8.1
0.002
7 15
20
V/μs nV√Hz
µV pp
%
µΑ
9
0.7
µs
Notes:
(1)
Typical value is based on the Vio drift observed after 1000 h at 125 °C extrapolated to 25 °C using the Arrhenius law and
(2)
When used in comparator mode, with high differential input voltage, during a long period of time with V
CC
close to 16 V and
V icm
>V
CC
/2, Vio can experience a permanent drift of a few mV drift. This phenomenon is notably worse at low temperatures.
6/32 DocID024310 Rev 4
TSX920, TSX921, TSX922, TSX923 Electrical characteristics
Table 5: Electrical characteristics at VCC+ = 10 V with VCC- = 0 V, Vicm = VCC/2,
Tamb = 25 °C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit
V io
∆V io
I ib
I io
R
IN
C
IN
CMRR
Input offset voltage
∆V io
/∆T Input offset voltage drift
Long-term input offset
Input bias current
Input offset current
Input resistance
Input capacitance
Common mode rejection ratio 20 log (ΔV ic
/ΔV io
)
V icm
= 2 V (all order codes except
TSX922IYST and TSX922IYDT)
T min
< T op
< T max
V icm
= 2 V (TSX922IYST and
TSX922IYDT order codes only)
T min
< T op
< T max
All order codes except TSX922IYST and TSX922IYDT
TSX922IYST and TSX922IYDT order codes only
TSX920/TSX921
TSX922/TSX923
V out
= V
CC
/2
T min
< T op
< T max
V out
= V
CC
/2
T min
< T op
< T max
72
70
64
2
2
92
128
10
10
1
8
85
75
4
5
5
6.5
10
15
100
200
100
200 mV
μV/°C nV/√month pA
TΩ pF
A vd
V
OH
V
OL
I out
Large signal voltage gain
High-level output voltage
Low-level output voltage
I sink
I source
V icm
= -0.1 V to 7 V, V
OUT
= V
CC
/2
T min
< T op
< T max
V icm
= -0.1 V to 10.1 V,
V
OUT
= V
CC
/2
T min
< T op
< T max
R
L
= 2 kΩ, V out
= 0.3 V to 9.7 V
T min
< T op
< T max
R
L
= 10 kΩ, V out
= 0.2 V to 9.8 V
T min
< T op
< T max
R
L
= 2 kΩ tο V
CC
/2
T min
< T op
< T max
R
L
= 10 kΩ tο V
CC
/2
T min
< T op
< T max
R
L
= 2 kΩ tο V
CC
/2
T min
< T op
< T max
R
L
= 10 kΩ tο V
CC
/2
T min
< T op
< T max
V out
= 10 V
T min
< T op
< T max
V out
= 0 V
T min
< T op
< T max
50
42
75
70
62
100 107
90
100 117
90
94
31
80
14
82
55
110
130
40
50
110
130
40
50 dB mV from
V
CC
+ mV mA
DocID024310 Rev 4 7/32
Electrical characteristics
Symbol Parameter Conditions
TSX920, TSX921, TSX922, TSX923
Min. Typ. Max. Unit
I
CC
Supply current
(per amplifier)
GBP Gain bandwidth product
F
U ɸm
Unity gain frequency
Phase margin
G m
Gain margin
No load, V out
= V
CC
/2
T min
< T op
< T max
R
L
= 10 kΩ, C
L
= 20 pF, G = 20 dB
3.1 3.6
3.6 mA
R
L
= 10 kΩ, C
L
= 20 pF
10
11.2
56
6
MHz
Degrees dB
SR+ Positive slew rate
SR- Negative slew rate
Av = 1, V out
= 0.5 to 9.5 V, measured between 10 % to 90 %
Av = 1, V out
= 9.5 to 0.5 V, measured between 90 % to 10 %
17.7
19.6
V/μs e n
Equivalent input noise voltage f = 10 kHz f = 100 kHz
∫e n
Low-frequency peak-topeak input noise
Bandwidth: f = 0.1 to 10 Hz
THD+N
Total harmonic distortion
+ noise f = 1 kHz, Av = 1, R
L
= 10 kΩ,
V out
= 2 V rms
Shutdown characteristics (TSX920 and TSX923 only)
I
CC_shdn
Supply current in shutdown mode
(per amplifier)
SHDN
= V
CC-
T min
< T op
< T max t on t off
Amplifier turn-on time
Amplifier turn-off time
16.8
12
8.64
0.0006
7
2.4
0.35
15
20 nV√Hz
µV pp
%
µΑ
µs
Notes:
(1)
Typical value is based on the Vio drift observed after 1000 h at 125 °C extrapolated to 25 °C using the Arrhenius law and
(2)
When used in comparator mode, with high differential input voltage, during a long period of time with V
CC
close to 16 V and
V icm
>V
CC
/2, Vio can experience a permanent drift of a few mV drift. This phenomenon is notably worse at low temperatures.
8/32 DocID024310 Rev 4
TSX920, TSX921, TSX922, TSX923 Electrical characteristics
Table 6: Electrical characteristics at VCC+ = 16 V with VCC- = 0 V, Vicm = VCC/2,
Tamb = 25 °C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit
V io
∆V io
I ib
I io
R
IN
C
IN
CMRR
Input offset voltage
∆V io
/∆T Input offset voltage drift
Long-term input offset
Input bias current
Input offset current
Input resistance
Input capacitance
Common mode rejection ratio 20 log (ΔV ic
/ΔV io
)
V icm
= 2 V (all order codes except
TSX922IYST and TSX922IYDT)
T min
< T op
< T max
V icm
= 2 V (TSX922IYST and
TSX922IYDT order codes only)
T min
< T op
< T max
All order codes except TSX922IYST and TSX922IYDT
TSX922IYST and TSX922IYDT order codes only
TSX920/TSX921
TSX922/TSX923
V out
= V
CC
/2
T min
< T op
< T max
V out
= V
CC
/2
T min
< T op
< T max
73
71
67
2
2
1.73
2.26
10
10
1
8
85
76
4
5
5
6.5
10
15
100
200
100
200 mV
μV/°C nV/√month pA
TΩ pF
SVRR
A vd
V
OH
V
OL
Supply voltage rejection ratio
Large signal voltage gain
High-level output voltage
Low-level output voltage
V icm
= -0.1 V to 13 V, V
OUT
= V
CC
/2
T min
< T op
< T max
V icm
= -0.1 V to 16.1 V,
V
OUT
= V
CC
/2
T min
< T op
< T max
V
CC
= 4.5 V tο 16 V
T min
< T op
< T max
R
L
= 2 kΩ, V out
= 0.3 V to 15.7 V
T min
< T op
< T max
R
L
= 10 kΩ, V out
= 0.2 V to 15.8 V
T min
< T op
< T max
R
L
= 2 kΩ tο V
CC
/2
T min
< T op
< T max
R
L
= 10 kΩ tο V
CC
/2
T min
< T op
< T max
R
L
= 2 kΩ tο V
CC
/2
T min
< T op
< T max
R
L
= 10 kΩ tο V
CC
/2
T min
< T op
< T max
65
73 85
71
100 105
90
100 113
90
150
43
140
30 dB mV from
V
CC
+ mV
200
230
50
70
200
230
50
70
DocID024310 Rev 4 9/32
Electrical characteristics
Symbol Parameter Conditions
TSX920, TSX921, TSX922, TSX923
Min. Typ. Max. Unit
I out
I
CC
I sink
I source
Supply current
(per amplifier)
V out
= 16 V
T min
< T op
< T max
V out
= 0 V
T min
< T op
< T max
No load, V out
= V
CC
/2
T min
< T op
< T max
R
L
= 10 kΩ, C
L
= 20 pF, G = 20 dB
45
40
65
60
50
74
2.8 3.4 mA
GBP Gain bandwidth product
F
U ɸm
Unity gain frequency
Phase margin
G m
Gain margin
10
12
55
3.4
MHz
R
L
= 10 kΩ, C
L
= 20 pF
5.9
Degrees dB
SR+ Positive slew rate
Av = 1, V out
= 0.5 to 15.5 V, measured between 10 % to 90 %
16.2
SR- Negative slew rate
Av = 1, V out
= 15.5 to 0.5 V, measured between 90 % to 10 % f = 10 kHz e n
Equivalent input noise voltage f = 100 kHz
∫e n
Low-frequency peak-topeak input noise
Bandwidth: f = 0.1 to 10 Hz
THD+N
Total harmonic distortion
+ noise f = 1 kHz, Av = 1, R
L
= 10 kΩ,
V out
= 4 V rms
Gain = 1, 100 mV input voltage,
0.1 % of final value t
S
Shutdown characteristics (TSX920 and TSX923 only)
I
CC_shdn
Supply current in shutdown mode
(per amplifier)
SHDN
= V
CC-
T min
< T op
< T max t on t off
Setting time
Amplifier turn-on time
Amplifier turn-off time
Gain = 1, 100 mV input voltage,
1 % of final value
17.2
16.5
11.8
8.58
0.0003
245
178
7
1.5
15
20
V/μs nV√Hz
µV pp
% ns
µΑ
0.2
µs
Notes:
(1)
Typical value is based on the Vio drift observed after 1000 h at 125 °C extrapolated to 25 °C using the Arrhenius law and
(2)
When used in comparator mode, with high differential input voltage, during a long period of time with V
CC
close to 16 V and
V icm
>V
CC
/2, Vio can experience a permanent drift of a few mV drift. This phenomenon is notably worse at low temperatures.
10/32 DocID024310 Rev 4
TSX920, TSX921, TSX922, TSX923 Electrical characteristic curves
4 Electrical characteristic curves
Figure 2: Supply current vs.supply voltage Figure 3: Distribution of input offset voltage at VCC = 4.5 V
Figure 4: Distribution of input offset voltage at VCC = 10 V
Figure 5: Distribution of input offset voltage at VCC = 16 V
Figure 6: Input offset voltage vs. temperature at VCC = 16 V
Figure 7: Distribution of input offset voltage drift over temperature
DocID024310 Rev 4 11/32
Electrical characteristic curves
Figure 8: Input offset voltage vs. common-mode voltage at VCC = 4 V
TSX920, TSX921, TSX922, TSX923
Figure 9: Input offset voltage vs. common-mode voltage at VCC = 16 V
Figure 10: Output current vs. output voltage at VCC = 4 V
Figure 11: Output current vs. output voltage at VCC = 10 V
12/32
Figure 12: Output current vs. output voltage at VCC = 16 V
Figure 13: Output rail linearity
DocID024310 Rev 4
TSX920, TSX921, TSX922, TSX923
Figure 14: Open loop gain vs. frequency
Electrical characteristic curves
Figure 15: Bode diagram vs. temperature for VCC = 4 V
Figure 16: Bode diagram vs. temperature for VCC = 10 V
Figure 17: Bode diagram vs. temperature for VCC = 16 V
Figure 18: Bode diagram at VCC = 16 V with low common-mode voltage
Figure 19: Bode diagram at VCC = 16 V with high common-mode voltage
DocID024310 Rev 4 13/32
Electrical characteristic curves
Figure 20: Bode diagram at VCC = 16 V and
RL = 10 kΩ, CL = 47 pF
TSX920, TSX921, TSX922, TSX923
Figure 21: Bode diagram at VCC = 16 V and
RL = 10 kΩ, CL = 120 pF
Figure 22: Bode diagram at VCC = 16 V and
RL = 2.2 kΩ, CL = 20 pF
Figure 23: Slew rate vs. supply voltage and temperature
Figure 24: Overshoot vs. capacitive load without feedback capacitor
Figure 25: Closed loop gain vs. frequency with different gain resistors
14/32 DocID024310 Rev 4
TSX920, TSX921, TSX922, TSX923
Figure 26: Large step response
Electrical characteristic curves
Figure 27: Small step response
Figure 28: Small step response with feedback capacitor CF
Figure 29: Output impedance vs. frequency in closed loop configuration
Figure 30: Noise vs. frequency with 16 V supply voltage Figure 31: 0.1 to 10 Hz noise
DocID024310 Rev 4 15/32
Electrical characteristic curves
Figure 32: THD+N vs. frequency at VCC = 16 V
TSX920, TSX921, TSX922, TSX923
Figure 33: THD+N vs. output voltage at VCC = 16 V
Figure 34: Power supply rejection ratio (PSRR) vs. frequency
Figure 35: Crosstalk vs. frequency between operators on TSX922 at VCC = 16 V
Figure 36: Startup time after standby released for VCC = 4 V
Figure 37: Startup time after standby released for VCC = 16 V
16/32 DocID024310 Rev 4
TSX920, TSX921, TSX922, TSX923
5
5.1
5.2
5.3
Application information
Application information
Operating voltages
The TSX92x operational amplifiers can operate from 4 V to 16 V. The parameters are fully specified at 4.5 V, 10 V, and 16 V power supplies. However, parameters are very stable in the full V
CC
range. Additionally, main specifications are guaranteed in the extended temperature range from -40 to 125 °C.
Rail-to-rail input
The TSX92x series is designed with two complementary PMOS and NMOS input differential pairs. The device has a rail-to-rail input and the input common mode range is extended from (V
CC-
) - 0.1 V to (V
CC+
) + 0.1 V. However, the performance of this device is clearly optimized for the PMOS differential pairs (which means from (V
CC-
) - 0.1 V to
(V
CC+
) - 2 V).
Beyond (V
CC+
) - 2 V, the operational amplifier is still functional but with downgraded
performances (see Figure 19 ). Performances are still suitable for a large number of
applications requiring the rail-to-rail input feature.
The TSX92x operational amplifiers are designed to prevent phase reversal.
Input pin voltage range
The TSX92x operational amplifiers have internal ESD diode protections on the inputs.
These diodes are connected between the input and each supply rail to protect MOSFETs inputs from electrostatic discharges.
Thus, if the input pin voltage exceeds the power supply by 0.5 V, the ESD diodes become conductive and excessive current could flow through them. To prevent any permanent damage, this current must be limited to 10 mA. This can be done by adding a resistor in
series with the input pin ( Figure 38: "Limiting input current with a series resistor" ). The
resistor value has to be calculated for a 10 mA current limitation on the input pins.
Figure 38: Limiting input current with a series resistor
DocID024310 Rev 4 17/32
Application information
5.4
5.5
TSX920, TSX921, TSX922, TSX923
Input offset voltage drift over temperature
The maximum input voltage drift over the temperature variation is defined as the offset variation related to offset value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum input voltage drift over temperature enables the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift over temperature is computed using Equation 1 .
Equation 1
∆V io
∆T
= ma x
V io
T – V io
25
T – 25 °C
°C with T = -40 °C and 125 °C.
The datasheet maximum value is guaranteed by a measurement on a representative sample size ensuring a C pk
(process capability index) greater than 2.
Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
Voltage acceleration, by changing the applied voltage
Temperature acceleration, by changing the die temperature (below the maximum junction temperature allowed by the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using
Equation 2
S
– V
U A
FV
= e
Where:
A
FV
is the voltage acceleration factor
β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1)
V
S
is the stress voltage used for the accelerated test
V
U
is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined in
Equation 3
A
FT
= e
E a
.
1
T
U
–
1
T
S
Where:
A
FT
is the temperature acceleration factor
E a
is the activation energy of the technology based on the failure rate
18/32 DocID024310 Rev 4
TSX920, TSX921, TSX922, TSX923 k is the Boltzmann constant (8.6173 x 10
-5
eV.K
-1
)
Application information
T
U
is the temperature of the die when V
U
is used (K)
T
S
is the temperature of the die under temperature stress (K)
The final acceleration factor, A
F
, is the multiplication of the voltage acceleration factor and
the temperature acceleration factor ( Equation 4 ).
Equation 4
A
F
= A
FT
× A
FV
A
F is calculated using the temperature and voltage defined in the mission profile of the product. The A
F
value can then be used in Equation 5 to calculate the number of months of
use equivalent to 1000 hours of reliable stress duration.
Equation 5
Months = A
F
× 1000 h × 12 months / 24 h × 365.25 days
To evaluate the op amp reliability, a follower stress condition is used where V
CC
is defined as a function of the maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules).
The V io
drift (in µV) of the product after 1000 h of stress is tracked with parameters at
different measurement conditions (see Equation 6 ).
Equation 6
V
CC
= maxV op with V icm
= V
CC
2
The long term drift parameter (ΔV io
), estimating the reliability performance of the product, is obtained using the ratio of the V io
(input offset voltage value) drift over the square root of
the calculated number of months ( Equation 7 ).
Equation 7
∆V io
=
V io dr ift month s
Where V io
drift is the measured drift value in the specified test conditions after 1000 h stress duration.
DocID024310 Rev 4 19/32
Application information
5.6
TSX920, TSX921, TSX922, TSX923
Capacitive load
Driving a large capacitive load can cause stability issues. Increasing the load capacitance produces gain peaking in the frequency response, with overshooting and ringing in the step response. It is usually considered that with a gain peaking higher than 2.3 dB the op-amp might become unstable. Generally, the unity gain configuration is the worst configuration
the system stable.
Figure 39: Stability criteria with a serial resistor
Figure 40: Test configuration for Riso
20/32 DocID024310 Rev 4
TSX920, TSX921, TSX922, TSX923
5.7
Application information
High-side current sensing
TSX92x rail to rail input devices can be used to measure a small differential voltage on a high side shunt resistor and translate it into a ground referenced output voltage. The gain is fixed by external resistance.
Figure 41: High-side current sensing configuration
V out can be expressed as follows:
Equation 8
V ou t
= R shun t
× I 1 –
R g2
R g2
+ R f2
1 +
R f1
R g1
+ I p
R g2
×
R g2
+
R f2
R f2
× 1 +
R f1
R g1
– l n
× R f1
– V io
1 +
R f1
R g1
Assuming that R f2
= R f1
= R f
and R g2
= R g1
= R g
, Equation 8 can be simplified as follows:
Equation 9
V out
= R shunt
× I
R f
R g
– V io
1 +
R f
R g
+ R f
× I io
With the TSX92x operational amplifiers, the high side current measurement must be made by respecting the common mode voltage of the amplifier: (V
CC-
) - 0.1 V to (V
CC+
) + 0.1 V. If the application requires a higher common voltage please refer to the TSC high side current sensing family.
DocID024310 Rev 4 21/32
Application information
5.8
TSX920, TSX921, TSX922, TSX923
High-speed photodiode
The TSX92x series is an excellent choice for current to voltage (I-V) conversions. Due to the CMOS technology, the input bias currents are extremely low. Moreover, the low noise and high unity-gain bandwidth of the TSX92x operational amplifiers make them particularly suitable for high-speed photodiode preamplifier applications.
The photodiode is considered as a capacitive current source. The input capacitance, C
IN
, includes the parasitic input Common mode capacitance, C
CM
(3pF), and the input differential mode capacitance, C
DIFF
(8pF). C
IN
acts in parallel with the intrinsic capacitance of the photodiode, C
D
. At higher frequencies, the capacitors affect the circuit response. The output capacitance of a current sensor has a strong effect on the stability of the op-amp feedback loop.
C
F
stabilizes the gain and limits the transimpedance bandwidth. To ensure good stability and to obtain good noise performance, C
F
can be set as shown in Equation 10 .
Equation 10 where,
C
IN
= C
CM
+ C
DIFF
= 11 pF
C
DIFF
is the differential input capacitance: 8 pF typical
C
CM
is the Common mode input capacitance: 3 pF typical
C
D
is the intrinsic capacitance of the photodiode
C
SMR
is the parasitic capacitance of the surface mount R
F
resistor: 0.2 pF typical
F
GBP
is the gain bandwidth product: 10 MHz at 16 V
R
F
fixes the gain as shown in Equation 11.
Equation 11
V
OUT
= R
F
x I
D
Figure 42: High-speed photodiode
22/32 DocID024310 Rev 4
TSX920, TSX921, TSX922, TSX923
6 Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
DocID024310 Rev 4 23/32
Package information
6.1 SOT23-5 package information
TSX920, TSX921, TSX922, TSX923
Figure 43: SOT23-5 package outline
24/32
Ref.
D1 e
E
F
L
K
A
A1
A2
B
C
D
Min.
0.90
0.90
0.35
0.09
2.80
2.60
1.50
0.10
0 degrees
1.05
0.40
0.15
2.90
1.90
0.95
2.80
1.60
0.35
Table 7: SOT23-5 mechanical data
Dimensions
Millimeters
Typ.
1.20
Min.
0.035
Max.
1.45
0.15
1.30
0.50
0.20
3.00
0.035
0.014
0.004
0.110
3.00
1.75
0.102
0.059
0.60 0.004
10 degrees 0 degrees
Inches
Typ.
0.047
0.041
0.016
0.006
0.114
0.075
0.037
0.110
0.063
0.014
Max.
0.057
0.006
0.051
0.020
0.008
0.118
0.118
0.069
0.024
10 degrees
DocID024310 Rev 4
TSX920, TSX921, TSX922, TSX923
6.2 SOT23-6 package information
Figure 44: SOT23-6 package outline
Package information
Ref.
D
E e
H
L
θ
A
A1
A2 b c
Min.
0.90
0.90
0.35
0.09
2.80
1.50
2.60
0.10
0 °
Table 8: SOT23-6 mechanical data
Dimensions
Millimeters
Typ. Min.
0.035
0.95
Max.
1.45
0.10
1.30
0.50
0.20
3.05
1.75
3.00
0.60
10 °
0.035
0.013
0.003
0.110
0.060
0.102
0.004
0 °
Inches
Typ.
0.037
Max.
0.057
0.004
0.051
0.019
0.008
0.120
0.069
0.118
0.024
10 °
DocID024310 Rev 4 25/32
Package information
6.3 MiniSO8 package information
TSX920, TSX921, TSX922, TSX923
Figure 45: MiniSO8 package outline
26/32
Ref. e
L
L1
L2 k ccc
A
A1
A2 b c
D
E
E1
Min.
0.40
0°
0
0.75
0.22
0.08
2.80
4.65
2.80
3.00
4.90
3.00
0.65
0.60
0.95
0.25
Table 9: MiniSO8 mechanical data
Dimensions
Millimeters
Typ. Min.
0.85
Max.
1.1
0.15
0.95
0.40
0.23
3.20
5.15
3.10
0.80
0
0.030
0.009
0.003
0.11
0.183
0.11
0.016
0° 8°
0.10
Inches
Typ.
0.033
0.118
0.193
0.118
0.026
0.024
0.037
0.010
Max.
0.043
0.006
0.037
0.016
0.009
0.126
0.203
0.122
0.031
8°
0.004
DocID024310 Rev 4
TSX920, TSX921, TSX922, TSX923
6.4 SO8 package information
Figure 46: SO8 package outline
Package information
Ref.
L
L1 k ccc
E
E1 e h
A
A1
A2 b c
D
Min.
0.10
1.25
0.28
0.17
4.80
5.80
3.80
0.25
0.40
1°
Table 10: SO8 mechanical data
Dimensions
Millimeters
Typ. Min. Max.
1.75
0.25
4.90
6.00
3.90
1.27
0.48
0.23
5.00
6.20
4.00
0.50
1.27
0.004
0.049
0.011
0.007
0.189
0.228
0.150
0.010
0.016
1.04
8°
0.10
1°
Inches
Typ.
0.193
0.236
0.154
0.050
0.040
Max.
0.069
0.010
0.019
0.010
0.197
0.244
0.157
0.020
0.050
8°
0.004
DocID024310 Rev 4 27/32
Package information
6.5 DFN8 2x2 package information
TSX920, TSX921, TSX922, TSX923
Figure 47: DFN8 2x2 package outline
28/32
Ref.
D
E e
L
A
A1 b
N
Min.
0.70
0.00
0.15
0.045
Table 11: DFN8 2x2 mechanical data
Dimensions
Millimeters
Typ.
0.75
0.02
0.20
2.00
2.00
0.50
0.55
Max.
0.80
0.05
0.25
0.65
Min.
0.028
0.000
0.006
0.018
8
Inches
Typ.
0.030
0.001
0.008
0.079
0.079
0.020
0.022
DocID024310 Rev 4
Max.
0.031
0.002
0.010
0.026
TSX920, TSX921, TSX922, TSX923
6.6 MiniSO10 package information
Figure 48: MiniSO10 package outline
Package information
Ref.
E1 e
L
L1 k aaa b c
D
E
A
A1
A2
Min.
0.05
0.78
0.25
0.15
2.90
4.75
2.90
0.40
0°
3.00
0.50
0.55
0.95
3°
0.10
0.86
0.33
0.23
3.00
4.90
Table 12: MiniSO-10 package mechanical data
Dimensions
Millimeters Inches
Typ. Max.
1.10
0.15
0.94
0.40
0.30
3.10
5.05
3.10
Min.
0.002
0.031
0.010
0.006
0.114
0.187
0.114
Typ.
0.70
6°
0.10
0.016
0°
0.004
0.034
0.013
0.009
0.118
0.193
0.118
0.020
0.022
0.037
3°
Max.
0.043
0.006
0.037
0.016
0.012
0.122
0.199
0.122
0.028
6°
0.004
DocID024310 Rev 4 29/32
Ordering information
7 Ordering information
Order code
TSX920ILT
TSX921ILT
TSX922IDT
TSX922IST
TSX922IQ2T
TSX923IST
TSX920, TSX921, TSX922, TSX923
Table 13: Order codes
Temperature range Package
-40 °C to 125 °C
SOT23-6
SΟΤ23-5
SO8
MiniSO8
DFN8 2x2
MiniSO8 (automotive grade)
SO8 (automotive grade)
MiniSO10
Packing Marking
K304
Tape and reel
K305
TSX922I
SX922IY
K305
K26
K312
SX922IY
K305
Notes:
(1)
Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to
AEC Q001 & Q 002 or equivalent.
30/32 DocID024310 Rev 4
TSX920, TSX921, TSX922, TSX923
8
Revision history
Revision history
Date Revision
Table 14: Document revision history
Changes
12-Apr-2013
27-Jun-2013
10-Dec-2013
14-Jan-2016
1
2
3
4
Initial release
Added TSX920,TSX922, TSX923 devices.
Added packages for TSX920,TSX922, and TSX923.
Added shutdown characteristics in Table 4, Table 5, and Table 6.
Added Figure 35, Figure 36, and Figure 37.
Updated Table 13 for new order codes.
Added long-term input offset voltage drift parameter in Table 4, Table 5, and Table 6.
Added Section 5.4: Input offset voltage drift over temperature in
Section 5: Application information.
Added Section 5.5: Long-term input offset voltage drift section in
Section 5: Application information.
Updated document layout
io
and DV io
/DT parameters
Table 7 : updated inches dimension "B" (typ) and "L" (typ and max) to
align with rounded-off values of POA.
Table 10 : updated minimum mm dimensions for "k"
Table 13: "Order codes" : added order codes TSX922IYST and
TSX922IYDT.
DocID024310 Rev 4 31/32
TSX920, TSX921, TSX922, TSX923
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2016 STMicroelectronics
– All rights reserved
32/32 DocID024310 Rev 4
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