STD3LN80K5
Nchannel 800 V, 2.75 Ω typ., 2 A MDmesh™ K5
Power MOSFET in a DPAK package
Datasheet - production data
Figure 1: Internal schematic diagram
D(2, TAB)
G(1)
Order code
STD3LN80K5
S(3)
Features
Order code V
DS
R
DS(on)
max
STD3LN80K5 800 V 3.25 Ω
Industry’s lowest R
DS(on)
x area
Industry’s best FoM (figure of merit)
Ultra-low gate charge
100% avalanche tested
Zener-protected
I
D
2 A
Applications
Switching applications
Description
This very high voltage N-channel Power
MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency.
AM01476v1
Table 1: Device summary
Marking Package
3LN80K5 DPAK
Packing
Tape and reel
July 2016 DocID027714 Rev 2
This is information on a product in full production.
1/15 www.st.com
Contents
Contents
STD3LN80K5
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
4.2
DPAK package information ............................................................... 9
DPAK packing information .............................................................. 12
5 Revision history ............................................................................ 14
2/15 DocID027714 Rev 2
STD3LN80K5
1
Electrical ratings
Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
GS
I
D
I
D
I
D
(1)
P
TOT
dv/dt (2) dv/dt (3)
T stg
T j
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Storage temperature range
Operating junction temperature range
Value
± 30
2
1.25
8
45
4.5
50
- 55 to 150 °C
Notes:
(1)
Pulse width limited by safe operating area.
(2)
I
SD
≤ 2 A, di/dt ≤ 100 A/µs; V
DSpeak
< V
(BR)DSS
, V
DD
= 640 V
(3)
V
DS
≤ 640 V.
Symbol
Table 3: Thermal data
Parameter
R thj-case
R
thj-pcb
(1)
Thermal resistance junction-case
Thermal resistance junction-pcb
Value
2.78
50
Unit
°C/W
°C/W
Notes:
(1)
When mounted on 1inch² FR-4 board, 2 oz Cu.
Symbol
Table 4: Avalanche characteristics
Parameter
I
AR
E
AS
Avalanche current, repetitive or not repetitive (pulse width limited by T jmax
)
Single pulse avalanche energy (starting T j
= 25°C, I
D
= I
AR
; V
DD
= 50 V)
Value Unit
0.7 A
155 mJ
Unit
V
A
A
A
W
V/ns
DocID027714 Rev 2 3/15
Electrical characteristics
2 Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Symbol Parameter
Table 5: On /off states
Test conditions
V
(BR)DSS
Drain-source breakdown voltage
I
D
= 1 mA, V
GS
= 0 V
I
DSS
Zero gate voltage drain current
V
DS
= 800 V, V
GS
= 0 V
V
DS
= 800 V, V
GS
= 0 V,
T
C
= 125 °C (1)
I
GSS
Gate body leakage current
V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source on-resistance
V
GS
= ± 20 V, V
GS
= 0 V
V
DS
= V
GS
, I
D
= 100 µA
V
GS
= 10 V, I
D
= 1 A
STD3LN80K5
Min. Typ. Max. Unit
800
1
V
µA
50 µA
±10 µA
4 5 V
2.75 3.25 Ω
3
Notes:
(1)
Defined by design, not subject to production test.
Symbol Parameter
Table 6: Dynamic
Test conditions
C iss
C oss
C rss
C
otr
(1)
C
oer
(2)
R
G
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent capacitance time related
Equivalent capacitance energy related
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
V
DS
= 0 to 640 V, V
GS
= 0 V f = 1 MHz, I
D
= 0 A
V
DD
= 640 V, I
D
= 2 A,
V
GS
= 10 V ( see Figure 15:
"Test circuit for gate charge behavior" )
Min. Typ. Max. Unit
-
-
-
102
11
0.1
-
-
- pF pF pF
-
-
-
-
-
-
20
7
12
2.63
0.91
1.53
-
-
-
-
-
- pF pF
Ω nC nC nC
Notes:
(1)
Time related is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS increases from 0 to 80% V
DSS
(2)
Energy related is defined as a constant equivalent capacitance giving the same stored energy as C oss
when V
DS increases from 0 to 80% V
DSS
4/15 DocID027714 Rev 2
STD3LN80K5
Symbol Parameter t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time t f
Fall time
Table 7: Switching times
Test conditions
V
DD
= 400 V, I
D
= 1 A, R
G
= 4.7
Ω,
V
GS
= 10 V ( see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform" )
Symbol Parameter
I
SD
Source-drain current
I
SDM
(1)
Source-drain current
(pulsed)
V
SD
(2)
Forward on voltage t rr
I
Q rr
RRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current t rr
I
Q rr
RRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Table 8: Source drain diode
Test conditions
I
I
I
SD
SD
V
= 2 A, V
DD
GS
= 0 V
circuit for inductive load switching and diode recovery times"
SD
V
= 2 A, di/dt = 100 A/µs,
= 60 V ( see
)
Figure 16: "Test
= 2 A, di/dt = 100 A/µs,
DD
= 60 V, T j
= 150 °C, (see
Figure 16: "Test circuit for inductive load switching and diode recovery times" )
Electrical characteristics
Min. Typ. Max. Unit
-
-
-
-
Min. Typ. Max. Unit
- 2 A
- 8 A
-
- 210
1.5 V ns
- 0.8 µC
-
-
-
-
6.2
7
30
26
7.6
345
1.2
7.2
-
-
-
- ns ns ns ns
A ns
µC
A
Notes:
(1)
Pulse width limited by safe operating area.
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%.
Symbol
Table 9: Gate-source Zener diode
Parameter Test conditions
V
(BR)GSO
Gate-source breakdown voltage I
GS
= ± 1 mA, I
D
= 0 A
Min. Typ. Max. Unit
30 - - V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry.
5/15 DocID027714 Rev 2
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STD3LN80K5
K
Figure 3: Thermal impedance
CG34360
10
0 c
10
-1
Figure 4: Output characteristics
10
-2
10
-5
10
-4
10
-3
10
-2
10
-1 t p
(s)
Figure 5: Transfer characteristics
6/15
Figure 6: Gate charge vs gate-source voltage
Figure 7: Static drain-source on-resistance
DocID027714 Rev 2
STD3LN80K5
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Source-drain diode forward characteristics
Figure 10: Normalized gate threshold voltage vs temperature
Figure 11: Normalized on-resistance vs temperature
Figure 12: Normalized V(BR)DSS vs temperature
Figure 13: Maximum avalanche energy vs starting TJ
DocID027714 Rev 2 7/15
Test circuits
3 Test circuits
Figure 14: Test circuit for resistive load switching times
STD3LN80K5
Figure 15: Test circuit for gate charge behavior
V
DD
RL
V
GS pulse width
2200
μF
+
1 kΩ
I
G
= CONST
2.7 kΩ
47 kΩ
100 Ω D.U.T.
V
G
AM01469v10
Figure 16: Test circuit for inductive load switching and diode recovery times
Figure 17: Unclamped inductive load test circuit
Figure 18: Unclamped inductive waveform
Figure 19: Switching time waveform
8/15 DocID027714 Rev 2
STD3LN80K5
4
4.1
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
DPAK package information
Figure 20: DPAK (TO-252) type A package outline
DocID027714 Rev 2
0068772_A_21
9/15
Package information
Dim.
D1
E
E1 e e1
H
L
(L1)
L2
L4
R
V2 b4 c c2
D
A
A1
A2 b
STD3LN80K5
Table 10: DPAK (TO-252) type A mechanical data mm
Min. Typ.
4.95
6.40
4.60
2.16
4.40
9.35
1.00
2.20
0.90
0.03
0.64
5.20
0.45
0.48
6.00
2.60
0.65
0.60
4.70
2.28
0.20
0°
2.80
0.80
5.10
Max.
5.25
6.60
4.80
2.40
4.60
10.10
1.50
2.40
1.10
0.23
0.90
5.40
0.60
0.60
6.20
3.00
0.95
1.00
8°
10/15 DocID027714 Rev 2
STD3LN80K5 Package information
Figure 21: DPAK (TO-252) recommended footprint (dimensions are in mm)
DocID027714 Rev 2 11/15
Package information
4.2 DPAK packing information
Figure 22: DPAK (TO-252) tape outline
STD3LN80K5
12/15 DocID027714 Rev 2
STD3LN80K5
Figure 23: DPAK (TO-252) reel outline
Package information
Dim.
F
K0
P0
P1
P2
R
T
W
A0
B0
B1
D
D1
E
7.9
1.9
40
0.25
15.7
1.5
1.5
1.65
7.4
2.55
3.9
Table 11: DPAK (TO-252) tape and reel mechanical data
Tape Reel mm
Dim.
Min.
6.8
10.4
Max.
7
10.6
12.1
1.6
1.85
7.6
2.75
4.1
8.1
2.1
A
B
C
D
G
N
T
Base qty.
Bulk qty.
Min.
1.5
12.8
20.2
16.4
50
0.35
16.3 mm
Max.
330
13.2
18.4
22.4
2500
2500
DocID027714 Rev 2 13/15
Revision history
5
STD3LN80K5
Revision history
Date Revision
Table 12: Document revision history
Changes
13-May-2015
27-Jul-2016
1
2
Initial release
Updated title and features in cover page.
Updated Section 1: "Electrical ratings"
and Section 2: "Electrical characteristics" .
Added Section 2.1: "Electrical characteristics (curves)" .
Document status promoted from preliminary to production data.
Minor text changes.
14/15 DocID027714 Rev 2
STD3LN80K5
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DocID027714 Rev 2 15/15
