STD9N40M2
Datasheet
N-channel 400 V, 0.59 Ω typ., 6 A MDmesh™ M2 Power MOSFET
in a DPAK package
Features
TAB
2 3
1
DPAK
D ( 2 , TAB )
Order code
VDS @ TJmax
RDS(on)max.
ID
STD9N40M2
450 V
0.8 Ω
6A
•
•
Extremely low gate charge
Excellent output capacitance (COSS) profile
•
•
100% avalanche tested
Zener-protected
Applications
G( 1)
•
Switching applications
Description
AM15572V1
S(3)
This device is an N-channel Power MOSFET developed using MDmesh™ M2
technology. Thanks to its strip layout and an improved vertical structure, the device
exhibits low on-resistance and optimized switching characteristics, rendering it
suitable for the most demanding high efficiency converters.
Product status
STD9N40M2
Product summary
Order code
STD9N40M2
Marking
9N40M2
Package
DPAK
Packing
Tape and reel
DS10114 - Rev 3 - August 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
STD9N40M2
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDS
Drain-source voltage
400
V
VGS
Gate-source voltage
±25
V
Drain current (continuous) at TC = 25 °C
6
A
Drain current (continuous) at TC = 100 °C
3.8
A
Drain current (pulsed)
24
A
Total dissipation at TC = 25 °C
60
W
Peak diode recovery voltage slope
15
V/ns
MOSFET dv/dt ruggedness
50
V/ns
-55 to 150
°C
Value
Unit
ID
ID
IDM
(1)
PTOT
dv/dt (2)
dv/dt
(3)
Tj
Tstg
Operating junction temperature range
Storage temperature range
1. Pulse width limited by safe operating area.
2. ISD ≤ 6 A, di/dt ≤ 400 A/μs; VDS peak < V(BR)DSS, VDD = 320 V.
3. VDS ≤ 320 V.
Table 2. Thermal data
Symbol
Parameter
Rthj-case
Thermal resistance junction-case
2.08
°C/W
Rthj-pcb(1)
Thermal resistance junction-pcb
50
°C/W
Value
Unit
2.5
A
148
mJ
1. When mounted on 1 inch² FR-4, 2 Oz copper board.
Table 3. Avalanche characteristics
Symbol
IAR
EAS
DS10114 - Rev 3
Parameter
Avalanche current, repetitive or not-repetitive
(pulse width limited by Tjmax)
Single pulse avalanche energy
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)
page 2/18
STD9N40M2
Electrical characteristics
2
Electrical characteristics
(TCASE = 25 °C unless otherwise specified)
Table 4. On/off states
Symbol
V(BR)DSS
Parameter
Drain-source breakdown
voltage
Test conditions
ID = 1 mA, VGS = 0 V
Min.
Typ.
Max.
400
Unit
V
VDS = 400 V, VGS = 0 V
1
µA
(1)
100
µA
Gate body leakage current
VDS = 0 V, VGS = ±25 V
±10
µA
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 250 µA
3
4
V
RDS(on)
Static drain-source on
resistance
VGS = 10 V, ID = 3 A
0.59
0.8
Ω
Typ.
Max.
Unit
-
pF
IDSS
IGSS
Zero gate voltage drain
current
VDS = 400 V, VGS = 0 V, TC = 125 °C
2
1. Defined by design, not subject to production test.
Table 5. Dynamic
Symbol
Parameter
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer capacitance
Coss eq.(1)
Equivalent output
capacitance
Rg
Gate input resistance
Qg
Total gate charge
Qgs
Gate-source charge
Qgd
Gate-drain charge
Test conditions
Min.
270
VDS = 100 V, f = 1 MHz, VGS = 0 V
-
22
0.7
VGS = 0 V, VDS = 0 to 320 V
-
94
-
pF
f = 1 MHz open drain
-
7.1
-
Ω
-
nC
8.8
VDD = 320 V, ID = 6 A,
VGS = 0 to 10 V(see Figure 14. Test
circuit for gate charge behavior)
-
1.7
4.8
1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0
to 80% VDSS.
Table 6. Switching times
Symbol
td(on)
tr
td(off)
tf
DS10114 - Rev 3
Parameter
Test conditions
Turn-on delay time
VDD = 200 V, ID = 3 A,
Rise time
RG = 4.7 Ω, VGS = 10 V
Turn-off delay time
(see Figure 13. Test circuit for
resistive load switching times and
Figure 18. Switching time waveform)
Fall time
Min.
Typ.
Max.
Unit
-
ns
10.5
-
9
7.5
21
page 3/18
STD9N40M2
Electrical characteristics
Table 7. Source drain diode
Symbol
ISD
Parameter
Test conditions
Source-drain current
Min.
Typ.
6
-
ISDM (1)
Source-drain current (pulsed)
VSD (2)
Forward on voltage
ISD = 6 A, VGS = 0 V
trr
Reverse recovery time
ISD = 6 A, di/dt = 100 A/µs
Qrr
Reverse recovery charge
IRRM
Reverse recovery current
VDD = 60 V (see Figure 15. Test
circuit for inductive load switching and
diode recovery times)
trr
Reverse recovery time
ISD = 6 A, di/dt = 100 A/µs
Qrr
Reverse recovery charge
IRRM
Reverse recovery current
VDD = 60 V, Tj = 150 °C (see Figure
15. Test circuit for inductive load
switching and diode recovery times)
24
-
-
-
Max.
1.6
Unit
A
V
208
ns
1.2
μC
11.5
A
264
ns
1.6
μC
12.5
A
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration = 300 μs, duty cycle 1.5%.
DS10114 - Rev 3
page 4/18
STD9N40M2
Electrical characteristics curves
2.1
Electrical characteristics curves
Figure 2. Thermal impedance
Figure 1. Safe operating area
GIPG050620141120SA
ID
(A)
10
n)
(o
DS
Op
Lim erat
ite ion
d b in
y m this
ax are
R
a
is
10µs
1
100µs
1ms
10ms
Tj=150°C
Tc=25°C
Single pulse
0.1
0.1
1
10
VDS(V)
100
Figure 3. Output characterisics
Figure 4. Transfer characteristics
GIPG050620141141SA
ID (A)
VGS=8, 9, 10V
10
7V
GIPG050620141144SA
ID
(A)
VDS=14V
10
6V
8
8
6
6
5V
4
4
2
2
4V
0
0
4
8
12
16
VDS(V)
Figure 5. Gate charge vs gate-source voltage
GIPG050620141149SA
VDS
VGS
(V)
(V)
VDD=320V
ID=6A
12 VDS
300
0
0
2
4
8
6
10
VGS(V)
Figure 6. Static drain-source on-resistance
GIPG050620141203SA
RDS(on)
(Ω)
VGS=10V
0.62
10
250
8
200
6
150
4
100
2
50
0.58
0
Qg(nC)
0.57
0.61
0.60
0
DS10114 - Rev 3
0
2
4
6
8
0.59
1
2
3
4
5
ID(A)
page 5/18
STD9N40M2
Electrical characteristics curves
Figure 7. Capacitance variations
Figure 8. Output capacitance stored energy
GIPG050620141211SA
C
(pF)
1000
GIPG090620140910SA
Eoss
(µJ)
1.2
Ciss
100
0.8
Coss
10
0.4
1
0.1
0.1
Crss
1
100
10
VDS(V)
Figure 9. Normalized gate threshold voltage vs
temperature
GIPG090620140915SA
VGS(th)
(norm)
VDS(V)
300
Figure 10. Normalized on-resistance vs temperature
GIPG090620140921SA
RDS(on)
(norm)
1.8
1.4
0.9
1
0.8
0.6
0.7
-25
25
75
125
TJ(°C)
Figure 11. Normalized V(BR)DSS vs temperature
GIPG090620141002SA
V(BR)DSS
(norm)
0.2
-75
125
TJ(°C)
GIPG090620141010SA
1
1.00
0.8
0.96
0.7
0.92
0.6
75
75
VSD (V)
0.9
25
25
Figure 12. Source-drain diode forward characteristics
1.04
-25
-25
TJ=-50°C
ID=1mA
1.08
0.88
-75
200
100
VGS=10V
1.0
DS10114 - Rev 3
0
2.2
ID=250µA
1.1
0.6
-75
0
125 TJ(°C)
0.5
TJ=25°C
TJ=150°C
1
2
3
4
5
ISD(A)
page 6/18
STD9N40M2
Test circuits
3
Test circuits
Figure 13. Test circuit for resistive load switching times
Figure 14. Test circuit for gate charge behavior
VDD
12 V
2200
+ μF
3.3
μF
VDD
VD
VGS
1 kΩ
100 nF
RL
IG= CONST
VGS
RG
47 kΩ
+
pulse width
D.U.T.
2.7 kΩ
2200
μF
pulse width
D.U.T.
100 Ω
VG
47 kΩ
1 kΩ
AM01469v1
AM01468v1
Figure 15. Test circuit for inductive load switching and
diode recovery times
D
G
A
D.U.T.
S
25 Ω
A
L
A
B
B
3.3
µF
D
G
+
VD
100 µH
fast
diode
B
Figure 16. Unclamped inductive load test circuit
RG
1000
+ µF
2200
+ µF
VDD
3.3
µF
VDD
ID
D.U.T.
S
D.U.T.
Vi
_
pulse width
AM01471v1
AM01470v1
Figure 18. Switching time waveform
Figure 17. Unclamped inductive waveform
ton
V(BR)DSS
td(on)
VD
toff
td(off)
tr
tf
90%
90%
IDM
VDD
10%
0
ID
VDD
AM01472v1
VGS
0
VDS
10%
90%
10%
AM01473v1
DS10114 - Rev 3
page 7/18
STD9N40M2
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
DS10114 - Rev 3
page 8/18
STD9N40M2
DPAK (TO-252) type A package information
4.1
DPAK (TO-252) type A package information
Figure 19. DPAK (TO-252) type A package outline
0068772_A_25
DS10114 - Rev 3
page 9/18
STD9N40M2
DPAK (TO-252) type A package information
Table 8. DPAK (TO-252) type A mechanical data
Dim.
mm
Min.
Max.
A
2.20
2.40
A1
0.90
1.10
A2
0.03
0.23
b
0.64
0.90
b4
5.20
5.40
c
0.45
0.60
c2
0.48
0.60
D
6.00
6.20
D1
4.95
E
6.40
E1
4.60
4.70
4.80
e
2.159
2.286
2.413
e1
4.445
4.572
4.699
H
9.35
10.10
L
1.00
1.50
(L1)
2.60
2.80
3.00
L2
0.65
0.80
0.95
L4
0.60
R
V2
DS10114 - Rev 3
Typ.
5.10
5.25
6.60
1.00
0.20
0°
8°
page 10/18
STD9N40M2
DPAK (TO-252) type C package information
4.2
DPAK (TO-252) type C package information
Figure 20. DPAK (TO-252) type C package outline
0068772_C_25
DS10114 - Rev 3
page 11/18
STD9N40M2
DPAK (TO-252) type C package information
Table 9. DPAK (TO-252) type C mechanical data
Dim.
mm
Min.
Typ.
Max.
A
2.20
2.30
2.38
A1
0.90
1.01
1.10
A2
0.00
0.10
b
0.72
0.85
b4
5.13
c
0.47
0.60
c2
0.47
0.60
D
6.00
D1
5.25
E
6.50
E1
4.70
e
5.46
6.10
6.20
6.60
6.70
2.186
2.286
2.386
H
9.80
10.10
10.40
L
1.40
1.50
1.70
L1
L2
2.90 REF
0.90
L3
L4
1.25
0.51 BSC
0.60
L6
DS10114 - Rev 3
5.33
0.80
1.00
1.80 BSC
θ1
5°
7°
9°
θ2
5°
7°
9°
V2
0°
8°
page 12/18
STD9N40M2
DPAK (TO-252) type C package information
Figure 21. DPAK (TO-252) recommended footprint (dimensions are in mm)
FP_0068772_25_C
DS10114 - Rev 3
page 13/18
STD9N40M2
DPAK (TO-252) packing information
4.3
DPAK (TO-252) packing information
Figure 22. DPAK (TO-252) tape outline
10 pitches cumulative
tolerance on tape +/- 0.2 mm
T
P0
Top cover
tape
P2
D
E
F
B1
K0
For machine ref. only
including draft and
radii concentric around B0
W
B0
A0
P1
D1
User direction of feed
R
Bending radius
User direction of feed
AM08852v1
DS10114 - Rev 3
page 14/18
STD9N40M2
DPAK (TO-252) packing information
Figure 23. DPAK (TO-252) reel outline
T
40mm min.
access hole
at slot location
B
D
C
N
A
G measured
at hub
Tape slot
in core for
tape start
2.5mm min.width
Full radius
AM06038v1
Table 10. DPAK (TO-252) tape and reel mechanical data
Tape
Dim.
mm
mm
Dim.
Min.
Max.
A0
6.8
7
A
B0
10.4
10.6
B
1.5
12.1
C
12.8
1.6
D
20.2
G
16.4
50
B1
DS10114 - Rev 3
Reel
Min.
Max.
330
13.2
D
1.5
D1
1.5
E
1.65
1.85
N
F
7.4
7.6
T
K0
2.55
2.75
P0
3.9
4.1
Base qty.
2500
P1
7.9
8.1
Bulk qty.
2500
P2
1.9
2.1
R
40
T
0.25
0.35
W
15.7
16.3
18.4
22.4
page 15/18
STD9N40M2
Revision history
Table 11. Document revision history
Date
Version
09-Jan-2014
1
Changes
First release.
– Modified: title
– Modified: values in Table 4
– Modified: RDS(on) and IDSS (test conditions) in Table 5
18-Jun-2014
2
– Modified: the entire typical values in Table 6, 7 and 8
– Added: Table 8
– Added: Section 2.1: Electrical characteristics (curves)
– Updated: Section 4: Package mechanical data
– Minor text changes
The document status is production data.
20-Aug-2018
3
Added Section 4.2 DPAK (TO-252) type C package information.
Minor text changes.
DS10114 - Rev 3
page 16/18
STD9N40M2
Contents
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1
DPAK (TO-252) type A package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
DPAK (TO-252) type C package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3
DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
DS10114 - Rev 3
page 17/18
STD9N40M2
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS10114 - Rev 3
page 18/18
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