STF23N80K5
N-channel 800 V, 0.23
Ω typ., 16 A MDmesh™ K5
Power MOSFET in a TO-220FP package
Datasheet - production data
TO-220FP
Figure 1: Internal schematic diagram
Features
Order code V
DS
R
DS(on)
max. I
D
P
TOT
STF23N80K5 800 V 0.28 Ω 16 A 35 W
Industry’s lowest R
DS(on)
x area
Industry’s best figure of merit (FoM)
Ultra low gate charge
100% avalanche tested
Zener-protected
Applications
Switching applications
Description
This very high voltage N-channel Power
MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency.
Order code
STF23N80K5
Table 1: Device summary
Marking Package
23N80K5 TO-220FP
Packing
Tube
August 2015 DocID028292 Rev 1
This is information on a product in full production.
1/13 www.st.com
Contents
Contents
STF23N80K5
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
TO-220FP package information ...................................................... 10
5 Revision history ............................................................................ 12
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STF23N80K5
1
Electrical ratings
Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
GS
I
D
I
DM
(1)
P
TOT
dv/dt (2) dv/dt (3)
V
ISO
T stg
T j
Gate-source voltage
Drain current (continuous) at T case
= 25 °C
Drain current (continuous) at T case
= 100 °C
Drain current (pulsed)
Total dissipation at T case
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Insulation withstand voltage (RMS) from all three leads to external heat sink (t=1 s;T
C
= 25 °C)
Storage temperature
Operating junction temperature
Value
±30
16
10
64
35
4.5
50
2500
-55 to 150
Notes:
(1)
Pulse width is limited by safe operating area.
(2)
I
SD
≤ 16 A, di/dt=100 A/μs; V
DS
peak < V
(BR)DSS
, V
DD
= 80% V
(BR)DSS
.
(3)
V
DS
≤ 640 V
Symbol
Table 3: Thermal data
Parameter
R thj-case
R thj-amb
Thermal resistance junction-case
Thermal resistance junction-ambient
Symbol
I
AR
(1)
E
AS
(2)
Table 4: Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive
Single pulse avalanche energy
Notes:
(1)
Pulse width limited by T jmax
.
(2)
starting T j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V.
Value
3.6
62.5
Value
5
400
V
°C
Unit
°C/W
Unit
A mJ
Unit
V
A
A
W
V/ns
DocID028292 Rev 1 3/13
Electrical characteristics
2
4/13
STF23N80K5
Electrical characteristics
(T case
= 25 °C unless otherwise specified)
Symbol Parameter
Table 5: Static
Test conditions
V
(BR)DSS
I
DSS
I
GSS
Drain-source breakdown voltage
V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 800 V
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 800 V,
T case
= 125 °C
Gate-body leakage current V
DS
= 0 V, V
GS
= ±20 V
V
DS
= V
GS
, I
D
= 100 µA V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source onresistance
V
GS
= 10 V, I
D
= 8 A
Symbol Parameter
Table 6: Dynamic
Test conditions
C iss
C oss
C rss
C
O(tr)
(1)
C
O(er)
(2)
R
G
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent output capacitance
Equivalent output capacitance
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
V
DS
= 0 to 640 V, V
GS
= 0 V
V
DS
= 0 to 640 V, V
GS
= 0 V f = 1 MHz, I
D
= 0 A
V
DD
= 640 V, I
D
= 16 A,
V
GS
= 10 V (see Figure 14:
"Test circuit for gate charge behavior" )
Min. Typ. Max. Unit
800 V
1
µA
50
4
±10 µA
5 V
0.23 0.28 Ω
3
Min. Typ. Max. Unit
-
-
1000
65
-
- pF
- 1.5 -
-
-
-
-
-
-
165
59
4.7
33
6
25
-
-
-
-
-
- pF
Ω nC
Notes:
(1)
Time related is defined as a constant equivalent capacitance giving the same charging time as C
OSS
when V
DS increases from 0 to 80% V
DSS
.
(2)
Energy related is defined as a constant equivalent capacitance giving the same stored energy as C
OSS
when
V
DS
increases from 0 to 80% V
DSS
Symbol Parameter
Table 7: Switching times
Test conditions Min. Typ. Max. Unit t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time t f
Fall time
V
DD
= 400 V, I
D
= 8 A
R
G
= 4.7
Ω, V
GS
= 10 V (see
Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform" )
-
-
-
-
14
9
48
9
-
-
-
- ns
DocID028292 Rev 1
STF23N80K5
Symbol
I
SD
Source-drain current
I
SDM
(1)
Source-drain current
(pulsed)
V
SD
(2)
Forward on voltage t rr
Q rr
Reverse recovery time
Reverse recovery charge
I
I
RRM t
Q rr rr
RRM
Parameter
Reverse recovery current
Reverse recovery time
Table 8: Source-drain diode
Test conditions
Reverse recovery charge
Reverse recovery current
V
GS
= 0 V, I
SD
= 16 A
I
SD
= 16 A, di/dt = 100 A/µs,
V
DD
= 60 V (see Figure 15:
"Test circuit for inductive load switching and diode recovery times" )
I
SD
= 16 A, di/dt = 100 A/µs,
V
DD
= 60 V, T j
= 150 °C (see
Figure 15: "Test circuit for inductive load switching and diode recovery times" )
Electrical characteristics
Min. Typ. Max. Unit
- 16 A
- 64 A
-
-
-
410
7
1.5 V ns
µC
-
-
-
-
34
650
10
32
A ns
µC
A
Notes:
(1)
Pulse width is limited by safe operating area.
(2)
Pulse test: pulse duration = 300 µs, duty cycle 1.5%.
Symbol
Table 9: Gate-source Zener diode
Parameter Test conditions Min. Typ. Max. Unit
V
(BR)GSO
Gate-source breakdown voltage I
GS
= ±1 mA, I
D
= 0 A ±30 - - V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry.
DocID028292 Rev 1 5/13
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STF23N80K5
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
6/13 DocID028292 Rev 1
STF23N80K5
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs temperature
Figure 10: Normalized on-resistance vs temperature
Figure 11: Normalized V(BR)DSS vs temperature
Figure 12: Maximum avalanche energy vs temperature
DocID028292 Rev 1 7/13
Test circuits
3 Test circuits
Figure 13: Test circuit for resistive load switching times
STF23N80K5
Figure 14: Test circuit for gate charge behavior
Figure 15: Test circuit for inductive load switching and diode recovery times
Figure 16: Unclamped inductive load test circuit
Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform
8/13 DocID028292 Rev 1
STF23N80K5
4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
DocID028292 Rev 1 9/13
Package information
4.1 TO-220FP package information
Figure 19: TO-220FP package outline
STF23N80K5
10/13 DocID028292 Rev 1
STF23N80K5
Dim.
G1
H
L2
L3
L4
L5
L6
L7
Dia
F
F1
F2
G
A
B
D
E
Table 10: TO-220FP package mechanical data mm
Min. Typ.
Package information
Max.
4.4
2.5
2.5
0.45
0.75
1.15
1.15
4.95
2.4
10
16
4.6
2.7
2.75
0.7
1
1.70
1.70
5.2
2.7
10.4
28.6
9.8
2.9
15.9
9
3
30.6
10.6
3.6
16.4
9.3
3.2
DocID028292 Rev 1 11/13
Revision history
5
STF23N80K5
Revision history
Date
28-Aug-2015
Table 11: Document revision history
Revision
1
Changes
First release.
12/13 DocID028292 Rev 1
STF23N80K5
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