G(1)
STFI12N60M2
N-channel 600 V, 0.
395 Ω typ., 9 A MDmesh™ M2
Power MOSFET in an I²PAKFP package
Datasheet - production data
Figure 1: Internal schematic diagram
D(2)
Features
Order code
STFI12N60M2
V
DS
R
DS(on)
max. I
D
P
TOT
600 V 0.
450 Ω
9 A 25 W
•
Extremely low gate charge
•
Excellent output capacitance (C
OSS
) profile
•
100% avalanche tested
•
Zener-protected
Applications
•
Switching applications
Description
This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology.
Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters.
Order code
STFI12N60M2
S(3)
AM15572v1_no_tab
Table 1: Device summary
Marking Package
12N60M2 I²PAKFP
Packing
Tube
May 2015 DocID027899 Rev 1
This is information on a product in full production.
1/12 www.st.com
Contents
Contents
STFI12N60M2
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
I²PAKFP (TO-281) package information ........................................... 9
5 Revision history ............................................................................ 11
2/12 DocID027899 Rev 1
STFI12N60M2
1
Electrical ratings
Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
GS
I
D
(1)
I
DM
(2)
P
TOT
dv/dt
(3) dv/dt
(4)
V
ISO
T stg
T j
Gate-source voltage
Drain current (continuous) at T case
= 25 °C
Drain current (continuous) at T case
= 100 °C
Drain current (pulsed)
Total dissipation at T case
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; T
C
= 25 °C)
Storage temperature
Operating junction temperature
Notes:
(1)
Limited by maximum junction temperature.
(2)
Pulse width is limited by safe operating area.
(3)
I
SD
≤ 9 A, di/dt=400 A/μs; V
DS(peak)
< V
(BR)DSS
, V
DD
= 80% V
(BR)DSS
.
(4)
V
DS
≤ 480 V.
Symbol
Table 3: Thermal data
Parameter
R thj-case
R thj-amb
Thermal resistance junction-case
Thermal resistance junction-ambient
Symbol
I
AR
(1)
E
AR
(2)
Table 4: Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive
Single pulse avalanche energy
Notes:
(1)
Pulse width limited by T jmax
.
(2)
starting T j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V.
-55 to 150
Value
5
62.5
Value
2.6
117
Value
±25
9
5.7
36
25
15
50
2.5 kV
°C
Unit
°C/W
Unit
A mJ
Unit
V
A
A
W
V/ns
DocID027899 Rev 1 3/12
Electrical characteristics
2 Electrical characteristics
(T case
= 25 °C unless otherwise specified)
Symbol Parameter
Table 5: Static
Test conditions
V
(BR)DSS
Drain-source breakdown voltage
V
GS
= 0 V, I
D
= 1 mA
I
DSS
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 600 V
V
GS
= 0 V, V
DS
= 600 V,
T case
= 125 °C
I
GSS
Gate-body leakage current
V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source onresistance
V
DS
= 0 V, V
GS
= ±25 V
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 4.5 A
Table 6: Dynamic
Test conditions Symbol
C iss
C oss
C rss
C
oss eq.
(1)
R
G
Q g
Q gs
Q gd
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent output capacitance
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
V
DS
= 0 to 480 V, V
GS
= 0 V f = 1 MHz, I
D
= 0 A
V
DD
= 400 V, I
D
= 9 A,
V
GS
= 10 V (see Figure 15:
"Gate charge test circuit" )
STFI12N60M2
Min. Typ. Max. Unit
600 V
1
µA
100
±10 µA
3 4 V
0.395 0.450
Ω
2
Min. Typ. Max. Unit
-
-
538
29
-
- pF
- 1.1 -
-
-
-
-
-
106
7
16
2.3
8.5
-
-
-
-
- pF
Ω nC
Notes:
(1)
C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS increases from 0 to 80% V
DSS
.
Symbol Parameter
Table 7: Switching times
Test conditions Min. Typ. Max. Unit t d(on) t r t d(off) t f
Turn-on delay time
Rise time
Turn-off delay time
Fall time
V
DD
= 300 V, I
D
= 4.5 A
R
G
= 4.7
Ω, V
GS
= 10 V (see
Figure 14: "Switching times test circuit for resistive load" and Figure 19: "Switching time waveform" )
-
-
-
-
9.2
9.2
56
18
-
-
-
- ns
4/12 DocID027899 Rev 1
STFI12N60M2
Symbol Parameter
Table 8: Source-drain diode
Test conditions
I
SD
Source-drain current
I
SDM
(1)
Source-drain current
(pulsed)
V
SD
(2)
Forward on voltage t rr
Q rr
Reverse recovery time
Reverse recovery charge
I
I
RRM t
Q rr rr
RRM
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
V
GS
= 0 V, I
SD
= 9 A
I
SD
= 9 A, di/dt = 100 A/µs,
V
DD
= 60 V (see Figure 16:
"Test circuit for inductive load switching and diode recovery times" )
I
SD
= 9 A, di/dt = 100 A/µs,
V
DD
= 60 V, T j
= 150 °C (see
Figure 16: "Test circuit for inductive load switching and diode recovery times" )
Electrical characteristics
Min. Typ. Max. Unit
- 9 A
- 36 A
-
-
-
284
2.4
1.6 V ns
µC
-
-
-
-
17
404
3.5
17.5
A ns
µC
A
Notes:
(1)
Pulse width is limited by safe operating area.
(2)
Pulse test: pulse duration = 300 µs, duty cycle 1.5%.
DocID027899 Rev 1 5/12
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STFI12N60M2
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
6/12 DocID027899 Rev 1
STFI12N60M2
Figure 8: Capacitance variations
Figure 10: Normalized on-resistance vs temperature
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs temperature
AM03184v1 V
GS(th)
(norm)
1.10
1.00
I
D
= 250 µA
0.90
0.80
0.70
-50 0 50 100 T j
(°C)
Figure 11: Normalized V(BR)DSS vs temperature
Figure 12: Output capacitance stored energy
Figure 13: Source- drain diode forward characteristics
V
SD
(V)
GIPG290120151002ALS
1.1
1.0
T j
= -50 °C
T j
= -25 °C
0.9
T j
= 150 °C
0.8
0.7
0.6
0.5
0 4 8 12 16 I
SD
(A)
DocID027899 Rev 1 7/12
Test circuits
3 Test circuits
Figure 14: Switching times test circuit for resistive load
STFI12N60M2
Figure 15: Gate charge test circuit
Figure 16: Test circuit for inductive load switching and diode recovery times
Figure 17: Unclamped inductive load test circuit
Figure 18: Unclamped inductive waveform
Figure 19: Switching time waveform
8/12 DocID027899 Rev 1
STFI12N60M2
4
4.1
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
I²PAKFP (TO-281) package information
Figure 20: I²PAKFP (TO-281) package outline
DocID027899 Rev 1
8291506 Re v. C
9/12
Package information
Dim.
H
L1
L2
L3
L4
L5
L6
E
F
F1
G
A
B
D
D1
Table 9: I²PAKFP (TO-281) mechanical data mm
Min. Typ.
4.40
2.50
2.50
0.65
0.45
0.75
-
4.95
10.00
21.00
13.20
10.55
2.70
0.85
7.50 7.60
STFI12N60M2
Max.
10.40
23.00
14.10
10.85
3.20
1.25
7.70
4.60
2.70
2.75
0.85
0.70
1.00
1.20
5.20
10/12 DocID027899 Rev 1
STFI12N60M2
5
Revision history
Revision history
Date
22-May-2015
Table 10: Document revision history
Revision
1
Changes
First release.
DocID027899 Rev 1 11/12
STFI12N60M2
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