STFI26NM60N
Nchannel 600 V, 0.135 Ω typ., 20 A MDmesh™ II
Power MOSFET in an I²PAKFP package
Datasheet - production data
1 2
3
I 2 PAKFP
(TO-281)
Figure 1: Internal schematic diagram
D(2)
G(1)
Features
Order code V
DS
R
DS(on) max I
D
STFI26NM60N 600 V 0.165 Ω 20 A
Fully insulated and low profile package with increased creepage path from pin to heatsink plate
100% avalanche tested
Low input capacitance and gate charge
Low gate input resistance
Applications
Switching applications
Description
This device is an N-channel Power MOSFET developed using the second generation of
MDmesh™ technology. This revolutionary Power
MOSFET associates a vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters.
S(3)
Order code
STFI26NM60N
AM01475v1_no Tab_noZen
Table 1: Device summary
Marking Package
26NM60N I²PAKFP (TO-281)
Packaging
Tube
December 2016 DocID022495 Rev 4
This is information on a product in full production.
1/12 www.st.com
Contents
Contents
STFI26NM60N
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
I²PAKFP package information ........................................................... 9
5 Revision history ............................................................................ 11
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STFI26NM60N
1 Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
DS
Drain-source voltage
V
GS
I
D
(1)
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
I
D
(1)
Drain current (continuous) at T
C
= 100 °C
I
DM
(1)(2)
Drain current (pulsed)
P
TOT
Total dissipation at T
C
= 25 °C
dv/dt (3)
Peak diode recovery voltage slope
V
T
ISO stg
Insulation withstand voltage (RMS) from all three leads to external heat sink
(t = 1 s; T
C
= 25 °C)
Storage temperature range
T j
Operating junction temperature range
Notes:
(1)
Limited by package.
(2)
Pulse width limited by safe operating area.
(3)
I
SD
≤ 20 A, di/dt ≤ 400 A/µs, V
DS(peak)
≤ V
(BR)DSS,
V
DD
≤ 80% V
(BR)DSS
Symbol
Table 3: Thermal data
Parameter
R thj-case
Thermal resistance junction-case
R thj-amb
Thermal resistance junction-ambient
Symbol
Table 4: Avalanche characteristics
Parameter
I
AS
E
AS
Single pulse avalanche current (pulse width limited by T jmax
)
Single pulse avalanche energy
(starting T
J
=25 °C, I
D
=I
AS
, V
DD
=50 V)
Electrical ratings
Value
600
±30
20
12.6
80
35
15
2500
Unit
V
V
A
A
A
W
V/ns
V
-55 to 150 °C
Value
3.6
62.5
Unit
°C/W
°C/W
Value
6
610
Unit
A mJ
DocID022495 Rev 4 3/12
Electrical characteristics
2 Electrical characteristics
(T
CASE
= 25 °C unless otherwise specified)
Symbol Parameter
Table 5: On/off states
Test conditions
V
(BR)DSS
I
DSS
Drain-source breakdown voltage
I
D
= 1 mA, V
GS
= 0 V
V
GS
= 0 V, V
DS
= 600 V
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 600 V,
T
C
= 125 °C (1)
Gate-body leakage current V
DS
= 0 V, V
GS
= ±25 V I
GSS
V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source onresistance
V
V
DS
GS
= V
GS
, I
D
= 10 V, I
= 250 µA
D
= 10 A
STFI26NM60N
Min. Typ. Max. Unit
600 V
1
µA
100
3
±0.1 µA
4 V
0.135 0.165 Ω
2
Notes:
(1)
Defined by design, not subject to production test.
Symbol Parameter
Table 6: Dynamic
Test conditions
C iss
C oss
C rss
C
oss eq.
(1)
Q g
Q gs
Q gd
R
G
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent output capacitance
Total gate charge
Gate-source charge
Gate-drain charge
Gate input resistance
V
DS
= 50 V, f = 1 MHz,
V
GS
= 0 V
V
GS
= 0 V, V
DS
= 0 to 480 V
V
DD
= 480 V, I
D
= 20 A,
V
GS
= 10 V
(see Figure 14: "Test circuit for gate charge behavior" )
f=1 MHz, I
D
=0 A
Min. Typ. Max. Unit
-
-
1800
115
-
- pF pF
-
-
-
-
-
-
6
310
60
8.5
30
2.8
-
-
-
-
-
- pF pF nC nC nC
Ω
Notes:
(1)
C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS increases from 0 to 80% V
DS
Symbol Parameter
Table 7: Switching times
Test conditions Min. Typ. Max. Unit t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time t f
Fall time
V
DD
= 300 V, I
D
= 10 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform" )
-
-
-
-
13
25
85
50
-
-
-
- ns ns ns ns
4/12 DocID022495 Rev 4
STFI26NM60N
Symbol Parameter
I
SD
(1)
Source-drain current
I
SDM
(2)
Source-drain current
(pulsed)
V
SD
(3)
Forward on voltage t rr
Q rr
Reverse recovery time
Reverse recovery charge
I
I
RRM t
Q rr rr
RRM
Table 8: Source-drain diode
Test conditions
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
I
SD
SD
= 20 A, V
GS
= 0 V
= 20 A, di/dt = 100 A/µs
V
DD
= 60 V
(see Figure 15: "Test circuit for inductive load switching and diode recovery times" )
I
SD
= 20 A, di/dt = 100 A/µs
V
DD
= 60 V, T j
= 150 °C
(see Figure 15: "Test circuit for inductive load switching and diode recovery times" )
Electrical characteristics
Min. Typ. Max. Unit
-
-
-
-
-
-
-
-
-
370
5.8
31.6
450
7.5
32.5
20
80
1.5
A
A
V ns
µC
A ns
µC
A
Notes:
(1)
Limited by package.
(2)
Pulse width limited by safe operating area.
(3)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
DocID022495 Rev 4 5/12
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STFI26NM60N
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
W
6/12 DocID022495 Rev 4
STFI26NM60N
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Source-drain diode forward characteristics
Figure 10: Normalized gate threshold voltage vs temperature
Figure 11: Normalized on-resistance vs temperature
Figure 12: Normalized V
(BR)DSS
vs temperature
DocID022495 Rev 4 7/12
Test circuits
3 Test circuits
Figure 13: Test circuit for resistive load switching times
STFI26NM60N
Figure 14: Test circuit for gate charge behavior
Figure 15: Test circuit for inductive load switching and diode recovery times
Figure 16: Unclamped inductive load test circuit
Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform
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STFI26NM60N
4
4.1
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
I²PAKFP package information
Figure 19: I²PAKFP (TO-281) package outline
DocID022495 Rev 4
8291506 Re v. C
9/12
Package information
Dim.
H
L1
L2
L3
L4
L5
L6
E
F
F1
G
A
B
D
D1
Table 9: I²PAKFP (TO-281) mechanical data mm
Min. Typ.
4.40
2.50
2.50
0.65
0.45
0.75
4.95
10.00
21.00
13.20
10.55
2.70
0.85
7.50 7.60
STFI26NM60N
Max.
10.40
23.00
14.10
10.85
3.20
1.25
7.70
4.60
2.70
2.75
0.85
0.70
1.00
1.20
5.20
10/12 DocID022495 Rev 4
STFI26NM60N
5
Revision history
Revision history
Date Revision
Table 10: Document revision history
Changes
15-Nov-2011
04-Jun-2012
10-Jun-2015
13-Dec-2016
1
2
3
4
First release.
Document status promoted from preliminary data to production data.
Updated P
TOT
and Derating factor values in Table 2: Absolute maximum ratings , R th-case
value in Table 3: Thermal data Package name has been updated.
Updated Section 4: Package information.
Minor text changes.
Modified Table 2: "Absolute maximum ratings" ,
Table 5: "On/off states" ,
Table 6: "Dynamic"
and Table 8: "Source-drain diode"
Modified Section 2.1: "Electrical characteristics (curves)"
Minor text changes
DocID022495 Rev 4 11/12
STFI26NM60N
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12/12 DocID022495 Rev 4
