STD60NF55LAT4
Automotive-grade Nchannel 55 V, 12 mΩ typ., 60 A
STripFET™ II Power MOSFET in a DPAK package
Datasheet - production data
Figure 1: Internal schematic diagram
D(2, TAB)
G(1)
Features
Order code V
DS
STD60NF55LAT4 55 V
AEC-Q101 qualified
Low threshold drive
R
DS(on) max
15 mΩ
I
D
60 A
Applications
Switching applications
Description
This Power MOSFET series realized with
STMicroelectronics unique STripFET™ process is specifically designed to minimize input capacitance and gate charge. It is therefore ideal as a primary switch in advanced high-efficiency isolated DC-DC converters for Telecom and
Computer applications. It is also suitable for any application with low gate charge drive requirements.
S(3)
Order code
STD60NF55LAT4
AM01475v1_noZen
Table 1: Device summary
Marking Package
D60NF55LA DPAK
Packing
Tape and reel
February 2017 DocID030283 Rev 1
This is information on a product in full production.
1/16 www.st.com
Contents
Contents
STD60NF55LAT4
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
4.2
DPAK (TO-252) type A2 package information................................. 10
DPAK (TO-252) packing information ............................................... 13
5 Revision history ............................................................................ 15
2/16 DocID030283 Rev 1
STD60NF55LAT4
1 Electrical ratings
Symbol
V
DS
V
GS
I
D
I
DM
(1)
P
TOT
dv/dt (2)
E
AS
(3)
T stg
T
J
Table 2: Absolute maximum ratings
Parameter
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
Single pulse avalanche energy
Storage temperature range
Operating junction temperature range
Notes:
(1)
Pulse width is limited by safe operating area.
(2)
I
SD
≤ 40A, di/dt ≤ 350 A/μs, V
DD
≤ V
(BR)DSS
, T
J
≤ T
JMAX
(3)
Starting T
J
= 25 °C, I
D
= 17.5 A, V
DD
= 24 V
Symbol
Table 3: Thermal data
Parameter
R thj-case
R
thj-pcb
(1)
Thermal resistance junction-case
Thermal resistance junction-pcb
Notes:
(1)
When mounted on a 1-inch² FR-4, 2 Oz copper board.
Electrical ratings
Value
55
±15
60
42
240
110
16
400
-55 to 175
Unit
V
V
A
A
W
V/ns mJ
°C
Value
1.36
50
Unit
°C/W
°C/W
DocID030283 Rev 1 3/16
Electrical characteristics
2 Electrical characteristics
(T case
= 25 °C unless otherwise specified)
Symbol Parameter
Table 4: Static
Test conditions
V
(BR)DSS
I
DSS
Drain-source breakdown voltage
I
GSS
V
GS(th)
Gate threshold voltage
V
GS
= 0 V, I
D
= 250 µA
V
GS
= 0 V, V
DS
= 55 V
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 55 V,
T
C
= 125 °C (1)
Gate-body leakage current V
DS
= 0 V, V
GS
= ±15 V
R
DS(on)
Static drain-source on-resistance
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 30 A
V
GS
= 5 V, I
D
= 30 A
STD60NF55LAT4
Min. Typ. Max. Unit
55
1
10
V
µA
1
12
14
±100 nA
2
15
17
V mΩ
Notes:
(1)
Defined by design, not subject to production test.
Symbol Parameter
Table 5: Dynamic
Test conditions
C iss
C oss
C rss
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 25 V, f = 1 MHz,
V
GS
= 0 V
V
DD
= 40 V, I
D
= 60 A,
V
GS
= 0 to 5 V, R
G
= 4.7 Ω
(see Figure 13: "Test circuit for gate charge behavior" )
Min. Typ. Max. Unit
1950
390
- - pF
130
-
40
10
20
- nC
4/16 DocID030283 Rev 1
STD60NF55LAT4
Symbol Parameter t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time t f
Fall time
Table 6: Switching times
Test conditions
V
DD
= 25 V, I
D
= 30 A,
R
G
= 4.7 Ω, V
GS
= 4.5 V
(see Figure 12: "Test circuit for resistive load switching times" and Figure 17: "Switching time waveform" )
Electrical characteristics
Min. Typ. Max. Unit
-
30
180
80
35
- ns
Symbol
I
SD
Source-drain current
I
SDM
(1)
Source-drain current
(pulsed)
V
SD
(2)
Forward on voltage t rr
Q rr
Reverse recovery time
Reverse recovery charge
I
RRM
Parameter
Table 7: Source-drain diode
Test conditions
Reverse recovery current
V
GS
= 0 V, I
SD
= 60 A
I
SD
= 40 A, di/dt = 100 A/µs,
V
DD
= 25 V, T
J
= 150 °C
(see Figure 14: "Test circuit for inductive load switching and diode recovery times"
Min. Typ. Max. Unit
- 60 A
- 240 A
-
-
-
65
130
1.3 V ns nC
- 4 A
Notes:
(1)
Pulse width is limited by safe operating area.
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
DocID030283 Rev 1 5/16
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STD60NF55LAT4
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
6/16
Figure 6: Source-drain diode forward characteristics
Figure 7: Static drain-source on-resistance
DocID030283 Rev 1
STD60NF55LAT4
Figure 8: Gate charge vs gate-source voltage
Electrical characteristics
Figure 9: Capacitance variations
Figure 10: Normalized gate threshold voltage vs temperature
Figure 11: Normalized on-resistance vs temperature
DocID030283 Rev 1 7/16
Test circuits
3 Test circuits
Figure 12: Test circuit for resistive load switching times
STD60NF55LAT4
Figure 13: Test circuit for gate charge behavior
Figure 14: Test circuit for inductive load switching and diode recovery times
Figure 15: Unclamped inductive load test circuit
Figure 16: Unclamped inductive waveform Figure 17: Switching time waveform
8/16 DocID030283 Rev 1
STD60NF55LAT4
4 Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
DocID030283 Rev 1 9/16
Package information
4.1 DPAK (TO-252) type A2 package information
Figure 18: DPAK (TO-252) type A2 package outline
STD60NF55LAT4
10/16 DocID030283 Rev 1
0068772_type-A2_rev21
STD60NF55LAT4
Dim.
D1
E
E1 e e1
H
L
L1
L2
L4
R
V2 b4 c c2
D
A
A1
A2 b
Package information
Table 8: DPAK (TO-252) type A2 mechanical data mm
Min. Typ. Max.
4.95
6.40
5.10
2.16
4.40
9.35
1.00
2.20
0.90
0.03
0.64
5.20
0.45
0.48
6.00
2.60
0.65
0.60
0°
5.10
5.20
2.28
2.80
0.80
0.20
5.25
6.60
5.30
2.40
4.60
10.10
1.50
2.40
1.10
0.23
0.90
5.40
0.60
0.60
6.20
3.00
0.95
1.00
8°
DocID030283 Rev 1 11/16
Package information STD60NF55LAT4
Figure 19: DPAK (TO-252) type A2 recommended footprint (dimensions are in mm)
12/16 DocID030283 Rev 1
STD60NF55LAT4
4.2 DPAK (TO-252) packing information
Figure 20: DPAK (TO-252) tape outline
Package information
DocID030283 Rev 1 13/16
Package information
Figure 21: DPAK (TO-252) reel outline
STD60NF55LAT4
14/16
Dim.
F
K0
P0
P1
P2
R
T
W
A0
B0
B1
D
D1
E
7.9
1.9
40
0.25
15.7
1.5
1.5
1.65
7.4
2.55
3.9
Table 9: DPAK (TO-252) tape and reel mechanical data
Tape Reel mm
Dim.
Min.
6.8
10.4
Max.
7
10.6
12.1
1.6
1.85
7.6
2.75
4.1
8.1
2.1
A
B
C
D
G
N
T
Base qty.
Bulk qty.
Min.
1.5
12.8
20.2
16.4
50
0.35
16.3 mm
Max.
330
13.2
18.4
22.4
2500
2500
DocID030283 Rev 1
STD60NF55LAT4
5 Revision history
Date Revision
Table 10: Document revision history
Changes
09-Feb-2017 1 First release
Revision history
DocID030283 Rev 1 15/16
STD60NF55LAT4
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics
– All rights reserved
16/16 DocID030283 Rev 1
