STD47N10F7AG
Automotive-grade Nchannel 100 V, 12.5 mΩ typ., 45 A,
STripFET™ F7 Power MOSFET in a DPAK package
Datasheet - production data
Figure 1: Internal schematic diagram
G(1)
D(2, TAB)
S(3)
Order code
STD47N10F7AG
Features
Order code V
DS
R
DS(on) max.
I
D
P
TOT
STD47N10F7AG 100 V 18 mΩ 45 A 60 W
AEC-Q101 qualified
Among the lowest R
Excellent FoM (figure of merit)
Low C rss
DS(on)
on the market
/C iss
ratio for EMI immunity
High avalanche ruggedness
Applications
Switching applications
Description
This N-channel Power MOSFET utilizes
STripF ET™ F7 technology with an enhanced trench gate structure that results in very low on-state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching.
AM01475v1_noZen
Table 1: Device summary
Marking Package
47N10F7 DPAK
Packing
Tape and reel
February 2017 DocID027183 Rev 3
This is information on a product in full production.
1/16 www.st.com
Contents
Contents
STD47N10F7AG
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
4.2
DPAK (TO-252) type A2 package information................................. 10
DPAK (TO-252) packing information ............................................... 13
5 Revision history ............................................................................ 15
2/16 DocID027183 Rev 3
STD47N10F7AG
1 Electrical ratings
Symbol
V
DS
V
GS
I
D
I
DM
(1)
P
TOT
T
J
T stg
Table 2: Absolute maximum ratings
Parameter
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Operating junction temperature range
Storage temperature range
Notes:
(1)
Pulse width is limited by safe operating area
Symbol
Table 3: Thermal data
Parameter
R thj-case
Thermal resistance junction-case
R
thj-pcb
(1)
Thermal resistance junction-pcb
Notes:
(1)
When mounted on a 1-inch² FR-4, 2 Oz copper board.
Electrical ratings
Value
100
±20
45
32
180
60
-55 to 175
Unit
V
V
A
A
W
°C
°C
Value
2.5
50
Unit
°C/W
DocID027183 Rev 3 3/16
Electrical characteristics
2 Electrical characteristics
(T case
= 25 °C unless otherwise specified)
Symbol Parameter
Table 4: Static
Test conditions
V
(BR)DSS
Drain-source breakdown voltage
V
GS
= 0 V, I
D
= 1 mA
I
DSS
Zero gate voltage drain current
I
GSS
Gate-body leakage current
V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source on-resistance
V
GS
= 0 V, V
DS
= 100 V
V
GS
= 0 V, V
DS
= 100 V,
T
C
= 125 °C (1)
V
DS
= 0 V, V
GS
= ±20 V
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 22.5 A
Notes:
(1)
Defined by design, not subject to production test.
Symbol Parameter
Table 5: Dynamic
Test conditions
C iss
C oss
C rss
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 50 V, f = 1 MHz,
V
GS
= 0 V
V
DD
= 50 V, I
D
= 45 A,
V
GS
= 0 to 10 V
(see Figure 14: "Test circuit for gate charge behavior" )
STD47N10F7AG
Min. Typ. Max. Unit
100 V
10
µA
100
±100 nA
4.5 V
12.5 18 mΩ
2.5
Min. Typ. Max. Unit
-
-
-
-
-
1640
360
25
25
5.1
-
-
-
-
- pF pF pF nC nC
- 12.2 - nC
4/16 DocID027183 Rev 3
STD47N10F7AG
Symbol Parameter t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time t f
Fall time
Table 6: Switching times
Test conditions
V
DD
= 50 V, I
D
= 22.5 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform" )
Electrical characteristics
Min. Typ. Max. Unit
-
-
-
-
15
17
24
8
-
-
-
- ns ns ns ns
Symbol
I
SD
Source-drain current
I
SDM
(1)
Source-drain current
(pulsed)
V
SD
(2)
Forward on voltage t rr
Q rr
Reverse recovery time
Reverse recovery charge
I
RRM
Parameter
Table 7: Source-drain diode
Test conditions
Reverse recovery current
V
GS
= 0 V, I
SD
= 45 A
I
SD
= 45 A, di/dt = 100 A/µs,
V
DD
= 80 V, T
J
= 150 °C
(see Figure 15: "Test circuit for inductive load switching and diode recovery times" )
Min. Typ. Max. Unit
- 45 A
- 180 A
-
-
-
53
67
1.1 V ns nC
- 2.5 A
Notes:
(1)
Pulse width is limited by safe operating area.
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
DocID027183 Rev 3 5/16
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STD47N10F7AG
Figure 3: Thermal impedance d
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage
GIPD09062015RV
Figure 7: Static drain-source on-resistance
6/16 DocID027183 Rev 3
STD47N10F7AG
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs temperature
Figure 10: Normalized on-resistance vs temperature Figure 11: Source-drain diode forward characteristics
Figure 12: Normalized V
(BR)DSS
vs temperature
DocID027183 Rev 3 7/16
Test circuits
3 Test circuits
Figure 13: Test circuit for resistive load switching times
STD47N10F7AG
Figure 14: Test circuit for gate charge behavior
Figure 15: Test circuit for inductive load switching and diode recovery times
Figure 16: Unclamped inductive load test circuit
Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform
8/16 DocID027183 Rev 3
STD47N10F7AG
4 Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
DocID027183 Rev 3 9/16
Package information
4.1 DPAK (TO-252) type A2 package information
Figure 19: DPAK (TO-252) type A2 package outline
STD47N10F7AG
10/16 DocID027183 Rev 3
0068772_type-A2_rev21
STD47N10F7AG
Dim.
D1
E
E1 e e1
H
L
L1
L2
L4
R
V2 b4 c c2
D
A
A1
A2 b
Package information
Table 8: DPAK (TO-252) type A2 mechanical data mm
Min. Typ. Max.
4.95
6.40
5.10
2.16
4.40
9.35
1.00
2.20
0.90
0.03
0.64
5.20
0.45
0.48
6.00
2.60
0.65
0.60
0°
5.10
5.20
2.28
2.80
0.80
0.20
5.25
6.60
5.30
2.40
4.60
10.10
1.50
2.40
1.10
0.23
0.90
5.40
0.60
0.60
6.20
3.00
0.95
1.00
8°
DocID027183 Rev 3 11/16
Package information STD47N10F7AG
Figure 20: DPAK (TO-252) type A2 recommended footprint (dimensions are in mm)
12/16 DocID027183 Rev 3
STD47N10F7AG
4.2 DPAK (TO-252) packing information
Figure 21: DPAK (TO-252) tape outline
Package information
DocID027183 Rev 3 13/16
Package information
Figure 22: DPAK (TO-252) reel outline
STD47N10F7AG
14/16
Dim.
F
K0
P0
P1
P2
R
T
W
A0
B0
B1
D
D1
E
7.9
1.9
40
0.25
15.7
1.5
1.5
1.65
7.4
2.55
3.9
Table 9: DPAK (TO-252) tape and reel mechanical data
Tape Reel mm
Dim.
Min.
6.8
10.4
Max.
7
10.6
12.1
1.6
1.85
7.6
2.75
4.1
8.1
2.1
A
B
C
D
G
N
T
Base qty.
Bulk qty.
Min.
1.5
12.8
20.2
16.4
50
0.35
16.3 mm
Max.
330
13.2
18.4
22.4
2500
2500
DocID027183 Rev 3
STD47N10F7AG
5
Revision history
Revision history
Date Revision
Table 10: Document revision history
Changes
23-Feb-2015
17-Jun-2015
01-Feb-2017
1
2
3
First release
Updated Section 4: Package mechanical data .
Minor text changes
Updated title and features on cover page.
Updated Section 1: "Electrical ratings"
and Section 2: "Electrical characteristics" .
Minor text changes
DocID027183 Rev 3 15/16
STD47N10F7AG
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics
– All rights reserved
16/16 DocID027183 Rev 3
