ESDALC5-1BM2, ESDALC5-1BT2
Single line low capacitance Transil
TM
, transient surge voltage suppressor (TVS) for ESD protection
Datasheet - production data
SOD882 SOD882T
Features
Single line low capacitance Transil diode
Bidirectional ESD protection
Breakdown voltage V
BR
= 5.8 V min
Low diode capacitance (26 pF typ. at 0 V)
Low leakage current < 60 nA at 5 V
Very small PCB area: 0.6 mm²
Applications
Where transient overvoltage protection in ESD sensitive equipment is required, such as:
Computers
Printers
Communication systems
Cellular phone handsets and accessories
Video equipment
Benefits
High ESD protection level
High integration
Suitable for high density boards
Lead-free packages
ECOPACK ® 2 compliant components
Complies with the following standards
IEC 61000-4-2 (exceeds level 4)
30 kV (air discharge)
30 kV (contact discharge)
MIL STD 883G - Method 3015-7: class 3
Human body model
Description
The ESDALC5-1BM2 (SOD882) and
ESDALC5-1BT2 (SOD882T) are bidirectional single-line TVS diodes designed to protect data lines or other I/O ports against ESD transients.
These devices are ideal for applications where both reduced line capacitance and board space saving are required.
Figure 1: Functional diagram
I/O1
I/O2
TM: Transil is a trademark of
STMicroelectronics
November 2016 DocID16936 Rev 6
This is information on a product in full production.
1/13 www.st.com
Characteristics
1 Characteristics
Symbol
V
PP
P
PP
I
PP
T stg
T j
T
L
ESDALC5-1BM2, ESDALC5-1BT2
Table 1: Absolute maximum ratings (T amb
= 25 °C)
Parameter
Peak pulse voltage
Peak pulse power
Peak pulse current
Storage temperature range
Junction temperature
IEC 61000-4-2:
Contact discharge
Air discharge
8/20μs, T j
initial = T
8/20μs
Maximum lead temperature for soldering during 10 s amb
Figure 2: Electrical characteristics (definitions)
Value
30
30
150
9
-65 to +150
-55 to +150
260
Unit kV
W
A
°C
2/13
Symbol
V
I
RM
R
C
V
BR d line
CL
Table 2: Electrical characteristics (T amb
= 25 °C)
Test condition Min. Typ. Max. Unit
From I/O1 to I/O2, IR = 1 mA
From I/O2 to I/O1, IR = 1 mA
V
RM
= 5 V
Dynamic resistance, pulse width 100 ns
From I/O1 to I/O2
From I/O2 to I/O1
F = 1 MHz, V
R
= 0 V
8 kV contact discharge after 30 ns IEC 61000 4-2
From I/O1 to I/O2
From I/O2 to I/O1
11
5.8
13
8
0.25
0.23
26
16
11
17
11
60
30
V nA
Ω pF
V
DocID16936 Rev 6
ESDALC5-1BM2, ESDALC5-1BT2
1.1 Characteristics (curves)
Figure 3: Peak pulse power dissipation versus initial junction temperature (maximum values)
Characteristics
Figure 4: Leakage current versus junction temperature (typical values)
250
225
200
175
150
125
100
75
50
25
0
0
PPP (W)
25 50 75
Tj(°C)
100 125 150
8/20µs
175
1000
IR (nA)
100
10
1
0.
1
0.01
25 50 75 100
V
R
= V
RM
= 5 V from I/O1 to I/O 2
125
Tj(°C)
150
1000
Figure 5: Leakage current versus junction temperature (typical values)
IR (nA)
V
R
= V
RM
= 5 V from I/O2 to I/O1
100
Figure 6: Peak pulse power versus exponential pulse duration (direct)
10000
P
PP
(W)
1000
10
100
1
10
0.1
0.01
25 50 75 100 125
Tj(°C)
150
Figure 7: Clamping voltage versus peak pulse current (typical values)
1
1 10 100 1000
Figure 8: Clamping voltage versus peak pulse current (typical values)
10
IPP (A)
8/20µs
T j initial
= 25 °C
From I/O1 to I/O2
10
IPP (A)
8/20µs
T j initial
= 25 °C
From I/O2 to I/O1
1 1
0,1
12 13 14 15 16 17 18 19 20 21
V
CL
(V)
22 23
0. 1
7 8 9 10 11 12 13 14
V
CL
(V)
15 16
DocID16936 Rev 6 3/13
Characteristics
Figure 9: Junction capacitance versus reverse applied voltage (typical values from I/O1 to I/O2)
35
C(pF)
30
25
20
15
10
5
0
0 1 2 3
T j = 25 °C
F = 1 MHz
Vosc = 30 mV from I/O1 to I/O2
4
V
R
(V)
5
ESDALC5-1BM2, ESDALC5-1BT2
Figure 10: Junction capacitance versus reverse applied voltage (typical values from I/O2 to I/O1)
35
C(pF)
30
25
20
15
10
5
0
0 1 2 3
T j = 25 °C
F = 1 MHz
Vosc = 30 mV from I/O2 to I/O1
4
V
R
(V)
5
Figure 11: ESD response to IEC 61000-4-2
(+8 kV air discharge)
Figure 12: ESD response to IEC 61000-4-2
(-8 kV air discharge)
4/13
Figure 13: S21 attenuation measurement result
0 dB
- 5
- 10
- 15
- 20
- 25
- 30
- 35
- 40
100k 1M 10M 100M 1G
F(Hz)
20
18
16
14
12
10
8
6
4
2
0
0
Figure 14: TLP measurement
IPP (A) from I/O2 to I/O1
5 10 15 from I/O1 to I/O2
VCL(V)
20 25
DocID16936 Rev 6
ESDALC5-1BM2, ESDALC5-1BT2
2
2.1
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
SOD882 package information
Figure 15: SOD882 package outline
Ref.
D
E e
A
A1 b1 b2
L1
L2
Min.
0.40
0.00
0.45
0.45
0.55
0.95
0.60
0.20
0.20
0.50
0.50
0.60
1.00
0.65
0.25
0.25
Table 3: SOD882 package mechanical data
Dimensions
Millimeters Inches
Typ.
0.47
Max.
0.50
0.05
0.55
0.55
0.65
1.05
0.70
0.30
0.30
Min.
0.016
0.000
0.018
0.018
0.022
0.037
0.024
0.008
0.008
Typ.
0.019
0.020
0.020
0.024
0.039
0.026
0.010
0.010
Max.
0.020
0.002
0.022
0.022
0.026
0.041
0.028
0.012
0.012
DocID16936 Rev 6 5/13
Package information
Figure 16: Footprint recommendations, dimensions in mm (inches)
ESDALC5-1BM2, ESDALC5-1BT2
Figure 17: Marking
0.55
(0.022)
0.55
(0.022)
0.50
0.020
Pin1
G
Pin 2
0.40
(0.016)
Product marking may be rotated by multiples of 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose.
Figure 18: SOD882 tape and specifications
6/13 DocID16936 Rev 6
ESDALC5-1BM2, ESDALC5-1BT2
2.2 SOD882T package information
Figure 19: SOD882T package outline
Package information
Ref.
A
A1 b1 b2
D
E e
L1
L2
Min.
0.30
0.00
0.45
0.45
0.55
0.95
0.60
0.20
0.20
0.50
0.50
0.60
1.00
0.65
0.25
0.25
Table 4: SOD882T package mechanical data
Dimensions
Millimeters
Typ. Max.
0.40
0.05
0.55
0.55
0.65
1.05
0.70
0.30
0.30
Min.
0.012
0.000
0.018
0.018
0.022
0.037
0.024
0.008
0.008
Inches
Typ.
0.020
0.020
0.024
0.039
0.026
0.010
0.010
Max.
0.016
0.002
0.022
0.022
0.026
0.041
0.028
0.012
0.012
DocID16936 Rev 6 7/13
Package information
Figure 20: Footprint recommendations, dimensions in mm (inches)
ESDALC5-1BM2, ESDALC5-1BT2
Figure 21: Marking
0.55
(0.022)
0.55
(0.022)
0.50
0.020
Pin1
H
Pin 2
0.40
(0.016)
Product marking may be rotated by multiples of 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose.
Figure 22: SOD882T tape and specifications
8/13 DocID16936 Rev 6
ESDALC5-1BM2, ESDALC5-1BT2
3
3.1
Recommendation on PCB assembly
Recommendation on PCB assembly
Stencil opening design
1. General recommendation on stencil opening design a. Stencil opening dimensions: L (Length), W (Width), T (Thickness).
2. General design rule a. Stencil thickness (T) = 75 ~ 125 μm b. Aspect ratio =
𝑊
𝑇
≥ 1.5
𝐿×𝑊 c. Aspect area =
2𝑇(𝐿+𝑊)
≥ 0.66
3. Reference design a. Stencil opening thickness: 100 μm b. Stencil opening for central exposed pad: Opening to footprint ratio is 50%. c. Stencil opening for leads: Opening to footprint ratio is 90%.
Figure 23: Stencil opening dimensions
L
T
W
Figure 24: Recommended stencil window position in mm (inches)
3.2 Solder paste
1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004.
2. “No clean” solder paste is recommended.
3. Offers a high tack force to resist component movement during high speed.
4. Solder paste with fine particles: powder particle size is 2038 μm.
DocID16936 Rev 6 9/13
Recommendation on PCB assembly
3.3 Placement
ESDALC5-1BM2, ESDALC5-1BT2
1. Manual positioning is not recommended.
2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering
3. Standard tolerance of ±0.05 mm is recommended.
4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages.
5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool.
6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
3.4
3.5
PCB design preference
1. To control the solder paste amount, the closed via is recommended instead of open vias.
2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
Reflow profile
Figure 25: ST ECOPACK® recommended soldering reflow profile for PCB mounting
10/13
Minimize air convection currents in the reflow oven to avoid component movement.
Maximum soldering profile corresponds to the latest IPC/JEDEC J-STD-020.
DocID16936 Rev 6
ESDALC5-1BM2, ESDALC5-1BT2
4 Ordering information
Figure 26: Ordering information scheme
Ordering information
ESDA LC 5 - 1 B x2
ESD array
Lo w capacitance
Breakdown voltage
5 = 5.8 Volts min
Number of lines
Directional
B = Bi-directional
Package
M2 = SOD882
T2 = Thin (SOD882T)
Order code
ESDALC5-1BM2
ESDALC5-1BT2
Table 5: Ordering information
Marking (1)
Package Weight Base qty.
G
H
SOD882
SOD882T
0.93 mg
0.82 mg
12000
12000
Notes:
(1)
The marking can be rotated by multiples of 90° to differentiate assembly location
Delivery mode
Tape and reel
Tape and reel
DocID16936 Rev 6 11/13
Revision history
5
ESDALC5-1BM2, ESDALC5-1BT2
Revision history
Date
Table 6: Document revision history
Revision Changes
02-Feb-2010
06-Jun-2012
05-Mar-2013
09-Jan-2014
02-Apr-2014
28-Nov-2016
1
2
3
4
5
6
Initial release.
Updated Figure 11, Figure 12, Figure 15, Figure 19, Table 3 , and Table 4 . Updated note in page 7, 8 and 13. Updated I
RM in Table 2 .
Clamping voltage at 30 ns added in Table 2 .
Updated Table 1, Table 2, Table 5, Figure 2, Figure 3, Figure
4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10,
Figure 11, Figure 12, Figure 16, Figure 17, Figure 20, Figure
21 and Figure 24 . Added Figure 14 .
Updated Figure 4 and Figure 5 .
Updated cover image, Table 2: "Electrical characteristics
(Tamb = 25 °C)" and Figure 2: "Electrical characteristics
(definitions)" .
12/13 DocID16936 Rev 6
ESDALC5-1BM2, ESDALC5-1BT2
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DocID16936 Rev 6 13/13
