ESDALC14-1BF4
Low clamping and low capacitance bidirectional single line ESD protection
Datasheet - production data
Description
The ESDALC14-1BF4 is a bidirectional single line TVS diode designed to protect the data line or other I/O ports against ESD transients.
The device is ideal for applications where both reduced line capacitance and board space saving are required.
Figure 1: Functional diagram
0201 package
Features
Low clamping voltage: V
CL
= 18 V
Bidirectional device
Low leakage current
0201 package
Ultra-low PCB area: 0.18 mm 2
ECOPACK ® 2 compliant component
Exceeds IEC 61000-4-2 level 4 standard:
±15 kV (air discharge)
±8 kV (contact discharge)
Applications
Where transient over voltage protection in ESD sensitive equipment is required, such as:
Smartphones, mobile phones and accessories
Tablet, PC, netbooks and notebooks
Portable multimedia devices and accessories
Digital cameras and camcorders
Communication and highly integrated systems
December 2017 DocID024898 Rev 3
This is information on a product in full production.
1/9 www.st.com
Characteristics
1 Characteristics
Symbol
V
PP
P
PP
I
PP
T j
T stg
T
L
Table 1: Absolute ratings (T amb
= 25 °C)
Parameter
Peak pulse voltage
IEC 61000-4-2 contact discharge
IEC 61000-4-2 air discharge
Peak pulse power dissipation (8/20 μs)
Peak pulse current (8/20 μs)
Operating junction temperature range
Storage temperature range
Maximum lead temperature for soldering during 10 s
Figure 2: Electrical characteristics (definitions)
ESDALC14-1BF4
Value
25
30
100
5
-40 to +150
-65 to +150
260
Unit kV
W
A
°C
°C
°C
Symbol
V
BR
I
RM
V
CL
C
LINE
Table 2: Electrical characteristics (T amb
= 25 °C)
Test condition Min. Typ. Max. Unit
I
R
= 1 mA
V
RM
= 12 V
8 kV contact discharge after 30 ns, IEC 61000-4-2
F = 1 MHz, V
LINE
= 0 V, V
OSC
= 30 mV
13
18
22
100
25
V nA
V pF
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ESDALC14-1BF4
1.1 Characteristics (curves)
100
10
1
Figure 3: Leakage current versus junction temperature (typical values)
Ir(nA)
0.1
25 50 75 100
V
R
=V
RM
=12V
IO/IO
125
T j
(°C)
150
Characteristics
Figure 4: Junction capacitance versus applied voltage (typical values)
30
C(pF)
25
T j
= 25 ° C
F = 1 MHz
Vosc = 30 mV
IO/IO
20
15
10
5
0
0 1 2 3 4 5 6 7 8 9
V
R
(V)
10 11 12
Figure 5: ESD response to IEC 61000-4-2
(+8 kV contact discharge)
10 V/div
1
2
3
4
VCL: Peak clamping voltage
VCL: Clamping voltage at 30 ns
VCL: Clamping voltage at 60 ns
VCL: Clamping voltage at 100 ns
1 35.2 V
2 17.2 V 3 16.4 V
4 15.0 V
Figure 6: ESD response to IEC 61000-4-2
(-8 kV contact discharge)
10 V/div
1
2
3
4
VCL: Peak clamping voltage
VCL: Clamping voltage at 30 ns
VCL: Clamping voltage at 60 ns
VCL: Clamping voltage at 100 ns
2 2
-18.2 V 3 -17.0 V 4 -15.1 V
20 ns/div
1 -33.8 V
20 ns/div
30
I
PP
(A)
Figure 7: Dynamic resistance
25
Positive polarity
Negative polarity
20
15
10
5
0
0
Rd 0.22
5 10 15 20
V
CL
(V)
25
Figure 8: Attenuation measurement result
0
-3
S21(dB)
-24
-27
-30
-33
-36
-39
-42
-45
-6
-9
-12
-15
-18
-21
-48
-51
-54
100k 1M 10M f (Hz)
100M 1G 10G
DocID024898 Rev 3 3/9
Package information
2
2.1
Package information
ESDALC14-1BF4
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
0201 package information
Figure 9: 0201 package outline
4/9
The marking codes can be rotated by 90° or 180° to differentiate assembly location. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose.
DocID024898 Rev 3
ESDALC14-1BF4
Ref.
A b
D
D1
E
E1 fD fE
Table 3: 0201 package mechanical data
Dimensions
Millimeters
Min.
0.280
0.125
0.570
0.270
0.175
0.110
0.040
Typ.
0.300
0.140
0.600
0.350
0.300
0.190
0.125
0.055
Figure 10: Marking
Package information
Max.
0.320
0.155
0.630
0.330
0.205
0.140
0.070
Pin1 Pin2
The marking codes can be rotated by 90° or 180° to differentiate assembly location. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose.
Figure 11: Tape and reel specification (in mm)
Bar indicates Pin1
Ø 1.5 ±0.1
2.0 ±0.05
4.0 ±0.1
0.2 ±0.02
0.36 ±0.03
All dimensions in mm
0.38 ±0.03
2.0 ±0.05
User direction of unreeling
DocID024898 Rev 3 5/9
Recommendation on PCB assembly
3 Recommendation on PCB assembly
3.1 Footprint
1.
Footprint in mm a.
SMD footprint design is recommended.
Figure 12: Footprint in mm
ESDALC14-1BF4
3.2 Stencil opening design
1.
Reference design a.
Stencil opening thickness: 75 μm / 3 mils
Figure 13: Recommended stencil window position in mm
3.3 Solder paste
1.
Halide-free flux qualification ROL0 according to ANSI/J-STD-004.
2.
“No clean” solder paste is recommended.
3.
Offers a high tack force to resist component movement during high speed.
4.
Use solder paste with fine particles: powder particle size 20-38 µm.
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ESDALC14-1BF4
3.4 Placement
Recommendation on PCB assembly
1.
Manual positioning is not recommended.
2.
It is recommended to use the lead recognition capabilities of the placement system, not the outline centering
3.
Standard tolerance of ±0.05 mm is recommended.
4.
1.0 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages.
5.
To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool.
6.
For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
3.5 PCB design preference
1.
To control the solder paste amount, the closed via is recommended instead of open vias.
2.
The position of tracks and open vias in the solder area should be well balanced. A symmetrical layout is recommended, to avoid any tilt phenomena caused by asymmetrical solder paste due to solder flow away.
3.6 Reflow profile
Figure 14: ST ECOPACK® recommended soldering reflow profile for PCB mounting
Minimize air convection currents in the reflow oven to avoid component movement.
DocID024898 Rev 3 7/9
Ordering information
4 Ordering information
Figure 15: Ordering information scheme
ESDALC14-1BF4
ESDA LC 14 1 B F4
ESD array
Low Capacitance
Breakdown voltage
Number of lines
B = Bi-directional
Package
F4 = 0201
5
Order code
ESDALC14-1BF4
Marking
Table 4: Ordering information
Package Weight Base qty.
1 (1)
0201 0.120 mg 15000
Notes:
(1)
The marking codes can be rotated by 90 °C or 180 °C to differentiate assembly location.
Delivery mode
Tape and reel
Revision history
Date
Table 5: Document revision history
Revision Changes
11-Oct-2013
03-Sep-2015
14-Dec-2017
1
2
3
First issue.
Updated Table 2.
Updated weight from 0.116 mg to 0.120 mg.
8/9 DocID024898 Rev 3
ESDALC14-1BF4
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