VME Interface VC16
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User Manual
0 VC 16 - *00211.A0, 01/97
CONTENT
1.
1.1
1.2.
1.3.
1.4.
2.
VME - CAMAC interface VC16 .................................................................................. 2
General description ....................................................................................................... 2
Front panel ................................................................................................................... 2
Interface description ..................................................................................................... 3
VC16 Installation .......................................................................................................... 6
Register Layout and operating modes .......................................................................... 7
3.
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Programming and CAMAC operations ........................................................................ 9
Call and crate on/off ..................................................................................................... 9
General CAMAC commands Z, C, I ......................................................................... 10
LAM servicing ............................................................................................................ 10
Read and write data .................................................................................................. 10
CAMAC status bits Q and X ...................................................................................... 11
Cable delay Correction ............................................................................................... 12
Using Interrupts .......................................................................................................... 12
4.
C - Library and software examples ............................................................................ 13
APPENDIX Technical documentation ........................................................................................ A
14th January 1997
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1. VME - CAMAC Interface VC16
1.1. General Description
The VC16 is a single-width 6U VME interface card for control of up to 15 CAMAC crates equipped with the W-I e
-N e
-R CC16 CAMAC crate controller.
The link between the CAMAC crates and the interface is performed by a 16-bit parallel interface (CP bus protocol) with a high speed data transfer ( up to 1Mb/s). The cable length of the VC16 and CC16 link may be up to 200 metres (twisted pair cable) or up to 30m in case of standard flat cable. The VME interface module VC16 will serve for correct timing in case of cable length > 10 metres by stretching the VME cycles, i.e. delaying the acknowledge time from the slave connected.
The VC16 is an A24/D16 VME bus slave. The module supports the AM codes $39 and
$3D. The VC16 sub-devices are addressed via 3 LSB address lines. The basic address is complete decoded and switch selectable. For LAM servicing one interrupt channel is installed. The interrupt request level (1-7) may be software selected in the VC16 status register.
The VC16 interface supports the special features of the CC16 like broadcast and block mode operation with automatic CAMAC NAF-code repeat. Additional the VC16 is equipped with an internal CP-bus cable delay correction and a CP-bus test feature .
The data transfer from / to the VME bus system has to be organised by an application program running on the VME CPU.
The different crates connected via the CC16 have 15 different geographic addresses and one broadcast address for parallel access. For special applications every single crate may be enabled / disabled for parallel download.
The VC 16 interface and the last CC16 controller in one chain have to be terminated to enable the correct function during the high speed data transfer.
1.2. Front Panel
Five status LED's are placed on the VC16 front panel to show ACCESS, LAM pending,
LAM enable as well as write or mode operations of the CP bus protocol with the following functions,
ACCESS
lights if there is any access from the CPU
LAM pending
lights if there is a LAM request from the actual CAMAC crate
LAM enable
lights if the LAM interrupt line is enabled
write CP
lights if VC16 write to CP bus
read/ mode CP
lights if VC16 access to CP bus mode
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VC16 module access
LAM pending
IRQ on LAM enable write CP mode CP interface connetor (CP bus
Fig. 1, CC16 front panel
Below the status LED's the 50-pin connector for parallel link to the interface (flat or twisted pair cable) is mounted Please note that both interface VC16 and the last CC16 in a chain have to be terminated by equal resistors (see next chapter)
1.3. Interface description
For any operation the CAMAC crate controller CC16 has to be linked to an external interface which is driven by a micro-processor or computer. The communication between the CC16 and the interface is performed according to the CP - "Communication bus
Protocol" (RS422 - developed by RWTH Aachen). The CP bus consists of 16 bi-directional data lines and 7 control lines used for geographical addressing of the installed CC16 as well as for control and data transfer strobes. All signals are transferred as bipolar TTL signals.
Both the CC16 and the used interface have to be terminated to enable correct function during the high speed data transfer.
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Fig. 2, VC16 block diagram
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The crate controller termination is performed with resistor networks (RN6 - RN8). Two types of cable termination are provided: type short distance long distance* resistor
DIL 220 Ohm
2 x SIL8 + 1 x 100Ohm *
Table 1 Termination resistor types (* factory prepared) cable length
<30m
>30m
Both ends of the link, i.e. CC16 and interface have to be terminated with equal resistors.
Note, that in case of multi-crate systems only the last CC16 in the chain has to be terminated.
Maximum tested distances between crate controller and interface are 30 metres in case of
50 pin-flat cable or up to 200 metres using twisted pair cable.
The pin assignment of the 50-pin CP-bus interface connector is given in the following table.
10
11
12
13
06
07
08
09
14
15
16
17
Pin
01
02
03
04
05
22
23
24
25
18
19
20
21
Line
D0*
D0
D1*
D1
D2*
D2
D3*
D3
D4*
D4
D5*
D5
D6*
D6
D7*
D7
D8*
D8
D9*
D9
D10*
D10
D11*
D11
D12*
Table 2, CP-bus Interface connector pin assignment
35
36
37
38
31
32
33
34
39
40
41
42
Pin
26
27
28
29
30
47
48
49
50
43
44
45
46
Line
D12
D13*
D13
D14*
D14
D15*
D15
GND
LAM
STATUS*
AKN
BusN1*
BusN1
BusN2*
BusN2
BusN4*
BusN4
BusN8*
BusN8
BusMODE*
BusMODE
BusWRITE*
BusWRITE
BusS*
BusS
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1.4. VC16 installation
Prepare the VC16 before inserting into the 6U-VME system, i.e. check or select the register range by the hexadecimal switches (S1 - S5 according to the following scheme and example for BADR = $800000 ).
Switch
Address
number value hex.
bin.
1
8
8
0100
2
0
0
0000
3
0
0
0000
4
0
0
0000
5
0
0
0000
-
-
0
0000 disable enable
settling delay
S5
AM: $39 $3D
S1 S2
S3 S4
Further the address modifier ($39 or $3D) has to be chosen by jumper setting on the VC16 board. The settling delay jumper should be in case of standard cable lengths up to 20 metres in the disabel position.
Switch off the VME crate and insert the VC16 into an empty VME slot. Connect the CC16 chain with the VC 16 by the 50 pin flat cable and switch on VME crate mains. For correct operation the VC16/CC16 system has to be initialised first by setting the geographical address of the called controller. Further the initial conditions for inhibit line (I - set off) and
IRQ on LAM should be defined (see next chapters). At the end of initialisation a CAMAC initialise (Z) should be performed.
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2. Register Layout and operating modes
The access to the CAMAC crate controller is performed according to the CP bus protocol via calls of several modes which are for selection of read / write operation or special controller functions. These modes are primary modes (PM) defining the type of operation and sub-modes (SM) for the controller functions (detailed description see CC16 Manual).
In opposite to the personal computer interface PC16 with the VME VC16 interface there is no more a direct access to the primary modes. The primary mode selection is automatically done during sub-mode write as well as write and read data by using several registers. Also for the geographical address load a single register is used.
The complete 14 byte register block is organised according to the following scheme:
Name
Status Register
Mode Register
Output Data
Input Data
Geogr. Address
Interrupt Vector
Set Test Interrupt
Table 3, VC16 address layout
Size
D0 - D11
D0 - D4
D0 - D15
D0 - D15
D0 - D7
D0 - D7 dummy
Address
BASE + $0
BASE + $2
BASE + $4
BASE + $6
BASE + $8
BASE + $A
BASE + $C
Access type read / write read / write read / write read read / write read / write
write
The Status register (BASE+$0) includes the VME interrupt levels, the LAM and CP status as well as the cable delay information which is necessary for correct timing in a high speed data transfer with long distances between the CAMAC crates and the interface. The bit assignment is given in the following table:
5
6
3
4
1
2
Bit
0
7
8
9
10
11
Description interrupt level 1 interrupt level 2 interrupt level 4
0=disable, 1=enable LAM interrupt
0=LAM pending, 1=no LAM
CP acknowledge - CAMAC X
CP status - CAMAC Q test interrupt cable delay 1 (20m length) cable delay 2 (30m length) cable delay 4 (50m length) cable delay 8 (100m length)
Access read / write read / write read / write read / write read read read read read / write read / write read / write read / write
Table 4, VC16 Status register bit assignment
To test the correct connection between CAMAC crate and interface the VC16 is equipped with a read back mode register facility which can be red after a CP-bus activity. This feature can be used for troubleshooting in case of link fail functions. The last called primary mode is stored in bit D0 and D1. The next three bits show the type of the CP bus activity. The detailed read back register pin assignment is given in the following table,
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Bit
1
2
3
4
5
Description primary mode primary mode
CP bus strobe
CP bus mode
CP bus write
Read back value write sub-mode
1
0
1
1
1
$1D
Example write data
0
0
1
1
1
$16 read data
1
1
1
0
0
$7
Table 5, CP-bus read back bit description
The primary modes of the CP bus protocol which are indicated by the first two bits are listed in the following table, primary mode
1
2
3
4 function set geographical address select device sub-mode register write data read data.
7
8
9
10
11
12
13
5
6
3
4
0
1
2
Table 6, CP-bus primary modes
SM
9
A
B
C
D
7
8
5
6
3
4
1
2 hexvalue.
0
Function write N, F, A and prompt CAMAC cycle bit write high byte (8 bit) to CAMAC dataway write low word (16 bit) to CAMAC dataway read low word (16 bit) from CAMAC dataway read high byte (8 bit) from CAMAC dataway block mode read low word (16 bit) with NAF-repeat
CAMAC cycle with C or Z if enabled enable for read / write CC16 status register (SCB) enable CAMAC-C for next SM6 call enable CAMAC-Z for next SM6 call set CAMAC-I to true set CAMAC-I to false enable VC16 LAM servicing disable VC16 LAM servicing
Table 7, CC16 Sub-modes
Via the 4 bits of the Mode register (BASE+$2) the different sub-modes of the CAMAC crate controllers are called. These sub-modes (SM) which chooses the controller function for CAMAC access are defined as follows:
The Output Data register (BASE+$4) as well as the Input Data register (BASE+$6) with a length of 16 bit are for the data transfer from and to the connected CAMAC crate controllers for:
- NAF-code (16 bit word, only output)
- low data word (16 bit)
- high data byte (8 bit).
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As described in more detail in the CC16 Manual the NAF-code includes the station number
N of an addressed module, the sub-address A and the function number F. It is decoded according to the following bit assignment:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
N1 N2 N4 N8 N16 F1 F2 F4 F8 F16 A1 A2 A4 A8 -S
Table 8, NAF code bits
The last bit S corresponds to an immediate CAMAC cycle on a NAF-load. If this bit is 0 the
NAF load in the CC16 will not cause a prompt CAMAC cycle. S=0 is necessary write data to the dataway. For read-operations one has to set S=1.
The
Geographic Address register (BASE+$8) is for selecting the CAMAC crate for the following operations. The chosen number defined by the first 4 bits ($0 ... $E) has to be equal to the value of the address switch on the CC16 front panel which has to be accessed.
The address $F is used for broadcast operations to all connected controllers. For test purposes the geographic address may be read back.
The VC16 is prepared for interrupt based LAM servicing. The interrupt request level
IRQ1* ... IRQ7* is defined by the setting of the first three bits of the VC16 status register.
The 8-bit STATUS/ID for the interrupt acknowledge cycle [D08(O)] has to be load into the
Vector register (BASE+$A). To test the interrupt function via the Test Interrupt register
(BASE+$C) a software interrupt may be produced. Note, that for this operation the LAM enable bit in the status register must be set to true. The interrupt reset is done by clearing the LAM enable bit.
3. Programming and CAMAC operation
The VC16 / CC16 operation is performed on the basis of setting or reading the several
VC16 registers which are described in chapter 2. The following instruction schemes are given in terms of setting these modes and registers and writing / reading data. Please consult the CC16 manual for the detailed CC16 functions.
3.1. Call and set crate on/off
select crate, write geographical address
write Geo.Addr.register(BASE+$8)
- set crate / branch
Set crate on / off
set SM7(BASE+$2) write SCB(BASE+$4)
- set SM to CC16 status register
- write scb with: bit2=0 switch crate on bit2=1 switch crate off to test the setting read the SCB with
read SCB(BASE+$8)
-
read SCB with: bit2=0 crate is on bit2=1 crate is off
The crate ON / OFF is displayed by a status LED at the front panel of the CC16. These ON
/ OFF modes are only relevant for broadcast operations.
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3.2. General CAMAC commands Z, C, I
CAMAC INITIALISE - Z
set SM9(BASE+$2) set SM6(BASE+$2)
- set SM to enable Z
-
set SM to perform Z cycle
Q and X response will be set to 1 as response of CC16 to the Z-cycle.
CAMAC CLEAR - C
set SM8(BASE+$2) set SM6(BASE+$2)
- set SM to enable C
-
set SM to perform C cycle
Q and X response will be set to 1 as response of CC16 to the C-cycle.
SET CAMAC INHIBIT - I
set SM10(BASE+$2)
- set SM to enable I
SET BACK CAMAC INHIBIT - I
set SM11(BASE+$2)
- set SM to disable I
The status of the inhibit line (I) is displayed at the CC16 front panel by the Inhibit LED.
3.3. LAM servicing
ENABLE IRQ ON LAM REQUEST
set SM12(BASE+$2)
- set SM to enable IRQ on LAM request
DISABLE IRQ ON LAM REQUEST
set SM13(BASE+$2)
- set SM to disable IRQ on LAM request
READ STATUS REGISTER SCB
set SM7(BASE+$2) read data(BASE+$6)
- set SM to CC16 status register
- read SCB (bits see CC16 manual)
CC16 INITIALISATION
The complete CC16 initialisation should include setting of crate / branch and SCB as well as of giving Z-cycle and checking for no setting of I-line,
write Geo.Addr.register(BASE+$8)
- set crate / branch
set SM7(BASE+$2)
- set SM to CC16 status register
write SCB(BASE+$4)
- write scb with bit2=0 switch crate on
3.4. Read and write data
ACCESS AND DATA TRANSFER TO CAMAC MODULES
The data transfer to or from modules of the CC16 controlled crate has to be done in two steps due to the 24-bit word length of the CAMAC bus. First read or write the low and middle byte as one 16-bit word. The second cycle is for reading / writing the high byte if
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required. However a lot of CAMAC modules use only word length up to 16 bit. In this case
16-bit data transfer is faster and more useful.
WRITE 24-BIT WORD
cycle
set SM0(BASE+$2) write NAFBASE+$4)
- set SM to write NAF
- write NAF -word with S-bit=0
set SM1(BASE+$2)
- set SM to write high byte
write data(BASE+$4)
- write high byte
set SM2(BASE+$2)
- set SM to write low word
write data(BASE+$4)
- write low word (0-15) and start CAMAC
WRITE 16-BIT WORD set SM0(BASE+$2) write NAFBASE+$4)
- set SM to write NAF
- write NAF -word with S-bit=0
set SM2(BASE+$2)
- set SM to write low word
write data(BASE+$4)
- write low word (0-15) and start CAMAC cycle
READ 24-BIT WORD set SM0(BASE+$2) write NAFBASE+$4) set SM3(BASE+$2) read data(BASE+$6) set SM4(BASE+$2) read data(BASE+$6)
- set SM to write NAF
- write NAF -word with S-bit=1 and start
CAMAC cycle
- set SM to read low word
- read low word (0-15)
- set SM to read high byte
- read high byte
READ 16-BIT WORD set SM0(BASE+$2) write NAFBASE+$4) set SM3(BASE+$2) read data(BASE+$6)
- set SM to write NAF
- write NAF -word with S-bit=1 and start
CAMAC cycle
- set SM to read low word
- read low word (0-15)
16-BIT FAST BLOCK TRANSFER (READ) set SM0(BASE+$2) write NAFBASE+$4) set SM5(BASE+$2) read data(BASE+$6) read data(BASE+$6) read data(BASE+$6) read data(BASE+$6)
- set SM to write NAF
- write NAF -word with S-bit=1 and start
CAMAC cycle
- set SM to block read low word
- read low word (0-15)
- read low word (0-15)
- read low word (0-15)
- read low word (0-15)
- read low word (0-15)
read data(BASE+$6)
...
the last word has to be read again by the full sequence :
set SM3(BASE+$2) read data(BASE+$6)
- set SM to read low word
- read low word (0-15)
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3.5. CAMAC status bits Q and X
The status bits Q and X are stored in the status register of the interface (ISR) in the first bits
CSD0 and CSD1. The Q- and X- bits will be stable within 1.4µs.
read ISR
- read ISR Q = bit 6 X = bit 5
3.6. Cable delay correction
The VC16 will serve for correct timing in case of cable lengths by strectching the VME bus cycles, e.g. delaying the acknowledge time from the controllers connected. The delay may be different for the 15 geographical addresses. The several delay values are defined within bit 8-11 of the VC16 status register. The following table gives examples for typical cable lengths / delay times (including CAMAC cycle), cable length
<10m
<30m
<50m
<100m
<200m delay time
1.2µs
1.4µs
1.8µs
2.8µs
5.2µs status register
(hex.) x0xx x1xx x3xx x7xx xFxx bit assignment
(bin.) xxxx 0000 xxxx xxxx xxxx 1001 xxxx xxxx xxxx 0011 xxxx xxxx xxxx 0111 xxxx xxxx xxxx 1111 xxxx xxxx
Table 9, Interface cable delay programming
To fix the cable delay first select the geographical crate address. Then the bits 8-11 of the statusregister has to be defined.
write Geo.Addr.reg.(BASE+$8)
- set crate / branch
write Status register (BASE) - write status register
3.7. Using interrupts
The VC16 is able to generate an interrupt on the VME bus after receiving a LAM request.
The interrupt level is defined within the VC16 status register, i.e. bits 0 - 2 (see table 4).
The vector address is loaded into the VC16 vector register (BASE+$A, see table 3).
For interrupt based LAM servicing first the VC16 has to be enabled for interrupt on LAM.
This is done by setting bit 3 of the VC16 status register to 1. To reset the LAM interrupt disable, i.e. set bit 3 to 0.
The interrupt servicing on the VME bus which is strongly CPU dependant has to be defined within the CAMAC control and read out software. For testing the interrupt can be generated by writing any dummy value into the test interrupt register (BASE+$C). For interrupt programming see the VME-CPU manual and programming language description.
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4. C-Library and software examples
The following chapter describes the contents of the OS-9 software kit. The included C-code library for the VC16 / CC16 is based on a general definition of the VME register access by the commands get_reg(address) and put_reg(address, data). This access which depends on the chosen address modifier AM, i.e. on the size of the address range (16bit /24bit/32bit) as well as on the kind of operation (supervisor / data / user / ...). is strongly CPU dependent.
Thus in the unit reg_acc.c the register access operations get_reg and put_reg used in the
cam_vc16.c library has to be defined for the used VME bus master. Programming examples are given for the ELTEC E7/E8 and the CES FIC8232 modules.
As an example for using the C-library please find the test program vc16test.c.
/*
cam_vc16.c
********************************************************************
CC16 / VC 16 C routines
----------------------------------------------------------------
Unit contains :
cam_adr - set I/O address (BADR)
getstatus
cam_cratecheck
set_crate
set_delay
cam_controller_ini
cam_z
- get CC16 status
- test crate available
- set geographical crate address
- set value for cable delay (4 bits)
- controller initialization
- CAMAC Initialize (Z)
cam_c
cam_i
cam_ci
cam_irq
cam_noirq
cam_q
cam_x
cam_nfa
cam_nfa_read
cam_nfaqx_read
cam_nfaqx_read24
cam_nfa_write
cam_nfaqx_write
cam_nfaqx_write24
cam_lam
cam_lamf
- CAMAC Clear (C)
- CAMAC Inhibit (I)
- CAMAC Clear + Inhibit (I) setzen
- enable CAMAC LAM-Interrupt
- disable CAMAC LAM-Interrupt
- get CAMAC Q-response
- get CAMAC X-response
- set N,F,A start CAMAC cycle
- set N,F,A and read 2 byte
- set N,F,A and read 2 byte with Q and X
- set N,F,A and read 3 byte with Q and X
- set N,F,A and write 2 byte
- set N,F,A and write 2 byte with Q and X
- set N,F,A and write 2 byte with Q and X
- get LAM source
- any LAM request
badr := basic I/O address
copyright: A. Ruben, W-Ie-Ne-R, PleinBaus GmbH 20.03.95
********************************************************************
CPU dependent register access has to be defined in unit reg_acc.h
*/
#include "reg_acc.c" unsigned int nfa; unsigned long int badr; unsigned long int badr2; unsigned long int badr4; unsigned long int badr6; unsigned long int badr8; unsigned long int badrA; unsigned long int badrC;
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void cam_adr(unsigned long int); int cam_cratecheck (void); void set_crate (int); void set_delay (int); void cam_controller_ini (unsigned long int); int getstatus(void); void cam_z(void); void cam_c(void); void cam_i(void); void cam_ci(void); void cam_0(void); int cam_q(void); int cam_x(void); void cam_irq(void); void cam_noirq(void); void cam_nfa(int, int, int); void cam_nfa_write(int, int, int, unsigned int); void cam_nfaqx_write(int, int, int, unsigned int, int *, int *); void cam_nfaqx_write24(int, int, int, long int, int *, int *); unsigned int cam_nfa_read(int, int, int); unsigned int cam_nfaqx_read(int, int, int, int *, int *); long int cam_nfaqx_read24(int, int, int, int *, int *);
/**************************************************************************/
void cam_adr(unsigned long int bad)
{
badr=bad;
badr2=badr+2;
badr4=badr+4;
badr6=badr+6;
badr8=badr+8;
badrA=badr+10;
badrC=badr+12;
};
/**************************************************************************/
int cam_cratecheck (void)
{
int j;
put_reg(badr8,0);
put_reg(badr2,7);
put_reg(badr4,0);
j=get_reg(badr6);
j=(j & 4) - 4;
if (j<0)
{
j=1;
}
return(j);
};
/**************************************************************************/
void set_crate (int crate)
{
put_reg(badr8,crate);
};
/**************************************************************************/
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void set_delay (int delay_bits)
{
unsigned int i;
i=get_reg(badr);
i=i & 0x0ff;
i=i | (delay_bits << 8);
put_reg(badr,i);
}
/**************************************************************************/
void cam_controller_ini (unsigned long int bad)
{
vme_init();
cam_adr(bad);
set_crate(0);
cam_z();
};
/**************************************************************************/
int getstatus(void)
{
char j;
j=0;
return(j & 7);
};
/***********************************************************************/
void cam_z(void)
{
put_reg(badr2,11);
put_reg(badr2,9);
put_reg(badr2,6);
};
/**************************************************************************/
void cam_c(void)
{
put_reg(badr2,11);
put_reg(badr2,8);
put_reg(badr2,6);
};
/*************************************************************************/
void cam_i(void)
{
put_reg(badr2,10);
};
/************************************************************************/
void cam_ci(void)
{
put_reg(badr2,10);
put_reg(badr2,8);
put_reg(badr2,6);
};
/*************************************************************************/
int cam_q(void)
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{
char j;
j=get_reg(badr);
return ( j >> 6) & 1;
};
/************************************************************************/
int cam_x(void)
{
char j;
j=get_reg(badr);
return ( j >> 5) & 1;
};
/************************************************************************/
void cam_irq(void)
{
put_reg(badr2,12);
};
/*************************************************************************/
void cam_noirq(void)
{
put_reg(badr2,13);
};
/*************************************************************************/
void cam_nfa(int n, int f, int a)
{
nfa= a << 5;
nfa= (nfa | f) << 5;
nfa= nfa | (n+0x8000);
put_reg(badr2,0);
put_reg(badr4,nfa);
};
/*************************************************************************/
void cam_nfa_write(int n, int f, int a, unsigned int data)
{
nfa= a << 5;
nfa= (nfa | f) << 5;
nfa= nfa | n;
put_reg(badr2,0);
put_reg(badr4,nfa);
put_reg(badr2,2);
put_reg(badr4,data);
};
/*************************************************************************/
void cam_nfaqx_write(int n, int f, int a, unsigned int data,int *q, int *x)
{
char j;
nfa= a << 5;
nfa= (nfa | f) << 5;
nfa= nfa | n;
put_reg(badr2,0);
put_reg(badr4,nfa);
put_reg(badr2,2);
16 VC 16 - *00211.A0, 01/97
put_reg(badr4,data);
j=get_reg(badr);
*q=( j >> 6 ) & 1;
*x=( j >> 5 ) & 1;
};
/*************************************************************************/
void cam_nfaqx_write24(int n, int f, int a, long int data,int *q, int *x)
{
char j;
int ih;
int il;
ih= (int) ((data >> 16) & 255);
il= (int) data;
nfa= a << 5;
nfa= (nfa | f) << 5;
nfa= nfa | n;
put_reg(badr2,0);
put_reg(badr4,nfa);
put_reg(badr2,1);
put_reg(badr4,ih);
put_reg(badr2,2);
put_reg(badr4,il);
j=get_reg(badr);
*q=( j >> 6 ) & 1;
*x=( j >> 5 ) & 1;
};
/*************************************************************************/
unsigned int cam_nfa_read(int n, int f, int a)
{
nfa= a << 5;
nfa= (nfa | f) << 5;
nfa= nfa | (n+0x8000);
put_reg(badr2,0);
put_reg(badr4,nfa);
put_reg(badr2,3);
return ((unsigned int) get_reg(badr6));
};
/*************************************************************************/
unsigned int cam_nfaqx_read(int n, int f, int a, int *q, int *x)
{
char j;
nfa= a << 5;
nfa= (nfa | f) << 5;
nfa= nfa | (n+0x8000);
put_reg(badr2,0);
put_reg(badr4,nfa);
put_reg(badr2,3);
nfa= (unsigned int) get_reg(badr6);
put_reg(badr,3);
nfa=(unsigned int) get_reg(badr4);
j=get_reg(badr);
*q=( j >> 6 ) & 1;
*x=( j >> 5 ) & 1;
return (nfa);
};
/*************************************************************************/
17 VC 16 - *00211.A0, 01/97
long int cam_nfaqx_read24(int n, int f, int a, int *q, int *x)
{
char j;
long int lh;
nfa= a << 5;
nfa= (nfa | f) << 5;
nfa= nfa | (n+0x8000);
put_reg(badr2,0);
put_reg(badr4,nfa);
put_reg(badr2,4);
lh=get_reg(badr6) & 255;
lh=lh <<16;
put_reg(badr2,3);
lh += get_reg(badr6) & 0xffff;
j=get_reg(badr);
*q=( j >> 6 ) & 1;
*x=( j >> 5 ) & 1;
return (lh);
};
/*************************************************************************/
int cam_lam(int station)
{
cam_nfa(station,8,0);
return (cam_q());
};
/*************************************************************************/
int cam_lamf(void)
{
int j;
j=get_reg(badr);
return(!j & 2);
};
18 VC 16 - *00211.A0, 01/97
/* reg_acc.c
********************************************************************
VME-bus CPU register Access
copyright: W-Ie-Ne-R, PleinBaus GmbH, A. Ruben 20.12.94
******************************************************************** void vme_init(void); void put_reg(unsigned long int ,unsigned long int ); unsigned long int get_reg(unsigned long int);
#define vc16_base 0x800000
#define eltec_base 0xff000000
#define cesfic_base 0xf0000000
/* for VC16 rotary switches */
/* for ELTEC CPU, AM$39 */
/* for CES FIC8232 CPU, 16bit data, AM$39*/
#define am 0x39 /* Address modifier for ATVME system */
/* jumper to AM$39 on VC16 board */
/*
################ ELTEC 68X00 CPU System ################
AM $39 by address offset
*/
#ifdef ELTEC void put_reg(unsigned long int regadr,unsigned long int data)
{ regadr+=eltec_base;
* ( short * ) regadr = data;
} unsigned long int get_reg(unsigned long int regadr)
{ regadr+=eltec_base; return ( * ( short * ) regadr);
} void vme_init(void)
{
}
#endif
/*
################ CES FIC8232 CPU System ################
AM $39 by address offset
*/
#ifdef CES void put_reg(unsigned long int regadr,unsigned long int data)
{ regadr+=cesfic_base;
* ( short * ) regadr = data;
} unsigned long int get_reg(unsigned long int regadr)
{ regadr+=cesfic_base;
19 VC 16 - *00211.A0, 01/97
return ( * ( short * ) regadr);
} void vme_init(void)
{
}
#endif
/*
################ PRO_VME PC-VME System ############
*/
#ifdef ATVME
#include "VMELIB.C" void put_reg(unsigned long int regadr,unsigned long int data)
{
WriteWordExt(regadr,data,am);
} unsigned long int get_reg(unsigned long int regadr)
{ return ReadWordExt(regadr, am);
} void vme_init(void)
{
Init_AT_VME();
}
#endif
20 VC 16 - *00211.A0, 01/97
/*
W-Ie-Ne-R CC16/VC16 Test and Demonstration
Version 1.1, revised 4/95
copyright, WIENER - Plein & Baus GmbH, 04.04.95
*/
#include <stdio.h>
#include "cam_vc16.c"
#define vc16_base 0x800000 /* for VC16 rotary switches */
#define cab_delay 0x0 /* for VC16-cc16 link cable delay */ int main()
{
int n1,f1,a1;
int q,x;
long int data;
char inbuf [130];
cam_controller_ini(vc16_base);
n1=1;
printf("\n W-IE-NE-R CC16/VC16 DEMONSTRATION \n");
printf("\n ------------------------------------------------- \n \n");
printf("\n NAF code operation demonstration (N=0 to stop) \n");
printf("\n copyright Plein & Baus GmbH, Burscheid/Germany - VI/94 \n \n");
/* demonstration of clear, inhibit and inizialise */
cam_c();
cam_i();
cam_z();
set_delay(0x0);
/* demonstration of NAF read and write operations */ cam_irq();
while (n1 != 0)
{
printf("\n ------------------------------------------------- \n");
printf("\n CAMAC station number N= \t");
gets(inbuf);
sscanf(inbuf, "\t%d", &n1);
printf("\n CAMAC function number F= \t");
gets(inbuf);
sscanf(inbuf, "\t%d", &f1);
printf("\n CAMAC subaddress A= \t");
gets(inbuf);
sscanf(inbuf, "\t%d", &a1);
printf("\n");
if (f1>8)
{
printf(" data to write : \t");
gets(inbuf);
sscanf(inbuf, "\t%li", &data);
cam_nfaqx_write24(n1,f1,a1,data,&q,&x);
printf("\t\t\t Q= %i X= %i",q,x);
}
21 VC 16 - *00211.A0, 01/97
else
{
data = cam_nfaqx_read24(n1,f1,a1,&q,&x);
printf(" data= %li",data);
printf("\t Q= %i X= %i \n",q,x);
}
}
}
22 VC 16 - *00211.A0, 01/97
Software Licence Agreement
Program: VC16 libraries and test/demonstration program (OS-9 or IBM-PC version)
This software is copyrighted by W-I e
-N e
-R Plein & Baus GmbH. All rights reserved. Any duplication, reproduction, transfer or distribution of the software and the manual as well as of parts of them is not allowed without the express prior written consent of the publisher. Disassembly of code is prohibited.
We do not make representations or warranties to the contents or use of the program and the software description.
Further, we reserve the right to make changes to any and all parts of the software and the manual, at any time, without obligation to notify any person or entity of such changes.
W-I e
-N e
-R, Plein & Baus GmbH
Müllersbaum 20
D - 51399 Burscheid
Germany
Phone: (49) (0) 2174 - 678 0
FAX: (49) (0) 2174 - 678 555
E-Mail: [email protected]
URL: http://www.wiener-d.com
23 VC 16 - *00211.A0, 01/97
