STMicroelectronics LIS2DU12 Datasheet
Oglas
Oglas
LIS2DU12
Datasheet
Ultralow-power accelerometer with anti-aliasing & motion detection
Product status link
LIS2DU12
Product summary
Order code
Temperature range [°C]
Package
Packing
LIS2DU12TR
-40 to +85
LGA-12L
Tape and reel
Product resources
TN0018 (design and soldering)
Product label
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Features
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Supply voltage range from 1.62 to 3.6 V with independent IO supply
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Ultralow power consumption
– Normal mode with anti-aliasing filter: 6.1 µA
Ultralow-power mode: 0.47 µA
One-shot mode: 0.2 µA
– Power-down: 0.02 µA
Low noise down to 181 µg/√Hz
±2 g /±4 g /±8 g /±16 g full scales
ODR from 1.6 Hz to 800 Hz
Embedded temperature sensor
Embedded FIFO: up to 512 samples of accelerometer and temperature data in high resolution or up to 768 samples of acceleration data at low resolution
High-speed I²C/SPI/MIPI I3C ® digital output interface
Embedded digital functions (free-fall, wake-up, single/double-tap recognition, activity/inactivity, 6D/4D orientation)
Self-test
Small package: 2.0 x 2.0 x 0.74 (max) mm LGA 12-lead
10000 g high shock survivability
ECOPACK and RoHS compliant
Applications
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Wearable devices (wristband and smart watches)
Game controllers
Hearing aids and portable healthcare devices
True wireless stereo
Wireless sensor nodes
Motion-activated user interfaces (screen rotation, tap, double tap)
Asset trackers
Description
The LIS2DU12 is a linear 3-axis accelerometer with advanced digital functions whose MEMS and ASIC have been expressly designed to build an outstanding ultralow-power architecture in which the anti-aliasing filter operates with a current consumption among the lowest in the market.
The LIS2DU12 has user-selectable full scales of ±2 g /±4 g /±8 g /±16 g and is capable of measuring accelerations with output data rates from 1.6 Hz to 800 Hz.
The LIS2DU12 has an integrated 128-level FIFO buffer allowing to store a wide range of data, reducing system power consumption.
The embedded self-test capability allows the user to check that the sensor works in the final application.
The LIS2DU12 has a dedicated internal engine to process motion and acceleration detection including free-fall, wake-up, single/double-tap recognition, activity/inactivity, and 6D/4D orientation.
DS12422 - Rev 4 - November 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
LIS2DU12
The LIS2DU12 is available in a small 2.0 x 2.0 mm plastic land grid array package (LGA) only 0.74 mm thin, which places it among the smallest solution available in the market. It is guaranteed to operate over an extended temperature range from -40°C to + 85 °C.
DS12422 - Rev 4 page 2/56
1
1.1
LIS2DU12
Block diagram and pin description
Block diagram and pin description
Block diagram a
CHARGE
AMPLIFIER
X+
X-
X AAF
Y+
Y-
Y
Z+
Z-
Z
AAF
AAF
TEMPERATURE SENSOR
Figure 1. Block diagram
A/D
CONVERTER
CONTROL
LOGIC
2
I C
SPI
MIPI I3C
®
CS
SCL/SPC
SDA/SDO/SDI
SDO/SA0
SELF TEST REFERENCE
TRIMMING
CIRCUITS
CLOCK
128 Level
FIFO
CONTROL LOGIC
&
INTERRUPT GEN.
INT1
INT2
DS12422 - Rev 4 page 3/56
LIS2DU12
Pin description
1.2
Pin description
Figure 2. Pin connections
Z
X
1
Y
(TOPVIEW)
DIRECTION OF THE
DETECTABLE
ACCELERATIONS
Vdd_IO 10
Vdd 9
GND 8
RES 7
11 12
6 5
1 SCL/SPC
2 CS
3 SDO/SA0
4 SDA/SDI/SDO
(BOTTOM VIEW)
Table 1. Pin description
Pin#
2
3
1
4
7
8
9
5
6
10
11
Name
Interrupt pin 1
Function
SCL
SPC
CS
I²C/MIPI I3C ® serial clock (SCL)
SPI serial port clock (SPC)
SPI/I²C/MIPI I3C ® mode selection
(1: SPI idle mode / I²C/MIPI I3C ® enabled;
0: SPI enabled / I²C/MIPI I3C ® disabled)
SDO
SA0
SDA
SDI
SDO
SPI serial data output (SDO)
I²C less significant bit of the device address (SA0)
I²C/MIPI I3C ® serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
Internally not connected. Can be tied to Vdd, Vdd_IO, or GND.
0 V supply
NC
GND
RES
GND
Vdd
Connect to GND
0 V supply
Power supply
Vdd_IO Power supply for I/O pins
INT2
INT1
Interrupt pin 2. Clock input when selected in single data conversion on demand.
1. CS and SDO/SA0 pins are internally pulled up. The pull-up of the CS pin can be disconnected by setting bit CS_PU_DIS of
to 1.
2. The INT1 and INT2 pins are internally pulled down. The internal pull-down of the INT1 pin can be disconnected by setting
the PD_DIS_INT1 bit in IF_CTRL (0Eh)
to 1. The internal pull-down of the INT2 pin can be disconnected by setting the
PD_DIS_INT2 bit in MD2_CFG (20h) to 1.
DS12422 - Rev 4 page 4/56
2
2.1
LIS2DU12
Mechanical and electrical specifications
Mechanical and electrical specifications
Mechanical characteristics
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted.
The product is factory calibrated at 1.8 V. The operational power supply range is from 1.62 V to 3.6 V.
Symbol Parameter
Table 2. Mechanical characteristics
Test conditions
FS Measurement range
So Sensitivity
An Noise density - normal mode
TyOff Zerog
TCO Zerog offset change vs. temperature
TCS Sensitivity change vs. temperature
ST Self-test positive difference
@ FS ±2 g
@ FS ±4 g
@ FS ±8 g
@ FS ±16 g
@ FS ±8 g
ODR = 800 Hz, BW = ODR/2
X-axis
Y-axis
Z-axis
Min.
Typ.
±2
±4
±8
±16
0.976
1.952
3.904
7.808
Max.
Unit g m g /digit
287
±11
±1
±0.035
µ g /√Hz m g m g /°C
%/°C
50
50
200
700
700
1200 m g
1. Typical specifications are not guaranteed.
2. Values after factory calibration test and trimming.
DS12422 - Rev 4 page 5/56
LIS2DU12
Electrical characteristics
2.2
Electrical characteristics
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted.
The product is factory calibrated at 1.8 V. The operational power supply range is from 1.62 V to 3.6 V.
Table 3. Electrical characteristics
Symbol
Vdd Supply voltage
Parameter
Vdd_IO I/O pins supply voltage (2)
Test conditions Min.
1.62
1.62
1.8
Max.
3.6
Vdd + 0.1
Unit
V
V
IddNM Current consumption in normal mode
IddULP Current consumption in ultralow-power mode
FS = ±8 g
ODR = 800 Hz,
BW = ODR/2 with anti-aliasing filter
FS = ±8 g
ODR = 1.6 Hz,
BW = ODR/2
6.1
0.47
µA
µA
Idd_PD Current consumption in power-down
V
IH
V
IL
Digital high-level input voltage
Digital low-level input voltage
V
OH
V
OL
Digital high-level output voltage
Digital low-level output voltage
I
OH
= 4 mA
I
OL
0.7*Vdd_IO
Vdd_IO - 0.2 V
20
0.3*Vdd_IO
0.2 V
1. Typical specifications are not guaranteed.
2. It is possible to remove Vdd, maintaining Vdd_IO without blocking the communication busses. In this condition the measurement chain is powered off.
3. 4 mA is the maximum driving capability, ie. the maximum DC current that can be sourced/sunk by the digital pin in order to guarantee the correct digital output voltage levels V
OH
and V
OL
.
V nA
V
2.3
Temperature sensor characteristics
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted.
Table 4. Temperature sensor characteristics
Symbol Parameter
Top
Toff
Operating temperature range
Temperature offset
Temperature sensor output change vs. temperature TSDr
TODR Temperature refresh rate
1. Typical specifications are not guaranteed.
2. The output of the temperature sensor is 0 LSB (typ.) at 25 °C.
3. 12-bit resolution.
Min.
-40
-15
ODR
Max.
+85
+15
Unit
°C
°C
°C/LSB
Hz
DS12422 - Rev 4 page 6/56
2.4
2.4.1
Note:
LIS2DU12
Communication interface characteristics
Communication interface characteristics
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 5. SPI slave timing values
Value
Symbol Parameter Unit
Min Max t c(SPC) f c(SPC) t su(CS) t h(CS) t su(SI) t h(SI) t v(SO) t h(SO) t dis(SO)
SPI clock cycle
SPI clock frequency
CS setup time
CS hold time
SDI input setup time
SDI input hold time
SDO valid output time
SDO output hold time
SDO output disable time
100
6
40
12
15
9
10
50
50
1. 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production.
ns
MHz ns
Figure 3. SPI slave timing diagram
CS t su(CS) t c(SPC) t h(CS)
SPC
SDI t su(SI)
MSB IN t h(SI) t v(SO)
MSB OUT t h(SO)
LSB IN t dis(SO)
LSB OUT SDO
Measurement points are done at 0.3·Vdd_IO and 0.7·Vdd_IO for both input and output ports.
DS12422 - Rev 4 page 7/56
2.4.2
Note:
LIS2DU12
Communication interface characteristics
I²C - inter-IC control interface
Subject to general operating conditions for Vdd and Top.
Table 6. I²C slave timing values
Symbol f
(SCL) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t h(ST) t su(SR) t su(SP) t w(SP:SR)
SCL clock frequency
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
Parameter
START/REPEATED START condition hold time
REPEATED START condition setup time
STOP condition setup time
Bus free time between STOP and START condition
Min
0
1.3
0.6
100
0
0.6
0.6
0.6
1.3
Max
400
0.9
Min
0
0.5
0.26
50
0
0.26
0.26
0.26
0.5
Max
1000
Data valid time
Data valid acknowledge time
0.9
0.9
0.45
0.45
C
B
Capacitive load for each bus line 400 550
1. Data based on standard I²C protocol requirement, not tested in production.
2. Data for I²C fast mode and I²C fast mode plus have been validated by characterization, not tested in production.
Unit kHz
µs ns
µs pF
Figure 4. I²C slave timing diagram
REPEATED
START
START t su(SR)
START
SDA t w(SP:SR) t su(SDA) t h(SDA) t su(SP)
STOP
SCL t h(ST) t w(SCLL) t w(SCLH)
Measurement points are done at 0.3·Vdd_IO and 0.7·Vdd_IO for both ports.
DS12422 - Rev 4 page 8/56
2.5
Note:
LIS2DU12
Absolute maximum ratings
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Symbol
Vdd
Vdd_IO
Vin
A
POW
Table 7. Absolute maximum ratings
Ratings
Supply voltage
I/O pins supply voltage
Input voltage on any control pin
(CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)
Acceleration (any axis, powered, Vdd = 1.8 V)
A
UNP
T
OP
T
STG
ESD
Acceleration (any axis, unpowered)
Operating temperature range
Storage temperature range
Electrostatic discharge protection
Maximum value
-0.3 to 4.3
-0.3 to 4.3
-0.3 to Vdd_IO+0.3
3000 g for 0.5 ms
10000 g for 0.2 ms
3000 g for 0.5 ms
10000 g for 0.2 ms
-40 to +85
-40 to +125
2 (HBM)
Unit
V
V
V g g g g
°C
°C kV
Supply voltage on any pin should never exceed 4.3 V.
This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part.
DS12422 - Rev 4 page 9/56
3
3.1
3.1.1
3.1.2
3.2
3.2.1
3.2.2
3.2.3
LIS2DU12
Terminology and functionality
Terminology and functionality
Terminology
Sensitivity
Sensitivity describes the gain of the sensor and can be determined by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the Earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and time. The sensitivity tolerance describes the range of sensitivities of a large population of sensors.
Zero-g level offset
Zerog level offset describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface measures 0 g on the X-axis and 0 g on the Y-axis whereas the Z-axis measures 1 g . The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as two’s complement number). A deviation from ideal value in this case is called zerog level offset. Offset is to some extent a result of stress to the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Zerog level offset change vs. temperature”.
Functionality
Operating modes
The LIS2DU12 has 3 operating modes: normal, ultralow-power and one-shot mode. In normal mode, an aggressive anti-aliasing filter is active regardless, but the overall current consumption remains extraordinarily low (refer to
).
Single data conversion on-demand modes
The device features two single data conversion on-demand modes: one-shot triggered by the INT2 pin, and one-shot triggered by the I²C/SPI/I3C digital interface.
Self-test
Self-test mode allows checking the sensor functionality without moving it, applying an actuation force to the sensor and simulating a definite input acceleration.
DS12422 - Rev 4 page 10/56
3.2.4
3.2.5
3.2.6
LIS2DU12
Functionality
Activity/inactivity, Android stationary/motion detection functions
The activity/inactivity function recognizes the device’s sleep state and allows reducing system power consumption.
When the activity/inactivity function is activated by setting the SLEEP_ON bit in
, the device automatically goes to the inactivity output data rate selected by the INACT_ODR[1:0] bits in register
With this feature the system may be efficiently switched from low-power mode to full performance depending on user-selectable positioning and acceleration events, thus ensuring power saving and flexibility.
The Android stationary/motion detection function only recognizes the device’s sleep state.
When the Android stationary/motion detection function is activated by setting to a STATIONARY condition the
INACT_ODR[1:0] bits in register
CTRL4 (13h) , the device detects acceleration below a fixed threshold but does
not change the ODR after sleep state detection.
The activity/inactivity recognition and Android stationary/motion detection functions are activated by writing the desired threshold in the
register. The high-pass filter is automatically enabled.
If the device is in sleep (inactivity/stationary) mode, when at least one of the axes exceeds the threshold in
, the device goes into a sleep-to-wake state (as wake-up).
For the activity/inactivity function, the device, in a wake-up state, returns to the ODR before sleep state detection.
Activity/inactivity, Android stationary/motion detection threshold and duration can be configured in the following control registers:
•
•
•
•
High tap/double-tap user configurability
The device embeds the possibility to select the following parameters: single axis or multiple axes in
axis priority in
threshold value of each axis in
,
max time threshold between two consecutive taps for double-tap recognition, min time threshold between
two consecutive taps to detect a new tap event in INT_DUR (1Bh)
Interrupt event recognition
The device may be configured to generate interrupt signals coming from an independent inertial wake-up/free-fall event or from the position of the device itself. Thresholds and timing of this interrupt generator are programmable by the end user in runtime.
Automatic programmable sleep-to-wake-up and return-to-sleep functions are also available for enhanced power saving.
The device interrupts signal can behave as:
•
•
•
•
•
Free-fall: 3-axis subthreshold recognition;
Wake-up: axis recognition;
Wake-to-sleep: change of state recognition active-sleep (also known as activity-inactivity);
6D and 4D orientation detection: change of position recognition;
Tap-tap: single, double, axis and sign recognition.
All these functions are parallel but during sleep it is not possible to recognize a tap-tap event. All these signals can be driven to the two interrupt pins (INT1 and INT2) through registers
.
1.
It is possible to configure the duration of the interrupt using the LIR and INT_SHORT_EN bits in
as shown in the following table.
DS12422 - Rev 4 page 11/56
3.3
3.4
3.5
3.6
LIS2DU12
Sensing element
LIR
0
1
Table 8. Configuration of duration of interrupt
INT_SHORT_EN
0
1
Interrupt level mode
Interrupt latched mode
Interrupt type
•
•
Interrupt level mode: the interrupt signal goes high when an interrupt event occurs and is reset when the acceleration data fall below the threshold.
Interrupt latched mode: the interrupt signal is the OR between the interrupt flags that are monitored on the INT1/INT2 pins. The interrupt signal goes high when interrupt event occurs and is reset when
is read. The status flags inside the interrupt source registers are coherent with the behavior of the INT1/INT2 pins. The interrupt generator block is inhibited for 1 ODR after the interrupt event.
Sensing element
A proprietary process is used to create a surface micromachined accelerometer. The technology allows processing suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. In order to be compatible with the traditional packaging techniques, a cap is placed on top of the sensing element to avoid blocking the moving parts during the molding phase of the plastic encapsulation. When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor.
At steady-state the nominal value of the capacitors are a few pF and when an acceleration is applied, the maximum variation of the capacitive load is in the fF range.
IC interface
The complete measurement chain is composed of a low-noise capacitive amplifier which converts the capacitive unbalancing of the MEMS sensor into an analog voltage using an analog-to-digital converter.
The acceleration data may be accessed through an I²C/SPI/MIPI I3C ® interface thus making the device particularly suitable for direct interfacing with a microcontroller.
The LIS2DU12 features a data-ready signal which indicates when a new set of measured acceleration data is available, thus simplifying data synchronization in the digital system that uses the device.
Factory calibration
The IC interface is factory-calibrated for sensitivity (So) and zerog level offset.
The trim values are stored inside the device in nonvolatile memory. Any time the device is turned on, the trimming parameters are downloaded into the registers to be used during active operation. This allows using the device without further calibration. If an accidental write occurs in the registers where the trimming parameters are stored, the BOOT bit in
CTRL4 (13h) can help to retrieve the correct trimming parameters from nonvolatile memory
without the need to switch on/off the device. This bit is automatically reset at the end of the download operation.
Setting this bit has no impact on the control registers.
Temperature sensor
The temperature is available in OUT_T_L (2Eh)
,
stored as two's complement data, left-justified in
12-bit mode and duplicated in registers TEMP_OUT_L (30h) - TEMP_OUT_H (31h)
.
Refer to
Table 4. Temperature sensor characteristics for the conversion factor.
DS12422 - Rev 4 page 12/56
4
LIS2DU12
Application hints
Application hints
Figure 5. LIS2DU12 electrical connections (top view)
SCL/SPC
1
CS
2
SDO/SA0
3
SDA/SDI/SDO
4
12 11
5 6
10
Vdd_IO
9
Vdd
8
GND
7
RES
Vdd_IO
100nF
GND
Vdd
10µF
100nF
GND
HOST
I 2 C /
MIPI I3C /
SPI (3/4-w)
LIS2DU12
I 2 C configuration
Vdd_IO
R pu
SCL
SDA
Pull-up to be added
R pu
=10kOhm
R pu
The device core is supplied through the Vdd line while the I/O pins are supplied through the Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF aluminum) should be placed as near as possible to pin 9 of the device (common design practice).
All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to
). It is possible to remove Vdd while maintaining Vdd_IO without blocking the communication bus, in this condition the measurement chain is powered off.
The functionality of the device and the measured acceleration data are selectable and accessible through the
I²C/MIPI I3C ® or SPI interfaces. When using the I²C, CS must be tied high (that is, connected to Vdd_IO).
The functions, the threshold and the timing of the two interrupt pins (INT1 and INT2) can be completely programmed by the user through the I²C/MIPI I3C ® /SPI interface.
DS12422 - Rev 4 page 13/56
LIS2DU12
Application hints
Table 9. Internal pin status
Pin # Name Function Pin status
1
2
3
SCL
SPC
CS
SDO
SA0
I²C/MIPI I3C ® serial clock (SCL)
SPI serial port clock (SPC)
SPI/I²C/MIPI I3C ® mode selection
1: SPI idle mode / I²C/MIPI I3C ® enabled
0: SPI enabled / I2C/MIPI I3C ® disabled
Serial data output (SDO)
I²C less significant bit of the device address (SA0)
4
SDA
SDI
SDO
I²C/MIPI I3C ® serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
NC Internally not connected. Can be tied to Vdd, Vdd_IO, or GND.
5
6
7
8
9
GND 0 V supply
RES Connect to GND
GND
Vdd
0 V supply
Power supply
10 Vdd_IO Power supply for I/O pins
11 INT2 Interrupt pin 2. Clock input when selected in single data conversion on demand.
Default: input without pull-up
Default: input with internal pull-up
Default: input with internal pull-up
Default: (SDA) input without pull-up
12 INT1 Interrupt pin 1
Default: input with internal pull-down (1)(2)
Default: input with internal pull-down
2. In order to disable the internal pull-down on the INT2 pin, write 1 to the PD_DIS_INT2 bit in
.
registers. The internal pull-down can be disconnected by setting the PD_DIS_INT1 bit of register
to 1.
When this is done, the INT1 pin needs to be externally biased. If INT1 = Vdd, only the SPI and I3C interfaces are available. If INT1 = GND, then the I²C, I3C and SPI interfaces are active.
DS12422 - Rev 4 page 14/56
5
5.1
5.1.1
5.1.2
LIS2DU12
Digital main blocks
Digital main blocks
FIFO
The LIS2DU12 embeds 128 slots of 12-bit FIFO data for each of the three output channels X, Y and Z of acceleration data and 12-bit FIFO data for temperature data. This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO.
In order to maximize the amount of data collected in FIFO, it is possible to double the slots of FIFO data (from 128 to 256) by writing the FIFO_DEPTH bit in
FIFO_CTRL (15h) with 2X depth mode.
When this mode is enabled, the most significant 8 bits for each acceleration axis are stored in FIFO. Each FIFO data word contains data of two consecutive ODRs, the actual and the previous one. The temperature data is no longer stored in FIFO but is available in the
TEMP_OUT_L (30h) and TEMP_OUT_H (31h) registers.
In high-resolution batch mode, accelerometer and temperature FIFO are stored in FIFO as 12 bits at ODR.
In 2X depth batch mode, each word contains two accelerometer data as 8 bits in FIFO at ODR/2.
The FIFO buffer can work according to six different modes:
•
•
•
•
•
Bypass mode
FIFO mode
Continuous mode
Continuous-to-FIFO mode
Bypass-to-continuous
• Bypass-to-FIFO
watermark is selected in the
generate dedicated interrupts on the INT1 and INT2 pins using the
The FTH bit in FIFO_STATUS1 (26h)
register goes to 1 when the number of unread samples is greater than or
equal to FTH[6:0] in FIFO_WTM (16h) . If FTH[6:0] is equal to 0, the FTH bit in
goes to 0.
The FIFO_OVR bit in FIFO_STATUS1 (26h) is equal to 1 if a FIFO sample is overwritten.
FSS[7:0] in FIFO_STATUS2 (27h) contains stored data levels of unread samples.
When FSS[7:0] is equal to 00000000, FIFO is empty. When FSS[7:0] is equal to 10000000, FIFO is full and the unread samples are 128.
Bypass mode
In bypass mode
FIFO_CTRL (15h) (FIFO_MODE[2:0] = 000), the FIFO is not operational, no data is collected in
FIFO memory, and it remains empty with only the actual sample available in the output registers.
Bypass mode is also used to reset the FIFO when in FIFO mode.
For each channel only the first address is used. When new data is available, the old data is overwritten.
FIFO mode
In FIFO mode
FIFO_CTRL (15h) (FIFO_MODE[2:0] = 001) data from the output channels are stored in the FIFO
memory until it is full. When 128 unread samples are stored in memory, data collecting is stopped.
001.
DS12422 - Rev 4 page 15/56
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
LIS2DU12
FIFO
Continuous mode
Continuous mode FIFO_CTRL (15h)
(FIFO_MODE[2:0] = 110) provides a continuous FIFO update: when 128 unread samples are stored in memory, as new data arrives, the oldest data is discarded and overwritten by the newer.
FIFO is greater than or equal to FTH[6:0] in FIFO_WTM (16h)
.
or to
the INT2 pin by writing the INT2_F_FTH bit to 1 in register CTRL3 (12h)
.
is asserted.
Continuous-to-FIFO mode
In continuous-to-FIFO mode FIFO_MODE[2:0] = 011 in the
FIFO_CTRL (15h) register, FIFO operates in
continuous mode and FIFO mode starts upon an edge trigger event. When the FIFO is full, data collecting is stopped. The trigger event could be single or double-tap, wake-up, free-fall, 6D interrupt or any combination of these events, but every interrupt has to be routed to the corresponding pin to be used as a trigger.
Bypass-to-continuous mode
In bypass-to-continuous mode FIFO_CTRL (15h)
(FIFO_MODE[2:0] = 100), data measurement storage inside
FIFO starts in continuous mode upon an edge trigger event.
The trigger event could be single or double-tap, wake-up, free-fall, 6D interrupt, or any combination of these events, but every interrupt has to be routed to the corresponding pin to be used as a trigger.
The sample that generated the trigger is available in FIFO.
Bypass-to-FIFO
In bypass-to-FIFO mode
FIFO_CTRL (15h) (FIFO_MODE_[2:0] = 111), data measurement storage inside FIFO
operates in FIFO mode when selected triggers are equal to 1, otherwise FIFO content is reset (bypass mode).
The trigger event could be single or double-tap, wake-up, free-fall, 6D interrupt, or any combination of these events, but every interrupt has to be routed to the corresponding pin to be used as a trigger.
The sample that generated the trigger is available in FIFO.
•
•
•
Output data read sequence from FIFO
Automatic address increment is provided to minimize interface transfer.
In high-resolution batching mode, if both the accelerometer and temperature data are read from FIFO, a read
operation is automatically performed from 8 output registers for every FIFO word ( OUT_X_L (28h) -
).
If only accelerometer data are read from FIFO, a read operation is automatically performed from 6
output registers for every FIFO word, skipping temperature data ( OUT_X_L (28h) –
ROUNDING_XYZ bit in the
register must be written to enable this rounding of the read address.
). In this case, the rounding of the read address is automatically enabled.
If the IF_ADD_INC bit of register
CTRL1 (10h) is set to 1, all FIFO words can be read in a single interface
transfer. Different read modes using a single interface transfer supported by the LIS2DU12 are:
FIFO_STATUS_2 register + N* FIFO_WORDS
FIFO_STATUS_1 register + FIFO_STATUS_2 register + N* FIFO_WORDS
TEMP_OUT + FIFO_STATUS_1 register + FIFO_STATUS_2 register + N* FIFO_WORDS
DS12422 - Rev 4 page 16/56
5.1.8
LIS2DU12
FIFO
FIFO empty condition
When FIFO is emptied, a special value is used in order to recognize an empty condition and no duplicated samples are read.
In high-resolution batch mode, the least significant 4 bits of data read during an empty condition are 1111.
In 2X depth mode the empty condition corresponds to 7Fh code. The accelerometer data are assigned to 7Eh in order to discriminate the empty condition.
DS12422 - Rev 4 page 17/56
6
6.1
LIS2DU12
Digital interfaces
Digital interfaces
The registers embedded inside the LIS2DU12 may be accessed through both the I²C, MIPI I3C ® and SPI serial interfaces. The latter may be software configured to operate either in 3-wire or 4-wire interface mode.
The serial interfaces are mapped to the same pins. To select/exploit the I²C/MIPI I3C ® interface, the CS line must be tied high (that is, connected to Vdd_IO).
Pin name
CS
SCL
SPC
SDA
SDI
SDO
SA0
SDO
Table 10. Serial interface pin description
SPI/I²C/MIPI I3C ® mode selection
1: SPI idle mode / I²C/MIPI I3C ® enabled
0: SPI enabled / I²C/MIPI I3C ® disabled
I²C/MIPI I3C ® serial clock (SCL)
SPI serial port clock (SPC)
I²C/MIPI I3C ® serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
I²C address selection (SA0)
SPI serial data output (SDO)
Pin description
I²C serial interface
The LIS2DU12 I²C is a bus slave. The I²C is employed to write data into registers whose content can also be read back.
The relevant I²C terminology is given in the table below.
Table 11. I²C terminology
Term
Transmitter The device that sends data to the bus
Receiver
Master
Slave
The device that receives data from the bus
Description
The device that initiates a transfer, generates clock signals, and terminates a transfer
The device addressed by the master
There are two signals associated with the I²C bus: the serial clock line (SCL) and the serial data line (SDA).
The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both lines must be connected to Vdd_IO through an external pull-up resistor. When the bus is free, both the lines are high.
The I²C interface is implemented with fast mode (400 kHz) I²C standards as well as with fast mode plus
(1000 kHz).
In order to disable the I²C block,
(I2C_DISABLE) = 1 must be set.
DS12422 - Rev 4 page 18/56
LIS2DU12
I²C serial interface
6.1.1
I²C operation
The transaction on the bus is started through a start (ST) signal. A start condition is defined as a high to low transition on the data line while the SCL line is held high. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master.
The slave address (SAD) associated to the LIS2DU12 is 001100xb where the x bit is modified by the SA0/SDO pin in order to modify the device address. If the SA0/SDO pin is connected to the supply voltage, the address is
0011001b, otherwise if the SA0/SDO pin is connected to ground, the address is 0011000b. This solution permits to connect and address two different accelerometers to the same I²C lines.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.
The I²C embedded inside the LIS2DU12 behaves like a slave device and the following protocol must be adhered to. After the start condition (ST), a slave address is sent. Once a slave acknowledge (SAK) has been returned, an
(IF_ADD_INC) bit defines the address increment.
The slave address is completed with a read/write bit. If the bit is 1 (read), a repeated start (SR) condition must be issued after the two subaddress bytes. If the bit is 0 (write) the master transmits to the slave with direction unchanged.
Table 12 explains how the SAD+read/write bit pattern is composed, listing all the possible
configurations.
Command
Read
Write
Read
Write
SAD[6:1]
001100
001100
001100
001100
Table 12. SAD+read/write patterns
SAD[0] = SA0
0
0
1
1
R/W
1
0
1
0
SAD+R/W
00110001 (31h)
00110000 (30h)
00110011 (33h)
00110010 (32h)
ST
Table 13. Transfer when master is writing one byte to slave
SAD + W SUB DATA
SAK SAK SAK
SP Master
Slave
Master
Slave
ST
Table 14. Transfer when master is writing multiple bytes to slave
SAD + W SUB DATA DATA
SAK SAK SAK SAK
ST
Table 15. Transfer when master is receiving (reading) one byte of data from slave
SAD + W SUB SR SAD + R
SAK SAK SAK DATA
NMAK
SP
Master
Slave
SP
Master
Slave
ST
Table 16. Transfer when master is receiving (reading) multiple bytes of data from slave
SAD+
W
SUB SR
SAD+
R
MAK MAK
SAK SAK SAK DATA DATA DATA
NMAK SP
DS12422 - Rev 4 page 19/56
6.2
LIS2DU12
SPI bus interface
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit (MSb) first. If a slave receiver doesn’t acknowledge the slave address (that is, it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. The master can then abort the transfer. A low to high transition on the
SDA line while the SCL line is high is defined as a stop condition. Each data transfer must be terminated by the generation of a stop (SP) condition.
In the presented communication format MAK is master acknowledge and NMAK is no master acknowledge.
SPI bus interface
The LIS2DU12 SPI is a bus slave. The SPI allows writing to and reading from the registers of the device.
The serial interface interacts with the application using 4 wires: CS , SPC , SDI and SDO .
Figure 6. Read and write protocol
CS
SPC
SDI
SDO
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS enables the serial port and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are respectively the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC .
Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC . The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS .
bit 0 : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In the latter case, the chip drives SDO at the start of bit 8.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands additional blocks of 8 clock periods are added. When the CTRL1 (10h)
(IF_ADD_INC) bit is 1, the address used to read/write data is increased at every block.
The function and the behavior of SDI and SDO remain unchanged.
DS12422 - Rev 4 page 20/56
6.2.1
LIS2DU12
SPI bus interface
SPI read
Figure 7. SPI read protocol
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0 : READ bit. The value is 1.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
bit 16-...
: data DO(...-8). Additional data in multiple byte reads.
Figure 8. Multiple byte SPI read protocol (2-byte example)
CS
SPC
SDI
SDO
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11DO10 DO9 DO8
DS12422 - Rev 4 page 21/56
6.2.2
LIS2DU12
SPI bus interface
SPI write
Figure 9. SPI write protocol
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
The SPI write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0 : WRITE bit. The value is 0.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DI(7:0) (write mode). This is the data that is written inside the device (MSb first).
bit 16-... : data DI(...-8). Additional data in multiple byte writes.
Figure 10. Multiple byte SPI write protocol (2-byte example)
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
DS12422 - Rev 4 page 22/56
6.2.3
LIS2DU12
SPI bus interface
SPI read in 3-wire mode
3-wire mode is entered by setting the
CTRL1 (10h) (SIM) bit equal to 1 (SPI serial interface mode selection).
Figure 11. SPI read protocol in 3-wire mode
CS
SPC
SDI/O
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI read command is performed with 16 clock pulses: bit 0 : READ bit. The value is 1.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
A multiple read command is also available in 3-wire mode.
DS12422 - Rev 4 page 23/56
6.3
6.3.1
LIS2DU12
MIPI I3C® interface
MIPI I3C
®
interface
MIPI I3C
®
slave interface
The LIS2DU12 interface includes an MIPI I3C ® SDR only slave interface able to work up to 8 MHz of the SCL frequency (compliant with release 1.0 of the specification) with MIPI I3C ® SDR embedded features:
•
•
•
•
•
•
CCC command
Direct CCC communication (SET and GET)
Broadcast CCC communication
Private communications
Private read and write for single byte
Multiple read and write
• In-band interrupt request
Refer to
Section 6.4 I²C/I3C coexistence in LIS2DU12 for details concerning the choice of the interface when
powering up the device.
DS12422 - Rev 4 page 24/56
6.3.2
LIS2DU12
MIPI I3C® interface
MIPI I3C
®
CCC supported commands
The list of MIPI I3C ® CCC commands supported by the device is detailed in the following table.
Table 17. MIPI I3C ® CCC commands
Command
SETDASA
ENEC
DISEC
ENTAS0
ENTAS1
ENTAS2
ENTAS3
RSTDAA
SETMWL
SETMRL
SETNEWDA
GETMWL
GETMRL
GETPID
GETBCR
GETDCR
GETSTATUS
GETMXDS
Command code
0x87
0x80 / 0x00
0x81/ 0x01
0x82 / 0x02
0x83 / 0x03
0x84 / 0x04
0x85 / 0x05
0x86 / 0x06
0x89 / 0x08
0x8A / 0x09
0x88
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
0x94
Default Description
Assign dynamic address using static address.
Static address values are: 0x18/0x19 depending on SDO pin if I2C_SA1 bit in register
is equal to 0.
Slave activity control (direct and broadcast)
Slave activity control (direct and broadcast)
Enter activity state (direct and broadcast)
Enter activity state (direct and broadcast)
Enter activity state (direct and broadcast)
Enter activity state (direct and broadcast)
Reset the assigned dynamic address (direct and broadcast)
Define maximum write length during private write (direct and broadcast)
Define maximum read length during private read (direct and broadcast)
Change dynamic address
0x02
0x08
0x00
0x45
0x10
0x0B
0x07
(1 byte)
0x00
0x08
(2 byte)
0x00
0x10
0x04
(3 byte)
Get maximum write length during private write
Get maximum read length during private read
Device ID register
Bus characteristics register
0x41 default MIPI I3C ® device characteristics register
0x00
0x00
(2 byte)
Status register
0x01
0x39
(2 byte)
Return max data speed
DS12422 - Rev 4 page 25/56
6.4
LIS2DU12
I²C/I3C coexistence in LIS2DU12
•
•
I²C/I3C coexistence in LIS2DU12
In the LIS2DU12, the SDA and SCL lines are common to both I²C and I3C. The I²C bus requires anti-spike filters on the SDA and SCL pins that are not compatible with I3C timing.
The device can be connected to both I²C and I3C or only to the I3C bus depending on the connection of the INT1 pin when the device is powered up:
INT1 pin floating (internal pull-down): I²C/I3C both active, see
INT1 pin connected to Vdd_IO: only I3C active, see Figure 13
Figure 12. I²C and I3C both active (INT1 pin not connected)
INT1 pin not connected
I²C/I3C both active
I²C/I3C
(both active)
I²C bus case I3C bus case
Master sends
I²C r/w
Master assigns DA to the slave
(1)
Master resets
DA
Slave performs requested r/w
I3C private R/W with and without 7Eh
CCC commands
Slave event management
Error detection and recovery
1.
Address assignment (SETDASA) must be performed with I²C fast mode plus timing. When the slave is addressed, the I²C slave is disabled and the timing is compatible with I3C specifications.
Figure 13. Only I3C active (INT1 pin connected to Vdd_IO)
INT1 pin connected to Vdd_IO
Only I3C active
I²C/I3C I3C bus case
Dynamic
Address
Assignment
(1)
Master resets
DA
I3C private R/W with and without 7Eh
CCC commands
Slave event management
Error detection and recovery
1.
When the slave is I3C only, the I²C slave is always disabled. The address can be assigned using I3C SDR timing.
DS12422 - Rev 4 page 26/56
7
DS12422 - Rev 4
LIS2DU12
Register mapping
Register mapping
Name
IF_PU_CTRL
IF_CTRL
CTRL1
CTRL2
CTRL3
CTRL4
CTRL5
FIFO_CTRL
FIFO_WTM
INTERRUPT_CFG
TAP_THS_X
TAP_THS_Y
TAP_THS_Z
INT_DUR
WAKE_UP_THS
WAKE_UP_DUR
FREE_FALL
MD1_CFG
MD2_CFG
WAKE_UP_SRC
TAP_SRC
SIXD_SRC
ALL_INT_SRC
STATUS
FIFO_STATUS1
FIFO_STATUS2
OUT_X_L
OUT_X_H
OUT_Y_L
OUT_Y_H
OUT_Z_L
OUT_Z_H
OUT_T_L
OUT_T_H
TEMP_OUT_L
The table given below provides a list of the 8-bit registers embedded in the device and the corresponding addresses.
Table 18. Register map
1F
20
21
22
23
18
19
1A
1B
1C
1D
1E
Hex
0C
0E
10
11
12
13
14
15
16
17
29
2A
2B
2C
2D
2E
2F
30
24
25
26
27
28
Register address
00011000
00011001
00011010
00011011
00011100
00011101
00011110
00011111
00100000
00100001
00100010
00100011
Binary
00001100
00001110
00010000
00010001
00010010
00010011
00010100
00010101
00010110
00010111
00100100
00100101
00100110
00100111
00101000
00101001
00101010
00101011
00101100
00101101
00101110
00101111
00110000
RW
RW
R
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
R
R
R
R
R
R
Comment Default
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000 page 27/56
LIS2DU12
Register mapping
Name
TEMP_OUT_H
WHO_AM_I
ST_SIGN
R
R
RW
1. R = read-only register, RW = readable/writable register
Hex
Register address
Binary
31
43
58
00110001
01000011
01011000
Default
00000000
01000101
110XXXXX
Comment
Reserved registers must not be changed. Writing to those registers may cause permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
DS12422 - Rev 4 page 28/56
8
8.1
8.2
LIS2DU12
Register description
Register description
IF_PU_CTRL (0Ch)
RW
This register contains bits to control the pull-ups of SDO, SDA and CS, modifying a default state.
Table 19. IF_PU_CTRL register
SDO_PU
_DIS
SDA_PU_EN 0
0
1. This bit must be set to 0 for the correct operation of the device.
0
CS_PU_DIS 0
SDO_PU_DIS
SDA_PU_EN
CS_PU_DIS
Table 20. IF_PU_CTRL register description
If 1, disconnects the internal pull-up of the SDO pin.
If 1, connects the internal pull-up of the SDA pin.
If 1, disconnects the internal pull-up of the CS pin.
IF_CTRL (0Eh)
RW
Table 21. IF_CTRL register
0
0
0
0
1. This bit must be set to 0 for the correct operation of the device.
0
PD_DIS
_INT1
PD_DIS_INT1
I3C_DISABLE
I2C_DISABLE
Table 22. IF_CTRL register description
If 1, pull-down of INT1 is disabled.
If 1, MIPI I3C ® interface is disabled.
If 1, I²C interface is disabled.
I3C_
DISABLE
0
I2C_
DISABLE
DS12422 - Rev 4 page 29/56
8.3
8.4
LIS2DU12
CTRL1 (10h)
CTRL1 (10h)
RW
PP_OD SIM
SW_
RESET
Table 23. CTRL1 register
IF_ADD_
INC
DRDY_
PULSED
WU_X_EN WU_Y_EN WU_Z_EN
Table 24. CTRL1 register description
PP_OD
SIM
SW_RESET
Push-pull/open-drain mode for INT pins
(0: INT pins in push-pull mode (default);
1: INT pins in open-drain mode)
SPI 3 or 4-wire mode
(0: 4-wire SPI (default); 1: 3-wire SPI)
Software reset, resets all CTRL registers to their default values. The software reset procedure has to be executed with the accelerometer in power-down mode.
IF_ADD_INC
Register address is automatically incremented during a multiple-byte access with a serial interface.
(0: disabled (default);
1: enabled)
DRDY_PULSED
Enables pulsed data-ready mode
(0: data-ready latched mode (returns to 0 only after reading over an interface) (default);
1: data-ready pulsed mode (the data-ready pulses are typ. 90 µs long))
WU_X_EN
WU_Y_EN
WU_Z_EN
Enables wake-up event detection status on X-axis. Default value: 0 (0: disabled; 1: enabled)
Enables wake-up event detection status on Y-axis. Default value: 0 (0: disabled; 1: enabled)
Enables wake-up event detection status on Z-axis. Default value: 0 (0: disabled; 1: enabled)
CTRL2 (11h)
RW
Table 25. CTRL2 register
INT1_
BOOT
INT1_F_
FULL
INT1_F_
FTH
INT1_F_
OVR
1. This bit must be set to 0 for the correct operation of the device.
INT1_
DRDY
0
0
INT1_BOOT
INT1_F_FULL
INT1_F_FTH
INT1_F_OVR
INT1_DRDY
Table 26. CTRL2 register description
Enables boot status on INT1 pin. Default value: 0 (0: disabled; 1: enabled)
Enables FIFO full on INT1 pin. Default value: 0 (0: disabled; 1: enabled)
Enables FIFO threshold interrupt on INT1 pin. Default value: 0 (0: disabled; 1: enabled)
Enables overrun interrupt on INT1 pin. Default value: 0 (0: disabled; 1: enabled)
Enables data-ready interrupt on INT1 pin. Default value: 0 (0: disabled; 1: enabled)
0
DS12422 - Rev 4 page 30/56
8.5
8.6
LIS2DU12
CTRL3 (12h)
CTRL3 (12h)
RW
Table 27. CTRL3 register
INT2_
BOOT
INT2_F_
FULL
INT2_F_
FTH
INT2_F_
OVR
1. This bit must be set to 0 for the correct operation of the device.
INT2_
DRDY
0
ST1
INT2_BOOT
INT2_F_FULL
INT2_F_FTH
INT2_F_OVR
INT2_DRDY
ST[1:0]
Table 28. CTRL3 register description
Enables boot status on INT2 pin. Default value: 0 (0: disabled; 1: enabled)
Enables FIFO full on INT2 pin. Default value: 0 (0: disabled; 1: enabled)
Enables FIFO threshold interrupt on INT2 pin. Default value: 0 (0: disabled; 1: enabled)
Enables overrun interrupt on INT2 pin. Default value: 0 (0: disabled; 1: enabled)
Enables data-ready interrupt on INT2 pin. Default value: 0 (0: disabled; 1: enabled)
These bits enable data acquisition during the self-test procedure.
ST0
CTRL4 (13h)
RW
Table 29. CTRL4 register
INACT_
ODR1
INACT_
ODR0
BDU 0
1. This bit must be set to 0 for the correct operation of the device.
0
0
SOC BOOT
Table 30. CTRL4 register description
INACT_ODR[1:0]
If the activity/inactivity function is enabled, then these bits select the accelerometer ODR during inactivity status, see
.
BDU
SOC
BOOT
Sensing chain block data update
(0: output registers MSByte and LSByte independent continuous update (default);
1: output registers are not updated until MSByte and LSByte have both been read)
Start of conversion bit. When one-shot mode is enabled, this bit provides the start for the measurement.
This bit is automatically cleared.
Reboots memory content. Default value: 0
(0: normal mode; 1: reboot memory content)
This bit is automatically cleared.
INACT_ODR1 INACT_ODR0
0
0
1
1
0
1
0
1
Table 31. ODR frequency in inactivity state
Frequency [Hz]
Stationary/motion detection: when selected, no ODR change is done if inactivity condition is detected
6
3
1.6
DS12422 - Rev 4 page 31/56
8.7
LIS2DU12
CTRL5 (14h)
CTRL5 (14h)
RW
ODR3 ODR2
ODR[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1110
1111
ODR1
Table 32. CTRL5 register
ODR0 BW1 BW0 FS1 FS0
Table 33. CTRL5 register description
ODR[3:0] ODR selection, see
.
BW[1:0]
Selects the device bandwidth which is dependent on the ODR selected. The available bandwidths are ODR/2,
ODR/4, ODR/8, and ODR/16 for ODR ≥ 50 Hz as shown in Table 35 . For ODR < 50 Hz, refer to Table 36 .
FS[1:0]
Sets the full scale, see Table 37 .
Table 34. Operating modes
Operating mode
Power-down
1.6 Hz in ultralow-power mode
3 Hz in ultralow-power mode
6 Hz in ultralow-power mode
6 Hz in normal mode
12.5 Hz in normal mode
25 Hz in normal mode
50 Hz in normal mode
100 Hz in normal mode
200 Hz in normal mode
400 Hz in normal mode
800 Hz in normal mode
One-shot using the INT2 pin
One-shot using the interface
DS12422 - Rev 4 page 32/56
DS12422 - Rev 4
ODR [Hz]
50
100
200
400
800
ODR [Hz]
6
12.5
25
BW[1:0]
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
00
01
10
11
Table 35. Bandwidth selection (ODR ≥ 50 Hz)
BW [Hz]
25
12.5
200
100
50
25
400
200
100
50
50
25
12.5
6
100
50
25
12.5
6
3
Settling time
[samples to be discarded]
1
2
6
14
6
14
0
2
1
2
0
0
4
4
14
8
0
0
0
1
Table 36. Bandwidth selection (ODR < 50 Hz)
BW[1:0] BW [Hz]
Settling time
[samples to be discarded]
00
01
10
11
00
00
01
10
11
01
10
11
6
3
-
-
-
-
-
-
3
12.5
6
3
11
5
11
1
5
11
LIS2DU12
CTRL5 (14h) page 33/56
8.8
LIS2DU12
FIFO_CTRL (15h)
FS1
1
1
0
0
Table 37. Full-scale selection
FS0
0
1
0
1
Full scale
±2 g
±4 g
±8 g
±16 g
FIFO_CTRL (15h)
RW
ROUNDING
_XYZ
FIFO_
DEPTH
0
0
1. This bit must be set to 0 for the correct operation of the device.
STOP_ON
_FTH
FIFO_MODE2 FIFO_MODE1 FIFO_MODE0
Table 38. FIFO_CTRL register description
ROUNDING_XYZ
This function is used to auto address the correct registers for a circular continuous read from
to
FIFO_DEPTH If 1, enables 2X FIFO.
STOP_ON_FTH
Sensing chain FIFO stop values memorization at threshold level.
(0: FIFO depth is not limited (default);
1: FIFO depth is limited to threshold level)
FIFO_MODE[2:0] Different FIFO modes are enabled as shown in Table 39 .
Table 39. Selection of FIFO mode
FIFO_MODE2 FIFO_MODE1 FIFO_MODE0
0 0 0 Bypass mode
0
0
0
0
1
1
1
0
1
Mode
FIFO mode: stops collecting data when FIFO is full
Reserved
Continuous-to-FIFO: stream mode until trigger is deasserted, then FIFO mode
1
1
1
1
0
0
1
1
0
1
0
1
Bypass-to-continuous: bypass mode until trigger is deasserted, then continuous mode
Reserved
Continuous mode: if the FIFO is full, the new sample overwrites the older sample.
Bypass-to-FIFO: bypass mode until trigger is deasserted, then FIFO mode
DS12422 - Rev 4 page 34/56
8.9
8.10
LIS2DU12
FIFO_WTM (16h)
FIFO_WTM (16h)
RW
-
FTH[6:0]
FTH6 FTH5
Table 40. FIFO_WTM register
FTH4 FTH3 FTH2
Table 41. FIFO_WTM register description
FIFO watermark threshold, maximum value is 127.
INTERRUPT_CFG (17h)
RW
-
INT_
SHORT_EN
Table 42. INTERRUPT_CFG register
WAKE_
THS_W
-
SLEEP_
STATUS_ON
_INT
H_
LACTIVE
FTH1
LIR
FTH0
INTERRUPTS
_ENABLE
Table 43. INTERRUPT_CFG register description
INT_SHORT_EN
WAKE_THS_W
INTERRUPTS_ ENABLE
In combination with the LIR bit, this bit allows selecting the desired interruption configuration (see
).
Weight of 1 LSB of wake-up threshold. Default value: 0
(0: 1 LSB = FS_XL / (2 6 );
1: 1 LSB = FS_XL / (2 8 ) )
SLEEP_STATUS_ON_INT
Sends the sleep status instead of sleep change to INT pins
(only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits are enabled, respectively in registers
and
H_LACTIVE
LIR
Interrupt active level
(0: interrupts active-high (default);
1: Interrupts active-low)
In combination with the INT_SHORT_EN bit, this bit allows selecting the desired interrupt
Enables basic interrupts (6D/4D, free-fall, wake-up, single/double tap, activity/inactivity).
Default value: 0
(0: interrupt disabled; 1: interrupt enabled)
DS12422 - Rev 4 page 35/56
8.11
8.12
LIS2DU12
TAP_THS_X (18h)
TAP_THS_X (18h)
RW
D4D_EN D6D_THS1 D6D_THS0
Table 44. TAP_THS_X register
TAP_THS_X_4 TAP_THS_X_3 TAP_THS_X_2 TAP_THS_X_1 TAP_THS_X_0
D4D_EN
D6D_THS[1:0]
TAP_THS_X_[4:0]
Table 45. TAP_THS_X register description
Portrait/landscape position detection and face-up/down position enabled (4D orientation)
Thresholds for D4D/D6D function
(00: 80 degrees;
01: 70 degrees;
10: 60 degrees;
11: 50 degrees)
X-axis recognition threshold. 1 LSB: FS / (2 5 ). Default value: 0
TAP_THS_Y (19h)
RW
TAP_
PRIORITY_2
TAP_
PRIORITY_1
TAP_
PRIORITY_0
Table 46. TAP_THS_Y register
TAP_THS_Y_4 TAP_THS_Y_3 TAP_THS_Y_2 TAP_THS_Y_1 TAP_THS_Y_0
TAP_PRIORITY_[2:0]
TAP_THS_Y_[4:0]
Table 47. TAP_THS_Y register description
Selection of axis priority for TAP detection (see Table 48 )
Y-axis recognition threshold. 1 LSB: FS / (2 5 ). Default value: 0
TAP_PRIORITY_[2:0]
000
001
010
011
100
101
110
111
Table 48. Selection of axis priority for tap detection
Max priority
X
Y
X
Z
Z
Z
X
Y
Mid priority
Y
X
Z
Y
X
Y
Y
Z
Min priority
Z
Z
Y
X
Y
X
Z
X
DS12422 - Rev 4 page 36/56
8.13
8.14
LIS2DU12
TAP_THS_Z (1Ah)
TAP_THS_Z (1Ah)
RW
TAP_X_EN
TAP_{X,Y,Z}_EN
TAP_THS_Z_[4:0]
TAP_Y_EN TAP_Z_EN
Table 49. TAP_THS_Z register
TAP_THS_Z_4 TAP_THS_Z_3 TAP_THS_Z_2 TAP_THS_Z_1 TAP_THS_Z_0
Table 50. TAP_THS_Z register description
Enables tap recognition in {X,Y,Z} direction
Z-axis recognition threshold. 1 LSB: FS / (2 5 ). Default value: 0
INT_DUR (1Bh)
RW
LATENCY3 LATENCY2 LATENCY1
Table 51. INT_DUR register
LATENCY0 QUIET1 QUIET0 SHOCK1 SHOCK0
Table 52. INT_DUR register description
LATENCY[3:0]
Maximum time gap for double-tap recognition duration. Default value: 0000 which corresponds to 16
ODR_time
Maximum time between two subsequent detected taps to determine a double-tap event (when double tap recognition is enabled).
1 LSB: 32 ODR_time.
QUIET[1:0]
Expected quiet time after a tap detection. Default value: 00 which corresponds to 2 ODR_time
Time after the first detected tap in which there must not be an overthreshold event.
1 LSB : 4 ODR_time.
SHOCK[1:0]
Maximum overthreshold event. Default value: 00 which corresponds to 4 ODR_time
Maximum time for an overthreshold signal detection to be recognized as a tap event.
1 LSB : 8 ODR_time.
DS12422 - Rev 4 page 37/56
8.15
8.16
LIS2DU12
WAKE_UP_THS (1Ch)
WAKE_UP_THS (1Ch)
RW
SINGLE_
DOUBLE_TAP
SLEEP_
ON
Table 53. WAKE_UP_THS register
WK_THS5 WK_THS4 WK_THS3 WK_THS2 WK_THS1 WK_THS0
Table 54. WAKE_UP_THS register description
SINGLE_DOUBLE_TAP
Enables single/double-tap event. Default value: 0
(0: only single-tap event enabled;
1: both single and double-tap events enabled)
SLEEP_ON If 1, activity/inactivity function is enabled.
WK_THS[5:0]
Threshold for wake-up: 1 LSB weight depends on WAKE_THS_W in
Default value: 000000
WAKE_UP_DUR (1Dh)
RW
Table 55. WAKE_UP_DUR register
FF_DUR5
WAKE_
DUR1
WAKE_
DUR0
0
1. This bit must be set to 0 for the correct operation of the device.
SLEEP_
DUR3
SLEEP_
DUR2
FF_DUR5
WAKE_DUR[1:0]
SLEEP_DUR[3:0]
SLEEP_
DUR1
Table 56. WAKE_UP_DUR register description
Free-fall duration. Default value: 0
In conjunction with FF_DUR[4:0] in
1 LSB: 1 ODR_time
Wake-up duration. Default value: 00
1 LSB: 1 ODR_time
Duration to go in sleep mode. Default value: 0000 which corresponds to 16 ODR_time
1 LSB: 512 ODR_time
SLEEP_
DUR0
DS12422 - Rev 4 page 38/56
8.17
8.18
LIS2DU12
FREE_FALL (1Eh)
FREE_FALL (1Eh)
RW
FF_DUR4
FF_DUR[4:0]
FF_THS[2:0]
FF_DUR3 FF_DUR2
Table 57. FREE_FALL register
FF_DUR1 FF_DUR0 FF_THS2
Table 58. FREE_FALL register description
Free-fall duration. Default value: 0
In conjunction with FF_DUR5 in
1 LSB: 1 ODR_time
Free-fall threshold
(000: 156 m g ;
001: 219 m g ;
010: 250 m g ;
011: 312 m g ;
100: 344 m g ;
101: 406 m g ;
110: 469 m g ;
111: 500 m g )
FF_THS1 FF_THS0
MD1_CFG (1Fh)
RW
Each bit in this register enables a signal to be carried over INT1; the pin's output is the OR combination of the signals selected here and in register
INT1_ SLEEP
CHANGE
INT1_
SINGLE_TAP
INT1_WU
Table 59. MD1_CFG register
INT1_FF
INT1_
DOUBLE_TAP
INT1_6D WU_DUR_X4 -
Table 60. MD1_CFG register description
INT1_SLEEP_CHANGE
Enables sleep change (or sleep status, depending on SLEEP_STATUS_ON_INT bit) on the INT1 pin. Default value: 0 (0: disabled; 1: enabled)
INT1_SINGLE_TAP
INT1_WU
Enables routing single-tap event to the INT1 pin. Default value: 0 (0: disabled; 1: enabled)
Enables routing wake-up event to the INT1 pin. Default value: 0 (0: disabled; 1: enabled)
INT1_FF
INT1_DOUBLE_TAP
INT1_6D
WU_DUR_X4
Enables routing free-fall event to the INT1 pin. Default value: 0 (0: disabled; 1: enabled)
Enables routing double-tap event to the INT1 pin.Default value: 0 (0: disabled; 1: enabled)
Enables routing 6D recognition event to the INT1 pin. Default value: 0 (0: disabled; 1: enabled)
If 1, the duration value for wake-up is increased by four times.
DS12422 - Rev 4 page 39/56
8.19
8.20
LIS2DU12
MD2_CFG (20h)
MD2_CFG (20h)
RW
Each bit in this register enables a signal to be carried over INT2; the pin's output is the OR combination of the signals selected here and in register
INT2_ SLEEP
CHANGE
INT2_
SINGLE_TAP
INT2_WU
Table 61. MD2_CFG register
INT2_FF
INT2_
DOUBLE_TAP
INT2_6D
PD_DIS
_INT2
-
Table 62. MD2_CFG register description
INT2_SLEEP_CHANGE
Enables sleep change (or sleep status, depending on SLEEP_STATUS_ON_INT bit) on the INT2 pin. Default value: 0 (0: disabled; 1: enabled)
INT2_SINGLE_TAP
INT2_WU
INT2_FF
INT2_DOUBLE_TAP
Enables routing single-tap event to the INT2 pin. Default value: 0 (0: disabled; 1: enabled)
Enables routing wake-up event to the INT2 pin. Default value: 0 (0: disabled; 1: enabled)
Enables routing free-fall event to the INT2 pin. Default value: 0 (0: disabled; 1: enabled)
Enables routing the double-tap event to the INT2 pin. Default value: 0 (0: disabled; 1: enabled)
INT2_6D
PD_DIS_INT2
Enables routing 6D recognition event to the INT2 pin. Default value: 0 (0: disabled; 1: enabled)
If 1, disables pull-down of INT2 pin.
WAKE_UP_SRC (21h)
R
FF_IA
WU_IA
X_WU
Y_WU
Z_WU
-
SLEEP_STATE
SLEEP_
CHANGE_IA
SLEEP_CHANGE_IA
FF_IA
Table 63. WAKE_UP_SRC register
SLEEP_
STATE
WU_IA X_WU Y_WU
Table 64. WAKE_UP_SRC register description
Detection of change in activity/inactivity status. Default value: 0
(0: change status not detected; 1: change status detected)
Free-fall event detection status. Default value: 0
(0: free-fall event not detected; 1: free-fall event detected)
Sleep status bit. Default value: 0
(0: activity status; 1: inactivity status)
Wake-up event detection status. Default value: 0
(0: wake-up event not detected; 1: wake-up event detected)
Wake-up event detection status on X-axis. Default value: 0
(0: wake-up event on X-axis not detected; 1: wake-up event on X-axis detected)
Wake-up event detection status on Y-axis. Default value: 0
(0: wake-up event on Y-axis not detected; 1: wake-up event on Y-axis detected)
Wake-up event detection status on Z-axis. Default value: 0
(0: wake-up event on Z-axis not detected; 1: wake-up event on Z-axis detected)
Z_WU
DS12422 - Rev 4 page 40/56
8.21
LIS2DU12
TAP_SRC (22h)
TAP_SRC (22h)
R
X_TAP
Y_TAP
Z_TAP
-
TAP_IA
SINGLE_TAP_IA
DOUBLE_TAP_IA
TAP_SIGN
TAP_IA
SINGLE_
TAP_IA
Table 65. TAP_SRC register
DOUBLE_
TAP_IA
TAP_SIGN X_TAP
Table 66. TAP_SRC register description
Tap event detection status. Default: 0
(0: tap event not detected; 1: tap event detected)
Single-tap event status. Default value: 0
(0: single-tap event not detected; 1: single-tap event detected)
Double-tap event detection status. Default value: 0
(0: double-tap event not detected; 1: double-tap event detected)
Sign of acceleration detected by tap event. Default: 0
(0: positive sign of acceleration detected by tap event;
1: negative sign of acceleration detected by tap event)
Tap event detection status on X-axis. Default value: 0
(0: tap event on X-axis not detected; 1: tap event on X-axis detected)
Tap event detection status on Y-axis. Default value: 0
(0: tap event on Y-axis not detected; 1: tap event on Y-axis detected)
Tap event detection status on Z-axis. Default value: 0
(0: tap event on Z-axis not detected; 1: tap event on Z-axis detected)
Y_TAP Z_TAP
DS12422 - Rev 4 page 41/56
LIS2DU12
SIXD_SRC (23h)
8.22
SIXD_SRC (23h)
R
D6D_IA
ZH
ZL
YH
YL
XH
XL
D6D_IA ZH
Table 67. SIXD_SRC register
ZL YH YL
Table 68. SIXD_SRC register description
Source of change in 6D/4D orientation. Default value: 0
(0: change orientation not detected; 1: change orientation detected)
Z-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over threshold) detected)
Z-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)
Y-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over-threshold) detected)
Y-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)
X-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over threshold) detected)
X-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)
XH XL
DS12422 - Rev 4 page 42/56
8.23
8.24
LIS2DU12
ALL_INT_SRC (24h)
ALL_INT_SRC (24h)
R
-
INT_
GLOBAL
Table 69. ALL_INT_SRC register
SLEEP_CHANGE
_IA_ALL
D6D_
IA_ALL
DOUBLE_
TAP_ALL
SINGLE_
TAP_ALL
INT_GLOBAL
SLEEP_CHANGE_IA_ALL
D6D_IA_ALL
DOUBLE_TAP_ALL
SINGLE_TAP_ALL
WU_IA_ALL
FF_IA_ALL
WU_IA_
ALL
Table 70. ALL_INT_SRC register description
•
•
•
•
•
•
•
This bit is 1 if one of the following events occur: detection of change in activity/inactivity status source of change in 6D/4D orientation double-tap event status single-tap event status wake-up event detection status free-fall event detection status sleep event status
Detection of change in activity/inactivity status. Default value: 0
(0: change in status not detected; 1: change in status detected)
Source of change in 6D/4D orientation. Default value: 0
(0: change in orientation not detected; 1: change in orientation detected)
Double-tap event status. Default value: 0
(0: event not detected, 1: event detected)
Single-tap event status. Default value: 0
(0: event not detected, 1: event detected)
Wake-up event status. Default value: 0
(0: event not detected, 1: event detected)
Free-fall event status. Default value: 0
(0: event not detected, 1: event detected)
FF_IA_
ALL
STATUS (25h)
R
-
Table 71. STATUS register
-
PD_
STATUS
DRDY
Table 72. STATUS register description
PD_STATUS Monitors power-down.
DRDY
This bit is 1 when new accelerometer data is available and until the MSB of one of the output registers has been read.
DS12422 - Rev 4 page 43/56
8.25
8.26
8.27
8.28
LIS2DU12
FIFO_STATUS1 (26h)
FIFO_STATUS1 (26h)
R
FTH
FTH
FIFO_OVR
FIFO_OVR -
Table 73. FIFO_STATUS1 register
-
Table 74. FIFO_STATUS1 register description
FIFO watermark status. The watermark is set through bits FTH[6:0] in
.
(0: FIFO filling is lower than WTM;
1: FIFO filling is equal to or higher than WTM)
FIFO overrun status: equal to 1 if FIFO has overwritten data.
FIFO_STATUS2 (27h)
R
FSS7 FSS6 FSS5
Table 75. FIFO_STATUS2 register
FSS4 FSS3 FSS2
-
FSS1
FSS[7:0]
OUTX[15:8]
Table 76. FIFO_STATUS2 register description
Number of unread data stored in FIFO
OUT_X_L (28h)
R
OUTX7
OUTX[7:0]
OUTX6 OUTX5
Table 77. OUT_X_L register
OUTX4 OUTX3 OUTX2
Table 78. OUT_X_L register description
LSBs of X data output. The last four bits are always zero since the data is 12-bit.
OUTX1
OUT_X_H (29h)
R
OUTX15 OUTX14 OUTX13
Table 79. OUT_X_H register
OUTX12 OUTX11 OUTX10 OUTX9
Table 80. OUT_X_H register description
MSBs of X data output
-
FSS0
OUTX0
OUTX8
DS12422 - Rev 4 page 44/56
8.29
8.30
8.31
8.32
LIS2DU12
OUT_Y_L (2Ah)
OUT_Y_L (2Ah)
R
OUTY7
OUTY[7:0]
OUTY6 OUTY5
Table 81. OUT_Y_L register
OUTY4 OUTY3 OUTY2
Table 82. OUT_Y_L register description
LSBs of Y data output. The last four bits are always zero since the data is 12-bit.
OUTY1
OUT_Y_H (2Bh)
R
OUTY15 OUTY14 OUTY13
Table 83. OUT_Y_H register
OUTY12 OUTY11 OUTY10 OUTY9
OUTY[15:8]
Table 84. OUT_Y_H register description
MSBs of Y data output.
OUT_Z_L (2Ch)
R
OUTZ7
OUTZ[7:0]
OUTZ6 OUTZ5
Table 85. OUT_Z_L register
OUTZ4 OUTZ3 OUTZ2
Table 86. OUT_Z_L register description
LSBs of Z data output. The last four bits are always zero since the data is 12-bit.
OUTZ1
OUT_Z_H (2Dh)
R
OUTZ15 OUTZ14 OUTZ13
Table 87. OUT_Z_H register
OUTZ12 OUTZ11 OUTZ10 OUTZ9
OUTZ[15:8]
Table 88. OUT_Z_H register description
MSBs of Z data output
OUTY0
OUTY8
OUTZ0
OUTZ8
DS12422 - Rev 4 page 45/56
8.33
8.34
8.35
8.36
LIS2DU12
OUT_T_L (2Eh)
OUT_T_L (2Eh)
R
OUTT7 OUTT6 OUTT5
Table 89. OUT_T_L register
OUTT4 OUTT3 OUTT2 OUTT1
OUTT[7:0]
Table 90. OUT_T_L register description
LSBs of temperature data output. The last four bits are always zero since the data is 12-bit.
OUT_T_H (2Fh)
R
OUTT15 OUTT14 OUTT13
Table 91. OUT_T_H register
OUTT12 OUTT11 OUTT10 OUTT9
OUTT[15:8]
Table 92. OUT_T_H register description
MSBs of temperature data output
TEMP_OUT_L (30h)
R
OUTT7 OUTT6 OUTT5
Table 93. TEMP_OUT_L register
OUTT4 OUTT3 OUTT2 OUTT1
OUTT[7:0]
Table 94. TEMP_OUT_L register description
LSBs of temperature data output. The last four bits are always zero since the data is 12-bit.
TEMP_OUT_H (31h)
R
OUTT15 OUTT14 OUTT13
Table 95. TEMP_OUT_H register
OUTT12 OUTT11 OUTT10 OUTT9
OUTT[15:8]
Table 96. TEMP_OUT_H register description
MSBs of temperature data output
OUTT0
OUTT8
OUTT0
OUTT8
DS12422 - Rev 4 page 46/56
8.37
8.38
LIS2DU12
WHO_AM_I (43h)
WHO_AM_I (43h)
This register is a read-only register. Its value is fixed at 45h.
0 1
Table 97. WHO_AM_I register default values
0 0 0 1 0 1
ST_SIGN (58h)
RW
Table 98. ST_SIGN register
STSIGN2 STSIGN1 STSIGN0 Reserved
1. Bits marked as Reserved must not be changed.
Reserved (1) Reserved (1) Reserved (1) Reserved (1)
STSIGN[2:0]
Table 99. ST_SIGN register description
These bits set the sign of the self-test procedure.
(110: positive sign (default); 001: negative sign)
DS12422 - Rev 4 page 47/56
9
9.1
9.2
LIS2DU12
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
Soldering information
The LGA package is compliant with the ECOPACK and RoHS standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
For the land pattern and soldering recommendations, consult technical note TN0018 available on www.st.com
.
LGA-12 package information
Figure 14. LGA-12 2.0 x 2.0 x 0.74 mm package outline and mechanical data
DS12422 - Rev 4
L e
ITEM n g t h [ L ]
W
H e i d t i g h h t
[
[
W
H ]
]
Dimensions are in millimeter unless otherwise specified
General Tolerance is +/-0.15mm unless otherwise specified
OUTER DIMENSIONS
DIMENSION [mm]
2
0 .
74
2
M A X
TOLERANCE [mm]
± 0 .
1
± 0 .
/
1
DM00170568 page 48/56
Revision history
Date
09-Nov-2022
Table 100. Document revision history
Version
4 Minor textual updates
Changes
LIS2DU12
DS12422 - Rev 4 page 49/56
LIS2DU12
Contents
Contents
DS12422 - Rev 4 page 50/56
LIS2DU12
Contents
DS12422 - Rev 4 page 51/56
LIS2DU12
Contents
DS12422 - Rev 4 page 52/56
LIS2DU12
List of tables
List of tables
DS12422 - Rev 4 page 53/56
LIS2DU12
List of tables
DS12422 - Rev 4 page 54/56
LIS2DU12
List of figures
List of figures
DS12422 - Rev 4 page 55/56
LIS2DU12
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DS12422 - Rev 4 page 56/56
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