Schneider Electric TSXDMR1652 Coprocessor User Guide
Reklāma
Reklāma
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Section
1 Introduction
Contents
1.1 General Description
1.2 Physical Description
2 Operation
Contents
2.1 Structure
2.2 Dialog with the PLC
2.3 Operating Modes of the Module
3 Functions
Contents
3.1 Function 0: Boolean logic
3.2 Function 1: Bistable Latch
3.3 Function 2: Timer/Monostable
3.4 Function 3: Counter
3.5 Interrupt Inputs
4 Installation and Wiring
Contents
4.1 Installation
4.2 Wiring
General Contents
Page
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19
22
24
27
28
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1
Section
5 Maintenance
Contents
5.1 Indicator Lights
5.2 Troubleshooting
6 Specifications
Contents
6.1 Technical Characteristics
6.2 Performance Characteristics
Page
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35
36
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2
X
Introduction
Sub-section
1.1 General Description
1.1-1 Module Functions
1.2 Physical Description
Introduction 1
Section 1
Page
4
4
5
3
1.1
General Description
The TSX DMR 1652 fast I/O coprocessor is an intelligent module that has 8 fast inputs and 8 fast outputs (24 VDC). It is designed for applications that require short response times (1 to 10 ms) and/or guaranteed response times (
±
0.50 ms), and in particular for applications requiring:
• The acquisition of transient or rapid events, with or without memorization, that may require an immediate action on the process,
• The control of actions, independently of the user program or CPU, with short
(1 ms), guaranteed time delays,
• The monitoring of the application cycle times, including that of the Fast task, or of the duration of an event (watchdog timer function),
• The rapid counting of parts or events (at a rate of up to 1 KHz) with threshold monitoring.
1.1-1 Module Operation and Logic Functions
The four user-selectable logic functions that can be configured and assigned to the inputs and outputs of the module are as follows:
Like all intelligent modules of the TSX Series 7 range, the TSX DMR 1652 operates on the complete I/O bus and communicates with the CPU through its Discrete interface and its Register interface (the Message interface is not used).
The module permanently reads its 8 fast inputs, which have reduced filtering.
When a change of state occurs, the module can generate interrupt signals (through its Discrete interface) according to the conditions (validation, rising or falling edge) dictated by the user program in the memory of the CPU. These interrupt signals have the effect of jumping the program scan to the Interrupt task, which has the highest priority.
The module’s 8 transistor outputs can be controlled by the module itself through integrated logic functions that can be selected and configured by the user.
These 2 types of operation (generation of interrupts, outputs controlled by the module) are compatible and can be used simultaneously.
Function 0: Boolean logic,
Function 1: Bistable latch (RS flip-flop),
Function 2: Timer/Monostable,
Function 3: Counting with threshold monitoring.
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Introduction 1
1.2
Physical Description
The TSX DMR 1652 fast I/O coprocessor is the same size as the other I/O module and can be installed in any slot of the TSX 47-30 and TSX 67/87 racks equipped with the complete I/O bus, or the first 4 slots of the TSX 47-20 (see Section 4 for installation details).
The front panel of the model is equipped with a set of indicator lights and a connector for receiving terminal block BLK4.
The rear panel of the module is equipped with three factory-coded locating devices
(code 776).
1 Fail : This LED is off during normal operation,
2 OK : This LED is on during normal operation, it goes off if the terminal block is opened or a module fault occurs,
3
Out i: This LED shows the output state,
4 Def : This LED is off in normal operation, on if a short circuit occurs on one of the outputs.
DMR 1652
Fail
OK
Out
4
5
6
7
0
1
2
3
Def
1
2
"Fail" (red = module failure),
"OK" (green = normal operation),
3
4
"Out 0" to "Out 7" (red = output at logic state 1),
"Def" (red = short circuit on one of the outputs).
Universal terminal block BLK4.
Factory-coded locating devices: code 776
Software code: See Sub-section 4.1
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7
6
5
6
X
Operation
Sub-section
2.1 Structure
2.1-1 Exchanges with the PLC Processor
2.2 Dialog with the PLC
2.2-1 Discrete Interface
2.2-2 Register Inteface
2.2-3 Interrupts
2.3 Operating Modes of the Module
2.3-1 Description
2.3-2 Action on the Operating Modes
2.3-3 Effect of Stopping the PLC
Operation 2
Section 2
Page
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11
12
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7
2.1
Structure
Process
In 0
In 1
In 2
In 3
In 4
In 5
In 6
In 7
DMR 1652
Out 0
Out 1
Out 2
Out 3
Out 4
Out 5
Out 6
Out 7
IT processor
MUX
IT function
4 inputs : 0/1/2/3
Group 0
4 outputs : 0/1/2/3
4 inputs : 4/5/6/7
Group 1
4 outputs : 4/5/6/7
User program
Input states
IT identification
Discrete interface
IT conditions
Control bits Bc
Function configurations
Control of outputs
Register interface
2.1-1 Exchanges with the PLC Processor
In the TSX 47-20 only:
• The interrupt (IT) function is not available as this PLC has no Interrupt task,
• The time required by the TSX 47-20 to exchange one register word with an intelligent module is twice the scan time of the PLC.
This factor must be taken into account in applications where the outputs of the
TSX DMR 1652 module are controlled by user program.
In the TSX 47-30 and TSX 67/87 PLCs, all the functions of the module are available without restriction.
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Operation 2
2.2
Dialog with the PLC
2.2-1 Discrete Interface
The TSX DMR 1652 fast I/O coprocessor module has:
• 8 isolated inputs (In0 to In7) which can generate 8 interrupts according to the conditions (validation, rising or falling edge) dictated by the user program,
• 8 isolated and protected transistor outputs (Out0 to Out7) which can be controlled by either:
- the user program,
- the module itself through predefined logic functions.
The communication between the module and the PLC is established through the
Discrete interface and the Register interface of the module.
Note: The Message interface is not used in the TSX DMR 1652 module.
The Discrete interface is used to transfer information concerning the I/O states and the generation of interrupts.
In the TSX 47-20
F
7
C B
Output states
8
0
7
7
4 3
Input states
0
0
Ixy,i
In the TSX 47-30 and TSX 67/87
F
7
C B
Output states
8
0
7
7
4 3
Generation of IT by In
0
0
Ixy,i
When the module is stopped, the output states are at 0.
2.2-2 Register Interface
The input word registers (IW) and output word registers (OW) are grouped according to the way they are used, as follows:
• Standard registers (IW/OWxy,0), used in the same way as in the other intelligent modules,
• Interrupt control registers (IW/OWxy,1 and 2), whose values can change during the operation of the module,
• Logic function configuration registers (IW/OWxy,3, 4, 5 and 6). Certain bits can change state during operation. The logic functions can be configured only when the module is stopped,
• Output control registers (IW/OWxy,7).
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Data stored in the input register words:
F
Ovr Def
C B
Run B A
Function No.
8 7 4 3 0
9 Fail 7 6 4 3
Tdi Vi7 Vi6 Vi5 Vi4 Vi3 Vi2 Vi1 Vi0
In7 In6 In5 In4 In3 In2 In1 In0
I/O group 0 to 3
Function No.
I/O group 4 to 7
CPU 7
Output states
0
IWxy,0
IWxy,1
IWxy,2
IWxy,3
IWxy,4
IWxy,5
IWxy,6
IWxy,7
Bit not used
Register word Bit Function
IWxy,0,
IWxy,0,
IWxy,0,
IWxy,0,
IWxy,0,
IWxy,0,
IWxy,0,
C : 1 = module running,
B : 1 = module not configured,
A : 1 = terminal block open or absent,
9 : 1 = initial self-test in progress,
8 : 1 = module failure (Fail),
7 : 1 = application fault (Ovr or Def),
6 : 1 = blocking fault,
IWxy,0,
IWxy,0,
IWxy,1,
IWxy,1,
4 : 1 = presence of a fault (except Fail),
3 : 1 = module available (self-test finished),
F : 1 = overrun fault (Ovr),
E : 1 = short-circuit on one of the outputs (Def),
IWxy,2, 0 to 7 : input states updated with a period of 1 to 10 ms (In0 to 7).
The other bits reflect the states of the control bits (recopy of the bit states of the output register words).
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Operation 2
Data stored in the output register words:
F C B
Run
Function No.
Function No.
8 7 4 3 0
4
8 Vi7 Vi6 Vi5 Vi4 Vi3 Vi2 Vi1 Vi0
Fe7 Fe6 Fe5 Fe4 Fe3 Fe2 Fe1 Fe0
I/O group 0 to 3
I/O group 4 to 7
CPU 7
Command of outputs
0
OWxy,0
OWxy,1
OWxy,2
OWxy,3
OWxy,4
OWxy,5
OWxy,6
OWxy,7
Bit not used
Register word Bit Function
OWxy,0,
OWxy,0,
C : 1 = activates the configured logic function (module set to
Run),
4 : 0 = interrupt system not validated,
1 = validation of the events generating interrupts,
OWxy,1, 8 : 1 = cancellation of the 100 ms time delay of interrupts (Tdi),
(see Section 3.5)
OWxy,1,0 to 7 : 0 = the corresponding input cannot generate an IT (Vi0 to 7),
OWxy,2,0 to 7 : 1 = IT on a falling edge of the corresponding input (Fe0 to 7),
0 = IT on a rising edge of the corresponding input,
OWxy,7, 8 : 1 = control by the user program of the 8 outputs. The states of the 8 outputs are contained in the least significant byte
(OWxy,7,0 to OWxy,7,7).
2.2-3 Interrupts
This function is available only with the TSX 47-30 and TSX 67/87. It is not available with the TSX 47-20 as this PLC has no Interrupt task.
The TSX DMR 1652 module has eight 24 VDC inputs, each of which can deliver an interrupt (IT) signal to the CPU.
The user program defines the interrupt conditions for each input: IT validated or not
(Vi0 to 7) and IT on a rising or falling edge (Fe0 to 7).
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2.3
Operating Modes of the Module
2.3-1 Description
The TSX DMR 1652 fast I/O coprocessor module has 3 operating modes as follows:
• Self-test (this is a transient state that occurs on power-up or when the module is plugged into a powered up PLC),
• Stop mode,
• Run mode.
2.3-2 Action on the Operating Modes
Self-test
The self-tests are executed each time the module is powered up; they monitor and process the internal faults of the module.
During the self-tests, the outputs of the module are set to 0.
If no faults have been detected at the end of the self-tests, the OK light comes on and the "module available" bit is set to 1.
Stop mode
In the Stop mode the module is inactive, whether it has been configured or not, and the states of the inputs and outputs in the image memory are at 0.
A Stop command from the CPU causes the re-initialization of the module and the acquisition of the configuration contained in the output register words OW.
Run mode
In the Run mode the module is fully operational. Any changes in the parameters of the selected logic function are taken into account, but the type of logic function (F0 to F3) cannot be changed (it can only be changed in the Stop mode).
A Run command from the CPU causes the validation of the configuration. If the configuration is not correct, the "not configured" bit is set to 1.
The Run command and the configuration can be sent simultaneously after the selftests.
2.3-3 Effect of Stopping the PLC
Stopping the PLC has no effect on the 8 inputs of the module and effects the 8 outputs of the module only in the following case:
• if SY8 = 1 (value by default) the outputs are reset to 0,
• if SY8 = 0, the outputs are activated normally.
Note: If the configuration of the PLC includes local or remote extension racks, the states of system bits SY32 to SY39 must be taken into account as well as the state of system bit SY8 (refer to the TSX T607 Programming Terminal User’s Manual, Book 1, Section
10.3).
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X
Functions
Sub-section
3.1 Function 0: Boolean Logic
3.1-1 Description of the Function
3.1-2 Parameterizing the Functions
3.1-3 Example
3.2 Function 1: Bistable Latch
3.2-1 Description of the Function
3.2-2 Parameterizing the Functions
3.2-3 Example
3.3 Function 2: Timer/Monostable
3.3-1 Description of the Function
3.3-2 Parameterizing the Functions
3.3-3 Typical Timing Diagrams
3.3-4 Example
3.4 Function 3: Counter
3.4-1 Description of the Function
3.4-2 Parameterizing the Functions
3.4-3 Example
3.5 Interrrupt Inputs
3.5-1 Description of the Function
3.5-2 Operation
3.5-3 Example
Functions 3
Section 3
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3.1
Function 0: Boolean Logic
3.1-1 Description of the Function
This logic function is intended for applications that require an immediate reaction to an external event when the validation conditions are true.
Typical examples of use include:
• The step by step advance of a sequential machine,
• The automatic selection or rejection of parts,
• The marking or stamping of parts.
Group 0:
Bc0
In0
AND
OUT 0
Bc1
OUT 1
In1
AND
In3 In2 In1 In0
AND
QD
AND
QC
In3 In2 In1 In0
Bc2
Bc3
AND
QF
AND
QE
AND
AND
QA
OR
OR
OUT 2
OR
OR
QB
The logic functions are the same for Group 1 (In4 to 7 and Out 4 to 7).
OUT 3
The functions are parameterized by defining the 6 nibbles (4-bit bytes) QA, QB, QC,
QD, QE and QF, which correspond to the logic connections of the functions.
The bits Bc0 to 3 are the validation condition bits that are supplied by the user program through the output word register interface OW. The acquisition of these bits by the module is indicated to the CPU through the input word register interface IW.
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Functions 3
3.1-2 Parameterizing the Functions
The functions are parameterized through the register interface by OWxy,3 and 4 for
Group 0 and by OWxy,5 and 6 for Group 1.
Group 0
F
0
QF
C B 8
Bc3 Bc2 Bc1 Bc0
QE
7
QB
QD
4 3
QA
QC
0
OWxy,3
OWxy,4
Group 1
F
0
QF
C B 8
Bc7 Bc6 Bc5 Bc4
QE
7
QB
QD
4 3
QA
QC
0
OWxy,5
OWxy,6
3.1-3 Example
Assignment of the following logic functions to Out0 to 2:
Out 0 = Bc 0.
Out 1 = Bc 1.
Out 2 = (Bc 2.
In 0
In 1
In 3) + (Bc 3 • In 2 • In 0)
OWxy,3, 0/3
OWxy,3, 4/7
OWxy,3, 8/B
OWxy,3, C/F
QA =
1 0
QB =
Control =
0 0 see Note
0 0
1 1 1 1
Function No.
=
0
H 'C'
H '0'
H 'F'
H '0'
H '0 F 0 C'
-> OWxy,3
OWxy,4, 0/3 QC =
0 0 0 0
QD =
1 0 0 0
H '0'
OWxy,4, 4/7
OWxy,4, 8/B
H '8'
H '1 4 8 0'
-> OWxy,4
QE =
0 1 0 0
H '4'
OWxy,4, C/F QF =
0 0 0 1
H '1'
Note: The four validation condition bits Bc0 to 3 do not have to be written when the functions are parameterized; their states can be defined at any time by the user program by writing output word OWxy,3.
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Writing the register words OWxy,3 and OWxy,4 (with the module in the Stop mode) implements the logic diagram below. A run command by the bit OWxy,0,C is then necessary to execute the logic function.
Group 0:
In0
In1
Bc0
AND
Bc1
AND
In3 In2 In1 In0 In3 In2 In1 In0
AND 1 0 0 0
QD
AND
QC
0 0 0 0
Bc2
AND
Bc3
AND 0 0 0 1
QF
AND
QE
0 1 0 0
AND
QA
OR 1 1 0 0
QB
OR 0 0 0 0
OUT 0
OUT 1
OR
OUT 2
OR
OUT 3
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Group 0
In 0
Bc 0
In 1
Bc 1
In 2
Bc 2
In 3
Bc 3
Functions 3
3.2
Function 1: Bistable Latch
3.2-1 Description of the Function
This logic function is intended for applications that require the memorization of a transient external event, or the activation of an output during a period determined by two external events, for example:
• The memorization of a transient contact with acknowledgement by the program or externally,
• The application of a strip of glue slaved to the change of state of 2 position detectors.
AND
OR
AND
OR
S
R
BL 0
Q
Q
S
BL 1
Q
R Q
Out 0
Out 1
Out 2
Out 3
The logic functions are the same for Group 1 (In4 to 7).
Input S :
Input R :
Output Q :
Output Q :
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3.2-2 Parameterizing the Functions
The functions are parameterized through the register interface by OWxy,3 and 4 for
Group 0 and by OWxy,5 and 6 for Group 1.
Group 0
F
1
C B 8 7
Bc3 Bc2 Bc1 Bc0
Unused
4 3
Unused
0
OWxy,3
OWxy,4
Group 1
F
1
C B 8 7
Bc7 Bc6 Bc5 Bc4
Unused
4 3
Unused
0
OWxy,5
OWxy,6
3.2-3 Example
Implementation of the bistable latch function with inputs In0 and In1.
H’1100'
→
OWxy,3 with H’1100'
Bc 0 = 1
Bc 1 = 0
Bc 2 = 0
Bc 3 = 0
Bc 0
In 0
In 1 Bc 1
Out 0
Out 1
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Functions 3
3.3
Function 2: Timer/Monostable
3.3-1 Description of the Function
This logic function is intended for applications that require short, guaranteed response times (timer and monostable), for example:
• The application of a strip of glue slaved to a time factor,
• The watchdog monitoring of the tasks (execution of the program).
Group 0
In 0
Bc 0
In 1
Bc 1
AND
Set
Enable preset
Ctrl timer
T
MT 0
MT0,P
TB0
M
Out 0
Out 1
In 2
Bc 2
In 3
Bc 3
Set
AND
Enable preset
Ctrl timer
T
MT 1
MT1,P
TB1
M
Out 2
Out 3
The logic function are the same for Group 1 (In4 to 7 and Out4 to 7).
Commands:
• Preset : On a rising edge of Set with Enable preset at 1
MT0,P/MT1,P (preset value
→ current value),
• Run : If the current value
≠
0 and Ctrl timer is at 1,
• Freeze current value: Ctrl timer = 0.
Outputs
• T (done) = 1 : if current value = 0 and Set and Ctrl timer are at 1,
• M (running) = 1 : if current value
≠
0 and Set and Ctrl timer are at 1,
• T = 0 and M = 0 : if Ctrl timer is at 0.
Remarks: The preset value MTi,P and the time base TB can be modified with the module running. The new values are not loaded into the IW register until the preset command is given.
During the initialization sequence, if the Set and Enable preset inputs are at 1, the preset value is not loaded (since there must be a rising edge on the Set input to load the preset value).
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3.3-2 Parameterizing the Functions
The functions are parameterized through the register interface by OWxy,3 and 4 for
Group 0 and by OWxy,5 and 6 for Group 1.
Group 0
F C B 8
2
Bc3 Bc2 Bc1
Preset value MT1,P
Bc0
7 4 3
TB1 TB0
Preset value MT0,P
0
OWxy,3
OWxy,4
Group 1
F C B 8
2
Bc7 Bc6 Bc5
Preset value MT3,P
Bc4
7 4 3
TB3 TB2
Preset value MT2,P
0
OWxy,5
OWxy,6
The time base values are configured as follows:
• 0 for 1 ms
• 1 for 10 ms
• 2 for 100 ms
The preset values vary from 0 to 255 and are entered in hexadecimal code.
The parameters are accessible by the user program in the IW register (in hexadecimal code for the current values MTi,V).
Group 0
F C B 8
2
Bc3 Bc2 Bc1
Current value MT1,V
Bc0
7 4 3
TB1
Current value
TB0
MT0,V
0
IWxy,3
IWxy,4
Group 1
F C B 8
2
Bc7 Bc6 Bc5
Current value MT3,V
Bc4
7 4 3
TB3
Current value
TB2
MT2,V
0
IWxy,5
IWxy,6
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Functions 3
3.3-3 Typical Timing Diagrams
The timing diagrams below are given as examples of the use of the timer and monostable functions.
It is assumed that the Enable preset input is always at state 1.
Timer function
Set
Ctrl timer
Current value MT,V :
Output T :
Monostable function
Set
Ctrl timer
Current value MT,V :
Output M :
3.3-4 Example
Configure function MT0 with a time base TB of 1 ms and a preset value of 155 ms.
H’2300'
→
OWxy,3 with
H’9B’
→
OWxy,4 with
H’2300'
H’9B’
FB = 1 ms
Bc0 = 1 (Enable Preset 1)
Bc1 = 1 (Ctrl timer 0)
Bc2 = 0 (Enable Preset 1)
Bc3 = 0 (Enable Preset 1)
MT0,P = 155 (Decimal value)
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3.4
Function 3: Counter
3.4-1 Description of the Function
This function is intended for applications that require the counting of parts or events, for example filling/packing, palletization, stock control, etc.
Groupe 0:
In 0
Bc 0
In 1
Bc 1
In 2
Bc 2
In 3
Bc 3
Up
Val Up
Down
Val Down
AND
Enable count
OR
Reset
D
R
C0
F
C0,T
C0,V
E
Out 0
Out 1
Out 2
Out 3
The logic functions are the same for Group 1 (In4 to 7 and Out 4 to 7).
Commands
• Count up : on a rising edge of the Up input if the Val Up input = 1 and the Reset input = 0,
• Count down: on a rising edge of the Down input if the Val Down input = 1 and
• Freeze : the Reset input = 0,
Enable count = 0 and Reset = 0,
• Reset to 0 : Reset = 1 (this input has the highest priority).
Outputs
• F Full : upcounting overflow output (the current value Ci,V changes from
+32767 to -32768),
• D Done : current value Ci,V
≥
threshold value Ci,T,
• R Run : current value Ci,V < threshold value Ci,T,
• E Empty : downcounting overflow output (the current value Ci,V changes from -32768 to +32767).
Remarks: The freezing of the current value by Enable count has no action on the outputs.
The overflow indicators F and E are memorized and acknowledged when the
Reset input = 1. The counter has no preset value.
During the initialization sequence, the current value Ci,V is at 0.
The outputs D and R are set according to the threshold value Ci,T.
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Functions 3
3.4-2 Parameterizing the Functions
The functions are parameterized through the register interface by OWxy,3 and 4 for
Group 0 and by OWxy,5 and 6 for Group 1.
Group 0
F
3
C B 8 7
Bc3 Bc2 Bc1 Bc0
C0,T threshold value
4 3
Unused
0
OWxy,3
OWxy,4
Group 1
F
3
C B 8 7
Bc7 Bc6 Bc5 Bc4
C1,T threshold value
4 3
Unused
0
OWxy,5
OWxy,6
The parameters are accessible by the user program in the IW register (in hexadecimal code for the current values Ci,V).
Group 0
F
3
C B 8 7
Bc3 Bc2 Bc1 Bc0
C0,V threshold value
4 3
Unused
0
IWxy,3
IWxy,4
Group 1
F
3
C B 8 7
Bc7 Bc6 Bc5 Bc4
C1,V threshold value
4 3
Unused
0
IWxy,5
IWxy,6
3.4-3 Example
Counter C0 with a threshold value C0,T of 16 000.
H’3500'
→
OWxy,3 with
16 000
→
OWxy,4
H’3500'
Bc0 = 1 (Val Up)
Bc1 = 0 (Val Down)
Bc2 = 1 (Enable Count)
Bc3 = 0 (Reset)
Timing diagram:
- 32 768 0
Current value C0,V :
32 767
Threshold C0,S :
16 000
Up
Output C0,D :
Output C0,R :
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3.5
Interrupt Inputs
3.5-1 Description and Configuration of the Function
This function is available with the TSX 47-30 and TSX 67/87 only.
The user program validates whichever of the 8 inputs are to generate an interrupt to the CPU (Vi = 1 in register word OWxy,1 (bits 0 to 7)).
It also defines for each input validated for IT the event causing the IT:
• Rising edge (Fe = 0),
• Falling edge (Fe = 1)
The edge thus defined causes:
• The interruption of the CPU, if it can be interrupted (OWxy,0,4 = 1).
• The setting to 1 of the bit corresponding to this input in the Discrete interface
(Ixy,0 to 7).
The same input cannot normally interrupt the CPU twice in less than 100 ms.
However, this time delay can be cancelled for all the inputs by the user program
(OWxy,1,8 = 1).
The parameters of the logic function can be changed with the module running.
3.5-2 Operation
Each input can, by configuration, generate an interrupt that has the effect of jumping the program scan to the Interrupt task (programmed by the user), thus permitting a rapid, programmed response to an external event.
After the CPU has been interrupted by one input, the interrupt requests from other inputs are memorized and processed as soon as the Interrupt task becomes available (end of processing and acknowledgement of IT in progress).
The time required to transfer an interrupt to the CPU is 1 ms.
Remarks: If the normal 100 ms time delay of the interrupts is cancelled (by setting OWxy,1,8 to 1), the user must take the necessary precautions to deal with interruptions of the CPU that may be too frequent.
It is possible to eliminate the processing time of the module and to reduce the transfer time of the interrupts to 200
µ s by configuring the group concerned for
Function 0 with all the parameters at 0:
H’0'
→
OWxy,3
→
OWxy,4 for Group 0 (In0 to 3),
H’0'
→
OWxy,5
→
OWxy,6 for Group 1 (In4 to 7).
24
Functions 3
3.5-3 Example
Description of the function:
The TSX DMR 1652 is installed in slot 2 of rack 0. The interrupt inputs are In0 and
In1.
• On a rising edge of In0 the PLC output O17,0 is set to 0,
• On a falling edge of In1 the PLC output O17,0 is set to 1.
Note: This example is given for information only. In reality, the TSX DMR 1652 is capable of performing the function described above independently of the CPU by using the bistable latch function F1.
Programming of the Master task:
The Grafcet representation below is used to show the various preparatory phases in graphic form. In a real application, the Grafcet steps are implemented by internal bits programmed in Ladder or Literal language (the Grafcet being reserved for the sequential processing of the application).
Initialization
0
IW2,03 Module available
1 Actions
Configuration of
DMR module
= 1
Module set to Run
Selection of IT on In0 and 1
Selection of type of edge causing IT
Resetting to 0 of the rest of the configuration
H’1000'
→
OW2,0 ;
H’0003'
→
OW2,1 ;
H’0002'
→
OW2,2 ;
0
→
OW2,2
→
OW2,3
→
OW2,4
→
OW2,5
→
OW2,6
→
OW2,7
2 Actions
Validation of IT
(module and CPU)
Validation of module IT
Demasking of CPU IT
Activation of IT task
SET OW2,0,4 ;
DMASKINT (I2) ;
START CTRL1
25
Programming of the Interrupt task
< IT generated by DMR ?
!
READINT (I2;B2)
< If IT from DMR, read DMR discrete bits
!
IF B2 THEN READBIT (I2;B10)
ELSE JUMP L10
< If IT from DMR, transfer the image of the output bits of module 17 to the Bi zone for updating
!
O17,0 [8]
→
B20 [8]
< Updating according to the origin of the IT (In0 or In1)
!
IF B10 THEN RESET B20
!
IF B11 THEN SET B20
< Explicit exchange of output module 17, confirmation of the
!
image of the output bits, and acknowledgement of the IT
WRITEBIT (B20;I17); B20 [8]
< Processing to the end of IT task
!
L10
26
X
Installation and Wiring
Sub-section
4.1 Installation
4.1-1 Possible Locations
4.1-2 Configuration
4.2 Wiring
4.2-1 Wiring the Terminal Block
4.2-2 Wiring Precautions
Installation and Wiring 4
Section 4
Page
28
28
28
29
29
29
27
4.1
Installation
4.1-1 Possible Locations
As a general rule, the TSX DMR 1652 module can be installed in any rack that is equipped with the complete bus.
Basic configuration
Basic configuration
(single rack)
Basic configuration
(double rack)
Local extension racks
(single)
Remote extension racks
(single)
Local extension racks
(double)
TSX 47 20 ..
Slots 0 to 3.
Interrupt inputs not available.
TSX 47 300
TSX 67 200
TSX 67 300
TSX 87 120
TSX 87 200
TSX 87 300
TSX RCE 860
Any slot,
5 intelligent modules max.
Interrupt inputs available.
Slots 0 to 7 of the lower rack.
Interrupt inputs available.
TSX RCF 860
Any slot.
Interrupt inputs available (*)
Any slot.
Interrupt inputs available (**)
TSX RDE 880 Slots 0 to 7 of the lower rack.
Interrupt inputs available (*)
Restrictions: (*) The TSX 67-300 and TSX 87-120/200 cannot process interrupts from extension racks (see page 40).
(**) The TSX 67-300 and TSX 87-120/200 cannot accept intelligent modules in remote extension racks.
Warning
The TSX DMR 1652 module should never be installed in the upper half of a double rack (wiring impossible and risk of damage).
4.1-2 Configuration
The TSX DMR 1652 has two types of configuration codes:
• A hardware configuration code, which is coded ex-factory on the 3 female locating devices on the back of the module,
• A software configuration code, which is entered on the TSX T607 or TSX T407 terminal during the configuration of the inputs and outputs.
Codes
Hardware
Software
TSX 47-20 TSX 47-30
TSX 67/87
77
62
776
776 or 62
28
Installation and Wiring 4
4.2
Wiring
4.2-1 Wiring the Terminal Block
Terminal block to be used: TSX BLK 4.
–
24 VDC
+
Signals
A4
A3
A2
A1
A8
A7
A6
A5
B8
B7
B6
B5
B4
B3
B2
B1
Out 0
Out 1
Out 2
Out 3
24 V
24 V
0 V
0 V
In 0
In 1
In 2
In 3
0 V
0 V
Signals
Out 4
Out 5
Out 6
Out 7
24 V
24 V
0 V
0 V
In 4
In 5
In 6
In 7
0 V
0 V
C5
C6
C7
C8
C1
C2
C3
C4
D1
D2
D3
D4
D5
D6
D7
D8
Outputs
Inputs
The connections between the 0 V terminals or 24 V terminals are made by the module. The module does not supply the 24 VDC power.
4.2-2 Wiring Precautions
The wiring precautions are the same as for the discrete I/O modules of the TSX
Series 7 range. Refer to the installation manual of the PLC concerned.
29
30
X
Maintenance
Sub-section
5.1 Indicator Lights
5.2 Troubleshooting
5.2-1 Types of Faults
5.2-2 Diagnostics
Maintenance 5
Section 5
Page
32
32
32
33
31
5.1
Indicator Lights
Front panel indicator lights:
TSX DMR 1652
Fail
OK
Out
Out
6
7
4
5
2
3
0
1
Def
Module failed
Normal operation
Output status lights
Defect (short-circuit) on one of the outputs
5.2
Troubleshooting
5.2-1 Types of Faults
• Open terminal block: Unlocking the terminal block resets all the outputs of the module to 0. The OK light goes out and bit B of the I/O status word is set to 1, this word can be accessed by the TSX T407 terminal in the Diagnostic mode.
• Short-circuit on one output: When an output of the module at state 1 is shortcircuited for more than 100 ms, the output is forced to 0 and the Def light comes on until the fault is acknowledged by opening the terminal block or cutting off the power supply to the outputs of the module.
• Overrun: When the total frequency of the input signals is too high (see Section
6.2), the IW and OW register exchanges are blocked (the user program loses control of the module) and the module is forced to the Stop mode after 10 ms.
• Module fault: If a fault is detected during the self-tests, the module is blocked. The
Fail light comes on and the OK light goes out.
32
Maintenance 5
5.2-2 Diagnostics
DMR light
PLC I/O light
Fault bits at 1
Fail on
OK out
On IWxy,0,8
Type of fault
Internal fault detected by self-tests
Consequences Acknowledgement on the module of the fault
µ
P reset Module de-energized
(1)
OK out
Fail out
OK out
Fail out
On
On
IWxy,0,6
IWxy,0,4
Fault of IT controller detected by self-tests
IWxy,0,A
IWxy,0,6
IWxy,0,4
Terminal block open or faulty
Blocking fault
Forced to
Stop (2)
Module de-energized
(1)
OK on
Def on
OK on
Out
Out
IWxy,1,F
IWxy,0,7
IWxy,0,4
IWxy,1,E
IWxy,0,7
IWxy,0,4
Overrun (1) or application fault (3)
Short-circuit on one output, or application fault
Forced to
Stop (2)
Output forced to 0
Close terminal block and command
Stop of module
Command
Stop then
Run of module
Open the terminal block or de-energize the actuator
(4)
Remarks: (1) If the fault persists, change the module.
(2) When the module is stopped, its outputs are reset to 0.
(3) An overrun fault is detected when the total number of changes of state of the inputs is more than 2400 and less than 10,000 (above 10,000 no detection is possible).
(4) The fault concerning a short-circuit on one of the outputs (Def) does not disappear until the terminal block is opened or the power supply to the outputs of the module is cut off.
See Section 2.3: Operating Modes of the Module.
Note: The faults that cause the I/O fault lights to come on (on the front of the processor or extension module of the PLC) also cause:
• SY10 = 0,
• SY40 to 47 = 0, depending on the rack concerned,
• Oxy,S = 1 for the faulty module.
33
34
X
Specifications
Sub-section
6.1 Technical Characteristics
6.1-1 Characteristics of the Module
6.1-2 Characteristics of the Inputs
6.1-3 Characteristics of the Outputs
6.1-4 Power Consumption
6.2 Performance Characteristics
6.2-1 Function 0: Boolean Logic
6.2-2 Function 1: Bistable Latch
6.2-3 Function 2: Timer/Monostable
6.2-4 Function 3: Counter
6.2-5 Interrupt Inputs
Specifications 6
Section 6
Page
36
36
37
38
38
39
39
39
39
39
40
35
6.1
Technical Characteristics
6.1-1 Characteristics of the Module
Inputs 8 fast inputs for 24 VDC signals, commoned to the 0 V of the power supply.
Outputs
Compatibility
Functional capacities
Temperature limits
8 transistor outputs, 24 VDC/350 mA positive logic, protected against short circuits and overvoltages.
Common supply to the 8 outputs (loads commoned to 0 V).
Inputs: Compatible with CELENEC 2 or 3 wire detectors.
Compatible with 24 VDC transistor outputs (PNP).
Compatible with 24 VDC output modules of the TSX
Series 7 range.
CONFORMING TO IEC 2 AND NFC 63850 STANDARDS
Outputs: Compatible with solenoids of < 8W,
Compatible with lamps of < 5W,
Compatible with all input modules of the TSX Series 7 range.
The outputs can be reconnected to the inputs.
• Counting : 16 bits (-32768 to +32767),
• Timing : 8 bits (0 -1023 increments), time bases: 1 ms, 10 ms, 100 ms.
• Operation : 0 to +60
°
C,
• Storage : -40 to 70
°
C.
36
Specifications 6
6.1-2 Characteristics of the Inputs
Nominal input values
• Voltage
• Current
• Sensor power supply
Limit input values
• at state 1 voltage current
• at state 0 voltage current
Input impedance
Response times:
• from state 0 to 1
• from state 1 to 0
Power dissipation
External line:
• permissible line resistance
• permissible leakage resistance
Isolation
• between input circuits and internal bus
• between input circuits and electrical or mechanical ground
24 VDC
15 mA
19.2 to 30 VDC
11 to 30 VDC
6 to 19 mA
V
≤
5 VDC
I
≤
3 mA
1500 to 1700 ohms
Min 0.1 ms Typ 0.2 ms Max 0.5 ms
Min 0.1 ms Typ 0.2 ms Max 0.5 ms
360 mW (at nominal voltage)
R
≤
500 ohms
R
≥
30 Kohms
1500 V (rms)
R > 10 Mohms at 500 VDC
50/60Hz
37
6.1-3 Characteristics of the Outputs
Nominal values
• nominal voltage
• nominal current
• current limitation
Limit values
• voltage
• current
• current for all 8 outputs
Response times
• from state 0 to 1
• from state 1 to 0
Leakage current at state 0
Residual voltage at state 1
Protection
• against overloads
• against inductive overvoltages
Power dissipation
Power consumption
Isolation
24 VDC
≤
0.35 A by thermal circuit-breaker
19.2 to 30 VDC
0.44 A for one output
≤
2.8 A with ventilated rack
< 100
µ s
< 500
µ s
< 0.1 mA
< 1.3 V thermal circuit-breaker discharge and clipping diodes
0.6 W (nominal voltage)
60 mA
> 10 Mohms at 500 VDC
Note: In case of power loss due to a short-circuit or overload, it is necessary to de-energize the actuators or remove and replace the terminal block to rearm the module.
6.1-4 Power Consumption
PLC output voltage
TSX DMR 1652 consumption
+5V
350 mA
+24V
15 mA
If the module is installed in a rack that is not ventilated, UL standards impose the following limitations:
• Inputs The number of inputs continuously at state 1 must not exceed 5,
• Outputs The total current for all 8 outputs must not exceed 1.7 A.
38
Specifications 6
6.2
Performance Characteristics
6.2-1 Function 0: Boolean Logic
To obtain the performance characteristics described below, the following conditions must be respected:
• Minimum duration of an input state: 1 ms,
• Maximum rate of change of all 8 inputs: 10 changes of state in 10 ms, with 2 changes of state maximum per millisecond.
Performance:
• Input/Output transfer time: 1 ms max.
6.2-2 Function 1: Bistable Latch
To obtain the performance characteristics described below, the following conditions must be respected:
• Minimum duration of an input state: 1 ms,
Performance:
• Input/Output transfer time: 1 ms max.
6.2-3 Function 2: Timer/Monostable
To obtain the performance characteristics described below, the following conditions must be respected:
• Minimum duration of an input state: 1 ms,
Performance:
• Input/Output transfer time: 1 ms max.,
• Time base resolution: 1 ms,
• Time base jitter:
±
0.5 ms.
6.2-4 Function 3: Counter
To obtain the performance characteristics described below, the following conditions must be respected:
• Minimum duration of an input state: 1 ms,
Performance:
• Input/Output transfer time: 1 ms max.,
• Maximum count rate: 500 Hz.
39
Note:
It is possible to increase the maximum count rate by limiting the performance of the function that is implemented on the other group, for example:
• Counter implemented on Group 0,
• Functions authorized on Group 1: F0, F1 or F2,
• Minimum duration of a state on the counter input: 500
µ s,
• Minimum duration of a state on the inputs of Group 1: 5 ms,
• Maximum rate of change of Group 1 inputs: 2 changes of state in 10 ms, with 2 changes of state maximum per millisecond.
In these conditions, the performance of the counter is as follows:
• Input/Output transfer time: 1 ms max.,
• Maximum count rate: 1 KHz.
6.2-5 Interrupt Function
The time required to activate the Interrupt task in the TSX 47-30 and TSX 67/87 the sum of two times (tic + tip).
• tic: time between the change of state of the interrupt input and the presence of the IT signal on the I/O bus.
tic = 1 ms for the TSX DMR 1652 module.
• tip: time between the presence of the IT signal on the I/O bus and the activation of the Interrupt task. This time depends on the type of PLC and whether local or remote extension racks are used, as shown in the table below.
Maximum time tip
TSX 47-30
TSX 67-20
TSX 67-30
TSX 87-10/20
TSX 87-30
(1)
(2)
Local I/O (TSX LES)
Basic config.
Extensions (1)
1.5 ms -
1.5 ms
2.5 ms
1.5 ms
-
2.5 ms
1 ms
-
1 ms
Remote I/O (TSX LFS)
Basic config.
Extensions (2)
-
2.2 ms
3.2 ms
2.2 ms
-
3.2 ms
1.7 ms
-
1.7 ms
Reminder of IT processing in local extension racks:
• TSX 67-20: IT processed by the CPU,
• TSX 87-30: IT processed by the CPU,
• TSX 67-30 and TSX 87-10/20: No IT processing.
Reminder of maximum distances for remote intelligent modules:
• TSX 67-20: 750 meters max.,
• TSX 87-30: 1000 meters max.,
• TSX 67-30 and TSX 87-10/20: No remote intelligent modules.
40
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