ELAN MICROELECTRONICS EM73PA00 4-Bit Microcontroller User's Manual
Below you will find brief information for 4-Bit Microcontroller EM73PA00. The EM73PA00 is an advanced single-chip CMOS 4-bit OTP (One Time Programming) microcontroller. It contains 24K-byte ROM, 128-nibble RAM, 4-bit ALU, 16-level subroutine nesting, 13-bit programmable counter, 8-bit watchdog timer, and 13-bit programmable timer on one chip. This device provides low power consumption, high-speed operation, and a range of features for controlling various applications.
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1.7 VERSION
ELAN MICROELECTRONICS CORPORATION
Preliminary
USER’S
EM73PA00
MANUAL
4-
B
it
M
icrocontroller
ELAN MICROELECTRONICS CORPORATION
Hsinchu Headquarters
No. 12, Innovation Road 1,
Science-based Industrial Park,
HsinChu, Taiwan, ROC
Phone : +886 3 563-9977
Fax : +886 3 563-9966 http://www.emc.com.tw
Hong Kong Office
Rm. 1005B, 10/F., Empire Centre,
68 Mody Road., Tsimshatsui,
Kowloon, Hong Kong
Phone : +852 2723-3376
Fax : +852 2723-7780
Trademark Acknowledgments
IBM is a registered trademark and PS/2 is a trademark of IBM.
Microsoft, MS, MS-DOS, and Windows are registered trademarks of Microsoft
Corporation.
©2002 ELAN MICROELECTRONICS CORPORATION
All Rights Reserved
Printed in Taiwan, ROC 6/2002
The material in this manual is subject to change without notice.
ELAN
MICROELECTRONICS
assumes no responsibility for errors that may appear in this manual.
ELAN MICROELECTRONICS
makes no commitment to update, nor to keep current, the information contained in this manual. The software described in this manual is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of the agreement. No part of this manual may be reproduced or transmitted in any form or by any means without the express written permission of
ELAN MICROELECTRONICS
.
INTRODUCTION ...........................................................................................................................................................5
1.1 O
VERVIEW
...............................................................................................................................................................5
1.2 K
EY
F
EATURES
........................................................................................................................................................5
1.3 F
UNCTIONAL
B
LOCK
D
IAGRAM
...............................................................................................................................6
1.4 P
IN
A
SSIGNMENTS
...................................................................................................................................................6
1.4 P
IN
A
SSIGNMENTS
...................................................................................................................................................7
1.5 P
AD
D
IAGRAM
.......................................................................................................................................................10
1.6 P
IN
D
ESCRIPTIONS
.................................................................................................................................................12
1.7 I
NSTRUCTION
S
ET
O
VERVIEW
................................................................................................................................13
1.7.1 Data Transfer.................................................................................................................................................13
1.7.2 Rotate.............................................................................................................................................................13
1.7.3 Arithmetic Operation .....................................................................................................................................13
1.7.4 Logical Operation..........................................................................................................................................14
1.7.5 Exchange .......................................................................................................................................................14
1.7.6 Branch ...........................................................................................................................................................15
1.7.7 Compare ........................................................................................................................................................15
1.7.8 Bit Manipulation............................................................................................................................................15
1.7.9 Subroutine......................................................................................................................................................16
1.7.10 Input/Output.................................................................................................................................................16
1.7.11 Flag Manipulation .......................................................................................................................................16
1.7.12 Interrupt Control .........................................................................................................................................16
1.7.13 CPU Control................................................................................................................................................17
1.7.14 Timer/Counter, Data Pointer, and Stack Pointer Control ..........................................................17
1.8 N
OTATION
C
ONVENTIONS
.....................................................................................................................................18
PROGRAMMING MODEL.........................................................................................................................................19
2.1 P
ROGRAM
ROM (24K
X
8
BITS
)
FOR
EM73PA00..................................................................................................19
2.1.1 User’s Program and Fixed Data ...................................................................................................................20
2.2 D
ATA
RAM ( 128-
NIBBLE
)...................................................................................................................................23
2.2.1 Zero Page ......................................................................................................................................................23
2.2.2 Stack...............................................................................................................................................................24
2.2.3 Data Area ......................................................................................................................................................24
2.2.4 Address Mode ................................................................................................................................................24
2.3
P
ROGRAM
C
OUNTER
(24K ROM)
FOR
EM73PA00 .........................................................................................25
2.3.1 Branch Instruction .........................................................................................................................................25
2.3.2 JUMP instruction...........................................................................................................................................25
2.3.3 Subroutine Instruction ...................................................................................................................................25
2.3.4 Interrupt Acceptance Operation ....................................................................................................................26
2.3.5 Interrupt Return Operation............................................................................................................................26
2.3.6 Reset Operation .............................................................................................................................................26
2.3.7 Other Operations ...........................................................................................................................................26
SIGNAL AND FUNCTION DESCRIPTIONS ...........................................................................................................27
3.1 A
CCUMULATOR
(ACC) .........................................................................................................................................27
3.2 F
LAGS
....................................................................................................................................................................27
3.2.1 Carry Flag (CF).............................................................................................................................................27
3.2.2 Zero Flag (ZF)...............................................................................................................................................28
3.2.3 Status Flag (SF).............................................................................................................................................28
3.2.4 Examples........................................................................................................................................................28
3.3 ALU ......................................................................................................................................................................28
3.3.1
ALU Structure ..........................................................................................................................................29
EM73PA00 User's Manual Introduction
• 3
3.3.2 ALU Supported Functions .............................................................................................................................29
3.4 HL R
EGISTER
........................................................................................................................................................30
3.4.1 HL Register Function ....................................................................................................................................30
3.5 S
TACK
P
OINTER
(SP).............................................................................................................................................31
3.6 D
ATA
P
OINTER
(DP)..............................................................................................................................................32
3.7 R
ESET
F
UNCTION
...................................................................................................................................................32
PIN TYPE CIRCUITY DIAGRAMS ..........................................................................................................................33
4.1 P
IN
T
YPE
C
IRCUITRY
D
IAGRAMS
...........................................................................................................................33
4.1.1 Reset Pin Type ...............................................................................................................................................33
4.1.2 Oscillation Pin Types.....................................................................................................................................33
4.1.3 Input Pin Types ..............................................................................................................................................34
4.1.4 I/O Pin Types .................................................................................................................................................34
4.1.5 Bi-direction I/O Program Controlling...........................................................................................................35
EM73PA00 I/O P
ORT
D
ESCRIPTIONS
...........................................................................................................................36
CLOCK AND TIMING ................................................................................................................................................37
5.1 O
VERVIEW
.............................................................................................................................................................37
5.2 C
LOCK AND
T
IMING
G
ENERATOR
..........................................................................................................................37
5.2.1
Clock and Timing Generator Structure ...................................................................................................37
5.2.2
Clock and Timing Generator Function....................................................................................................38
5.3 I
NTERNAL
T
IME
B
ASE
............................................................................................................................................38
5.3.1 Time Base Interrupt (TBI ).............................................................................................................................39
5.4
T
IMER
/C
OUNTER
..............................................................................................................................................39
5.4.1 Counter Function...........................................................................................................................................40
5.4.2 Timer Function ...............................................................................................................................................41
INTERRUPT AND POWER SAVING FUNCTIONS ...............................................................................................43
6.1 O
VERVIEW
.............................................................................................................................................................43
6.2 I
NTERRUPT
F
UNCTION
...........................................................................................................................................43
6.2.1
Interrupt Structure ...................................................................................................................................44
6.2.2 Interrupt Operation .......................................................................................................................................45
6.3 P
OWER
S
AVING
(OFF / S
LEEP
) F
UNCTION
............................................................................................................46
6.3.1 Off / Sleep Control .........................................................................................................................................46
6.3.2 Off and Sleep Conditions ...............................................................................................................................46
6.3.3 Release Condition..........................................................................................................................................47
6.3.4 Edge Off/Sleep Mode:....................................................................................................................................47
MISCELLANEOUS FUNCTION ................................................................................................................................48
7.1 O
VERVIEW
.............................................................................................................................................................48
7.2 R
EMOTE CONTROL SIGNAL OUTPUT PORT
..............................................................................................................48
7.3 L
OW
V
OLTAGE
D
ETECTOR
....................................................................................................................................48
7.4 W
ATCH
D
OG
T
IMER
..............................................................................................................................................49
ELECTRICAL PROPERTIES ....................................................................................................................................50
8.1 O
VERVIEW
.............................................................................................................................................................50
8.2 A
BSOLUTE
M
AXIMUM
R
ATINGS
............................................................................................................................50
8.3 R
ECOMMENDED
O
PERATING
C
ONDITIONS
.............................................................................................................50
8.4 DC E
LECTRICAL
C
HARACTERISTICS
......................................................................................................................51
EM73PA00 User's Manual Introduction
• 4
Introduction
Chapter
1
1.1 Overview
EM73PA00 is an advanced single chip CMOS 4-bit OTP(One Time
Programming) microcontroller. It contains 24K-byte ROM, 128-nibble RAM,
4-bit ALU, 16-level subroutine nesting, 13-bit programmable counter, 8-bit watchdog timer, and 13-bit programmable timer on one chip.
1.2 Key Features
EM73PA00 User's Manual
• Si gate CMOS process
• Low power consumption
• Single power supply : 2.5V to 5.5V.
• High-speed operation : 4MHz max.
• ROM capacity
• RAM capacity
: 24576 X 8 bits.
: 128 X 4 bits.
• Built-in time base counter : 22 stages.
• I/P : 8 bits input port
• O/P: 8 bits output port
• I/O: 5 bits bi-direction I/O port
• Programmable counter and timer
• Built-in watchdog timer
• Low voltage detector
• Subroutine nesting : Up to 16 levels.
• Interrupt : Three (Internal)
• Standby function
• Instruction execution time : 1us @4MHz
• Packaging : chip form EM73PA00H, 28-pin SOP EM73PA00AM,
28-pin TSSOP EM73PA00BM
• RMO : carrier wave output port of remote controller
Introduction
• 5
1.3 Functional Block Diagram
The figure below illustrates a simplified block diagram of the EM73PA00 followed by pin assignments description.
RESET
XIN XOUT
Reset
Control
Clock
Generator
Timing
Generator
Sleep Mode
Control
System Control
Interrupt
Control
Instruction Decoder
Instruction Registor
Time
Base
12 bits timer
12 bits counter
ROM
PC
Data pointer
ACC
ALU
Z
Flag
C S
Stack pointer
Stack
RAM
HR LR
I/O Control
P0.0/WAKEUP0
P0.1/WAKEUP1
P0.2/WAKEUP2
P0.3/WAKEUP3
EM73PA00 Block Diagram
EM73PA00 User's Manual Introduction
• 6
1.4 Pin Assignments
TOP view
P52 □ 1
P53 □ 2
□
P60 □ 3
P61 □ 4
P62 □ 5
P63 □ 6
P11 □ 7
RMO □ 8
(VPP)TEST □ 9
(VDD)VDD □ 10
(Xin)Xin □ 11
Xout □ 12
(GND) Vss □ 13
(RESET) RESET □ 14
(*): Progrmming OTP signal lines
Physical Dimension of SOP28
28 □ P51
27 □ P50
26 □ P43
25 □ P42
24 □ P41
23 □ P40
22 □ P03 (DCLK)
21 □ P02 (OEB)
20 □ P01 (PGMB)
19 □ P00 (ALCK)
18 □ P73
17 □ P72
16 □ P71 (DOUT)
15 □ P70 (DIN)
D b
EM73PA00 User's Manual
e
DETAIL"A"
L
7 o
(4X)
θ
DETAIL "A"
Introduction
• 7
Symbol
A 92
Dimension in mils
— 106
Dimension in mm
2.337 — 2.692 e
L 16 — 50 — 1.27
θ
0
° 5
Physical Dimension of TSSOP28
E 1 E
C
L 1
L
D E T A IL "A " (2:1)
£ c e
D b
A 2 A
A 1
EM73PA00 User's Manual Introduction
• 8
Symbol
A
Min Normal Max
- - 1.20
A1 0.05 0.10 0.15
A2 0.80 1.00 1.05 b 0.19 - 0.30 c 0.09 - 0.20
D 9.60 9.70 9.80
E1 4.30 4.40 4.50
θ
0 o
C - 8 o
EM73PA00 User's Manual Introduction
• 9
1.5 Pad Diagram
6 5 4 3 2 1 28 27 26 25 24
(0,0)
P1.1
P1.0
VSS
VDD
9
10
7
8
11 12 13
EM73PA00
14 15 16 17
20
19
18
23
22
21
P4.0
P0.3
P0.2
P0.1
P0.0
P7.3
EM73PA00 User's Manual Introduction
• 10
Pad No. Symbol X Y
1 P5.2 5.5 1604.6
2 P5.3 -115.6 1604.6
3 P6.0 -236.7 1604.6
4 P6.1 -357.8 1604.6
5 P6.2 -478.9 1604.6
6 P6.3 -600.0 1604.6
7 P1.1 -610.0 -489.8
8 P1.0 -610.0 -686.4
9 TEST -610.0 -833.4
10 VDD -610.0 -1058.6
11 XIN -537.5 -1625.0
12 XOUT -365.7 -1625.0
13 VSS -186.2 -1625.0
15 P7.0 210.4 -1625.0
16 P7.1 382.2 -1625.0
17 P7.2 554.0 -1625.0
18 P7.3 610.0 -1351.9
19 P0.0 610.0 -1180.1
20 P0.1 610.0 -1008.3
21 P0.2 610.0 -836.5
22 P0.3 610.0 -664.7
23 P4.0 610.0 -492.9
24 P4.1 612.1 1604.6
25 P4.2 489.9 1604.6
26 P4.3 368.8 1604.6
27 P5.0 247.7 1604.6
28 P5.1 126.6 1604.6
Chip size : 1520 * 3550 um
For PCB layout, IC substrate must be floated or connected to Vss.
EM73PA00 User's Manual Introduction
• 11
1.6 Pin Descriptions
Symbol Pin-Ty pe
V
DD
-
V
SS
TEST
RESET
XIN /
OSCin
XOUT
P7(0..3)
P1.1
OSC-A
OSC-H
OSC-A
I/O
-
-
Function Mask Options
1. Power supply (+)
2. Power supply (+) for programming OTP.
1. Power supply (-)
2. Power supply (-) for programming OTP.
1. Test pin, high active.
2. VPP:high voltage(12V) power source for programming OTP.
Pull-down resistor
-
-
2. RESET: reset input signal for programming OTP.
1. Crystal or RC or external clock source connecting pin
2. Xin: oscillator signal input for programming OTP.
Crystal connecting pin
Pull-up resistor
Low voltage detector enable
Crystal or RC osc type
4-bit bi-direction I/O port
P7.1/DOUT: data output for programming OTP.
P7.0/DIN: data input for programming OTP.
1-bit bi-direction I/O port
-
-
Output : open-drain or push-pull
Input : pull-up resistor or none
P0(0..3)
P4(0..3)
INPUT
INPUT
4-bit input port
P0.0/ALCK: address counter clock for programming OTP.
P0.1/PGMB: program data to OTP cells for programming OTP.
P0.2/OEB: data output enable for programming OTP.
P0.3/DCLK: data in/out clock signal for programming OTP.
4-bit input port
Pull-up/pull-down resistor
Wakeup
P5(0..3)
P6(0..3)
O/P
O/P
4 bit output port
4 bit output port
Pull-up/pull-down resistor
Wakeup
Push-pull or open-drain
Push-pull or open-drain
EM73PA00 User's Manual Introduction
• 12
1.7 Instruction Set Overview
The instruction set is optimized to support those instructions most commonly used or executed.
1.7.1 Data Transfer
Operation Description Byte Cycle
(Binary)
LDA X 0110 1010 xxxx xxxx
Acc
←RAM[x]
Flag
CF ZF SF
LDHL x
LDIA
LDL
STA
STAM
STAMD
#k
#k x
STAMI
0100 1110 xxxx xxx0
1101 kkkk
1000 kkkk
0110 1001 xxxx xxxx
0101 1001
0111 1101
0111 1111
Acc
←RAM[HL]
Acc
←ROM[DP]
L
Acc
←ROM[DP]
H
, DP+1
HR
←k
LR
←RAM[x],HR←RAM[x+1] 2 2 - 1
Acc
←k
LR
←k
RAM[x]
←Acc
RAM[HL]
←Acc
RAM[HL]
←Acc, LR-1
RAM[HL]
←Acc, LR+
STD #k,y 0100 1000 kkkk yyyy
RAM[y]
←k
STDMI #k 1010 kkkk
RAM[HL]
←k, LR+
THA
TLA
0111 0110
0111 0100
Acc
←HR
Acc
←LR
RLCA
RRCA
1.7.2 Rotate
Operation Description Byte Cycle
(Binary)
0101 0000
0101 0001
[←CF←Acc←]
[→CF→Acc→]
Flag
CF ZF SF
ADCAM
1.7.3 Arithmetic Operation
Operation Description Byte Cycle
(Binary)
0111 0000
ADD #k,y 0100 1001 kkkk yyyy
ADDA #k 0110 1110 0101 kkkk
ADDAM 0111 0001
Acc
←Acc + RAM[HL] + CF
RAM[y]
←RAM[y] + k
Acc
←Acc + k
Acc
←Acc + RAM[HL]
Flag
CF ZF SF
2 2
1 1
EM73PA00 User's Manual Introduction
• 13
ADDH #k 0110 1110 1001 kkkk
ADDL #k 0110 1110 0001 kkkk
ADDM #k 0110 1110 1101 kkkk
DECA
DECL
0101 1100
0111 1100
DECM
INCA
INCL
INCM
0101 1101
0101 1110
0111 1110
0101 1111
SUBA #k 0110 1110 0111 kkkk
SUBM #k 0110 1110 1111 kkkk
HR
←HR + k
LR
←LR + k
RAM[HL]
←RAM[HL] + k
Acc
←Acc-1
LR
←LR-1
RAM[HL]
←RAM[HL] -1
Acc
←Acc +1
LR
←LR +1
RAM[HL]
←RAM[HL]+1
Acc
←k-Acc
Acc
←RAM[HLl - Acc - CF'
RAM[HL]
←k - RAM[HL]
1.7.4 Logical Operation
Operation Description Byte Cycle
(Binary)
ANDA #k 0110 1110 0110 kkkk
ANDAM 0111 1011
ANDM #k 0110 1110 1110 kkkk
ORA #k 0110 1110 0100 kkkk
ORAM 0111 1000
ORM #k 0110 1110 1100 kkkk
XORAM 0111 1001
Acc
←Acc&k
Acc
←Acc & RAM[HL]
RAM[HL]
←RAM[HL]&k
Acc
←Acc | k
Acc
←Acc | RAM[HL]
RAM[HL]
←RAM[HL] | k
Acc
←Acc^RAM[HL]
Flag
CF ZF SF
EXA x 0110 1000 xxxx xxxx
EXAH
EXAL
EXHL x
1.7.5 Exchange
Operation Description Byte Cycle
(Binary)
0110 0110
0110 0100
0100 1100 xxxx xxx0
Acc
↔RAM[x]
Acc
↔HR
Acc
↔LR
Acc
↔RAM[HL]
LR
↔RAM[x],HR↔RAM[x+1]
Flag
CF ZF SF
EM73PA00 User's Manual Introduction
• 14
BR
JHL
1.7.6 Branch
Code Byte Cycle
000a aaaa aaaa aaaa
0100 0110
If SF=1 than PCÅ a
Else null
PCÅRAM[HL+3],RAM[HL
+2],RAM[HL+1],RAM[HL]
1 2
Flag
CF ZF SF
- - -
1.7.7 Compare
Code Byte Cycle
CMP #k,y 0100 1011 kkkk yyyy
CMPA x 0110 1011 xxxx xxxx
CMPAM 0111 0011
CMPH #k 0110 1110 1011 kkkk
CMPIA #k 1011 kkkk
CMPL #k 0110 1110 0011 kkkk k-RAM[y]
RAM[x]-Acc
RAM[HL] - Acc k - HR k - Acc k-LR
2
2
1
2
1
2
2
2
1
2
1
2
Flag
CF ZF SF
C Z Z'
C
C
-
C
-
Z Z'
Z Z'
Z C
Z Z'
Z C
1.7.8 Bit Manipulation
Mnemonic Object Code (Binary) Operation Description Byte Cycle
CLM b 1111 00bb
CLP p,b 0110 1101 11bb pppp
CLPL 0110 0000
CLR y,b 0110 1100 11bb yyyy
SEM b 1111 01bb
SEP p,b 0110 1101 01bb pppp
SET
TF y,b 0110 1100 01bb yyyy y,b 0110 1100 00bb yyyy
TFM b 1111 11bb
TFP p,b 0110 1101 00bb pppp
TFPL
TT
TTP
0110 0001 y,b 0110 1100 10bb yyyy p,b 0110 1101 10bb pppp
RAM[HL] b
←0
PORT[p] b
←0
PORT[LR
3-2
+4]
LR1-0
←0
RAM[y] b
←0
RAM[HL] b
←1
PORT[p] b
←1
PORT[LR
3-2
+4]
LR1-0
←1
RAM[y] b
←1
SF
←RAM[y] b
'
SF
←Acc b
'
SF
←RAM[HL] b
'
SF
←PORT[p] b
'
SF
←PORT[LR
3-2
+4]
LR1-0
'
SF
←RAM[y] b
SF
←PORT[p] b
2
2
Flag
CF ZF SF
2 -
2 -
- *
- *
EM73PA00 User's Manual Introduction
• 15
LCALL a
SCALL a
RET
1.7.9 Subroutine
001a aaaa aaaa aaaa
1110 nnnn
0100 1111
SP
←SP -1, PC←a
STACK[SP]
←PC,
SP
←SP - 1, PC←a, a = 8n + 6 (n
=1~15),a=86h(n=0)
STACK[SP]
←PC,
PC
←STACK[SP], SP=SP + 1
Byte Cycle
2 2
Flag
CF ZF SF
- - -
1
1
2
2
- -
- -
-
-
1.7.10 Input/Output
Mnemonic Object Code (Binary) Operation Description Byte Cycle
INA p 0110 1111 0100 pppp
INM p 0110 1111 1100 pppp
OUT #k,p 0100 1010 kkkk pppp
OUTA p 0110 1111 000p pppp
OUTM p 0110 1111 100p pppp
Acc
←PORT[p]
RAM[HL]
←PORT[p]
PORT[p]
←k
PORT[p]
←Acc
PORT[p]
←RAM[HL]
Flag
CF ZF SF
1.7.11 Flag Manipulation
Mnemonic Object Code (Binary)
TFCFC
TTCFS
0101 0011
0101 0010
Flag
Operation Description Byte Cycle CF ZF SF
SF
←CF', CF←0
SF
←CF, CF←1
SF
←ZF
1.7.12 Interrupt Control
Mnemonic Object Code (Binary)
CIL r 0110 0011 00rr rrrr
DICIL r 0100 0100 00rr rrrr
EICIL r 0100 0101 00rr rrrr
Flag
Operation Description Byte Cycle CF ZF SF
IL
←IL & r
2 2 - - 1
EIF
←0, IL←IL&r
EIF
←1, IL←IL&r
MASK
↔Acc
FLAG.PCÅ STACK[SP]
SP
←SP+1, EIF←1
1 2 * * *
EM73PA00 User's Manual Introduction
• 16
1.7.13 CPU Control
Flag
Mnemonic Object Code (Binary) Operation Description Byte Cycle CF ZF SF
NOP 0101 0110 no operation 1 1 - - -
HALT 0100 0111 CPU halt, wait interrupt release
1 1 - - -
1.7.14 Timer/Counter, Data Pointer, and Stack
Pointer Control
Flag
Mnemonic Object Code (Binary) Operation Description Byte Cycle CF ZF SF
LDADPL 0110 1010 1111 1100
Acc
←[DP]
L
2 2 - Z 1 LDADPM
LDADPH
0110 1010 1111 1101
0110 1010 1111 1110
Acc
←[DP]
M
Acc
←[DP]
H
LDASP
LDATAL
LDATAM
0110 1010 1111 1111
0110 1010 1111 0100
0110 1010 1111 0101
Acc
←SP
Acc
←[TA]
L
Acc
←[TA]
M
LDATAH
LDATBL
LDATBM
0110 1010 1111 0110
Acc
←[TA]
H
0110 1010 1111 1000
Acc
←[TB]
L
0110 1010 1111 1001
Acc
←[TB]
M
LDATBH
STADPL
STADPM
STADPH
STASP
0110 1010 1111 1010
Acc
←[TB]
H
0110 1001 1111 1100
[DP]
L
←Acc
0110 1001 1111 1101
[DP]
M
←Acc
0110 1001 1111 1110
[DP]
H
←Acc
0110 1001 1111 1111
SP
←Acc
STATAL 0110 1001 1111 0100
[TA]
L
←Acc
STATAM 0110 1001 1111 0101
[TA]
M
←Acc
STATAH 0110 1001 1111 0110
[TA]
H
←Acc
STATBL 0110 1001 1111 1000
[ TB]
L
←Acc
STATBM 0110 1001 1111 1001
[TB]
M
←Acc
STATBH 0110 1001 1111 1010
[TB]
H
←Acc
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
- Z 1
- Z 1
- Z 1
- Z 1
- Z 1
- Z 1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
- 1
- 1
- 1
EM73PA00 User's Manual Introduction
• 17
1.8 Notation Conventions
The following are the notation conventions used in the above tables and throughout this manual unless otherwise specified.
Symbol
HR
PC
SP
Acc
CF
SF
EI
MASK
TA
RAM[HL]
ROM[DP]
L
[DP]
L
[DP]
H
Operation
H register
Program counter
Stack pointer
Accumulator
Carry flag
Status flag
Enable interrupt register
Interrupt mask
Timer/counter A
Data memory (address : HL )
Low 4-bit of program memory
Low 4-bit of data pointer register
High 4-bit of data pointer register
[TA]
M
([TB]
M
) Middle 4-bit of CounterA/TimerB register
←
+
Transfer
Addition
&
^
Logic AND
Logic XOR
. x p r
LR
1-0
Concatenation
8-bit RAM address
4-bit or 5-bit port address
6-bit interrupt latch
Contents of bit assigned by bit
1 to 0 of LR
Symbol Operation
|
'
#k y b
PC
12-6 a
5-0
LR
DP
STACK[SP]
FLAG
L register
Data pointer
Stack specified by SP
All flags
ZF
LR
3-2
IL
Zero flag
Bit 3 to 2 of LR
Interrupt latch
Port ( address : p ) PORT[p]
TB
RAM[x]
Timer/counter B
Data memory (address : x)
ROM[DP]
H
[DP]
M
[TA]
L
([TB]
L
)
High 4-bit of program memory
Middle 4-bit of data pointer register
Low 4-bit of CounterA/TimerB register
[TA]
H
([TB]
H
) High 4-bit of CounterA/TimerB register
↔
-
Exchange
Subtraction
Logic OR
Inverse operation
4-bit immediate data
4-bit zero-page address
Bit address
Bit 12 to 6 of program counter
Bit 5 to 0 of destination address for branch instruction
EM73PA00 User's Manual Introduction
• 18
Programming Model
Chapter
2
2.1 Program ROM (24K x 8bits) for EM73PA00
EM73PA00 User's Manual
24K x 8 bits program ROM contains user’s program and some fixed data.
The basic structure of the program may be categorized into 4 partitions.
1. Address 0000h: Reset start address.
2. Address 0002h ~ 000Ch: 3 kinds of interrupt service routine entry
addresses.
3. Address 000Eh-0086h: SCALL subroutine entry address, only available at 000Eh, 0016h, 001Eh, 0026h,
002Eh, 0036h, 003Eh, 0046h, 004Eh, 0056h,
005Eh, 0066h, 006Eh, 0076h, 007Eh. 0086h.
4. Address 0000h ~ 1FFFh: Except for the regions used for the above functions, other region can be used as user’s region.
Address Bank 0:
0000h Reset start address
0002h Reserved
0004h
Reserved
0006h TRGA
0008h TRGB
000Ah TBI
000Ch Reserved
000Eh
0086h
SCALL, subroutine call entry
:
:
07FFh
0800h
0FFFh
1000h
1FFFh
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Data table for
[LDAX],
[LDAXI] instructions
Programming Model
• 19
EM73PA00 User's Manual
2.1.1 User’s Program and Fixed Data
User’s program and fixed data are stored in the program ROM. User’s program is executed using the PC value to fetch an instruction code.
User’s Program
The 24Kx8 bits program ROM can be divided into 4 banks at 4Kx8 bits per bank.
The program ROM bank is selected by P3 (2..0). The program counter is a
13-bit binary counter. The PC and P3 are initialized to "0" during reset.
When P3(2..0) = 000B, program ROM Bank0 and Bank1, are selected.
When P3(2..0) = 001B, Bank0 and Bank2 are selected.
When P3(2..0) = 010B, Bank0 and Bank3 are selected.
Address P3 = x000B P3 = x001B P3 = x010B P3 = x011B P3 = x100B
0000h
:
:
0FFFh
1000h
:
:
1FFFh
Bank1
Bank0
Bank2 Bank3 Bank4 Bank5
XA :
XB :
XC :
Example:
BANK 0
START: :
:
:
#00H
; set program ROM to bank1
OUTA P3
:
:
:
#01H
; set program ROM to bank2
OUTA P3
BR XB1
:
:
:
; set program ROM to bank3
LDIA #02H
OUTA P3
BR XC1
:
:
:
XD : :
:
:
Programming Model
• 20
EM73PA00 User's Manual
; - - - - - - - - - - - - - - - - - - - - - - - - - -
XA1 : :
:
XA2 :
:
:
; - - - - - - - - - - - - - - - - - - - - - - - - - -
XB1 : :
:
XB2 :
:
:
:
; - - - - - - - - - - - - - - - - - - - - - - - - - -
XC1 : :
:
:
XC2 : :
Fixed Data
Fixed Data is read out by table-look-up instruction. The instruction requires the Data Pointer (DP) to indicate the ROM address in obtaining the ROM code data (except Bank0):
LDAX Acc
← ROM[DP]
L
LDAXI
← ROM[DP]
H
,DP+1
Where: DP is a 12-bit data register that stores the program ROM address as pointer for the ROM code data. User must to initially load ROM address into DP register with instructions "LDADPL”, "LDADPM”, and "LDADPH" and assign the bank # by out (bank #-1) into P3.
To obtain the lower nibble of ROM code data, use instruction
"LDAX", and use "LDAXI." to obtain the higher nibble. After
"LDAXI" instruction. The DP value will be increased one automatically
Example:
Read out the ROM code of address 777h in Bank 1 and 111h in Bank 2 by table-look-up instruction.
:
OUT #00h,P3; set bank 1
LDIA #07h;
STADPL
STADPM
STADPH
:
; DP2-0
← 07h
; DP5-3
← 07h
; DP8-6
← 07h, Load DP=777h
LDL #00h;
LDH #03h;
Programming Model
• 21
LDAX
STAMI
LDAXI
STAMI
;
; ACC
; ACC
← 6h
; RAM[30]
← 6h
← 5h, increase DP=778h
; RAM[31]
← 5h
OUT #01h,P3; set bank 1
LDIA #01h;
STADPL
STADPM
; DP2-0
← 01h
; DP5-3
← 01h
; DP8-6
← 01h, Load DP=111h
STADPH
:
LDL #02h;
LDH #03h;
LDAX
STAMI
LDAXI
; ACC
← Ch
; RAM[32]
← Ch
; ACC
← Ah, increase DP=112h
; RAM[33]
←Ah
STAMI
;
BANK 1
ORG 0777h
DATA 56h;
:
BANK 2
ORG 111h
DATA ACh;
EM73PA00 User's Manual Programming Model
• 22
2.2 Data RAM ( 128-nibble )
A total of 128-nibble data RAM is available from address 000 to 7Fh. Data
RAM includes the Zero Page region, Stacks and Data areas.
Increment
Address
000h
− 00Fh
Zero Page
010h
− 01Fh
020h
− 020Fh
:
:
:
040h
− 04Fh
LEVEL 0
050h
− 05Fh
LEVEL 4
060h
− 06Fh
LEVEL 8
070h
− 07Fh
LEVEL 12
080h
− 0EFh
0F0h
− 0FFh
LEVEL 1
LEVEL 5
LEVEL 2
LEVEL 6
LEVEL 9 LEVEL 10
LEVEL 13 LEVEL 14
No Used Area
System Used Area
LEVEL 3
LEVEL 7
LEVEL 11
LEVEL 15
2.2.1 Zero Page
From 000h to 00Fh is the zero-page location. It is used as the zero-page address mode pointer for instructions "STD #k,y; ADD #k,y; CLR y,b; and
CMP y,b".
Example:
Write immediate data "07h" to address "03h" of RAM, and clear bit 2 from
RAM.
STD #07h, 03h ; RAM[03]
← 07h
CLR 0Eh,2 ; RAM[0Eh]2
← 0
EM73PA00 User's Manual Programming Model
• 23
EM73PA00 User's Manual
2.2.2 Stack
There are 16 ( maximum ) stack levels that user can use as subroutines
(including interrupt and CALL). User can assign any level as the starting stack by providing the level number to stack pointer (SP).
When an instruction (CALL or subroutine) is invoked before the subroutine is entered, the previous PC address is saved into the stack until its return from those subroutines. The PC value is restored by the data saved in stack.
2.2.3 Data Area
Except for the area used for user application, the whole RAM can be used as data area for storing and loading general data.
2.2.4 Address Mode
The Data Memory also consisted of three Address Modes, namely-
1) Indirect Address Mode
RAM address
ØØ
The address is specified by the HL registers.
Example:
LDAM
← RAM[HL]
STAM
← Acc
2) Direct Address Mode
field
XXXX XXXX the second byte in the instruction field.
ØØ
XXXX XXXX
RAM address
Example:
LDA
; Acc
← RAM[43h]
STA
; RAM[23h]
← Acc
Programming Model
• 24
3) Zero-Page Address Mode
Instruction field yyyy
Ø
RAM address
0000 yyyy
The zero-page is in address 000h~00Fh.
The address are the lower nibble of the second byte in the instruction field.
Example:
STD #k, y ; RAM[y]← #k
2.3 Program Counter (24K ROM) for EM73PA00
The Program Counter (PC) consisted of 13-bit counter. It indicates the next address to be executed by program ROM instruction.
For an 8K-byte size ROM, PC indicates address 0000h - 1FFFh as BRANCH and CALL instructions. PC is changed when indicating the desired instruction.
2.3.1 Branch Instruction
BR a
Object code: 000a aaaa aaaa aaaa
Condition: SF=1; PC
← PC
13.a
(branch condition satisfied)
PC a a a a a a a a a a a a a
SF=0; PC
← PC +2(branch condition not satisfied)
PC Original PC value+2
2.3.2 JUMP instruction
JHL
Object code: 0100 0110
Condition: PC
← RAM[HL+3]
.
RAM[HL+2]
.
RAM[HL+1]
.
RAM[HL]; HL%4=0
PC a a a a a a a a a a a a a
2.3.3 Subroutine Instruction
SCALL a
Object Code: 1110 nnnn
Condition: PC
← a ; a=8n+6 , n=1..Fh ;a=86h, n=0
PC
0 0 0 0 0
a a A a a
1 1 0
Programming Model
• 25
EM73PA00 User's Manual
EM73PA00 User's Manual
LCALL a
Object code: 001a aaaa aaaa aaaa
Condition: PC
← a
PC a A a a a a a a a a a a a
RET
Object code: 0100 1111
Condition: PC
← STACK[SP]; SP + 1
PC The return address stored in stack
2.3.4 Interrupt Acceptance Operation
When an interrupt is received, the original PC is entered into stack and interrupt vector is loaded into PC. The interrupt vectors are as follows:
TRGA (Counter overflow interrupt)
PC
0 0 0 0 0 0 0 0 0 0 0 1 1 0
TRGB (Timer overflow interrupt)
PC
0 0 0 0 0 0 0 0 0 0 1 0 0 0
TBI (Time base interrupt)
PC
0 0 0 0 0 0 0 0 0 0 1 0 1 0
2.3.5 Interrupt Return Operation
Object code: 0100 1101
Condition: FLAG. PC
← STACK[SP]; EI← 1; SP + 1
PC The return address stored in stack
2.3.6 Reset Operation
PC
0 0 0 0 0 0 0 0 0 0 0 0 0 0
2.3.7 Other Operations
For 1-byte instruction execution: PC + 1
For 2-byte instruction execution: PC + 2
For 3-byte instruction execution: PC + 3
Programming Model
• 26
Signal and Function
Descriptions
Chapter
3
3.1 Accumulator (ACC)
Accumulator (ACC) is a 4-bit data register for temporary data. ACC plays the role of holding the source data and result for arithmetic, logic, and comparison operations.
3.2 Flags
There are three types of flag:
• Carry Flag (CF)
• Zero Flag (ZF)
• Status Flag (SF)
These three 1-bit flags are influenced by the arithmetic, logic, and comparison operation.
All flags are loaded into stack when an interrupt subroutine is served, and the flags are restored after RTI instruction is executed.
3.2.1 Carry Flag (CF)
The Carry Flag is affected by the following operations: a) Addition: CF as a carry out indicator. Under Addition operation, when a carry-out occurs, CF is "1".
Likewise, if the operation has no carry-out, CF
is
EM73PA00 User's Manual Signal and Function Descriptions
• 27
3.3 ALU
b) Subtraction: CF as a borrow-in indicator. Under Subtraction operation, when a borrow-in occurs, the CF is
"0". Likewise, if there is no borrow-in, CF will
be
"1". c) Comparison: CF is as a borrow-in indicator for Comparison operation as in the Subtraction operation. d) Rotation: CF shifts into the empty bit of accumulator for rotation and holds the shift out data after
rotation. e) CF Test Instruction:
Under TFCFC instruction, the CF’ content is sent into SF, then clears itself as "0". For
TTCFS instruction, the content of CF is sent into SF then sets itself as "1".
3.2.2 Zero Flag (ZF)
ZF is affected by the result of ALU. If the ALU operation generate a "0" result, the ZF is "1". Otherwise, the ZF is "0".
3.2.3 Status Flag (SF)
The SF is affected by instruction operation and system status. a) SF is initiated to "1" for reset condition. b) Branch instruction is decided by SF. When SF=1, branch condition is satisfied. Likewise, when SF=0, branch condition is dissatisfied.
3.2.4 Examples
Check the following arithmetic operation for CF, ZF, and SF
Arithmetic Operation
LDIA #00h
LDIA #03h
ADDA #05h
ADDA #0Dh
ADDA #0Eh
CF
-
-
-
-
-
ZF SF
1 1
0 1
0 1
0 0
0 0
The Arithmetic and logic operations of 4-bit data are performed in ALU unit.
EM73PA00 User's Manual Signal and Function Descriptions
• 28
EM73PA00 User's Manual
3.3.1 ALU Structure
C,Z
ALU supports user arithmetic operation functions, including Addition, Subtraction, and Rotation.The C, Z affect the ZF, CF, and SF results.
ZF CF SF
Data Bus
3.3.2 ALU Supported Functions
1) Addition:
ALU supports Addition function with instructions ADDAM, ADCAM, ADDM
#k, and ADD #k,y. The Addition operation affects signal C and signal Z.
Under Addition operation, if the result is "0", Z will be "1". Otherwise, Z will be "0". When Addition operation has a carry-out, C is "1". Otherwise, C will be "0".
Example: Operation C Z
2) Subtraction:
ALU supports Subtraction function with instructions SUBM #k, SUBA #k,
SBCAM, and DECM. The Subtraction operation affects C and Z.
Under Subtraction operation, if the result is negative, C is equal to "0" or borrow out. If the result is positive, C will be "1".
Likewise, if the result of subtraction operation is "0", the Z is "1". Otherwise,
Z will be "1".
Example: Operation
8-4=4
7-F= -8(1000)
C
1
0
Z
0
0
3) Rotation:
Two types of Rotation operations are available. One is Rotation Left, the other is Rotation Right.
Signal and Function Descriptions
• 29
RLCA instruction rotates ACC value counter-clockwise, shift the CF value into the LSB bit of ACC, and then hold the shift out data in CF.
MSB LSB
ACC
C F
RRCA instruction rotates ACC value clockwise, shift the CF value into the
MSB bit of ACC, and then hold the shift out data in CF.
MSB LSB
ACC
C F
Example: Rotate ACC clockwise (right) and shift "1" into the MSB bit of
ACC.
TTCFS; CF
← 1
RRCA; rotate ACC right and shift CF=1 into MSB.
3.4 HL Register
HL Register are two 4-bit registers. They are used as a pair of pointer for
RAM memory address. They are also used as 2 independent temporary 4-bit data registers. For certain instructions, L Register can be a pointer to indicate the pin number (Port 4).
The following illustrates the HL Register structure.
3 2 1 0 3 2 1 0
H REGISTER L REGISTER
3.4.1 HL Register Function
1) Temporary Register Function
HL Register is used as a temporary register for instructions LDL #k, LDH #k,
LDHL, THA, THL, INCL, DECL, EXAL, EXAH.
LDHL legal address should be even number.
Example: Load immediate data "5h" into L register, "Dh" into H register.
EM73PA00 User's Manual Signal and Function Descriptions
• 30
2) Memory Pointer Function
HL Register is used as a pointer of RAM memory address for instructions
LDAM, STAM, STAMI.
Example: Store immediate data #Ah into RAM of address 35h.
STDMI #0Ah ; RAM[35]
← Ah
3) I/O Port Pointer Function
HL Register is used as a pointer to indicate the I/O port bit for instructions
SELP, CLPL, TFPL (when LR = 0, it indicates P4.0).
Example: Set bit 0 of Port 4 to "1"
SEPL ; P4.0
← 1
4)direct Jump function
HL Register is used as a pointer to indicate the destination address for instructions JHL. HL should be limited on xxxxxx00.
Example: Jump to address 1234h
LDIA #01H;
STAMD
LDIA #02H;
STAMD
LDIA #03H;
STAMD
STAM
JHL
3.5 Stack Pointer (SP)
Stack Pointer is a 4-bit register that stores the present stack level number.
The SP value must be set first before using stack. CPU will not initiate the
SP value after a reset condition. When a new subroutine is received, the SP value is automatically decreased by one. Likewise, if a subroutine is sent, the SP value is increased by one.
The data transfer between ACC and SP is done with instructions "LDASP" and "STASP".
Example:
LDIA #0FH ;
STASP ;
←0FH
EM73PA00 User's Manual Signal and Function Descriptions
• 31
:
NEXT1:
:
3.6 Data Pointer (DP)
Data Pointer is a 12-bit register that stores the ROM address indicating the
ROM code data specified by user (refer to Chapter 2, Program ROM).
3.7 Reset Function
When
RESET
pin is held in low level for at least 3 instruction cycles with the
CPU working normally, the CPU will begin to initialize the whole internal states. When
RESET
pin changes to high level, the CPU will begin to work in normal condition.
The following table shows the CPU internal state during reset condition:
Hardware Condition Under RESET (f1) State
Program counter
P3
Status flag
Initial value
0000h
00h
01h
Interrupt enable flip-flop ( EI )
MASK0 ,1, 2
00h
00h
Interrupt latch ( IL ) 00h
RMO 0h
P7, P1.1 input
P5,P6 0Fh
The
RESET
pin is a hysteresis input pin and it has a pull-up resistor.
The simplest RESET circuit is to connect
RESET
pin with a capacitor to V
SS and a diode to V
DD
.
RESET
EM73PA00 User's Manual Signal and Function Descriptions
• 32
Chapter
4
Pin Type Circuity Diagrams
4.1 Pin Type Circuitry Diagrams
4.1.1 Reset Pin Type
EM73PA00 User's Manual
Type Reset-A
4.1.2 Oscillation Pin Types
XIN
Crystal
Osc.
4MHz (100KΩ)
XIN/OSCIN
RC
Osc.
XOUT
XOUT
Type Osc-H
Pin Type Circuity Diagrams
• 33
4.1.3 Input Pin Types
WAKEUP CONTROL MASK OPTION
WAKEUP FUNCTION
Type Input-A
Type Input-B
4.1.4 I/O Pin Types
PathB
SHL
Special function control input
O/P
Output
Data latch
Output data
Type O/P
Output data
Output control
I/O
Input enable
Input data
Type O/P
EM73PA00 User's Manual Pin Type Circuity Diagrams
• 34
4.1.5 Bi-direction I/O Program Controlling
P10 is the command port for controlling P7.
Port 10
3 2 1 0
Input /Output mode selection
P7C3 P7C2 P7C1 P7C0 P7Cn
Initial state: 0000
0
Function Description
P7.n as input port.
1 P7.n as output port.
n:3~0
P11.1 is the command port for controlling P1.1.
Port 11
3 2 1 0
Input /Output mode selection
TIMF CNTF P1C - P1C
Initial state: 0000
0
Function Description
P1.1 as input port.
1 P1.1 as output port.
Example: P7 output by program control.
OUTA P10
:
:
;P7(3..1) define output port
:
:
EM73PA00 User's Manual Pin Type Circuity Diagrams
• 35
EM73PA00 I/O Port Descriptions
Port Input Function
4
5
6
7
0
1
2
3
E Input port , wake-up function
P1.1 input
--
--
E Input port, wake-up function
--
--
E Input port
8
9
--
--
10 I P7C
11 I TIMF+CNTF+P1C
12 --
13 --
14 --
15 --
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Output Function
P1.0 :RMO, P1.1 output
I P3(1..0) : ROM bank selection
--
E Output port
E Output port
E Output port
--
--
I P7C
I TIMFC+CNTFC+P1C
--
--
--
--
I Sleep/Off mode control register
--
--
--
I Watch Dog Timer control register
--
I Timebase control register
I Counter control register
I Timer control register
--
Remarks
P7 output by program control
Ref. Tmr/Cnt
EM73PA00 User's Manual Pin Type Circuity Diagrams
• 36
Clock and Timing
Chapter
5
5.1 Overview
This chapter summarizes the clock and timing for EM73PA00 CPU.
5.2 Clock and Timing Generator
The clock generator is supported by a single clock system. The clock sources from crystal. The working frequency range is 200KHz to 4MHz depending on the actual working voltage.
5.2.1 Clock and Timing Generator Structure
The clock generator unit generates a basic system clock "fc".
When CPU is in off mode, the clock generator will remain disabled until the off condition ends.
EM73PA00 User's Manual Clock and Timing
• 37
The system clock control unit generates 4 basic clock phase ( S1, S2, S3,
S4 ) and a system clock signal.
Mask option sleep
XIN
clock generator
fc
System clock control
System clock
XOUT
S1 S2 S3 S4
5.2.2 Clock and Timing Generator Function
The “fc” frequency is equal to the oscillation frequency of pins XIN and XOUT with crystal (resonator).
When CPU is under off mode, the XOUT pin is in "high" state.
The instruction cycle equals to 4 basic clock “fc”.
1 instruction cycle = 4 / fc
5.3 Internal Time Base
As illustrated below, a time base has 23 stages.
fc
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Time base provides basic frequency for the following functions:
• TBI (time base interrupt)
• Timer/counter, internal clock source
• Warm-up time for off-mode disable
EM73PA00 User's Manual Clock and Timing
• 38
5.3.1 Time Base Interrupt (TBI )
The time base is used to generate a single fixed frequency interrupt. Eight types of frequencies can be selected with the "P25" setting:
Single clock mode
P25 3 2 1 0
(initial
0 0 x x: Interrupt disable
0 1 0 0: Interrupt frequency XIN / 2
10
Hz
0 1 0 1: Interrupt frequency XIN / 2
0 1 1 0: Interrupt frequency XIN / 2
0 1 1 1: Interrupt frequency XIN / 2
11
Hz
12
Hz
13
Hz
1 1 0 0: Interrupt frequency XIN / 2
9
Hz
1 1 0 1: Interrupt frequency XIN / 2
1 1 1 0: Interrupt frequency XIN / 2
1 1 1 1: Interrupt frequency XIN / 2
8
Hz
15
Hz
17
Hz
1 0 x x: Reserved
5.4 Timer/Counter
With Counter, the counter data are saved in the timer registers TAH, TAM, and TAL. User can set initial counter value. Such value is loaded or stored by executing instructions "LDATAH(M,L), STATAH(M,L)."
With Timer, the timer data are saved in the TBH, TBM, and TBL. User can set initial counter value. Such value is loaded or stored by executing instructions "LDATBH (M,L), STATBH (M,L)".
The timer/counter basic structure (see figure below) consisted of two identical modules. The timer or counter module can be set as initial timer or counter values which are sent to the register. P28 and P29 are the command ports for Counter and Timer. User can choose different operating modes and internal clock rates to set these two ports. When timer/counter overflows, it will generate a TRGB/TRGA interrupt request to interrupt control unit.
EM73PA00 User's Manual Clock and Timing
• 39
CNTF,TIMF
Interrupt control
Data bus
12-bit counter 12-bit counter
RMO
P7.0
Event counter control Timer control
CNTFC,TIMFC
Internal clock
P28
CNT
P29
TMM IPS
5.4.1 Counter Function
RMO and P7.0are the external inputs for Counter
Port 28
3 2 1 0
COUNTER MODE SELECTION
CNT * *
Initial state: 0000
CNT
0 0 Stop
Function Description
1 0
1 1
RMO input counter
P7.0 input counter
Under counter , the counter increased by one at any falling edge of RMO and
P7.0.
When counter counts overflow, it will provide an interrupt request TRGA to interrupt control.
P11 3 2
Read
Write
TIMF
TIMFC
CNTF
CNTFC
P1C -
CNTF: When MASK2=0, if Counter overflow then read P11.2 whose value
(CNTF) is 1.
CNTFC: When write 1 to P11.2 ,then Flag is reset (CNTFC =0).
EM73PA00 User's Manual Clock and Timing
• 40
Example: Enable Counter with P28
P28;
interrupt latch
←
0, enable EI
EM73PA00 User's Manual
5.4.2 Timer Function
P29 is the command port for timer
Port 29
3 2 1 0
TMM * IPS
Initial state: 0000
TMM
0
Counter mode selection
Stop
Function Description
1 Timer mode
Internal pulse rate selection
IPS
0 0
0 1
1 0
1 1
Function Description
XIN/2
8
Hz
XIN/2
10
Hz
XIN/2
12
Hz
XIN/2
14
Hz
Under Timer , Timer increased by one at any falling edge of internal pulse.user can choose above 4 types of internal pulse rate by setting IPS to timer command.
When timer counts overflow, it will provide an interrupt request TRGB to interrupt control.
P11 3 2
Read
Write
TIMF
TIMFC
CNTF
CNTFC
P1C -
TIMF: When MASK1=0, if Timer overflow then read P11.3 whose value
(TIMF) is 1.
TIMFC: When write 1 to P11.3 ,then Flag is reset (TIMFC =0).
Example: To generate TRGB interrupt request after 60ms with system clock XIN=4MHz
EXAE;
Enable mask 1
EICIL 111011B;
interrupt latch <-0,enable EI
Clock and Timing
• 41
;
STATBL;
STATBM;
STATBH;
NOTE
The preset value of Timer/Counter Register is calculated as follows:
Internal pulse rate: XIN/2^10 ; XIN = 4MHz
The time of Timer/Counter count one = 2^10 /XIN = 1024/4000=0.256ms
The number of internal pulse to get timer overflow = 60 ms/ 0.256ms = 234.375
= 0EAh
The preset value of Timer/Counter Register = 1000h - 0EAh = F16h
EM73PA00 User's Manual Clock and Timing
• 42
Chapter
6
Interrupt and Power Saving
Functions
6.1 Overview
This chapter summarizes the interrupt and power saving functions of
EM73PA00 CPU.
6.2 Interrupt Function
They are 3 internal interrupt sources. Multiple interrupts are admitted according to their priority .
Internal Timer overflow interrupt (TRGB)
Internal Time base interrupt(TBI)
1
2
3
IL3
IL2
IL1
Interrupt Enable
Condition
EI=1, MASK2=1
EI=1, MASK1=1
EI=1, MASK0=1
Program ROM
Entry Address
006h
008h
00Ah
EM73PA00 User's Manual Interrupt and Power Saving Functions
• 43
6.2.1 Interrupt Structure
TRGB
MASK1 TRGA
MASK2
TIMFC
P11
TIMF
Reset by system reset and program instruction r1
TBI
MASK0 r2
IL1 IL2
CNTFC P11 CNTF r3
IL3
Reset by system reset and program instruction i
Set by program i
Priority Checker
EI
Entry address generator
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• Interrupt and Power Saving Functions
EM73PA00 User’s Manual
Interrupt Controller
IL1-IL3 Interrupt latch. Holds all interrupt requests from all interrupt sources. IL can not be set by the program, but can be reset by program or system reset. So IL can only decide which interrupt source can be accepted.
MASK0 - MASK2 MASK register may promote or inhibit all interrupt sources.
EI Enable interrupt Flip-Flop may promote or inhibit all interrupt sources. When interrupt occurs, EI is auto cleared to "0". After RTI instruction is executed, EI is auto set to "1" again .
Priority Checker Check interrupt priority when multiple interrupts occur.
6.2.2 Interrupt Operation
Follow the steps below for interrupt operation:
1. Locate PC and all flags to stack.
2. Set interrupt entry address to PC.
3. Set SF= 1.
4. Clear EI to inhibit other interrupts happened.
5. Clear the IL with which interrupt source has already been accepted.
6. Execute interrupt subroutine from the interrupt entry address.
7. CPU accept RTI, restore PC and flags from stack . Set EI to accept other interrupt requests.
Example: Enable interrupt “TRGA".
EXAE; set mask register "1100B"
EICIL 111111B ; enable interrupt F.F.
EM73PA00 User’s Manual Interrupt and Power Saving Functions
• 45
6.3 Power Saving (OFF / Sleep) Function
During Off and Sleep Modes, CPU keeps the systems internal status under low power consumption condition.
Under Off Mode, the system clock changes into snooze state. The system needs a warm up period to stabilize the system clock back to running condition after wake-up.
Under Sleep Mode, the system clock does not turn into snooze state. It needs no warm-up period.
6.3.1 Off / Sleep Control
The Off and Sleep Modes are controlled by Port 16, and released by P0(0..3) or P4(0...3), dependent on Mask Option.
P16 3 2 1 0
WM SE SWWT
Initial value: 0000
WM
0
Set wake-up release mode
Wake-up in edge release mode
1 Wake-up in level release mode
SWWT
Set wake-up warm-up time
00 2
16
/XIN
01 2
12
/XIN
10 2
14
/XIN
11 Sleep mode
SE
0
1
OSC
Stop
Stop
Stop
No Stop
Note
Off mode 0
Off mode 1
Off mode 2
No Need warm-up time
Enable off/sleep
Reserved
Enable off/sleep mode
6.3.2 Off and Sleep Conditions
The following conditions exist when system is under Off/Sleep Mode:
• Osc stop (off only) and CPU internal status held
• Internal time base clear to "0"
• CPU internal memory, flags, register, and I/O held original states
• Program Counter freezes at the executed address until CPU released.
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• Interrupt and Power Saving Functions
EM73PA00 User’s Manual
Example: Entry the Off/Sleep mode
OUTA P16 ;entry Off mode1,wakeup in edge.
6.3.3 Release Condition
The following conditions exists when system is wakes-up from Off /Sleep
Mode:
• Osc starts to oscillate (off only)
• Warm-up period in process (off only)
• According PC to execute the following program
6.3.4 Edge Off/Sleep Mode:
Releases the Off/Sleep condition by the falling edge of any of the following pins:
• P0(0..3)
• P4(0..3)
When P0/P4 wakeup in edge/level release mode, must attend to the other
P0/P4 whether enable wakeup release mode, because the wakeup result decide by wakeup function gating. (Ref 4.1.3)
NOTE
There are 8 independent mask options for wake-up function in EM73PA00. So, the wake-up function of P0(0..3) or P4(0...3) is enabled or disabled independently.
HALT condition: Program Counter execute HALT instruction ,OSC not stop and
CPU internal status held. CPU internal memory, flags, register and I/O held original state. When Interrupt happen the HALT condition released.
EM73PA00 User’s Manual Interrupt and Power Saving Functions
• 47
Miscellaneous Function
Chapter
7
7.1 Overview
This chapter describes the remote control signal output, low voltage detector and watch dog timer features of EM73PA00.
7.2 Remote control signal output port
This RMO is a dedicate terminal for carrier wave output of remote controller. When a remote control data is written into the remote control output data register, P1.0, the data is output from RMO terminal as it is.
Port 1
3 2 1 0
* * *
REG Value
RMO
0
Function Description
Output low
1 Output high
Initial state: ***0
7.3 Low Voltage Detector
If power supply voltage is lower than normally operating voltage, automatically initializes internal system. This function can be used by masking option.
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• Miscellaneous Function
EM73PA00 User’s Manual
7.4 Watch Dog Timer
The watch dog timer is an 8-bit timer that protects from runaway programs. The block diagram of the watch dog timer are shown below. The watch dog timer is enabled or disabled by mask option. If watch dog timer is enabled, each interval time whice choosing by P21, the system will be reset.
XIN/2**15
WDT counter
0 1 2 3 4 5 6 7
WDT control
RESET pin
Mask option
P21 WDT register
P21 is the control port of watch dog timer, and the WDT time up signal will reset the system.
Port 21
3 2 1 0
REG Value
Function Description
CWC * WDT
CWC
0
Clear WDT
1 Nothing
Initial state: 0*00
WDT 00 2
19
/XIN
01 2
22
/XIN
10 2
15
/XIN
11 2
12
/XIN
EM73PA00 User’s Manual Miscellaneous Function
• 49
Electrical Properties
Chapter
8
8.1 Overview
This chapter provides information on electrical, thermal and timing properties of the EM73PA00.
8.2 Absolute Maximum Ratings
Items
Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating Temperature
Storage Temperature
Sym.
V
DD
V
IN
V
O
P
D
T
OPR
T
STG
Ratings
-0.3V to 6V
V ss
-0.3V to V
DD
+0.3V
V ss
to V
DD
300mW
-20
°C to 70°C
-40
°C to 125°C
Conditions
T
OPR
= 25
°C
T
OPR
= 25
°C
T
OPR
= 25
°C
T
OPR
= 25
°C
8.3 Recommended Operating Conditions
Condition Items
Supply Voltage
Input Voltage
Operating Frequency
Sym.
V
DD
V
IH
V
IL
Ratings
2.5V to 5.5V
0.80xV
DD
to V
DD
0V to 0.20xV
DD
200KHz to 4MHz
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• Electrical Properties
EM73PA00 User’s Manual
8.4 DC Electrical Characteristics
V
DD
=3V, V
SS
=0V, T
OPR
=--20 o
C to 70 o
C
Parameters Sym. Min Typ. Max. Unit Conditions
no load, Fc=4MHz
Operation current consumpion
I
VDD
- 0.4 1 mA
Standby current consumption
I
DDs
- 0.4 1 uA no load, at OFF mode, No use low voltage detector
I
DDs
- 4 6 uA no load, at OFF mode, Use low voltage detector Standby current consumption
Input Current
High level input current 1
High level input current 2
Low level input current 1
Low level input current 2
High level output current 1
High level output current 2
High level output current 3
Low level output current 1
Low level output current 2
Low level output current 3
Hysteresis width
Low battery detector
I
IH
I
IH1
I
IH2
I
IL1
-120
I
IL2
I
OH1
I
OH2
I
OH3
-900
I
OL1
I
OL2
I
OL3
3
-10
-20
-7
2
4
1.0
10
-50
-4
-10
-3
-450 -200 uA
5
8
1.5
30
-20
-1.5
-5
TEST
P0, P4, P7, V
IH
= V
DD
V
HYS-
- 1 - V
Vlb - 2.3 - V o
C
, Vin=Vdd-0.3V
P0, P4, P7 with pull-up resistor
RESET , Vin=Vss
-1.5 mA P1.1,P7, Vout = 2.1V
15
16
3 uA uA uA mA RMO, Vout = 2.1V
P5, P6, Vout = 2.6V mA RMO, Vout = 0.9V mA P1.1,P7, Vout = 0.9V mA P5, P6, Vout = 0.4V
EM73PA00 User’s Manual Electrical Properties
• 51
V
DD
=4.5V, V
SS
=0V, T
OPR
=--20 o
C to 70 o
C
Parameters Sym. Min Typ. Max. Unit Conditions
Operation current consumpion
Standby current consumption
Standby current consumption
Input Current
High level input current 1
High level input current 2
Low level input current 1
Low level input current 2
High level output current 1
High level output current 2
High level output current 3
Low level output current 1
Low level output current 2
Low level output current 3
Hysteresis width
Low battery detector
I
I
I
I
VDD
I
DDs
I
DDs
I
I
I
I
IH
I
IH1
-
-
-
20
1
0.8
4
30
2
1.5
6
50 mA uA uA uA
No load, Fc=4MHz
No load, at OFF mode, No use low voltage detector
No load, at OFF mode, Use low voltage detector
TEST
P0, P4, P7, V
IH
= V
DD
I
IH2
-11 -8 -5 uA
RESET
, Vin=Vdd-0.3V
I
I
IL1
IL2
OH1
OH2
OH3
OL1
OL2
OL3
-200
-20
-30
-10
5
8
1.0
-150
-15
-20
-7
15
12
1.5
-100
-10
-10
-3
-1.2 -0.9 -0.6
25
20
3 uA uA
RESET
, Vin=Vss mA RMO, Vout = 3.2V mA mA mA mA
P0, P4, P7 with pull-up resistor
P1.1,P7, Vout = 3.2V
P5, P6, Vout = 3.9V
RMO, Vout = 0.9V
P1.1,P7, Vout = 0.9V
P5, P6, Vout = 0.4V
V
HYS-
- 1 - V
Vlb - 2.3 - V o
C
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• Electrical Properties
EM73PA00 User’s Manual
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Key features
Si gate CMOS process
Low power consumption
High-speed operation
24K-byte ROM
128-nibble RAM
4-bit ALU
16-level subroutine nesting
13-bit programmable counter
8-bit watchdog timer
13-bit programmable timer
Frequently asked questions
The maximum operating frequency is 4MHz.
It has 128 nibbles of RAM.
The watchdog timer is a safety feature that helps prevent the microcontroller from getting stuck in an infinite loop.
These are different package types for the EM73PA00. EM73PA00H is chip form, EM73PA00AM is 28-pin SOP, and EM73PA00BM is 28-pin TSSOP.
