Atmel AT90S8414 Manual

AT90S8414
Contents
PIN CONFIGURATIONS ............................................................................................................................................... 4-5
BLOCK DIAGRAM ......................................................................................................................................................... 4-6
DESCRIPTION................................................................................................................................................................. 4-7
Pin Descriptions.............................................................................................................................................................. 4-8
Crystal Oscillator ............................................................................................................................................................ 4-9
AT90S8414 AVR RISC MICROCONTROLLER CPU .......................................................................................... 4-10
Architectural Overview ................................................................................................................................................ 4-10
The General Purpose Register File ............................................................................................................................... 4-11
THE X-REGISTER, Y-REGISTER AND Z-REGISTER ....................................................................................................................................... 4-12
The ALU - Arithmetic Logic Unit................................................................................................................................ 4-13
The Downloadable Flash Program Memory................................................................................................................. 4-13
The SRAM Data Memory - Internal and External ....................................................................................................... 4-13
The Program and Data Addressing Modes ................................................................................................................... 4-15
REGISTER DIRECT, SINGLE REGISTER Rd...................................................................................................................................................... 4-15
REGISTER DIRECT, TWO REGISTERS Rd AND Rr .......................................................................................................................................... 4-15
I/O DIRECT .............................................................................................................................................................................................................. 4-16
SRAM DIRECT........................................................................................................................................................................................................ 4-16
SRAM DIRECT WITH DISPLACEMENT............................................................................................................................................................. 4-16
SRAM/REGISTER INDIRECT ............................................................................................................................................................................... 4-17
SRAM/REGISTER INDIRECT WITH PRE-DECREMENT ................................................................................................................................. 4-17
SRAM/REGISTER INDIRECT WITH POST-INCREMENT ................................................................................................................................ 4-17
CONSTANT ADDRESSING USING THE LPM INSTRUCTION........................................................................................................................ 4-18
DIRECT PROGRAM ADDRESS, JMP AND CALL ............................................................................................................................................. 4-18
INDIRECT PROGRAM ADDRESSING, IJMP AND ICALL ............................................................................................................................... 4-18
RELATIVE PROGRAM ADDRESSING, RJMP AND RCALL............................................................................................................................ 4-19
The EEPROM Data Memory........................................................................................................................................ 4-19
Memory Access Times and Instruction Execution Timing .......................................................................................... 4-19
I/O Memory .................................................................................................................................................................. 4-22
THE STATUS REGISTER - SREG ......................................................................................................................................................................... 4-23
THE STACK POINTER - SP ................................................................................................................................................................................... 4-24
Reset and Interrupt Handling........................................................................................................................................ 4-24
RESET SOURCES ................................................................................................................................................................................................... 4-25
POWER-ON RESET ................................................................................................................................................................................................ 4-26
EXTERNAL RESET ................................................................................................................................................................................................ 4-27
WATCHDOG RESET .............................................................................................................................................................................................. 4-27
INTERRUPT HANDLING ...................................................................................................................................................................................... 4-28
THE GENERAL INTERRUPT MASK REGISTER - GIMSK............................................................................................................................... 4-28
THE TIMER/COUNTER INTERRUPT MASK REGISTER - TIMSK.................................................................................................................. 4-29
THE TIMER/COUNTER INTERRUPT FLAG REGISTER - TIFR ...................................................................................................................... 4-29
EXTERNAL INTERRUPTS .................................................................................................................................................................................... 4-30
INTERRUPT RESPONSE TIME............................................................................................................................................................................. 4-32
MCU CONTROL REGISTER - MCUCR................................................................................................................................................................ 4-32
Sleep Modes.................................................................................................................................................................. 4-32
IDLE MODE............................................................................................................................................................................................................. 4-33
POWER DOWN MODE .......................................................................................................................................................................................... 4-33
TIMER / COUNTERS.................................................................................................................................................... 4-33
The Timer/Counter Prescaler........................................................................................................................................ 4-33
The 8-Bit Timer/Counter0 ............................................................................................................................................ 4-34
THE TIMER/COUNTER0 CONTROL REGISTER - TCCR0 ............................................................................................................................... 4-35
THE TIMER COUNTER 0 - TCNT0....................................................................................................................................................................... 4-36
THE OUTPUT COMPARE REGISTER 0 - OCR0................................................................................................................................................. 4-36
The 16-Bit Timer/Counter1 .......................................................................................................................................... 4-36
THE TIMER/COUNTER1 CONTROL REGISTER A - TCCR1A ........................................................................................................................ 4-39
Preliminary
4-1
THE TIMER/COUNTER1 CONTROL REGISTER B - TCCR1B......................................................................................................................... 4-39
THE TIMER/COUNTER1 - TCNT1H AND TCNT1L........................................................................................................................................... 4-40
TIMER/COUNTER1 OUTPUT COMPARE REGISTER - OCR1AH AND OCR1AL......................................................................................... 4-41
TIMER/COUNTER1 OUTPUT COMPARE REGISTER - OCR1BH AND OCR1BL ......................................................................................... 4-41
THE TIMER/COUNTER1 INPUT CAPTURE REGISTER - ICR1H AND ICR1L .............................................................................................. 4-41
TIMER/COUNTER1 IN PWM MODE ................................................................................................................................................................... 4-42
THE WATCHDOG TIMER.......................................................................................................................................... 4-43
THE WATCHDOG TIMER CONTROL REGISTER - WDTCR........................................................................................................................... 4-44
EEPROM READ/WRITE ACCESS............................................................................................................................. 4-44
THE EEPROM ADDRESS REGISTER - EEAR .................................................................................................................................................... 4-45
THE EEPROM DATA REGISTER - EEDR ........................................................................................................................................................... 4-45
THE EEPROM CONTROL REGISTER - EECR.................................................................................................................................................... 4-45
THE SERIAL PERIPHERAL INTERFACE - SPI..................................................................................................... 4-46
THE SPI CONTROL REGISTER - SPCR............................................................................................................................................................... 4-48
THE SPI STATUS REGISTER - SPSR ................................................................................................................................................................... 4-49
THE SPI DATA REGISTER - SPDR ...................................................................................................................................................................... 4-50
THE UART...................................................................................................................................................................... 4-50
Data Transmission ........................................................................................................................................................ 4-50
Data Reception.............................................................................................................................................................. 4-52
UART Control .............................................................................................................................................................. 4-53
THE UART I/O DATA REGISTER - UDR ............................................................................................................................................................ 4-53
THE UART STATUS REGISTER - USR ............................................................................................................................................................... 4-53
THE UART CONTROL REGISTER - UCR ........................................................................................................................................................... 4-54
THE BAUD RATE GENERATOR.......................................................................................................................................................................... 4-55
THE UART BAUD RATE REGISTER - UBRR..................................................................................................................................................... 4-56
THE ANALOG COMPARATOR................................................................................................................................. 4-57
THE ANALOG COMPARATOR CONTROL AND STATUS REGISTER - ACSR ............................................................................................ 4-57
I/O-PORTS ...................................................................................................................................................................... 4-58
Port A............................................................................................................................................................................ 4-58
THE PORT A DATA REGISTER - PORTA........................................................................................................................................................... 4-59
THE PORT A DATA DIRECTION REGISTER - DDRA...................................................................................................................................... 4-59
THE PORT A INPUT PINS ADDRESS - PINA ..................................................................................................................................................... 4-59
PORTA AS GENERAL DIGITAL I/O .................................................................................................................................................................... 4-59
PORT A SCHEMATICS .......................................................................................................................................................................................... 4-60
Port B ............................................................................................................................................................................ 4-60
THE PORT B DATA REGISTER - PORTB ........................................................................................................................................................... 4-61
THE PORT B DATA DIRECTION REGISTER - DDRB ...................................................................................................................................... 4-61
THE PORT B INPUT PINS ADDRESS - PINB...................................................................................................................................................... 4-61
PORTB AS GENERAL DIGITAL I/O .................................................................................................................................................................... 4-61
ALTERNATE FUNCTIONS FOR PORTB............................................................................................................................................................. 4-62
PORT B SCHEMATICS .......................................................................................................................................................................................... 4-63
Port C ............................................................................................................................................................................ 4-66
THE PORT C DATA REGISTER - PORTC ........................................................................................................................................................... 4-66
THE PORT C DATA DIRECTION REGISTER - DDRC ...................................................................................................................................... 4-67
THE PORT C INPUT PINS ADDRESS - PINC...................................................................................................................................................... 4-67
PORTC AS GENERAL DIGITAL I/O .................................................................................................................................................................... 4-67
PORT C SCHEMATICS .......................................................................................................................................................................................... 4-67
Port D............................................................................................................................................................................ 4-69
THE PORT D DATA REGISTER - PORTD........................................................................................................................................................... 4-69
THE PORT D DATA DIRECTION REGISTER - DDRD...................................................................................................................................... 4-69
THE PORT D INPUT PINS ADDRESS - PIND ..................................................................................................................................................... 4-69
PORTD AS GENERAL DIGITAL I/O .................................................................................................................................................................... 4-70
ALTERNATE FUNCTIONS FOR PORTD............................................................................................................................................................. 4-70
PORTD SCHEMATICS ........................................................................................................................................................................................... 4-71
MEMORY PROGRAMMING...................................................................................................................................... 4-74
4-2
AT90S8414 Preliminary
AT90S8414
Program Memory Lock Bits ......................................................................................................................................... 4-74
Programming the Flash and EEPROM......................................................................................................................... 4-74
Parallel Programming ................................................................................................................................................... 4-75
Serial Downloading ...................................................................................................................................................... 4-75
SERIAL PROGRAMMING ALGORITHM ............................................................................................................................................................ 4-75
Programming Characteristics........................................................................................................................................ 4-79
ABSOLUTE MAXIMUM RATINGS ........................................................................................................................... 4-79
D.C. CHARACTERISTICS........................................................................................................................................... 4-80
A.C. CHARACTERISTICS........................................................................................................................................... 4-81
EXTERNAL DATA MEMORY READ CYCLE......................................................................................................... 4-81
EXTERNAL MEMORY WRITE CYCLE .................................................................................................................. 4-82
XTERNAL CLOCK DRIVE WAVEFORMS ............................................................................................................. 4-82
EXTERNAL CLOCK DRIVE....................................................................................................................................... 4-82
ORDERING INFORMATION...................................................................................................................................... 4-83
AT90S8414 REGISTER SUMMARY........................................................................................................................... 4-84
AT90S8414 INSTRUCTION SET SUMMARY........................................................................................................... 4-85
Preliminary
4-3
4-4
AT90S8414 Preliminary
AT90S8414
Features
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Utilizes the AVRä Enhanced RISC Architecture
AVRä - High Performance and Low Power RISC Architecture
120 Powerful Instructions - Most Single Clock Cycle Execution
Efficient Context Switching Concept
8 Kbytes of In-System Reprogrammable Downloadable Flash
SPI Serial Interface for Program Downloading
Endurance: 1,000 Write/Erase Cycles
256 bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
256 bytes Internal RAM
32 x 8 General Purpose Working Registers
32 Programmable I/O Lines
Programmable Serial UART
SPI Serial Interface
VCC Min.: 2.7 V
Fully Static Operation
One 8-Bit Timer/Counter with Separate Prescaler
One 16-Bit Timer/Counter with Separate Prescaler
and Compare and Capture Modes
Dual 10 bit PWM
External and Internal Interrupt Sources
Programmable Watchdog Timer
On-Chip Analog Comparator
Low Power Idle and Power Down Modes
Programming Lock for Software Security
8-Bit
Microcontroller
with 8K bytes
Downloadable
Flash
Pin Configurations
Preliminary
4-5
Block Diagram
Figure 1: The AT90S8414 Block Diagram
4-6
AT90S8414 Preliminary
AT90S8414
Description
The AT90S8414 is a low-power CMOS 8 bit microcontroller based on the AVR enhanced RISC architecture. By
executing powerful instructions in a single clock cycle, the AT90S8414 achieves throughputs approaching 1 MIPS per
MHz allowing the system designer to optimize power consumption versus processing speed.
The AVR core is based on an enhanced RISC architecture that combines a rich instruction set with 32 general purpose
working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two
independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is
more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The
architecture supports high level languages efficiently while on-chip context switching hardware allows high performance,
low power real timer control system design.
The AT90S8414 provides the following features: 8K bytes of Downloadable Flash, 256-bytes EEPROM, 256-bytes
SRAM, 32 general purpose I/O lines, 32 general purpose working registers, flexible timer/counters with compare modes,
internal and external interrupts, a programmable serial UART, programmable Watchdog Timer with internal oscillator,
an SPI serial port and two software selectable power saving modes. The Idle Mode stops the CPU while allowing the
SRAM, timer/counters, SPI port and interrupt system to continue functioning. The power down mode saves the register
contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.
The device is manufactured using Atmel’s high density non-volatile memory technology. The on-chip Downloadable
Flash allows the program memory to be reprogrammed in-system through an SPI serial interface or by a conventional
nonvolatile memory programmer. By combining an enhanced RISC 8 bit CPU with Downloadable Flash on a monolithic
chip, the Atmel AT90S8414 is a powerful microcontroller that provides a highly flexible and cost effective solution to
many embedded control applications.
The AT90S8414 AVR is supported with a full suite of program and system development tools including: C compilers,
macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
Preliminary
4-7
Pin Descriptions
VCC
Supply voltage
GND
Ground
Port A (PA7..PA0)
Port A is an 8-bit bidirectional I/O port. Port pins can provide internal pullups (selected for each bit). The Port A output
buffers can sink 20mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are externally
pulled low, they will source current (IIL) if the internal pullups are activated.
Port A serves as Multiplexed Address/Data input/output when using external SRAM.
Port B (PB7..PB0)
Port B is an 8-bit bidirectional I/O pins with internal pullups. The Port B output buffers can sink 20 mA. As inputs, Port
B pins that are externally pulled low will source current (IIL) if the pullups are activated.
Port B also serves the functions of various special features of the AT90S8414 as listed on Page 4-62.
Port C (PC7..PC0)
Port C is an 8-bit bidirectional I/O port with internal pullups. The Port C output buffers can sink 20 mA. As inputs, Port
C pins that are externally pulled low will source current (IIL) if the pullups are activated.
Port C also serves as Address output when using external SRAM.
Port D (PD7..PD0)
Port D is an 8-bit bidirectional I/O port with internal pullups. The Port D output buffers can sink 20 mA. As inputs, Port
D pins that are externally pulled low will source current (IIL) if the pullups are activated.
Port D also serves the functions of various special features of the AT90S8414 as listed on Page 4-70.
RESET
Reset input. A low on this pin for two machine cycles while the oscillator is running resets the device.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier
ICP / VPP
ICP is the input pin for the Timer/Counter1 Input Capture function.
When programming the AT90S8414 in parallel programming mode, the programming voltage, VPP is applied to this pin.
OC1B
OC1B is the output pin for the Timer/Counter1 Output CompareB function
4-8
AT90S8414 Preliminary
AT90S8414
ALE / PROG
ALE is the Address Latch Enable used when the External Memory is enabled. The ALE strobe is used to latch the loworder address (8 bits) into an address latch during the first access cycle, and the AD0-7 pins are used for data during the
second access cycle.
In parallel programming mode, this pin is pulsed to write data.
Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively , of an inverting amplifier which can be configured for use as an
on-chip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device
from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3.
Figure 2: Oscillator Connections
Figure 3: External Clock Drive Configuration
Preliminary
4-9
AT90S8414 AVR RISC Microcontroller CPU
The AT90S8414 AVR RISC microcontroller is upward compatible with the AVR Enhanced RISC Architecture. The
programs written for the AT90S8414 MCU are fully compatible with the range of AVR 8-bit MCUs (AT90Sxxxx) with
respect to source code and clock cycles for execution.
Architectural Overview
The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle
access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two
operands are output from the register file, the operation is executed, and the result is stored back in the register file - in
one clock cycle.
Six of the 32 registers can be used as three 16-bits indirect address register pointers for SRAM addressing - enabling
efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table
look up function. These added function registers are the 16-bits X-register, Y-register and Z-register.
Figure 4: The AT90S8414 AVR Enhanced RISC Architecture
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register
operations are also executed in the ALU. Figure 4 shows the AT90S8414 AVR Enhanced RISC microcontroller
architecture.
4-10
AT90S8414 Preliminary
AT90S8414
In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.
This is enabled by the fact that the register file is assigned the 32 lowermost SRAM addresses, allowing them to be
accessed as though they were ordinary memory locations.
The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program
memory is executed with a single level pipelining. While one instruction is being executed, the next instruction is prefetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program
memory is in-system downloadable Flash memory.
With the relative jump and call instructions, the whole 4K address space is directly accessed. All AVR instructions have a
single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size
and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts
are executed). The 16-bit stack pointer SP is read/write accessible in the I/O space.
The 256 bytes data SRAM can be easily accessed through the four different addressing modes supported in the AVR
architecture.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/Dconverters, and other I/O functions. The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the
status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of
the program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower
the interrupt address vector the higher priority.
Preliminary
4-11
The General Purpose Register File
Figure 5 shows the structure of the 32 general purpose working registers in the CPU.
7
General
Purpose
Working
Registers
0
R0
R1
R2
…
R13
R14
R15
R16
R17
…
R26
R27
R28
R29
R30
R31
Addr.
$00
$01
$02
$0D
$0E
$0F
$10
$11
$1A
$1B
$1C
$1D
$1E
$1F
X-register low byte
X-register high byte
Y-register low byte
Y-register high byte
Z-register low byte
Z-register high byte
Figure 5: AVR CPU general purpose working registers
All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only
exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and
a register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the
registers in the register file - R16..R31. The general SBC, SUB, CP, AND and OR and all other operations between two
registers or on a single register apply to the entire register file.
As shown in Figure 5, each register is also assigned a data memory address, mapping them directly into the first 32
locations of the user SRAM area. Although not being physically implemented as SRAM locations, this memory
organization provides great flexibility in access of the registers, as the X ,Y and Z registers can be set to index any
register in the file.
The 256 bytes of SRAM available for general data are implemented as addresses $0020 to $011F.
4-12
AT90S8414 Preliminary
AT90S8414
THE X-REGISTER, Y-REGISTER AND Z-REGISTER
The registers R26..R31 have some added functions to their general purpose usage. These registers are address pointers for
indirect addressing of the SRAM. The three indirect address registers X, Y and Z are defined as:
X - register
15
7
0
R27 ($1B)
Y - register
15
7
R26 ($1A)
0
15
7
0
0
7
R29 ($1D)
Z - register
0
0
7
R28 ($1C)
0
0
0
7
R31 ($1F)
R30 ($1E)
Figure 6: The X, Y and Z Registers
In the different addressing modes these address registers have functions as fixed displacement, automatic increment and
decrement (see the descriptions for the different instructions).
The ALU - Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within
a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided
into three main categories - arithmetic, logic and bit-functions. Some microcontrollers in the AVR product family feature
a hardware multiplier in the arithmetic part of the ALU.
The Downloadable Flash Program Memory
The AT90S8414 contains 8K bytes on-chip downloadable Flash memory for program storage. Since all instructions are
single 16-bit words, the Flash is organized as 4K x 16 words. The Flash memory has an endurance of at least 1000
write/erase cycles.
See Page 4-74 for a detailed description on Flash data downloading.
Constant tables must be allocated within the address 0-4K (see the LPM - Load Program Memory instruction
description).
See Page 4-15 for the different program memory addressing modes.
Preliminary
4-13
The SRAM Data Memory - Internal and External
The following figure shows how the AT90S8414 SRAM Memory is organized:
Register File
R0
R1
R2
¼
SRAM
$0000
$0001
$0002
¼
R29
R30
R31
$001D
$001E
$001F
$0020
$0021
¼
Internal SRAM start®
Internal SRAM end®
External SRAM start®
External SRAM end®
$011D
$011E
$011F
$0120
$0121
…
$FFFE
$FFFF
Figure 7: SRAM Organization
The 288 top SRAM Memory locations address both the Register file and the internal data SRAM. The first 32 locations
address the register file, and the next 256 locations address the internal data SRAM. An optional external data SRAM can
be placed in the same SRAM memory space. Following the last address of the internal SRAM space and up to 64K - 1, is
the external data SRAM address area.
When the addresses accessing the SRAM memory space exceeds the internal data SRAM locations, the external data
SRAM is accessed using the same instructions as for the internal data SRAM access. When the internal data SRAM is
accessed, the read and write strobe pins ( RD and WR ) are inactive during the whole access cycle. The external data
SRAM physical address locations corresponding to the internal data SRAM addresses can not be reached by the CPU.
External SRAM operation is enabled by setting the SRE bit in the MCUCR register. See Page 4-32 for details.
The five different addressing modes for the SRAM data memory cover: Direct, Direct with Displacement, Indirect,
Indirect with Pre-Decrement and Indirect with Post-Increment. In the register file, registers R26 to R31 feature the
indirect addressing pointer registers.
The Direct with Displacement mode features a 63 address locations reach from the base address given by the Y or Zregister.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X,
Y and Z are decremented and incremented.
4-14
AT90S8414 Preliminary
AT90S8414
The 32 general purpose working registers, the 256 bytes of internal data SRAM, and the 64K bytes of optional external
data SRAM in the AT90S8414 are all accessible through all these addressing modes.
See the next section for a detailed description of the different addressing modes.
The Program and Data Addressing Modes
The AT90S8414 AVR Enhanced RISC microcontroller supports powerful and efficient addressing modes for access to
the program memory (Flash) and data memory (SRAM). This section describes the different addressing modes supported
by the AVR architecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all
figures show the exact location of the addressing bits.
REGISTER DIRECT, SINGLE REGISTER Rd
Figure 8: Direct Single Register Addressing
The operand is contained in register d (Rd).
REGISTER DIRECT, TWO REGISTERS Rd AND Rr
Figure 9: Direct Register Addressing, Two Registers
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).
Preliminary
4-15
I/O DIRECT
Figure 10: I/O Direct Addressing
Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.
SRAM DIRECT
Figure 11: Direct SRAM Addressing
A 16-bit SRAM or Register Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination
or source register.
SRAM DIRECT WITH DISPLACEMENT
Figure 12: SRAM Direct with Displacement
Operand address is the result of the Y or Z-register contents added to the address contained in 6 bits of the instruction
word.
4-16
AT90S8414 Preliminary
AT90S8414
SRAM/REGISTER INDIRECT
Figure 13: SRAM Indirect Addressing
Operand address is the contents of the X, Y or the Z-register.
SRAM/REGISTER INDIRECT WITH PRE-DECREMENT
Figure 14: SRAM Indirect Addressing With Pre-Decrement
The X, Y or the Z-register is decremented before the operation. Operand address is the decremented contents of the X, Y
or the Z-register.
SRAM/REGISTER INDIRECT WITH POST-INCREMENT
Figure 15: SRAM Indirect Addressing With Post-Increment
The X, Y or the Z-register is incremented after the operation. Operand address is the content of the X, Y or the Z-register
prior to incrementing.
Preliminary
4-17
CONSTANT ADDRESSING USING THE LPM INSTRUCTION
Figure 16: Code Memory Constant Addressing
Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 4K) and LSB, select
low byte if cleared (LSB = 0) or high byte if set (LSB = 1).
DIRECT PROGRAM ADDRESS, JMP AND CALL
Figure 17: Direct Program Memory Addressing
Program execution continues at the address immediate in the instruction words.
INDIRECT PROGRAM ADDRESSING, IJMP AND ICALL
Figure 18: Indirect Program Memory Addressing
Program execution continues at address contained by the Z-register (i.e. the PC is loaded with the contents of the Zregister).
4-18
AT90S8414 Preliminary
AT90S8414
RELATIVE PROGRAM ADDRESSING, RJMP AND RCALL
Figure 19: Relative Program Memory Addressing
Program execution continues at address PC + k. The relative address k is ± 2K.
The EEPROM Data Memory
The AT90S8414 contains 256 bytes of data EEPROM memory. It is organized as a separate data space, in which single
bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between
the EEPROM and the CPU is described on Page 4-44 specifying the EEPROM address register, the EEPROM data
register, and the EEPROM control register.
For the SPI data downloading, see Page 4-75 for a detailed description.
Memory Access Times and Instruction Execution Timing
This section describes the general access timing concepts for instruction execution and internal memory access.
The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the chip. No
internal clock division is used.
Figure 20 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the
fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the
corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
T1
T2
T3
T4
System Clock Ø
1’st Instruction Fetch
1’st Instruction Execute
2’nd Instruction Fetch
2’nd Instruction Execute
3’rd Instruction Fetch
3’rd Instruction Execute
4’th Instruction Fetch
Figure 20: The Parallel Instruction Fetches and Instruction Executions
Preliminary
4-19
Figure 21 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two
register operands is executed, and the result is stored back to the destination register.
T1
T2
T3
T4
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Store Result in Register
Figure 21: Single Cycle ALU Operation
The internal data SRAM access is performed in two System Clock cycles as described in Figure 22.
T1
T2
T3
T4
System Clock Ø
Internal Address Bus
Internal Read Signal
Internal Data Bus (read)
Internal Write Signal
Internal Data Bus (write)
Figure 22: On-Chip Data SRAM Access Cycles
The external data SRAM access is performed in two System Clock cycles as described in Figure 23.
4-20
AT90S8414 Preliminary
AT90S8414
T1
T2
T3
T4
System Clock Ø
External Address [7..0]
External Address [15..8]
ALE
External Data Bus (read)
External Data Bus (write)
RD
WR
Figure 23: External Data SRAM Memory Cycles without Wait State
The external data SRAM memory access cycle with the Wait State bit enabled (Wait State active) is shown in Figure 24.
T1
T2
T3
T4
System Clock Ø
External Address [7..0]
External Address [15..8]
ALE
External Data Bus (read)
External Data Bus (write)
RD
WR
Internal Wait State
Figure 24: External Data SRAM Memory Cycles with Wait State
Preliminary
4-21
I/O Memory
The I/O space definition of the AT90S8414 is shown in the following table:
Table 1: AT90S8414 I/O Space
Address Hex
$3F
$3E
$3D
$3B
$39
$38
$35
$33
$32
$31
$2F
$2E
$2D
$2C
$2B
$2A
$29
$28
$25
$24
$21
$1E
$1D
$1C
$1B
$1A
$19
$18
$17
$16
$15
$14
$13
$12
$11
$10
$0F
$0E
$0D
$0C
$0B
$0A
$09
$08
Name
SREG
SPH
SPL
GIMSK
TIMSK
TIFR
MCUCR
TCCR0
TCNT0
OCR0
TCCR1A
TCCR1B
TCNT1H
TCNT1L
OCR1AH
OCR1AL
OCR1BH
OCR1BL
ICR1H
ICR1L
WDTCR
EEAR
EEDR
EECR
PORTA
DDRA
PINA
PORTB
DDRB
PINB
PORTC
DDRC
PINC
PORTD
DDRD
PIND
SPDR
SPSR
SPCR
UDR
USR
UCR
UBRR
ACSR
Function
Status REGister
Stack Pointer High
Stack Pointer Low
General Interrupt MaSK register
Timer/Counter Interrupt MaSK register
Timer/Counter Interrupt Flag register
MCU general Control Register
Timer/Counter0 Control Register
Timer/Counter0 (8-bit)
Timer/Counter0 Output Compare Register
Timer/Counter1 Control Register A
Timer/Counter1 Control Register B
Timer/Counter1 High Byte
Timer/Counter1 Low Byte
Timer/Counter1 Output Compare Register A High Byte
Timer/Counter1 Output Compare Register A Low Byte
Timer/Counter1 Output Compare Register B High Byte
Timer/Counter1 Output Compare Register B Low Byte
T/C 1 Input Capture Register High Byte
T/C 1 Input Capture Register Low Byte
Watchdog Timer Control Register
EEPROM Address Register
EEPROM Data Register
EEPROM Control Register
Data Register, Port A
Data Direction Register, Port A
Input Pins, Port A
Data Register, Port B
Data Direction Register, Port B
Input Pins, Port B
Data Register, Port C
Data Direction Register, Port C
Input Pins, Port C
Data Register, Port D
Data Direction Register, Port D
Input Pins, Port D
SPI I/O Data Register
SPI Status Register
SPI Control Register
UART I/O Data Register
UART Status Register
UART Control Register
UART Baud Rate Register
Analog Comparator Control and Status Register
Note: reserved and unused locations are not shown in the table
All the different AT90S8414 I/Os and peripherals are placed in the I/O space. The different I/O locations are accessed by
the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space. I/O
4-22
AT90S8414 Preliminary
AT90S8414
registers within the address range $00 - $19 are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set
chapter for more details.
The different I/O and peripherals control registers are explained in the following chapters.
THE STATUS REGISTER - SREG
The AVR status register - SREG - at I/O space location $3F is defined as:
Bit
$3F
Read/Write
Initial value
7
I
R/W
0
6
T
R/W
0
5
H
R/W
0
4
S
R/W
0
3
V
R/W
0
2
N
R/W
0
1
Z
R/W
0
0
C
R/W
0
SREG
Bit 7 - I : Global Interrupt Enable:
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is
then performed in the interrupt mask registers - GIMSK and TIMSK. If the global interrupt enable register is cleared
(zero), none of the interrupts are enabled independent of the GIMSK and TIMSK values. The I-bit is cleared by hardware
after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.
Bit 6 - T : Bit Copy Storage:
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated
bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into
a bit in a register in the register file by the BLD instruction.
Bit 5 - H : Half Carry Flag:
The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed
information.
Bit 4 - S : Sign Bit, S = N Å V :
The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the
Instruction Set Description for detailed information.
Bit 3 - V : Two’s Complement Overflow Flag:
The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for
detailed information.
Bit 2 - N : Negative Flag:
The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set
Description for detailed information.
Bit 1 - Z : Zero Flag:
The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set
Description for detailed information.
Bit 0 - C : Carry Flag:
The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed
information.
Preliminary
4-23
THE STACK POINTER - SP
The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E and
$3D. Since the stack address space is within the data SRAM, a 9 bit stack pointer is used to address the stack in the
AT90S8414.
Bit
$3E
$3D
Read/Write
Initial value
15
SP7
7
R
R/W
0
0
14
SP6
6
R
R/W
0
0
13
SP5
5
R
R/W
0
0
12
SP4
4
R
R/W
0
0
11
SP3
3
R
R/W
0
0
10
SP2
2
R
R/W
0
0
9
SP1
1
R
R/W
0
0
8
SP8
SP0
0
R/W
R/W
0
0
SPH
SPL
The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack
space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are
enabled. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it
is decremented by two when data is pushed onto the Stack with subroutine CALL and interrupt. The Stack Pointer is
incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data
is popped from the Stack with return from subroutine RET or return from interrupt IRET.
Reset and Interrupt Handling
The AT90S8414 provides 13 different interrupt sources. These interrupts and the separate reset vector, each have a
separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be
set (one) together with the I-bit in the status register in order to enable the interrupt.
The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The
complete list of vectors is shown in Table 2. The list also determines the priority levels of the different interrupts. The
lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External
Interrupt Request 0 etc.
Table 2: Reset and Interrupt Vectors
Vector No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Program Address
$000
$001
$002
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
Source
RESET
INT0
INT1
TIMER1 CAPT
TIMER1 COMPA
TIMER1 COMPB
TIMER1 OVF
TIMER0, COMP
TIMER0, OVF
SPI, STC
UART, RX
UART, UDRE
UART, TX
ANA_COMP
Interrupt Definition
Hardware Pin and Watchdog Reset
External Interrupt Request 0
External Interrupt Request 1
Timer/Counter1 Capture Event
Timer/Counter1 Compare Match A
Timer/Counter1 Compare Match B
Timer/Counter1 Overflow
Timer/Counter0 Compare Match
Timer/Counter0 Overflow
Serial Transfer Complete
UART, Rx Complete
UART Data Register Empty
UART, Tx Complete
Analog Comparator
The most typical and general program setup for the Reset and Interrupt Vector Addresses are:
4-24
AT90S8414 Preliminary
AT90S8414
Address
$000
$001
$002
$003
$004
$005
$006
$007
$008
$009
$00a
$00b
$00c
$00d
;
$00e
…
Labels
MAIN:
…
Code
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
RESET
EXT_INT0
EXT_INT1
TIM1_CAPT
TIM1_COMPA
TIM1_COMPB
TIM1_OVF
TIM0_COMP
TIM0_OVF
SPI_HANDLE
UART_RXC
UART_DRE
UART_TXC
ANA_COMP
<instr>
…
xxx
…
Comments
; Reset Handle
; IRQ0 Handle
; IRQ1 Handle
; Timer1 capture Handle
; Timer1 compareA Handle
; Timer1 compareB Handle
; Timer1 overflow Handle
; Timer0 compare Handle
; Timer0 overflow Handle
; SPI TX Handle
; UART RX Complete Handle
; UDR Empty Handle
; UART TX Complete Handle
; Analog Comparator Handle
; Main program start
RESET SOURCES
The AT90S2312 has three sources of reset:
· Power-On Reset. The MCU is reset when a supply voltage is applied to the VCC and GND pins.
· External Reset. The MCU is reset when a low level is present on the RESET pin for more than two XTAL cycles
· Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled.
During reset, all I/O registers are then set to their initial values, and the program starts execution from address $000. The
instruction placed in address $000 must be an RJMP - relative jump - instruction to the reset handling routine. If the
program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at
these locations. The circuit diagram in Figure 25 shows the reset logic. Table 3 defines the timing and electrical
parameters of the reset circuitry.
Figure 25: Reset Logic
Table 3: Reset Characteristics
Symbol
Parameter
Min
Typ
Max
Units
VPOT
Power-On Reset Threshold Voltage
1.8
2
2.2
V
VRST
TPOR
RESET Pin Threshold Voltage
Power-On Reset Period
2
3
4
ms
TTOUT
Reset Delay Time-Out Period
11
16
21
ms
VCC/2
V
Preliminary
4-25
POWER-ON RESET
A Power-On Reset (POR) circuit ensures that the device is not started until the XTAL oscillator has stabilized. As shown
in Figure 25, an internal timer clocked from the Watchdog timer oscillator prevents the MCU from starting until after a
certain period after VCC has reached the Power-On Threshold voltage - VPOT, regardless of the VCC rise time (see Figure
26 and Figure 27). The total reset period is the Power-On Reset period - tPOR + the Delay Time-out period - tTOUT.
As the RESET pin is pulled high by an on-chip resistor, the pin can be left unconnected if no external reset is required.
Connecting RESET to VCC will have the same effect. By holding the RESET pin low for a period after VCC has been
applied, the Power-On Reset period can be extended. Refer to Figure 28 for a timing example on this.
Figure 26: MCU Start-Up, RESET Tied to VCC or Unconnected. Rapidly Rising VCC
Figure 27: MCU Start-Up, RESET Tied to VCC or Unconnected. Slowly Rising VCC
4-26
AT90S8414 Preliminary
AT90S8414
Figure 28: MCU Start-Up, RESET Controlled Externally
EXTERNAL RESET
An external reset is generated by a low level on the RESET pin. The pin must be held low for at least two crystal clock
cycles. When RESET reaches the Reset Threshold Voltage - VRST on its positive edge, the delay timer starts the MCU
after the Time-out period tTOUT has expired.
Figure 29: External Reset During Operation
WATCHDOG RESET
When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration. On the falling edge of this
pulse, the delay timer starts counting the Time-out period tTOUT . Refer to Page 3-43 for details on operation of the
Watchdog.
Preliminary
4-27
Figure 30: Watchdog Reset During Operation
INTERRUPT HANDLING
The AT90S8414 has two 8-bit Interrupt Mask control registers; GIMSK - General Interrupt Mask register and TIMSK Timer/Counter Interrupt Mask register.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user
software must set (one) the I-bit to enable interrupts.
When the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine,
hardware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by
writing a logic one to the flag bit position(s) to be cleared.
THE GENERAL INTERRUPT MASK REGISTER - GIMSK
Bit
$3B
Read/Write
Initial value
7
INT1
R/W
0
6
INT0
R/W
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
R
0
GIMSK
Bit 7 - INT1 : External Interrupt Request 1 Enable:
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is
enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR)
defines whether the external interrupt is activated on rising or falling edge of the INT1 pin or level sensed. If the INT1
pin for external interrupts shall be activated, the DDD3 bit in the Data Direction Register PORTD (DDRD) must be
cleared (zero) to force an input pin. The corresponding interrupt of External Interrupt Request 1 is executed from
program memory address $002. See also “External Interrupts”.
Bit 6 - INT0 : External Interrupt Request 0 Enable:
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is
activated. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR)
defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. If the INT0
pin for external interrupts shall be activated, the DDD2 bit in the Data Direction Register PORTD (DDRD) must be
cleared (zero) to force an input pin. The corresponding interrupt of External Interrupt Request 0 is executed from
program memory address $001. See also “External Interrupts”.
Bits 5..0 - Res : Reserved bits:
These bits are reserved bits in the AT90S8414 and always read as zero.
4-28
AT90S8414 Preliminary
AT90S8414
THE TIMER/COUNTER INTERRUPT MASK REGISTER - TIMSK
Bit
$39
Read/Write
Initial value
7
TOIE1
R/W
0
6
OCIE1A
R/W
0
5
OCIE1B
R/W
0
4
R
0
3
TICIE1
R/W
0
2
R
0
1
TOIE0
R/W
0
0
OCIE0
R/W
0
TIMSK
Bit 7 - TOIE1 : Timer/Counter1 Overflow Interrupt Enable:
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is
enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs. The
Overflow Flag (Timer/Counter1) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR. When Timer/Counter1
is in PWM mode, the Timer Overflow flag is set when the counter changes counting direction at $0000.
Bit 6 - OCE1A :Timer/Counter1 Output CompareA Match Interrupt Enable:
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match
interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1
occurs. The CompareA Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register - TIFR.
Bit 5 - OCIE1B :Timer/Counter1 Output CompareB Match Interrupt Enable:
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match
interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1
occurs. The CompareB Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register - TIFR.
Bit 4 - Res : Reserved bit:
This bit is a reserved bit in the AT90S8414 and always reads zero.
Bit 3 - TICIE1 : Timer/Counter1 Input Capture Interrupt Enable:
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event
Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin
31, ICP. The Input Capture Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register - TIFR.
Bit 2 - Res : Reserved bit:
This bit is a reserved bit in the AT90S8414 and always reads zero.
Bit 1 - TOIE0 : Timer/Counter0 Overflow Interrupt Enable:
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is
enabled. The corresponding interrupt (at vector $008) is executed if an overflow in Timer/Counter0 occurs. The
Overflow Flag (Timer0) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR.
Bit 0 - OCIE0 :Timer/Counter0 Output Compare Match Interrupt Enable:
When the OCIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match
interrupt is enabled. The corresponding interrupt (at vector $007) is executed if a compare match in Timer/Counter0
occurs. The Compare Flag (Timer0) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR.
THE TIMER/COUNTER INTERRUPT FLAG REGISTER - TIFR
Bit
$38
Read/Write
Initial value
7
TOV1
R/W
0
6
OCF1A
R/W
0
5
OCIFB
R/W
0
4
R
0
3
ICF1
R/W
0
2
R
0
1
TOV0
R/W
0
0
OCF0
R/W
0
TIFR
Preliminary
4-29
Bit 7 - TOV1 : Timer/Counter1 Overflow Flag:
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit
in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1
Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.
Bit 6 - OCF1A : Output Compare Flag 1A:
The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output
Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A
(Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare match
Interrupt is executed.
Bit 5 - OCF1B : Output Compare Flag 1B:
The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output
Compare Register 1B. OCF1 is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, OCF1 is cleared by writing a logic one to the flag.. When the I-bit in SREG, and OCIE1B (Timer/Counter1
Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare match Interrupt is
executed.
Bit 4 - Res : Reserved bit:
This bit is a reserved bit in the AT90S8414 and always reads zero.
Bit 3 - ICF1 : - Input Capture Flag 1:
The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to
the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling
vector. Alternatively, ICF1 is cleared by writing a logic one to the flag.
Bit 2 - Res : Reserved bit:
This bit is a reserved bit in the AT90S8414 and always reads zero.
Bit 1 - TOV0 : Timer/Counter0 Overflow Flag:
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the
SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0
Overflow interrupt is executed.
Bit 0 - OCF0 : Output Compare Flag 0:
The OCF0 bit is set (one) when a compare match occurs between the Timer/Counter0 and the compared data in OCR0 Output Compare Register0. OCF0 is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, OCF0 is cleared by writing a logic one to the flag.. When the SREG I-bit, and OCIE0 (Timer/Counter0
Compare match Interrupt Enable), and OCF0 are set (one), the Timer/Counter0 Compare match Interrupt is executed.
EXTERNAL INTERRUPTS
The external interrupts are triggered by the INT1 and INT0 pins. Since these pins are alternate function pins in the
general I/O ports, the corresponding pins must be set as input pins in the data direction register - DDRX.
The external interrupts are set up as indicated in the specification for the general interrupt mask register - GIMSK.
4-30
AT90S8414 Preliminary
AT90S8414
INTERRUPT RESPONSE TIME
The interrupt response time for all the enabled AVR interrupt is 4 clock cycles. After the 4 clock cycles the program
vector address for the actual interrupt handling routine is executed. During this 4 clock cycle period, the Program Counter
(2 bytes) is pushed onto the Stack, and the Stack Pointer is decremented by 2. A return from an interrupt handling routine
(same as for a subroutine call routine) takes 4 clock cycles. During these 4 clock cycles, the Program Counter (2 bytes) is
popped back from the Stack, and the Stack Pointer is incremented by 2.
Note that the Status Register - SREG - is not handled by the AVR hardware, neither for interrupts nor for subroutines.
For the interrupt handling routines requiring a storage of the SREG, this must be performed by user software.
For Interrupts triggered by events that can remain static (E.g. the Output Compare register0 matching the value of
Timer/Counter0) the interrupt flag is set when the event occurs. If the interrupt flag is cleared and the interrupt condition
persists, the flag will not be set until the event occurs the next time.
MCU CONTROL REGISTER - MCUCR
The MCU Control Register contains control bits for general MCU functions.
Bit
$35
Read/Write
Initial value
7
SRE
R/W
0
6
SRW
R/W
0
5
SE
R/W
0
4
SM
R/W
0
3
ISC11
R/W
0
2
ISC10
R/W
0
1
ISC01
R/W
0
0
ISC00
R/W
0
MCUCR
Bit 7 - SRE : External SRAM Enable:
When the SRE bit is set (one), the external data SRAM is enabled, and the pin functions AD0-7 (Port A), A8-15 (Port C),
WR and RD (Port D) are activated as the alternate pin functions. Then the SRE bit overrides any pin direction settings
in
the
respective
data
direction
registers.
See
“
Preliminary
4-31
The SRAM Data Memory - Internal and External” for description of the External SRAM pin functions. When the SRE
bit is cleared (zero), the external data SRAM is disabled, and the normal pin and data direction settings are used.
Bit 6 - SRW : External SRAM Wait State:
When the SRW bit is set (one), a one cycle wait state is inserted in the external data SRAM access cycle. When the SRW
bit is cleared (zero), the external data SRAM access is executed with the normal two cycle scheme. See Figure 23
External Data SRAM Memory Cycles without Wait State and Figure 24: External Data SRAM Memory Cycles with
Wait State.
Bit 5 - SE : Sleep Enable:
The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid
the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit
just before the execution of the SLEEP instruction.
Bit 4 - SM : Sleep Mode:
This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode.
When SM is set (one), Power Down mode is selected as sleep mode. For details, refer to the paragraph “Sleep Modes”
below.
Bit 3, 2 - ISC11, ISC10 : Interrupt Sense Control 1 bit 1 and bit 0:
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask in
the GIMSK is set. The level and edges on the external INT1 pin that activate the interrupt are defined in the following
table:
Table 4: Interrupt 1 Sense Control
ISC11
0
0
1
1
ISC10
0
1
0
1
Description
The low level of INT1 generates an interrupt request.
Reserved
The falling edge of INT1 generates an interrupt request.
The rising edge of INT1 generates an interrupt request.
Note: When changing the ISC11/ISC10 bits, INT1 must be disabled by clearing its Interrupt Enable bit in the GIMSK
Register. Otherwise an interrupt can occur when the bits are changed.
Bit 1, 0 - ISC01, ISC00 : Interrupt Sense Control 0 bit 1 and bit 0:
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask is
set. The level and edges on the external INT0 pin that activate the interrupt are defined in the following table:
Table 5: Interrupt 0 Sense Control
ISC01
0
0
1
1
ISC00
0
1
0
1
Description
The low level of INT0 generates an interrupt request.
Reserved
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
Note: When changing the ISC10/ISC00 bits, INT0 must be disabled by clearing its Interrupt Enable bit in the GIMSK
Register. Otherwise an interrupt can occur when the bits are changed.
Sleep Modes
To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. If an
enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the instruction following SLEEP,
4-32
AT90S8414 Preliminary
AT90S8414
enters the interrupt routine and resumes execution from the address following the last executed instruction. To avoid
entering the Interrupt Routine, let a CLI - Disable Global Interrupts follow the SLEEP instruction. If reset occurs while
the MCU is in Sleep Mode, the MCU awakes and executes from the reset vector. The contents of the register file and the
I/O memory are unaltered in both modes.
Note that if a level triggered interrupt is used for wake-up, the low level must be held for a time longer than the oscillator
start-up time of 16 ms. Otherwise, the interrupt flag may return to zero before the MCU starts executing.
IDLE MODE
When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle Mode stopping the CPU but
allowing Timer/Counters, Watchdog and the interrupt system to continue operating. This enables the MCU to wake up
from external triggered interrupts as well as internal ones like Timer Overflow interrupt and watchdog reset. If wakeup
from the Analog Comparator interrupt is not required, the analog comparator can be powered down by setting the ACDbit in the Analog Comparator Control and Status register - ACSR. This will reduce power consumption during Idle
Mode.
POWER DOWN MODE
When the SM bit is set (one), the SLEEP instruction forces the MCU into the Power Down Mode. In this mode, the
oscillator is stopped. The user can select whether the watchdog shall be enabled during power-down mode. If the
watchdog is enabled, it will wake up the MCU when the Watchdog Time-out period expires. If the watchdog is disabled,
only an external reset or an external interrupt can wake up the MCU.
Timer / Counters
The AT90S8414 provides two general purpose Timer/Counters - one 8-bit T/C and one 16-bit T/C. The Timer/Counters
have separate prescaling selection from the same 10-bit prescaling timer. Both Timer/Counters can either be used as a
timer with an internal clock timebase or as a counter with an external pin connection which triggers the counting.
The Timer/Counter Prescaler
Figure 31 shows the general Timer/Counter prescaler.
Figure 31: Timer/Counter Prescaler
Preliminary
4-33
The four different prescaled selections are: CK/8, CK/64, CK/256 and CK/1024 where CK is the oscillator clock. For the
two Timer/Counters, added selections as CK, external source and stop, can be selected as clock sources.
The 8-Bit Timer/Counter0
Figure 32 shows the block diagram for Timer/Counter0.
The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be
stopped as described in the specification for the Timer/Counter0 Control Register - TCCR0. The different status flags
(overflow and compare match) and control signals are found in the Timer/Counter0 Control Register - TCCR0. The
interrupt enable/disable settings for Timer/Counter0 are found in the Timer/Counter Interrupt Mask Register - TIMSK.
When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU.
To assure proper sampling of the external clock, the minimum time for the external clock being low and high must be at
least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock.
The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling
opportunities. Similarly, the high prescaling opportunities make the Timer/Counter0 useful for lower speed functions or
exact timing functions with infrequent actions.
Figure 32: Timer/Counter0 Block Diagram
The Timer/Counter0 supports an Output Compare function using the Output Compare Register 0 - OCR0 as the data
source to be compared to the Timer/Counter0 contents. The Output Compare functions include optional clearing of the
counter on compare matches, and actions on the Output Compare pin 0 on compare matches. The Output Compare pin 0
function makes the Timer/Counter0 useful for PWM (Pulse Width Modulation) functions.
4-34
AT90S8414 Preliminary
AT90S8414
THE TIMER/COUNTER0 CONTROL REGISTER - TCCR0
Bit
$33
Read/Write
Initial value
7
R
0
6
R
0
5
COM01
R/W
0
4
COM00
R/W
0
3
CTC0
R/W
0
2
CS02
R/W
0
1
CS01
R/W
0
0
CS00
R/W
0
TCCR0
Bits 7,6 - Res : Reserved bits:
These bits are reserved bits in the AT90S8414 and always read zero.
Bits 5,4 - COM01, COM00 : Compare Output Mode0, bit 1 and 0:
The COM01 and COM00 control bits determine any output pin action following a compare match in Timer/Counter0.
Any output pin actions are effective on pin OC0 - Output Compare pin 0. Since this is an alternative function to an I/O
port, the corresponding data direction control bit must be set (one) to control an output pin. The control configuration is
defined in the following table:
Table 6: Compare 0 Mode Select
COM01
0
0
1
1
COM00
0
1
0
1
Description
Timer/Counter0 disconnected from output pin OC0.
Toggle the OC0 output line.
Clear the OC0 output line (to zero).
Set the OC0 output line (to one).
Note: When changing the COM01/COM00 bits, Output Compare Interrupt 0 must be disabled by clearing its Interrupt
Enable bit in the TIMSK Register. Otherwise an interrupt can occur when the bits are changed.
Bit 3 - CTC0 : Clear Timer/Counter0 on Compare match:
When the CTC0 control bit is set (one), the Timer/Counter0 is reset to $00 in the clock cycle after the compare match. If
the CTC0 control bit is cleared, the Timer/Counter0 continues running freely until it is stopped, set, cleared or wraps
around (overflow).
Bits 2,1,0 - CS02, CS01, CS00 : Clock Select0, bit 2,1 and 0:
The Clock Select0 bits 2,1 and 0 define the prescaling source of Timer0.
Table 7: Clock 0 Prescale Select
CS02
0
0
0
0
1
1
1
1
CS01
0
0
1
1
0
0
1
1
CS00
0
1
0
1
0
1
0
1
Description
Stop, the Timer/Counter0 is stopped.
CK
CK / 8
CK / 64
CK / 256
CK / 1024
External Pin T0, rising edge
External Pin T0, falling edge
The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the
CK oscillator clock. If the external pin modes are used, the corresponding setup must be performed in the actual data
direction control register (cleared to zero gives an input pin).
Bits 5..3 - Res : Reserved bits:
Preliminary
4-35
These bits are reserved bits in the AT90S8414 and always read zero.
THE TIMER COUNTER 0 - TCNT0
Bit
$32
Read/Write
Initial value
7
MSB
R/W
0
6
5
4
3
2
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
LSB
R/W
0
TCNT0
The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock
source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation.
THE OUTPUT COMPARE REGISTER 0 - OCR0
Bit
$31
Read/Write
Initial value
7
MSB
R/W
0
6
5
4
3
2
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
LSB
R/W
0
OCR0
The Output Compare Register 0 is the source register for the Timer/Counter0 compare match functions.
The 16-Bit Timer/Counter1
Figure 33 shows the block diagram for Timer/Counter1.
4-36
AT90S8414 Preliminary
AT90S8414
Figure 33: Timer/Counter1 Block Diagram
The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK, or an external pin. In addition it can be
stopped as described in the specification for the Timer/Counter1 Control Register - TCCR1B. The different status flags
(overflow, compare match and capture event) and control signals are found in the Timer/Counter1 Control Registers TCCR1A and TCCR1B. The interrupt enable/disable settings for Timer/Counter1 are found in the Timer/Counter
Interrupt Mask Register - TIMSK.
When Timer/Counter1 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU.
To assure proper sampling of the external clock, the minimum time for the external clock being low and high must be at
least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock.
The 16-bit Timer/Counter1 features both a high resolution and a high accuracy usage with the lower prescaling
opportunities. Similarly, the high prescaling opportunities makes the Timer/Counter1 useful for lower speed functions or
exact timing functions with infrequent actions.
The Timer/Counter1 supports two Output Compare functions using the Output Compare Register 1 A and B - OCR1A
and OCR1B as the data sources to be compared to the Timer/Counter1 contents. The Output Compare functions include
optional clearing of the counter on compareA match, and actions on the Output Compare pins on both compare matches.
Preliminary
4-37
Timer/Counter1 can also be used as a 10 bit Pulse With Modulator. In this mode the counter and the OCR1A/OCR1B
registers serve as a dual glitch-free stand-alone PWM with centered pulses. Refer to Page 4-42 for a detailed description
on this function.
The Input Capture function of Timer/Counter1 provides a capture of the Timer/Counter1 contents to the Input Capture
Register - ICR1, triggered by an external event on the Input Capture Pin - ICP. The actual capture event settings are
defined by the Timer/Counter1 Control Register - TCCR1B. In addition, the Analog Comparator can be set to trigger the
Input Capture. Refer to the paragraph, “The Analog Comparator”, for details on this. The ICP pin logic is shown in
Figure 34.
Figure 34: ICP Pin Schematic Diagram
The Timer/Counter1 input capture noise canceler block diagram is shown in Figure 35.
Figure 35: The Input Capture Noise Canceler
If the noise canceler function is enabled, the actual trigger condition for the capture event is monitored over 4 samples
before the capture is activated. The sampling clock is the same clock as the clock source selected for the Timer/Counter1.
4-38
AT90S8414 Preliminary
AT90S8414
THE TIMER/COUNTER1 CONTROL REGISTER A - TCCR1A
Bit
$2F
Read/Write
Initial value
7
COM1A1
R/W
0
6
COM1A0
R/W
0
5
COM1B1
R/W
0
4
COM1B0
R/W
0
3
R
0
2
R
0
1
R
0
0
PWM1
R/W
0
TCCR1A
Bits 7,6 - COM1A1, COM1A0 : Compare Output Mode1A, bits 1 and 0:
The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1.
Any output pin actions affect pin OC1A - Output CompareA pin 1. Since this is an alternative function to an I/O port, the
corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in
Table 8.
Bits 5,4 - COM1B1, COM1B0 : Compare Output Mode1B, bits 1 and 0:
The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1.
Any output pin actions affect pin OC1B - Output CompareB. Since this is an alternative function to an I/O port, the
corresponding direction control bit must be set (one) to control an output pin. The following control configuration is
given:
Table 8: Compare 1 Mode Select
COM1X1
0
0
1
1
Notes:
COM1X0
0
1
0
1
Description
Timer/Counter1 disconnected from output pin OC1X
Toggle the OC1X output line.
Clear the OC1X output line (to zero).
Set the OC1X output line (to one).
X = A or B
In PWM mode, these bits have a different function. Refer to Table 10 for a detailed description.
When changing the COM1X1/COM1X0 bits, Output Compare Interrupts 1 must be disabled by clearing their
Interrupt Enable bits in the TIMSK Register. Otherwise an interrupt can occur when the bits are changed.
Bits 3..1 - Res : Reserved bits:
These bits are reserved bits in the AT90S8414 and always read zero.
Bit 0 - PWM1 : Pulse Width Modulator enable:
This bit enables the PWM mode for Timer/Counter1. This mode is described on Page 4-42.
THE TIMER/COUNTER1 CONTROL REGISTER B - TCCR1B
Bit
$2E
Read/Write
Initial value
7
ICNC1
R/W
0
6
ICES1
R/W
0
5
R
0
4
R
0
3
CTC1
R/w
0
2
CS12
R/W
0
1
CS11
R/W
0
0
CS10
R/W
0
TCCR1B
Bit 7 - ICNC1 : Input Capture1 Noise Canceler (4 CKs):
When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is
triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set
(one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according
to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is the same as the clock source
frequency selected for the Timer/Counter1.
Bit 6 - ICES1 : Input Capture1 Edge Select:
Preliminary
4-39
While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are
transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.
Bits 5, 4 - Res : Reserved bits:
These bits are reserved bits in the AT90S8414 and always read zero.
Bit 3 - CTC1 : Clear Timer/Counter1 on Compare match:
When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match.
If the CTC1 control bit is cleared, the Timer/Counter1 continues counting until it is stopped, cleared, wraps around
(overflow) or changes direction. In PWM mode, this bit has no effect.
Bits 2,1,0 - CS12, CS11, CS10 : Clock Select1, bit 2,1 and 0:
The Clock Select1 bits 2,1 and 0 define the prescaling source of Timer/Counter1.
Table 9: Clock 1 Prescale Select
CS12
0
0
0
0
1
1
1
1
CS11
0
0
1
1
0
0
1
1
CS10
0
1
0
1
0
1
0
1
Description
Stop, the Timer/Counter1 is stopped.
CK
CK / 8
CK / 64
CK / 256
CK / 1024
External Pin T1, rising edge
External Pin T1, falling edge
The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the
CK oscillator clock. If the external pin modes are used, the corresponding setup must be performed in the actual direction
control register (cleared to zero gives an input pin).
THE TIMER/COUNTER1 - TCNT1H AND TCNT1L
Bit
$2D
$2C
15
MSB
Read/Write
Initial value
7
R/W
R/W
0
0
14
6
R/W
R/W
0
0
13
5
R/W
R/W
0
0
12
4
R/W
R/W
0
0
11
3
R/W
R/W
0
0
10
2
R/W
R/W
0
0
9
8
1
R/W
R/W
0
0
LSB
0
R/W
R/W
0
0
TCNT1H
TCNT1L
This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes
are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary register (TEMP).
· TCNT1 Timer/Counter1 Write:
When the CPU writes to the low byte TCNT1L, the written data is placed in the TEMP register. Next, when the CPU
writes the high byte TCNT1H, this byte of data is combined with the byte data in the TEMP register, and all 16 bits
are written in the TCNT1 Timer/Counter1 register simultaneously. Consequently, the low byte TCNT1L must be
accessed first for a full 16-bit register write operation.
· TCNT1 Timer/Counter1 Read:
4-40
AT90S8414 Preliminary
AT90S8414
When the CPU reads the low byte TCNT1L, the data of the low byte TCNT1L is sent to the CPU and the data of the
high byte TCNT1H is placed in the TEMP register. When the CPU reads the data in the high byte TCNT1H, the CPU
receives the data in the TEMP register. Consequently, the low byte TCNT1L must be accessed first for a full 16-bit
register read operation.
The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write access. If
Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 continues counting in the clock cycle
after it is preset with the written value.
TIMER/COUNTER1 OUTPUT COMPARE REGISTER - OCR1AH AND OCR1AL
Bit
$2B
$2A
Read/Write
Initial value
15
MSB
7
R/W
R/W
0
0
14
6
R/W
R/W
0
0
13
5
R/W
R/W
0
0
12
4
R/W
R/W
0
0
11
3
R/W
R/W
0
0
10
2
R/W
R/W
0
0
9
8
1
R/W
R/W
0
0
LSB
0
R/W
R/W
0
0
OCR1AH
OCR1AL
TIMER/COUNTER1 OUTPUT COMPARE REGISTER - OCR1BH AND OCR1BL
Bit
$29
$28
Read/Write
Initial value
15
MSB
14
7
R/W
R/W
0
0
6
R/W
R/W
0
0
13
5
R/W
R/W
0
0
12
4
R/W
R/W
0
0
11
3
R/W
R/W
0
0
10
2
R/W
R/W
0
0
9
1
R/W
R/W
0
0
8
LSB
0
R/W
R/W
0
0
OCR1BH
OCR1BL
The output compare registers are 16-bit read/write registers.
The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1.
Actions on compare matches are specified in the Timer/Counter1 Control and Status register.
Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used
when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the low byte,
OCR1AL or OCR1BL, the data is temporarily stored in the TEMP register. When the CPU writes the high byte,
OCR1AH or OCR1BH, the TEMP register is simultaneously written to OCR1AL or OCR1BL. Consequently, the low
byte OCR1AL or OCR1BL must be written first for a full 16-bit register write operation.
Preliminary
4-41
THE TIMER/COUNTER1 INPUT CAPTURE REGISTER - ICR1H AND ICR1L
Bit
$25
$24
15
MSB
Read/Write
Initial value
7
R
R
0
0
14
6
R
R
0
0
13
5
R
R
0
0
12
4
R
R
0
0
11
3
R
R
0
0
10
2
R
R
0
0
9
8
1
R
R
0
0
LSB
0
R
R
0
0
ICR1H
ICR1L
The input capture register is a 16-bit read-only register.
When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin
- ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the
same time, the input capture flag - ICF1 - is set (one).
Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to
ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and
the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H,
the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16bit register read operation.
TIMER/COUNTER1 IN PWM MODE
When the PWM mode is selected, Timer/Counter1 and the Output Compare Register1A - OCR1A and the Output
Compare Register1B - OCR1B, form a dual 10-bit, free-running, glitch-free and phase correct PWM with outputs on the
PD5(OC1A) and OC1B pins. Timer/Counter1 acts as an up/down counter, counting up from $0000 to $03FF (i.e. from 0
to 1023), when it turns and counts down again to zero before the cycle is repeated. When the counter value matches the
contents of the 10 least significant bits of OCR1A or OCR1B, the PD5(OC1A)/OC1B pins are set or cleared according to
the settings of the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1 Control Register TCCR1A.
Refer to Table 10 for details.
Table 10: Compare1 Mode Select in PWM Mode
COM1X1
0
0
1
COM1X0
0
1
0
1
1
Effect on OCX1
Not connected
Not connected
Cleared on compare match, upcounting. Set on compare match, downcounting (noninverted PWM).
Cleared on compare match, downcounting. Set on compare match, upcounting (inverted
PWM).
Note: X = A or B
Note that in the PWM mode, the 10 least significant OCR1A/OCR1B bits, when written, are transferred to a temporary
location. They are latched when Timer/Counter1 reaches the top - $03FF. This prevents the occurrence of odd-length
PWM pulses (glitches) in the event of an unsynchronized OCR1A/OCR1B write. See Figure 36 for an example.
4-42
AT90S8414 Preliminary
AT90S8414
Figure 36: Effects on Unsynchronized OCR1 Latching
When OCR1 contains $0000 or $03FF, the output OC1A/OC1B is held low or high according to the settings of
COM1A1/COM1A0 or COM1B1/COM1B0. This is shown in Table 11:
Table 11: PWM Outputs OCR1X = $0000 or $03FF
COM1X1
1
1
1
1
Note:
COM1X
0
0
0
1
1
OCR1X
Output OC1X
$0000
$03FF
$0000
$03FF
L
H
H
L
X = A or B
In PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter changes direction at $0000. Timer Overflow
Interrupt1 operates exactly as in normal Timer/Counter mode, i.e. it is executed when TOV1 is set provided that Timer
Overflow Interrupt1 and global interrupts are enabled. This does also apply to the Timer Output Compare1 flags and
interrupts.
f
The PWM output frequency is given by: fPWM = TC1 , where fTC1 is the Timer/Counter1 Clock Source frequency.
2046
The Watchdog Timer
The Watchdog Timer is clocked from a separate on-chip oscillator which runs at 1MHz. By controlling the Watchdog
Timer prescaler, the Watchdog reset interval can be adjusted from 16 to 2048 ms. The WDR - Watchdog Reset instruction resets the Watchdog Timer. From the Watchdog is reset, eight different clock cycle periods can be selected to
determine the reset period. If the reset period expires without another Watchdog reset, the AT90S8414 resets and
executes from the reset vector. For timing details on the Watchdog reset, refer to Page 2-27.
Preliminary
4-43
Figure 37: Watchdog Timer
THE WATCHDOG TIMER CONTROL REGISTER - WDTCR
Bit
$21
Read/Write
Initial value
7
R
0
6
R
0
5
R
0
4
R
0
3
WDE
R/W
0
2
WDP2
R/W
0
1
WDP1
R/W
0
0
WDP0
R/W
0
WDTCR
Bits 7..4 - Res : Reserved bits:
These bits are reserved bits in the AT90S8414 and will always read as zero.
Bit 3 - WDE : Watch Dog Enable:
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer
function is disabled.
Bits 2..0 - WDP2, WDP1, WDP0 : Watch Dog Timer Prescaler 2, 1 and 0:
The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The
different prescaling values and their corresponding Timeout Periods are shown in Table 12.
Table 12: Watch Dog Timer Prescale Select
WDP2
0
0
0
0
1
1
1
1
WDP1
0
0
1
1
0
0
1
1
WDP0
0
1
0
1
0
1
0
1
Timeout Period
16 ms
32 ms
64 ms
128 ms
256 ms
512 ms
1024 ms
2048 ms
EEPROM Read/Write Access
The EEPROM access registers are accessible in the I/O space using the IN and OUT instructions.
4-44
AT90S8414 Preliminary
AT90S8414
The write access time is in the range of 2.5 - 4ms, depending on the Vcc voltages. A self-timing function, however, lets
the user software detect when the next byte can be written.
The read access time is the same as for the Flash memory and is of no concern to the user software.
THE EEPROM ADDRESS REGISTER - EEAR
Bit
$1E
Read/Write
Initial value
7
MSB
R/W
0
6
5
4
3
2
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
LSB
R/W
0
EEAR
Bits 7..0 - EEAR7..0 : EEPROM Address:
The EEPROM Address Register - EEAR7..0 - specifies the EEPROM address in the 256 bytes EEPROM space. The
EEPROM data bytes are addressed linearly between 0 and 255.
THE EEPROM DATA REGISTER - EEDR
Bit
$1D
Read/Write
Initial value
7
MSB
R/W
0
6
5
4
3
2
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
LSB
R/W
0
EEDR
Bits 7..0 - EEDR7..0 : EEPROM Data:
For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given
by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the
address given by EEAR.
THE EEPROM CONTROL REGISTER - EECR
Bit
$1C
Read/Write
Initial value
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
EEWE
R/W
0
0
EERE
R/W
0
EECR
Bits 7..2 - Res : Reserved bits:
These bits are reserved bits in the AT90S8414 and will always be read as zero.
Bit 1 - EEWE : EEPROM Write Enable:
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set
up, the EEWE bit must be set to write the value into the EEPROM. When the write access time (typically 2.5ms at
Vcc=5V or 4ms at Vcc=2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this
bit and wait for a zero before writing the next byte.
Bit 0 - EERE : EEPROM Read Enable:
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the
EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in
the EEDR register. The EEPROM read access time is within a single clock cycle and there is no need to poll the EERE
bit.
Preliminary
4-45
The Serial Peripheral Interface - SPI
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90S8414 and
peripheral devices or between several AT90S8414 devices. The AT90S8414 SPI features include the following:
·
·
·
·
·
·
·
·
Full-Duplex, 3-Wire Synchronous Data Transfer
Master or Slave Operation
5 Mbit/s Bit Frequency (max.)
LSB First or MSB First Data Transfer
Four Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wakeup from Idle Mode (Slave Mode Only)
Figure 38: SPI Block Diagram
The interconnection between master and slave CPUs with SPI is shown in Figure 39. The PB7(SCK) pin is the clock
output in the master mode and is the clock input in the slave mode. Writing to the SPI data register of the master CPU
starts the SPI clock generator, and the data written shifts out of the PB5(MOSI) pin and into the PB5(MOSI) pin of the
slave CPU. After shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF). If the SPI
interrupt enable bit (SPIE) in the SPCR register is set, an interrupt is requested. The Slave Select input, PB4( SS ), is set
4-46
AT90S8414 Preliminary
AT90S8414
low to select an individual SPI device as a slave. When PB4( SS ) is set high, the SPI port is deactivated and the
PB6(MOSI) pin can be used as an input. Slave/Master mode can also be selected in software by clearing or setting the
MSTR bit in the SPI Control Register.
The two shift registers in the Master and the Slave can be considered as one distributed 16-bit circular shift register. This
is shown in Figure 39. When data is shifted from the master to the slave, data is also shifted in the opposite direction,
simultaneously. This means that during one shift cycle, data in the master and the slave are interchanged.
Figure 39: SPI Master-Slave Interconnection
The system is single buffered in the transmit direction and double buffered in the receive direction. This means that
characters to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When
receiving data, however, a received character must be read from the SPI Data Register before the next character has been
completely shifted in. Otherwise, the first character is lost.
When the SPI is enabled, the DDB5-DDB7 bits in Data Direction Register B (DDRB) are overridden and have no effect.
For the PB4( SS ) pin, however, DDB4 is assigned the following functionality when the SPI is enabled.
· When DDB4 is cleared (zero) another SPI device can act as master by setting SS low. As long as SS is held high, the
MSTR bit in SPCR selects Master/Slave. If SS is set low, MSTR will be forced low.
· When DDB4 is set (one), the PB4( SS ) pin can be used as a general output. The MSTR bit selects Master/Slave.
There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits
CPHA and CPOL. The SPI data transfer formats are shown in Figure 40 and Figure 41.
Preliminary
4-47
Figure 40: SPI Transfer Format with CHPA = 0
Figure 41: SPI Transfer Format with CHPA = 1
THE SPI CONTROL REGISTER - SPCR
Bit
$0D
Read/Write
Initial value
7
SPIE
R/W
0
6
SPE
R/W
0
5
DORD
R/W
0
4
MSTR
R/W
0
3
CPOL
R/W
0
2
CPHA
R/W
1
1
SPR1
R/W
0
0
SPR0
R/W
0
SPCR
Bit 7 - SPIE : SPI Interrupt Enable:
This bit causes setting of the SPIF bit in the SPSR register to execute the SPI interrupt provided that global interrupts are
enabled.
Bit 6 - SPE : SPI Enable:
When the SPE bit is set (one), the SPI is enabled and SS , MOSI, MISO and SCK are connected to pins PB4, PB5, PB6
and PB7.
Bit 5 - DORD : Data ORDer:
When the DORD bit is set (one), the LSB of the data word is transmitted first.
When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.
4-48
AT90S8414 Preliminary
AT90S8414
Bit 4 - MSTR : Master/Slave Select:
This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS on Device1 is set low
by Device2 while MSTR is set in Device1, MSTR will be forced low and Device1 will be a slave.
Bit 3 - CPOL : Clock POLarity:
When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure
40 and Figure 41 for additional information.
Bit 2 - CPHA : Clock PHAse:
Refer to Figure 40 or Figure 41 for the functionality of this bit.
Bits 1,0 - SPR1, SPR0 : SPI Clock Rate Select 1 and 0:
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR2 have no effect on the slave.
The relationship between SCK and the Oscillator Clock frequency fcl is shown in the following table:
Table 13: Relationship Between SCK and the Oscillator Frequency
SPR1
0
SPR0
0
SCK Frequency
fcl/4
0
1
fcl/16
1
0
fcl/64
1
1
fcl/128
THE SPI STATUS REGISTER - SPSR
Bit
$0E
Read/Write
Initial value
7
SPIF
R
0
6
WCOL
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
R
0
SPSR
Bit 7 - SPIF : SPI Interrupt Flag:
When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and
global interrupts are enabled. SPIF is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, the SPIF bit is cleared by first reading the SPI status register with SPIF set (one), then accessing the SPI
Data Register (SPDR).
Bit 6 - WCOL : Write COLlision flag:
The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. During data transfer, the result of
reading the SPDR register may be incorrect, and writing to it will have no effect. The WCOL bit (and the SPIF bit) are
cleared (zero) by first reading the SPI Status Register with WCOL set (one), and then accessing the SPI Data Register.
Bit 5..0 - Res : Reserved bits:
These bits are reserved bits in the AT90S8414 and will always read as zero.
The SPI interface on the AT90S8414 is also used for program memory and EEPROM downloading or uploading. See
Page 4-75 for serial programming and reading.
Preliminary
4-49
THE SPI DATA REGISTER - SPDR
Bit
$0F
Read/Write
Initial value
7
MSB
R/W
0
6
5
4
3
2
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
LSB
R/W
0
SPDR
The SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register.
Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
The UART
The AT90S8414 features a full duplex Universal Asynchronous Receiver and Transmitter (UART). The main features
are:
·
·
·
·
·
·
·
·
Baud rate generator generates any baud rate
High baud rates at low XTAL frequencies
8 or 9 bits data
Noise filtering
Overrun detection
Framing Error detection
False Start Bit detection
Three separate interrupts on TX Complete, TX Data Register Empty and RX Complete
Data Transmission
A block schematic of the UART transmitter is shown in Figure 42.
4-50
AT90S8414 Preliminary
AT90S8414
Figure 42: UART Transmitter
Data transmission is initiated by writing the data to be transmitted to the UART I/O Data Register, UDR. Data is
transferred from UDR to the Transmit shift register when:
·
·
A new character has been written to UDR after the stop bit from the previous character has been shifted out. The
shift register is loaded immediately.
A new character has been written to UDR before the stop bit from the previous character has been shifted out. The
shift register is loaded when the stop bit of the character currently being transmitted has been shifted out.
If the 10(11)-bit Transmitter shift register is empty or when, data is transferred from UDR to the shift register. At this
time the UDRE (UART Data Register Empty) bit in the UART Status Register, USR, is set. When this bit is set (one), the
UART is ready to receive the next character. At the same time as the data is transferred from UDR to the 10(11)-bit shift
register, bit 0 of the shift register is cleared (start bit) and bit 9 or 10 is set (stop bit). If 9 bit data word is selected (the
CHR9 bit in the UART Control Register, UCR is set), the TXB8 bit in UCR is transferred to bit 9 in the Transmit shift
register.
On the Baud Rate clock following the transfer operation to the shift register, the start bit is shifted out on the TXD pin.
Then follows the data, LSB first. When the stop bit has been shifted out, the shift register is loaded if any new data has
been written to the UDR during the transmission. During loading, UDRE is set. If there is no new data in the UDR
register to send when the stop bit is shifted out, the UDRE flag will remain set. In this case, after the stop bit has been
present on TXD for one bit length, the TX Complete Flag, TXC, in USR is set.
Preliminary
4-51
The TXEN bit in UCR enables the UART transmitter when set (one). By clearing this bit (zero), the PD1 pin can be used
for general I/O. When TXEN is set, the UART Transmitter will be connected to the PD1 pin regardless of the setting of
the DDD1 bit in DDRB.
Data Reception
Figure 43 shows a block diagram of the UART Receiver
Figure 43: UART Receiver
The receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud rate. While the line is
idle, one single sample of logical zero will be interpreted as the falling edge of a start bit, and the start bit detection
sequence is initiated. Let sample 1 denote the first zero-sample. Following the 1 to 0-transition, the receiver samples the
RXD pin at sample 8, 9 and 10. If two or more of these three samples are found to be logical ones, the start bit is rejected
as a noise spike and the receiver starts looking for the next 1 to 0-transition.
If however, a valid start bit is detected, sampling of the data bits following the start bit is performed. These bits are also
sampled at samples 8, 9 and 10. The logical value found in at least two of the three samples is taken as the bit value. All
bits are shifted into the transmitter shift register as they are sampled. Sampling of an incoming character is shown in
Figure 44.
4-52
AT90S8414 Preliminary
AT90S8414
Figure 44: Sampling Received Data
When the stop bit enters the receiver, the majority of the three samples must be one to accept the stop bit. If two or more
samples are logical zeros, the Framing Error (FE) flag in the UART Status Register (USR) is set. Before reading the
UDR register, the user should always check the FE bit to detect Framing Errors.
Whether or not a valid stop bit is detected at the end of a character reception cycle, the data is transferred to UDR and the
RXC flag in USR is set. UDR is in fact two physically separate registers, one for transmitted data and one for received
data. When UDR is read, the Receive Data register is accessed, and when UDR is written, the Transmit Data register is
accessed. If 9 bit data word is selected (the CHR9 bit in the UART Control Register, UCR is set), the RXB8 bit in UCR
is loaded with bit 9 in the Transmit shift register when data is transferred to UDR.
If, after having received a character, the UDR register has not been accessed since the last receive, the OverRun (OR)
flag in UCR is set. This means that the new data transferred to the shift register has overwritten the old data not yet read,
and the old data is lost. The user should always check the OR bit before reading from the UDR register in order to detect
any overruns.
By clearing the RXEN bit in the UCR register, the receiver is disabled. This means that the PD0 pin can be used as a
general I/O pin. When RXEN is set, the UART Receiver will be connected to the PD0 pin regardless of the setting of the
DDD0 bit in DDRB.
UART Control
THE UART I/O DATA REGISTER - UDR
Bit
$0C
Read/Write
Initial value
7
MSB
R/W
0
6
5
4
3
2
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
LSB
R/W
0
UDR
The UDR register is actually two physically separate registers sharing the same I/O address. When writing to the register,
the UART Transmit Data register is written. When reading from UDR, the UART Receive Data register is read.
THE UART STATUS REGISTER - USR
Bit
$0B
Read/Write
Initial value
7
RXC
R
0
6
TXC
R
1
5
UDRE
R
1
4
FE
R
0
3
OR
R
0
2
R
0
1
R
0
0
R
0
USR
The USR register is a read-only register providing information on the UART Status.
Bit 7 - RXC: UART Receive Complete:
This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR. The bit is set
regardless of any detected framing errors. When the RXCIE bit in UCR is set, setting of RXC causes the UART Receive
Complete interrupt to be executed. RXC is cleared by hardware when executing the corresponding interrupt handling
vector. Alternatively, the bit is cleared (zero) by first reading USR while RXC is set (one) and then reading UDR.
Bit 6 - TXC : UART Transmit Complete:
This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out
and no new data has been written to the UDR. This flag is especially useful in half-duplex communications interfaces,
Preliminary
4-53
where a transmitting application must enter receive mode and free the communications bus immediately after completing
the transmission.
When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete interrupt to be executed. TXC
is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared
(zero) by first reading USR while TXC is set and then writing UDR.
This bit is set (one) during reset to indicate that the transmitter is not busy transmitting anything.
Bit 5 - UDRE : UART Data Register Empty:
This bit is set (one) when a character written to UDR is transferred to the Transmit shift register. Setting of this bit
indicates that the transmitter is ready to receive a new character for transmission.
When the UDRIE bit in UCR is set, setting of UDRE causes the UART Transmit Complete interrupt to be executed.
UDRE is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the UDRE bit
is cleared (zero) by first reading USR while UDRE is set and then writing UDR.
UDRE is set (one) during reset to indicate that the transmitter is ready.
Bit 4 - FE : Framing Error:
This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero.
The FE bit is cleared (zero) by first reading USR while FE is set and then reading UDR.
Bit 3 - OR : OverRun:
This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDR register is not read
before the next character is transferred from the Receiver Shift register.
The OR bit is cleared (zero) by first reading USR while OR is set and then reading UDR.
Bits 2..0 - Res : Reserved bits:
These bits are reserved bits in the AT90S8414 and will always read as zero.
THE UART CONTROL REGISTER - UCR
Bit
$0A
Read/Write
Initial value
7
RXCIE
R/W
0
6
TXCIE
R/W
0
5
UDRIE
R/W
0
4
RXEN
R/W
0
3
TXEN
R/W
0
2
CHR9
R/W
0
1
RXB8
R
0
0
TXB8
W
0
UCR
Bit 7 - RXCIE : RX Complete Interrupt Enable:
When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Complete interrupt routine to be
executed provided that global interrupts are enabled.
Bit 6 - TXCIE : TX Complete Interrupt Enable:
When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Complete interrupt routine to be
executed provided that global interrupts are enabled.
4-54
AT90S8414 Preliminary
AT90S8414
Bit 5 - UDRIE : UART Data Register Empty Interrupt Enable:
When this bit is set (one), a setting of the UDRE bit in USR will cause the UART Data Register Empty interrupt routine
to be executed provided that global interrupts are enabled.
Bit 4 - RXEN : Receiver Enable:
This bit enables the UART receiver when set (one). When the receiver is disabled, the TXC, OR and FE status flags
cannot become set. If these flags are set, turning off RXEN does not cause them to be cleared.
Bit 3 - TXEN : Transmitter Enable:
This bit enables the UART transmitter when set (one). When disabling the transmitter while transmitting a character, the
transmitter is not disabled before the character in the shift register plus any following character in UDR has been
completely transmitted.
Bit 2 - CHR9 : 9 Bit Characters:When this bit is set (one) transmitted and received characters are 9 bit long plus start
th
th
and stop bits. The 9 bit is read and written by using the RXB8 and TXB8 bits in UCR, respectively. The 9 data bit can
be used as an extra stop bit or a parity bit.
Bit 1 - RXB8 : Receive Data Bit 8
th
When CHR9 is set (one), RXB8 is the 9 data bit of the received character.
Bit 0 - TXB8 : Transmit Data Bit 8
th
When CHR9 is set (one), TXB8 is the 9 data bit in the character to be transmitted.
THE BAUD RATE GENERATOR
The baud rate generator is a frequency divider which generates baud-rates according to the following equation:
BAUD =
· BAUD
· fck
· UBRR
fck
16(UBRR + 1)
= Baud-Rate
= Crystal Clock frequency
= Contents of the UART Baud Rate register, UBRR (0-255)
For standard crystal frequencies, the most commonly used baud rates can be generated by using the UBRR settings in
Table 14. UBRR values which yield an actual baud rate differing less than 2% from the target baud rate, are bolded in the
table.
Preliminary
4-55
Table 14: UBRR Settings at Various Crystal Frequencies
Baud Rate
2400
4800
9600
14400
19200
28800
57600
115200
1 MHz %Error 1.8432 MHz %Error
2 MHz %Error 2.4576 MHz %Error
25
0.2 UBRR=
47
0.0 UBRR=
51
0.2 UBRR=
63
0.0
UBRR=
12
0.2 UBRR=
23
0.0 UBRR=
25
0.2 UBRR=
31
0.0
UBRR=
11
0.0 UBRR=
12
0.2 UBRR=
15
0.0
UBRR=
6
7.5 UBRR=
7
0.0 UBRR=
UBRR=
3
7.8 UBRR=
8
3.7 UBRR=
10
3.1
5
0.0 UBRR=
7
0.0
UBRR=
2
7.8 UBRR=
6
7.5 UBRR=
3
0.0 UBRR=
UBRR=
1
7.8 UBRR=
3
7.8 UBRR=
4
6.3
1
0.0 UBRR=
UBRR=
0
7.8 UBRR=
1
7.8 UBRR=
2
12.5
0
0.0 UBRR=
UBRR=
0
84.3 UBRR=
0
7.8 UBRR=
0
25.0
Baud Rate
2400
4800
9600
14400
19200
28800
57600
115200
3.2768 MHz %Error 3.6864 MHz %Error
4 MHz %Error
4.608 MHz %Error
84
0.4 UBRR=
95
0.0 UBRR=
103
0.2 UBRR=
119
0.0
UBRR=
42
0.8 UBRR=
47
0.0 UBRR=
51
0.2 UBRR=
59
0.0
UBRR=
20
1.6 UBRR=
23
0.0 UBRR=
25
0.2 UBRR=
29
0.0
UBRR=
13
1.6 UBRR=
15
0.0 UBRR=
19
0.0
UBRR=
16
2.1 UBRR=
11
0.0 UBRR=
12
0.2 UBRR=
14
0.0
UBRR=
10
3.1 UBRR=
6
1.6 UBRR=
7
0.0 UBRR=
9
0.0
UBRR=
8
3.7 UBRR=
3
0.0 UBRR=
4
0.0
UBRR=
3
12.5 UBRR=
3
7.8 UBRR=
UBRR=
1
12.5 UBRR=
1
7.8 UBRR=
2
20.0
1
0.0 UBRR=
Baud Rate
2400
4800
9600
14400
19200
28800
57600
115200
7.3728 MHz %Error
8 MHz %Error
9.216 MHz %Error 11.059 MHz %Error
UBRR=
287
191
0.0 UBRR=
207
0.2 UBRR=
239
0.0 UBRR=
UBRR=
95
0.0 UBRR=
103
0.2 UBRR=
119
0.0 UBRR=
143
0.0
UBRR=
47
0.0 UBRR=
51
0.2 UBRR=
59
0.0 UBRR=
71
0.0
UBRR=
31
0.0 UBRR=
34
0.8 UBRR=
39
0.0 UBRR=
47
0.0
UBRR=
23
0.0 UBRR=
25
0.2 UBRR=
29
0.0 UBRR=
35
0.0
UBRR=
16
2.1 UBRR=
15
0.0 UBRR=
19
0.0 UBRR=
23
0.0
UBRR=
8
3.7 UBRR=
7
0.0 UBRR=
9
0.0 UBRR=
11
0.0
3
0.0 UBRR=
4
0.0 UBRR=
5
0.0
UBRR=
3
7.8 UBRR=
Baud Rate
2400
4800
9600
14400
19200
28800
57600
115200
14.746 MHz %Error
16 MHz %Error 18.432 MHz %Error
20 MHz %Error
UBRR=
383
UBRR=
416
UBRR=
479
UBRR=
520
191
0.0 UBRR=
207
0.2 UBRR=
239
0.0 UBRR=
UBRR=
259
95
0.0 UBRR=
103
0.2 UBRR=
119
0.0 UBRR=
129
0.2
UBRR=
63
0.0 UBRR=
68
0.6 UBRR=
79
0.0 UBRR=
86
0.2
UBRR=
47
0.0 UBRR=
51
0.2 UBRR=
59
0.0 UBRR=
64
0.2
UBRR=
31
0.0 UBRR=
34
0.8 UBRR=
39
0.0 UBRR=
42
0.9
UBRR=
15
0.0 UBRR=
19
0.0 UBRR=
21
1.4
UBRR=
16
2.1 UBRR=
7
0.0 UBRR=
9
0.0 UBRR=
10
1.4
UBRR=
8
3.7 UBRR=
THE UART BAUD RATE REGISTER - UBRR
Bit
$09
Read/Write
Initial value
7
MSB
R/W
0
6
5
4
3
2
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
LSB
R/W
0
UBRR
The UBRR register is an 8-bit read/write register which specifies the UART Baud Rate according to the description on
Page 4-55.
4-56
AT90S8414 Preliminary
AT90S8414
The Analog Comparator
The analog comparator compares the input values on the positive pin PB2 (AIN0) and negative pin PB3 (AIN1). When
the voltage on the positive pin PB2 (AIN0) is higher than the voltage on the negative pin PB3 (AIN1), the Analog
Comparator Output, ACO is set (one). The comparator’s output can be set to trigger the Timer/Counter1 Input Capture
function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can
select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its
surrounding logic is shown in Figure 45.
Figure 45: Analog Comparator Block Diagram
THE ANALOG COMPARATOR CONTROL AND STATUS REGISTER - ACSR
Bit
$08
Read/Write
Initial value
7
ACD
R/W
0
6
R
0
5
ACO
R
0
4
ACI
R/W
0
3
ACIE
R/W
0
2
ACIC
R/W
0
1
ACIS1
R/W
0
0
ACIS0
R/W
0
ACSR
Bit 7 - ACD : Analog Comparator Disable
When this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off
the analog comparator. It is most commonly used if power consumption during Idle Mode is critical, and wake-up from
the analog comparator is not required. When changing the ACD bit, the Analog Comparator Interrupt must be disabled
by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.
Bit 6 - Res : Reserved bit:
This bit is a reserved bit in the AT90S8414 and will always read as zero.
Bit 5 - ACO : Analog Comparator Output:
ACO is directly connected to the comparator output.
Bit 4 - ACI : Analog Comparator Interrupt Flag:
This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog
Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic
one to the flag.
Preliminary
4-57
Bit 3 - ACIE : Analog Comparator Interrupt Enable:
When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the analog comparator interrupt is
activated. When cleared (zero), the interrupt is disabled. For details on the comparator, refer to Page 4-57.
Bit 2 - ACIC : Analog Comparator Input Capture enable:
When set (one), this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator.
The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator
utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When cleared (zero), no
connection between the analog comparator and the Input Capture function is given. To make the comparator trigger the
Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set (one).
Bits 1,0 - ACIS1, ACIS0 : Analog Comparator Interrupt Mode Select:
These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are
shown in Table 15.
Table 15: ACIS1/ACIS0 Settings
ACIS1
0
0
1
1
ACIS0
0
1
0
1
Interrupt Mode
Comparator Interrupt on Output Toggle
Reserved
Comparator Interrupt on Falling Output Edge
Comparator Interrupt on Rising Output Edge
Note: When changing the ACIS1/ACIS0 bits, The Analog Comparator Interrupt must be disabled by clearing its Interrupt
Enable bit in the ACSR register. Otherwise an interrupt can occur when the bits are changed.
I/O-Ports
Port A
PORT A is an 8-bit bi-directional I/O port.
Three data memory address locations are allocated for the Port A, one each for the Data Register - PORTA ($1B), Data
Direction Register - DDRA ($1A) and the Port A Input Pins - PINA ($19). The Port A Input Pins address is read only,
while the Data Register and the Data Direction Register are read/write.
All port pins have individually selectable pullups. The PORT A output buffers can sink 20mA and thus drive LED
displays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current (IIL) if
the internal pullups are activated.
The PORT A pins have alternate functions related to the optional external data SRAM. PORT A can be configured to be
the multiplexed low-order address/data bus during accesses to the external data memory. In this mode, PORT A has
internal pullups.
PORT A also receives the code bytes during Flash programming and outputs the code bytes during program verification.
External pullups are required during program verification.
When PORT A is set to the alternate function by the SRE - External SRAM Enable - bit in the MCUCR - MCU Control
Register, the alternate settings override the data direction register.
4-58
AT90S8414 Preliminary
AT90S8414
THE PORT A DATA REGISTER - PORTA
Bit
$1B
Read/Write
Initial value
7
PORTA7
R/W
0
6
PORTA6
R/W
0
5
PORTA5
R/W
0
4
PORTA4
R/W
0
3
PORTA3
R/W
0
2
PORTA2
R/W
0
1
PORTA1
R/W
0
0
PORTA0
R/W
0
4
DDA4
R/W
0
3
DDA3
R/W
0
2
DDA2
R/W
0
1
DDA1
R/W
0
0
DDA0
R/W
0
4
PINA4
R
Hi-Z
3
PINA3
R
Hi-Z
2
PINA2
R
Hi-Z
1
PINA1
R
Hi-Z
0
PINA0
R
Hi-Z
PORTA
THE PORT A DATA DIRECTION REGISTER - DDRA
Bit
$1A
Read/Write
Initial value
7
DDA7
R/W
0
6
DDA6
R/W
0
5
DDA5
R/W
0
DDRA
THE PORT A INPUT PINS ADDRESS - PINA
Bit
$19
Read/Write
Initial value
7
PINA7
R
Hi-Z
6
PINA6
R
Hi-Z
5
PINA5
R
Hi-Z
PINA
The Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each
Port A pin. When reading PORTA the PORTA Data Latch is read, and when reading PINA, the logical values present on
the pins are read.
PORTA AS GENERAL DIGITAL I/O
All 8 bits in PORT A are equal when used as digital I/O pins.
PAn, General I/O pin: The DDAn bit in the DDRA register selects the direction of this pin, if DDAn is set (one), PAn is
configured as an output pin. If DDAn is cleared (zero), PAn is configured as an input pin. If PORTAn is set (one) when
the pin configured as an input pin, the MOS pull up resistor is activated. To switch the pull up resistor off, the PORTAn
has to be cleared (zero) or the pin has to be configured as an output pin.
Table 16: DDAn Effects on PORT A Pins
DDAn
0
0
1
1
PORTAn
0
1
0
1
I/O
Input
Input
Output
Output
Pull up
No
Yes
No
No
Comment
Tri-state (Hi-Z)
PAn will source current (IIL) if ext. pulled low.
Push-Pull Zero Output
Push-Pull One Output
n: 7,6…0, pin number.
Preliminary
4-59
PORT A SCHEMATICS
Note that all port pins are synchronized. The synchronization latch is however, not shown in the figure.
Figure 46: PORTA Schematic Diagrams (Pins PA0 - PA7)
Port B
Port B is an 8-bit bi-directional I/O port.
Three data memory address locations are allocated for the Port B, one each for the Data Register - PORTB ($18), Data
Direction Register - DDRB ($17) and the Port B Input Pins - PINB ($16). The Port B Input Pins address is read only,
while the Data Register and the Data Direction Register are read/write.
All port pins have individually selectable pullups. The Port B output buffers can sink 20mA and thus drive LED displays
directly. When pins PB0 to PB7 are used as inputs and are externally pulled low, they will source current (IIL) if the
internal pullups are activated.
The Port B pins with alternate functions are shown in the following table:
4-60
AT90S8414 Preliminary
AT90S8414
Table 17: Port B Pins Alternate Functions
Port Pin
PB0
PB1
PB2
PB3
PB4
Alternate Functions
T0 (Timer/Counter 0 external counter input)
T1 (Timer/Counter 1 external counter input)
AIN0 (Analog comparator positive input)
AIN1 (Analog comparator negative input)
(SPI Slave Select input)
MOSI (SPI Bus Master Output/Slave Input)
MISO (SPI Bus Master Input/Slave Output)
SCK (SPI Bus Serial Clock)
PB5
PB6
PB7
When the pins are used for the alternate function the DDRB and PORTB register has to be set according to the alternate
function description.
THE PORT B DATA REGISTER - PORTB
Bit
$18
Read/Write
Initial value
7
PORTB7
R/W
0
6
PORTB6
R/W
0
5
PORTB5
R/W
0
4
PORTB4
R/W
0
3
PORTB3
R/W
0
2
PORTB2
R/W
0
1
PORTB1
R/W
0
0
PORTB0
R/W
0
4
DDB4
R/W
0
3
DDB3
R/W
0
2
DDB2
R/W
0
1
DDB1
R/W
0
0
DDB0
R/W
0
4
PINB4
R
Hi-Z
3
PINB3
R
Hi-Z
2
PINB2
R
Hi-Z
1
PINB1
R
Hi-Z
0
PINB0
R
Hi-Z
PORTB
THE PORT B DATA DIRECTION REGISTER - DDRB
Bit
$17
Read/Write
Initial value
7
DDB7
R/W
0
6
DDB6
R/W
0
5
DDB5
R/W
0
DDRB
THE PORT B INPUT PINS ADDRESS - PINB
Bit
$16
Read/Write
Initial value
7
PINB7
R
Hi-Z
6
PINB6
R
Hi-Z
5
PINB5
R
Hi-Z
PINB
The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port
B pin. When reading PORTB, the PORTB Data Latch is read, and when reading PINB, the logical values present on the
pins are read.
PORTB AS GENERAL DIGITAL I/O
All 8 bits in port B are equal when used as digital I/O pins.
PBn, General I/O pin: The DDBn bit in the DDRB register selects the direction of this pin, if DDBn is set (one), PBn is
configured as an output pin. If DDBn is cleared (zero), PBn is configured as an input pin. If PORTBn is set (one) when
the pin configured as an input pin, the MOS pull up resistor is activated. To switch the pull up resistor off, the PORTBn
has to be cleared (zero) or the pin has to be configured as an output pin.
Preliminary
4-61
Table 18: DDBn Effects on Port B Pins
DDBn
0
0
1
1
PORTBn
0
1
0
1
I/O
Input
Input
Output
Output
Pull up
No
Yes
No
No
Comment
Tri-state (Hi-Z)
PBn will source current (IIL) if ext. pulled low.
Push-Pull Zero Output
Push-Pull One Output
n: 7,6…0, pin number.
ALTERNATE FUNCTIONS FOR PORTB
The alternate pin configuration is as follows:
SCK - PORTB, Bit 7:
SCK: Master clock output, slave clock input pin for SPI channel
MISO - PORTB, Bit 6:
MISO: Master data input, slave data output pin for SPI channel
MOSI - PORTB, Bit 5:
MOSI: SPI Master data output, slave data input for SPI channel
SS - PORTB, Bit 4:
S S
(Slave port select input)
AIN1 - PORTB, Bit 3
AIN1, Analog Comparator Negative Input. When configured as an input (DDB3 is cleared (zero)) and with the internal
MOS pull up resistor switched off (PB3 is cleared (zero)), this pin also serves as the negative input of the on-chip analog
comparator.
AIN0 - PORTB, Bit 2
AIN0, Analog Comparator Positive Input. When configured as an input (DDB2 is cleared (zero)) and with the internal
MOS pull up resistor switched off (PB2 is cleared (zero)), this pin also serves as the positive input of the on-chip analog
comparator.
T1 - PORTB, Bit 1:
T1, Timer/Counter1 counter source: The PB1 pin has to be configured as an input (DDB1 is cleared (zero)) to serve this
function. See the timer description for further details. The internal pull up MOS resistor can be activated as described
above.
T0 - PORTB, Bit 0:
T0: Timer/Counter0 counter source: The PB0 pin has to be configured as an input (DDB0 is cleared (zero)) to serve this
function. See the timer description for further details. The internal pull up MOS resistor can be activated as described
above.
4-62
AT90S8414 Preliminary
AT90S8414
PORT B SCHEMATICS
Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures.
Figure 47: PORTB Schematic Diagram (Pins PB0 and PB1)
Preliminary
4-63
Figure 48: PORTB Schematic Diagram (Pins PB2 and PB3)
Figure 49: PORTB Schematic Diagram (Pin PB4)
4-64
AT90S8414 Preliminary
AT90S8414
Figure 50: PORTB Schematic Diagram (Pin PB5)
Figure 51: PORTB Schematic Diagram (Pin PB6)
Preliminary
4-65
Figure 52: PORTB Schematic Diagram (Pin PB7)
Port C
PORT C is an 8-bit bi-directional I/O port.
Three data memory address locations are allocated for the Port C, one each for the Data Register - PORTC ($15), Data
Direction Register - DDRC ($14) and the Port C Input Pins - PINC ($13). The Port C Input Pins address is read only,
while the Data Register and the Data Direction Register are read/write.
All port pins have individually selectable pullups. The PORT C output buffers can sink 20mA and thus drive LED
displays directly. When pins PC0 to PC7 are used as inputs and are externally pulled low, they will source current (IIL) if
the internal pullups are activated.
The PORT C pins have alternate functions related to the optional external data SRAM. PORT C can be configured to be
the high-order address byte during accesses to external data memory. In this mode, PORT C uses internal pullups when
emitting 1’s.
PORT C also receives the high-order address bits and some control signals during Flash programming and verification.
When PORT C is set to the alternate function by the SRE - External SRAM Enable - bit in the MCUCR - MCU Control
Register, the alternate settings override the data direction register.
THE PORT C DATA REGISTER - PORTC
Bit
$15
Read/Write
Initial value
4-66
7
PORTC7
R/W
0
6
PORTC6
R/W
0
5
PORTC5
R/W
0
4
PORTC4
R/W
0
AT90S8414 Preliminary
3
PORTC3
R/W
0
2
PORTC2
R/W
0
1
PORTC1
R/W
0
0
PORTC0
R/W
0
PORTC
AT90S8414
THE PORT C DATA DIRECTION REGISTER - DDRC
Bit
$14
Read/Write
Initial value
7
DDC7
R/W
0
6
DDC6
R/W
0
5
DDC5
R/W
0
4
DDC4
R/W
0
3
DDC3
R/W
0
2
DDC2
R/W
0
1
DDC1
R/W
0
0
DDC0
R/W
0
4
PINC4
R
Hi-Z
3
PINC3
R
Hi-Z
2
PINC2
R
Hi-Z
1
PINC1
R
Hi-Z
0
PINC0
R
Hi-Z
DDRC
THE PORT C INPUT PINS ADDRESS - PINC
Bit
$13
Read/Write
Initial value
7
PINC7
R
Hi-Z
6
PINC6
R
Hi-Z
5
PINC5
R
Hi-Z
PINC
The Port C Input Pins address - PINC - is not a register, and this address enables access to the physical value on each Port
C pin. When reading PORTC, the PORTC Data Latch is read, and when reading PINC, the logical values present on the
pins are read.
PORTC AS GENERAL DIGITAL I/O
All 8 bits in PORT C are equal when used as digital I/O pins.
PCn, General I/O pin: The DDCn bit in the DDRC register selects the direction of this pin, if DDCn is set (one), PCn is
configured as an output pin. If DDCn is cleared (zero), PCn is configured as an input pin. If PORTCn is set (one) when
the pin configured as an input pin, the MOS pull up resistor is activated. To switch the pull up resistor off, PORTCn has
to be cleared (zero) or the pin has to be configured as an output pin.
Table 19: DDCn Effects on PORT C Pins
DDCn
0
0
1
1
PORTCn
0
1
0
1
I/O
Input
Input
Output
Output
Pull up
No
Yes
No
No
Comment
Tri-state (Hi-Z)
PCn will source current (IIL) if ext. pulled low.
Push-Pull Zero Output
Push-Pull One Output
n: 7…0, pin number.
PORT C SCHEMATICS
Note that all port pins are synchronized. The synchronization latch is however, not shown in the figure.
Preliminary
4-67
Figure 53: PORTC Schematic Diagram (Pins PC0 - PC7)
4-68
AT90S8414 Preliminary
AT90S8414
Port D
Port D is an 8 bit bi-directional I/O port with internal pullups.
Three data memory address locations are allocated for the Port D, one each for the Data Register - PORTD ($12), Data
Direction Register - DDRD ($11) and the Port D Input Pins - PIND ($10). The Port D Input Pins address is read only,
while the Data Register and the Data Direction Register are read/write.
The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current (IIL)
if the pullups are activated.
Some Port D pins have alternate functions as shown in the following table:
Table 20: Port D Pins Alternate Functions
Port Pin
PD0
PD1
PD2
PD3
PD4
PD5
PD6
Alternate Function
RDX (UART Input line )
TDX (UART Output line)
INT0 (External interrupt 0 input)
INT1 (External interrupt 1 input)
OC0 (Timer/Counter0 Output compare match output)
OC1A (Timer/Counter1 Output compareA match output)
WR (Write strobe to external memory)
PD7
(Read strobe to external memory)
When the pins are used for the alternate function the DDRD and PORTD register has to be set according to the alternate
function description.
THE PORT D DATA REGISTER - PORTD
Bit
$12
Read/Write
Initial value
7
PORTD7
R/W
0
6
PORTD6
R/W
0
5
PORTD5
R/W
0
4
PORTD4
R/W
0
3
PORTD3
R/W
0
2
PORTD2
R/W
0
1
PORTD1
R/W
0
0
PORTD0
R/W
0
4
DDD4
R/W
0
3
DDD3
R/W
0
2
DDD2
R/W
0
1
DDD1
R/W
0
0
DDD0
R/W
0
4
PIND4
R
Hi-Z
3
PIND3
R
Hi-Z
2
PIND2
R
Hi-Z
1
PIND1
R
Hi-Z
0
PIND0
R
Hi-Z
PORTD
THE PORT D DATA DIRECTION REGISTER - DDRD
Bit
$11
Read/Write
Initial value
7
DDD7
R/W
0
6
DDD6
R/W
0
5
DDD5
R/W
0
DDRD
THE PORT D INPUT PINS ADDRESS - PIND
Bit
$10
Read/Write
Initial value
7
PIND7
R
Hi-Z
6
PIND6
R
Hi-Z
5
PIND5
R
Hi-Z
Preliminary
PIND
4-69
The Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each
Port D pin. When reading PORTD, the PORTD Data Latch is read, and when reading PIND, the logical values present on
the pins are read.
PORTD AS GENERAL DIGITAL I/O
PDn, General I/O pin: The DDDn bit in the DDRD register selects the direction of this pin. If DDDn is set (one), PDn is
configured as an output pin. If DDDn is cleared (zero), PDn is configured as an input pin. If PDn is set (one) when
configured as an input pin the MOS pull up resistor is activated. To switch the pull up resistor off the PDn has to be
cleared (zero) or the pin has to be configured as an output pin.
Table 21: DDDn Bits on Port D Pins
DDDn
0
0
1
1
PORTDn
0
1
0
1
I/O
Input
Input
Output
Output
Pull up
No
Yes
No
No
Comment
Tri-state (Hi-Z)
PDn will source current (IIL) if ext. pulled low.
Push-Pull Zero Output
Push-Pull One Output
n: 7,6…0, pin number.
ALTERNATE FUNCTIONS FOR PORTD
RD - PORTD, Bit 7:
RD is the external data memory read control strobe.
WR - PORTD, Bit 6:
WR is the external data memory write control strobe.
OC1- PORTD, Bit 5:
OC1, Output compare match output: The PD5 pin can serve as an external output when the Timer/Counter1 compare
matches. The PD5 pin has to be configured as an output (DDD5 set (one)) to serve this function. See the Timer/Counter1
description for further details, and how to enable the output. The OC1 pin is also the output pin for the PWM mode timer
function.
OC0- PORTD, Bit 4:
OC0, Output compare match output: The PD4 pin can serve as an external output when the Timer/Counter0 compare
matches. The PD4 pin has to be configured as an output (DDD4 set (one)) to serve this function. See the Timer/Counter0
description for further details, and how to enable the output.
INT1 - PORTD, Bit 3:
INT1, External Interrupt source 1: The PD3 pin can serve as an external active low interrupt source to the MCU. The
PD3 pin has to be configured as an input (DDD3 is cleared (zero)) to serve this function. The internal pull up MOS
resistor can be activated as described above. See the interrupt description for further details, and how to enable the
source.
4-70
AT90S8414 Preliminary
AT90S8414
INT0 - PORTD, Bit 2:
INT0, External Interrupt source 0: The PD2 pin can serve as an external active low interrupt source to the MCU. The
PD2 pin has to be configured as an input (DDD2 is cleared (zero)) to serve this function. The internal pull up MOS
resistor can be activated as described above. See the interrupt description for further details, and how to enable the
source.
TXD - PORTD, Bit 1:
TXD is the serial UART output pin. See “The UART”.
RXD - PORTD, Bit 0:
RXD is the serial UART output pin. See “The UART”.
PORTD SCHEMATICS
Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures.
Figure 54: PORTD Schematic Diagram (Pin PD0)
Preliminary
4-71
Figure 55: PORTD Schematic Diagram (Pin PD1)
Figure 56: PORTD Schematic Diagram (Pins PD2 and PD3)
4-72
AT90S8414 Preliminary
AT90S8414
Figure 57: PORTD Schematic Diagrams (Pin PD4 and PD5)
Figure 58: PORTD Schematic Diagram (Pin PD6)
Preliminary
4-73
Figure 59: PORTD Schematic Diagram (Pin PD7)
Memory Programming
Program Memory Lock Bits
The AT90S8414 MCU provides three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain
the additional features listed in Table 22.
Table 22: Lock Bit Protection Modes
Program Lock Bits
Mode
LB1
LB2
1
U
U
2
P
Protection Type
No program lock features
Further programming of the Flash is disabled
U
Same as mode 2, but verify is also disabled.
3
P
P
Note: The Lock Bits can only be erased with the Chip Erase operation.
4-74
AT90S8414 Preliminary
AT90S8414
Programming the Flash and EEPROM
Atmel’s AT90S8414 offers 8K bytes of in-system reprogrammable Flash Program memory and 256 bytes of EEPROM
Data memory.
The AT90S8414 is normally shipped with the on-chip Flash Program and EEPROM Data memory arrays in the erased
state (i.e. contents = $FF) and ready to be programmed. This device supports a High-Voltage (12V) Parallel
programming mode and a Low-Voltage Serial programming mode. The serial programming mode provides a convenient
way to download the Program and Data into the AT90S8414 inside the user’s system.
The Program and Data memory arrays on the AT90S8414 are programmed byte-by-byte in either programming modes.
An auto-erase cycle is provided with the self-timed programming operation in the serial programming mode.
Parallel Programming
To be determined
Serial Downloading
Both the Program and Data memory arrays can be programmed using the serial SPI bus while R E S E T is pulled to GND.
The serial interface consists of pins SCK, MOSI (input) and MISO (output). After R E S E T is set low, the Programming
Enable instruction needs to be executed first before program/erase operations can be executed.
An auto-erase cycle is built into the self-timed programming operation (in the serial mode ONLY) and there is no need to
first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROMarrays into $FF.
The Program and EEPROM memory arrays have separate address spaces:
$0000 to $1FFF for Program memory and $0000 to $00FF for EEPROM memory.
Either an external system clock is supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and
XTAL2. The maximum serial clock (SCK) frequency should be less than 1/4 of the crystal frequency. With a 10 MHz
oscillator clock, the maximum SCK frequency is 2.5 MHz.
Preliminary
4-75
SERIAL PROGRAMMING ALGORITHM
To program and verify the AT90S8414 in the serial programming mode, the following sequence is recommended (See
four byte instruction formats in
4-76
AT90S8414 Preliminary
AT90S8414
Table 23):
1. Power-up sequence:
Apply power between VCC and GND.
Set R E S E T pin to ’L’.
If a crystal is not connected across pins XTAL1 and XTAL2, apply a 1 MHz to 24 MHz clock to the XTAL1 pin and
wait for at least 10 milliseconds.
2. Enable serial programming by sending the Programming Enable serial instruction to pin MOSI/PB5. The frequency
of the shift clock supplied at pin SCK/PB7 needs to be less than the CPU clock at XTAL1 divided by 4.
3. The Program or EEPROM array is programmed one byte at a time by supplying the address and data together with
the appropriate Write instruction. The selected memory location is first automatically erased before new data is
written.
4. Any memory location can be verified by using the Read instruction which returns the content at the selected address
at serial output MISO/PB6.
polling is used to indicate the end of a write cycle, which typically takes less than 2.5 ms.
5. At the end of the programming session, R E S E T can be set high to commence normal operation.
6. Power-off sequence (if needed):
Set XTAL1 to ‘L’ (if a crystal is not used).
Set R E S E T to ‘H’
Turn VCC power off.
Preliminary
4-77
Table 23: Serial Programming Instruction Set
Instruction
Programming
Enable
Instruction Format
Byte 1
Byte 2
Operation
Byte 3
Byte4
1010 1100
0101 0011
xxxx xxxx
xxxx xxxx
1010 1100
100x xxxx
xxxx xxxx
xxxx xxxx
0010 H000
xxxx aaaa
bbbb bbbb
oooo oooo
Write Program
Memory
0110 H000
xxxx aaaa
bbbb bbbb
iiii iiii
Read EEPROM
Memory
1010 0000
xxxx xxxx
bbbb bbbb
oooo oooo
Write EEPROM
Memory
1110 0000
xxxx xxxx
bbbb bbbb
iiii iiii
Write Lock Bits
1010 1100
111x x012
xxxx xxxx
xxxx xxxx
Read Device
Code
0011 0000
xxxx xxxx
xxxx xxxx
oooo oooo
Chip Erase
Read Program
Memory
Note:
a = address high bits
b = address low bits
H = 0 - Low byte, 1 - High Byte
o = data out
i = data in
x = don’t care
1 = lock bit 1
2 = lock bit 2
Figure 60: Serial Programming and Verify
4-78
AT90S8414 Preliminary
Enable Serial Programming after RESET goes
low.
Chip erase both 8K & 256
byte memory arrays
Read H(high or low) data o
from Program memory at
word address a:b
Write H(high or low) data i
to Program memory at
word address a:b
Read data o from
EEPROM memory at
address b
Write data i to EEPROM
memory at address b
Write lock bits. Set bits
1,2=’0’ to program lock
bits.
Read Device Code o
AT90S8414
When writing serial data to the AT90S8414, data is clocked on the rising edge of CLK.
When reading data from the AT90S8414, data is clocked on the falling edge of CLK. See Figure 61 for an explanation.
Programming Characteristics
Figure 61: Serial Downloading Waveforms
Absolute Maximum Ratings
Operating Temperature…........... -55°C to +125°C
Storage Temperature…….......... -65°C to +150°C
Voltage on any Pin
with respect to Ground…….......... -1.0 V to +7.0 V
NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or other conditions beyond those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Maximum Operating Voltage……........…….. 6.6 V
DC Output Current……………………........25.0mA
Preliminary
4-79
D.C. Characteristics
TA=-40°C to 85°C Vcc=2.7V to 6.0V (unless otherwise noted)
Symbol
VIL
Parameter
Input Low Voltage
Condition
VIH
Input High Voltage
(Except XTAL1, RESET)
VIH1
Input High Voltage
(XTAL1, RESET)
VOL
IOL = 20 mA, VCC = 5 V
IOL = 10 mA, VCC = 2.7 V
IHI = 10 mA, VCC = 5 V
IHI = 5 mA, VCC = 2.7 V
VCC = 5 V
VCC = 2.7 V
VCC = 5 V
VCC = 2.7 V
RRST
ICC
Output Low Voltage(1)
(Ports B,C,D)
Output High Voltage
(Ports B,C,D)
Output Source Current
(Ports B,C,D)
Output Sink Current
(Port B,C,D)
Reset Pulldown Resistor
Power Supply Current
ICC
Power Down Mode(2)
VACIO
Analog Comparator
Input Offset Voltage
Analog Comparator
Input Leakage Current
Analog Comparator
Propagation Delay
WDT enabled, 3V
WDT disabled, 3V
VCC = 5V
VOH
IOH
IOL
IACLK
tACPD
Min
-0.5
Typ
0.2 VCC +
0.9
0,7 VCC
Units
V
VCC +
0.5
0.5
V
4.5
10
5
20
10
50
3.5
1000
5
AT90S8414 Preliminary
mA
mA
KW
mA
mA
20
10
nA
750
500
Notes:
1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10mA
Maximum total IOL for all output pins: 80mA
Port A: 26 mA
Ports A, B, D 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current
greater than the listed test conditions.
2. Minimum VCC for Power Down is 2 V.
4-80
V
mA
mA
mV
50
<1
1
V
V
10
Active Mode, 3V, 4MHz
Idle Mode 3V, 4MHz
VCC = 2.7 V
VCC = 4.0 V
Max
0.2 Vcc 0.1
VCC + 0.5
ns
AT90S8414
A.C. Characteristics
Load capacitance for Port A & ALE = 100 pF; Load capacitance for all outputs = 80 pF.
10 MHz Oscillator
Min
Max
Symbol
1/tCK
tLHLL
tAVLL
tLLAX
tRLRH
Parameter
Oscillator Frequency
ALE Pulse Width
Address Valid to ALE Low
Address Hold After ALE Low
RD Pulse Width
50
40
10
150
tWLWH
WR Pulse Width
50
tRLDV
RD Low to Valid Data In
tRHDX
Data Hold After RD
tRHDZ
Data Float After RD
ALE Low to Valid Data In
Address to Valid Data In
tLLDV
tAVDV
tLLWL
Variable Oscillator
Min
Max
0
20
tck/2
tck/2-10
10
3 tck/2
tck/2
ns
10
0
ALE Low to RD or WR
Units
MHz
ns
ns
ns
ns
10
0
ns
ns
20
20
ns
60
100
100
tck/2+10
tck
tck
ns
ns
ns
tAVWL
Address to RD or WR Low
90
tck-10
ns
tQVWX
Data Valid to WR High
60
tck/2+10
ns
tWHQX
Data Hold after WR
15
15
ns
tWHLH
RD or WR High to ALE High
100
tck
ns
External Data Memory Read Cycle
Preliminary
4-81
External Memory Write Cycle
External Clock Drive Waveforms
External Clock Drive
Symbol
Parameter
1/tCLCL
tCLCL
tCHCX
tCLCX
tCLCH
tCHCL
Oscillator Frequency
Clock Period
High Time
Low Time
Rise Time
Fall Time
4-82
VCC = 2.7 V to 6.0 V
Min
Max
0
10
100
40
40
10
10
AT90S8414 Preliminary
VCC = 4.0 V to 6.0 V
Min
Max
0
24
41.7
16.7
16.7
4.15
4.15
Units
MHz
ns
ns
ns
ns
ns
AT90S8414
Ordering Information
Ordering Code
AT90S8414-JC
AT90S8414-PC
AT90S8414-JI
AT90S8414-PI
44J
40P6
Package
44J
40P6
44J
40P6
Operation Range
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C)
Package Type
44 Lead, Plastic J-Leaded Chip Carrier (PLCC)
40 Lead, 0.600” Wide, Plastic Dual in Line Package (PDIP)
Preliminary
4-83
AT90S8414 Register Summary
Address
$3F
$3E
$3D
$3C
$3B
$3A
$39
$38
$37
$36
$35
$34
$33
$32
$31
$30
$2F
$2E
$2D
$2C
$2B
$2A
$29
$28
$27
$26
$25
$24
$23
$22
$21
$20
$1F
$1E
$1D
$1C
$1B
$1A
$19
$18
$17
$16
$15
$14
$13
$12
$11
$10
$0F
$0E
$0D
$0C
$0B
$0A
$09
$08
…
$00
4-84
Name
SREG
SPH
SPL
Reserved
GIMSK
Reserved
TIMSK
TIFR
Reserved
Reserved
MCUCR
Reserved
TCCR0
TCNT0
OCR0
Reserved
TCCR1A
TCCR1B
TCNT1H
TCNT1L
OCR1AH
OCR1AL
OCR1BH
OCR1BL
Reserved
Reserved
ICR1H
ICR1L
Reserved
Reserved
WDTCR
Reserved
Reserved
EEAR
EEDR
EECR
PORTA
DDRA
PINA
PORTB
DDRB
PINB
PORTC
DDRC
PINC
PORTD
DDRD
PIND
SPDR
SPSR
SPCR
UDR
USR
UCR
UBRR
ACSR
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
I
SP7
T
SP6
H
SP5
S
SP4
V
SP3
N
SP2
Z
SP1
C
SP8
SP0
4-23
4-24
4-24
INT1
INT0
-
-
-
-
-
-
4-28
TOIE1
TOV1
OCIE1A
OCF1A
OCIE1B
OCF1B
-
TICIE1
ICF1
-
TOIE0
TOV0
OCIE0
OCF0
4-29
4-29
SRE
SRW
SE
SM
ISC11
ISC10
ISC01
ISC00
4-32
CTC0
CS02
CS01
CS00
4-35
4-36
4-36
COM1A1
COM1A0
COM1B1
COM1B0
ICNC1
ICES1
CTC1
Timer/Counter1 - Counter Register High Byte
Timer/Counter1 - Counter Register Low Byte
Timer/Counter1 - Output Compare Register A High Byte
Timer/Counter1 - Output Compare Register A Low Byte
Timer/Counter1 - Output Compare Register B High Byte
Timer/Counter1 - Output Compare Register B Low Byte
CS12
CS11
PWM1
CS10
4-39
4-39
4-40
4-40
4-41
4-41
4-41
4-41
COM01
COM00
Timer/Counter0 (8 Bit)
Timer/Counter0 Output Compare Register
Timer/Counter1 - Input Capture Register High Byte
Timer/Counter1 - Input Capture Register Low Byte
-
-
-
EEPROM Address Register
EEPROM Data Register
PA7
PA6
PA5
DDA7
DDA6
DDA5
PINA7
PINA6
PINA5
PB7
PB6
PB5
DDB7
DDB6
DDB5
PINB7
PINB6
PINB5
PC7
PC6
PC5
DDC7
DDC6
DDC5
PINC7
PINC6
PINC5
PD7
PD6
PD5
DDD7
DDD6
DDD5
PIND7
PIND6
PIND5
SPI Data Register
SPIF
WCOL
SPIE
SPE
DORD
UART I/O Data Register
RXC
TXC
UDRE
RXCIE
TXCIE
UDRIE
UART Baud Rate Register
ACD
ACO
-
PA4
DDA4
PINA4
PB4
DDB4
PINB4
PC4
DDC4
PINC4
PD4
DDD4
PIND4
4-41
4-41
WDE
PA3
DDA3
PINA3
PB3
DDB3
PINB3
PC3
DDC3
PINC3
PD3
DDD3
PIND3
WDP2
PA2
DDA2
PINA2
PB2
DDB2
PINB2
PC2
DDC2
PINC2
PD2
DDD2
PIND2
WDP1
EEWE
PA1
DDA1
PINA1
PB1
DDB1
PINB1
PC1
DDC1
PINC1
PD1
DDD1
PIND1
WDP0
EERE
PA0
DDA0
PINA0
PB0
DDB0
PINB0
PC0
DDC0
PINC0
PD0
DDD0
PIND0
MSTR
CPOL
CPHA
SPR1
SPR0
FE
RXEN
OR
TXEN
CHR9
RXB8
TXB8
ACI
ACIE
ACIC
ACIS1
ACIS0
AT90S8414 Preliminary
4-44
4-45
4-45
4-45
4-59
4-59
4-59
4-61
4-61
4-61
4-66
4-67
4-67
4-69
4-69
4-69
4-50
4-49
4-48
4-53
4-53
4-54
4-56
4-57
AT90S8414
AT90S8414 Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
Rd ¬ Rd + Rr
Z,C,N,V,H
1
ADC
Rd, Rr
Add with Carry two Registers
Rd ¬ Rd + Rr + C
Z,C,N,V,H
1
ADIW
Rdl,K
Add Immediate to Word
Rdh:Rdl ¬ Rdh:Rdl + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract two Registers
Rd ¬ Rd - Rr
Z,C,N,V,H
1
SUBI
Rd, K
Subtract Constant from Register
Rd ¬ Rd - K
Z,C,N,V,H
1
SBC
Rd, Rr
Subtract with Carry two Registers
Rd ¬ Rd - Rr - C
Z,C,N,V,H
1
SBCI
Rd, K
Subtract with Carry Constant from Reg.
Rd ¬ Rd - K - C
Z,C,N,V,H
1
SBIW
Rdl,K
Subtract Immediate from Word
Rdh:Rdl ¬ Rdh:Rdl - K
Z,C,N,V,S
2
AND
Rd, Rr
Logical AND Registers
Rd ¬ Rd · Rr
Z,N,V
1
ANDI
Rd, K
Logical AND Register and Constant
Rd ¬ Rd · K
Z,N,V
1
OR
Rd, Rr
Logical OR Registers
Rd ¬ Rd v Rr
Z,N,V
1
1
ORI
Rd, K
Logical OR Register and Constant
Rd ¬ Rd v K
Z,N,V
EOR
Rd, Rr
Exclusive OR Registers
Rd ¬ Rd Å Rr
Z,N,V
1
COM
Rd
One’s Complement
Rd ¬ $FF - Rd
Z,C,N,V
1
NEG
Rd
Two’s Complement
Rd ¬ $00 - Rd
Z,C,N,V,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd ¬ Rd v K
Z,N,V
1
CBR
Rd,K
Clear Bit(s) in Register
Rd ¬ Rd · ($FF - K)
Z,N,V
1
INC
Rd
Increment
Rd ¬ Rd + 1
Z,N,V
1
DEC
Rd
Decrement
Rd ¬ Rd - 1
Z,N,V
1
TST
Rd
Test for Zero or Minus
Rd ¬ Rd · Rd
Z,N,V
1
CLR
Rd
Clear Register
Rd ¬ Rd Å Rd
Z,N,V
1
SER
Rd
Set Register
Rd ¬ $FF
None
1
BRANCH INSTRUCTIONS
RJMP
k
Relative Jump
PC ¬ PC + k + 1
None
2
IJMP
Indirect Jump to (Z)
PC ¬ Z
None
2
Relative Subroutine Call
PC ¬ PC + k + 1
None
3
ICALL
Indirect Call to (Z)
PC ¬ Z
None
3
RET
Subroutine Return
PC ¬ STACK
None
4
RETI
Interrupt Return
PC ¬ STACK
I
RCALL
k
4
CPSE
Rd,Rr
Compare, Skip if Equal
if (Rd = Rr) PC ¬ PC + 2 or 3
None
CP
Rd,Rr
Compare
Rd - Rr
Z, N,V,C,H
1
CPC
Rd,Rr
Compare with Carry
Rd - Rr - C
Z, N,V,C,H
1
CPI
Rd,K
Compare Register with Immediate
Rd - K
Z, N,V,C,H
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b)=0) PC ¬ PC + 2 or 3
None
1/2
SBRS
Rr, b
Skip if Bit in Register is Set
if (Rr(b)=1) PC ¬ PC + 2 or 3
None
1/2
SBIC
Rr, b
Skip if Bit in I/O Register Cleared
if (Rr(b)=0) PC ¬ PC + 2 or 3
None
2/3
SBIS
Rr, b
Skip if Bit in I/O Register is Set
if (Rr(b)=1) PC ¬ PC + 2 or 3
None
2/3
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PC¬PC+k + 1
None
1/2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PC¬PC+k + 1
None
1/2
BREQ
k
Branch if Equal
if (Z = 1) then PC ¬ PC + k + 1
None
1/2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC ¬ PC + k + 1
None
1/2
BRCS
k
Branch if Carry Set
if (C = 1) then PC ¬ PC + k + 1
None
1/2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC ¬ PC + k + 1
None
1/2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC ¬ PC + k + 1
None
1/2
BRLO
k
Branch if Lower
if (C = 1) then PC ¬ PC + k + 1
None
1/2
BRMI
k
Branch if Minus
if (N = 1) then PC ¬ PC + k + 1
None
1/2
BRPL
k
Branch if Plus
if (N = 0) then PC ¬ PC + k + 1
None
1/2
BRGE
k
Branch if Greater or Equal, Signed
if (N Å V= 0) then PC ¬ PC + k + 1
None
1/2
BRLT
k
Branch if Less Than Zero, Signed
if (N Å V= 1) then PC ¬ PC + k + 1
None
1/2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC ¬ PC + k + 1
None
1/2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC ¬ PC + k + 1
None
1/2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC ¬ PC + k + 1
None
1/2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC ¬ PC + k + 1
None
1/2
1/2
1/2
1
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC ¬ PC + k + 1
None
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC ¬ PC + k + 1
None
1/2
BRIE
k
Branch if Interrupt Enabled
if ( I = 1) then PC ¬ PC + k + 1
None
1/2
BRID
k
Branch if Interrupt Disabled
if ( I = 0) then PC ¬ PC + k + 1
None
1/2
(continued)
Preliminary
4-85
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move Between Registers
Rd ¬ Rr
None
1
LDI
Rd, K
Load Immediate
Rd ¬ K
None
1
LD
Rd, X
Load Indirect
Rd ¬ (X)
None
2
LD
Rd, X+
Load Indirect and Post-Inc.
Rd ¬ (X), X ¬ X + 1
None
2
LD
Rd, - X
Load Indirect and Pre-Dec.
X ¬ X - 1, Rd ¬ (X)
None
2
LD
Rd, Y
Load Indirect
Rd ¬ (Y)
None
2
LD
Rd, Y+
Load Indirect and Post-Inc.
Rd ¬ (Y), Y ¬ Y + 1
None
2
LD
Rd, - Y
Load Indirect and Pre-Dec.
Y ¬ Y - 1, Rd ¬ (Y)
None
2
LDD
Rd,Y+q
Load Indirect with Displacement
Rd ¬ (Y + q)
None
2
LD
Rd, Z
Load Indirect
Rd ¬ (Z)
None
2
LD
Rd, Z+
Load Indirect and Post-Inc.
Rd ¬ (Z), Z ¬ Z+1
None
2
LD
Rd, -Z
Load Indirect and Pre-Dec.
Z ¬ Z - 1, Rd ¬ (Z)
None
2
LDD
Rd, Z+q
Load Indirect with Displacement
Rd ¬ (Z + q)
None
2
LDS
Rd, k
Load Direct from SRAM
Rd ¬ (k)
None
3
ST
X, Rr
Store Indirect
(X) ¬ Rr
None
2
ST
X+, Rr
Store Indirect and Post-Inc.
(X) ¬ Rr, X ¬ X + 1
None
2
ST
- X, Rr
Store Indirect and Pre-Dec.
X ¬ X - 1, (X) ¬ Rr
None
2
ST
Y, Rr
Store Indirect
(Y) ¬ Rr
None
2
ST
Y+, Rr
Store Indirect and Post-Inc.
(Y) ¬ Rr, Y ¬ Y + 1
None
2
ST
- Y, Rr
Store Indirect and Pre-Dec.
Y ¬ Y - 1, (Y) ¬ Rr
None
2
STD
Y+q,Rr
Store Indirect with Displacement
(Y + q) ¬ Rr
None
2
ST
Z, Rr
Store Indirect
(Z) ¬ Rr
None
2
ST
Z+, Rr
Store Indirect and Post-Inc.
(Z) ¬ Rr, Z ¬ Z + 1
None
2
ST
-Z, Rr
Store Indirect and Pre-Dec.
Z ¬ Z - 1, (Z) ¬ Rr
None
2
STD
Z+q,Rr
Store Indirect with Displacement
(Z + q) ¬ Rr
None
2
STS
k, Rr
LPM
Store Direct to SRAM
(k) ¬ Rr
None
3
Load Program Memory
R0 ¬ (Z)
None
3
1
IN
Rd, P
In Port
Rd ¬ P
None
OUT
P, Rr
Out Port
P ¬ Rr
None
1
PUSH
Rr
Push Register on Stack
STACK ¬ Rr
None
2
POP
Rd
Pop Register from Stack
Rd ¬ STACK
None
2
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set Bit in I/O Register
I/O(P,b) ¬ 1
N
2
CBI
P,b
Clear Bit in I/O Register
I/O(P,b) ¬ 0
N
2
LSL
Rd
Logical Shift Left
Rd(n+1) ¬ Rd(n), Rd(0) ¬ 0
Z,C,N,V
1
LSR
Rd
Logical Shift Right
Rd(n) ¬ Rd(n+1), Rd(7) ¬ 0
Z,C,N,V
1
ROL
Rd
Rotate Left Through Carry
Rd(0)¬C,Rd(n+1)¬ Rd(n),C¬Rd(7)
Z,C,N,V
1
ROR
Rd
Rotate Right Through Carry
Rd(7)¬C,Rd(n)¬ Rd(n+1),C¬Rd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n) ¬ Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)¬Rd(7..4),Rd(7..4)¬Rd(3..0)
None
1
BSET
s
Flag Set
SREG(s) ¬ 1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s) ¬ 0
SREG(s)
1
BST
Rr, b
Bit Store from Register to T
T ¬ Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b) ¬ T
None
1
SEC
Set Carry
C¬1
C
1
CLC
Clear Carry
C¬0
C
1
SEN
Set Negative Flag
N¬1
N
1
CLN
Clear Negative Flag
N¬0
N
1
SEZ
Set Zero Flag
Z¬1
Z
1
CLZ
Clear Zero Flag
Z¬0
Z
1
SEI
Global Interrupt Enable
I¬1
I
1
CLI
Global Interrupt Disable
I¬0
I
1
SES
Set Signed Test Flag
S¬1
S
1
CLS
Clear Signed Test Flag
S¬0
S
1
SEV
Set Twos Complement Overflow.
V¬1
V
1
CLV
Clear Twos Complement Overflow
V¬0
V
1
SET
Set T in SREG
T¬1
T
1
CLT
Clear T in SREG
T¬0
T
1
SEH
Set Half Carry Flag in SREG
H¬1
H
1
CLH
Clear Half Carry Flag in SREG
H¬0
H
1
NOP
No Operation
SLEEP
Sleep
WDR
Watchdog Reset
4-86
AT90S8414 Preliminary
None
1
(see specific descr. for Sleep function)
None
1
(see specific descr. for WDR/timer)
None
1
AT90S8414
Preliminary
4-87