advertisement
Features
• High-performance, Low-power AVR
®
8-bit Microcontroller
• RISC Architecture
– 118 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
• Data and Non-volatile Program Memory
– 2K Bytes of In-System Programmable Program Memory Flash
Endurance: 10,000 Write/Erase Cycles
– 128 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– 128 Bytes Internal SRAM
– Programming Lock for Flash Program and EEPROM Data Security
• Peripheral Features
– 8-bit Timer/Counter with Separate Prescaler
– 8-bit High-speed Timer with Separate Prescaler
2 High Frequency PWM Outputs with Separate Output Compare Registers
Non-overlapping Inverted PWM Output Pins
– Universal Serial Interface with Start Condition Detector
– 10-bit ADC
11 Single Ended Channels
8 Differential ADC Channels
7 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)
– On-chip Analog Comparator
– External Interrupt
– Pin Change Interrupt on 11 Pins
– Programmable Watchdog Timer with Separate On-chip Oscillator
• Special Microcontroller Features
– Low Power Idle, Noise Reduction, and Power-down Modes
– Power-on Reset and Programmable Brown-out Detection
– External and Internal Interrupt Sources
– In-System Programmable via SPI Port
– Internal Calibrated RC Oscillator
• I/O and Packages
– 20-lead PDIP/SOIC: 16 Programmable I/O Lines
– 32-lead QFN/MLF: 16 programmable I/O Lines
• Operating Voltages
– 2.7V - 5.5V for ATtiny26L
– 4.5V - 5.5V for ATtiny26
• Speed Grades
– 0 - 8 MHz for ATtiny26L
– 0 - 16 MHz for ATtiny26
• Power Consumption at 1 MHz, 3V and 25
°
C for ATtiny26L
– Active 16 MHz, 5V and 25
°
C: Typ 15 mA
– Active 1 MHz, 3V and 25
°
C: 0.70 mA
– Idle Mode 1 MHz, 3V and 25
°
C: 0.18 mA
– Power-down Mode: < 1 µA
8-bit
Microcontroller with 2K Bytes
Flash
ATtiny26
ATtiny26L
Pin Configuration
(MOSI/DI/SDA/OC1A) PB0
(MISO/DO/OC1A) PB1
(SCK/SCL/OC1B) PB2
(OC1B) PB3
VCC
GND
(ADC7/XTAL1) PB4
(ADC8/XTAL2) PB5
(ADC9/INT0/T0) PB6
(ADC10/RESET) PB7
PDIP/SOIC
7
8
5
6
3
4
1
2
9
10
16
15
14
13
20
19
18
17
12
11
PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (AREF)
GND
AVCC
PA4 (ADC3)
PA5 (ADC4)
PA6 (ADC5/AIN0)
PA7 (ADC6/AIN1)
MLF Top View
NC
(OC1B) PB3
NC
VCC
GND
NC
(ADC7/XTAL1) PB4
(ADC8/XTAL2) PB5
7
8
5
6
3
4
1
2
24
23
22
21
20
19
18
17
NC
PA2 (ADC2)
PA3 (AREF)
GND
NC
NC
AVCC
PA4 (ADC3)
2
ATtiny26(L)
Note: Note: The bottom pad under the QFN/MLF package should be soldered to ground.
1477G–AVR–03/05
Description
ATtiny26(L)
The ATtiny26(L) is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny26(L) achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny26(L) has a high precision ADC with up to 11 single ended channels and 8 differential channels. Seven differential channels have an optional gain of 20x. Four out of the seven differential channels, which have the optional gain, can be used at the same time. The ATtiny26(L) also has a high frequency 8-bit PWM module with two independent outputs. Two of the
PWM outputs have inverted non-overlapping output pins ideal for synchronous rectification. The Universal Serial Interface of the ATtiny26(L) allows efficient software implementation of TWI (Two-wire Serial Interface) or SM-bus interface. These features allow for highly integrated battery charger and lighting ballast applications, low-end thermostats, and firedetectors, among other applications.
The ATtiny26(L) provides 2K bytes of Flash, 128 bytes EEPROM, 128 bytes SRAM, up to 16 general purpose I/O lines, 32 general purpose working registers, two 8-bit
Timer/Counters, one with PWM outputs, internal and external Oscillators, internal and external interrupts, programmable Watchdog Timer, 11-channel, 10-bit Analog to Digital
Converter with two differential voltage input gain stages, and four software selectable power saving modes. The Idle mode stops the CPU while allowing the Timer/Counters and interrupt system to continue functioning. The ATtiny26(L) also has a dedicated ADC
Noise Reduction mode for reducing the noise in ADC conversion. In this sleep mode, only the ADC is functioning. The Power-down mode saves the register contents but freezes the oscillators, disabling all other chip functions until the next interrupt or hardware reset. The Standby mode is the same as the Power-down mode, but external oscillators are enabled. The wakeup or interrupt on pin change features enable the
ATtiny26(L) to be highly responsive to external events, still featuring the lowest power consumption while in the Power-down mode.
The device is manufactured using Atmel’s high density non-volatile memory technology.
By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the
ATtiny26(L) is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
The ATtiny26(L) AVR is supported with a full suite of program and system development tools including: Macro assemblers, program debugger/simulators, In-circuit emulators, and evaluation kits.
3
1477G–AVR–03/05
Block Diagram
Figure 1. The ATtiny26(L) Block Diagram
VCC
8-BIT DATA BUS
INTERNAL
OSCILLATOR
GND
PROGRAM
COUNTER
PROGRAM
FLASH
STACK
POINTER
SRAM
WATCHDOG
TIMER
MCU CONTROL
REGISTER
AVCC
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
GENERAL
PURPOSE
REGISTERS
X
Y
Z
MCU STATUS
REGISTER
TIMER/
COUNTER0
TIMER/
COUNTER1
CONTROL
LINES
ALU
UNIVERSAL
SERIAL
INTERFACE
STATUS
REGISTER
INTERRUPT
UNIT
PROGRAMMING
LOGIC
ISP INTERFACE EEPROM
INTERNAL
CALIBRATED
OSCILLATOR
TIMING AND
CONTROL
OSCILLATORS
DATA REGISTER
PORT A
DATA DIR.
REG.PORT A
ADC DATA REGISTER
PORT B
DATA DIR.
REG.PORT B
PORT A DRIVERS PORT B DRIVERS
PA0-PA7 PB0-PB7
4
ATtiny26(L)
1477G–AVR–03/05
Pin Descriptions
VCC
GND
AVCC
Port A (PA7..PA0)
Port B (PB7..PB0)
XTAL1
XTAL2
About Code
Examples
ATtiny26(L)
Digital supply voltage pin.
Digital ground pin.
AVCC is the supply voltage pin for Port A and the A/D Converter (ADC). It should be externally connected to V
CC
, even if the ADC is not used. If the ADC is used, it should be connected to V
CC
through a low-pass filter. See page 94 for details on operating of the
ADC.
Port A is an 8-bit general purpose I/O port. PA7..PA0 are all I/O pins that can provide internal pull-ups (selected for each bit). Port A has alternate functions as analog inputs
for the ADC and analog comparator and pin change interrupt as described in “Alternate
Port B is an 8-bit general purpose I/O port. PB6..0 are all I/O pins that can provide internal pull-ups (selected for each bit). PB7 is an I/O pin if not used as the reset. To use pin
PB7 as an I/O pin, instead of RESET pin, program (“0”) RSTDISBL Fuse. Port B has alternate functions for the ADC, clocking, timer counters, USI, SPI programming, and
pin change interrupt as described in “Alternate Port Functions” on page 46.
An External Reset is generated by a low level on the PB7/RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting oscillator amplifier.
This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
5
1477G–AVR–03/05
AVR CPU Core
Architectural Overview
The fast-access Register File concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the Register File, the operation is executed, and the result is stored back in the
Register File – in one clock cycle.
Six of the 32 registers can be used as 16-bit pointers for indirect memory access. These pointers are called the X-, Y-, and Z-pointers, and they can address the Register File and the Flash program memory.
Figure 2. The ATtiny26(L) AVR Enhanced RISC Architecture
8-bit Data Bus
Control
Registers
1024 x 16
Program
FLASH
Program
Counter
Status and Test
Interrupt
Unit
Instruction
Register
32 x 8
General
Purpose
Registers
Universal
Serial Interface
ISP Unit
Instruction
Decoder
2 x 8-bit
Timer/Counter
ALU
Control Lines
Watchdog
Timer
128 x 8
SRAM
128 byte
EEPROM
ADC
Analog
Comparator
I/O Lines
6
ATtiny26(L)
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 2 shows the ATtiny26(L) AVR Enhanced RISC microcontroller architecture. In addition to the register operation, the conventional memory addressing modes can be used on the
Register File as well. This is enabled by the fact that the Register File is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control
Registers, Timer/Counters, A/D Converters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register
File, $20 - $5F.
1477G–AVR–03/05
General Purpose
Register File
ATtiny26(L)
The AVR uses a Harvard architecture concept with separate memories and buses for program and data memories. The program memory is accessed with a two stage pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System programmable Flash memory.
With the relative jump and relative call instructions, the whole address space is directly accessed. All AVR instructions have a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The 8-bit Stack Pointer SP is read/write accessible in the I/O space. For programs written in C, the stack size must be declared in the linker file. Refer to the C user guide for more information.
The 128 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control
Registers, Timer/Counters, and other I/O functions. The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional
Global Interrupt Enable bit in the Status Register. All the different interrupts have a separate Interrupt Vector in the Interrupt Vector table at the beginning of the program memory. The different interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.
Figure 3 shows the structure of the 32 general purpose working registers in the CPU.
Figure 3. AVR CPU General Purpose Working Registers
General
Purpose
Working
Registers
7
R27
R28
R29
R30
R31
R16
R17
…
R26
…
R13
R14
R15
0 Addr.
R0 $00
R1
R2
$01
$02
$0D
$0E
$0F
$10
$11
$1A
$1B
$1C
$1D
$1E
$1F
X-register Low Byte
X-register High Byte
Y-register Low Byte
Y-register High Byte
Z-register Low Byte
Z-register High Byte
7
1477G–AVR–03/05
X-register, Y-register, and Zregister
All of the register operating instructions in the instruction set have direct and single cycle access to all registers. The only exceptions are the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a register, and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the Register File – R16..R31. The general SBC, SUB, CP,
AND, and OR, and all other operations between two registers or on a single register apply to the entire Register File.
As shown in Figure 3, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any register in the file.
The registers R26..R31 have some added functions to their general purpose usage.
These registers are address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as:
Figure 4. X-, Y-, and Z-register
X-register
15
7
R27 ($1B)
0 7
R26 ($1A)
0
0
Y-register
15
7
R29 ($1D)
0 7
R28 ($1C)
0
0
Z-register
15
7
R31 ($1F)
0 7
R30 ($1E)
0
0
In the different addressing modes, these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different instructions).
ALU – Arithmetic Logic
Unit
The high-performance AVR ALU operates in direct connection with all 32 general purpose working registers. Within a single clock cycle, ALU operations between registers in the Register File are executed. The ALU operations are divided into three main categories – Arithmetic, Logical, and Bit-functions.
8
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
Status Register – SREG
The AVR Status Register – SREG – at I/O space location $3F is defined as:
Bit
$3F ($5F)
Read/Write
Initial Value
7
I
R/W
0
6
T
R/W
0
5
H
R/W
0
4
S
R/W
0
3
V
R/W
0
2
N
R/W
0
1
Z
R/W
0
0
C
R/W
0
SREG
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in the Interrupt Mask Registers –
GIMSK and TIMSK. If the Global Interrupt Enable Register is cleared (zero), none of the interrupts are enabled independent of the GIMSK and TIMSK values. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the
SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source and destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the
Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. See the
Instruction Set Description for detailed information.
• Bit 4 – S: Sign Bit, S = N
⊕
V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the Instruction Set Description for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction
Set Description for detailed information.
9
1477G–AVR–03/05
Stack Pointer – SP
Program and Data
Addressing Modes
Register Direct, Single
Register Rd
The ATtiny26(L) Stack Pointer is implemented as an 8-bit register in the I/O space location $3D ($5D). As the ATtiny26(L) data memory has 224 ($E0) locations, eight bits are used.
Bit
$3D ($5D)
Read/Write
Initial Value
7
SP7
R/W
0
6
SP6
R/W
0
5
SP5
R/W
0
4
SP4
R/W
0
3
SP3
R/W
0
2
SP2
R/W
0
1
SP1
R/W
0
0
SP0
R/W
0
SP
The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack
Pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The
Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt RETI.
The ATtiny26(L) AVR Enhanced RISC microcontroller supports powerful and efficient addressing modes for access to the Flash program memory, SRAM, Register File, and
I/O Data memory. This section describes the different addressing modes supported by the AVR architecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits.
Figure 5. Direct Single Register Addressing
The operand is contained in register d (Rd).
10
ATtiny26(L)
1477G–AVR–03/05
Register Direct, Two Registers
Rd and Rr
Figure 6. Direct Register Addressing, Two Registers
ATtiny26(L)
I/O Direct
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d
(Rd).
Figure 7. I/O Direct Addressing
Data Direct
1477G–AVR–03/05
Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.
Figure 8. Direct Data Addressing
Data Space
31 $0000
15
OP
20 19
Rr/Rd
16
16 LSBs
0
$00DF
11
Data Indirect with
Displacement
Data Indirect
A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register.
Figure 9. Data Indirect with Displacement
Data Space
$0000
15 0
Y OR Z - REGISTER
15
OP
10 n
6 5 a
0
$00DF
Operand address is the result of the Y- or Z-register contents added to the address contained in 6 bits of the instruction word.
Figure 10. Data Indirect Addressing
Data Space
$0000
15 0
X-, Y-, OR Z-REGISTER
Data Indirect with Predecrement
$00DF
Operand address is the contents of the X-, Y-, or the Z-register.
Figure 11. Data Indirect Addressing with Pre-decrement
Data Space
15 0
X-, Y-, OR Z-REGISTER
$0000
-1
$00DF
12
ATtiny26(L)
1477G–AVR–03/05
Data Indirect with Postincrement
ATtiny26(L)
The X-, Y-, or Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y-, or Z-register.
Figure 12. Data Indirect Addressing with Post-increment
Data Space
$0000
15 0
X-, Y-, OR Z-REGISTER
1
Constant Addressing Using the LPM Instruction
$00DF
The X-, Y-, or Z-register is incremented after the operation. Operand address is the content of the X-, Y-, or Z-register prior to incrementing.
Figure 13. Code Memory Constant Addressing
PROGRAM MEMORY
$000
$3FF
Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 1K), the LSB selects low byte if cleared (LSB = 0) or high byte if set
(LSB = 1).
13
1477G–AVR–03/05
Indirect Program Addressing,
IJMP and ICALL
Figure 14. Indirect Program Memory Addressing
PROGRAM MEMORY
$000
$3FF
Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register).
Relative Program Addressing,
RJMP and RCALL
Figure 15. Relative Program Memory Addressing
PROGRAM MEMORY
$000
+1
$3FF
Program execution continues at address PC + k + 1. The relative address k is from
-2048 to 2047.
14
ATtiny26(L)
1477G–AVR–03/05
Memories
ATtiny26(L)
The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the chip. No internal clock division is used.
Figure 16 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 16. The Parallel Instruction Fetches and Instruction Executions
T1 T2 T3 T4
System Clock Ø
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 17 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.
Figure 17. Single Cycle ALU Operation
T1 T2 T3 T4
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
The internal data SRAM access is performed in two System Clock cycles as described in Figure 18.
15
1477G–AVR–03/05
Figure 18. On-chip Data SRAM Access Cycles
T1 T2
System Clock Ø
Address
Data
WR
Data
RD
Prev. Address Address
T3 T4
In-System Programmable
Flash Program Memory
The ATtiny26(L) contains 2K bytes On-chip In-System Programmable Flash memory for program storage. Since all instructions are 16- or 32-bit words, the Flash is organized as
1K x 16. The Flash memory has an endurance of at least 10,000 write/erase cycles. The
ATtiny26(L) Program Counter – PC – is 10 bits wide, thus addressing the 1024 program
memory addresses, see “Memory Programming” on page 107 for a detailed description
on Flash data downloading. See “Program and Data Addressing Modes” on page 10 for
the different program memory addressing modes.
Figure 19. SRAM Organization
Register File
R0
R1
R2
...
Data Address Space
$0000
$0001
$0002
...
R29
R30
R31
I/O Registers
$00
$01
$02
…
$3D
$3E
$3F
$001D
$001E
$001F
$0020
$0021
$0022
…
$005D
$005E
$005F
Internal SRAM
$0060
$0061
...
$00DE
$00DF
SRAM Data Memory
Figure 19 above shows how the ATtiny26(L) SRAM Memory is organized.
The lower 224 Data Memory locations address the Register File, the I/O Memory and the internal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next 128 locations address the internal data SRAM.
16
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space. The Indirect with Displacement mode features a 63 address locations reach from the base address given by the Y- or Zregister.
When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented and incremented.
The 32 general purpose working registers, 64 I/O Registers and the 128 bytes of internal data SRAM in the ATtiny26(L) are all accessible through all these addressing modes.
See “Program and Data Addressing Modes” on page 10 for a detailed description of the
different addressing modes.
EEPROM Data Memory
The ATtiny26(L) contains 128 bytes of data EEPROM memory. It is organized as a sep-
arate data space, in which single bytes can be read and written (see “Memory
Programming” on page 107). The EEPROM has an endurance of at least 100,000
write/erase cycles per location.
EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space.
The write access time is typically 8.3 ms. A self-timing function lets the user software detect when the next byte can be written. A special EEPROM Ready Interrupt can be set to trigger when the EEPROM is ready to accept new data.
An ongoing EEPROM write operation will complete even if a reset condition occurs.
In order to prevent unintentional EEPROM writes, a two state write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed.
EEPROM Address Register –
EEAR Bit
$1E ($3E)
Read/Write
Initial Value
R
0
7
–
6
EEAR6
R/W
X
5
EEAR5
R/W
X
4
EEAR4
R/W
X
3
EEAR3
R/W
X
2
EEAR2
R/W
X
1
EEAR1
R/W
X
0
EEAR0
R/W
X
EEAR
• Bit 7 – RES: Reserved Bits
This bit are reserved bit in the ATtiny26(L) and will always read as zero.
• Bit 6..0 – EEAR6..0: EEPROM Address
The EEPROM Address Register – EEAR – specifies the EEPROM address in the 128 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
127. The initial value of EEAR is undefined. A proper value must be written before the
EEPROM may be accessed.
17
1477G–AVR–03/05
EEPROM Data Register –
EEDR Bit
$1D ($3D)
Read/Write
Initial Value
7
MSB
R/W
0
6
R/W
0
5
R/W
0
4
R/W
0
3
R/W
0
2
R/W
0
1
R/W
0
0
LSB
R/W
0
EEDR
• Bit 7..0 – EEDR7..0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by
EEAR.
EEPROM Control Register –
EECR Bit
$1C ($3C)
Read/Write
Initial Value
R
0
7
–
R
0
6
–
R
0
5
–
R
0
4
–
3
EERIE
R/W
0
2
EEMWE
R/W
0
1
EEWE
R/W
0
0
EERE
R/W
0
EECR
• Bit 7..4 – RES: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and will always read as zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared (zero).
• Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles.
See the description of the EEWE bit for an EEPROM write procedure.
• Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal – EEWE – is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value in to the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential):
1.
Wait until EEWE becomes zero.
2.
Write new EEPROM address to EEAR (optional).
3.
Write new EEPROM data to EEDR (optional).
4.
Write a logical one to the EEMWE bit in EECR.
5.
Within four clock cycles after setting EEMWE, write a logical one to EEWE.
Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the
EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.
When the access time (typically 8.3 ms) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed.
18
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be set. When the
EERE bit is cleared (zero) by hardware, requested data is found in the EEDR Register.
The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O Registers, the write operation will be interrupted, and the result is undefined.
Table 1. EEPROM Programming Time
Symbol
EEPROM Write (from CPU)
Number of Calibrated RC
Oscillator Cycles
(1)
8448
Note: 1. Uses 1 MHz clock, independent of CKSEL-Fuse settings.
Typical Programming
Time
8.5 ms
EEPROM Write During Powerdown Sleep Mode
When entering Power-down sleep mode while an EEPROM write operation is active, the
EEPROM write operation will continue, and will complete before the write access time has passed. However, when the write operation is completed, the crystal Oscillator continues running, and as a consequence, the device does not enter Power-down entirely.
It is therefore recommended to verify that the EEPROM write operation is completed before entering Power-down.
Preventing EEPROM
Corruption
During periods of low V
CC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using the EEPROM, and the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low.
EEPROM data corruption can easily be avoided by following these design recommendations (one is sufficient):
1.
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not, an external Brown-out
Reset Protection circuit can be applied.
2.
Keep the AVR core in Power-down Sleep mode during periods of low V
CC
. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the EEPROM Registers from unintentional writes.
Store constants in Flash memory if the ability to change memory contents from software is not required. Flash memory can not be updated by the CPU, and will not be subject to corruption.
19
1477G–AVR–03/05
I/O Memory
20
ATtiny26(L)
The I/O space definition of the ATtiny26(L) is shown in Table 2
Table 2. ATtiny26(L) I/O Space
(1)
Address Hex Name Function
$2B ($4B)
$29 ($29)
$21 ($41)
$1E ($3E)
$1D ($3D)
$1C ($3C)
$1B ($3B)
$1A ($3A)
$19 ($39)
$18 ($38)
$17 ($37)
$16 ($36)
$0F ($2F)
$0E ($2E)
$0D ($2D)
$08 ($28)
$07 ($27)
$3F ($5F)
$3D ($5D)
$3B ($5B)
$3A ($5A)
$39 ($59)
$38 ($58)
$35 ($55)
$34 ($54)
$33 ($53)
$32 ($52)
$31 ($51)
$30 ($50)
$2F ($4F)
$2E ($4E)
$2D ($4D)
$2C ($4C)
SREG
SP
GIMSK
GIFR
Status Register
Stack Pointer
General Interrupt Mask Register
General Interrupt Flag Register
TIMSK
TIFR
Timer/Counter Interrupt Mask Register
Timer/Counter Interrupt Flag Register
MCUCR MCU Control Register
MCUSR MCU Status Register
TCCR0 Timer/Counter0 Control Register
TCNT0 Timer/Counter0 (8-bit)
OSCCAL Oscillator Calibration Register
TCCR1A Timer/Counter1 Control Register A
TCCR1B Timer/Counter1 Control Register B
TCNT1 Timer/Counter1 (8-bit)
OCR1A Timer/Counter1 Output Compare Register A
OCR1B Timer/Counter1 Output Compare Register B
OCR1C Timer/Counter1 Output Compare Register C
PLLCSR PLL Control and Status Register
WDTCR Watchdog Timer Control Register
EEAR EEPROM Address Register
EEDR
EECR
EEPROM Data Register
EEPROM Control Register
PORTA Data Register, Port A
DDRA Data Direction Register, Port A
PINA Input Pins, Port A
PORTB Data Register, Port B
DDRB
PINB
Data Direction Register, Port B
Input Pins, Port B
USIDR
USISR
USICR
ACSR
Universal Serial Interface Data Register
Universal Serial Interface Status Register
Universal Serial Interface Control Register
Analog Comparator Control and Status Register
ADMUX ADC Multiplexer Select Register
1477G–AVR–03/05
ATtiny26(L)
Table 2. ATtiny26(L) I/O Space
(1)
(Continued)
Address Hex Name Function
$06($26)
$05($25)
ADCSR ADC Control and Status Register
ADCH ADC Data Register High
$04($24) ADCL ADC Data Register Low
Note: 1. Reserved and unused locations are not shown in the table.
All ATtiny26(L) I/O and peripheral registers are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set chapter for more details. For compatibility with future devices, reserved bits should be written zero if accessed. Reserved I/O memory addresses should never be written.
1477G–AVR–03/05
21
System Clock and
Clock Options
Clock Systems and their
Distribution
Figure 20 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as
described in “Power Management and Sleep Modes” on page 36. The clock systems
are detailed below.
Figure 20. Clock Distribution
Timer/Counter1
General I/O modules
ADC CPU Core RAM
Flash and
EEPROM
CPU Clock – clk
CPU
I/O Clock – clk
I/O
Flash Clock – clk
FLASH
ADC Clock – clk
ADC clk
I/O clk
ADC
AVR Clock
Control Unit clk
CPU clk
FLASH
Reset Logic
Clock
Source clock
Multiplexer
Watchdog Timer
Watchdog clock
Watchdog
Oscillator clk
PCK clk
PLL
PLL
External RC
Oscillator
External clock
Crystal
Oscillator
Low-Frequency
Crystal Oscillator
Calibrated RC
Oscillator
The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, and USI.
The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock.
The ADC is provided with a dedicated clock domain. This allows halting the CPU and
I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.
22
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
Internal PLL for Fast
Peripheral Clock Generation – clk
PCK
The internal PLL in ATtiny26(L) generates a clock frequency that is 64x multiplied from nominally 1 MHz input. The source of the 1 MHz PLL input clock is the output of the internal RC Oscillator which is automatically divided down to 1 MHz, if needed. See the
Figure 21 on page 23. When the PLL reference frequency is the nominal 1 MHz, the fast peripheral clock is 64 MHz. The fast peripheral clock, or a clock prescaled from that, can be selected as the clock source for Timer/Counter1.
The PLL is locked on the RC Oscillator and adjusting the RC Oscillator via OSCCAL
Register will adjust the fast peripheral clock at the same time. However, even if the possibly divided RC Oscillator is taken to a higher frequency than 1 MHz, the fast peripheral clock frequency saturates at 70 MHz (worst case) and remains oscillating at the maximum frequency. It should be noted that the PLL in this case is not locked any more with the RC Oscillator clock.
Therefore it is recommended not to take the OSCCAL adjustments to a higher frequency than 1 MHz in order to keep the PLL in the correct operating range. The internal
PLL is enabled only when the PLLE bit in the register PLLCSR is set or the PLLCK Fuse is programmed (“0”). The bit PLOCK from the register PLLCSR is set when PLL is locked.
Both internal 1 MHz RC Oscillator and PLL are switched off in Power-down and Standby sleep modes.
Figure 21. PCK Clocking System
PLLE
PLLCK &
CKSEL
FUSES
OSCCAL
Lock
Detector
PLOCK
RC OSCILLATOR
1
2
4
8 MHz
DIVIDE
TO 1 MHz
PLL
64x
PCK
DIVIDE
BY 4
CK
XTAL1
XTAL2
OSCILLATORS
23
1477G–AVR–03/05
Clock Sources
24
ATtiny26(L)
The device has the following clock source options, selectable by Flash Fuse bits as
shown below on Table 3. The clock from the selected source is input to the AVR clock
generator, and routed to the appropriate modules.The use of pins PB5 (XTAL2), and
PB4 (XTAL1) as I/O pins is limited depending on clock settings, as shown below in
Table 3. Device Clocking Options Select
Device Clocking Option
External Crystal/Ceramic Resonator
External Low-frequency Crystal
External RC Oscillator
Calibrated Internal RC Oscillator
External Clock
PLL Clock
PLLCK
1
1
1
0
1
1
CKSEL3..0
1111 - 1010
1001
1000 - 0101
0100 - 0001
0000
0001
Table 4. PB5, and PB4 Functionality vs. Device Clocking Options
(1)
Device Clocking Option
External Clock
PLLCK
1
CKSEL [3:0]
0000
PB4
XTAL1
Internal RC Oscillator
Internal RC Oscillator
Internal RC Oscillator
Internal RC Oscillator
External RC Oscillator
External RC Oscillator
External RC Oscillator
External RC Oscillator
External Low-frequency Oscillator
External Crystal/Resonator Oscillator
External Crystal/Resonator Oscillator
External Crystal/Resonator Oscillator
External Crystal/Resonator Oscillator
External Crystal/Resonator Oscillator
External Crystal/Resonator Oscillator
PLL
1001
1010
1011
1100
1101
1110
1111
0001
0001
0010
0011
0100
0101
0110
0111
1000
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
XTAL1
XTAL1
XTAL1
XTAL1
XTAL1
XTAL1
XTAL1
I/O
I/O
I/O
I/O
I/O
XTAL1
XTAL1
XTAL1
XTAL1
I/O
I/O
XTAL2
XTAL2
XTAL2
XTAL2
XTAL2
XTAL2
XTAL2
I/O
I/O
I/O
I/O
I/O
PB5
I/O
I/O
I/O
Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.
The various choices for each clocking option is given in the following sections. When the
CPU wakes up from Power-down, the selected clock source is used to time the start-up, ensuring stable oscillator operation before instruction execution starts. When the CPU starts from Reset, there is as an additional delay allowing the power to reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for
1477G–AVR–03/05
Default Clock Source
Crystal Oscillator
ATtiny26(L)
each time-out is shown in Table 5. The frequency of the Watchdog Oscillator is voltage
dependent as shown in the Electrical Characteristics section.
Table 5. Number of Watchdog Oscillator Cycles
Typ Time-out (V
CC
= 5.0V)
4.1 ms
65 ms
Typ Time-out (V
CC
= 3.0V)
4.3 ms
69 ms
Number of Cycles
4K (4,096)
64K (65,536)
The deviced is shipped with CKSEL = “0001”, SUT = “10”, and PLLCK unprogrammed.
The default clock source setting is therefore the internal RC Oscillator with longest startup time. This default setting ensures that all users can make their desired clock source setting using an In-System or Parallel Programmer.
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 22. Either a quartz crystal or a ceramic resonator may be used. The maximum frequency for resonators is
12 MHz. The CKOPT Fuse should always be unprogrammed when using this clock option. C1 and C2 should always be equal. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use
with crystals are given in Table 6. For ceramic resonators, the capacitor values given by
the manufacturer should be used.
Figure 22. Crystal Oscillator Connections
C2
XTAL2
C1
XTAL1
GND
The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in
Table 6. Crystal Oscillator Operating Modes
Frequency
Range (MHz)
Recommended Range for Capacitors C1 and
C2 for Use with Crystals (pF) CKSEL3..1
101
(1)
110
0.4 - 0.9
0.9 - 3.0
–
12 - 22
111
3.0 - 16
16 -
12 - 22
12 - 15
Note: 1. This option should not be used with crystals, only with ceramic resonators.
25
1477G–AVR–03/05
Low-frequency Crystal
Oscillator
The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown
Table 7. Start-up Times for the Crystal Oscillator Clock Selection
CKSEL0 SUT1..0
0 00
Start-up Time from Power-down
258 CK (1)
Additional Delay from
Reset (V
CC
= 5.0V)
4.1 ms
0
0
0
1
1
1
1
01
10
11
00
01
10
11
258 CK (1)
1K CK (2)
1K CK (2)
1K CK (2)
16K CK
16K CK
16K CK
65 ms
–
4.1 ms
65 ms
–
4.1 ms
65 ms
Recommended
Usage
Ceramic resonator, fast rising power
Ceramic resonator, slowly rising power
Ceramic resonator,
BOD enabled
Ceramic resonator, fast rising power
Ceramic resonator, slowly rising power
Crystal Oscillator,
BOD enabled
Crystal Oscillator, fast rising power
Crystal Oscillator, slowly rising power
Notes: 1. These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application.
2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application.
To use a 32.768 kHz watch crystal as the clock source for the device, the Low-frequency Crystal Oscillator must be selected by setting the PLLCK to “1” and CKSEL
Fuses to “1001”. The crystal should be connected as shown in Figure 22. By programming the CKOPT Fuse, the user can enable internal capacitors on XTAL1 and XTAL2, thereby removing the need for external capacitors. The internal capacitors have a nominal value of 36 pF.
When this oscillator is selected, start-up times are determined by the SUT Fuses as
Table 8. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection
SUT1..0
00
01
Start-up Time from Power-down
1K CK
(1)
1K CK (1)
Additional Delay from
Reset (V
CC
= 5.0V)
4.1 ms
65 ms
Recommended Usage
Fast rising power or BOD enabled
Slowly rising power
10
11
32K CK 65 ms
Reserved
Stable frequency at start-up
Note: 1. These options should only be used if frequency stability at start-up is not important for the application.
26
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
External RC Oscillator
For timing insensitive applications, the external RC configuration shown in Figure 23 can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22 pF. By programming the CKOPT Fuse, the user can enable an internal
36 pF capacitor between XTAL1 and GND, thereby removing the need for an external capacitor.
Figure 23. External RC Configuration
V
CC
PB5 (XTAL2)
R
XTAL1
C
GND
The oscillator can operate in four different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..0 as shown in
Table 9. External RC Oscillator Operating Modes
CKSEL3..0
0101
0110
0111
1000
Frequency Range (MHz)
0.1 - 0.9
0.9 - 3.0
3.0 - 8.0
8.0 - 12.0
When this oscillator is selected, start-up times are determined by the SUT Fuses as
Table 10. Start-up Times for the External RC Oscillator Clock Selection
SUT1..0
00
01
Start-up Time from Power-down
18 CK
18 CK
Additional Delay from
Reset (V
CC
= 5.0V)
–
4.1 ms
Recommended Usage
BOD enabled
Fast rising power
10
11
18 CK
6 CK (1)
65 ms
4.1 ms
Slowly rising power
Fast rising power or BOD enabled
Notes: 1. This option should not be used when operating close to the maximum frequency of the device.
27
1477G–AVR–03/05
Calibrated Internal RC
Oscillator
The calibrated internal RC Oscillator provides a fixed 1.0, 2.0, 4.0, or 8.0 MHz clock. All frequencies are nominal values at 5V and 25
°
C. This clock may be selected as the sys-
tem clock by programming the CKSEL Fuses as shown in Table 11. If selected, it will
operate with no external components. The CKOPT Fuse should always be unprogrammed when using this clock option. During Reset, hardware loads the calibration byte into the OSCCAL Register and thereby automatically calibrates the RC Oscillator.
At 5V, 25
°
C and 1.0 MHz Oscillator frequency selected, this calibration gives a frequency within ± 3% of the nominal frequency. Using run-time calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve ±
1% accuracy at any given V
CC
and Temperature. When this oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the reset time-out. For more information on the pre-programmed calibration value, see the section
“Calibration Byte” on page 109.
Table 11. Internal Calibrated RC Oscillator Operating Modes
CKSEL3..0
0001 (1)
Nominal Frequency (MHz)
1.0
0010
0011
0100
2.0
4.0
8.0
Note: 1. The device is shipped with this option selected.
When this oscillator is selected, start-up times are determined by the SUT Fuses as
shown in Table 12. PB4 (XTAL1) and PB5 (XTAL2) can be used as general I/O ports.
Table 12. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection
SUT1..0
00
01
10
(1)
11
Start-up Time from
Power-down
6 CK
6 CK
6 CK
Additional Delay from
Reset (V
CC
= 5.0V)
–
4.1 ms
65 ms
Reserved
Recommended Usage
BOD enabled
Fast rising power
Slowly rising power
Note: 1. The device is shipped with this option selected.
Oscillator Calibration Register
– OSCCAL Bit
$31 ($51)
Read/Write
Initial Value
7
CAL7
R/W
6
CAL6
R/W
5
CAL5
4
CAL4
3
CAL3
2
CAL2
R/W R/W R/W R/W
Device Specific Calibration Value
1
CAL1
R/W
0
CAL0
R/W
OSCCAL
• Bits 7..0 – CAL7..0: Oscillator Calibration Value
Writing the calibration byte to this address will trim the internal oscillator to remove process variations from the oscillator frequency. During Reset, the 1 MHz calibration value which is located in the signature row high byte (address 0x00) is automatically loaded into the OSCCAL Register. If the internal RC is used at other frequencies, the calibration value must be loaded manually. This can be done by first reading the signature row by a programmer, and then store the calibration values in the Flash or EEPROM. Then the value can be read by software and loaded into the OSCCAl Register. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register
28
ATtiny26(L)
1477G–AVR–03/05
External Clock
ATtiny26(L) will increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated Oscillator is used to time EEPROM and
Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the oscillator is intended for calibration to 1.0, 2.0, 4.0, or 8.0 MHz. Tuning to other values is
not guaranteed, as indicated in Table 13.
Table 13. Internal RC Oscillator Frequency Range.
OSCCAL Value
$00
Min Frequency in Percentage of
Nominal Frequency
50%
$7F
$FF
75%
100%
Max Frequency in Percentage of
Nominal Frequency
100%
150%
200%
To drive the device from an external clock source, XTAL1 should be driven as shown in
Figure 24. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000” and PLLCK to “1”. By programming the CKOPT Fuse, the user can enable an internal 36 pF capacitor between XTAL1 and GND.
Figure 24. External Clock Drive Configuration
PB5 (XTAL2)
EXTERNAL
CLOCK
SIGNAL
XTAL1
GND
When this clock source is selected, start-up times are determined by the SUT Fuses as
Table 14. Start-up Times for the External Clock Selection
SUT1..0
00
01
Start-up Time from
Power-down
6 CK
6 CK
Additional Delay from
Reset (V
CC
= 5.0V)
–
4.1 ms
10
11
6 CK 65 ms
Reserved
Recommended Usage
BOD enabled
Fast rising power
Slowly rising power
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behaviour. It is required to ensure that the MCU is kept in reset during such changes in the clock frequency.
29
1477G–AVR–03/05
High Frequency PLL
Clock – PLL
CLK
There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC
Oscillator for the use of the Peripheral Timer/Counter1 and for the system clock source.
When selected as a system clock source, by programming (“0”) the fuse PLLCK, it is divided by four. When this option is used, the CKSEL3..0 must be set to “0001”. This clocking option can be used only when operating between 4.5 - 5.5V to guaratee safe operation. The system clock frequency will be 16 MHz (64 MHz/4). When using this
clock option, start-up times are determined by the SUT Fuses as shown in Table 15.
See also “PCK Clocking System” on page 23.
Table 15. Start-up Times for the PLLCK
SUT1..0
00
Start-up Time from
Power-down
1K CK
Additional Delay from
Reset (V
CC
= 5.0V)
–
01
10
11
1K CK
1K CK
16K CK
4.1 ms
65 ms
–
Recommended Usage
BOD enabled
Fast rising power
Slowly rising power
Slowly rising power
30
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
System Control and
Reset
The ATtiny26(L) provides four sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V
POT
).
• External Reset. To use the PB7/RESET pin as an External Reset, instead of I/O pin, unprogram (“1”) the RSTDISBL Fuse. The MCU is reset when a low level is present on the
RESET pin for more than 50 ns.
• Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the
Watchdog is enabled.
• Brown-out Reset. The MCU is reset when the supply voltage V
CC
is below the Brown-out
Reset threshold (V
BOT
).
During reset, all I/O Registers are then set to their initial values, and the program starts execution from address $000. The instruction placed in address $000 must be an RJMP
– Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. Figure 25 shows the reset logic for the ATtiny26(L). Table 16 shows the timing and electrical parameters of the reset circuitry for ATtiny26(L).
Figure 25. Reset Logic for the ATtiny26(L)
DATA BUS
MCU Status
Register (MCUSR)
BODEN
BODLEVEL
Brown-Out
Reset Circuit
Clock
Generator
CK
CKSEL[3:0]
Delay Counters
TIMEOUT
31
1477G–AVR–03/05
Power-on Reset
Table 16. Reset Characteristics
Symbol Parameter Condition Min Typ Max Units
V
POT
Power-on Reset Threshold
Voltage (rising)
Power-on Reset Threshold
Voltage (falling) (1)
1.4
1.3
2.3
2.3
V
V
V t
RST
RST
RESET Pin Threshold Voltage
Minimum pulse width on
RESET Pin
Brown-out Reset Threshold
Voltage
(2)
BODLEVEL = 1
0.2
2.4
2.7
0.9
1.5
2.9
V
CC
µs
V
BOT t
BOD
V
HYST
Minimum low voltage period for
Brown-out Detection
Brown-out Detector hysteresis
BODLEVEL = 0 3.7
BODLEVEL = 1
BODLEVEL = 0
4.0
2
2
130
4.5
V
µs
µs mV
Notes: 1. The Power-on Reset will not work unless the supply voltage has been below V
POT
(falling)
2. V
BOT
may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to V
CC
= V
BOT
during the production test. This guarantees that a Brown-out Reset will occur before V
CC
drops to a voltage where correct operation of the microcontroller is no longer guaranteed.
The test is performed using BODLEVEL=1 for ATtiny26L and BODLEVEL=0 for
ATtiny26. BODLEVEL=1 is not applicable for ATtiny26.
See start-up times from reset from “System Clock and Clock Options” on page 22.
When the CPU wakes up from Power-down, only the clock counting part of the start-up time is used. The Watchdog Oscillator is used for timing the real-time part of the start-up time.
A Power-on Reset (POR) pulse is generated by an On-chip Detection circuit. The detection level is defined in Table 16 The POR is activated whenever V
CC
is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as detect a failure in supply voltage.
The Power-on Reset (POR) circuit ensures that the device is reset from Power-on.
Reaching the Power-on Reset threshold voltage invokes a delay counter, which determines the delay, for which the device is kept in RESET after V
CC
rise. The time-out period of the delay counter can be defined by the user through the CKSEL Fuses. The
different selections for the delay period are presented in “System Clock and Clock
Options” on page 22. The RESET signal is activated again, without any delay, when the
V
CC
decreases below detection level.
32
ATtiny26(L)
1477G–AVR–03/05
External Reset
ATtiny26(L)
Figure 26. MCU Start-up, RESET Tied to VCC
V
POT
VCC
V
RST
RESET
TIME-OUT t
TOUT
INTERNAL
RESET
Figure 27. MCU Start-up, RESET Controlled Externally
V
POT
VCC
V
RST
RESET t
TOUT
TIME-OUT
INTERNAL
RESET
An External Reset is generated by a low level on the RESET pin. Reset pulses longer than 500 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold
Voltage – V
RST
– on its positive edge, the delay timer starts the MCU after the Time-out period t
TOUT
has expired.
Figure 28. External Reset During Operation
VCC
RESET
V
RST t
TOUT
TIME-OUT
INTERNAL
RESET
33
1477G–AVR–03/05
Brown-out Detection
ATtiny26(L) has an On-chip Brown-out Detection (BOD) circuit for monitoring the V
CC level during the operation. The BOD circuit can be enabled/disabled by the fuse
BODEN. When the BOD is enabled (BODEN programmed), and V
CC
decreases below the trigger level, the Brown-out Reset is immediately activated. When V
CC
increases above the trigger level, the Brown-out Reset is deactivated after a delay. The delay is defined by the user in the same way as the delay of POR signal, in Table 29. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis of 50 mV to ensure spike free Brown-out Detection.
The BOD circuit will only detect a drop in V
CC
if the voltage stays below the trigger level for longer than t
BOD
given in Table 16.
Figure 29. Brown-out Reset During Operation
V
CC
V
BOT-
V
BOT+
RESET
Watchdog Reset
TIME-OUT t
TOUT
INTERNAL
RESET
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t
TOUT
. Refer to page 78 for details on operation of the Watchdog.
Figure 30. Watchdog Time-out
1 CK Cycle
34
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
MCU Status Register –
MCUSR
Bit
$34 ($54)
Read/Write
Initial Value
R
0
7
–
R
0
6
–
R
0
5
–
R
0
4
–
3
WDRF
R/W
2
BORF
1
EXTRF
R/W R/W
See Bit Description
0
PORF
R/W
MCUSR
• Bit 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set (one) if a Watchdog Reset occurs. The bit is reset (zero) by a Power-on
Reset, or by writing a logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set (one) if a Brown-out Reset occurs. The bit is reset (zero) by a Power-on
Reset, or by writing a logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set (one) if an External Reset occurs. The bit is reset (zero) by a Power-on
Reset, or by writing a logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set (one) if a Power-on Reset occurs. The bit is reset (zero) by writing a logic zero to the flag.
To make use of the reset flags to identify a reset condition, the user should read and then reset (zero) the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.
35
1477G–AVR–03/05
Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements.
To enter any of the four sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed. The SM1, and SM0 bits in the MCUCR
Register select which sleep mode (Idle, ADC Noise Reduction, Power Down, or Standby) will be activated by the SLEEP instruction. See Table 17 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The
MCU is then halted for four cycles in addition to the start-up time, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a
Reset occurs during sleep mode, the MCU wakes up and executes from the Reset
Vector.
Table 19 on page 38 presents the different clock systems in the ATtiny26, and their dis-
tribution. The figure is helpful in selecting an appropriate sleep mode.
MCU Control Register –
MCUCR
The MCU Control Register contains control bits for general MCU functions.
Bit
$35 ($55)
Read/Write
Initial Value
R
0
7
–
6
PUD
R/W
0
5
SE
R/W
0
4
SM1
R/W
0
3
SM0
R/W
0
R
0
2
–
1
ISC01
R/W
0
0
ISC00
R/W
0
MCUCR
• Bits 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
• Bit 6 – PUD: Pull-up Disable
When this bit is set (one), the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See
“Configuring the Pin” on page 42 for more details about this feature.
• Bit 5 – SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the Sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the Sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.
• Bits 4,3 – SM1/SM0: Sleep Mode Select Bits 1 and 0
These bits select between the four available Sleep modes, as shown in the following table.
Table 17. Sleep Modes
SM1
0
0
1
1
SM0
0
1
0
1
Sleep Mode
Idle mode
ADC Noise Reduction mode
Power-down mode
Standby mode
For details, refer to the paragraph “Sleep Modes” below.
• Bit 2 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
36
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
Idle Mode
ADC Noise Reduction
Mode
Power-down Mode
• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask is set (one). The activity on the external INT0 pin that activates the interrupt is defined in the following table.
Table 18. Interrupt 0 Sense Control
(1)
ISC01 ISC00 Description
1
1
0
0
0
1
0
1
The low level of INT0 generates an interrupt request.
Any change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
Note: 1. When changing the ISC10/ISC00 bits, INT0 must be disabled by clearing its Interrupt
Enable bit in the GIMSK Register. Otherwise an interrupt can occur when the bits are changed.
When the SM1..0 bits are written to “00”, the SLEEP instruction makes the MCU enter
Idle mod e, stopping the CPU but allo wing Ana lo g Co mpa rator, ADC, USI,
Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk
CPU
and clk
FLASH
, while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and USI Start and Overflow interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status
Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.
When the SM1..0 bits are written to “01”, the SLEEP instruction makes the MCU enter
ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the External Interrupts, the USI start condition detection, and the Watchdog to continue operating (if enabled). This sleep mode basically halts clk
I/O
, clk
CPU
, and clk
FLASH
, while allowing the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a
Watchdog Reset, a Brown-out Reset, USI start condition interrupt, an EEPROM ready interrupt, an External Level Interrupt on INT0, or a pin change interrupt can wake up the
MCU from ADC Noise Reduction mode.
When the SM1..0 bits are written to “10”, the SLEEP instruction makes the MCU enter
Power-down mode. In this mode, the External Oscillator is stopped, while the External
Interrupts, the USI start condition detection, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, USI start condition interrupt, an External Level Interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL
Fuses that define the reset time-out period, as described in “Clock Sources” on page 24.
37
1477G–AVR–03/05
Note that if a level triggered external interrupt or pin change interrupt is used from
Power-down mode, the changed level must be held for some time to wake up the MCU.
This makes the MCU less sensitive to noise.
If the wake-up condition disappears before the MCU wakes up and starts to execute, e.g., a low level on INT0 is not held long enough, the interrupt causing the wake-up will not be executed.
Standby Mode
When the SM1..0 bits are “11” and an External Crystal/Resonator clock option is selected, the SLEEP instruction forces the MCU into the Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From
Standby mode, the device wakes up in only six clock cycles.
Table 19. Active Clock Domains and Wake-up Sources in the different Sleep Modes.
Active Clock domains Oscillators Wake-up Sources
Sleep Mode
Idle clk
CPU clk
FLASH clk
IO
X clk
ADC
X
Main Clock
Source Enabled
X
INT0, and Pin
Change
X
USI Start
Condition
X
ADC Noise
Reduction
Power-down
Standby
(1)
X X
X
X
(2)
X (2)
X
(2)
Notes: 1. Only recommended with external crystal or resonator selected as clock source.
2. Only level interrupt INT0.
X
X
X
EEPROM
Ready
X
X
ADC
X
X
Other I/O
X
38
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
Minimizing Power
Consumption
Analog to Digital Converter
Analog Comparator
Brown-out Detector
Internal Voltage Reference
Watchdog Timer
Port Pins
There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again,
When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep modes, the Analog Comparator is automatically disabled. However, if the
Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog
Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Ref-
If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled by the BODEN Fuse, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will
The Internal Voltage Reference (see Table 20) will be enabled when needed by the
Brown-out Detector, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the Internal Voltage Reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately.
Table 20. Internal Voltage Reference
Symbol Parameter
V
BG t
BG
I
BG
Bandgap reference voltage
Bandgap reference start-up time
Bandgap reference current consumption
Min
1.15
Typ
1.18
40
10
Max
1.40
70
Units
V
µs
µA
If the Watchdog Timer is not needed in the application, this module should be turned off.
If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to
the total current consumption. Refer to “Watchdog Timer” on page 78 for details on how
to configure the Watchdog Timer.
When entering a sleep mode, all port pins should be configured to use minimum power.
The most important thing is then to ensure that no pins drive resistive loads. In sleep modes where the both the I/O clock (clk
I/O
) and the ADC clock (clk
ADC
) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting
wake-up conditions, and it will then be enabled. Refer to “Digital Input Enable and Sleep
Modes” on page 45 for details on which pins are enabled. If the input buffer is enabled
39
1477G–AVR–03/05
and the input signal is left floating or have an analog signal level close to V
CC
/2, the input buffer will use excessive power.
40
ATtiny26(L)
1477G–AVR–03/05
I/O Ports
Introduction
ATtiny26(L)
All AVR ports have true Read-Modify-Write functionality when used as general digital
I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer, except reset, has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both V
CC
and Ground as indicated in Figure 31.
Figure 31. I/O Pin Equivalent Schematic
Pxn
C pin
R pu
Logic
See Figure
"General Digital I/O" for
Details
All registers and bit references in this section are written in general form. A lower case
“x” represents the numbering letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally
Three I/O memory address locations are allocated for each port, one each for the Data
Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The
Port Input Pins I/O location is read only, while the Data Register and the Data Direction
Register are read/write. In addition, the Pull-up Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when set.
tures on the device. How each alternate function interferes with the port pin is described
in “Alternate Port Functions” on page 46. Refer to the individual module sections for a
full description of the alternate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O.
41
1477G–AVR–03/05
Ports as General Digital
I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 32 shows a functional description of one I/O-port pin, here generically called Pxn.
Figure 32. General Digital I/O
(1)
Configuring the Pin
PUD
Q D
DDxn
Q
CLR
RESET
WDx
RDx
Pxn
SLEEP
Q D
PORTxn
Q
CLR
RESET
WPx
RRx
SYNCHRONIZER
D Q
L Q
D Q
PINxn
Q
RPx clk
I/O
PUD:
SLEEP: clk
I/O
:
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
WDx:
RDx:
WPx:
RRx:
RPx:
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
Note: 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
I/O
,
SLEEP, and PUD are common to all ports.
address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when a reset condition becomes active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,
PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} =
0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the
42
ATtiny26(L)
1477G–AVR–03/05
Reading the Pin Value
ATtiny26(L) difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state
({DDxn, PORTxn} = 0b11) as an intermediate step.
Table 21 summarizes the control signals for the pin value.
Table 21. Port Pin Configurations
DDxn PORTxn
0 0
PUD
(in MCUCR)
X
0
0
1
1
1
1
0
1
0
1
X
X
I/O
Input
Input
Input
Output
Output
Pull-up Comment
No Tri-state (Hi-Z)
Yes
Pxn will source current if ext. pulled low
No
No
No
Tri-state (Hi-Z)
Output Low (Sink)
Output High (Source)
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register Bit. As shown in Figure 32, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure
33 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted t pd,max respectively.
and t pd,min
Figure 33. Synchronization when Reading an Externally Applied Pin Value
SYSTEM CLK
INSTRUCTIONS
SYNC LATCH
PINxn r17
XXX XXX in r17, PINx
0xFF 0x00 t pd, max t pd, min
Consider the clock period starting shortly after the first falling edge of the system clock.
The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows t pd,max
and t pd,min
, a single
43
1477G–AVR–03/05
signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 34. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay t pd clock period.
through the synchronizer is one system
Figure 34. Synchronization when Reading a Software Assigned Pin Value
SYSTEM CLK r16
INSTRUCTIONS
SYNC LATCH
PINxn r17 out PORTx, r16 nop
0xFF in r17, PINx
0x00 t pd
0xFF
44
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins.
Assembly Code Example (1)
...
; Define pull-ups and set outputs high
; Define directions for port pins ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0) out PORTB,r16 out DDRB,r17
; Insert nop for synchronization nop
; Read port pins in r16,PINB
...
C Code Example unsigned char i;
...
/* Define pull-ups and set outputs high */
/* Define directions for port pins */
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
/* Insert nop for synchronization */
_NOP();
/* Read port pins */ i = PINB;
...
Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.
Digital Input Enable and Sleep
Modes
As shown in Figure 32, the digital input signal can be clamped to ground at the input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep
Controller in Power-down mode, Standby mode, and ADC Noise Reduction mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to V
CC
/2.
SLEEP is overridden for port pins enabled as External Interrupt pins. If the External
Interrupt Request is not enabled, SLEEP is active also for these pins. SLEEP is also
If a logic high level (“one”) is present on an Asynchronous External Interrupt pin configured as “Interrupt on a Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change.
45
1477G–AVR–03/05
Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode, and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal pullup. In this case, the pullup will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pullup or pulldown. Connecting unused pins directly to V
CC
or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output.
Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/Os. Figure
35 shows how the port pin control signals from the simplified Figure 32 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family.
Figure 35. Alternate Port Functions (1)
PUOExn
PUOVxn
1
0
PUD
DDOExn
DDOVxn
1
0
PVOExn
PVOVxn
Q D
DDxn
Q
CLR
RESET
WDx
RDx
Pxn
1
0
1
0
DIEOExn
DIEOVxn
SLEEP
Q D
PORTxn
Q
CLR
RESET
WPx
RRx
RPx
SYNCHRONIZER
D
SET
Q
L
CLR
Q
D Q
PINxn
CLR
Q clk
I/O
DIxn
AIOxn
PUOExn: Pxn PULL-UP OVERRIDE ENABLE
PUOVxn: Pxn PULL-UP OVERRIDE VALUE
DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE
DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE
PVOExn: Pxn PORT VALUE OVERRIDE ENABLE
PVOVxn: Pxn PORT VALUE OVERRIDE VALUE
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP: SLEEP CONTROL
PUD:
WDx:
RDx:
RRx:
WPx:
RPx: clk
I/O
:
DIxn:
AIOxn:
PULLUP DISABLE
WRITE DDRx
READ DDRx
READ PORTx REGISTER
WRITE PORTx
READ PORTx PIN
I/O CLOCK
DIGITAL INPUT PIN n ON PORTx
ANALOG INPUT/OUTPUT PIN n ON PORTx
Note: 1. WPx, WDx, RLx, RPx, and RDx are common to all pins within the same port. clk
I/O
,
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
46
ATtiny26(L)
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Table 22 summarizes the function of the overriding signals. The pin and port indexes from Figure 35 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function.
Table 22. Generic Description of Overriding Signals for Alternate Functions
Signal Name Full Name Description
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Pull-up Override
Enable
Pull-up Override
Value
Data Direction
Override Enable
Data Direction
Override Value
If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010.
If PUOE is set, the pull-up is enabled/disabled when
PUOV is set/cleared, regardless of the setting of the
DDxn, PORTxn, and PUD Register bits.
If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit.
If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit.
Port Value
Override Enable
If this signal is set and the Output Driver is enabled, the port value is controlled by the PVOV signal. If
PVOE is cleared, and the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit.
If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn Register bit.
Port Value
Override Value
Digital Input Enable
Override Enable
Digital Input Enable
Override Value
Digital Input
If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If this signal is cleared, the Digital
Input Enable is determined by MCU-state (Normal mode, sleep modes).
If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/cleared, regardless of the MCU state (Normal mode, sleep modes).
This is the Digital Input to alternate functions. In the figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. Unless the
Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer.
Analog Input/output This is the Analog Input/Output to/from alternate functions. The signal is connected directly to the pad, and can be used bidirectionally.
The following subsections shortly describes the alternate functions for each port, and relates the overriding signals to the alternate function. Refer to the alternate function description for further details.
47
MCU Control Register –
MCUCR
The MCU Control Register contains control bits for general MCU functions.
Bit
$35 ($55)
Read/Write
Initial Value
R
0
7
–
6
PUD
R/W
0
5
SE
R/W
0
4
SM1
R/W
0
3
SM0
R/W
0
R
0
2
–
1
ISC01
R/W
0
0
ISC00
R/W
0
MCUCR
• Bit 6 – PUD: Pull-up Disable
When this bit is set (one), the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See
“Configuring the Pin” on page 42 for more details about this feature.
Alternate Functions of Port A Port A has an alternate functions as analog inputs for the ADC and Analog Comparator and pin change interrupt as shown in Table 23. If some Port A pins are configured as outputs, it is essential that these do not switch when a conversion is in progress. This
might corrupt the result of the conversion. The ADC is described in “Analog to Digital
Converter” on page 94. Analog Comparator is described in “Analog Comparator” on
page 91. Pin change interrupt triggers on pins PA7, PA6 and PA3 if interrupt is enabled
and it is not masked by the alternate functions even if the pin is configured as an output.
See details from “Pin Change Interrupt” on page 62.
Table 23. Port A Pins Alternate Functions
Port Pin Alternate Function
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
ADC6 (ADC input channel 6)
AIN1 (Analog Comparator negative input)
PCINT1 (Pin Change Interrupt 1)
ADC5 (ADC input channel 5)
AIN0 (Analog Comparator positive input)
PCINT1 (Pin Change Interrupt 1)
ADC4 (ADC input channel 4)
ADC3 (ADC input channel 3)
AREF (ADC external reference)
PCINT1 (Pin Change Interrupt 1)
ADC2 (ADC input channel 2)
ADC1 (ADC input channel 1)
ADC0 (ADC input channel 0)
Table 24 and Table 25 relates the alternate functions of Port A to the overriding signals shown in Figure 35 on page 46. Thera are changes on PA7, PA6, and PA3 digital inputs. PA3 output and pullup driver are also overridden.
• ADC6/AIN1 Port – A, Bit 7
AIN1: Analog Comparator Negative input and ADC6: ADC input channel 6 . Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator or analog to digital converter.
PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate function do not mask the interrupt. The masking alternate function is the Analog Comparator. Digital input is enabled on pin PA7 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate function.
• ADC5/AIN0 Port – A, Bit 6
48
ATtiny26(L)
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
AIN0: Analog Comparator Positive input and ADC5: ADC input channel 5 . Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator or analog to digital converter.
PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate function do not mask the interrupt. The masking alternate function is the Analog Comparator. Digital input is enabled on pin PA6 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate function.
• ADC4, ADC3 Port – A, Bit 5, 4
ADC4/ADC3: ADC Input Channel 4 and 3. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the analog to digital converter.
• AREF/PCINT1 Port – A, Bit 3
AREF: External Reference for ADC. Pullup and output driver are disabled on PA3 when the pin is used as an external reference or Internal Voltage Reference (2.56V) with external capacitor at the AREF pin by setting (one) the bit REFS0 in the ADC Multiplexer
Selection Register (ADMUX).
PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate function do not mask the interrupt. The masking alternate function is the pin usage as an analog reference for the ADC. Digital input is enabled on pin PA3 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate function.
Table 24. Overriding Signals for Alternate Functions in PA7..PA4
Signal
Name
PUOE
PA7/ADC6/
AIN1/PCINT1
0
PA6/ADC5/
AIN0/PCINT1
0
PA5/ADC4
0
PUOV
DDOE
DDOV
PVOE
0
0
0
0
PVOV 0
DIEOE PCINT1_ENABLE (1) •
ACSR[ACD]
DIEOV 1
DI
AIO
PCINT1
ADC6 INPUT, AIN1
0
0
0
0
0
PCINT1_ENABLE (1) •
ACSR[ACD]
1
PCINT1
ADC5 INPUT, AIN0
0
0
0
0
0
0
0
0
0
0
0
0
PA4/ADC3
0
0 0
– –
ADC4 INPUT ADC3 INPUT
49
Table 25. Overriding Signals for Alternate Functions in PA3..PA0
Signal
Name
PUOE
PA3/AREF/PCINT1
ADMUX[REFS0]
PA2/ADC2
0
PA1/ADC1
0
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
0
0
0
ADMUX[REFS0]
0
PCINT1_ENABLE (1) •
~
(2)
ADMUX[REFS0]
1
PCINT1
ANALOG REFERENCE INPUT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PA0/ADC0
0
0 0 0
– – –
ADC2 INPUT ADC1 INPUT ADC0 INPUT
Notes: 1. Note that the PCINT1 Interrupt is only enabled if both the Global Interrupt Flag is enabled, the PCIE1 flag in GIMSK is set and the alternate function of the pin is dis-
abled as described in “Pin Change Interrupt” on page 62
2. Not operator is marked with “~”.
50
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
Alternate Functions Of Port B Port B has an alternate functions for the ADC, Clocking, Timer/Counters, USI, SPI pro-
gramming and pin change interrupt. The ADC is described in “Analog to Digital
Converter” on page 94, Clocking in “AVR CPU Core” on page 6, timers in
“Timer/Counters” on page 64 and USI in “Universal Serial Interface – USI” on page 80.
Pin change interrupt triggers on pins PB7 - PB0 if interrupt is enabled and it is not masked by the alternate functions even if the pin is configured as an output. See details
from “Pin Change Interrupt” on page 62. Pin functions in programming modes are
described in “Memory Programming” on page 107. The alternate functions are shown in
Table 26.
Table 26. Port B Pins Alternate Functions
Port Pin Alternate Functions
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
ADC10 (ADC Input Channel 10)
RESET (External Reset Input)
PCINT1 (Pin Change Interrupt 1)
ADC9 (ADC Input Channel 9)
INT0 (External Interrupt 0 Input)
T0 (Timer/Counter 0 External Counter Clock Input)
PCINT1 (Pin Change Interrupt 1)
ADC8 (ADC Input Channel 8)
XTAL2 (Crystal Oscillator Output)
PCINT1 (Pin Change Interrupt 1)
ADC7 (ADC Input Channel 7)
XTAL1 (Crystal Oscillator Input)
PCINT1 (Pin Change Interrupt 1)
OC1B (Timer/Counter1 PWM Output B, Timer/Counter1Output Compare B Match
Output)
PCINT0 (Pin Change Interrupt 0)
SCK (USI Clock Input/Output)
SCL (USI External Open-collector Serial Clock)
OC1B (Inverted Timer/Counter1 PWM Output B)
PCINT0 (Pin Change Interrupt 0)
DO (USI Data Output)
OC1A (Timer/Counter1 PWM Output A, Timer/Counter1 Output Compare A Match
Output)
PCINT0 (Pin Change Interrupt 0)
DI (USI Data Input)
SDA (USI Serial Data)
OC1A (Inverted Timer/Counter1 PWM Output A)
PCINT0 (Pin Change Interrupt 0)
The alternate pin configuration is as follows:
• ADC10/RESET/PCINT1 – Port B, Bit 7
ADC10: ADC Input Channel 10. Configure the port pins as inputs with the internal pullups switched off to avoid the digital port function from interfering with the function of the analog to digital converter.
RESET: External Reset input is active low and enabled by unprogramming (“1”) the
RSTDISBL Fuse. Pullup is activated and output driver and digital input are deactivated when the pin is used as the RESET pin.
51
1477G–AVR–03/05
52
ATtiny26(L)
PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate function do not mask the interrupt. The masking alternate function is the pin usage as RESET. Digital input is enabled on pin PB7 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate function.
• ADC9/INT0/T0/PCINT1 – Port B, Bit 6
ADC9: ADC Input Channel 9. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the analog to digital converter.
INT0: External Interrupt source 0: The PB6 pin can serve as an external interrupt source enabled by setting (one) the bit INT0 in the General Input Mask Register (GIMSK).
T0: Timer/Counter0 External Counter Clock input is enabled by setting (one) the bits
CS02 and CS01 in the Timer/Counter0 Control Register (TCCR0).
PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate functions are the external low level Interrupt source 0 (INT0) and the Timer/Counter0 External Counter clock input (T0). Digital input is enabled on pin PB6 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functions.
• ADC8/XTAL2/PCINT1 – Port B, Bit 5
ADC8: ADC Input Channel 8. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the analog to digital converter.
XTAL2: Chip Clock Oscillator pin 2. Used as clock pin for all chip clock sources except internal calibrateble RC Oscillator, external clock and PLL clock. When used as a clock pin, the pin can not be used as an I/O pin. When using internal calibratable RC Oscillator, External clock or PLL clock as Chip clock sources, PB5 serves as an ordinary I/O pin.
PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate functions are the XTAL2 outputs. Digital input is enabled on pin PB5 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functions.
• ADC7/XTAL1/PCINT1 – Port B, Bit 4
ADC7: ADC Input Channel 7. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the analog to digital converter.
XTAL1: Chip Clock Oscillator pin 1. Used for all chip clock sources except internal calibrateble RC oscillator and PLL clock. When used as a clock pin, the pin can not be used as an I/O pin. When using internal calibratable RC Oscillator or PLL clock as chip clock sources, PB4 serves as an ordinary I/O pin.
PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate functions are the XTAL1 inputs. Digital input is enabled on pin PB4 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functions.
• OC1B/PCINT0 – Port B, Bit 3
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
OC1B: Output Compare match output: The PB3 pin can serve as an output for the
Timer/Counter1 compare match B. The PB3 pin has to be configured as an output
(DDB3 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode.
PCINT0: Pin Change Interrupt 0 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate function is the output compare match output
OC1B. Digital input is enabled on pin PB3 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functions.
• SCK/SCL/OC1B/PCINT0 – Port B, Bit 2
SCK: Clock input or output in USI Three-wire mode. When the SPI is enabled this pin is configured as an input. In the USI Three-wire mode the bit DDRB2 controls the direction of the pin, output for the Master mode and input for the Slave mode.
SCL: USI External Open-collector Serial Clock for USI Two-wire mode. The SCL pin is pulled low when PORTB2 is cleared (zero) or USI start condition is detected and
DDRB2 is set (one). Pull-up is disabled in USI Two-wire mode.
OC1B: Inverted Timer/Counter1 PWM Output B: The PB2 pin can serve as an inverted output for the Timer/Counter1 PWM mode if USI is not enabled. The PB2 pin has to be configured as an output (DDB2 set (one)) to serve this function.
PCINT1: Pin Change Interrupt 0 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate function are the inverted output compare match output OC1B and USI clocks SCK/SCL. Digital input is enabled on pin PB2 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functions.
• DO/OC1A/PCINT0 – Port B, Bit 1
DO: Data Output in USI Three-wire mode. Data output (DO) overrides PORTB1 value and it is driven to the port when the data direction bit DDB1 is set (one). However the
PORTB1 bit still controls the pullup, enabling pullup if direction is input and PORTB1 is set(one).
OC1A: Output Compare match output: The PB1 pin can serve as an output for the
Timer/Counter1 compare match A. The PB1 pin has to be configured as an output
(DDB1 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function if not used in programming or USI.
PCINT0: Pin Change Interrupt 0 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate functions are the output compare match output OC1A and Data Output (DO) in USI Three-wire mode. Digital input is enabled on pin
PB1 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functions.
53
• DI/SDA/OC1A/PCINT0 – Port B, Bit 0
DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port functions., so pin must be configure as an input.
SDA: Serial Data in USI Two-wire mode. Serial data pin is bi-directional and uses opencollector output. The SDA pin is enabled by setting the pin as an output. The pin is pulled low when the PORTB0 or USI shiftRegister is zero when DDB0 is set (one). Pullup is disabled in USI Two-wire mode.
OC1A: Inverted Timer/Counter1 PWM output A: The PB0 pin can serve as an Inverted output for the PWM mode if not used in programming or USI. The PB0 pin has to be configured as an output (DDB0 set (one)) to serve this function.
PCINT0: Pin Change Interrupt 0 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate functions are the inverted output compare match output OC1A and USI data DI or SDA. Digital input is enabled on pin PB0 also in
SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functions. Table 27 and Table 28 relate the alternate functions of Port B to the overriding
signals shown in “Alternate Port Functions” on page 46.
Table 27. Overriding Signals for Alternate Functions in PB7..PB4
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
PB7/ADC10/RESET/
PCINT1
RSTDSBL (1)
0
0
1
RSTDSBL (1)
0
PCINT1_ENABLE (2) | RSTDSBL (1)
PCINT1_ENABLE
~ (5) RSTDSBL (1)
(2)
•
PB6/ADC9/INT0/TO/
PCINT1
0
0
0
0
0
0
~T0_EXT_CLOCK (6) •
PCINT1_ENABLE
(2)
|
INT0_ENABLE (4)
1
PB5/ADC8/XTAL2/
PCINT1
~
0
0
0
0
(5) PB5IOENABLE
~PB5IOENABLE (3)
(3)
PCINT1_ENABLE (2) |
~PB5IOENABLE
(3)
PCINT1_ENABLE
PB5IOENABLE (3)
(2)
•
PB4/ADC7/XTAL1
~PB4IOENABLE (3)
0
~PB4IOENABLE
0
0
(3)
0
PCINT_ ENABLE (2) |
~PB4IOENABLE
(3)
|
EXT_CLOCK_ENABLE (7)
PCINT1_ENABLE
(2)
•
PB4IOENABLE (3) |
EXT_CLOCK_ENABLE
External Clock, PCINT1 DI PCINT1 INT0, T0, PCINT1 PCINT1
AIO ADC10, RESET INPUT ADC9 ADC8, XTAL2 XTAL1
Notes:
1. RSTDISBL Fuse (active low) is described in section “System Control and Reset” on page 31.
2. Note that the PCINT1 Interrupt is only enabled if both the Global Interrupt Flag is enabled, the PCIE1 flag in GIMSK is set
and the alternate function of the pin is disabled as described in “Pin Change Interrupt” on page 62.
4. External low level interrupt is enabled if both the Global Interrupt Flag is enabled and the INT0 flag in GIMSK is set as
described in “External Interrupt” on page 62.
5. Not operator is marked with “~”.
54
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
Table 28. Overriding Signals for Alternate Functions in PB3..PB0
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
PB3/OC1B/PCINT0
0
0
0
0
OC1B_ENABLE
OC1B
(1)
PCINT0_ENABLE
~OC1B_ENABLE
(2)
(1)
•
PB2/SCK/SCL/OC1B/PCI
NT0
USI_TWO-WIRE (3)
0
USI_TWO-WIRE (3)
(USI_SCL_HOLD
~ (8)
(4)
|
PORTB2) • DDB2
USI_TWO-WIRE
(3)
•
DDB2 | OC1B_ENABLE
~(USI_TWO-WIRE •
DDB2) • OC1B
(1)
~(USI_TWO-WIRE |
USI_THREE-WIRE |
OC1B_ENABLE) •
PCINT0_ENABLE
(2)
|
USI_START_I.ENABLE
(5)
1
PCINT0, SCL, SCK
PB1/DO/OC1A/PCINT0
0
0
0
0
USI_THREE-WIRE
OC1A_ENABLE (1)
OC1A_ENABLE) •
(3)
PCINT0_ENABLE (2)
|
USI_THREE-WIRE (3) •
DO
(6)
| ~USI_THREE-
WIRE • OC1A_ENABLE (1)
• OC1A
~(USI_THREE-WIRE |
PB0/DI/SDA/OC1A
USI_TWO-WIRE (3)
0
USI_TWO-WIRE (3)
(~SDA | ~PORTB0) •
DDB0
|
USI_TWO-WIRE
(3)
• DDB0
OC1A_ENABLE
(1)
~(USI_TWO-WIRE•
DDB0) •
OC1A_ENABLE (1) • OC1A
~(USI_TWO-WIRE (3) |
USI_THREE-WIRE
(3)
|
OC1A_ENABLE (1) ) •
PCINT0_ENABLE
(2)
|
USI_START_I.ENABLE
(5)
1
PCINT0, SDA
DIEOV
DI
1
PCINT0
1
PCINT0
AIO – – – –
Notes: 1. Enabling of the Timer/Counter1 Compare match outputs and Timer/Counter1 PWM Outputs OC1A/OC1B and OC1A/OC1B
are described in the section “8-bit Timer/Counter1” on page 67.
2. Note that the PCINT0 Interrupt is only enabled if both the Global Interrupt Flag is enabled, the PCIE0 flag in GIMSK is set
and the alternate function of the pin is disabled as described in “Pin Change Interrupt” on page 62.
4. Shift clock (SCL) hold for USI is in described “Universal Serial Interface – USI” on page 80.
5. USI start up interrupt is enabled if both the Global Interrupt Flag is enabled and the USISIE flag in the USICR Register is set
as described in “Universal Serial Interface – USI” on page 80.
8. Not operator is marked with “~”.
55
1477G–AVR–03/05
Register Description for
I/O Ports
Port A Data Register – PORTA
Port A Data Direction Register
– DDRA Bit
$1A ($3A)
Read/Write
Initial Value
Port A Input Pins Address –
PINA
Bit
$1B ($3B)
Read/Write
Initial Value
7
PORTA7
R/W
0
6
PORTA6
R/W
0
5
PORTA5
R/W
0
4
PORTA4
R/W
0
3
PORTA3
R/W
0
2
PORTA2
R/W
0
1
PORTA1
R/W
0
0
PORTA0
R/W
0
PORTA
7
DDA7
R/W
0
6
DDA6
R/W
0
5
DDA5
R/W
0
4
DDA4
R/W
0
3
DDA3
R/W
0
2
DDA2
R/W
0
1
DDA1
R/W
0
0
DDA0
R/W
0
DDRA
Bit
$19 ($39)
Read/Write
Initial Value
7
PINA7
R
N/A
6
PINA6
R
N/A
5
PINA5
R
N/A
4
PINA4
R
N/A
3
PINA3
R
N/A
2
PINA2
R
N/A
1
PINA1
R
N/A
0
PINA0
R
N/A
PINA
Port B Data Register – PORTB
Bit
$18 ($38)
Read/Write
Initial Value
7 6 5 4 3 2 1 0
PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PORTB
Port B Data Direction Register
– DDRB Bit
$17 ($37)
Read/Write
Initial Value
Port B Input Pins Address –
PINB
7
DDB7
R/W
0
Bit
$16 ($36)
Read/Write
Initial Value
7
PINB7
R
N/A
6
DDB6
R/W
0
6
PINB6
R
N/A
5
DDB5
R/W
0
5
PINB5
R
N/A
4
DDB4
R/W
0
4
PINB4
R
N/A
3
DDB3
R/W
0
3
PINB3
R
N/A
2
DDB2
R/W
0
2
PINB2
R
N/A
1
DDB1
R/W
0
1
PINB1
R
N/A
0
DDB0
R/W
0
0
PINB0
R
N/A
DDRB
PINB
56
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
Interrupts
Interrupt Vectors
The ATtiny26(L) provides eleven interrupt sources. These interrupts and the separate
Reset Vector, each have a separate program vector in the program memory space. All the interrupts are assigned individual enable bits which must be set (one) together with the I-bit in the Status Register in order to enable the interrupt.
The lowest addresses in the program memory space are automatically defined as the
Reset and Interrupt vectors. The complete list of vectors is shown in Table 29. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0 etc.
A
B
C
8
9
6
7
Table 29. Reset and Interrupt Vectors
Vector No Program Address Source
1 $000 RESET
4
5
2
3
$001
$002
$003
$004
INT0
I/O Pins
Interrupt Definition
Hardware Pin and Watchdog Reset
External Interrupt Request 0
Pin Change Interrupt
TIMER1, CMPA Timer/Counter1 Compare Match 1A
TIMER1, CMPB Timer/Counter1 Compare Match 1B
$005
$006
$007
$008
$009
$00A
$00B
TIMER1, OVF1
TIMER0, OVF0
USI_STRT
USI_OVF
EE_RDY
ANA_COMP
Timer/Counter1 Overflow
Timer/Counter0 Overflow
USI Start
USI Overflow
EEPROM Ready
Analog Comparator
The most typical and general program setup for the Reset and Interrupt Vector
Addresses are:
Address Labels Code Comments
$006
$007
$008
$009
$00A
$00B
$000
$001
$002
$003
$004
$005
;
$009
$00A rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp
RESET: ldi out
RESET
EXT_INT0
PIN_CHANGE
TIM1_CMP1A
TIM1_CMP1B
TIM1_OVF
TIM0_OVF
USI_STRT
USI_OVF
EE_RDY
ANA_COMP
ADC
; Reset handler
; IRQ0 handler
; Pin change handler
; Timer1 compare match 1A
; Timer1 compare match 1B
; Timer1 overflow handler
; Timer0 overflow handler
; USI Start handler
; USI Overflow handler
; EEPROM Ready handler
; Analog Comparator handler
; ADC Conversion Handler r16, RAMEND ; Main program start
SP, r16
57
1477G–AVR–03/05
Interrupt Handling
Interrupt Response Time
General Interrupt Mask
Register – GIMSK
$00B
… sei
… … …
The ATtiny26(L) has two 8-bit Interrupt Mask Control Registers; GIMSK – General Interrupt Mask Register and TIMSK – Timer/Counter Interrupt Mask Register.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.
The I-bit is set (one) when a Return from Interrupt instruction – RETI – is executed.
When the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared.
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared
(zero), the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software.
If one or more interrupt conditions occur when the Global Interrupt Enable bit is cleared
(zero), the corresponding interrupt flag(s) will be set and remembered until the Global
Interrupt Enable bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is active.
Note that the Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After the four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter
(10 bits) is pushed onto the Stack. The vector is a relative jump to the interrupt routine, and this jump takes two clock cycles. If an interrupt occurs during execution of a multicycle instruction, this instruction is completed before the interrupt is served.
A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (10 bits) is popped back from the Stack. When AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register – SREG
– is not handled by the AVR hardware, neither for interrupts nor for subroutines. For the routines requiring a storage of the SREG, this must be performed by user software.
Bit
$3B ($5B)
Read/Write
Initial Value
R
0
7
–
6
INT0
R/W
0
5
PCIE1
R/W
0
4
PCIE0
R/W
0
R
0
3
–
R
0
2
–
R
0
1
–
R
0
0
– GIMSK
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the MCU general Control Register (MCUCR) define whether the external
58
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L) interrupt is activated on rising or falling edge, on pin change, or low level of the INT0 pin.
Activity on the pin will cause an interrupt request even if INT0 is configured as an output.
The corresponding interrupt of External Interrupt Request 0 is executed from program
memory address $001. See also “External Interrupt” on page 62.
• Bit 5 – PCIE1: Pin Change Interrupt Enable1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the interrupt pin change is enabled on analog pins PB[7:4], PA[7:6] and PA[3]. Unless the alternate function masks out the interrupt, any change on the pin mentioned before will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is
executed from program memory address $002. See also “Pin Change Interrupt” on page 62.
• Bit 4– PCIE0: Pin Change Interrupt Enable0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the interrupt pin change is enabled on digital pins PB[3:0]. Unless the alternate function masks out the interrupt, any change on the pin mentioned before will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from program
memory address $002. See also “Pin Change Interrupt” on page 62.
• Bits 3..0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
General Interrupt Flag
Register – GIFR Bit
$3A ($5A)
Read/Write
Initial Value
R
0
7
–
6
INTF0
R/W
0
• Bit 7 – Res: Reserved Bit
5
PCIF
R/W
0
R
0
4
–
R
0
3
–
R
0
2
–
R
0
1
–
R
0
0
– GIFR
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
• Bit 6 – INTF0: External Interrupt Flag0
When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one).
If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the
Interrupt Vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. The flag is always cleared when INT0 is configured as level interrupt.
• Bit 5 – PCIF: Pin Change Interrupt Flag
When an event on pins PB[7:0], PA[7:6], or PA[3] triggers an interrupt request, PCIF becomes set (one). PCIE1 enables interrupt from analog pins PB[7:4], PA[7:6], and
PA[3]. PCIE0 enables interrupt on digital pins PB[3:0]. Note that pin change interrupt enable bits PCIE1 and PCIE0 also mask the flag if they are not set. For example, if
PCIE0 is cleared, a pin change on PB[3:0] does not set PCIF. If an alternate function is enabled on a pin, PCIF is masked from that individual pin. If the I-bit in SREG and the
PCIE bit in GIMSK are set (one), the MCU will jump to the Interrupt Vector at address
$002. The flag is cleared when the interrupt routine is executed. Alternatively, the flag
can be cleared by writing a logical one to it. See also “Pin Change Interrupt” on page 62.
• Bits 4..0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
Timer/Counter Interrupt Mask
Register – TIMSK Bit
$39 ($59)
7
–
6
OCIE1A
5
OCIE1B
4
–
3
–
2
TOIE1
1
TOIE0
0
– TIMSK
59
1477G–AVR–03/05
Read/Write
Initial Value
R
0
R/W
0
• Bit 7 – Res: Reserved Bit
R/W
0
R
0
R
0
R/W
0
R/W
0
R
0
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
• Bit 6 – OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 compare match A, interrupt is enabled. The corresponding interrupt at vector $003 is executed if a compare match A occurs. The Compare Flag in
Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register.
• Bit 5 – OCIE1B: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 compare match B, interrupt is enabled. The corresponding interrupt at vector $004 is executed if a compare match B occurs. The Compare Flag in
Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register.
• Bit 4..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
• Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector
$005) is executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer1) is set (one) in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector
$006) is executed if an overflow in Timer/Counter0 occurs. The Overflow Flag (Timer0) is set (one) in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
Timer/Counter Interrupt Flag
Register – TIFR Bit
$38 ($58)
Read/Write
Initial Value
R
0
7
–
6
OCF1A
R/W
0
5
OCF1B
R/W
0
R
0
4
–
R
0
3
–
2
TOV1
R/W
0
1
TOV0
R/W
0
R
0
0
– TIFR
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
• Bit 6 – OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A – Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the
I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 A Compare
Match interrupt is executed.
• Bit 5 – OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1B – Output Compare Register 1A. OCF1B is cleared by hard-
60
ATtiny26(L)
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L) ware when executing the corresponding interrupt handling vector. Alternatively, OCF1B is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the
I-bit in SREG, OCIE1B, and OCF1B are set (one), the Timer/Counter1 B Compare
Match interrupt is executed.
• Bits 4..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
• Bit 2 – TOV1: Timer/Counter1 Overflow Flag
The bit TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV1 is cleared, after synchronization clock cycle, by writing a logical one to the flag.
When the SREG I-bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and
TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed.
• Bit 1 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logical one to the flag. When the SREG I-bit, and TOIE0
(T i me r/Co un ter 0 Ov erflo w Inte rru pt E n ab le ), a nd T OV 0 are s et (o ne ), th e
Timer/Counter0 Overflow interrupt is executed.
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
61
External Interrupt
Pin Change Interrupt
The External Interrupt is triggered by the INT0 pin. Observe that, if enabled, the interrupt will trigger even if the INT0 pin is configured as an output. This feature provides a way of generating a software interrupt. The External Interrupt can be triggered by a falling or rising edge, a pin change, or a low level. This is set up as indicated in the specification for the MCU Control Register – MCUCR. When the External Interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low.
The changed level is sampled twice by the Watchdog Oscillator clock, and if both these samples have the required level, the MCU will wake up. The period of the Watchdog
Oscillator is 1.0 µs (nominal) at 3.0V and 25°C. The frequency of the Watchdog Oscilla-
tor is voltage dependent as shown in “Electrical Characteristics” on page 126.
The pin change interrupt is triggered by any change on any I/O pin of Port B and pins
PA3, PA6, and PA7, if the interrupt is enabled and alternate function of the pin does not mask out the interrupt. The bit PCIE1 in GIMSK enables interrupt from pins PB[7:4],
PA[7:6], and PA[3]. PCIE0 enables interrupt on digital pins PB[3:0].
The pin change interrupt is different from other interrupts in two ways. First, pin change interrupt enable bits PCIE1 and PCIE0 also mask the flag if they are not set. The normal operation on most interrupts is that the flag is always active and only the execution of the interrupt is masked by the interrupt enable.
Secondly, please note that pin change interrupt is disabled for any pin that is configured as an alternate function. For example, no pin change interrupt is generated from pins that are configured as AREF, AIN0 or AIN1, OC1A, OC1A, OC1B, OC1B, XTAL1, or
XTAL2 in a fuse selected clock option, Timer0 clocking, or RESET function. See Table
30 for alternate functions which mask the pin change interrupt and how the function is enabled. For example pin change interrupt on the PB0 is disabled when USI Two-wire mode or USI Three-wire mode or Timer/Counter1 inverted output compare is enabled.
If the interrupt is enabled, the interrupt will trigger even if the changing pin is configured as an output. This feature provides a way of generating a software interrupt. Also observe that the pin change interrupt will trigger even if the pin activity triggers another interrupt, for example the external interrupt. This implies that one external event might cause several interrupts.
The value of the programmed fuse is “0” and unprogrammed is “1”. Each of the lines enables the alternate function so “or” function of the lines enables the function.
62
ATtiny26(L)
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Table 30. Alternative Functions
Pin Alternate Function
PA3 AREF
PA6 Analog Comparator
PA7 Analog Comparator
PB0 USI Two-wire mode
USI Three-wire mode
TC1 compare/PWM
PB1 USI Three-wire mode
TC1 compare/PWM
PB2 USI Two-wire mode
USI Three-wire mode
TC1 compare/PWM
PB3 TC1 compare/PWM
PB4 XTAL1, clock source
PB5 XTAL2, clock source
PB6 External interrupt
TC0 clock
PB7 RESET
Control Register[Bit Name] which set the Alternate Function
(1)
ADMUX[REFS0]
ACSR[ACD]
ACSR[ACD]
USICR[USIWM1]
USICR[USIWM1,USIWM0]
TCCR1A[COM1A1,COM1A0,PWM1A]
USICR[USIWM1,USIWM0]
TCCR1A[COM1A1]
TCCR1A[COM1A0]
USICR[USIWM1]
USICR[USIWM1,USIWM0]
TCCR1A[COM1B1,COM1B0,PWM1B]
TCCR1A[COM1B1]
TCCR1A[COM1B0]
FUSE[PLLCK,CKSEL]
FUSE[PLLCK,CKSEL]
FUSE[PLLCK,CKSEL]
GIMSK[INT0],MCUCR[ISC01,ISC01]
TCCR0[CS02,CS01]
RSTDISBL FUSE
1
01
011
01
1
1
1
01
011
1
1
10000
10101-11111
11001-11111
100
11
1
Bit or Fuse
Value
()
1
0
0
Notes: 1. Each line represents a bit or fuse combination which enables the function.
A fuse value of “0” is programmed, “1” is unprogrammed.
63
Timer/Counters
Timer/Counter0
Prescaler
Th e ATtiny26 (L) pro vid es two gen eral pur pose 8- bit T im er/Co unte rs. T he
Timer/Counters have separate prescaling selection from the separate prescaler. The
Timer/Counter0 clock (CK) as the clock timebase. The Timer/Counter1 has two clocking modes, a synchronous mode and an asynchronous mode. The synchronous mode uses the system clock (CK) as the clock timebase and asynchronous mode uses the fast peripheral clock (PCK) as the clock time base.
Figure 36 below shows the Timer/Counter prescaler.
Figure 36. Timer/Counter0 Prescaler
CK 10-BIT T/C PRESCALER
CLEAR
PSR0
T0(PB6)
0
CS00
CS01
CS02
TIMER/COUNTER0 CLOCK SOURCE
The four prescaled selections are: CK/8, CK/64, CK/256, and CK/1024 where CK is the oscillator clock. CK, external source, and stop, can also be selected as clock sources.
64
ATtiny26(L)
1477G–AVR–03/05
Timer/Counter1
Prescaler
8-bit Timer/Counter0
ATtiny26(L)
Figure 37 shows the Timer/Counter1 prescaler. For Timer/Counter1 the clock selections are between PCK to PCK/16384 and stop in asynchronous mode and CK to CK/16384
and stop in synchronous. The clock options are described in Table 34 on page 72 and
the Timer/Counter1 Control Register, TCCR1B. Setting the PSR1 bit in TCCR1B Register resets the prescaler. The PCKE bit in the PLLCSR Register enables the asynchronous mode.
Figure 37. Timer/Counter1 Prescaler
PCKE
PSR1
CK
PCK
(64 MHz)
S
A
T1CK 14-BIT
T/C PRESCALER
0
CS10
CS11
CS12
CS13
TIMER/COUNTER1 COUNT ENABLE
Figure 38 shows the block diagram for Timer/Counter0.
The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition, it can be stopped as described in the specification for the
Timer/Counter0 Control Register – TCCR0. The overflow status flag is found in the
Timer/Counter Interrupt Flag Register – TIFR. Control signals are found in the
Timer/Counter0 Control Register – TCCR0. The interrupt enable/disable settings for
Timer/Counter0 are found in the Timer/Counter Interrupt Mask Register – TIMSK.
When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To ensure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock.
The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions.
65
1477G–AVR–03/05
Figure 38. Timer/Counter0 Block Diagram
Timer/Counter0 Control
Register – TCCR0
66
ATtiny26(L)
Bit
$33 ($53)
Read/Write
Initial Value
R
0
7
–
R
0
6
–
R
0
5
–
R
0
4
–
3
PSR0
R/W
0
2
CS02
R/W
0
1
CS01
R/W
0
0
CS00
R/W
0
TCCR0
• Bits 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
• Bit 3 – PSR0: Prescaler Reset Timer/Counter0
When this bit is set (one), the prescaler of the Timer/Counter0 will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always be read as zero.
• Bits 2, 1, 0 – CS02, CS01, CS00: Clock Select0, Bit 2, 1, and 0
The Clock Select0 bits 2, 1, and 0 define the prescaling source of Timer0.
Table 31. Clock 0 Prescale Select
CS02 CS01 CS00 Description
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
Stop, the Timer/Counter0 is stopped
CK
CK/8
CK/64
CK/256
CK/1024
External Pin T0, falling edge
External Pin T0, rising edge
1477G–AVR–03/05
Timer/Counter0 – TCNT0
8-bit Timer/Counter1
ATtiny26(L)
The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used, the corresponding setup must be performed in the actual Data Direction Control
Register (cleared to zero gives an input pin).
Bit
$32 ($52)
Read/Write
Initial Value
7
MSB
R/W
0
6
R/W
0
5
R/W
0
4
R/W
0
3
R/W
0
2
R/W
0
1
R/W
0
0
LSB
R/W
0
TCNT0
The Timer/Counter0 is implemented as an up-counter with read and write access. If the
Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the timer clock cycle following the write operation.
The Timer/Counter1 has two clocking modes: a synchronous mode and an asynchronous mode. The synchronous mode uses the system clock (CK) as the clock timebase and asynchronous mode uses the fast peripheral clock (PCK) as the clock time base.
The PCKE bit from the PLLCSR Register enables the asynchronous mode when it is set
(“1”). The Timer/Counter1 general operation is described in the asynchronous mode and the operation in the synchronous mode is mentioned only if there is differences between these two modes. Figure 39 shows Timer/Counter1 synchronization register block diagram and synchronization delays in between registers. Note that all clock gating details are not shown in the figure. The Timer/Counter1 Register values go through the internal synchronization registers, which cause the input synchronization delay, before affecting the counter operation. The registers TCCR1A, TCCR1B, OCR1A, OCR1B, and OCR1C can be read back right after writing the register. The read back values are delayed for the Timer/Counter1 (TCNT1) Register and flags (OCF1A, OCF1B, and TOV1), because of the input and output synchronization.
This module features a high resolution and a high accuracy usage with the lower prescaling opportunities. Timer/Counter1 can also support two accurate, high speed, 8-bit
Pulse Width Modulators using clock speeds up to 64 MHz. In this mode, Timer/Counter1 and the Output Compare Registers serve as dual stand-alone PWMs with non-overlap-
ping non-inverted and inverted outputs. Refer to page 74 for a detailed description on
this function. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions.
67
1477G–AVR–03/05
68
ATtiny26(L)
Figure 39. Timer/Counter1 Synchronization Register Block Diagram
IO -re g is te rs
O C R 1 A
O C R 1 B
O C R 1 C
T C C R 1 A
T C C R 1 B
8 -B IT D A T A B U S
In p u t sy n c ro n iz a tio n T im e r/C o u n te r1 re g is te rs
O C R 1 A _ S I
O C R 1 B _ S I
O C R 1 C _ S I
T C C R 1 A _ S I
T C C R 1 B _ S I
T C N T 1
O u tp u t s y nc ro n iz atio n re g is te rs
T C N T _ S O
O C F 1 A _ S O
T C N T 1
O C F 1 A
O C F 1 B
T O V 1
T C N T 1 _ S I
O C F 1 A _ S I
O C F 1 B _ S I
T O V 1 _ S I
O C F 1 B _ S O
T O V 1 _ S O
O u tp u t m u ltip lex e rs
T C N T 1
S
A
S
A
O C F 1 A
S
A
O C F 1 B
S
A
T O V 1
P C K E
C K
S
A
P C K
S Y N C
M O D E
A S Y N C
M O D E
1 C K d e la y
S
A n o d e la y
1 /2 P C K -1 C K d e la y 1 P C K d e lay 1 /2 P C K -1 C K d e la y n o d e la y
Timer/Counter1 and the prescaler allow running the CPU from any clock source while the prescaler is operating on the fast 64 MHz PCK clock in the asynchronous mode.
Note that the system clock frequency must be lower than one half of the PCK frequency.
Only when the system clock is generated from PCK dividing that by two, the ratio of the
PCK/system clock can be exactly two. The synchronization mechanism of the asynchronous Timer/Counter1 needs at least two edges of the PCK when the system clock is high. If the frequency of the system clock is too high, it is a risk that data or control values are lost.
The following Figure 40 shows the block diagram for Timer/Counter1.
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Figure 40. Timer/Counter1 Block Diagram
T/C1 OVER-
FLOW IRQ
T/C1 COMPARE
MATCH A IRQ
T/C1 COMPARE
MATCH B IRQ
OC1A
(PB0)
OC1A
(PB1)
OC1B
(PB2)
OC1B
(PB3)
TIMER INT. MASK
REGISTER (TIMSK)
TIMER INT. FLAG
REGISTER (TIFR)
TIMER/COUNTER1
TIMER/COUNTER1
(TCNT1)
T/C CLEAR
T/C CONTROL
REGISTER 1 (TCCR1B)
T/C1 CONTROL
LOGIC
CK
PCK
8-BIT COMPARATOR
T/C1 OUTPUT
COMPARE REGISTER
(OCR1A)
8-BIT COMPARATOR
T/C1 OUTPUT
COMPARE REGISTER
(OCR1B)
8-BIT COMPARATOR
T/C1 OUTPUT
COMPARE REGISTER
(OCR1C)
8-BIT DATA BUS
Three status flags (overflow and compare matches) are found in the Timer/Counter
Interrupt Flag Register – TIFR. Control signals are found in the Timer/Counter Control
Registers TCCR1A and TCCR1B. The interrupt enable/disable settings are found in the
Timer/Counter Interrupt Mask Register – TIMSK.
The Timer/Counter1 contains three Output Compare Registers, OCR1A, OCR1B, and
OCR1C, as the data source to be compared with the Timer/Counter1 contents. In normal mode the Output Compare functions are operational with all three Output Compare
Registers. OCR1A determines action on the OC1A pin (PB1), and it can generate
Timer1 OC1A interrupt in normal mode and in PWM mode. Likewise, OCR1B determines action on the OC1B pin (PB3) and it can generate Timer1 OC1B interrupt in normal mode and in PWM mode. OCR1C holds the Timer/Counter maximum value, i.e., the clear on compare match value. An overflow interrupt (TOV1) is generated when
Timer/Counter1 counts from $FF to $00 or from OCR1C to $00. This function is the same for both normal and PWM mode. The inverted PWM outputs OC1A and OC1B are not connected in normal mode.
In PWM mode, OCR1A and OCR1B provide the data values against which the
Timer/Counter value is compared. Upon compare match the PWM outputs (OC1A,
OC1A, OC1B, OC1B) are generated. In PWM mode, the Timer/Counter counts up to the value specified in the Output Compare Register OCR1C and starts again from $00. This feature allows limiting the counter “full” value to a specified value, lower than $FF.
Together with the many prescaler options, flexible PWM frequency selection is provided.
Table 37 lists clock selection and OCR1C values to obtain PWM frequencies from 20
kHz to 250 kHz in 10 kHz steps and from 250 kHz to 500 kHz in 50 kHz steps. Higher
PWM frequencies can be obtained at the expense of resolution.
69
Timer/Counter1 Control
Register A – TCCR1A Bit
$30 ($50)
Read/Write
Initial Value
7
COM1A1
R/W
0
6
COM1A0
R/W
0
5
COM1B1
R/W
0
4
COM1B0
R/W
0
3
FOC1A
R/W
0
2
FOC1B
R/W
0
1
PWM1A
R/W
0
0
PWM1B
R/W
0
TCCR1A
• Bits 7, 6 – COM1A1, COM1A0: Comparator A Output Mode, Bits 1 and 0
The COM1A1 and COM1A0 control bits determine any output pin action following a
Compare Match with Compare Register A in Timer/Counter1. Output pin actions affect pin PB1 (OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. Note that OC1A is not connected in normal mode.
Table 32. Comparator A Mode Select
COM1A1 COM1A0 Description
1
1
0
0
0
1
0
1
Timer/Counter Comparator A disconnected from output pin OC1A.
Toggle the OC1A output line.
Clear the OC1A output line.
Set the OC1A output line.
In PWM mode, these bits have different functions. Refer to Table 35 on page 75 for a
detailed description.
• Bits 5, 4 – COM1B1, COM1B0: Comparator B Output Mode, Bits 1 and 0
The COM1B1 and COM1B0 control bits determine any output pin action following a
Compare Match with Compare Register B in Timer/Counter1. Output pin actions affect pin PB3 (OC1B). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. Note that OC1B is not connected in normal mode.
Table 33. Comparator B Mode Select
COM1B1 COM1B0 Description
1
1
0
0
0
1
0
1
Timer/Counter Comparator B disconnected from output pin OC1B.
Toggle the OC1B output line.
Clear the OC1B output line.
Set the OC1B output line.
In PWM mode, these bits have different functions. Refer to Table 35 on page 75 for a
detailed description.
• Bit 3 – FOC1A: Force Output Compare Match 1A
Writing a logical one to this bit forces a change in the Compare Match output pin PB1
(OC1A) according to the values already set in COM1A1 and COM1A0. If COM1A1 and
COM1A0 written in the same cycle as FOC1A, the new settings will be used. The Force
Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM1A1 and COM1A0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1A bit always reads as zero. FOC1A is not in use if PWM1A bit is set.
• Bit 2 – FOC1B: Force Output Compare Match 1B
70
ATtiny26(L)
1477G–AVR–03/05
Timer/Counter1 Control
Register B – TCCR1B
ATtiny26(L)
Writing a logical one to this bit forces a change in the Compare Match output pin PB3
(OC1B) according to the values already set in COM1B1 and COM1B0. If COM1B1 and
COM1B0 written in the same cycle as FOC1B, the new settings will be used. The Force
Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM1B1 and COM1B0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1B bit always reads as zero. FOC1B is not in use if PWM1B bit is set.
• Bit 1 – PWM1A: Pulse Width Modulator A Enable
When set (one) this bit enables PWM mode based on comparator OCR1A in
Timer/Counter1 and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C Register value.
• Bit 0 – PWM1B: Pulse Width Modulator B Enable
When set (one) this bit enables PWM mode based on comparator OCR1B in
Timer/Counter1 and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C Register value.
Bit
$2F ($4F)
Read/Write
Initial Value
7
CTC1
R/W
0
6
PSR1
R/W
0
R
0
5
–
R
0
4
–
3
CS13
R/W
0
2
CS12
R/W
0
1
CS11
R/W
0
0
CS10
R/W
0
TCCR1B
• Bit 7 – CTC1: Clear Timer/Counter on Compare Match
When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare match with OCR1C Register value. If the control bit is cleared,
Timer/Counter1 continues counting and is unaffected by a compare match.
• Bit 6 – PSR1: Prescaler Reset Timer/Counter1
When this bit is set (one), the Timer/Counter prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always read as zero.
• Bit 5..4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
71
1477G–AVR–03/05
• Bits 3..0 – CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0
The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.
Table 34. Timer/Counter1 Prescale Select
CS13 CS12 CS11 CS10
0 0 0 0
Description
Asynchronous Mode
Description
Synchronous Mode
Timer/Counter1 is stopped.
Timer/Counter1 is stopped.
1
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
PCK
PCK/2
PCK/4
PCK/8
PCK/16
PCK/32
PCK/64
PCK/128
PCK/256
PCK/512
PCK/1024
PCK/2048
PCK/4096
PCK/8192
PCK/16384
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
CK
CK/2
CK/4
CK/8
CK/16
CK/32
CK/64
CK/128
CK/256
CK/512
CK/1024
CK/2048
CK/4096
CK/8192
CK/16384
The Stop condition provides a Timer Enable/Disable function.
Timer/Counter1 – TCNT1
Bit
$2E ($4E)
Read/Write
Initial Value
7
MSB
R/W
0
6
R/W
0
5
R/W
0
4
R/W
0
3
R/W
0
2
R/W
0
1
R/W
0
0
LSB
R/W
0
TCNT1
This 8-bit register contains the value of Timer/Counter1.
Timer/Counter1 is realized as an up counter with read and write access. Due to synchronization of the CPU, Timer/Counter1 data written into Timer/Counter1 is delayed by one CPU clock cycle in synchronous mode and at most two CPU clock cycles for asynchronous mode.
Timer/Counter1 Output
Compare RegisterA – OCR1A Bit
$2D ($4D)
Read/Write
Initial Value
7
MSB
R/W
0
6
R/W
0
5
R/W
0
4
R/W
0
3
R/W
0
2
R/W
0
1
R/W
0
0
LSB
R/W
0
OCR1A
The Output Compare Register A is an 8-bit read/write register.
The Timer/Counter Output Compare Register A contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1A. A compare match does only occur if Timer/Counter1 counts to the OCR1A value. A soft-
72
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L) ware write that sets TCNT1 and OCR1A to the same value does not generate a compare match.
A compare match will set the compare interrupt flag OCF1A after a synchronization delay following the compare event.
Timer/Counter1 Output
Compare RegisterB – OCR1B Bit
$2C ($4C)
Read/Write
Initial Value
7
MSB
R/W
0
6
R/W
0
5
R/W
0
4
R/W
0
3
R/W
0
2
R/W
0
1
R/W
0
0
LSB
R/W
0
OCR1B
The Output Compare Register B is an 8-bit read/write register.
The Timer/Counter Output Compare Register B contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1A. A compare match does only occur if Timer/Counter1 counts to the OCR1B value. A software write that sets TCNT1 and OCR1B to the same value does not generate a compare match.
A compare match will set the compare interrupt flag OCF1B after a synchronization delay following the compare event.
Timer/Counter1 Output
Compare RegisterC – OCR1C Bit
$2B ($4B)
Read/Write
Initial Value
7
MSB
R/W
0
6
R/W
0
5
R/W
0
4
R/W
0
3
R/W
0
2
R/W
0
1
R/W
0
0
LSB
R/W
0
OCR1C
The Output Compare Register C is an 8-bit read/write register.
The Timer/Counter Output Compare Register C contains data to be continuously compared with Timer/Counter1. A compare match does only occur if Timer/Counter1 counts to the OCR1C value. A software write that sets TCNT1 and OCR1C to the same value does not generate a compare match.
If the CTC1 bit in TCCR1B is set, a compare match will clear TCNT1 and set an Overflow Interrupt Flag (TOV1). The flag is set after a synchronization delay following the compare event.
This register has the same function in normal mode and PWM mode.
PLL Control and Status
Register – PLLCSR Bit
$29 ($29)
Read/Write
Initial Value
R
0
7
–
R
0
6
–
R
0
5
–
R
0
4
–
R
0
3
–
2
PCKE
R/W
0
1
PLLE
R/W
0/1
0
PLOCK
R
0
PLLCSR
• Bit 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
• Bit 2 – PCKE: PCK Enable
The PCKE bit change the Timer/Counter1 clock source. When it is set, the asynchronous clock mode is enabled and fast 64 MHz PCK clock is used as Timer/Counter1 clock source. If this bit is cleared, the synchronous clock mode is enabled, and system clock CK is used as Timer/Counter1 clock source. This bit can be set only if PLLE bit is set. It is safe to set this bit only when the PLL is locked i.e., the PLOCK bit is 1.
• Bit 1 – PLLE: PLL Enable
73
1477G–AVR–03/05
When the PLLE is set, the PLL is started and if needed internal RC Oscillator is started as a PLL reference clock. If PLL is selected as a system clock source the value for this bit is always 1.
• Bit 0 – PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable PCK for Timer/Counter1. After the PLL is enabled, it takes about 64 µs/100 µs
(typical/worst case) for the PLL to lock.
Timer/Counter1 Initialization for Asynchronous Mode
To change Timer/Counter1 to the asynchronous mode, first enable PLL, and poll the
PLOCK bit until it is set, and then set the PCKE bit.
Timer/Counter1 in PWM Mode When the PWM mode is selected, Timer/Counter1 and the Output Compare Register C
– OCR1C form a dual 8-bit, free-running and glitch-free PWM generator with outputs on the PB1(OC1A) and PB3(OC1B) pins. Also inverted, non-overlapping outputs are available on pins PB0(OC1A) and PB2(OC1B), respectively. The non-overlapping output pairs (OC1A - OC1A and OC1B - OC1B) are never both set at the same time. This allows driving power switches directly. The non-overlap time is one prescaled clock cycle, and the high time is one cycle shorter than the low time.
The non-overlap time is generated by delaying the rising edge, i.e., the positive edge is one prescaled and one PCK cycle delayed and the negative edge is one PCK cycle delayed in the asynchronous mode. In the synchronous mode he positive edge is one prescaled and one CK cycle delayed and the negative edge is one CK cycle delayed.
The high time is also one prescaled cycle shorter in the both operation modes.
Figure 41. The Non-overlapping Output Pair
OC1x
OC1x x = A or B t non-overlap
When the counter value match the contents of OCR1A and OCR1B, the OC1A and
O C 1 B o u t p u t s a r e s e t o r c l e a r e d a c c o r d i n g t o t h e C O M 1 A 1 / C O M 1 A 0 o r
COM1B1/COM1B0 bits in the Timer/Counter1 Control Register A – TCCR1A, as shown
Timer/Counter1 acts as an up-counter, counting from $00 up to the value specified in the Output Compare Register (OCR1C), and starting from $00 up again. A compare match with OC1C will set an Overflow Interrupt Flag (TOV1) after a synchronization delay following the compare event.
74
ATtiny26(L)
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Table 35. Compare Mode Select in PWM Mode
COM1x1 COM1x0 Effect on Output Compare Pins
0
0
1
1
0
1
0
1
OC1x not connected.
OC1x not connected.
OC1x cleared on compare match. Set when TCNT1 = $01.
OC1x set one prescaled cycle after compare match. Cleared when
TCNT1 = $00.
OC1x cleared on compare match. Set when TCNT1 = $01.
OC1x not connected.
OC1x set one prescaled cycle after compare match. Cleared when
TCNT = $00
OC1x not connected.
Note that in PWM mode, writing to the Output Compare Registers OCR1A or OCR1B, the data value is first transferred to a temporary location. The value is latched into
OCR1A or OCR1B when the Timer/Counter reaches OCR1C. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1A or
OCR1B. See Figure 42 for an example.
Figure 42. Effects of Unsynchronized OCR Latching
Compare Value Changes
Counter Value
Compare Value
PWM Output OC1x
Synchronized OC1x Latch
Unsynchronized OC1x Latch
Compare Value changes
Counter Value
Compare Value
PWM Output OC1x
Glitch
During the time between the write and the latch operation, a read from OCR1A or
OCR1B will read the contents of the temporary location. This means that the most recently written value always will read out of OCR1A or OCR1B.
When OCR1A or OCR1B contain $00 or the top value, as specified in OCR1C Register, the output PB1(OC1A) or PB3(OC1B) is held low or high according to the settings of
COM1A1/COM1A0. This is shown in Table 36.
75
Table 36. PWM Outputs OCR1x = $00 or OCR1C, x = A or B
COM1x1
1
1
0
0
1
1
COM1x0
0
0
1
1
1
1
OCR1x
$00
OCR1C
$00
OCR1C
$00
OCR1C
Output OC1x
L
H
L
H
H
L
Output OC1x
H
L
Not connected
Not connected
Not connected
Not connected
In PWM mode, the Timer Overflow Flag – TOV1, is set as in normal Timer/Counter mode. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode, i.e., it is executed when TOV1 is set provided that Timer Overflow Interrupt and global interrupts are enabled. This also applies to the Timer Output Compare flags and interrupts.
The frequency of the PWM will be Timer Clock 1 Frequency divided by (OCR1C value + 1). See the following equation: f
PWM
=
( f
------------------------------------
OCR1C + 1
)
Resolution shows how many bit is required to express the value in the OCR1C Register.
It is calculated by following equation
Resolution
PWM
= log
2
(OCR1C + 1)
76
ATtiny26(L)
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Table 37. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode
PWM Frequency (kHz) Clock Selection CS13..CS10
OCR1C RESOLUTION (Bits)
300
350
400
450
500
180
190
200
250
60
70
80
90
20
30
40
50
140
150
160
170
100 PCK/4
110 PCK/4
120
130
PCK/4
PCK/2
PCK/2
PCK/2
PCK/2
PCK/2
PCK/16
PCK/16
PCK/8
PCK/8
PCK/8
PCK/4
PCK/4
PCK/4
PCK/2
PCK/2
PCK/2
PCK
PCK
PCK
PCK
PCK
PCK
0011
0011
0011
0010
0010
0010
0010
0010
0101
0101
0100
0100
0100
0011
0011
0011
0010
0010
0010
0001
0001
0001
0001
0001
0001
228
212
199
187
159
144
132
245
132
228
199
177
199
132
199
159
212
182
159
141
127
177
167
159
255
7.8
7.7
7.6
7.6
7.3
7.2
7.1
7.9
7.1
7.8
7.6
7.5
7.6
7.1
7.6
7.3
7.7
7.5
7.3
7.1
7.0
7.5
7.4
7.3
8.0
77
Watchdog Timer
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1
MHz. This is the typical value at V other V
CC
CC
= 5V. See characterization data for typical values at
levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted from 16 to 2048 ms. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the
ATtiny26(L) resets and executes from the Reset Vector. For timing details on the Watch-
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer
Control Register for details.
Figure 43. Watchdog Timer
Normally 1 MHz
WATCHDOG
PRESCLALER
WATCHDOG
RESET
WDP0
WDP1
WDP2
WDE
Watchdog Timer Control
Register – WDTCR
MCU RESET
Bit
$21 ($41)
Read/Write
Initial Value
R
0
7
–
R
0
6
–
R
0
5
–
4
WDCE
R/W
0
3
WDE
R/W
0
2
WDP2
R/W
0
1
WDP1
R/W
0
0
WDP0
R/W
0
WDTCR
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. In
Safety Level 1 and 2, this bit must also be set when changing the prescaler bits.
• Bit 3 – WDE: Watchdog Enable
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared
(zero) the Watchdog Timer function is disabled. WDE can be cleared only when the
WDCE bit is set(one). To disable an enabled Watchdog Timer, the following procedure must be followed:
78
ATtiny26(L)
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
1.
In the same operation, write a logical one to WDCE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts.
2.
Within the next four clock cycles, write a logical 0 to WDE. This disables the
Watchdog.
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the
Watchdog Timer is enabled. The different prescaling values and their corresponding
time-out periods are shown in Table 38.
Table 38. Watchdog Timer Prescale Select
(1)
WDP2 WDP1 WDP0
0 0 0
1
1
1
0
1
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
Number of WDT
Oscillator Cycles
16K (16,384)
32K (32,768)
64K (65,536)
128K (131,072)
256K (262,144)
512K (524,288)
1,024K (1,048,576)
2,048K (2,097,152)
Typical Time-out at V
CC
= 3.0V
17.1 ms
34.3 ms
68.5 ms
0.14 s
0.27 s
0.55 s
1.1 s
2.2 s
Typical Time-out at V
CC
= 5.0V
16.3 ms
32.5 ms
65 ms
0.13 s
0.26 s
0.52 s
1.0 s
2.1 s
Note: 1. The frequency of the Watchdog Oscillator is voltage dependent. The WDR – Watchdog Reset – instruction should always be executed before the Watchdog Timer is enabled. This ensures that the reset period will be in accordance with the Watchdog
Timer prescale settings. If the Watchdog Timer is enabled without reset, the Watchdog Timer may not start counting from zero.
79
Universal Serial
Interface – USI
Overview
The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space than solutions based on software only. Interrupts are included to minimize the processor load. The main features of the USI are:
• Two-wire Synchronous Data Transfer (Master or Slave, f
SCLmax
= f
CK
/16)
• Three-wire Synchronous Data Transfer (Master, f
SCKmax
= f
CK
/2, Slave f
SCKmax
= f
CK
/4)
• Data Received Interrupt
• Wakeup from Idle Mode
• In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
• Two-wire Start Condition Detector with Interrupt Capability
A simplified block diagram of the USI is shown on Figure 44.
Figure 44. Universal Serial Interface, Block Diagram
D Q
LE
PB1
DO
(Output only)
PB0
DI/SDA
(Input/Open Drain)
USIDR
4-bit Counter
3
2
1
0
3
2
1
0
[1]
TIM0 OVF
0
1
Two-wire Clock
Control Unit
CLOCK
HOLD
PB2
SCK/SCL
(Input/Open Drain)
USISR
2
80
ATtiny26(L)
USICR
The 8-bit Shift Register is directly accessible via the data bus and contains the incoming and outgoing data. The register has no buffering so the data must be read as quickly as possible to ensure that no data is lost. The most significant bit is connected to one of two output pins depending of the wire mode configuration. A transparent latch is inserted between the serial register output and output pin, which delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration.
The 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. Both the serial register and the counter are clocked simultaneously by the same clock source. This allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note that when an external clock source is selected the counter counts both clock edges. In this case the counter counts the number of edges, and not the number of bits. The clock can be selected from three different sources: the SCK pin, Timer 0 overflow, or from software.
The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus. It can also generate wait states by holding the clock pin low after a start condition is detected, or after the counter overflows.
1477G–AVR–03/05
ATtiny26(L)
Register Descriptions
USI Data Register – USIDR
Bit
$0F ($2F)
Read/Write
Initial Value
7
MSB
R/W
0
6
R/W
0
5
R/W
0
4
R/W
0
3
R/W
0
2
R/W
0
1
R/W
0
0
LSB
R/W
0
USIDR
The USI uses no buffering of the serial register, i.e., when accessing the Data Register
(USIDR) the serial register is accessed directly. If a serial clock occurs at the same cycle the register is written, the register will contain the value written and no shift is performed.
A (left) shift operation is performed depending of the USICS1..0 bits setting. The shift operation can be controlled by an external clock edge, by a Timer/Counter0 overflow, or directly by software using the USICLK strobe bit. Note that even when no wire mode is selected (USIWM1..0 = 0) both the external data input (DI/SDA) and the external clock input (SCK/SCL) can still be used by the Shift Register.
The output pin in use, DO or SDA depending on the wire mode, is connected via the output latch to the most significant bit (bit 7) of the Data Register. The output latch is open
(transparent) during the first half of a serial clock cycle when an external clock source is selected (USICS1 = 1), and constantly open when an internal clock source is used
(USICS1 = 0). The output will be changed immediately when a new MSB written as long as the latch is open. The latch ensures that data input is sampled and data output is changed on opposite clock edges.
Note that the corresponding Data Direction Register (DDRB2/1) to the pin must be set to one for enabling data output from the Shift Register.
USI Status Register – USISR
Bit
$0E ($2E)
Read/Write
Initial Value
7
USISIF
R/W
0
6
USIOIF
R/W
0
5
USIPF
R/W
0
4
USIDC
R
0
3
USICNT3
R/W
0
2
USICNT2
R/W
0
1
USICNT1
R/W
0
0
USICNT0
R/W
0
USISR
The Status Register contains interrupt flags, line status flags and the counter value.
Note that doing a Read-Modify-Write operation on USISR Register, i.e., using the SBI or
CBI instructions, will clear pending interrupt flags. It is recommended that register contents is altered by using the OUT instruction only.
• Bit 7 – USISIF: Start Condition Interrupt Flag
When Two-wire mode is selected, the USISIF flag is set (to one) when a start condition is detected. When output disable mode or Three-wire mode is selected and (USICSx =
0b11 & USICLK = 0) or (USICS = 0b10 & USICLK = 0), any edge on the SCK pin sets the flag.
An interrupt will be generated when the flag is set while the USISIE bit in USICR and the
Global Interrupt Enable Flag are set. The flag will only be cleared by writing a logical one to the USISIF bit. Clearing this bit will release the start detection hold of SCL in Two-wire mode.
A start condition interrupt will wakeup the processor from all four sleep modes.
• Bit 6 – USIOIF: Counter Overflow Interrupt Flag
This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to
0). An interrupt will be generated when the flag is set while the USIOIE bit in USICR and the Global Interrupt Enable Flag are set. The flag will only be cleared if a one is written
81
1477G–AVR–03/05
to the USIOIF bit. Clearing this bit will release the counter overflow hold of SCL in Twowire mode.
A counter overflow interrupt will wakeup the processor from Idle sleep mode.
• Bit 5 – USIPF: Stop Condition Flag
When Two-wire mode is selected, the USIPF flag is set (one) when a stop condition is detected. The flag is cleared by writing a one to this bit. Note that this is not an interrupt flag. This signal is useful when implementing Two-wire bus master arbitration.
• Bit 4 – USIDC: Data Output Collision
This bit is logical one when bit 7 in the Shift Register differs from the physical pin value.
The flag is only valid when Two-wire mode is used. This signal is useful when implementing Two-wire bus master arbitration.
• Bits 3..0 – USICNT3..0: Counter Value
These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or written by the CPU.
The 4-bit counter increments by one for each clock generated either by the external clock edge detector, by a Timer/Counter0 overflow, or by software using USICLK or
USITC strobe bits. The clock source depends of the setting of the USICS1..0 bits. For external clock operation a special feature is added that allows the clock to be generated by writing to the USITC strobe bit. This feature is enabled by write a one to the USICLK bit while setting an external clock source (USICS1 = 1).
Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input
(SCK/SCL) are can still be used by the counter.
USI Control Register – USICR
Bit
$0D ($2D)
Read/Write
Initial Value
7
USISIE
R/W
0
6
USIOIE
R/W
0
5
USIWM1
R/W
0
4
USIWM0
R/W
0
3
USICS1
R/W
0
2 1
USICS0 USICLK
R/W
0
W
0
0
USITC
W
0
USICR
The Control Register includes interrupt enable control, wire mode setting, clock select setting, and clock strobe.
• Bit 7 – USISIE: Start Condition Interrupt Enable
Setting this bit to one enables the Start Condition detector interrupt. If there is a pending interrupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will
immediately be executed. Refer to the description of “Bit 7 – USISIF: Start Condition
Interrupt Flag” on page 81 for further details.
When Two-wire mode is selected, the USISIF flag is set (to one) when a start condition is detected. When output disable mode or Three-wire mode is selected and (USICSx =
0b11 & USICLK = 0) or (USICS = 0b10 & USICLK = 0), any edge on the SCK pin sets the flag.
• Bit 6 – USIOIE: Counter Overflow Interrupt Enable
Setting this bit to one enables the Counter Overflow interrupt. If there is a pending interrupt when the USIOIE and the Global Interrupt Enable Flag is set to one, this will
immediately be executed. Refer to the description of “Bit 6 – USIOIF: Counter Overflow
Interrupt Flag” on page 81 for further details.
82
ATtiny26(L)
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
• Bit 5..4 – USIWM1..0: Wire Mode
These bits set the type of wire mode to be used. Basically only the function of the outputs are affected by these bits. Data and clock inputs are not affected by the mode selected and will always have the same function. The counter and Shift Register can therefore be clocked externally, and data input sampled, even when outputs are disabled. The relations between USIWM1..0 and the USI operation is summarized in
Table 39.
When Two-wire mode is selected, the USISIF flag is set (to one) when a start condition is detected. When output disable mode or Three-wire mode is selected and (USICSx =
0b11 & USICLK = 0) or (USICS = 0b10 & USICLK = 0), any edge on the SCK pin sets the flag.
Table 39. Relations between USIWM1..0 and the USI Operation
USIWM1 USIWM0 Description
0 0
0
1
1
1
0
1
Outputs, clock hold, and start detector disabled. Port pins operates as normal.
Three-wire mode. Uses DO, DI, and SCK pins.
The Data Output (DO) pin overrides the PORTB1 bit in the PORTB
Register in this mode. However, the corresponding DDRB1 bit still controls the data direction. When the port pin is set as input
(DDRB1 = 0) the pins pull-up is controlled by the PORTB1 bit.
The Data Input (DI) and Serial Clock (SCK) pins do not affect the normal port operation. When operating as master, clock pulses are software generated by toggling the PORTB2 bit while DDRB2 is set to output. The USITC bit in the USICR Register can be used for this purpose.
Two-wire mode. Uses SDA (DI) and SCL (SCK) pins
(1)
.
The Serial Data (SDA) and the Serial Clock (SCL) pins are bidirectional and uses open-collector output drives. The output drivers are enabled by the DDRB0/2 bit in the DDRB Register.
When the output driver is enabled for the SDA pin, the output driver will force the line SDA low if the output of the Shift Register or the PORTB0 bit in the PORTB Register is zero. Otherwise the SDA line will not be driven (i.e., it is released). When the SCL pin output driver is enabled the SCL line will be forced low if the PORTB2 bit in the PORTB
Register is zero, or by the start detector. Otherwise the SCL line will not be driven.
The SCL line is held low when a start detector detects a start condition and the output is enabled. Clearing the start condition flag (USISIF) releases the line. The SDA and SCL pin inputs is not affected by enabling this mode. Pull-ups on the SDA and SCL port pin are disabled in Two-wire mode.
Two-wire mode. Uses SDA and SCL pins.
Same operation as for the Two-wire mode described above, except that the SCL line is also held low when a counter overflow occurs, and is held low until the Counter Overflow Flag (USIOIF) is cleared.
Note: 1. The DI and SCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively to avoid confusion between the modes of operation.
83
84
ATtiny26(L)
• Bit 3..2 – USICS1..0: Clock Source Select
These bits set the clock source for the Shift Register and counter. The data output latch ensures that the output is changed at the opposite edge of the sampling of the data input (DI/SDA) when using external clock source (SCK/SCL). When software strobe or
Timer0 overflow clock option is selected the output latch is transparent and therefore the output is changed immediately. Clearing the USICS1..0 bits enables software strobe option. When using this option, writing a one to the USICLK bit clocks both the Shift
Register and the counter. For external clock source (USICS1 = 1), the USICLK bit is no longer used as a strobe, but selects between external clocking, and software clocking by the USITC strobe bit.
Table 40 shows the relationship between the USICS1..0 and USICLK setting and clock
source used for the Shift Register and the 4-bit counter.
Table 40. Relations between the USICS1..0 and USICLK Setting
USICS1 USICS0 USICLK
0 0 0
Shift Register Clock
Source
No Clock
4-bit Counter Clock
Source
No Clock
0 0 1
1
1
0
1
1
1
0
1
0
1
0
1
X
0
1
Software clock strobe
(USICLK)
Timer/Counter0 overflow
External, positive edge
External, negative edge
External, positive edge
External, negative edge
Software clock strobe
(USICLK)
Timer/Counter0 overflow
External, both edges
External, both edges
Software clock strobe
(USITC)
Software clock strobe
(USITC)
• Bit 1 – USICLK: Clock Strobe
Writing a one to this bit location strobes the Shift Register to shift one step and the counter to increment by one provided that the USICS1..0 bits are set to zero and by doing so selects the software clock strobe option. The output will change immediately when the clock strobe is executed i.e. in the same instruction cycle. The value shifted into the Shift Register is sampled the previous instruction cycle. The bit will be read as zero.
When an external clock source is selected (USICS1 = 1), the USICLK function is changed from a clock strobe to a Clock Select Register. Setting the USICLK bit in this
case will select the USITC strobe bit as clock source for the 4-bit counter (see Table 40).
• Bit 0 – USITC: Toggle Clock Port Pin
Writing a one to this bit location toggles the PORTB2 (SCK/SCL) value from either from
0 to 1, or 1 to 0. The toggling is independent of the DDRB2 setting, but if the PORTB2 value is to be shown on the pin the DDRB2 must be set as output (to one). This feature allows easy clock generation when implementing master devices. The bit will be read as zero.
When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of when the transfer is done when operating as a master device.
1477G–AVR–03/05
ATtiny26(L)
Functional Descriptions
Three-wire Mode The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but does not have the slave select (SS) pin functionality. However, this feature can be implemented in software if necessary. Pin names used by this mode are: DI, DO, and SCK.
Figure 45. Three-wire Mode Operation, Simplified Diagram
DO
PBx
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PBy
DI
PBz
SCK
SLAVE
PBx
DO
PBy
DI
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PBz
SCK
PORTBz
MASTER
Figure 45 shows two USI units operating in Three-wire mode, one as master and one as slave. The two shift Registers are interconnected in such way that after eight SCK clocks, the data in each register are interchanged. The same clock also increments the
USI’s 4-bit counter. The Counter Overflow (interrupt) flag, or USIOIF, can therefore be used to determine when a transfer is completed. The clock is generated by the master device software by toggling the PB2 pin via the PORTB Register or by writing a one to the USITC bit in USICR.
Figure 46. Three-wire Mode, Timing Diagram
CYCLE
( Reference ) 1 2 3 4
SCK
SCK
DO
DI MSB
MSB 6
6
5
5
4
4
5
3
3
6
2
2
7
1
1
8
LSB
LSB
A B C D E
The Three-wire mode timing is shown in Figure 46. At the top of the figure is a SCK cycle reference. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The SCK timing is shown for both external clock modes. In external clock mode
0 (USICS0 = 0), DI is sampled at positive edges, and DO is changed (Data Register is
85
1477G–AVR–03/05
SPI Master Operation
Example shifted by one) at negative edges. External clock mode 1 (USICS0 = 1) uses the opposite edges versus mode 0, i.e., samples data at negative and changes the output at positive edges. The USI clock modes corresponds to the SPI data mode 0 and 1.
Referring to the timing diagram (Figure 46.), a bus transfer involves the following steps:
1.
The slave device and master device sets up its data output and, depending on the protocol used, enables its output driver (mark A and B). The output is set up by writing the data to be transmitted to the serial Data Register. Enabling of the output is done by setting the corresponding bit in the port data direction register
(DDRB2). Note that point A and B does not have any specific order, but both must be at least one half SCK cycle before point C where the data is sampled.
This must be done to ensure that the data setup requirement is satisfied. The 4bit counter is reset to zero.
2.
The master generates a clock pulse by software toggling the SCK line twice (C and D). The bit value on the slave and master’s data input (DI) pin is sampled by the USI on the first edge (C), and the data output is changed on the opposite edge (D). The 4-bit counter will count both edges.
3.
Step 2. is repeated eight times for a comlpete register (byte) transfer.
4.
After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that the transfer is completed. The data bytes transferred must now be processed before a new transfer can be initiated. The overflow interrupt will wake up the processor if it is set to Idle mode. Depending of the protocol used the slave device can now set its output to high impedance.
The following code demonstrates how to use the USI module as a SPI master:
SPITransfer: out USIDR,r16 ldi out ldi r16,(1<<USIOIF)
USISR,r16 r16,(1<<USIWM0)+(1<<USICS1)+(1<<USICLK)+(1<<USITC)
SPITransfer_loop: out USICR,r16 sbis USISR,USIOIF rjmp SPITransfer_loop in ret r16,USIDR
The code is size optimized using only 8 instructions (+ ret). The code example assumes that the DO and SCK pins are enabled as output in the DDRB Register. The value stored in register r16 prior to the function is called is transferred to the slave device, and when the transfer is completed the data received from the slave is stored back into the r16 register.
The second and third instructions clears the USI Counter Overflow Flag and the USI counter value. The fourth and fifth instruction set Three-wire mode, positive edge Shift
Register clock, count at USITC strobe, and toggle SCK (PORTB2). The loop is repeated
16 times.
86
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
The following code demonstrates how to use the USI module as a SPI Master with maximum speed (fsck = fck/2):
SPITransfer_Fast: out USIDR,r16 ldi r16,(1<<USIWM0)+(0<<USICS0)+(1<<USITC) ldi r17,(1<<USIWM0)+(0<<USICS0)+(1<<USITC)+(1<<USICLK) out USICR,r16 ; MSB out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 ; LSB out USICR,r17 ret in r16,USIDR
SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI slave: init: ldi out r16,(1<<USIWM0)+(1<<USICS1)
USICR,r16
...
SlaveSPITransfer: out ldi
USIDR,r16 r16,(1<<USIOIF) out USISR,r16
SlaveSPITransfer_loop: sbis USISR,USIOIF rjmp SlaveSPITransfer_loop in ret r16,USIDR
The code is size optimized using only 8 instructions (+ ret). The code example assumes that the DO is configured as output and SCK pin is configured as input in the DDRB
Register. The value stored in register r16 prior to the function is called is transferred to
87
1477G–AVR–03/05
Two-wire Mode the master device, and when the transfer is completed the data received from the master is stored back into the r16 register.
Note that the first two instructions is for initialization only and needs only to be executed once.These instructions sets Three-wire mode and positive edge Shift Register clock.
The loop is repeated until the USI Counter Overflow Flag is set.
The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate limiting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA.
Figure 47. Two-wire Mode Operation, Simplified Diagram
VCC
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PBy
SDA
Two-wire Clock
Control Unit
HOLD
SCL
PBz
SCL
SLAVE
88
ATtiny26(L)
PBy
SDA
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PBz
SCL
PORTBz
MASTER
Figure 47 shows two USI units operating in Two-wire mode, one as master and one as slave. It is only the physical layer that is shown since the system operation is highly dependent of the communication scheme used. The main differences between the master and slave operation at this level, is the serial clock generation which is always done by the master, and only the slave uses the clock control unit. Clock generation must be implemented in software, but the shift operation is done automatically by both devices.
Note that only clocking on negative edge for shifting data is of practical use in this mode.
The slave can insert wait states at start or end of transfer by forcing the SCL clock low.
This means that the master must always check if the SCL line was actually released after it has generated a positive edge.
Since the clock also increments the counter, a counter overflow can be used to indicate that the transfer is completed. The clock is generated by the master by toggling the PB2 pin via the PORTB Register.
The data direction is not given by the physical layer. A protocol, like the one used by the
TWI-bus, must be implemented to control the data flow.
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Figure 48. Two-wire Mode, Typical Timing Diagram
SDA
SCL
S
1 - 7
ADDRESS
8
R/W
9
ACK
1 - 8
DATA
9
ACK
1 - 8
DATA
9
ACK
P
A B C D E F
Referring to the timing diagram (Figure 48.), a bus transfer involves the following steps:
1.
The a start condition is generated by the master by forcing the SDA low line while the SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift Register, or by setting the PORTB0 bit to zero. Note that DDRB0 must be set to one for the output to be enabled. The slave device’s start detector logic
(Figure 49.) detects the start condition and sets the USISIF flag. The flag can generate an interrupt if necessary.
2.
In addition, the start detector will hold the SCL line low after the master has forced an negative edge on this line (B). This allows the slave to wake up from sleep or complete its other tasks, before setting up the Shift Register to receive the address by clearing the start condition flag and reset the counter.
3.
The master set the first bit to be transferred and releases the SCL line (C). The slave samples the data and shift it into the serial register at the positive edge of the SCL clock.
4.
After eight bits are transferred containing slave address and data direction (read or write), the slave counter overflows and the SCL line is forced low (D). If the slave is not the one the master has addressed it releases the SCL line and waits for a new start condition.
5.
If the slave is addressed it holds the SDA line low during the acknowledgment cycle before holding the SCL line low again (i.e., the Counter Register must be set to 14 before releasing SCL at (D)). Depending of the R/W bit the master or slave enables its output. If the bit is set, a master read operation is in progress
(i.e., the slave drives the SDA line) The slave can hold the SCL line low after the acknowledge (E).
6.
Multiple bytes can now be transmitted, all in same direction, until a stop condition is given by the master (F). Or a new start condition is given.
If the slave is not able to receive more data it does not acknowledge the data byte it has last received. When the master does a read operation it must terminate the operation by force the acknowledge bit low after the last byte transmitted.
Figure 49. Start Condition Detector, Logic Diagram
SDA
SCL
Write( USISIF)
D Q
CLR
D Q
CLR
USISIF
CLOCK
HOLD
89
Start Condition Detector
Alternative USI Usage
Half-duplex Asynchronous
Data Transfer
4-bit Counter
12-bit Timer/Counter
Edge Triggered External
Interrupt
Software Interrupt
The start condition detector is shown in Figure 49. The SDA line is delayed (in the range of 50 to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled in Two-wire mode.
When Two-wire mode is selected, the USISIF flag is set (to one) when a start condition is detected. When output disable mode or Three-wire mode is selected and (USICSx =
0b11 & USICLK = 0) or (USICS = 0b10 & USICLK = 0), any edge on the SCK pin sets the flag.
The start condition detector is working asynchronously and can therefore wake up the processor from the Power-down sleep mode. However, the protocol used might have restrictions on the SCL hold time. Therefore, when using this feature in this case the
“Bit 7 – USISIF: Start Condition Interrupt Flag” on page 81 for further details.
When the USI unit is not used for serial communication, it can be set up to do alternative tasks due to its flexible design.
By utilizing the Shift Register in Three-wire mode, it is possible to implement a more compact and higher performance UART than by software only.
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the counter is clocked externally, both clock edges will generate an increment.
Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit counter.
By setting the counter to maximum value (F) it can function as an additional external interrupt. The overflow flag and interrupt enable bit are then used for the external interrupt. This feature is selected by the USICS1 bit.
The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.
90
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
Analog Comparator
The Analog Comparator compares the input values on the positive pin PA6 (AIN0) and negative pin PA7 (AIN1). When the voltage on the positive pin PA6 (AIN0) is higher than the voltage on the negative pin PA7 (AIN1), the Analog Comparator Output, ACO is set
(one). The comparator’s output can trigger a separate interrupt, exclusive to the Analog
Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in the Figure 50.
Figure 50. Analog Comparator Block Diagram
ACBG
PA6
(AIN0)
PA7
(AIN1)
MUX
ACME
ADC
MULTIPLEXER OUTPUT
Analog Comparator Control and Status Register – ACSR Bit
$08 ($28)
Read/Write
Initial Value
7
ACD
R/W
0
6
ACBG
R/W
0
5
ACO
R
X
4
ACI
R/W
0
3
ACIE
R/W
0
2
ACME
R/W
0
1
ACIS1
R/W
0
0
ACIS0
R/W
0
ACSR
• Bit 7 – ACD: Analog Comparator Disable
When this bit is set(one), the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR.
Otherwise an interrupt can occur when the bit is changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set (one), it selects internal bandgap reference voltage (1.18V) as the positive comparator input.
• Bit 5 – ACO: Analog Comparator Output
ACO is directly connected to the comparator output.
91
1477G–AVR–03/05
92
ATtiny26(L)
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Analog Comparator interrupt is activated. When cleared (zero), the interrupt is disabled.
• Bit 2 – ACME: Analog Comparator Multiplexer Enable
When the ACME bit is set (one) and the ADC is switched off (ADEN in ADCSR is zero),
MUX3...0 in ADMUX select the input pin to replace the negative input to the Analog
Comparator, as shown in Table 42 on page 93. If ACME is cleared (zero) or ADEN is set
(one), PA7(AIN1) is applied to the negative input to the Analog Comparator.
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator inter-
rupt. The different settings are shown in Table 41.
Table 41. ACIS1/ACIS0 Settings
(1)
ACIS1
0
ACIS0
0
Interrupt Mode
Comparator Interrupt on Output Toggle
0
1
1
1
0
1
Reserved
Comparator Interrupt on Falling Output Edge
Comparator Interrupt on Rising Output Edge
Note: 1. When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed.
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Table 42. Analog Comparator Input Selection (1)
ACME ADEN MUX3...0
(3)
Analog Comparator Negative Input
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
XXXX
XXXX
0000
0001
0010
0011
0100
0101
AIN1
AIN1
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
(2)
ADC7
(2)
ADC8
ADC9
ADC10
Undefined
Undefined
Undefined
Undefined
Undefined
Notes: 1. MUX4 does not affect Analog Comparator input selection.
2. Pin change interrupt on PA6 and PA7 is disabled if the Analog Comparator is enabled. This happens regardless of whether AIN1 or AIN0 has been replaced as inputs to the Analog Comparator.
3. The MUX3...0 selections go into effect after one clock cycle delay.
93
Analog to Digital
Converter
Features
• 10-bit Resolution
• ±2 LSB Absolute Accuracy
• 0.5 LSB Integral Non-linearity
• Optional Offset Cancellation
• 13 - 260 µs Conversion Time
• 11 Multiplexed Single Ended Input Channels
• 8 Differential Input Channels
• 7 Differential Input Channels with Optional Gain of 20x
• Optional Left Adjustment for ADC Result Readout
• 0 - AVCC ADC Input Voltage Range
• Selectable ADC Reference Voltage
• Free Running or Single Conversion Mode
• Interrupt on ADC Conversion Complete
• Sleep Mode Noise Canceler
The ATtiny26(L) features a 10-bit successive approximation ADC. The ADC is connected to an 11-channel Analog Multiplexer which allows eight differential voltage input combinations or 11 single-ended voltage inputs constructed from seven pins from Port A and four pins from Port B. Seven of the differential inputs are equipped with a programmable gain stage, providing amplification steps of 0 dB (1x) and 26 dB (20x) on the differential input voltage before the A/D conversion. There are four groups of three differential analog input channel selections. All input channels in each group share a common negative terminal, while another ADC input can be selected as the positive input terminal. The single-ended voltage inputs refer to 0V (GND).
The ADC contains a Sample and Hold Amplifier which ensures that the input voltage to the ADC is held at a constant level during conversion. A block diagram of the ADC is shown in Figure 51.
The ADC has an analog supply voltage pin, AVCC. The voltage on AVCC must not differ more than ±0.3V from V
CC
. See the paragraph “ADC Noise Canceling Techniques” on page 105 on how to connect these pins.
An internal reference voltage of nominally 2.56V is provided On-chip, and this reference may be externally decoupled at the AREF pin by a capacitor.
94
ATtiny26(L)
1477G–AVR–03/05
Operation
ATtiny26(L)
Figure 51. Analog to Digital Converter Block Schematic
ADC CONVERSION
COMPLETE IRQ
8-BIT DATA BUS
ADC MULTIPLEXER
SELECT (ADMUX)
ADC CTRL. & STATUS
REGISTER (ADCSR)
15
ADC DATA REGISTER
(ADCH/ADCL)
0
PRESCALER
MUX DECODER
ADC10
ADC9
ADC8
ADC3
ADC2
ADC1
ADC0
ADC7
ADC6
ADC5
ADC4
VCC
AREF
INTERNAL
2.56 V
REFERENCE
GND
INTERNAL 1.18 V
REFERENCE
POS.
INPUT
MUX
10-BIT DAC
CONVERSION LOGIC
SAMPLE & HOLD
COMPARATOR
-
+
SINGLE ENDED /
DIFFERENTIAL SELECTION
+
-
GAIN
AMPLIFIER
ADC
MULTIPLEXER OUTPUT
NEG.
INPUT
MUX
The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or and internal 2.56V reference voltage may be connected to the AREF pin by writing to the REFS bits in ADMUX.
The internal voltage reference may thus be decoupled by an external capacitor at the
AREF pin to improve noise immunity.
The analog input channel and differential gain are selected by writing to the MUX bits in
ADMUX. Any of the 11 ADC input pins ADC10..0, as well as GND and a fixed bandgap voltage reference of nominally 1.18V (V
BG
), can be selected as single ended inputs to the ADC. A selection of ADC input pins can be selected as positive and negative inputs to the differential gain amplifier.
If differential channels are selected, the differential gain stage amplifies the voltage difference between the selected input channel pair by the selected gain factor. Note that the voltage on the positive input terminal must be higher than on the negative input ter-
95
1477G–AVR–03/05
Prescaling and
Conversion Timing
minal, otherwise the gain stage will saturate at 0V (GND). This amplified value then becomes the analog input to the ADC. If single ended channels are used, the gain amplifier is bypassed altogether.
The ADC can operate in two modes – Single Conversion and Free Running mode. In
Single Conversion mode, each conversion will have to be initiated by the user. In Free
Running mode, the ADC is constantly sampling and updating the ADC Data Register.
The ADFR bit in ADCSR selects between the two available modes.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSR. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes.
A conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.
This bit stays high as long as the conversion is in progress and will be set to zero by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change.
The ADC generates a 10-bit result, which is presented in the ADC Data Registers,
ADCH and ADCL. By default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes.
When ADC access to the Data Registers is prohibited between reading of ADCH and
ADCL, the interrupt will trigger even if the result is lost.
Figure 52. ADC Prescaler
ADEN
CK
Reset
7-BIT ADC PRESCALER
ADPS0
ADPS1
ADPS2
ADC CLOCK SOURCE
96
ATtiny26(L)
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
The successive approximation circuitry requires an input clock frequency between
50 kHz and 200 kHz. The ADC module contains a prescaler, which divides the system clock to an acceptable ADC clock frequency.
The ADPS bits in ADCSR are used to generate a proper ADC clock input frequency from any chip clock frequency above 100 kHz. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSR. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low.
When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at the following rising edge of the ADC clock cycle. If differential channels are selected, the conversion will only start at every other rising edge of the ADC clock cycle after ADEN was set.
A normal conversion takes 13 ADC clock cycles. In certain situations, the ADC needs more clock cycles to initialization and minimize offset errors. Extended conversions take
25 ADC clock cycles and occur as the first conversion after the ADC is switched on
(ADEN in ADCSR is set).
Special care should be taken when changing differential channels. Once a differential channel has been selected, the gain stage may take as much as 125 µs to stabilize to the new value. Thus conversions should not be started within the first 125 µs after selecting a new differential channel. Alternatively, conversions results obtained within this period should be discarded. The same settling time should be observed for the first differential conversion after changing ADC reference (by changing the REFS1:0 bits in
ADMUX).
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC clock cycles after the start of an extended conversion. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge. In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. Using Free Running mode and an
ADC clock frequency of 200 kHz gives the lowest conversion time, 65 µs , equivalent to
15 kSPS. For a summary of conversion times, see Table 43.
Figure 53. ADC Timing Diagram, Extended Conversion (Single Conversion Mode)
Extended Conversion
Next
Conversion
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25
MUX and REFS
Update
Sample & Hold
Conversion
Complete
1 2 3
MSB of Result
LSB of Result
MUX and REFS
Update
97
Figure 54. ADC Timing Diagram, Single Conversion
One Conversion
1 2 3 4 5 6 7 8 9 10 11 12 13
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
Sample & Hold
MUX and REFS
Update
Conversion
Complete
Figure 55. ADC Timing Diagram, Free Running Conversion
One Conversion Next Conversion
Cycle Number
11
ADC Clock
12 13 1
ADSC
ADIF
ADCH
ADCL
2 3
MSB of Result
LSB of Result
4
Conversion
Complete
Sample & Hold
MUX and REFS
Update
Next Conversion
1 2 3
MSB of Result
LSB of Result
MUX and REFS
Update
Changing Channel or
Reference Selection
Table 43. ADC Conversion Time
Condition
Sample & Hold (Cycles from
Start of Conversion)
Extended conversion
Normal conversions
13.5
1.5
Conversion
Time (Cycles)
25
13
Conversion
Time (µs)
125 - 500
65 - 260
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started.
Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in ADCSR is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or reference selection values to ADMUX until one
ADC clock cycle after ADSC is written.
98
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
Special care should be taken when changing differential channels. Once a differential channel has been selected, the gain stage may take as much as 125 µs to stabilize to the new value. Thus conversions should not be started within the first 125 µs after selecting a new differential channel. Alternatively, conversion results obtained within this period should be discarded.
The same settling time should be observed for the first differential conversion after changing ADC reference (by changing the REFS1:0 bits in ADMUX).
ADC Noise Canceler
Function
The ADC features a noise canceler that enables conversion during ADC Noise Reduc-
tion mode (see “Power Management and Sleep Modes” on page 36) to reduce noise
induced from the CPU core and other I/O peripherals. If other I/O peripherals must be active during conversion, this mode works equivalently for Idle mode. To make use of this feature, the following procedure should be used:
1.
Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled.
ADEN = 1
ADSC = 0
ADFR = 0
ADIE = 1
2.
Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted.
3.
If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine.
ADC Conversion Result
After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH).
For single ended conversion, the result is
ADC =
V
⋅
1024
--------------------------
V
REF where V
IN
is the voltage on the selected input pin and V
REF
the selected voltage refer-
ence (see Table 45 on page 101 and Table 46 on page 102). 0x000 represents analog
ground, and 0x3FF represents the selected reference voltage minus one LSB.
If differential channels are used, the result is
ADC =
(
V – V
) ⋅
GAIN
⋅
1024
---------------------------------------------------------------------------
V
REF where V
POS
is the voltage on the positive input pin, V
NEG
the voltage on the negative input pin, GAIN the selected gain factor, and V
REF
the selected voltage reference. Keep in mind that V
POS
must be higher than V
NEG
, otherwise, the ADC value will saturate at
0x000. Figure 56 shows the decoding of the differential input range.
Table 44 shows the resulting output codes if the differential input channel pair (ADCn -
ADCm) is selected with a gain of GAIN and a reference voltage of V
REF
.
99
1477G–AVR–03/05
100
ATtiny26(L)
Figure 56. Differential Measurement Range
Output Code
0x3FF
0x000
0
V
REF
/GAIN
Differential Input
Voltage (Volts)
Table 44. Correlation Between Input Voltage and Output Codes
V
ADCn
V
ADCm
+ V
REF
/GAIN
V
ADCm
+ (1023/1024) V
REF
/GAIN
V
ADCm
+ (1022/1024) V
REF
/GAIN
...
V
ADCm
+ (1/1024) V
REF
/GAIN
V
ADCm
Read code
0x3FF
0x3FF
0x3FE
...
0x001
0x000
...
1
Corresponding decimal value
1023
1023
1022
0
Example:
ADMUX = 0xEB (ADC0 - ADC1, 20x gain, 2.56V reference, left adjusted result)
Voltage on ADC0 is 400 mV, voltage on ADC1 is 300 mV.
ADCR = 1024 * 20 * (400 - 300) / 2560 = 800 = 0x320
ADCL will thus read 0x00, and ADCH will read 0xC8. Writing zero to ADLAR right adjusts the result: ADCL = 0x20, ADCH = 0x03.
1477G–AVR–03/05
ATtiny26(L)
ADC Multiplexer Selection
Register – ADMUX Bit
$07 ($27)
Read/Write
Initial Value
7
REFS1
R/W
0
6
REFS0
R/W
0
5
ADLAR
R/W
0
4
MUX4
R/W
0
3
MUX3
R/W
0
2
MUX2
R/W
0
1
MUX1
R/W
0
0
MUX0
R/W
0
ADMUX
• Bit 7, 6 – REFS1, REFS0: Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in Table 45. If these bits
are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). The user should disregard the first conversion result after changing these bits to obtain maximum accuracy. If differential channels are used, using AVCC or an external AREF higher than (AVCC - 0.2V) is not recommended, as this will affect ADC accuracy. The internal voltage reference may not be used if an external reference voltage is being applied to the AREF pin.
Table 45. Voltage Reference Selections for ADC
REFS1 REFS0 Voltage Reference Selection
0
0
1
1
0
1
0
1
AVCC
AREF (PA3), Internal Vref turned off.
Internal Voltage Reference (2.56 V), AREF pin (PA3) not connected.
Internal Voltage Reference (2.56 V) with external capacitor at AREF pin
(PA3).
• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data
Register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately,
regardless of any ongoing conversions. For a complete description of this bit, see “ADC
Data Register – ADCL and ADCH” on page 104.
• Bits 4..0 – MUX4..MUX0: Analog Channel and Gain Selection Bits
The value of these bits selects which combination of analog inputs are connected to the
ADC. These bits also select the gain for the differential channels. See Table 46 for
details.
If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
101
1477G–AVR–03/05
102
ATtiny26(L)
10111
11000
11001
11010
11011
(1)
11100
11101
11110
11111
01111
10000
10001
(1)
10010
10011
10100
10101
10110 (1)
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
(1)
01110
Table 46. Input Channel and Gain Selections
MUX4..0
00000
Single Ended
Input
ADC0
Positive Differential
Input
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10
N/A
N/A
N/A
N/A
1.18V (V
BG
)
0V (GND)
ADC4
ADC4
ADC4
ADC5
ADC6
ADC6
ADC8
ADC8
ADC0
ADC0
ADC1
ADC2
ADC2
ADC2
ADC3
ADC4
ADC9
ADC10
ADC10
Negative Differential
Input
N/A
N/A
Gain
Note:
1. For offset measurements only. See “Offset Compensation Schemes” on page 105.
ADC3
ADC5
ADC5
ADC5
ADC5
ADC5
ADC9
ADC9
ADC1
ADC1
ADC1
ADC1
ADC1
ADC3
ADC3
ADC3
ADC9
ADC9
ADC9
20x
1x
20x
1x
1x
20x
1x
20x
1x
1x
20x
20x
20x
1x
20x
20x
20x
20x
1x
1477G–AVR–03/05
ATtiny26(L)
ADC Control and Status
Register – ADCSR Bit
$06 ($26)
Read/Write
Initial Value
7
ADEN
R/W
0
6
ADSC
R/W
0
5
ADFR
R/W
0
4
ADIF
R/W
0
3
ADIE
R/W
0
2
ADPS2
R/W
0
1
ADPS1
R/W
0
0
ADPS0
R/W
0
ADCSR
• Bit 7 – ADEN: ADC Enable
Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, a logical “1” must be written to this bit to start each conversion. In Free Running mode, a logical “1” must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if
ADSC is written at the same time as the ADC is enabled, a dummy conversion will precede the initiated conversion. This dummy conversion performs initialization of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion,
ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect.
• Bit 5 – ADFR: ADC Free Running Select
When this bit is set (one) the ADC operates in Free Running mode. In this mode, the
ADC samples and updates the Data Registers continuously. Clearing this bit (zero) will terminate Free Running mode.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the Ibit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.
103
1477G–AVR–03/05
• Bits 2..0 – ADPS2..0: ADC Prescaler Select Bits
These bits determine the division factor between the CK frequency and the input clock to the ADC.
Table 47. ADC Prescaler Selections
ADPS2
0
ADPS1
0
ADPS0
0
Division Factor
2
1
1
1
0
1
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
8
16
2
4
32
64
128
ADC Data Register – ADCL and ADCH
ADLAR = 0
ADLAR = 1
Bit
$05 ($25)
$04 ($24)
Read/Write
Initial Value 0
0
R
R
15
–
ADC7
7
0
0
R
R
14
–
ADC6
6
0
0
R
R
13
–
ADC5
5
0
0
R
R
12
–
ADC4
4
0
0
R
R
11
–
ADC3
3
0
0
R
R
10
–
ADC2
2
0
0
R
R
9
ADC9
ADC1
1
0
0
R
R
8
ADC8
ADC0
0
ADCH
ADCL
Bit
$05 ($25)
$04 ($24)
Read/Write
Initial Value 0
0
R
R
15
ADC9
ADC1
7
0
0
R
R
14
ADC8
ADC0
6
0
0
R
R
13
ADC7
–
5
0
0
R
R
12
ADC6
–
4
0
0
R
R
11
ADC5
–
3
0
0
R
R
10
ADC4
–
2
0
0
R
R
9
ADC3
–
1
0
0
R
R
8
ADC2
–
0
ADCH
ADCL
When an ADC conversion is complete, the result is found in these two registers. The
ADLAR bit in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH.
• ADC9..0: ADC Conversion Result
These bits represent the result from the conversion. For differential channels, this is the
absolute value after gain adjustment, as indicated in Table 46 on page 102. For single
ended channels, $000 represents analog ground, and $3FF represents the selected reference voltage minus one LSB.
104
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
Scanning Multiple
Channels
ADC Noise Canceling
Techniques
Offset Compensation
Schemes
Since change of analog channel always is delayed until a conversion is finished, the
Free Running mode can be used to scan multiple channels without interrupting the converter. Typically, the ADC Conversion Complete interrupt will be used to perform the channel shift. However, the user should take the following fact into consideration:
The interrupt triggers once the result is ready to be read. In Free Running mode, the next conversioin will start immediately when the interrupt triggers. If ADMUX is changed after the interrupt triggers, the next conversion has already started, and the old setting is used.
Digital circuitry inside and outside the ATtiny26(L) generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques:
1.
The analog part of the ATtiny26(L) and all analog components in the application should have a separate analog ground plane on the PCB. This ground plane is connected to the digital ground plane via a single point on the PCB.
2.
Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks.
3.
The AVCC pin on the ATtiny26(L) should be connected to the digital V
CC voltage via an LC network as shown in Figure 57.
supply
4.
Use the ADC noise canceler function to reduce induced noise from the CPU.
5.
If some pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress in that port.
The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as possible. The remaining offset in the analog path can be measured directly by selecting the same channel for both differential inputs. This offset residue can be then subtracted in software from the measurement results. Using this kind of software based offset correction, offset on any channel can be reduced below one LSB.
105
1477G–AVR–03/05
Figure 57. ADC Power Connections
(MOSI/DI/SDA/OC1A) PB0
1
(MISO/DO/OC1A) PB1 2
(SCK/SCL/OC1B) PB2
3
(OC1B) PB3
4
VCC
5
GND 6
(ADC7/XTAL1) PB4 7
(ADC8/XTAL2) PB5 8
(ADC9/INT0/T0) PB6 9
(ADC10/RESET) PB7 10
ATtiny26/L
PA0 (ADC0)
19 PA1 (ADC1)
18 PA2 (ADC2)
17 PA3 (AREF)
16
GND
15
AVCC
14 PA4 (ADC3)
13 PA5 (ADC4)
12 PA6 (ADC5/AIN0)
11 PA7 (ADC6/AIN1)
106
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
Memory
Programming
Program and Data
Memory Lock Bits
The ATtiny26 provides two Lock bits which can be left unprogrammed (“1”) or can be
programmed (“0”) to obtain the additional features listed in Table 49. The Lock bits can
only be erased to “1” with the Chip Erase command.
Table 48. Lock Bit Byte
(1)
Lock Bit Byte Bit No
LB2
LB1
1
0
3
2
5
4
7
6
–
–
–
–
Description
–
–
Lock bit
Lock bit
Default Value
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
Note: 1. “1” means unprogrammed, “0” means programmed
Table 49. Lock Bit Protection Modes
Memory Lock Bits
LB Mode LB2
(2)
LB1
(2)
1 1 1
Protection Type
No memory lock features enabled.
2
3
1
0
0
0
Further programming of the Flash and EEPROM is disabled in parallel and serial programming mode. The
Fuse bits are locked in both serial and parallel programming mode.
(1)
Further programming and verification of the Flash and
EEPROM is disabled in parallel and serial programming mode. The Fuse bits are locked in both serial and parallel programming mode.
(1)
Notes: 1. Program the Fuse bits before programming the Lock bits.
2. “1” means unprogrammed, “0” means programmed
107
1477G–AVR–03/05
Fuse Bits
108
ATtiny26(L)
The ATtiny26 has two Fuse bytes. Table 50 and Table 51 describe briefly the functional-
ity of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed.
Table 50. Fuse High Byte
Fuse High Byte Bit No Description
7
6
–
–
SPIEN (1)
EESAVE
BODLEVEL
5
4
3
2
1
–
Select if PB7 is I/O pin or
RESET pin
Enable Serial Program and Data Downloading
EEPROM memory is preserved through the Chip
Erase
Brown out detector trigger level
Default Value
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed, PB7 is
RESET pin)
0 (programmed, SPI prog. enabled)
1 (unprogrammed, EEPROM not preserved)
1 (unprogrammed)
BODEN 0
Brown out detector enable
1 (unprogrammed, BOD disabled)
Notes: 1. The SPIEN Fuse is not accessible in serial programming mode.
2. When programming the RSTDISBL Fuse, Parallel Programming has to be used to change fuses or perform further programming.
Table 51. Fuse Low Byte
Fuse Low Byte Bit No Description
PLLCK
CKOPT
(3)
7
6
Use PLL for internal clock
Oscillator options
SUT1 5 Select start-up time
SUT0
CKSEL3
CKSEL2
CKSEL1
CKSEL0
2
1
4
3
0
Select start-up time
Select Clock source
Select Clock source
Select Clock source
Select Clock source
Default Value
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed) (1)
0 (programmed)
(1)
0 (programmed) (2)
0 (programmed)
(2)
0 (programmed) (2)
1 (unprogrammed)
(2)
Notes:
1. The default value of SUT1..0 results in maximum start-up time. See Table 12 on page
2. The default setting of CKSEL3..0 results in internal RC Oscillator at 1 MHz. See
Table 3 on page 24 for details.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the
Lock bits.
1477G–AVR–03/05
Latching of Fuses
Signature Bytes
Calibration Byte
ATtiny26(L)
The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in normal mode.
All Atmel microcontrollers have a three-byte signature code which identifies the device.
This code can be read in both serial and parallel mode, also when the device is locked.
The three bytes reside in a separate address space.
For the ATtiny26 the signature bytes are:
1.
$000: $1E (indicates manufactured by Atmel).
2.
$001: $91 (indicates 2KB Flash memory).
3.
$002: $09 (indicates ATtiny26 device when $001 is $91).
The ATtiny26 stores four different calibration values for the internal RC Oscillator. These bytes resides in the signature row high byte of the addresses 0x0000, 0x0001, 0x0002, and 0x0003 for 1, 2, 4, and 8 MHz respectively. During Reset, the 1 MHz value is automatically loaded into the OSCCAL Register. If other frequencies are used, the
calibration value has to be loaded manually, see “Oscillator Calibration Register – OSC-
Page Size
Table 52. No. of Words in a Page and no. of Pages in the Flash
Flash Size
1K words (2K bytes)
Page Size PCWORD No. of Pages PCPAGE PCMSB
16 words PC[3:0] 64 PC[9:4] 9
Parallel Programming
Parameters, Pin
Mapping, and
Commands
Signal Names
Table 53. No. of Words in a Page and no. of Pages in the EEPROM
EEPROM Size
128 bytes
Page Size
4 bytes
PCWORD
EEA[1:0]
No. of Pages
32
PCPAGE
EEA[7:0]
EEAMSB
7
This section describes how to parallel program and verify Flash Program memory,
EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATtiny26. Pulses are assumed to be at least 250 ns unless otherwise noted.
In this section, some pins of the ATtiny26 are referenced by signal names describing their functionality during parallel programming, see Figure 58 and Table 54. Pins not described in the following table are referenced by pin names.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a posi-
tive pulse. The bit coding is shown in Table 56.
When pulsing WR or OE, the command loaded determines the action executed. The dif-
ferent Commands are shown in Table 57.
109
1477G–AVR–03/05
Figure 58. Parallel Programming
WR
XA0
XA1/BS2
PAGEL/BS1
OE
RDY/BSY
+12 V
+5V
PB0
PB1
PB2
PB3
PB5
PB6
RESET
XTAL1/PB4
GND
VCC
AVCC
PA7: PA0
+5V
DATA
110
ATtiny26(L)
Table 54. Pin Name Mapping
Signal Name in
Programming Mode Pin Name I/O Function
WR
XA0
XA1/BS2
(1)
PB0
PB1
PAGEL/BS1
(1)
OE
RDY/BSY
DATA
PB2
PB3
PB5
PB6
PA7:0
I
I Write Pulse (Active low)
I XTAL Action Bit 0
XTAL Action Bit 1 multiplexed with Byte Select 2
(“0” selects low byte, “1” selects 2’nd high byte)
I
Program Memory and EEPROM data Page Load multiplexed with Byte Select 1 (“0” selects low byte, “1” selects high byte).
I Output Enable (Active low)
O
0: Device is busy programming, 1: Device is ready for new command
I/O Bidirectional Data bus (Output when OE is low)
Note: 1. The pin is used for two different control signals. In the description below, normally only one of the signals is referred. E.g., “give BS1 a positive pulse” equals “give
PAGEL/BS1 a positive pulse”.
Table 55. Pin Values used to Enter Programming Mode
Pin
PAGEL/BS1
Symbol
Prog_enable[3]
XA1/BS2
XA0
WR
Prog_enable[2]
Prog_enable[1]
Prog_enable[0]
Value
0
0
0
0
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Table 56. XA1 and XA0 Coding (1)
XA1 XA0 Action when XTAL1 is Pulsed
0
0
1
1
0
1
0
1
Load Flash or EEPROM Address (High or low address byte determined by
BS1).
Load Data (High or Low data byte for Flash determined by BS1).
Load Command
No Action, Idle
Note: 1. [XA1, XA0] = 0b11 is “No Action, Idle”. As long as XTAL1 is not pulsed, the Command, Address, and Data Registers remain unchanged. Therefore, there are no problems using BS2 as described below even though BS2 is multiplexed with XA1.
BS2 is only asserted when reading the fuses (OE is low) and XTAL1 is not pulsed.
Table 57. Command Byte Bit Coding
Command Byte Command Executed
1000 0000
0100 0000
0010 0000
0001 0000
0001 0001
0000 1000
0000 0100
0000 0010
0000 0011
Chip Erase
Write Fuse Bits
Write Lock Bits
Write Flash
Write EEPROM
Read Signature Bytes and Calibration Byte
Read Fuse and Lock Bits
Read Flash
Read EEPROM
111
Parallel Programming
Enter Programming Mode
Considerations for Efficient
Programming
The following algorithm puts the device in parallel programming mode:
1.
Apply 4.5 - 5.5 V between V
CC
and GND, and wait for at least 100 µs.
2.
Set RESET to “0” and toggle XTAL1 at least 6 times.
3.
Set the Prog_enable pins listed in Table 55 on page 110 to “0000” and wait at
least 100 ns.
4.
Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after +12V has been applied to RESET, will cause the device to fail entering programming mode.
Note: If the RESET pin is disabled by programming the RSTDISBL Fuse, it may not be possible to follow the proposed algorithm above. The same may apply when External Crystal or
External RC configuration is selected because it is not possible to apply qualified XTAL1 pulses. In such cases, the following algorithm should be followed:
1.
Set Prog_enable pins listed in Table 55 on page 110 to “0000”.
2.
Apply 4.5 - 5.5V between V
CC
and GND simultanously as 11.5 - 12.5V is applied to RESET.
3.
Wait 100 ns.
4.
Re-program the fuses to ensure that External Clock is selected as clock source
(CKSEL3:0 = 0b0000) and RESET pin is activated (RSTDISBL unprogrammed).
If Lock bits are programmed, a Chip Erase command must be executed before changing the fuses.
5.
Exit Programming mode by power the device down or by bringing RESET pin to
0b0.
6.
Entering Programming mode with the original algorithm, as described above.
The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered.
• The command needs only be loaded once when writing or reading multiple memory locations.
• Skip writing the data value $FF, that is the contents of the entire EEPROM (unless the EESAVE Fuse is programmed) and Flash after a Chip Erase.
• Address high byte needs only be loaded before programming or reading a new 256word window in Flash or 256-byte EEPROM. This consideration also applies to
Signature bytes reading.
112
ATtiny26(L)
1477G–AVR–03/05
Chip Erase
Programming the Flash
ATtiny26(L)
The Chip Erase will erase the Flash and EEPROM
(1)
memories plus Lock bits. The Lock bits are not reset until the program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are reprogrammed.
Note: 1. The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.
Load Command “Chip Erase”
1.
Set XA1, XA0 to “10”. This enables command loading.
2.
Set BS1 to “0”.
3.
Set DATA to “1000 0000”. This is the command for Chip Erase.
4.
Give XTAL1 a positive pulse. This loads the command.
5.
Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.
6.
Wait until RDY/BSY goes high before loading a new command.
The Flash is organized in pages, see Table 52 on page 109. When programming the
Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory:
A. Load Command "Write Flash"
1.
Set XA1, XA0 to “10”. This enables command loading.
2.
Set BS1 to “0”.
3.
Set DATA to “0001 0000”. This is the command for Write Flash.
4.
Give XTAL1 a positive pulse. This loads the command.
B. Load Address Low byte
1.
Set XA1, XA0 to “00”. This enables address loading.
2.
Set BS1 to “0”. This selects low address.
3.
Set DATA = Address low byte ($00 - $FF).
4.
Give XTAL1 a positive pulse. This loads the address low byte.
C. Load Data Low Byte
1.
Set XA1, XA0 to “01”. This enables data loading.
2.
Set DATA = Data low byte ($00 - $FF).
3.
Give XTAL1 a positive pulse. This loads the data byte.
D. Load Data High Byte
1.
Set BS1 to “1”. This selects high data byte.
2.
Set XA1, XA0 to “01”. This enables data loading.
3.
Set DATA = Data high byte ($00 - $FF).
4.
Give XTAL1 a positive pulse. This loads the data byte.
E. Repeat B through D until the entire buffer is filled or until all data within the page is loaded.
While the lower bits in the address are mapped to words within the page, the higher bits address the pages within the FLASH. This is illustrated in Figure 59 on page 114. Note that if less than 8 bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a page write.
113
1477G–AVR–03/05
114
ATtiny26(L)
F. Load Address High byte
1.
Set XA1, XA0 to “00”. This enables address loading.
2.
Set BS1 to “1”. This selects high address.
3.
Set DATA = Address high byte ($00 - $03).
4.
Give XTAL1 a positive pulse. This loads the address high byte.
G. Program Page
1.
Set BS1 to “0”.
2.
Give WR a negative pulse. This starts programming of the entire page of data.
RDY/BSYgoes low.
3.
Wait until RDY/BSY goes high. (See Figure 60 for signal waveforms.)
H. Repeat B through G until the entire Flash is programmed or until all data has been programmed.
I. End Page Programming
1.
Set XA1, XA0 to “10”. This enables command loading.
2.
Set DATA to “0000 0000”. This is the command for No Operation.
3.
Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset.
Figure 59. Addressing the Flash which is Organized in Pages
(1)
PROGRAM
COUNTER
PCMSB
PCPAGE
PAGEMSB
PCWORD
PAGE ADDRESS
WITHIN THE FLASH
WORD ADDRESS
WITHIN A PAGE
PROGRAM MEMORY
PAGE
PAGE
INSTRUCTION WORD
PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
Note: 1. PCPAGE and PCWORD are listed in Table 52 on page 109.
1477G–AVR–03/05
ATtiny26(L)
Figure 60. Programming the Flash Waveforms
(1)
E
Programming the EEPROM
A
$10
B C D B C D F
ADDR. LOW DATA LOW DATA HIGH ADDR. LOW DATA LOW DATA HIGH ADDR. HIGH
G
XX
DATA
XA1/BS2
XA0
PAGEL/BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
Note: 1. “XX” is don’t care. The letters refer to the programming description above.
The EEPROM is organized in pages, see Table 53 on page 109. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM
data memory is as follows (refer to “Programming the Flash” on page 113 for details on
Command, Address and Data loading):
1.
A: Load Command “0001 0001”.
2.
B: Load Address Low Byte ($00 - $FF).
3.
C: Load Data ($00 - $FF).
J: Repeat 2 and 3 until the entire buffer is filled
K: Program EEPROM page
1.
Set BS1 to “0”.
2.
Give WR a negative pulse. This starts programming of the EEPROM page.
RDY/BSY goes low.
3.
Wait until to RDY/BSY goes high before programming the next page.
(See Figure 61 for signal waveforms.)
115
1477G–AVR–03/05
Figure 61. Programming the EEPROM Waveforms
J
Reading the Flash
Reading the EEPROM
Programming the Fuse Low
Bits
A
$11
B
ADDR. LOW
C
DATA
B
ADDR. LOW
C
DATA XX
K
DATA
XA1/BS2
XA0
PAGEL/BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
The algorithm for reading the Flash memory is as follows (refer to “Programming the
Flash” on page 113 for details on Command and Address loading):
1.
A: Load Command “0000 0010”.
2.
F: Load Address High Byte ($00 - $03).
3.
B: Load Address Low Byte ($00 - $FF).
4.
Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.
5.
Set BS1 to “1”. The Flash word high byte can now be read at DATA.
6.
Set OE to “1”.
The algorithm for reading the EEPROM memory is as follows (refer to “Programming the
Flash” on page 113 for details on Command and Address loading):
1.
A: Load Command “0000 0011”.
2.
B: Load Address Low Byte ($00 - $FF).
3.
Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at
DATA.
4.
Set OE to “1”.
1.
A: Load Command “0100 0000”.
2.
C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3.
Set BS1 and BS2 to “0”.
4.
Give WR a negative pulse and wait for RDY/BSY to go high.
116
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
Programming the Fuse High
Bits
1.
A: Load Command “0100 0000”.
2.
C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3.
Set BS1 to “1” and BS2 to “0”. This selects high data byte.
4.
Give WR a negative pulse and wait for RDY/BSY to go high.
5.
Set BS1 to “0”. This selects low data byte.
Figure 62. Programming the Fuse Waveforms
Write Fuse Low Byte
DATA
A
$40
C
DATA XX
A
$40
C
DATA
Write Fuse High Byte
XX
XA1/BS2
XA0
PAGEL/BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
Programming the Lock Bits
Reading the Fuse and Lock
Bits
The algorithm for programming the Lock bits is as follows (refer to “Programming the
Flash” on page 113 for details on Command and Data loading):
1.
A: Load Command “0010 0000”.
2.
C: Load Data Low Byte. Bit n = “0” programs the Lock bit.
3.
Give WR a negative pulse and wait for RDY/BSY to go high.
The Lock bits can only be cleared by executing Chip Erase.
1.
A: Load Command “0000 0100”.
2.
Set OE to “0”, BS2 to “0”, and BS1 to “0”. The status of the Fuse Low bits can now be read at DATA (“0” means programmed).
3.
Set OE to “0”, BS2 to “1”, and BS1 to “1”. The status of the Fuse High bits can now be read at DATA (“0” means programmed).
4.
Set OE to “0”, BS2 to “0”, and BS1 to “1”. The status of the Lock bits can now be read at DATA (“0” means programmed).
5.
Set OE to “1”.
117
1477G–AVR–03/05
Figure 63. Mapping Between BS1, BS2 and the Fuse- and Lock-bits During Read
Fuse Low Byte 0
DATA
Lock Bits 0
1
BS1
Fuse High Byte
1
BS2
Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to Programming the
Flash for details on Command and Address loading):
1.
A: Load Command “0000 1000”.
2.
B: Load Address Low Byte ($00 - $02).
3.
Set OE to “0” and BS1 to “0”. The selected Signature byte can now be read at
DATA.
4.
Set OE to “1”.
Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to Programming the
Flash for details on Command and Address loading):
1.
A: Load Command “0000 1000”.
2.
B: Load Address Low Byte.
3.
Set OE to “0” and BS1 to “1”. The Calibration byte can now be read at DATA.
4.
Set OE to “1”.
Parallel Programming
Characteristics
Figure 64. Parallel Programming Timing, Including some General Timing
Requirements t
XLWL
XTAL1 t
XHXL t
DVXH t
XLDX
Data & Contol
(DATA, XA0, XA1/BS2
PAGEL/BS1) t
BVWL t
WLWH t
WLBX
WR
WLRL
RDY/BSY t
WLRH
118
ATtiny26(L)
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
F ig ur e 65. P ar al l el P ro gr am m in g T i min g, L oa di ng S eq ue nc e w i th T i min g
Requirements
(1)
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE) t
XLXH t
XLXH t
XLXH
XTAL1
PAGEL/BS1
DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
XA0
XA1/BS2
Note: 1. The timing requirements shown in Figure 64 (i.e., t
DVXH
, t
XHXL
, and t
XLDX
) also apply to loading operation.
Figure 66. Parallel Programming Timing, Reading Sequence (Within the Same Page) with Timing Requirements ()
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE) t
XLOL
XTAL1 t
BHDV
PAGEL/BS1 t
OLDV
OE t
OHDZ
DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
XA0
XA1/BS2
Note: 1. The timing requirements shown in Figure 64 (i.e. t
DVXH to reading operation.
, t
XHXL
, and t
XLDX
) also apply
119
120
ATtiny26(L)
Table 58. Parallel Programming Characteristics, V
CC
= 5V ± 10%
Symbol Parameter Min Typ Max Units t
BVWL t
WLWH t
WLRL t
WLRH t
WLRH_CE t
XLOL t
BVDV t
OLDV t
OHDZ
V
PP
I
PP t
DVXH t
XLXH t
XHXL t
XLDX t
XLWL t
WLBX
Programming Enable Voltage
Programming Enable Current
Data and Control Valid before XTAL1 High
XTAL1 Low to XTAL1 High
XTAL1 Pulse Width High
Data and Control Hold after XTAL1 Low
XTAL1 Low to WR Low
BS2/1 Hold after WR Low
BS1 Valid to WR Low
WR Pulse Width Low
WR Low to RDY/BSY Low
WR Low to RDY/BSY High
WR Low to RDY/BSY High for Chip Erase
XTAL1 Low to OE Low
BS1 Valid to DATA valid
OE Low to DATA Valid
OE High to DATA Tri-stated
(1)
(2)
11.5
67
200
150
67
0
67
67
150
0
3.7
7.5
0
0
12.5
250
1
4.5
9
250
250
250
µ
V
A ns ns ns ns ns ns ns ns
µ s ms ms ns ns ns ns
Notes: 1. t
WLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands.
2. t
WLRH_CE is valid for the Chip Erase command.
1477G–AVR–03/05
ATtiny26(L)
Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI
(input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in
Table 59 on page 121, the pin mapping for SPI programming is listed. Not all parts use
the SPI pins dedicated for the internal SPI interface. Note that throughout the description about Serial downloading, MOSI and MISO are used to describe the serial data in and serial data out respectively.
Serial Programming Pin
Mapping
Table 59. Pin Mapping Serial Programming
Symbol Pins
MOSI
MISO
SCK
PB0
PB1
PB2
Figure 67. Serial Programming and Verify
(1)
I/O
I
O
I
Description
Serial data in
Serial data out
Serial clock
2.7 - 5.5V
VCC
2.7 - 5.5V
(2)
MOSI
MISO
SCK
PB0
PB1
PB2
XTAL1
AVCC
RESET
GND
Notes: 1. If the device is clocked by the internal oscillator, there is no need to connect a clock source to the XTAL1 pin.
2. V
CC
-0.3V < AVCC < V
CC
+0.3V, however, AVCC should always be within 2.7 - 5.5V.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the serial mode ONLY) and there is no need to first execute the
Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into $FF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f ck
< 12 MHz, 3 CPU clock cycles for f ck
≥
12 MHz
High: > 2 CPU clock cycles for f ck
< 12 MHz, 3 CPU clock cycles for f ck
≥
12 MHz
121
1477G–AVR–03/05
SPI Serial Programming
Algorithm
When writing serial data to the ATtiny26, data is clocked on the rising edge of SCK.
When reading data from the ATtiny26, data is clocked on the falling edge of SCK. See
Figure 68, Figure 69, and Table 69 for timing details.
To program and verify the ATtiny26 in the serial programming mode, the following
sequence is recommended (See four byte instruction formats in Table 61 ):
1.
Power-up sequence:
Apply power between V
CC
and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during
Power-up. In this case, RESET must be given a positive pulse of at least two
CPU clock cycles duration after SCK has been set to “0”.
2.
Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI.
3.
The serial programming instructions will not work if the communication is out of synchronization. When in synchronize the second byte ($53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all 4 bytes of the instruction must be transmitted. If the $53 did not echo back, give RESET a positive pulse and issue a new Programming
Enable command.
4.
The Flash is programmed one page at a time. The page size is found in Table 52 on page 109. The memory page is loaded one byte at a time by supplying the 4
LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for given address. The Program Memory
Page is stored by loading the Write Program Memory Page instruction with the 6
MSB of the address. If polling is not used, the user must wait at least t
WD_FLASH
before issuing the next page. (See Table 60). Accessing the serial programming
interface before the Flash write operation completes can result in incorrect programming.
5.
The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait at least t
WD_EEPROM before issuing the next byte. (See
Table 60). In a chip erased device, no $FFs in the data file(s) need to be
programmed.
6.
Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO.
7.
At the end of the programming session, RESET can be set high to commence normal operation.
8.
Power-off sequence (if needed):
Set RESET to “1”.
Turn V
CC
power off.
122
ATtiny26(L)
1477G–AVR–03/05
Data Polling Flash
Data Polling EEPROM
ATtiny26(L)
When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value $FF. At the time the device is ready for a new page, the programmed value will read correctly. This is used to determine when the next page can be written. Note that the entire page is written simultaneously and any address within the page can be used for polling. Data polling of the Flash will not work for the value $FF, so when programming this value, the user will have to wait for at least t
WD_FLASH
before programming the next page. As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF, can be skipped.
WD_FLASH
value.
When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value $FF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value $FF, but the user should have the following in mind: As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF, can be skipped. This does not apply if the EEPROM is re-programmed without chip-erasing the device. In this case, data polling cannot be used for the value $FF, and the user will have to wait at least t
WD_EEPROM
before programming the next byte. See Table 60 for t
WD_EEPROM
value.
Table 60. Minimum Wait Delay before Writing the Next Flash or EEPROM Location
Symbol Minimum Wait Delay t
WD_FLASH t
WD_EEPROM t
WD_ERASE t
WD_FUSE
4.5 ms
9.0 ms
9.0 ms
4.5 ms
Figure 68. Serial Programming Waveforms
SERIAL DATA INPUT
(MOSI)
MSB LSB
SERIAL DATA OUTPUT
(MISO)
SERIAL CLOCK INPUT
(SCK)
SAMPLE
MSB LSB
123
1477G–AVR–03/05
Table 61. Serial Programming Instruction Set
Instruction
Programming Enable
Chip Erase
Read Program Memory
Instruction Format Operation
Byte 1 Byte 2 Byte 3 Byte4
1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after
RESET goes low.
1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash.
0010 H 000 xxxx xx aa bbbb bbbb oooo oooo Read H (high or low) data o from
Program memory at word address a:b.
Load Program Memory Page 0100 H 000 xxxx xxxx xxxx bbbb iiii iiii Write H (high or low) data i to Program
Memory page at word address b. Data low byte must be loaded before data high byte is applied within the same address.
Write Program Memory Page 0100 1100 xxxx xx aa bbbb xxxx xxxx xxxx Write Program Memory Page at address a:b.
Read EEPROM Memory 1010 0000 xxxx xxxx x bbb bbbb oooo oooo Read data o from EEPROM memory at address b.
Write EEPROM Memory 1100 0000 xxxx xxxx x bbb bbbb iiii iiii Write data i to EEPROM memory at address b.
Read Lock Bits 0101 1000 0000 0000 xxxx xxxx xxxx xxoo Read Lock bits. “0” = programmed, “1”
= unprogrammed. See
for details.
Write Lock Bits
Read Signature Byte
Write Fuse Bits
Write Fuse High Bits
1010 1100 111x xxxx xxxx xxxx 1111 11 ii Write Lock bits. Set bits = “0” to
program Lock bits. See Table 48 on page 107
for details.
0011 0000 xxxx xxxx xxxx xx bb oooo oooo Read Signature Byte o at address b.
1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to unprogram. See
1010 1100 1010 1000 xxxx xxxx xxx i iiii Set bits = “0” to program, “1” to unprogram. See
Read Fuse Bits
Read Fuse High Bits
Read Calibration Byte
0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse bits. “0” = programmed, “1”
= unprogrammed. See
for details.
0101 1000 0000 1000 xxxx xxxx xxx o oooo Read Fuse high bits.
“0” = programmed,
“1” = unprogrammed. See
Table 50 on page 108 for details.
0011 1000 xxxx xxxx 0000 00 bb oooo oooo Read Calibration Byte o.
Note: a = address high bits
b = address low bits
H = 0 – Low byte, 1 – High Byte
o = data out
i = data in x = don’t care
124
ATtiny26(L)
1477G–AVR–03/05
Serial Programming
Characteristics
ATtiny26(L)
Figure 69. Serial Programming Timing
MOSI t
OVSH
SCK t
SHSL
MISO t
SHOX t
SLSH
t
SLIV
Table 62. Serial Programming Characteristics, T
A
= -40
°
C to 85
°
C, V
CC
(Unless Otherwise Noted) (1)
= 2.7V - 5.5V
Symbol Parameter Min Typ Max Units
1/t
CLCL t
CLCL
1/t
CLCL t
CLCL t
SHSL t
SLSH t
OVSH t
SHOX t
SLIV
Oscillator Frequency (V
CC
Oscillator Period (V
CC
Oscillator Period (V
CC
SCK Pulse Width High
SCK Pulse Width Low
= 2.7 - 5.5 V)
= 2.7 - 5.5 V)
Oscillator Frequency (V
CC
= 4.5 - 5.5 V)
= 4.5 - 5.5 V)
MOSI Setup to SCK High
MOSI Hold after SCK High
SCK Low to MISO Valid
Note: 1. 2 t
CLCL
for f ck
< 12 MHz, 3 t
CLCL
for f ck
>= 12 MHz
0
125
0
62.5
2 t
CLCL
(1)
2 t
CLCL
(1) t
CLCL
2 t
CLCL
20
8
16 ns ns ns ns ns
MHz ns
MHz ns
125
1477G–AVR–03/05
Electrical Characteristics
Absolute Maximum Ratings*
Operating Temperature.................................. -55
°
C to +125
°
C
Storage Temperature ..................................... -65°C to +150
°
C
Voltage on Any Pin except RESET with Respect to Ground .............................-0.5V to V
CC
+ 0.5V
Voltage on RESET with Respect to Ground ....-0.5V to +13.0V
Maximum Operating Voltage ............................................ 6.0V
DC Current per I/O Pin ............................................... 40.0 mA
DC Current V
CC
and GND Pins ................................ 200.0 mA
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics
T
A
= -40
°
C to 85
°
C, V
CC
= 2.7V to 5.5V (unless otherwise noted)
Symbol Parameter Condition
V
IL
V
IH
V
IL1
V
IH1
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Except XTAL1 pin and
RESET pins
Except XTAL1 and
RESET pins
XTAL1 pin, External
Clock Selected
XTAL1 pin, External
Clock Selected
RESET pin V
IL2
V
IH2
V
IL3
V
IH3
Input High Voltage
Input Low Voltage
RESET pin
RESET pin as I/O
V
OL
V
OH
I
IL
I
IH
Input High Voltage
Output Low Voltage (4)
(Ports A, B)
Output High Voltage (5)
(Ports A, B)
Input Leakage
Current I/O Pin
Input Leakage
Current I/O Pin
Reset Pull-up Resistor
RESET pin as I/O
I
OL
= 20 mA, V
CC
= 5V
I
OL
= 10 mA, V
CC
= 3V
I
OH
= -20 mA, V
I
OH
= -10 mA, V
CC
= 5V
CC
= 3V
V
CC
= 5.5
V, pin low
(absolute value)
V
CC
= 5.5
V, pin high
(absolute value)
R
RST
R pu
I/O Pin Pull-up Resistor
Min.
-0.5
0.6V
CC
(3)
-0.5
0.8V
CC
(3)
-0.5
0.9V
CC
(3)
-0.5
0.6V
CC
(3)
4.2
2.3
20
20
Max.
0.2V
CC
V
CC
+0.5
0.1V
CC
V
CC
+0.5
0.2V
CC
V
CC
+0.5
0.2V
CC
V
CC
+0.5
0.7
0.5
1
1
100
100
Units
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA k
Ω k
Ω
126
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
T
A
= -40
°
C to 85
°
C, V
CC
= 2.7V to 5.5V (unless otherwise noted) (Continued)
Symbol Parameter Condition Min.
Typ.
(1)
Max.
Units
I
CC
Power Supply Current
Active 1 MHz, V
CC
= 3V
( ATtiny26 L)
Active 4 MHz, V
CC
= 3V
( ATtiny26 L)
Active 8 MHz, V
CC
= 5V
( ATtiny26 )
Idle 1 MHz, V
CC
= 3V
( ATtiny26 L)
Idle 4 MHz, V
CC
= 3V
( ATtiny26 L)
0.70
2.5
8
0.18
0.75
6
15
2 mA mA mA mA mA
Idle 8 MHz, V
CC
= 5V
( ATtiny26 )
3.5
7 mA
I
V
ACIO
ACLK
Power-down mode
(6)
Analog Comparator
Input Offset Voltage
Analog Comparator
Input Leakage Current
WDT enabled, V
CC
= 3V
WDT disabled, V
CC
= 3V
V
CC
= 5V
V in
= V
CC
/2
V
CC
= 5V
V in
= V
CC
/2
-50
7.5
0.3
<10
15
3
40
50
µA
µA mV nA t
ACID
Analog Comparator
Propagation Delay
V
CC
V
CC
= 2.7V
= 4.0V
750
500 ns
Notes: 1. Typical value at 25
°
C
2. “Max” means the highest value where the pin is guaranteed to be read as low
3. “Min” means the lowest value where the pin is guaranteed to be read as high
4. Although each I/O port can sink more than the test conditions (20mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed:
1] The sum of all IOL, for all ports, should not exceed 400 mA.
2] The sum of all IOL, for port A0 - A7, should not exceed 300 mA.
3] The sum of all IOL, for ports B0 - B7 should not exceed 300 mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition.
5. Although each I/O port can source more than the test conditions (20 mA at V
CC
= 5V, 10 mA at V
CC
= 3V) under steady state conditions (non-transient), the following must be observed:
1] The sum of all IOH, for all ports, should not exceed 400 mA.
2] The sum of all IOH, for port A0 - A7, should not exceed 300 mA.
3] The sum of all IOH, for ports B0 - B7 should not exceed 300 mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition.
6. Minimum V
CC
for Power-down is 2.5V
127
1477G–AVR–03/05
External Clock Drive
Waveforms
Figure 70. External Clock Drive Waveforms
V
IL1
V
IH1
External Clock Drive
Table 63. External Clock Drive
Symbol Parameter
1/t
CLCL t
CLCL t
CHCX t
CLCX t
CLCH t
CHCL
Oscillator Frequency
Clock Period
High Time
Low Time
Rise Time
Fall Time
∆ t
CLCL
Change in period from one clock cycle to the next
V
CC
= 2.7 - 5.5V
V
CC
= 4.5 - 5.5V
Min Max Min Max
0
125
8 0
62.5
16
50
50
25
25
1.6
1.6
0.5
0.5
Units
MHz ns ns ns
µ s
µ s
2 2
Table 64. External RC Oscillator, Typical Frequencies
R [k
Ω
]
(1)
33
C [pF]
22 f
(2)
650 kHz
10 22 2.0 MHz
Notes: 1. R should be in the range 3 k
Ω
- 100 k
Ω
, and C should be at least 20 pF. The C values given in the table includes pin capacitance. This will vary with package type.
2. The frequency will vary with package type and board layout.
128
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
ADC Characteristics
Table 65. ADC Characteristics, Single Ended Channels, T
A
= -40
°
C to 85
°
C
Symbol Parameter Condition
Resolution
Absolute Accuracy
(Including INL, DNL, Quantization Error, Gain and Offset Error)
Integral Non-Linearity (INL)
Differential Non-Linearity (DNL)
Gain Error
Offset error
Single Ended Conversion
Single Ended Conversion
V
REF
= 4V, V
CC
= 4V
ADC clock = 200 kHz
Single Ended Conversion
V
REF
= 4V, V
CC
= 4V
ADC clock = 1 MHz
Single Ended Conversion
V
REF
= 4V, V
CC
= 4V
ADC clock = 200 kHz
Noise Reduction mode
Single Ended Conversion
V
REF
= 4V, V
CC
= 4V
ADC clock = 1 MHz
Noise Reduction mode
Single Ended Conversion
V
REF
= 4V, V
CC
= 4V
ADC clock = 200 kHz
Single Ended Conversion
V
REF
= 4V, V
CC
= 4V
ADC clock = 200 kHz
Single Ended Conversion
V
REF
= 4V, V
CC
= 4V
ADC clock = 200 kHz
Single Ended Conversion
V
REF
= 4V, V
CC
= 4V
ADC clock = 200 kHz
Clock Frequency
Conversion Time
Analog Supply Voltage AVCC
V
REF
V
IN
Reference Voltage
Input Voltage
ADC Conversion Output
Input Bandwidth
V
INT
R
REF
R
AIN
Internal Voltage Reference
Reference Input Resistance
Analog Input Resistance
Note: 1. Minimum for AVCC is 2.7V.
2. Maximum for AVCC is 5.5V
Min
50
13
V
CC
- 0.3
(1)
2.0
GND
0
2.4
Typ
10
1
2
1
2
0.5
0.5
0.75
0.5
38.5
2.7
32
100
Max Units
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
1000
260
V
CC
AVCC
V
REF
1023
2.9
kHz
µs
V
V
V
LSB kHz
V k
Ω
M
Ω
129
1477G–AVR–03/05
Table 66. ADC Characteristics, Differential Channels, T
A
= -40
°
C to 85
°
C
Symbol Parameter Condition
Resolution
Absolute Accuracy
Integral Non-Linearity (INL)
(Accuracy after Calibration for Offset and
Gain Error)
Gain Error
Offset Error
Gain = 1x
Gain = 20x
Gain = 1x
V
REF
= 4V, V
CC
= 5V
ADC clock = 50 - 200 kHz
Gain = 20x
V
REF
= 4V, V
CC
= 5V
ADC clock = 50 - 200 kHz
Gain = 1x
V
REF
= 4V, V
CC
= 5V
ADC clock = 50 - 200 kHz
Gain = 20x
V
REF
= 4V, V
CC
= 5V
ADC clock = 50 - 200 kHz
Gain = 1x
Gain = 20x
Gain = 1x
V
REF
= 4V, V
CC
= 5V
ADC clock = 50 - 200 kHz
Gain = 20x
V
REF
= 4V, V
CC
= 5V
ADC clock = 50 - 200 kHz
AVCC
V
REF
V
V
IN
DIFF
Clock Frequency
Conversion Time
Analog Supply Voltage
Reference Voltage
Input Voltage
Input Differential Voltage
ADC Conversion Output
Input Bandwidth
V
INT
R
REF
Internal Voltage Reference
Reference Input Resistance
R
AIN
Analog Input Resistance
Notes: 1. Minimum for AVCC is 2.7V.
2. Maximum for AVCC is 5.5V.
Min
50
26
V
CC
- 0.3
(1)
2.0
GND
0
0
2.4
Typ
24
27
1.5
2
2
2.5
4
6
4
2.7
32
100
Max
10
10
Units
Bits
Bits
LSB
LSB
LSB
LSB
%
%
LSB
LSB
200
65
V
CC
+ 0.3
(2)
AVCC - 0.5
V
CC
V
REF
/Gain
1023
2.9
V
V
LSB kHz
V k
Ω
M
Ω kHz
µs
V
V
130
ATtiny26(L)
1477G–AVR–03/05
ATtiny26 Typical
Characteristics
Active Supply Current
ATtiny26(L)
The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with railto-rail output is used as clock source.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as
C
L
* V
CC
*f where C
L
= load capacitance, V
CC
= operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates.
The difference between current consumption in Power-down mode with Watchdog
Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer.
Figure 71. Active Supply Current vs. Frequency (0.1 - 1.0 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
0.1 - 1.0 MHz
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0 0.1
0.2
0.3
0.4
0.5
Frequency (MHz)
0.6
0.7
0.8
0.9
1
5.5V
5.0V
4.5V
4.0V
3.3V
3.0V
2.7V
131
1477G–AVR–03/05
132
ATtiny26(L)
Figure 72. Active Supply Current vs. Frequency (1 - 20 MHz)
25
20
15
10
5
0
0 2 4
ACTIVE SUPPLY CURRENT vs. FREQUENCY
1 - 20 MHz
6
2.7V
8 10
Frequency (MHz)
12
3.0V
14
3.3V
16
4.0V
18 20
5.5V
5.0V
4.5V
Figure 73. Active Supply Current vs. V
CC
(Internal RC Oscillator, 8 MHz)
ACTIVE SUPPLY CURRENT vs. V
CC
INTERNAL RC OSCILLATOR, 8 MHz
14
12
10
8
6
4
2
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
-40 °C
25 °C
85 °C
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Figure 74. Active Supply Current vs. V
CC
(Internal RC Oscillator, 4 MHz)
ACTIVE SUPPLY CURRENT vs. V
CC
INTERNAL RC OSCILLATOR, 4 MHz
8
7
6
5
4
3
2
1
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
5
Figure 75. Active Supply Current vs. V
CC
(Internal RC Oscillator, 2 MHz)
5.5
85 °C
25 °C
-40 °C
ACTIVE SUPPLY CURRENT vs. V
CC
INTERNAL RC OSCILLATOR, 2 MHz
4
3.5
3
2.5
2
1.5
1
0.5
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
85 °C
25 °C
-40 °C
133
134
ATtiny26(L)
Figure 76. Active Supply Current vs. V
CC
(Internal RC Oscillator, 1 MHz)
ACTIVE SUPPLY CURRENT vs. V
CC
INTERNAL RC OSCILLATOR, 1 MHz
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
Figure 77. Active Supply Current vs. V
CC
(PLL Oscillator)
5 5.5
25 °C
85 °C
-40 °C
ACTIVE SUPPLY CURRENT vs. V
CC
PLL OSCILLATOR
25
20
15
10
5
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
-40 °C
25 °C
85 °C
1477G–AVR–03/05
Idle Supply Current
ATtiny26(L)
Figure 78. Active Supply Current vs. V
CC
(32 kHz External Oscillator)
ACTIVE SUPPLY CURRENT vs. V
CC
32kHz EXTERNAL OSCILLATOR
50
40
30
20
70
60
10
0
1.5
2 2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
25 °C
Figure 79. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY
0.1 - 1.0 MHz
0.6
0.5
0.4
0.3
0.2
0.1
0
0 0.1
0.2
0.3
0.4
0.5
Frequency (MHz)
0.6
0.7
0.8
0.9
1
5.5V
5.0V
4.5V
4.0V
3.3V
3.0V
2.7V
135
1477G–AVR–03/05
136
ATtiny26(L)
Figure 80. Idle Supply Current vs. Frequency (1 - 20 MHz)
12
10
8
6
4
2
0
0 2 4
IDLE SUPPLY CURRENT vs. FREQUENCY
1 - 20 MHz
6
4.0V
3.3V
2.7V
3.0V
8 10
Frequency (MHz)
12 14 16 18 20
5.5V
5.0V
4.5V
Figure 81. Idle Supply Current vs. V
CC
(Internal RC Oscillator, 8 MHz)
7
6
5
4
3
2
1
0
2 2.5
3
IDLE SUPPLY CURRENT vs. V
CC
INTERNAL RC OSCILLATOR, 8 MHz
3.5
V
CC
(V)
4 4.5
5 5.5
-40 °C
25 °C
85 °C
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Figure 82. Idle Supply Current vs. V
CC
(Internal RC Oscillator, 4 MHz)
IDLE SUPPLY CURRENT vs. V
CC
INTERNAL RC OSCILLATOR, 4 MHz
3.5
3
2.5
2
1.5
1
0.5
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
5
Figure 83. Idle Supply Current vs. V
CC
(Internal RC Oscillator, 2 MHz)
5.5
-40 °C
25 °C
85 °C
IDLE SUPPLY CURRENT vs. V
CC
INTERNAL RC OSCILLATOR, 2 MHz
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
25 °C
85 °C
-40 °C
137
138
ATtiny26(L)
Figure 84. Idle Supply Current vs. V
CC
(Internal RC Oscillator, 1 MHz)
IDLE SUPPLY CURRENT vs. V
CC
INTERNAL RC OSCILLATOR, 1 MHz
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2 2.5
3 3.5
V
CC
(V)
4
Figure 85. Idle Supply Current vs. V
CC
(PLL Oscillator)
4.5
5 5.5
25 °C
85 °C
-40 °C
IDLE SUPPLY CURRENT vs. V
CC
PLL OSCILLATOR
85 °C
-40 °C
25 °C 10
8
6
4
2
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
1477G–AVR–03/05
ATtiny26(L)
Figure 86. Idle Supply Current vs. V
CC
(32 kHz External Oscillator)
IDLE SUPPLY CURRENT vs. V
CC
32kHz EXTERNAL OSCILLATOR
20
15
10
5
30
25
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
5
Power-down Supply Current Figure 87. Power-down Supply Current vs. V
CC
(Watchdog Timer Disabled)
5.5
25 °C
POWER-DOWN SUPPLY CURRENT vs. V
CC
WATCHDOG TIMER DISABLED
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
85 °C
-40 °C
25 °C
139
1477G–AVR–03/05
Standby Supply Current
Figure 88. Power-down Supply Current vs. V
CC
(Watchdog Timer Enabled)
POWER-DOWN SUPPLY CURRENT vs. V
CC
WATCHDOG TIMER ENABLED
20
18
16
14
12
10
8
6
4
2
0
2
85 °C
25 °C
-40 °C
2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
Figure 89. Standby Supply Current vs. V
CC
(455 kHz Resonator, Watchdog Timer
Disabled)
STANDBY SUPPLY CURRENT vs. V
CC
455 kHz RESONATOR, WATCHDOG TIMER DISABLED
70
60
50
40
30
20
10
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
140
ATtiny26(L)
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Figure 90. Standby Supply Current vs. V
CC
(1 MHz Resonator, Watchdog Timer
Disabled)
STANDBY SUPPLY CURRENT vs. V
CC
1 MHz RESONATOR, WATCHDOG TIMER DISABLED
40
30
20
10
60
50
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
Figure 91. Standby Supply Current vs. V
CC
(2 MHz Resonator, Watchdog Timer
Disabled)
STANDBY SUPPLY CURRENT vs. V
CC
2 MHz RESONATOR, WATCHDOG TIMER DISABLED
80
70
60
50
40
30
20
10
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
141
142
ATtiny26(L)
Figure 92. Standby Supply Current vs. V
CC
(2 MHz XTAL, Watchdog Timer Disabled)
STANDBY SUPPLY CURRENT vs. V
CC
2 MHz XTAL, WATCHDOG TIMER DISABLED
50
40
30
20
10
0
2
90
80
70
60
2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
Figure 93. Standby Supply Current vs. V
CC
(4 MHz Resonator, Watchdog Timer
Disabled)
120
100
80
60
40
20
0
2 2.5
STANDBY SUPPLY CURRENT vs. V
CC
4 MHz RESONATOR, WATCHDOG TIMER DISABLED
3 3.5
V
CC
(V)
4 4.5
5 5.5
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Figure 94. Standby Supply Current vs. V
CC
(4 MHz XTAL, Watchdog Timer Disabled)
STANDBY SUPPLY CURRENT vs. V
CC
4 MHz XTAL, WATCHDOG TIMER DISABLED
120
100
80
60
40
20
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
Figure 95. Standby Supply Current vs. V
CC
(6 MHz Resonator, Watchdog Timer
Disabled)
STANDBY SUPPLY CURRENT vs. V
CC
6 MHz RESONATOR, WATCHDOG TIMER DISABLED
160
140
120
100
80
60
40
20
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
143
Pin Pull-up
Figure 96. Standby Supply Current vs. V
CC
(6 MHz XTAL, Watchdog Timer Disabled)
STANDBY SUPPLY CURRENT vs. V
CC
6 MHz XTAL, WATCHDOG TIMER DISABLED
180
160
140
120
100
80
60
40
20
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
5
Figure 97. I/O Pin Pull-up Resistor Current vs. Input Voltage (V
CC
= 5V)
5.5
160
85 °C
140
120
-40 °C
100
25 °C
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 5V
80
60
40
20
0
0 1 2 3
V
OP
(V)
4 5 6
144
ATtiny26(L)
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Figure 98. I/O Pin Pull-up Resistor Current vs. Input Voltage (V
CC
= 2.7V)
85 °C
70
60
-40 °C
25 °C
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 2.7V
50
40
30
20
10
0
0 0.5
1 1.5
V
OP
(V)
2 2.5
3
Figure 99. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V
CC
= 5V)
60
40
20
0
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
Vcc = 5V
120
-40 °C
100
80
85 °C
25 °C
V
RESET
(V)
145
Pin Driver Strength
Figure 100. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V
CC
= 2.7V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
Vcc = 2.7V
60
-40 °C
50
85 °C
25 °C
40
30
20
10
0
0 0.5
1 1.5
V
RESET
(V)
2 2.5
3
Figure 101. I/O Pin Source Current vs. Output Voltage (V
CC
= 5V)
90
80
70
60
50
40
30
20
10
0
0 1
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 5V
-40 °C
25 °C
85 °C
2 3
V
OH
(V)
4
146
ATtiny26(L)
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Figure 102. I/O Pin Source Current vs. Output Voltage (V
CC
= 2.7V)
30
25
20
15
10
5
0
0
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 2.7V
-40 °C
25 °C
85 °C
0.5
1 1.5
V
OH
(V)
2
Figure 103. I/O Pin Sink Current vs. Output Voltage (V
CC
= 5V)
2.5
90
80
70
60
50
40
30
20
10
0
0 0.5
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 5V
-40 °C
25 °C
85 °C
1
V
OL
(V)
1.5
2
3
2.5
147
148
ATtiny26(L)
Figure 104. I/O Pin Sink Current vs. Output Voltage (V
CC
= 2.7V)
35
30
25
20
15
10
5
0
0
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 2.7V
-40 °C
25 °C
85 °C
0.5
1
V
OL
(V)
1.5
2 2.5
Figure 105. Reset Pin as I/O – Source Current vs. Output Voltage (V
CC
= 5V)
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 5V
-40 °C
25 °C
85 °C
1 2 3
V
OH
(V)
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Figure 106. Reset Pin as I/O – Source Current vs. Output Voltage (V
CC
= 2.7V)
2.5
2
1.5
1
0.5
0
0
RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 2.7V
-40 °C
25 °C
85 °C
0.5
1 1.5
V
OH
(V)
2 2.5
3
Figure 107. Reset Pin as I/O –Sink Current vs. Output Voltage (V
CC
= 5V)
14
12
10
8
6
4
2
0
0
RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 5V
-40 °C
25 °C
85 °C
0.5
1
V
OL
(V)
1.5
2 2.5
149
Pin Thresholds and
Hysteresis
Figure 108. Reset Pin as I/O – Sink Current vs. Output Voltage (V
CC
= 2.7V)
2.5
2
1.5
1
0.5
0
0
4.5
4
3.5
3
RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 2.7V
-40 °C
25 °C
85 °C
0.5
1
V
OL
(V)
1.5
2 2.5
Figure 109. I/O Pin Input Threshold Voltage vs. V
CC
(V
IH
, I/O Pin Read as “1”)
I/O PIN INPUT THRESHOLD VOLTAGE vs. V
CC
VIH, IO PIN READ AS '1'
2.5
2
1.5
1
0.5
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
-40 °C
85 °C
25 °C
150
ATtiny26(L)
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Figure 110. I/O Pin Input Threshold Voltage vs. V
CC
(V
IL
, I/O Pin Read as “0”)
I/O PIN INPUT THRESHOLD VOLTAGE vs. V
CC
VIL, IO PIN READ AS '0'
2
1.5
1
0.5
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
5
Figure 111. I/O Pin Input Hysteresis vs. V
CC
I/O PIN INPUT HYSTERESIS vs. V
CC
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
5
5.5
-40 °C
25 °C
85 °C
5.5
85°C
25°C
-40°C
151
152
ATtiny26(L)
Figure 112. Reset Pin as I/O – Input Threshold Voltage vs. V
CC
(V
IH
, Reset Pin Read as “1”)
RESET PIN AS I/O - INPUT THRESHOLD VOLTAGE vs. V
CC
VIH, RESET PIN READ AS '1'
2.5
2
1.5
1
0.5
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
Figure 113. Reset Pin as I/O – Input Threshold Voltage vs. V
CC
(V
IL
, Reset Pin Read as “0”)
5 5.5
-40 °C
85 °C
25 °C
RESET PIN AS I/O - INPUT THRESHOLD VOLTAGE vs. V
CC
VIL, RESET PIN READ AS '0'
2.5
2
1.5
1
0.5
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
-40 °C
25 °C
85 °C
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Figure 114. Reset Pin as I/O – Pin Hysteresis vs. V
CC
RESET PIN AS I/O - PIN HYSTERESIS vs. V
CC
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
5
85°C
-40°C
25°C
5.5
Figure 115. Reset Input Threshold Voltage vs. V
CC
(V
IH
, Reset Pin Read as “1”)
2.5
2
1.5
1
0.5
0
1.5
-40 °C
25 °C
85 °C
2
RESET INPUT THRESHOLD VOLTAGE vs. V
CC
VIH, RESET PIN READ AS '1'
2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
153
154
ATtiny26(L)
Figure 116. Reset Input Threshold Voltage vs. V
CC
(V
IL
, Reset Pin Read as “0”)
2.5
2
1.5
1
0.5
0
2
85 °C
25 °C
-40 °C
2.5
RESET INPUT THRESHOLD VOLTAGE vs. V
CC
VIL, RESET PIN READ AS '0'
3 3.5
V
CC
(V)
4 4.5
5
Figure 117. Reset Input Pin Hysteresis vs. V
CC
5.5
RESET INPUT PIN HYSTERESIS vs. V
CC
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
2
-40 °C
25
85
°C
°C
2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
1477G–AVR–03/05
ATtiny26(L)
BOD Thresholds and Analog
Comparator Offset
Figure 118. BOD Thresholds vs. Temperature (BOD Level is 4.0V)
BOD THRESHOLDS vs. TEMPERATURE
BODLEVEL IS 4.0V
4.3
4.2
4.1
Rising V
CC
4
3.9
Falling V
CC
3.8
-50 -40 -30 -20 -10 0 10 20 30
Temperature (C)
40 50 60 70 80 90 100
Figure 119. BOD Thresholds vs. Temperature (BOD Level is 2.7V)
BOD THRESHOLDS vs. TEMPERATURE
BODLEVEL IS 2.7V
3.1
3
2.9
Rising V
CC
2.8
2.7
Falling V
CC
2.6
-50 -40 -30 -20 -10 0 10 20 30
Temperature (C)
40 50 60 70 80 90 100
155
1477G–AVR–03/05
156
ATtiny26(L)
Figure 120. Bandgap Voltage vs. V
CC
BANDGAP vs. V
CC
1.236
1.234
1.232
1.23
1.228
1.226
1.224
1.222
1.22
1.218
1.216
2.5
-40°C
85°C
25°C
3 3.5
4
Vcc (V)
4.5
5 5.5
Figure 121. Analog Comparator Offset Voltage vs. Common Mode Voltage (V
CC
= 5.0V)
0.009
0.008
0.007
0.006
0.005
0.004
0.003
0.002
0.001
0
0
ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE
Vcc = 5V
1 2 3
Common Mode Voltage (V)
4
-40°C
25°C
85°C
1477G–AVR–03/05
ATtiny26(L)
Figure 122. Analog Comparator Offset Voltage vs. Common Mode Voltage (V
CC
= 2.7V)
Internal Oscillator Speed
0.009
0.008
0.007
0.006
0.005
0.004
0.003
0.002
0.001
0
0
ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE
Vcc = 2.7V
0.5
1 1.5
Common Mode Voltage (V)
2 2.5
-40°C
25°C
85°C
3
Figure 123. Watchdog Oscillator Frequency vs. V
CC
WATCHDOG OSCILLATOR FREQUENCY vs. V
CC
1.4
1.35
1.3
1.25
1.2
1.15
1.1
1.05
2 2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
-40 °C
25 °C
85 °C
157
1477G–AVR–03/05
158
ATtiny26(L)
Figure 124. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature
8.9
8.4
7.9
7.4
6.9
6.4
-60
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
-40 -20 0 20
T a
(ËšC)
40 60 80
5.0V
3.5V
2.7V
100
Figure 125. Calibrated 8 MHz RC Oscillator Frequency vs. V
CC
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. V
CC
9
8.5
8
7.5
7
6.5
6
2 2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
-40 °C
25 °C
85 °C
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Figure 126. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
17.5
15.5
13.5
11.5
9.5
7.5
5.5
3.5
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
OSCCAL VALUE
Figure 127. Calibrated 4 MHz RC Oscillator Frequency vs. Temperature
4.3
4.2
4.1
4
3.9
3.8
3.7
3.6
3.5
3.4
-60
CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
-40 -20 0 20
T a
(ËšC)
40 60 80
5.0V
3.5V
2.7V
100
159
160
ATtiny26(L)
Figure 128. Calibrated 4 MHz RC Oscillator Frequency vs. V
CC
CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. V
CC
4.4
4.3
4.2
4.1
4
3.9
3.8
3.7
3.6
3.5
3.4
2 2.5
3 3.5
V
CC
(V)
4 4.5
5
Figure 129. Calibrated 4 MHz RC Oscillator Frequency vs. Osccal Value
5.5
-40 °C
25 °C
85 °C
CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
9.6
8.6
7.6
6.6
5.6
4.6
3.6
2.6
1.6
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
OSCCAL VALUE
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Figure 130. Calibrated 2 MHz RC Oscillator Frequency vs. Temperature
CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
2.15
2.1
2.05
2
1.95
1.9
1.85
1.8
1.75
-60 -40 -20 0 20
T a
(ËšC)
40 60 80
5.0V
3.5V
2.7V
100
Figure 131. Calibrated 2 MHz RC Oscillator Frequency vs. V
CC
CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. V
CC
2.15
2.1
2.05
2
1.95
1.9
1.85
1.8
1.75
1.7
2 2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
-40 °C
25 °C
85 °C
161
162
ATtiny26(L)
Figure 132. Calibrated 2 MHz RC Oscillator Frequency vs. Osccal Value
CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
4.3
3.8
3.3
2.8
2.3
1.8
1.3
0.8
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
OSCCAL VALUE
Figure 133. Calibrated 1 MHz RC Oscillator Frequency vs. Temperature
CALIBRATED 1 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
1.04
1.02
1
0.98
0.96
0.94
0.92
0.9
-60 -40 -20 0 20
V
CC
(V)
40 60
5.0V
3.5V
2.7V
80 100
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Figure 134. Calibrated 1 MHz RC Oscillator Frequency vs. V
CC
CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. V
CC
0.95
0.9
0.85
2
1.1
1.05
1
2.5
3 4.5
5 3.5
V
CC
(V)
4 5.5
-40°C
25°C
85°C
Figure 135. Calibrated 1 MHz RC Oscillator Frequency vs. Osccal Value
CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
OSCCAL VALUE
163
Current Consumption of
Peripheral Units
Figure 136. Brown-out Detector Current vs. V
CC
BROWNOUT DETECTOR CURRENT vs. V
CC
0.035
0.03
0.025
0.02
0.015
0.01
0.005
0
2
-40 °C
25 °C
85 °C
2.5
3 3.5
V
CC
(V)
4
Figure 137. ADC Current vs. V
CC
(AREF = AV
CC
)
4.5
5 5.5
ADC CURRENT vs. V
CC
AREF = AVCC
250
200
150
100
50
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
-40 °C
25 °C
85 °C
164
ATtiny26(L)
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Figure 138. AREF External Reference Current vs. V
CC
AREF EXTERNAL REFERENCE CURRENT vs. VCC
250
200
150
100
50
0
2 2.5
3 3.5
V
CC
(V)
4
Figure 139. Analog Comparator Current vs. V
CC
4.5
5 5.5
-40 °C
25 °C
85 °C
ANALOG COMPARATOR CURRENT vs. V
CC
120
100
80
60
40
20
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
5 5.5
85 °C
25 °C
-40 °C
165
Figure 140. Programming Current vs. V
CC
PROGRAMMING CURRENT vs. VCC
5
4
3
2
1
0
2 2.5
3 3.5
V
CC
(V)
4 4.5
Current Consumption in
Reset and Reset Pulsewidth
Figure 141. Reset Supply Current vs. V
CC
(0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up)
5 5.5
-40 °C
25 °C
85 °C
RESET SUPPLY CURRENT vs. V
CC
0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP
3.5
3
2.5
2
1.5
1
0.5
0
0 0.1
0.2
0.3
0.4
0.5
Frequency (MHz)
0.6
0.7
0.8
0.9
1
5.5V
5.0V
4.5V
4.0V
3.3V
3.0V
2.7V
166
ATtiny26(L)
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Figure 142. Reset Supply Current vs. V
CC
(1 - 20 MHz, Excluding Current Through The Reset Pull-up)
12
10
8
6
20
18
16
14
4
2
0
0 2
RESET SUPPLY CURRENT vs. V
CC
1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP
4 6 8 10
Frequency (MHz)
12 14 16 18 20
5.5V
5.0V
4.5V
4.0V
3.3V
3.0V
2.7V
Figure 143. Reset Pulsewidth vs. V
CC
1200
1000
800
600
400
200
0
0 1 2
RESET PULSE WIDTH vs. V
CC
85 °C
25 °C
-40 °C
3
V
CC
(V)
167
Register Summary
Address
$12 ($32)
$11 ($31)
$10 ($30)
$0F ($2F)
$0E ($2E)
$0D ($2D)
$0C ($2C)
$0B ($2)B
$0A ($2A)
$09 ($29)
$08 ($28)
$07 ($27)
$06 ($26)
$05 ($25)
$04 ($24)
…
$00 ($20)
$22 ($42)
$21 ($41)
$20 ($40)
$1F ($3F)
$1E ($3E)
$1D ($3D)
$1C ($3C)
$1B ($3B)
$1A ($3A)
$19 ($39)
$18 ($38)
$17 ($37)
$16 ($36)
$15 ($35)
$14 ($34)
$13 ($33)
$31 ($51)
$30 ($50)
$2F ($4F)
$2E ($4E)
$2D ($4D)
$2C ($4C)
$2B ($4B)
$2A ($4A)
$29 ($49)
$28 ($48)
$27 ($47)
$26 ($46)
$25 ($45)
$24 ($44)
$23 ($43)
$3F ($5F)
$3E ($5E)
$3D ($5D)
$3C ($5C)
$3B ($5B)
$3A ($5A)
$39 ($59)
$38 ($58)
$37 ($57)
$36 ($56)
$35 ($55)
$34 ($54)
$33 ($53)
$32 ($52)
Name
Reserved
Reserved
Reserved
USIDR
USISR
USICR
Reserved
Reserved
Reserved
Reserved
ACSR
ADMUX
ADCSR
ADCH
ADCL
Reserved
Reserved
Reserved
WDTCR
Reserved
Reserved
EEAR
EEDR
EECR
PORTA
DDRA
PINA
PORTB
DDRB
PINB
Reserved
Reserved
Reserved
OSCCAL
TCCR1A
TCCR1B
TCNT1
OCR1A
OCR1B
OCR1C
Reserved
PLLCSR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SREG
Reserved
SP
Reserved
GIMSK
GIFR
TIMSK
TIFR
Reserved
Reserved
MCUCR
MCUSR
TCCR0
TCNT0
Bit 7
I
SP7
-
-
-
-
-
-
-
COM1A1
CTC1
-
-
-
-
PORTA7
DDA7
PINA7
PORTB7
DDB7
PINB7
USISIF
USISIE
ACD
REFS1
ADEN
PUD
-
-
COM1A0
PSR1
-
-
USIOIF
USIOIE
ACBG
REFS0
ADSC
EEAR6
-
PORTA6
DDA6
PINA6
PORTB6
DDB6
PINB6
Bit 6
T
SP6
INT0
INTF0
OCIE1A
OCF1A
Bit 5
H
SP5
PCIE1
PCIF
OCIE1B
OCF1B
-
Bit 4
S
SP4
PCIE0
-
-
-
WDCE
Bit 3
V
SP3
-
-
-
-
SE
-
-
SM1
-
SM0
WDRF
PSR0
Timer/Counter0 (8-Bit)
Oscillator Calibration Register
COM1B0 FOC1A
CS13
-
BORF
CS02
COM1B1
-
FOC1B
CS12
Timer/Counter1 (8-Bit)
Timer/Counter1 Output Compare Register A (8-Bit)
Timer/Counter1 Output Compare Register B (8-Bit)
Timer/Counter1 Output Compare Register C (8-Bit)
PCKE
WDE
Bit 2
N
SP2
-
-
TOIE1
TOV1
WDP2
EEAR5
-
PORTA5
DDA5
PINA5
PORTB5
DDB5
PINB5
EEAR4 EEAR3
EEPROM Data Register (8-Bit)
-
PORTA4
EERIE
PORTA3
DDA4
PINA4
PORTB4
DDB4
PINB4
DDA3
PINA3
PORTB3
DDB3
PINB3
EEAR2
EEMWE
PORTA2
DDA2
PINA2
PORTB2
DDB2
PINB2
EEAR1
EEWE
PORTA1
DDA1
PINA1
PORTB1
DDB1
PINB1
EEAR0
EERE
PORTA0
DDA0
PINA0
PORTB0
DDB0
PINB0
ACO
ADLAR
ADFR
ACI
MUX4
ACIE
MUX3
ADIF ADIE
ADC Data Register High Byte
ADC Data Register Low Byte
ACME
MUX2
ADPS2
Bit 1
Z
SP1
-
-
TOIE0
TOV0
ISC01
EXTRF
CS01
PWM1A
CS11
PLLE
WDP1
Bit 0
C
SP0
-
-
-
-
Universal Serial Interface Data Register (8-Bit)
USIPF
USIWM1
USIDC
USIWM0
USICNT3
USICS1
USICNT2
USICS0
USICNT1
USICLK
USICNT0
USITC
ACIS1
MUX1
ADPS1
ISC00
PORF
CS00
PWM1B
CS10
PLOCK
WDP0
ACIS0
MUX0
ADPS0
Page
168
ATtiny26(L)
1477G–AVR–03/05
Instruction Set Summary
Mnemonic Operands Description
TST
CLR
SER
BRANCH INSTRUCTIONS
RJMP
IJMP
RCALL
ICALL
LDI
LD
LD
LD
EOR
COM
NEG
SBR
CBR
INC
DEC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
SBIC
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
RET
RETI
CPSE
CP
CPC
CPI
SBRC
SBRS
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
ADC
ADIW
Rd, Rr
Rd, Rr
Rdl, K
Add Two Registers
Add with Carry Two Registers
Add Immediate to Word
SUB
SUBI
SBC
SBCI
SBIW
AND
ANDI
OR
ORI
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Subtract Two Registers
Subtract Constant from Register
Subtract with Carry Two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Logical OR Register and Constant
Rd, Rr
Rd
Rd
Rd, K
Rd, K
Rd
Rd
Rd
Rd
Rd k k
Rd, Rr
Rd, Rr
Rd, Rr
Rd, K
Rr, b
Rr, b k k k k
P, b
P, b s, k s, k k k k k k k k k
BRTS
BRTC
BRVS
BRVC k k k k
BRIE
BRID k k
DATA TRANSFER INSTRUCTIONS
MOV Rd, Rr
Rd, K
Rd, X
Rd, X+
Rd, -X
Exclusive OR Registers
One’s Complement
Two’s Complement
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Decrement
Test for Zero or Minus
Clear Register
Set Register
Relative Jump
Indirect Jump to (Z)
Relative Subroutine Call
Indirect Call to (Z)
Subroutine Return
Interrupt Return
Compare, Skip if Equal
Compare
Compare with Carry
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Branch if Not Equal
Branch if Carry Set
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
Branch if Minus
Branch if Plus
Branch if Greater or Equal, Signed
Branch if Less than Zero, Signed
Branch if Half-carry Flag Set
Branch if Half-carry Flag Cleared
Branch if T-flag Set
Branch if T-flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
Move between Registers
Load Immediate
Load Indirect
Load Indirect and Post-inc.
Load Indirect and Pre-dec.
1477G–AVR–03/05
ATtiny26(L)
Operation
Rd
←
Rd + Rr
Rd
←
Rd + Rr + C
Rdh:Rdl
←
Rdh:Rdl + K
Rd
←
Rd - Rr
Rd
←
Rd - K
Rd
←
Rd - Rr - C
Rd
←
Rd - K - C
Rdh:Rdl
←
Rdh:Rdl - K
Rd
←
Rd
•
Rr
Rd
←
Rd
•
K
Rd
←
Rd v Rr
Rd
←
Rd v K
Rd
←
Rd
⊕
Rr
Rd
←
$FF - Rd
Rd
←
$00 - Rd
Rd
←
Rd v K
Rd
←
Rd
•
($FF - K)
Rd
←
Rd + 1
Rd
←
Rd - 1
Rd
←
Rd
•
Rd
Rd
←
Rd
⊕
Rd
Rd
←
$FF
PC
←
PC + k + 1
PC
←
Z
PC
←
PC + k + 1
PC
←
Z
PC
←
STACK
PC
←
STACK if (Rd = Rr) PC
←
PC + 2 or 3
Rd - Rr
Rd - Rr - C
Rd - K if (Rr(b) = 0) PC
←
PC + 2 or 3 if (Rr(b) = 1) PC
←
PC + 2 or 3 if (P(b) = 0) PC
←
PC + 2 or 3 if (P(b) = 1) PC
←
PC + 2 or 3 if (SREG(s) = 1) then PC
←
PC + k + 1 if (SREG(s) = 0) then PC
←
PC + k + 1 if (Z = 1) then PC
←
PC + k + 1 if (Z = 0) then PC
←
PC + k + 1 if (C = 1) then PC
←
PC + k + 1 if (C = 0) then PC
←
PC + k + 1 if (C = 0) then PC
←
PC + k + 1 if (C = 1) then PC
←
PC + k + 1 if (N = 1) then PC
←
PC + k + 1 if (N = 0) then PC
←
PC + k + 1 if (N
⊕
V = 0) then PC
←
PC + k + 1 if (N
⊕
V = 1) then PC
←
PC + k + 1 if (H = 1) then PC
←
PC + k + 1 if (H = 0) then PC
←
PC + k + 1 if (T = 1) then PC
←
PC + k + 1 if (T = 0) then PC
←
PC + k + 1 if (V = 1) then PC
←
PC + k + 1 if (V = 0) then PC
←
PC + k + 1 if (I = 1) then PC
←
PC + k + 1 if (I = 0) then PC
←
PC + k + 1
Rd
←
Rr
Rd
←
K
Rd
←
(X)
Rd
←
(X), X
←
X + 1
X
←
X - 1, Rd
←
(X)
# Clocks
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
4
4
1/2/3
1
1
1
1/2/3
1/2/3
2
2
3
3
1
2
2
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
Flags
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
I
None
Z,N,V,C,H
Z,N,V,C,H
Z,N,V,C,H
None
None
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,C,N,V
Z,C,N,V,H
None
None
None
None
None
169
Instruction Set Summary (Continued)
Mnemonic Operands
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
NOP
SLEEP
WDR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
LDD
LDS
ST
ST
ST
ST
ST
LD
LD
LD
LDD
LD
LD
LD
ST
STD
ST
ST
ST
STD
STS
LPM
-Y, Rr
Y+q, Rr
Z, Rr
Z+, Rr
-Z, Rr
Z+q, Rr k, Rr
LPM
IN
OUT
PUSH
Rd, Z
Rd, P
P, Rr
Rr
POP Rd
BIT AND BIT-TEST INSTRUCTIONS
SBI
CBI
LSL
P, b
P, b
Rd
Rd
Rd
Rd s s
Rd
Rd
Rr, b
Rd, b
Rd, Y
Rd, Y+
Rd, -Y
Rd,Y+q
Rd, Z
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
X, Rr
X+, Rr
-X, Rr
Y, Rr
Y+, Rr
Description
Load Indirect
Load Indirect and Post-inc.
Load Indirect and Pre-dec.
Load Indirect with Displacement
Load Indirect
Load Indirect and Post-inc.
Load Indirect and Pre-dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Store Indirect and Post-inc.
Store Indirect and Pre-dec.
Store Indirect
Store Indirect and Post-inc.
Store Indirect and Pre-dec.
Store Indirect with Displacement
Store Indirect
Store Indirect and Post-inc.
Store Indirect and Pre-dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
Load Program Memory
In Port
Out Port
Push Register on Stack
Pop Register from Stack
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
Logical Shift Right
Rotate Left through Carry
Rotate Right through Carry
Arithmetic Shift Right
Swap Nibbles
Flag Set
Flag Clear
Bit Store from Register to T
Bit Load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Two’s Complement Overflow
Clear Two’s Complement Overflow
Set T in SREG
Clear T in SREG
Set Half-carry Flag in SREG
Clear Half-carry Flag in SREG
No Operation
Sleep
Watchdog Reset
Operation
Rd
←
(Y)
Rd
←
(Y), Y
←
Y + 1
Y
←
Y - 1, Rd
←
(Y)
Rd
←
(Y + q)
Rd
←
(Z)
Rd
←
(Z), Z
←
Z + 1
Z
←
Z - 1, Rd
←
(Z)
Rd
←
(Z + q)
Rd
←
(k)
(X)
←
Rr
(X)
←
Rr, X
←
X + 1
X
←
X - 1, (X)
←
Rr
(Y)
←
Rr
(Y)
←
Rr, Y
←
Y + 1
Y
←
Y - 1, (Y)
←
Rr
(Y + q)
←
Rr
(Z)
←
Rr
(Z)
←
Rr, Z
←
Z + 1
Z
←
Z - 1, (Z)
←
Rr
(Z + q)
←
Rr
(k)
←
Rr
R0
←
(Z)
Rd
←
(Z)
Rd
←
P
P
←
Rr
STACK
←
Rr
Rd
←
STACK
S
←
0
V
←
1
V
←
0
T
←
1
T
←
0
H
←
1
H
←
0
C
←
0
N
←
1
N
←
0
Z
←
1
Z
←
0
I
←
1
I
←
0
S
←
1
I/O(P,b)
←
1
I/O(P,b)
←
0
Rd(n+1)
←
Rd(n), Rd(0)
←
0
Rd(n)
←
Rd(n+1), Rd(7)
←
0
Rd(0)
←
C, Rd(n+1)
←
Rd(n), C
←
Rd(7)
Rd(7)
←
C, Rd(n)
←
Rd(n+1), C
←
Rd(0)
Rd(n)
←
Rd(n+1), n = 0..6
Rd(3..0)
←
Rd(7..4), Rd(7..4)
←
Rd(3..0)
SREG(s)
←
1
SREG(s)
←
0
T
←
Rr(b)
Rd(b)
←
T
C
←
1
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
Flags
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
T
T
V
V
H
H
None
None
None
S
S
I
I
Z
Z
N
N
None
None
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
C
C
T
None
# Clocks
1
2
3
1
2
2
2
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
170
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
Ordering Information
Speed (MHz)
8
Power Supply
2.7 - 5.5V
Ordering Code
ATtiny26L-8PC
ATtiny26L-8SC
ATtiny26L-8MC
ATtiny26L-8PI
ATtiny26L-8SI
ATtiny26L-8MI
ATtiny26L-8PU
ATtiny26L-8SU
ATtiny26L-8MU
Package
(1)
20P3
20S
32M1-A
20P3
20S
32M1-A
20P3
20S
32M1-A
Operational Range
Commercial
(0
°
(-40
C to 70
°
°
Industrial
C to 85
C)
°
C)
16 4.5 - 5.5V
ATtiny26-16PC
ATtiny26-16SC
ATtiny26-16MC
ATtiny26-16PI
ATtiny26-16SI
ATtiny26-16MI
ATtiny26-16PU
ATtiny26-16SU
ATtiny26-16MU
20P3
20S
32M1-A
20P3
20S
32M1-A
20P3
20S
32M1-A
Commercial
(0
°
C to 70
°
Industrial
(-40
°
C to 85
C)
°
C)
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
20P3
20S
32M1-A
1477G–AVR–03/05
Package Type
20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
171
Packaging Information
20P3
D
PIN
1
E1
A
SEATING PLANE
L
B
A1
B1 e
E
C
Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
2325 Orchard Parkway
R
San Jose, CA 95131
TITLE
20P3 eB eC
, 20-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN
A –
A1
D
0.381
25.493
E
E1
B
B1
7.620
6.096
0.356
1.270
NOM
–
–
–
–
–
MAX
5.334
– –
– 25.984 Note 2
8.255
7.112
0.559
1.551
L
C eB eC
2.921
0.203
–
0.000
–
–
–
–
3.810
0.356
10.922
1.524
e 2.540 TYP
NOTE
Note 2
1/12/04
DRAWING NO.
REV.
20P3 C
172
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
20S
C
1
E H
N
Top View
A1
End View
e
D
Side View
b
A
COMMON DIMENSIONS
(Unit of Measure = inches)
E
H
L
C
D e
SYMBOL MIN
A 0.0926
A1 b
0.0040
0.0130
0.0091
0.4961
0.2914
0.3940
0.0160
NOM
0.050 BSC
MAX NOTE
0.1043
0.0118
0.0200
4
0.0125
0.5118
1
0.2992
2
0.4190
0.050
3
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information.
2. Dimension "D" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006") per side.
3. Dimension "E" does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010") per side.
4. "L" is the length of the terminal for soldering to a substrate.
5. The lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm
(0.024") per side.
1/9/02
DRAWING NO.
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
20S2 , 20-lead, 0.300" Wide Body, Plastic Gull
Wing Small Outline Package (SOIC)
20S2
REV.
A
173
1477G–AVR–03/05
32M1-A
D
D1
1
2
3
Pin 1 ID
0
E1 E SIDE VIEW
P
P
TOP VIEW
K
D2
Pin #1 Notch
(0.20 R) b
BOTTOM VIEW e
1
2
3
E2
L
K
A2
A
Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.
A3
A1
0.08 C
D
D1
D2
E
E1
E2
e
L
P
0
K
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN
A 0.80
A1 –
A2
A3
b
–
0.18
NOM
0.90
0.02
0.65
0.20 REF
0.23
2.95
2.95
0.30
–
–
0.20
5.00 BSC
4.75 BSC
3.10
5.00 BSC
4.75BSC
3.10
0.50 BSC
0.40
–
–
–
MAX NOTE
1.00
0.05
1.00
0.30
3.25
3.25
0.50
0.60
12 o
–
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32M1-A , 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm,
3.10 mm Exposed Pad, Micro Lead Frame Package (MLF)
8/19/04
DRAWING NO.
REV.
32M1-A D
174
ATtiny26(L)
1477G–AVR–03/05
Errata
ATtiny26, all revisions
No errata.
ATtiny26(L)
1477G–AVR–03/05
175
Datasheet Revision
History
Changes from Rev.
1477F-12/04 to Rev.
1477G-03/05
Changes from Rev.
1477E-10/03 to Rev.
1477F-12/04
Changes from Rev.
1477D-05/03 to Rev.
1477E-10/03
Changes from Rev.
1477C-09/02 to Rev.
1477D-05/03
Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision.
1.
MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead Frame
Package QFN/MLF”.
2.
Updated “Electrical Characteristics” on page 126
3.
Updated “Ordering Information” on page 171
1.
Updated Table 16 on page 32, Table 9 on page 27, and Table 29 on page 57.
2.
Added Table 20 on page 39.
3.
Added “Changing Channel or Reference Selection” on page 98.
4.
Updated “Offset Compensation Schemes” on page 105.
5.
Updated “Electrical Characteristics” on page 126.
6.
Updated package information for “20P3” on page 172.
7.
Rearranged some sections in the datasheet.
1.
Removed Preliminary references.
2.
3.
Removed SSOP package reference from “Pin Configuration” on page 2.
4.
Updated V
RST
and t
RST
in Table 16 on page 32.
5.
Updated “Calibrated Internal RC Oscillator” on page 28.
6.
Updated DC Characteristics for V
OL
trical Characteristics” on page 126.
, I
IL
, I
IH
, I
CC
Power Down and V
ACIO
7.
Updated V
INT
, INL and Gain Error in “ADC Characteristics” on page 129 and
page 130. Fixed typo in “Absolute Accuracy” on page 130.
8.
Added Figure 106 in “Pin Driver Strength” on page 146, Figure 120, Figure 121
and Figure 122 in “BOD Thresholds and Analog Comparator Offset” on page
155. Updated Figure 117 and Figure 118.
9.
Removed LPM Rd, Z+ from “Instruction Set Summary” on page 169. This
instruction is not supported in ATtiny26.
1.
Updated “Packaging Information” on page 172.
2.
Removed ADHSM from “ADC Characteristics” on page 129.
3.
Added section “EEPROM Write During Power-down Sleep Mode” on page 19.
176
ATtiny26(L)
1477G–AVR–03/05
ATtiny26(L)
4.
Added section “Default Clock Source” on page 25.
5.
Corrected PLL Lock value in the “Bit 0 – PLOCK: PLL Lock Detector” on page
6.
Added information about conversion time when selecting differential chan-
7.
Corrected {DDxn, PORTxn} value on page 43.
8.
Added section “Unconnected Pins” on page 46.
9.
Added note for RSTDISBL Fuse in Table 50 on page 108.
10. Corrected DATA value in Figure 61 on page 116.
11. Added WD_FUSE period in Table 60 on page 123.
13. Updated “ATtiny26 Typical Characteristics” on page 131.
14. Added LPM Rd, Z and LPM Rd, Z+ in “Instruction Set Summary” on page 169.
1.
Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.
Changes from Rev.
1477B-04/02 to Rev.
1477C-09/02
Changes from Rev.
1477A-03/02 to Rev.
1477B-04/02
1.
Removed all references to Power Save sleep mode in the section “System
Clock and Clock Options” on page 22.
2.
Updated the section “Analog to Digital Converter” on page 94 with more
details on how to read the conversion result for both differential and singleended conversion.
3.
Updated “Ordering Information” on page 171 and added QFN/MLF package
information.
177
1477G–AVR–03/05
Table of Contents
ATtiny26(L)
Pin Configuration................................................................................. 2
About Code Examples......................................................................... 5
AVR CPU Core ..................................................................................... 6
Program and Data Addressing Modes................................................................ 10
In-System Programmable Flash Program Memory ............................................ 16
System Clock and Clock Options .................................................... 22
High Frequency PLL Clock – PLLCLK................................................................ 30
System Control and Reset ................................................................ 31
Power Management and Sleep Modes............................................. 36
i
1477G–AVR–03/05
ii
ATtiny26(L)
External Interrupt............................................................................... 62
Timer/Counters .................................................................................. 64
Watchdog Timer................................................................................. 78
Universal Serial Interface – USI........................................................ 80
Analog Comparator ........................................................................... 91
Analog to Digital Converter .............................................................. 94
Changing Channel or Reference Selection ........................................................ 98
Memory Programming..................................................................... 107
Program and Data Memory Lock Bits............................................................... 107
1477G–AVR–03/05
1477G–AVR–03/05
ATtiny26(L)
Parallel Programming Parameters, Pin Mapping, and Commands .................. 109
Electrical Characteristics................................................................ 126
ATtiny26 Typical Characteristics ................................................... 131
Register Summary ........................................................................... 168
Instruction Set Summary ................................................................ 169
Ordering Information ....................................................................... 171
Packaging Information .................................................................... 172
Datasheet Revision History ............................................................ 176
Changes from Rev. 1477F-12/04 to Rev. 1477G-03/05 ................................... 176
Changes from Rev. 1477E-10/03 to Rev. 1477F-12/04 ................................... 176
Changes from Rev. 1477D-05/03 to Rev. 1477E-10/03 ................................... 176
Changes from Rev. 1477C-09/02 to Rev. 1477D-05/03................................... 176
Changes from Rev. 1477B-04/02 to Rev. 1477C-09/02 ................................... 177
Changes from Rev. 1477A-03/02 to Rev. 1477B-04/02 ................................... 177
iii
iv
ATtiny26(L)
1477G–AVR–03/05
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Atmel Operations
Memory
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
Literature Requests www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-
TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT
OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
© Atmel Corporation 2005. All rights reserved. Atmel and Everywhere You Are
SM
®
, logo and combinations thereof, AVR
®
are the trademarks of Atmel Corporation or its subsidiaries. Microsoft
®
, and AVR Studio
, Windows
®
are registered trademarks,
®
, Windows NT
®
, and Windows XP
® are the registered trademarks of Microsoft Corporation. Other terms and product names may be trademarks of others.
Printed on recycled paper.
1477G–AVR–03/05
advertisement
Related manuals
advertisement