GOWIN PicoRV32 Software Download Reference manual

Gowin PicoRV32 Software Download
Reference Manual
IPUG913-1.5E, 08/18/2023
Copyright © 2023 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
and GOWIN are trademarks of Guangdong Gowin Semiconductor Corporation
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and is not responsible for any damage incurred to your hardware, software, data, or
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Revision History
Date
Version
Description
01/16/2020
1.0E
03/06/2020
1.1E
06/01/2020
1.2E
07/16/2021
1.3E
02/11/2022
1.4E
Initial version published.
 MCU supports GPIO of Wishbone bus interface;
 MCU supports extension AHB bus interface;
 MCU supports off-chip SPI-Flash download and startup;
 MCU supports the read, write and erasure SPI-Flash;
 MCU supports Hardware Stack Protection and Trap Stack Overflow.
 MCU on-line debug function supported;
 MCU core interrupt handler function enhanced;
 MCU core instruction optimized;
 Mergebin tool updated supports GowinSynthesis® to parse the rules of
naming.
 The synthesis tool, SynplifyPro, deleted;
 FPGA software version updated;
 Supported devices updated.
The reference design of makehex and mergebin added.
08/18/2023
1.5E
Arora V FPGA products supported.
Contents
Contents
Contents ............................................................................................................... i
List of Figures .................................................................................................... iii
List of Tables ...................................................................................................... iv
1 Download Methods ......................................................................................... 1
2 Software Programming Output Used as ITCM Initialization Value .............. 3
2.1 Tools.................................................................................................................................... 3
2.2 Command Parameters........................................................................................................ 3
2.3 Hardware Configuration ...................................................................................................... 3
2.4 Software Configuration ....................................................................................................... 4
2.4.1 Configure BUILD_MODE ................................................................................................. 4
2.4.2 Flash linker Configuration ................................................................................................ 4
2.4.3 Output File Format Configuration .................................................................................... 5
2.5 Design Flow ........................................................................................................................ 5
2.6 Devices Supported ............................................................................................................. 6
3 Merge Results of Software Design and Hhardware Design ........................ 7
3.1 Tools.................................................................................................................................... 7
3.2 Command Parameters........................................................................................................ 7
3.3 Hardware Configuration ...................................................................................................... 8
3.3.1 ITCM Configuration.......................................................................................................... 8
3.3.2 Post-Place File Configuration .......................................................................................... 9
3.4 Software Configuration ....................................................................................................... 9
3.4.1 BUILD_MODE Configuration ........................................................................................... 9
3.4.2 Flash linker Configuration .............................................................................................. 10
3.4.3 Output File Format Configuration .................................................................................. 10
3.5 Design Flow ...................................................................................................................... 10
3.5.1 Merge ............................................................................................................................. 10
3.5.2 Download ....................................................................................................................... 11
3.6 Devices Supported ........................................................................................................... 11
4 Off-chip SPI-Flash Memory Download ........................................................ 12
4.1 Software Configuration ..................................................................................................... 12
IPUG913-1.5E
i
Contents
4.1.1 BUILD_MODE Configuration ......................................................................................... 12
4.1.2 Flash Linker Configuration ............................................................................................. 13
4.2 Hardware Configuration .................................................................................................... 15
4.2.1 ITCM Configuration........................................................................................................ 15
4.2.2 Dual-Purpose Pin Configuration .................................................................................... 16
4.3 Design Flow ...................................................................................................................... 16
4.4 Download .......................................................................................................................... 17
4.4.1 Download Bitstream Files in Hardware Design ............................................................. 17
4.4.2 Download Software Programming Design BIN File ....................................................... 19
4.5 Devices Supported ........................................................................................................... 21
IPUG913-1.5E
ii
List of Figures
List of Figures
Figure 2-1 Boot Mode and ITCM Initial Value Configuration ............................................................. 4
Figure 2-2 BUILD_MODE Configuration ............................................................................................ 4
Figure 2-3 Flash Linker Configuration ............................................................................................... 5
Figure 3-1 ITCM Configuration .......................................................................................................... 8
Figure 3-2 Post-Place File Configuration ........................................................................................... 9
Figure 3-3 Boot Mode Configuration .................................................................................................. 9
Figure 3-4 Flash Linker Configuration ............................................................................................... 10
Figure 3-5 Merge the Outputs of Software Design and Hardware Design ........................................ 11
Figure 4-1 BUILD_MODE "BUILD_BURN" Configuration ................................................................. 12
Figure 4-2 BUILD_MODE "BUILD_XIP" Configuration...................................................................... 13
Figure 4-3 Flash Linker Configuration ............................................................................................... 14
Figure 4-4 Flash Linker Configuration ............................................................................................... 15
Figure 4-5 ITCM Configuration .......................................................................................................... 16
Figure 4-6 Dual-Purpose Pin Configuration ....................................................................................... 16
Figure 4-7 Arora Family Device configuration .................................................................................... 18
Figure 4-8 Arora V Device Configuration ........................................................................................... 19
Figure 4-9 Arora Family Device configuration .................................................................................... 20
Figure 4-10 Arora V Device configuration .......................................................................................... 21
IPUG913-1.5E
iii
List of Tables
List of Tables
Table 3-1 mergebin Commands and Parameters .............................................................................. 7
IPUG913-1.5E
iv
1 Download Methods
1
Download Methods
Gowin_PicoRV32 provides three download methods of hardware
design and software design:
1. Use the mapping file generated by software programming design as
the initial value of ITCM, the instruction memory, in hardware design.
a) Gowin_PicoRV32 software programming design:
-
Define the macro definition of config.h as #define
BUILD_MODE BUILD_LOAD
-
Select sections.lds as FLASH linker
-
Build to generate software programming design BIN files.
b) Use makehex tool to convert the software programming design BIN
files to ram32.hex, the mapping file in a hexadecimal format;
c) Configure ITCM, the instruction memory, where IP Core Generator
generates Gowin_PicoRV32 design.
-
Select "MCU boot and run in ITCM" in Boot Mode.
-
ITCM Initialiaztion File import ram32.hex file in b) as the initial
value of ITCM.
d) Synthesis, place & route to generate the bitstream files in hardware
design including software programming design and hardware
design;
e) Use Programmer to download bitstream files in hardware design;
f)
After each update of the software programming design, rerun a) ~
e).
2. Merge the software programming design BIN files generated by
software programming design and the BIN files in hardware design
generated by hardware design.
a) Generate the Gowin_PicoRV32 bitstream files and Post-Place File
in hardware design according to the application requirements in
accordance with Method 1. If there is no hardware update
requirement, the fixed bitstream files in hardware design will not be
updated.
IPUG913-1.5E
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1 Download Methods
b) Update Gowin_PicoRV32 software programming design:
-
Define the macro definition of config.h as #define
BUILD_MODE BUILD_LOAD
-
Configure sections.lds as FLASH linker
-
Update user application design according to the application
requirements
-
Build to generate software programming design BIN files.
c) Use mergebin tool to merge the software programming design BIN
files and bitstream files in hardware design in a);
d) Generate new bitstream files in hardware design after merging the
software design and the hardware design;
e) Use Programmer to download the new bitstream files in hardware
design after merging.
f)
After each update of the software programming design, rerun b) ~
e).
3. Use off-chip SPI-Flash memory to download the BIN files generated by
software programming design.
a) Configure ITCM, the instruction memory, where IP Core Generator
generates Gowin_PicoRV32 design.
-
Select "MCU boot and run in external Flash" or "MCU boot
from external Flash and run in ITCM" in Boot Mode
b) Gowin_PicoRV32 hardware design generates bitstream files in
hardware design with the function of off-chip SPI-Flash
downloading and startup;
c) Use Programmer to download bitstream files in hardware design;
d) Gowin_PicoRV32 software programming design:
-
MCU boot and run in external Flash
Define the macro definition of config.h as #define
BUILD_MODE BUILD_XIP
Select sections_xip.lds as FLASH linker
-
MCU boot from external Flash and run in ITCM
Define the macro definition of config.h as #define
BUILD_MODE BUILD_BURN
Select sections.lds as FLASH linker
-
Build to generate software programming design BIN files.
e) Use Programmer to download the BIN files generated by software
programming design.
IPUG913-1.5E
2(21)
2 Software Programming Output Used as ITCM Initialization Value
2.1 Tools
2
Software Programming Output
Used as ITCM Initialization Value
2.1 Tools
…\tool\makehex\bin\makehex32.exe
…\tool\makehex\bin\makehex08.exe
Note!
Access the above software tools via this link:
http://cdn.gowinsemi.com.cn/Gowin_PicoRV32.zip
2.2 Command Parameters
Software tool command and parameter
 makehex32.exe bin-file
 makehex08.exe bin-file
2.3 Hardware Configuration
Double click to open ITCM configuration options when configuring
Gowin_PicoRV32 in IP Core Generator tool integrated in Gowin Software:
Select "ITCM > Boot Mode > MCU boot and run in ITCM" option.
Import ram32.hex, the mapping file in a hexadecimal format, as the
initial value of ITCM in "ITCM Initialization File", as shown in Figure 2-1.
IPUG913-1.5E
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2 Software Programming Output Used as ITCM Initialization Value
2.4 Software Configuration
Figure 2-1 Boot Mode and ITCM Initial Value Configuration
2.4 Software Configuration
2.4.1 Configure BUILD_MODE
Define the macro definition of config.h as #define BUILD_MODE
BUILD_LOAD, as shown in Figure 2-2.
Figure 2-2 BUILD_MODE Configuration
2.4.2 Flash linker Configuration
In the "Project Explorer" view of GMD software, select the current
software project, right-click and select "Properties > C/C++ Build >
Settings > Tool Settings > GNU RISC-V Cross C Linker > General", select
"sections.lds" as the Flash linker, as shown in Figure 2-3.
IPUG913-1.5E
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2 Software Programming Output Used as ITCM Initialization Value
2.5 Design Flow
Figure 2-3 Flash Linker Configuration
2.4.3 Output File Format Configuration
Compile Gowin_PicoRV32 software programming design and
generate software programming design BIN files.
Run makehex32.exe bin-file to generate ram32.hex, the mapping file
in a hexadecimal format.
2.5 Design Flow
1. Gowin_PicoRV32 software programming design:
-
The definition of config.h: #define BUILD_MODE BUILD_LOAD
-
Select section.lds as FLASH linker
-
Build to generate software programming design BIN files
-
Run makehex32.exe to generate ram32.hex, the mapping file in a
hexadecimal format, as the initial value of ITCM in
Gowin_PicoRV32 IP design
2. Gowin_PicoRV32 Hardware Design:
-
Select "ITCM > Boot Mode > MCU boot and run in ITCM" option
-
Import ram32.hex as the initial value of ITCM in "ITCM Initialization
File"
3. Generate Gowin_PicoRV32 IP design, instantiate Gowin_PicoRV32
IPUG913-1.5E
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2 Software Programming Output Used as ITCM Initialization Value
2.6 Devices Supported
Top Module, and connect user design
4. Add physical and timing Constraints
5. Use GowinSynthesis® to synthesize and generate the netlist file
6. Run Place & Route tool to generate the bitstream files containing
software programming design
7. Use Programmer to download
8. After each update of the software programming design, rerun 1~7
2.6 Devices Supported
IPUG913-1.5E

LittleBee® Family FPGA products

Arora Family FPGA products

Arora V FPGA products
6(21)
3 Merge Results of Software Design and Hardware Design
3
3.1 Tools
Merge Results of Software Design
and Hardware Design
3.1 Tools
…\tool\mergebin\bin\mergebin.bat
Access the above software tools via this link:
http://cdn.gowinsemi.com.cn/Gowin_PicoRV32.zip
3.2 Command Parameters

Software tool: mergebin.bat

mergebin software commands and parameters:
call posp_parse.exe posp-file itcm-size gwsyn
call merge_bit.exe bin-file BramLoc.txt fs-file
For the description of commands and parameters, please refer to
Table 3-1.
Table 3-1 mergebin Commands and Parameters
IPUG913-1.5E
Parameter
Description
posp_parse.exe
Parse the posp file generated by place & layout,
generate the location information of BSRAM in ITCM,
and output to the BramLoc.txt file.
posp-file
posp file name, same with the project name, with an
extension of posp.
itcm-size
The ITCM Size (KB) of Gowin_PicoRV32
For example, if set ITCM as 64K Byte, the value is 64.
gwsyn
Specify GowinSynthesis® as the synthesis tool.
merge_bit.exe
Merge Gowin_PicoRV32 software design and hardware
design
bin-file
software programming design BIN files generated by
Gowin_PicoRV32 software programming design
BramLoc.txt
ITCM layout location information file generated by
posp_parse.exe
fs-file
Bitstream files in hardware design generated by
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3 Merge Results of Software Design and Hardware Design
Parameter
3.3 Hardware Configuration
Description
Gowin_PicoRV32 hardware design
Merge the software programming design BIN files generated by
software programming design and the bitstream files in hardware design
generated by hardware design.
When mergebin.bat is in use, you can modify the parameters, such as
posp-file, itcm-size, bin-file, and fs-file according to your requirements.
3.3 Hardware Configuration
Generate the Gowin_PicoRV32 IP design according to Method 1 in
Chapter 2, synthesize, place and layout to generate the bitstream files and
Post-Place File in hardware design. If there is no hardware update
requirement, the fixed bitstream files in hardware design will not be
updated.
After each update of the software programming design, simply use the
mergebin tool each time to merge the bitstream files in hardware design
mentioned above with the software programming design BIN files for each
update.
3.3.1 ITCM Configuration
Double click to open ITCM configuration options when configuring
Gowin_PicoRV32 in IP Core Generator tool integrated in Gowin Software:

Select "ITCM > Boot Mode > MCU boot and run in ITCM" option

Import ram32.hex, the mapping file in a hexadecimal format, as the
initial value of ITCM in "ITCM Initialization File", as shown in Figure 3-1.
Figure 3-1 ITCM Configuration
IPUG913-1.5E
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3 Merge Results of Software Design and Hardware Design
3.4 Software Configuration
3.3.2 Post-Place File Configuration
A posp file, as the posp input file of posp_parse.exe, will be generated
when the value in "Place & Route > General > Generate Post-Place File" is
True, as shown in Figure 3-2.
Figure 3-2 Post-Place File Configuration
3.4 Software Configuration
3.4.1 BUILD_MODE Configuration
Configure the macro definition of config.h as #define BUILD_MODE
BUILD_LOAD, as shown in Figure 3-3.
Figure 3-3 Boot Mode Configuration
IPUG913-1.5E
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3 Merge Results of Software Design and Hardware Design
3.5 Design Flow
3.4.2 Flash linker Configuration
In the "Project Explorer" view of GMD software, select the current
software project, right-click and select "Properties > C/C++ Build >
Settings > Tool Settings > GNU RISC-V Cross C Linker > General", select
sections.lds as the Flash linker, as shown in Figure 3-4.
Figure 3-4 Flash Linker Configuration
3.4.3 Output File Format Configuration
Compile Gowin_PicoRV32 software programming design and
generate software programming design BIN files.
3.5 Design Flow
3.5.1 Merge
1. Generate the Gowin_PicoRV32 bitstream files and Post-Place File in
hardware design according to the application requirements in
accordance with Method 1 in Chapter 2. If there is no hardware update
requirement, the fixed bitstream files in hardware design will not be
updated.
2. Update Gowin_PicoRV32 software programming design:
IPUG913-1.5E
-
Define the macro definition of config.h as #define BUILD_MODE
BUILD_LOAD
-
Select sections.lds as FLASH linker
10(21)
3 Merge Results of Software Design and Hardware Design
3.6 Devices Supported
-
Update user application design according to the application
requirements
-
Build to generate software programming design BIN files.
3. Modify mergebin.bat according to the actual application, perform
mergebin.bat, merge the bitstream files in hardware design generated
by hardware design and the software programming design BIN files
generated by software programming design to generate new bitstream
files, as shown in Figure 3-5;
4. After each update of the software programming design, rerun 3~4.
Figure 3-5 Merge the Outputs of Software Design and Hardware Design
3.5.2 Download
After merging, use Programmer, the download tool, to download the
new bitstream files in hardware design.
For the usage of Gowin Programmer, please see SUG502, Gowin
Programmer User Guide.
3.6 Devices Supported
Arora Family FPGA products
IPUG913-1.5E
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4 Off-chip SPI-Flash Memory Download
4.1 Software Configuration
4
Off-chip SPI-Flash Memory
Download
4.1 Software Configuration
4.1.1 BUILD_MODE Configuration
If "ITCM > Boot Mode > MCU boot from external Flash and run in
ITCM" is selected in Gowin_PicoRV32 IP design, then config.h is defined
as #define BUILD_MODE BUILD_BURN in Gowin_PicoRV32 software
programming design config.h, as shown in Figure 4-1.
Figure 4-1 BUILD_MODE "BUILD_BURN" Configuration
If the "ITCM > Boot Mode > MCU boot and run in external Flash" is
selected in Gowin_PicoRV32 IP design, then config.h is defined as #define
BUILD_MODE BUILD_XIP in Gowin_PicoRV32 software programming
design config.h, as shown in Figure 4-2.
IPUG913-1.5E
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4 Off-chip SPI-Flash Memory Download
4.1 Software Configuration
Figure 4-2 BUILD_MODE "BUILD_XIP" Configuration
4.1.2 Flash Linker Configuration
If "ITCM > Boot Mode > MCU boot from external Flash and run in
ITCM" is selected in the Gowin_PicoRV32 IP design, then the current
software project is selected in the "Project Explorer" view of the GMD
software; right-click and select "Properties > C/C++ Build > Settings > Tool
Settings > GNU RISC-V Cross C Linker > General", then select
"Selections.lds" as the Flash linker, as shown in Figure 4-3.
For example, "${workspace_loc:/${ProjName}/src/sections.lds}".
IPUG913-1.5E
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4 Off-chip SPI-Flash Memory Download
4.1 Software Configuration
Figure 4-3 Flash Linker Configuration
If "ITCM > Boot Mode > MCU boot and run in external Flash" is
selected in the Gowin_PicoRV32 IP design, then the current software
project is selected in the "Project Explorer" view of the GMD software;
right-click and select "Properties > C/C++ Build > Settings > Tool Settings >
GNU RISC-V Cross C Linker > General", then select "sections_xip.lds" as
the Flash linker, as shown in Figure 4-4。
For example, "${workspace_loc:/${ProjName}/src/sections_xip.lds}".
IPUG913-1.5E
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4 Off-chip SPI-Flash Memory Download
4.2 Hardware Configuration
Figure 4-4 Flash Linker Configuration
4.2 Hardware Configuration
4.2.1 ITCM Configuration
Select the "ITCM > Boot Mode > MCU Boots from External Flash and
Runs in ITCM" or "MCU Boots from External Flash and Runs in External
Flash" option in the IP Core Generator tool of Gowin Software, as shown in
Figure 4-5.
IPUG913-1.5E
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4 Off-chip SPI-Flash Memory Download
4.3 Design Flow
Figure 4-5 ITCM Configuration
4.2.2 Dual-Purpose Pin Configuration
Configure MSPI as regular IO under "Place & Route > Dual-Purpose
Pin", as shown in Figure 4-6.
Figure 4-6 Dual-Purpose Pin Configuration
4.3 Design Flow
1. Gowin_PicoRV32 Hardware Design:
IPUG913-1.5E
-
Select "Boot Mode > MCU boot from external Flash and run in
ITCM" or "MCU boot and run in external Flash"
-
Generate Gowin_PicoRV32 IP design
16(21)
4 Off-chip SPI-Flash Memory Download
-
4.4 Download
Synthesis, place & route to generate the bitstream files with
off-chip SPI-Flash memory download function
2. Configure Device configuration with Programmer to download the
bitstream files in hardware design.
3. Gowin_PicoRV32 software programming design:
-
MCU boot and run in external Flash:
Define the macro definition of config.h as #define BUILD_MODE
BUILD_XIP
Select sections_xip.lds as FLASH linker
-
MCU boot from external Flash and run in ITCM
Define the macro definition of config.h as #define BUILD_MODE
BUILD_BURN
Select sections.lds as FLASH linker
-
Build to generate software programming design BIN files.
4. Configure Device configuration with Programmer to download the
software programming design BIN files.
4.4 Download
For the usage of Gowin Programmer, please see SUG502, Gowin
Programmer User Guide.
4.4.1 Download Bitstream Files in Hardware Design
Gowin_PicoRV32 hardware design generates bitstream files with the
function of off-chip SPI-Flash downloading and startup. Use the download
tool Programmer to download the hardware design bitstream file.
Click "Tools > Programmer" in the menu bar or "Programmer" (
the tool bar to open the "Device configuration".
) in
If the development board has a Arora Family FPGA product on board,
the download configuration option is as shown in Figure 4-7.

Select "External Flash Mode" in "Access Mode" drop-down list.

Select "exFlash Erase, Program thru GAO-Bridge" or "exFlash Erase,
Program, Verify thru GAO-Bridge" in "Operation" drop-down list.

Import the hardware design bitstream file required to download in
"Programming Options > File name" option.

Select "Generic Flash" from "External Flash Options > Device".

Set "0x000000" in "External Flash Options > Start Address".
Click "Save", as shown in Figure 4-7.
IPUG913-1.5E
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4 Off-chip SPI-Flash Memory Download
4.4 Download
Figure 4-7 Arora Family Device configuration
If the development board has a Arora V FPGA product on board, the
download configuration option is as shown in Figure 4-8.

Select "External Flash Mode 5AT" in "Access Mode" drop-down list.

Select "exFlash Erase, Program 5AT" or "exFlash Erase, Program,
Verify 5AT" in "Operation" drop-down list.

Import the hardware design bitstream file required to download in
"Programming Options > File name" option.

Select "Generic Flash" from "External Flash Options > Device".

Set "0x000000" in "External Flash Options > Start Address".
Click "Save", as shown in Figure 4-8.
IPUG913-1.5E
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4 Off-chip SPI-Flash Memory Download
4.4 Download
Figure 4-8 Arora V Device Configuration
After device configuration, click "Program/Configure" (
) in the
Programmer toolbar to complete the downloading of bitstream files in
hardware design.
4.4.2 Download Software Programming Design BIN File
After Gowin_PicoRV32 software programming design, generate
software programming design BIN files, and use Programmer to download
Gowin_PicoRV32 software programming design BIN files.
In GMD software, click "Run＞Programmer" from the menu bar or
"Programmer" ( ) from the tool bar to open Programmer.
(
Click "Edit > Configure Device" in the menu bar or "Configure Device"
) in the tool bar to open the "Device configuration".
If the development board has a Arora Family FPGA product on board,
the download configuration option is as shown in Figure 4-9.

Select "External Flash Mode" in "Access Mode" drop-down list.

Select "exFlash C Bin Erase, Program thru GAO-Bridge" or "exFlash C
Bin Erase, Program, Verify thru GAO-Bridge" in "Operation" drop-down
list.

Select "FW/MCU Input Options > Firmware/Binary File" to import the
software programming design BIN files to download.

Select "Generic Flash" from "External Flash Options > Device".

Set "0x400000" in "External Flash Options > Start Address".
Click "Save", as shown in Figure 4-9.
IPUG913-1.5E
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4 Off-chip SPI-Flash Memory Download
4.4 Download
Figure 4-9 Arora Family Device configuration
If the development board has a Arora V FPGA product on board, the
download configuration option is as shown in Figure 4-10.

Select "External Flash Mode 5AT" in "Access Mode" drop-down list.

Select "exFlash C Bin Erase, Program 5AT" or "exFlash Erase,
Program, Verify 5AT" in "Operation" drop-down list.

Import the hardware design bitstream file required to download in
"FW/MCU/Binary Input Options > Firmware/Binary File" option.

Select "Generic Flash" from "External Flash Options > Device".

Set "0x600000" in "External Flash Options > Start Address".
Click "Save", as shown in Figure 4-10.
IPUG913-1.5E
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4 Off-chip SPI-Flash Memory Download
4.5 Devices Supported
Figure 4-10 Arora V Device configuration
After device configuration, click "Program/Configure" (
) in the
Programmer tool bar to complete the downloading of software
programming design BIN files.
4.5 Devices Supported
IPUG913-1.5E

Arora Family FPGA products

Arora V FPGA products
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