GOWIN GW1NS-2C MCU Software Program Reference manual

Gowin_EMPU(GW1NS-2C) Software
Programming
Reference Manual
IPUG516-1.5E, 06/22/2021
Copyright © 2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
, Gowin, and GOWINSEMI are trademarks of Guangdong Gowin
Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark
Office, and other countries. All other words and logos identified as trademarks or service
marks are the property of their respective holders. No part of this document may be
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Disclaimer
GOWINSEMI assumes no liability and provides no warranty (either expressed or implied)
and is not responsible for any damage incurred to your hardware, software, data, or
property resulting from usage of the materials or intellectual property except as outlined in
the GOWINSEMI Terms and Conditions of Sale. All information in this document should be
treated as preliminary. GOWINSEMI may make changes to this document at any time
without prior notice. Anyone relying on this documentation should contact GOWINSEMI for
the current documentation and errata.
Revision History
Date
Version
Description
08/30/2018
1.0E
Initial version published.
11/30/2018
1.1E
04/12/2019

Software programming libraries optimized.

uC/OS-III and FreeRTOS operating systems supported.

Extented peripheral I2C, SPI and UART software
programming supported.
1.2E

08/06/2019
12/02/2019
1.2.1E
1.3E
MCU software programming libraries updated.
 MCU
software
reference design updated.
Known
issue
of SPIprogramming
and ADC fixed.

MCU compiling software GMD V1.0 updated.

RTOS reference design updated.

Hardware and software reference design of AHB2 and
APB2 extented bus interface added.
04/27/2020
06/22/2021
1.4E
1.5E

Known issue of ADC conversion precision fixed.

GW1NSR-2C supporting AHB PSRAM of MCU.

Development board reference design updated.

Known issue of SPI full duplex read and write fixed.

Known issue of GPIO in/out initialization fixed.

MCU software upgraded.

Reference design updated.
Contents
Contents
Contents ............................................................................................................... i
List of Figures .................................................................................................... iv
List of Tables ....................................................................................................... v
1 Software Programming Library ...................................................................... 1
1.1 MCU Core Software Programming .................................................................................... 1
1.2 Embedded Operating System Software Programming ...................................................... 2
2 Memory System ............................................................................................... 3
2.1 Standard Peripherals Memory Mapping ............................................................................. 3
2.2 Core System Memory Mapping .......................................................................................... 4
3 Interrupt Handler ............................................................................................. 5
4 Universal Asynchronous Receiver/Transmitter ............................................ 8
4.1 Features ............................................................................................................................. 8
4.2 Register Description ........................................................................................................... 9
4.3 Initialization Definition ....................................................................................................... 10
4.4 Usage of Drivers ............................................................................................................... 11
4.5 Reference Design ............................................................................................................. 11
5 Timer ............................................................................................................... 13
5.1 Features ........................................................................................................................... 13
5.2 Register Description ......................................................................................................... 14
5.3 Initialization Definition ....................................................................................................... 14
5.4 Usage of Drivers ............................................................................................................... 14
5.5 Reference Design ............................................................................................................. 15
6 Watchdog ....................................................................................................... 16
6.1 Features ........................................................................................................................... 16
6.2 Register Description ......................................................................................................... 16
IPUG516-1.5E
i
Contents
6.3 Initialization Definition ....................................................................................................... 17
6.4 Usage of Drivers ............................................................................................................... 18
6.5 Reference Design ............................................................................................................. 18
7 GPIO ............................................................................................................... 19
7.1 Features ........................................................................................................................... 19
7.2 Register Description ......................................................................................................... 20
7.3 Initialization Definition ....................................................................................................... 22
7.4 Usage of Drivers ............................................................................................................... 23
7.5 Reference Design ............................................................................................................. 24
8 ADC ................................................................................................................. 25
8.1 Features ........................................................................................................................... 25
8.2 Register Description ......................................................................................................... 25
8.3 Initialization Definition ....................................................................................................... 26
8.4 Usage of Drivers ............................................................................................................... 26
8.5 Reference Design ............................................................................................................. 27
9 SPI................................................................................................................... 28
9.1 Features ........................................................................................................................... 28
9.2 Register Description ......................................................................................................... 28
9.3 Initialization Definition ....................................................................................................... 29
9.4 Usage of Drivers ............................................................................................................... 29
9.5 Reference Design ............................................................................................................. 30
10 System Controller ........................................................................................ 31
10.1 Register Description ....................................................................................................... 31
10.2 Usage of Drivers ............................................................................................................. 31
11 I2C .................................................................................................................. 33
11.1 Features.......................................................................................................................... 33
11.2 Register Description ....................................................................................................... 33
11.3 Usage of Drivers ............................................................................................................. 34
11.4 Reference Design ........................................................................................................... 34
12 FPGA Logic Extended Universal Asynchronous Receiver/Transmitter .. 35
12.1 Features ......................................................................................................................... 35
12.2 Register Description ....................................................................................................... 36
IPUG516-1.5E
ii
Contents
12.3 Initialization Definition ..................................................................................................... 37
12.4 Usage of Drivers ............................................................................................................. 38
12.5 Reference Design ........................................................................................................... 38
13 SysTick ......................................................................................................... 39
13.1 Features ......................................................................................................................... 39
13.2 Register Description ....................................................................................................... 39
13.3 Usage of Drivers ............................................................................................................. 40
13.4 Reference Design ........................................................................................................... 40
14 Memory Management .................................................................................. 41
14.1 Features ......................................................................................................................... 41
14.2 Usage of Drivers ............................................................................................................. 41
14.3 Reference Design ........................................................................................................... 41
15 AHB PSRAM ................................................................................................. 42
15.1 Features ......................................................................................................................... 42
15.2 Register Description ....................................................................................................... 42
15.3 Usage of Drivers ............................................................................................................. 44
15.4 Reference Design ........................................................................................................... 44
16 Embedded Real-time Operating System .................................................... 45
16.1 uC/OS-III ........................................................................................................................ 45
16.1.1 Features ...................................................................................................................... 45
16.1.2 Operating System Version .......................................................................................... 45
16.1.3 Operating System Configuration ................................................................................. 45
16.1.4 Reference Design ....................................................................................................... 46
16.2 FreeRTOS ...................................................................................................................... 46
16.2.1 Features ...................................................................................................................... 46
16.2.2 Operating System Version .......................................................................................... 46
16.2.3 Operating System Configuration ................................................................................. 46
16.2.4 Reference Design ....................................................................................................... 46
IPUG516-1.5E
iii
List of Figures
List of Figures
Figure 4-1 UART Buffering Diagram .................................................................................................. 9
Figure 5-1 TIMER Diagram ................................................................................................................ 13
Figure 6-1 WatchDog Operation Diagram ......................................................................................... 16
Figure 7-1 GPIO Block Diagram ........................................................................................................ 19
Figure 12-1 UART Buffering Diagram ................................................................................................ 36
IPUG516-1.5E
iv
List of Tables
List of Tables
Table 1-1 MCU Core Software Programming .................................................................................... 1
Table 2-1 Definition of Standard Peripherals Memory Mapping ........................................................ 3
Table 2-2 Definition of System Control Memory Mapping ................................................................. 4
Table 3-1 Definition of Interrupt Controller ......................................................................................... 5
Table 4-1 UART Register Description ................................................................................................ 9
Table 4-2 UART Initialization Definition .............................................................................................. 10
Table 4-3 Usage of UART Drivers ...................................................................................................... 11
Table 5-1 TIMER Register Description ............................................................................................... 14
Table 5-2 TIMER Initialization Definition ............................................................................................ 14
Table 5-3 Usage of TIMER Drivers .................................................................................................... 14
Table 6-1 Watchdog Register Description .......................................................................................... 17
Table 6-2 WatchDog Initialization Definition ....................................................................................... 17
Table 6-3 Usage of WatchDog Drivers ............................................................................................... 18
Table 7-1 GPIO Register Description ................................................................................................. 20
Table 7-2 GPIO Initialization Definition .............................................................................................. 22
Table 7-3 Usage of GPIO Drivers ...................................................................................................... 23
Table 8-1 ADC Register Description .................................................................................................. 25
Table 8-2 ADC Initialization Definition ................................................................................................ 26
Table 8-3 Usage of ADC Drivers ........................................................................................................ 26
Table 9-1 SPI Master Register Description ........................................................................................ 28
Table 9-2 SPI Master Initialization Definition ..................................................................................... 29
Table 9-3 Usage of SPI Master Drivers ............................................................................................. 29
Table 10-1 SYSCON Register Description ........................................................................................ 31
Table 10-2 Usage of SYSCON Drivers .............................................................................................. 31
2
Table 11-1 I C Master Register Description ....................................................................................... 33
2
Table 11-2 Usage of I C Master Drivers ............................................................................................. 34
Table 12-1 UART Register Description .............................................................................................. 36
IPUG516-1.5E
v
List of Tables
Table 12-2 UART Initialization Definition ............................................................................................ 37
Table 12-3 Usage of UART Drivers .................................................................................................... 38
Table 13-1 SysTick Register Description ........................................................................................... 39
Table 13-2 Usage of SysTick Drivers ................................................................................................. 40
Table 14-1 Usage of Memory Management Drivers .......................................................................... 41
Table 15-1 AHB PSRAM Register Description ................................................................................... 42
Table 15 -2 Usage of AHB PSRAM Drivers ....................................................................................... 44
IPUG516-1.5E
vi
1 Software Programming Library
1
1.1 MCU Core Software Programming
Software Programming Library
Gowin_EMPU(GW1NS-2C) supports software programming library:
Gowin_EMPU\src\c_lib
Gowin_EMPU(GW1NS-2C) supports two kinds of software
programming:

MCU core software programming

Embedded operating system software programming
1.1 MCU Core Software Programming
Gowin_EMPU(GW1NS-2C) software programming library supports
MCU core software programming, as shown in Table 1-1.
Table 1-1 MCU Core Software Programming
Files
Description
startup_gw1ns2c.s
MCU core startup program
core_cm3.c
MCU core register definition
gw1ns2c.h
Definition of interrupt vector table, register, and address
mapping
IPUG516-1.5E
system_gw1ns2c.c
System initialization and system clock definition
gw1ns2c_flash.ld
GMD EDA Flash linker
gw1ns2c_adc.c
ADC drive function definition
gw1ns2c_gpio.c
GPIO drive function definition
gw1ns2c_uart.c
UART drive function definitiom
gw1ns2c_timer.c
Timer drive function definition
gw1ns2c_wdog.c
Watchdog drive function definition
gw1ns2c_spi.c
SPI Master drive function definition
1(47)
1 Software Programming Library
1.2 Embedded Operating System Software Programming
Files
Description
gw1ns2c_i2c.c
I2C Master drive function definition
gw1ns2c_misc.c
Interrupt priority management and SysTick
gw1ns2c_syscon.c
System control drive function definition
gw1ns2c_it.c
Interrupt handler function definition
malloc.c
Dynamic memory management malloc and free
function redirection definition
retarget.c
UART0 printf function redirection definition
gowin_psram.c
AHB PSRAM drive function definition
1.2 Embedded Operating System Software Programming
Gowin_EMPU(GW1NS-2C) supports software programming in the
following two real-time operating systems:
IPUG516-1.5E

uC/OS-III

FreeRTOS
2(47)
2 Memory System
2.1 Standard Peripherals Memory Mapping
2
Memory System
2.1 Standard Peripherals Memory Mapping
The standard peripherals memory mapping addresses for
Gowin_EMPU(GW1NS-2C) are as shown in Table 2-1.
Table 2-1 Definition of Standard Peripherals Memory Mapping
Standard Peripheral
Type
Address Mapping
Description
FLASH
–
0x00000000
128KB
SRAM
–
0x20000000
2KB, 4KB, 8KB
TIMER0
TIMER_TypeDef
0x40000000
Timer 0
TIMER1
TIMER_TypeDef
0x40001000
Timer 1
UART0
UART_TypeDef
0x40004000
UART0
UART1
UART_TypeDef
0x40005000
UART1
WatchDog
WDOG_TypeDef
0x40008000
Watchdog
GPIO0
GPIO_TypeDef
0x40010000
GPIO port
SYSCON
SYSCON_TypeDef
0x4001F000
System Control
I2C
I2C_TypeDef
0x40002000
I2C
ADC
ADC_TypeDef
0x40002100
ADC
SPI
SPI_TypeDef
0x40002200
SPI
FPGA
UART
UART_TypeDef
0x40002300
Logic
Universal
Extended
Asynchronous
Receiver/Transmitter
APB2 Master 1
–
0x40002400
APB2 Master [1]
APB2 Master 2
–
0x40002500
APB2 Master [2]
APB2 Master 3
–
0x40002600
APB2 Master [3]
APB2 Master 4
–
0x40002700
APB2 Master [4]
IPUG516-1.5E
3(47)
2 Memory System
2.2 Core System Memory Mapping
Standard Peripheral
Type
Address Mapping
Description
APB2 Master 5
–
0x40002800
APB2 Master [5]
APB2 Master 6
–
0x40002900
APB2 Master [6]
APB2 Master 7
–
0x40002A00
APB2 Master [7]
APB2 Master 8
–
0x40002B00
APB2 Master [8]
APB2 Master 9
–
0x40002C00
APB2 Master [9]
APB2 Master 10
–
0x40002D00
APB2 Master [10]
APB2 Master 11
–
0x40002E00
APB2 Master [11]
APB2 Master 12
–
0x40002F00
APB2 Master [12]
AHB2 Master
–
0xA0000000
AHB2 Master
AHB2 Slave
–
–
AHB2 Slave
PSRAM
PSRAM_TypeDef
0xA0000000
AHB PSRAM
2.2 Core System Memory Mapping
Gowin_EMPU(GW1NS-2C) core system memory mapping definition is
as shown in Table 2-2 .
Table 2-2 Definition of System Control Memory Mapping
System Control
Type
Address Mapping
Description
ITM
ITM_Type
0xE0000000
ITM configuration structure
DWT
DWT_Type
0xE0001000
DWT configuration structure
CoreDebug
CoreDebug_Type
0xE000EDF0
Core Debug configuration structure
ETM
ETM_Type
0xE0041000
ETM configuration structure
SysTick
SysTick_Type
0xE000E010
SysTick configuration structure
NVIC
NVIC_BASE
0xE000E100
NVIC configuration structure
SCnSCB
SCnSCB_Type
0xE000E000
System control Register not in SCB
SCB
SCB_Type
0xE000ED00
SCB configuration structure
TPIU
TPIU_Type
0xE0040000
TPIU configuration structure
IPUG516-1.5E
4(47)
3 Interrupt Handler
3
Interrupt Handler
The nested vector interrupt controller (NVIC) includes the following
features:

Supports up to 32 low latency interrupts;

Provides 2 interrupt handler signals to users (USER_INT0 and
USER_INT1);

Supports programmable interrupt priorities of 0 -7;

Low latency interrupts and exception handler;

Interrupt signal edge or pulse detection;

Interrupt priority adjustment.
Gowin_EMPU(GW1NS-2C) interrupt controller definition is shown in
Table 3-1.
Table 3-1 Definition of Interrupt Controller
Address
Interrupt
Number
Description
0x00000000
__StackTop
–
Top of Stack
0x00000004
Reset_Handler
–
Reset Handler
0x00000008
NMI_Handler
–
NMI Handler
0x0000000C
HardFault_Handler
-13
Hard Fault Handler
0x00000010
MemManage_Handler
-12
MPU Fault Handler
0x00000014
BusFault_Handler
-11
Bus Fault Handler
0x00000018
UsageFault_Handler
-10
Usage Fault Handler
0x0000001C
0
–
Reserved
0x00000020
0
–
Reserved
0x00000024
0
–
Reserved
0x00000028
0
–
Reserved
0x0000002C
SVC_Handler
-5
SVCall Handler
IPUG516-1.5E
5(47)
3 Interrupt Handler
Address
Interrupt
Number
Description
0x00000030
DebugMon_Handler
-4
Debug Monitor Handler
0x00000034
0
–
Reserved
0x00000038
PendSV_Handler
-2
PendSV Handler
0x0000003C
SysTick_Handler
-1
SysTick Handler
0x00000040
UART0_Handler
0
16+ 0: UART 0 RX and TX Handler
0x00000044
Spare1_Handler
1
16+ 1: Not Used
0x00000048
UART1_Handler
2
16+ 2: UART 1 RX and TX Handler
0x0000004C
Spare3_Handler
3
16+ 3: Not Used
0x00000050
Spare4_Handler
4
16+ 4: Not Used
0x00000054
0
–
16+ 5: Reserved
0x00000058
PORT0_COMB_Handler
6
16+ 6: GPIO Port 0 Combined Handler
0x0000005C
Spare7_Handler
7
16+ 7: Not Used
0x00000060
TIMER0_Handler
8
16+ 8: TIMER 0 handler
0x00000064
TIMER1_Handler
9
16+ 9: TIMER 1 handler
0x00000068
0
–
16+10: Reserved
0x0000006C
Spare11_Handler
11
16+11: Not Used
0x00000070
UARTOVF_Handler
12
16+12: UART 0,1 Overflow Handler
0x00000074
USER_INT0_Handler
13
16+13: USER_INT0 Handler
0x00000078
USER_INT1_Handler
14
16+14: USER_INT1 Handler
0x0000007C
Spare15_Handler
15
16+ 15: Not Used
0x00000080
PORT0_0_Handler
16
16+16: GPIO Port 0 pin 0 Handler
0x00000084
PORT0_1_Handler
17
16+17: GPIO Port 0 pin 1 Handler
0x00000088
PORT0_2_Handler
18
16+18: GPIO Port 0 pin 2 Handler
0x0000008C
PORT0_3_Handler
19
16+19: GPIO Port 0 pin 3 Handler
0x00000090
PORT0_4_Handler
20
16+20: GPIO Port 0 pin 4 Handler
0x00000094
PORT0_5_Handler
21
16+21: GPIO Port 0 pin 5 Handler
0x00000098
PORT0_6_Handler
22
16+22: GPIO Port 0 pin 6 Handler
0x0000009C
PORT0_7_Handler
23
16+23: GPIO Port 0 pin 7 Handler
0x000000A0
PORT0_8_Handler
24
16+24: GPIO Port 0 pin 8 Handler
0x000000A4
PORT0_9_Handler
25
16+25: GPIO Port 0 pin 9 Handler
0x000000A8
PORT0_10_Handler
26
16+26: GPIO Port 0 pin 10 Handler
0x000000AC
PORT0_11_Handler
27
16+27: GPIO Port 0 pin 11 Handler
IPUG516-1.5E
6(47)
3 Interrupt Handler
Address
Interrupt
Number
Description
0x000000B0
PORT0_12_Handler
28
16+28: GPIO Port 0 pin 12 Handler
0x000000B4
PORT0_13_Handler
29
16+29: GPIO Port 0 pin 13 Handler
0x000000B8
PORT0_14_Handler
30
16+30: GPIO Port 0 pin 14 Handler
0x000000BC
PORT0_15_Handler
31
16+31: GPIO Port 0 pin 15 Handler
IPUG516-1.5E
7(47)
4 Universal Asynchronous Receiver/Transmitter
4
4.1 Features
Universal Asynchronous
Receiver/Transmitter
4.1 Features
There are two UARTs accessed by the APB in
Gowin_EMPU(GW1NS-2C):

The max. baud rate is 921.6Kbit/s;

No parity bit;

8-bit data bit;

1-bit stop bit.
UART Buffering diagram is as shown in Figure 4-1.
IPUG516-1.5E
8(47)
4 Universal Asynchronous Receiver/Transmitter
4.2 Register Description
Figure 4-1 UART Buffering Diagram
You can write a new character to the write buffer
While the shift register is sending out a character.
Write buffer
TXD
Shift register
TX FSM
APB
interface
Baud rate
generator
RX FSM
RXD
Shift register
Read buffer
The shift register can receive the next
character while the data in the receive
buffer is waiting for the processor to
read it.
The UART supports the High Speed Test Mode (HSTM). When the
register CTRL[6] is set to 1, the serial data is transmitted one bit per cycle,
and the text information can be transmitted in a short time.
The baud rate divider register should be set when using UART. For
example, if the APB1 bus frequency is running at 12MHz and the baud rate
is required to be 9600, the baud rate divider register can be set to
12000000/9600=1250.
4.2 Register Description
The UART register description is as shown in Table 4-1.
Table 4-1 UART Register Description
Name
Address Offset
Type
Width
Initial Value
Description
DATA
0x000
RW
8
0x--
[7:0] Data Value
[3] RX buffer overrun,
write 1 to clear
STATE
0x004
RW
4
0x0
[2] TX buffer overrun,
write 1 to clear
[1]
IPUG516-1.5E
RX
buffer
full,
9(47)
4 Universal Asynchronous Receiver/Transmitter
Name
Address Offset
4.3 Initialization Definition
Type
Width
Initial Value
Description
read-only
[0]
TX
buffer
full,
speed
test
read-only
[6]
High
mode for TX only
[5] RX overrun interrupt
enable
[4] TX overrun interrupt
CTRL
0x008
RW
7
0x00
enable
[3] RX interrupt enable
[2] TX interrupt enable
[1] RX enable
[0] TX enable
[3] RX overrun interrupt,
write 1 to clear
INTSTAT
US/
INTCLEA
[2] TX overrun interrupt,
0x00C
RW
4
0x0
R
write 1 to clear
[1] RX interrupt, write 1
to clear
[0] TX interrupt, write 1
to clear
BAUDDI
V
[19:0] Baud rate divider,
0x010
RW
20
0x00000
the minimum number is
16
4.3 Initialization Definition
The UART initialization definition is shown in Table 4-2.
Table 4-2 UART Initialization Definition
Name
Type
Value
Description
UART_BaudRate
uint32_t
Max 921.6Kbit/s
Baud rate
UART_Mode
UARTMode_TypeDef
ENABLE/DISABLE
Enable/Disable TX/RX mode
UART_Int
UARTInt_TypeDef
ENABLE/DISABLE
Enable/Disable TX/RX interrupt
UART_Ovr
UARTOvr_TypeDef
ENABLE/DISABLE
UART_Hstm
FunctionalState
ENABLE/DISABLE
IPUG516-1.5E
Enable/Disable
TX/RX
overrun
interrupt
Enable/Disable TX high speed test
mode
10(47)
4 Universal Asynchronous Receiver/Transmitter
4.4 Usage of Drivers
4.4 Usage of Drivers
The usage of UART drivers is shown in Table 4-3.
Table 4-3 Usage of UART Drivers
Name
Description
UART_Init
Initializes UARTx
UART_GetRxBufferFull
Returns UARTx RX buffer full status
UART_GetTxBufferFull
Returns UARTx TX buffer full status
UART_GetRxBufferOverrunStatus
Returns UARTx RX buffer overrun status
UART_GetTxBufferOverrunStatus
Returns UARTx TX buffer overrun status
UART_ClearRxBufferOverrunStatus
Clears Rx buffer overrun status
UART_ClearTxBufferOverrunStatus
Clears Tx buffer overrun status
UART_SendChar
Sends a character to UARTx TX buffer
UART_SendString
Sends a string to UARTx TX buffer
UART_ReceiveChar
Receives a character from UARTx RX buffer
UART_GetBaudDivider
Returns UARTx baud rate divider value
UART_GetTxIRQStatus
Returns UARTx TX interrupt status
UART_GetRxIRQStatus
Returns UARTx RX interrupt status
UART_ClearTxIRQ
Clears UARTx TX interrupt status
UART_ClearRxIRQ
Clears UARTx RX interrupt status
UART_GetTxOverrunIRQStatus
Returns UARTx TX overrun interrupt status
UART_GetRxOverrunIRQStatus
Returns UARTx RX overrun interrupt status
UART_ClearTxOverrunIRQ
Clears UARTx TX overrun interrupt request
UART_ClearRxOverrunIRQ
Clears UARTx RX overrun interrupt request
UART_SetHSTM
Sets UARTx TX high speed test mode
UART_ClrHSTM
Clears UARTx TX high speed test mode
4.5 Reference Design
Gowin_EMPU(GW1NS-2C) supports UART software programming
reference design in ARM Keil MDK V5.26 and above and GOWIN MCU
Designer V1.1 and above. Click the link to get the following reference
designs: https://www.gowinsemi.com/en/document/.zip
IPUG516-1.5E

Gowin_EMPU\ref_design\MCU_RefDesign \Keil_RefDesign\uart

Gowin_EMPU\ref_design\MCU_RefDesign \Keil_RefDesign\retarget
11(47)
4 Universal Asynchronous Receiver/Transmitter
IPUG516-1.5E
4.5 Reference Design

Gowin_EMPU\ref_design\MCU_RefDesign \Keil_RefDesign\uart0_int

Gowin_EMPU\ref_design\MCU_RefDesign\GMD_RefDesign\uart

Gowin_EMPU\ref_design\MCU_RefDesign \GMD_RefDesign\retarget

Gowin_EMPU\ref_design\MCU_RefDesign \GMD_RefDesign\uart0_int
12(47)
5 Timer
5.1 Features
5
Timer
5.1 Features
There two synchronization standard timers accessed by APB in
Gowin_EMPU(GW1NS-2C):

32-bit counter

Supports the interrupt request signal

Supports the external input signal EXTIN to enable clock

TIMER0: EXTIN connects to GPIO [1]

TIMER1: EXTIN connects to GPIO [6]
The TIMER diagram is shown in Figure 5-1.
Figure 5-1 TIMER Diagram
IPUG516-1.5E
13(47)
5 Timer
5.2 Register Description
5.2 Register Description
The TIMER register description is as shown in Table 5-1 .
Table 5-1 TIMER Register Description
Name
Address Offset
Type
Width
Initial Value
Description
[3] Timer interrupt enable
CTRL
0x000
RW
4
[2] Select external input as clock
0x0
[1] Select external input as enable
[0] Enable
VALUE
0x004
RW
32
0x00000000
RELOAD
0x008
RW
32
0x00000000
0x00C
RW
1
0x0
INTSTATUS
/INTCLEAR
[31:0] Current value
[31:0] Reload value, writing to this
register sets the current value
[0] Timer interrupt, write 1 to clear
5.3 Initialization Definition
The TIMER initialization definition is as shown in Table 5-2.
Table 5-2 TIMER Initialization Definition
Name
Type
Value
Description
Reload
uint32_t
–
Reload value
TIMER_Int
TIMERInt_TypeDef
SET/RESET
Enable/Disable interrupt
TIMER_Exti
TIMERExti_TypeDef
–
External input as enable or clock
5.4 Usage of Drivers
The usage of TIMER drivers is shown in Table 5-3.
Table 5-3 Usage of TIMER Drivers
IPUG516-1.5E
Name
Description
TIMER_Init
Initializes TIMERx
TIMER_StartTimer
Starts TIMERx
TIMER_StopTimer
Stops TIMERx
TIMER_GetIRQStatus
Returns TIMERx interrupt status
TIMER_ClearIRQ
Clears TIMERx interrupt status
TIMER_GetReload
Returns TIMERx reload value
14(47)
5 Timer
5.5 Reference Design
Name
Description
TIMER_SetReload
Sets TIMERx reload value
TIMER_GetValue
Returns TIMERx current value
TIMER_SetValue
Sets TIMERx current value
TIMER_EnableIRQ
Enable TIMERx interrupt request
TIMER_DisableIRQ
Disable TIMERx interrupt request
5.5 Reference Design
Gowin_EMPU(GW1NS-2C) supports Timer software programming
reference design in ARM Keil MDK V5.26 and above and GOWIN MCU
Designer V1.1 and above. Click the link to get the following reference
designs: https://www.gowinsemi.com/en/document/.zip
IPUG516-1.5E

Gowin_EMPU\ref_design\MCU_RefDesign\Keil_RefDesign\timer

Gowin_EMPU\ref_design\MCU_RefDesign\GMD_RefDesign\timer
15(47)
6 Watchdog
6.1 Features
6
Watchdog
6.1 Features
There is one WatchDog accessed by the APB in
Gowin_EMPU(GW1NS-2C):

A 32-bit down-counter initialized by the LOAD register;

Supports interrupt request;

When the clock is enabled, the counter is decremented by the posedge
of the WDOGCLK signal;

A reset request is generated and the counter is stopped when the
counter is decremented to 0 to monitor interrupts;

Provide reset caused by software crash and method.
WatchDog operation daigram is shown in Figure 6-1.
Figure 6-1 WatchDog Operation Diagram
Counter reloaded
and count down
without reprogram
Count down
without reprogram
WatchDog is
programmed
Counter reaches
zero
Counter reaches
zero
If the INTEN bit in the
WDOGCONTROL
register is set to 1,
WDOGINT is asserted
If the RESEN bit in the
WDOGCONTROL
register is set to 1,
WDOGRES is asserted
6.2 Register Description
The WatchDog register description is as shown in Table 6-1.
IPUG516-1.5E
16(47)
6 Watchdog
6.3 Initialization Definition
Table 6-1 Watchdog Register Description
Name
Address Offset
Type
Width
Initial Value
Description
LOAD
0x00
RW
32
0xFFFFFFFF
VALUE
0x04
RO
32
0xFFFFFFFF
CTRL
0x08
RW
2
0x0
INTCLR
0x0C
WO
–
–
RIS
0x10
RO
1
0x0
MIS
0x14
RO
1
0x0
RESERVED
0xC00-0x014
–
–
–
LOCK
0xC00
RW
32
0x00000000
RESERVED
0xF00-0xC00
–
–
–
Reserved
ITCR
0xF00
RW
1
0x0
Integration test mode enable
The value from which the counter
is to decrement
The
current
value
of
the
decrementing counter
[1] Enable reset output
[0] Enable the interrupt
Clears the watchdog interrupt and
reloads the counter
Raw interrupt status from the
counter
Enable interrupt status from the
counter
Reserved
[32:1] Enable register writes
[0] Register write enable status
[1] Integration test WDOGRES
ITOP
0xF04
WO
2
value
0x0
[0] Integration test WDOGINT
value
6.3 Initialization Definition
The WatchDog initialization definition is as shown in Table 6-2.
Table 6-2 WatchDog Initialization Definition
Name
Type
Value
Description
WDOG_Reload
uint32_t
–
Reloads value
WDOG_Lock
WDOGLock_TypeDef
SET/RESET
Enable/Disable lock register write access
WDOG_Res
WDOGRes_TypeDef
SET/RESET
Enable/Disable reset flag
WDOG_Int
WDOGInt_TypeDef
SET/RESET
Enable/Disable interrupt flag
WDOG_ITMode
WDOGMode_Typedef
SET/RESET
Enable/Disable integration test mode flag
IPUG516-1.5E
17(47)
6 Watchdog
6.4 Usage of Drivers
6.4 Usage of Drivers
The usage of WatchDog drivers is shown in Table 6-3.
Table 6-3 Usage of WatchDog Drivers
Name
Description
WDOG_Init
Initializes WatchDog
WDOG_RestartCounter
Restarts watchdog counter
WDOG_GetCounterValue
Returns counter value
WDOG_SetResetEnable
Sets reset enable
WDOG_GetResStatus
Returns reset status
WDOG_SetIntEnable
Sets interrupt enable
WDOG_GetIntStatus
Returns interrupt enable
WDOG_ClrIntEnable
Clears interrupt enable
WDOG_GetRawIntStatus
Returns raw interrupt status
WDOG_GetMaskIntStatus
Returns masked interrupt status
WDOG_LockWriteAccess
Disable write access all registers
WDOG_UnlockWriteAccess
Enable write access all registers
WDOG_SetITModeEnable
Sets integration test mode enable
WDOG_ClrITModeEnable
Clears integration test mode enable
WDOG_GetITModeStatus
Returns integration test mode status
WDOG_SetITOP
Sets integration test output reset or interrupt
WDOG_GetITOPResStatus
Returns integration test output reset status
WDOG_GetITOPIntStatus
Returns integration test output interrupt status
WDOG_ClrITOP
Clears integration test output reset or interrupt
6.5 Reference Design
Gowin_EMPU(GW1NS-2C) supports WatchDog software
programming reference design in ARM Keil MDK V5.26 and above and
GOWIN MCU Designer V1.1 and above. Click the link to get the following
reference designs: https://www.gowinsemi.com/en/document/.zip
IPUG516-1.5E

Gowin_EMPU\ref_design\MCU_RefDesign\Keil_RefDesign\wdog

Gowin_EMPU\ref_design\MCU_RefDesign\GMD_RefDesign\watchdo
g
18(47)
7 GPIO
7.1 Features
7
GPIO
7.1 Features
There is one GPIO module with a 16-bit input and output interface
accessed by AHB in Gowin_EMPU(GW1NS-2C):

Connects with FPGA Fabric;

Each IO pin can generate an interrupt;

Supports the bit mask;

Supports pin multiplexing
The GPIO block diagram is as shown in Figure 7-1.
Figure 7-1 GPIO Block Diagram
IPUG516-1.5E
19(47)
7 GPIO
7.2 Register Description
7.2 Register Description
The GPIO register description is as shown in Table 7-1.
Table 7-1 GPIO Register Description
Name
Address Offset
Type
Width
Initial Value
Description
[15:0] Data value
Read Sampled at pin
Write to data output register
DATA
0x0000
RW
16
0x----
Read back value goes through
double flip-flop
synchronization logic with delay of
two cycles
[15:0] Data output register value
DATAOUT
0x0004
RW
16
0x0000
Read current value of data output
register
write to data output register
RESERVED
0x0008
-0x000C
–
–
–
Reserved
[15:0] Output enable set
Write 1 to set the output enable bit
Write 0 no effect
OUTENSET
0x0010
RW
16
0x0000
Read back 0 indicates the signal
direction as input
1 indicates the signal direction as
output
[15:0] Output enable clear
Write 1 to clear the output enable bit
Write 0 no effect
OUTENCLR
0x0014
RW
16
0x0000
Read back 0 indicates the signal
direction as input
1 indicates the signal direction as
output
[15:0] Alternative function set
Write 1 to set the ALTFUNC bit
ALTFUNCS
ET
0x0018
RW
16
0x0000
Write 0 no effect
Read back 0 for I/O
1 for an alternate function
IPUG516-1.5E
20(47)
7 GPIO
Name
7.2 Register Description
Address Offset
Type
Width
Initial Value
Description
[15:0] Alternative function clear
Write 1 to clear the ALTFUNC bit
ALTFUNCC
LR
0x001C
RW
16
0x0000
Write 0 no effect
Read back 0 for I/O
1 for an alternate function
[15:0] Interrupt enable set
Write 1 to set the enable bit
INTENSET
0x0020
RW
16
0x0000
Write 0 no effect
Read back 0 indicates interrupt
disabled
1 indicates interrupt enabled
[15:0] Interrupt enable clear
Write 1 to clear the enable bit
INTENCLR
0x0024
RW
16
0x0000
Write 0 no effect
Read back 0 indicates interrupt
disabled
1 indicates interrupt enabled
[15:0] Interrupt type set
Write 1 to set the interrupt type bit
INTTYPESE
T
0x0028
RW
16
0x0000
Write 0 no effect
Read back 0 for LOW/HIGH level
1 for falling edge or rising edge
[15:0] Interrupt type clear
Write 1 to clear the interrupt type bit
INTTYPECL
R
0x002C
RW
16
0x0000
Write 0 no effect
Read back 0 for LOW/HIGH level
1 for falling edge or rising edge
[15:0]
Polarity-level,
edge
IRQ
configuration
Write 1 to set the interrupt polarity bit
INTPOLSET
0x0030
RW
16
0x0000
Write 0 no effect
Read back 0 for LOW level or falling
edge
1 for HIGH level or rising edge
INTPOLCL
R
IPUG516-1.5E
0x0034
RW
16
0x0000
[15:0]
Polarity-level,
edge
IRQ
configuration
21(47)
7 GPIO
7.3 Initialization Definition
Name
Address Offset
Type
Width
Initial Value
Description
Write 1 to clear the interrupt polarity
bit
Write 0 no effect
Read back 0 for LOW level or falling
edge
1 for HIGH level or rising edge
[15:0] Write IRQ status clear register
INTSTATUS
/INTCLEAR
0x0038
RW
16
0x0000
Write 1 to clear interrupt request
Write 0 no effect
Read back IRQ status register
Lower 8-bit masked access
[9:2] of the address value are used
as enable bit mask for the access
MASKLOW
0x0400
BYTE
-0x07FC
RW
16
0x----
[15:8] not used
[7:0] Data for lower byte access, with
[9:2] of address value used as
enable mask for each bit
Higher 8-bit masked access
[9:2] of the address value are used
as enable bit mask for the access
MASKHIGH
0x0800
BYTE
-0x0BFC
RW
16
0x----
[15:8] Data for higher byte access,
with [9:2] of address value used as
enable mask for each bit
[7:0] not used
RESERVED
0x0C00
–
-0x0FCF
–
–
Reserved
7.3 Initialization Definition
The GPIO initialization definition is shown in Table 7-2.
Table 7-2 GPIO Initialization Definition
Name
Type
Value
Description
GPIO_Pin_0
GPIO_Pin_1
GPIO_Pin
uint32_t
GPIO_Pin_2
16 bits GPIO Pins
GPIO_Pin_3
GPIO_Pin_4
IPUG516-1.5E
22(47)
7 GPIO
7.4 Usage of Drivers
Name
Type
Value
Description
GPIO_Pin_5
GPIO_Pin_6
GPIO_Pin_7
GPIO_Pin_8
GPIO_Pin_9
GPIO_Pin_10
GPIO_Pin_11
GPIO_Pin_12
GPIO_Pin_13
GPIO_Pin_14
GPIO_Pin_15
GPIO_Mode_IN
GPIO_Mode
GPIOMode_TypeDef
GPIO_Mode_OUT
16 bits GPIO Pins mode
GPIO_Mode_AF
GPIO_Int_Disable
GPIO_Int_Low_Level
GPIO_Int
GPIOInt_TypeDef
GPIO_Int_High_Level
16 bits GPIO Pins interrupt
GPIO_Int_Falling_Edge
GPIO_Int_Rising_Edge
7.4 Usage of Drivers
The usage of GPIO drivers is shown in Table 7-3.
Table 7-3 Usage of GPIO Drivers
IPUG516-1.5E
Name
Description
GPIO_Init
Initializes GPIOx
GPIO_SetOutEnable
Sets GPIOx output enable
GPIO_ClrOutEnable
Clears GPIOx output enable
GPIO_GetOutEnable
Returns GPIOx output enable
GPIO_SetBit
GPIO output one
GPIO_ResetBit
GPIO output zero
GPIO_WriteBits
GPIO output
GPIO_ReadBits
GPIO input
GPIO_SetAltFunc
Sets GPIOx alternate function enable
GPIO_ClrAltFunc
Clears GPIOx alternate function enable
23(47)
7 GPIO
7.5 Reference Design
Name
Description
GPIO_GetAltFunc
Returns GPIOx alternate function enable
GPIO_IntClear
Clears GPIOx interrupt request
GPIO_GetIntStatus
Returns GPIOx interrupt status
GPIO_SetIntEnable
GPIO_ClrIntEnable
Sets GPIOx interrupt enable
Returns GPIOx interrupt status
Clears GPIOx interrupt enable
Returns GPIOx interrupt enable
GPIO_SetIntHighLevel
Setups GPIOx interrupt as high level
GPIO_SetIntRisingEdge
Setups GPIOx interrupt as rising edge
GPIO_SetIntLowLevel
Setups GPIOx interrupt as low level
GPIO_SetIntFallingEdge
Setups GPIOx interrupt as falling edge
GPIO_MaskedWrite
Setups GPIOx output value using masked access
7.5 Reference Design
Gowin_EMPU(GW1NS-2C) supports GPIO software programming
reference design in ARM Keil MDK V5.26 and above and GOWIN MCU
Designer V1.1 and above. Click the link to get the following reference
designs: https://www.gowinsemi.com/en/document/.zip
IPUG516-1.5E

Gowin_EMPU\ref_design\MCU_RefDesign\Keil_RefDesign\led

Gowin_EMPU\ref_design\MCU_RefDesign\Keil_RefDesign\keyscan

Gowin_EMPU\ref_design\MCU_RefDesign\Keil_RefDesign\DigitalSeg

Gowin_EMPU\ref_design\MCU_RefDesign\GMD_RefDesign\led

Gowin_EMPU\ref_design\MCU_RefDesign\GMD_RefDesign\keyscan

Gowin_EMPU\ref_design\MCU_RefDesign\GMD_RefDesign\DigitalSe
g
24(47)
8 ADC
8.1 Features
8
ADC
8.1 Features
There is one ADC module accessed by the APB in
Gowin_EMPU( GW1NS-2C:

APB interface

Max. Clock frequency16MHz

User-defined VREF reference voltage

8-Channel, time-sharing ADC
8.2 Register Description
The ADC register description is shown in Table 8-1.
Table 8-1 ADC Register Description
Name
Address Offset
Type
Width
Initial Value
DATA
0x00
RO
12
0x000
Description
[11:0]
data
[1]
STATUS
0x04
RW
2
0x0
conversion
Start
of
conversion status
[0]
End
of
conversion status
[5] AD conversion
mode
CTRL
0x08
RW
6
0x00
[4] AD conversion
starting
[2:0] Channel
IPUG516-1.5E
25(47)
8 ADC
8.3 Initialization Definition
8.3 Initialization Definition
The ADC initialization definition is shown in Table 8-2.
Table 8-2 ADC Initialization Definition
Name
Type
ADC_Mode
uint32_t
ADC_Status
uint32_t
Value
Description
ADC_MODE_CONT
ADC_MODE_SINGLE
ADC_STATUS_ON
ADC_STATUS_OFF
ADC continuous or single conversion mode
Start or stop conversion
ADC_CHSEL_0
ADC_CHSEL_1
ADC_CHSEL_2
ADC_Chsel
uint32_t
ADC_CHSEL_3
ADC_CHSEL_4
ADC channel 0-7
ADC_CHSEL_5
ADC_CHSEL_6
ADC_CHSEL_7
8.4 Usage of Drivers
The usage of ADC drivers is shown in Table 8-3.
Table 8-3 Usage of ADC Drivers
IPUG516-1.5E
Name
Description
ADC_Init
Initializes ADC
ADC_SetMode
Sets ADC conversion mode
ADC_GetMode
Returns ADC conversion mode
ADC_SetPowerStatus
Sets ADC running status
ADC_GetPowerStatus
Returns ADC running status
ADC_SetChannel
Sets ADC conversion channel
ADC_GetChannel
Returns ADC conversion channel
ADC_GetEocStatus
Returns stopping status
ADC_GetSocStatus
Returns starting status
ADC_ReadData
Returns ADC conversion data
26(47)
8 ADC
8.5 Reference Design
8.5 Reference Design
Gowin_EMPU(GW1NS-2C) supports ADC software programming
reference design in ARM Keil MDK V5.26 and above and GOWIN MCU
Designer V1.1 and above. Click the link to get the following reference
designs: https://www.gowinsemi.com/en/document/.zip
IPUG516-1.5E

Gowin_EMPU\ref_design\MCU_RefDesign\Keil_RefDesign\adc

Gowin_EMPU\ref_design\MCU_RefDesign\GMD_RefDesign\adc
27(47)
9 SPI
9.1 Features
9
SPI
9.1 Features
There is one SPI Master module accessed by APB in
Gowin_EMPU(GW1NS-2C):






APB interface
Full duplex synchronous serial data transmission
Supports Master working mode
Supports configurable clock polarity and phase
Configurable serial clock frequency generated by SPI
8 bits width for data receive register and data transmission register
9.2 Register Description
The definition of SPI Master register is as shown in Table 9-1.
Table 9-1 SPI Master Register Description
Name
Address Offset
Type
Width
Initial Value
Description
RDATA
0x00
RO
8
0x00
Read data register
WDATA
0x04
WO
8
0x00
Write data register
[7] Error status
[6]
Receive
ready
status
[5]
STATUS
0x08
RW
8
0x00
Transmit
ready
status
[4] Be transmitting
[3] Transmit overrun
error status
[2] Receive overrun
IPUG516-1.5E
28(47)
9 SPI
9.3 Initialization Definition
Name
Address Offset
Type
Width
Initial Value
Description
error status
[1:0] Reserved
SSMASK
0x0C
RW
8
0x00
Unused
selected
slave address
[4:3] Clock selected
CTRL
0x10
RW
5
0x00
[2] Polarity
[1] Phase
[0] Direction
9.3 Initialization Definition
The SPI Master initialization definition is shown in Table 9-2.
Table 9-2 SPI Master Initialization Definition
Name
Type
Value
Description
MSB/LSB first transmission
DIRECTION
uint8_t
1/0
0: MSB first;
1: LSB first.
Posedge/Negedge transmit data
PHASE
uint8_t
1/0
0: Sample at posedge edge;
1: Sample at negedge edge.
Initialize polarity to one/zero
POLARITY
uint8_t
1/0
0: Idle sclk low;
1: Idle sclk high.
CLKSEL_CLK_DIV_2
CLKSEL
uint8_t
CLKSEL_CLK_DIV_4
CLKSEL_CLK_DIV_6
Select clock divided 2/4/6/8
CLKSEL_CLK_DIV_8
9.4 Usage of Drivers
The usage of SPI Master drivers is shown in Table 9-3.
Table 9-3 Usage of SPI Master Drivers
IPUG516-1.5E
Name
Description
SPI_Init
Initializes SPI
SPI_SetDirection
Sets direction
29(47)
9 SPI
9.5 Reference Design
Name
Description
SPI_ClrDirection
Clears direction
SPI_GetDirection
Returns direction
SPI_SetPhase
Sets phase
SPI_ClrPhase
Clears phase
SPI_GetPhase
Returns phase
SPI_SetPolarity
Sets polarity
SPI_ClrPolarity
Clears polarity
SPI_GetPolarity
Returns polarity
SPI_SetClkSel
Sets clock selection
SPI_GetClkSel
Returns clock selection
SPI_GetToeStatus
Reads transmit overrun error status
SPI_GetRoeStatus
Reads receive overrun error status
SPI_GetTmtStatus
Reads transmitting status
SPI_GetTrdyStatu
Reads transmit ready status
SPI_GetRrdyStatus
Reads receive ready error status
SPI_GetErrStatus
Reads error status
SPI_ClrToeStatus
Clears transmit overrun error status
SPI_ClrRoeStatus
Clears receive overrun error status
SPI_ClrErrStatus
Clears error status
SPI_ReadWriteByte
Full duplex read and write a byte
SPI_WriteData
Writes data
SPI_ReadData
Reads data
SPI_Select_Slave
Select slave
9.5 Reference Design
Gowin_EMPU(GW1NS-2C) supports SPI Master software
programming reference design in ARM Keil MDK V5.26 and above and
GOWIN MCU Designer V1.1 and above. Click the link to get the following
reference designs: https://www.gowinsemi.com/en/document/.zip
IPUG516-1.5E

Gowin_EMPU\ref_deisgn\MCU_RefDesign\Keil_RefDesign\spi

Gowin_EMPU\ref_deisgn\MCU_RefDesign\GMD_RefDesign\spi
30(47)
10 System Controller
10.1 Register Description
10
System Controller
10.1 Register Description
The SYSCON register description is shown in Table 10-1.
Table 10-1 SYSCON Register Description
Name
Address Offset
Type
Width
Initial Value
REMAP
0x000
RW
1
0x0
PMUCTRL
0x004
RW
1
0x0
RESETOP
0x008
RW
1
0x0
0x00C
–
–
–
RESERVED
0
Description
Remap
control
register
PMU
control
register
reset
option
register
Reserved
[2] Lockup reset
[1]
RSTINFO
0x010
RW
3
0x0
Watchdog
reset request
[0] System reset
request
10.2 Usage of Drivers
The usage of SYSCON drivers is shown in Table 10-2.
Table 10-2 Usage of SYSCON Drivers
IPUG516-1.5E
Name
Description
SYSCON_Init
Initializes SYSCON
SYSCON_GetRemap
Returns REMAP
31(47)
10 System Controller
IPUG516-1.5E
10.2 Usage of Drivers
Name
Description
SYSCON_GetPmuctrlEnable
Returns PMUCTRL Enable
SYSCON_GetResetopLockuprst
Returns RESETOP LOCKUPRST
SYSCON_GetRstinfoSysresetreq
Returns RSTINFO SYSRESETREQ
SYSCON_GetRstinfoWdogresetreq
Returns RSTINFO SYSRESETREQ
SYSCON_GetRstinfoLockreset
Returns RSTINFO SYSRESETREQ
32(47)
11 I2C
11.1 Features
11
I2 C
11.1 Features
There is one I2C Master module accessed by the APB in
Gowin_EMPU(GW1NS-2C):







APB interface
Compliant with I2C protocol;
Bus arbitration and arbitration lost detection;
Bus busy detection;
Start/Stop/Repeated Start/Acknowledge generation;
Start/Stop/Repeated Start detection;
Supports 7-bit addressing mode.
11.2 Register Description
The I2C Master register description is as shown in Table 11-1.
Table 11-1 I2C Master Register Description
Name
Address Offset
Type
Width
Initial Value
Description
Clock prescale register
PRER
0x00
RW
16
0xFFFF
[15:0]
Prescale
value
=
sys_clk/(5*SCL)-1
CTR
0x04
RW
8
0x00
TXR
0x08
WO
8
0x00
RXR
0x0C
RO
8
0x00
[7] Enable I2C
[7:1] Next transmission data
[0] Data direction
[7:0] Last received data
[7] Start transmission status
CR
0x010
WO
8
0x00
[6] Over transmission status
[5] Read enable, read data from
IPUG516-1.5E
33(47)
11 I2C
11.3 Usage of Drivers
Name
Address Offset
Type
Width
Initial Value
Description
slave
[4] Write enable, write data to slave
[3] Acknowledge
[7] Receive acknowledge signal
from slave
SR
0x14
RO
8
0x00
[6] I2C busy status
[5] Arbitration loss
[1] Data transmission status flag
11.3 Usage of Drivers
The usage of I2C Master drivers is shown in Table 11-2.
Table 11-2 Usage of I2C Master Drivers
Name
Description
I2C_Init
I2C Initialization
I2C_SendByte
Sends a byte to I2C bus
I2C_SendBytes
Sends multiple bytes to I2C bus
I2C_SendData
Sends multiple bytes to I2C bus once time
I2C_ReceiveByte
Reads a byte from I2C bus
I2C_ReadBytes
Reads multiple bytes from I2C bus
I2C_ReceiveData
Reads multiple bytes from I2C bus once time
I2C_Rate_Set
Sets I2C traffic rate
I2C_Enable
Enable I2C bus
I2C_UnEnable
Disable I2C bus
11.4 Reference Design
Gowin_EMPU(GW1NS-2C) supports I2C Master software
programming reference design in ARM Keil MDK V5.26 and above and
GOWIN MCU Designer V1.1 and above. Click the link to get the following
reference designs: https://www.gowinsemi.com/en/document/.zip
IPUG516-1.5E

Gowin_EMPU\ref_design\MCU_RefDesign\Keil_RefDesign\i2c

Gowin_EMPU\ref_design\MCU_RefDesign\GMD_RefDesign\i2c
34(47)
12 FPGA Logic Extended Universal Asynchronous Receiver/Transmitter
12.1 Features
12
FPGA Logic Extended Universal
Asynchronous Receiver/Transmitter
12.1 Features
There is one FPGA logic extended UART accessed by the APB2 in
Gowin_EMPU( GW1NS-2C):

The max. baud rate is 921.6Kbit/s

No parity bit

8-bit data bit

1-bit stop bit
UART Buffering diagram is as shown in Figure 12-1 .
IPUG516-1.5E
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12 FPGA Logic Extended Universal Asynchronous Receiver/Transmitter
12.2 Register Description
Figure 12-1 UART Buffering Diagram
You can write a new character to the write buffer
While the shift register is sending out a character.
Write buffer
Shift register
TXD
TX FSM
APB
interface
Baud rate
generator
RX FSM
Shift register
Read buffer
RXD
The shift register can receive the next
character while the data in the receive
buffer is waiting for the processor to
read it.
The UART supports the High Speed Test Mode (HSTM). When the
register CTRL[6] is set to 1, the serial data is transmitted one bit per cycle,
and the text information can be transmitted in a short time.
The baud rate divider register should be set when using UART. For
example, if the APB1 bus frequency is running at 12MHz and the baud rate
is required to be 9600, the baud rate divider register can be set to
12000000/9600=1250.
12.2 Register Description
The UART register description is as shown in Table 12-1.
Table 12-1 UART Register Description
Name
Address Offset
Type
Width
Initial Value
Description
DATA
0x000
RW
8
0x--
[7:0] Data Value
[3] RX buffer overrun, write
1 to clear
STATE
0x004
RW
4
0x0
[2] TX buffer overrun, write
1 to clear
[1] RX buffer full, read-only
IPUG516-1.5E
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12 FPGA Logic Extended Universal Asynchronous Receiver/Transmitter
Name
Address Offset
Type
Width
12.3 Initialization Definition
Initial Value
Description
[0] TX buffer full, read-only
[6] High speed test mode
for TX only
[5] RX overrun interrupt
enable
[4] TX overrun interrupt
CTRL
0x008
RW
7
0x00
enable
[3] RX interrupt enable
[2] TX interrupt enable
[1] RX enable
[0] TX enable
[3] RX overrun interrupt,
write 1 to clear
INTSTATU
S/
INTCLEA
[2] TX overrun interrupt,
0x00C
RW
4
write 1 to clear
0x0
[1] RX interrupt, write 1 to
R
clear
[0] TX interrupt, write 1 to
clear
BAUDDIV
0x010
RW
20
0x00000
[19:0] Baud rate divider, the
minimum number is 16
12.3 Initialization Definition
The UART initialization definition is shown in Table 12-3.
Table 12-2 UART Initialization Definition
Name
Type
Value
Description
UART_BaudRate
uint32_t
Max 921.6Kbit/s
Baud rate
UART_Mode
UARTMode_TypeDef
ENABLE/DISABLE
Enable/Disable TX/RX mode
UART_Int
UARTInt_TypeDef
ENABLE/DISABLE
Enable/Disable TX/RX interrupt
UART_Ovr
UARTOvr_TypeDef
ENABLE/DISABLE
UART_Hstm
FunctionalState
ENABLE/DISABLE
IPUG516-1.5E
Enable/Disable
TX/RX
overrun
interrupt
Enable/Disable TX high speed test
mode
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12 FPGA Logic Extended Universal Asynchronous Receiver/Transmitter
12.4 Usage of Drivers
12.4 Usage of Drivers
The usage of UART drivers is shown in Table 12-3.
Table 12-3 Usage of UART Drivers
Name
Description
UART_Init
Initializes UARTx
UART_GetRxBufferFull
Returns UARTx RX buffer full status
UART_GetTxBufferFull
Returns UARTx TX buffer full status
UART_GetRxBufferOverrunStatus
Returns UARTx RX buffer overrun status
UART_GetTxBufferOverrunStatus
Returns UARTx TX buffer overrun status
UART_ClearRxBufferOverrunStatus
Clears Rx buffer overrun status
UART_ClearTxBufferOverrunStatus
Clears Tx buffer overrun status
UART_SendChar
Sends a character to UARTx TX buffer
UART_SendString
Sends a string to UARTx TX buffer
UART_ReceiveChar
Receives a character from UARTx RX buffer
UART_GetBaudDivider
Returns UARTx baud rate divider value
UART_GetTxIRQStatus
Returns UARTx TX interrupt status
UART_GetRxIRQStatus
Returns UARTx RX interrupt status
UART_ClearTxIRQ
Clears UARTx TX interrupt status
UART_ClearRxIRQ
Clears UARTx RX interrupt status
UART_GetTxOverrunIRQStatus
Returns UARTx TX overrun interrupt status
UART_GetRxOverrunIRQStatus
Returns UARTx RX overrun interrupt status
UART_ClearTxOverrunIRQ
Clears UARTx TX overrun interrupt request
UART_ClearRxOverrunIRQ
Clears UARTx RX overrun interrupt request
UART_SetHSTM
Sets UARTx TX high speed test mode
UART_ClrHSTM
Clears UARTx TX high speed test mode
12.5 Reference Design
Gowin_EMPU(GW1NS-2C) supports FPGA logic extended UART
software programming reference design in ARM Keil MDK V5.26 and
above and GOWIN MCU Designer V1.1 and above. Click the link to get the
following reference designs: https://www.gowinsemi.com/en/document/.zip
IPUG516-1.5E

Gowin_EMPU\ref_design\MCU_RefDesign \Keil_RefDesign\uartes

Gowin_EMPU\ref_design\MCU_RefDesign\GMD_RefDesign\uartes
38(47)
13 SysTick
13.1 Features
13
SysTick
13.1 Features
There is a 24-bit system timer SysTick with the function of automatic
overload and overrun interrupt in Gowin_EMPU(GW1NS-2C), which can
get certain time interval through this timer.
13.2 Register Description
The SysTick register description is shown in Table 13-1.
Table 13-1 SysTick Register Description
Name
Address Offset
Type
Width
Initial Value
Description
[16] Count down to zero flag
CTRL
0x00
RW
17
0x00000
[2] External clock source
[1] Enable interrupt request
[0] Enable Systick
LOAD
0x04
RW
24
0x000000
[23:0] Reload value
VAL
0x08
RW
24
0x000000
[23:0] Return current count down value
[31] Whether a separate reference clock
is provided
CALIB
0x0C
RW
32
0x00000000
[30] Whether the TENMS value is exact
[23:0] 10ms calibration value
IPUG516-1.5E
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13 SysTick
13.3 Usage of Drivers
13.3 Usage of Drivers
The usage of SysTick drivers is shown in Table 13-2.
Table 13-2 Usage of SysTick Drivers
Name
Description
SysTick_Config
Initializes and starts the SysTick counter and interrupt
13.4 Reference Design
Gowin_EMPU(GW1NS-2C) supports SysTick software programming
reference design in ARM Keil MDK V5.26 and above and GOWIN MCU
Designer V1.1 and above. Click the link to get the following reference
designs: https://www.gowinsemi.com/en/document/.zip
IPUG516-1.5E

Gowin_EMPU\ref_design\MCU_RefDesign\Keil_RefDesign\systick

Gowin_EMPU\ref_design\MCU_RefDesign\GMD_RefDesign\systick
40(47)
14 Memory Management
14.1 Features
14
Memory Management
14.1 Features
Gowin_EMPU (GW1NS-2C) supports dynamic memory management
and defines malloc and free functions by re-direction to realize dynamic
memory application and release.
14.2 Usage of Drivers
The usage of memory management drivers is shown in Table 14-1.
Table 14-1 Usage of Memory Management Drivers
Name
Description
mem_init
Initializes memory management
mymemset
Sets the values of memory space
mymemcpy
Copies from source to destination
mymemcmp
Compares source with destination
mymalloc
Allocates a memory space dynamically
myfree
Frees a memory space
14.3 Reference Design
Gowin_EMPU(GW1NS-2C) supports memory management software
programming reference design in ARM Keil MDK V5.26 and above and
GOWIN MCU Designer V1.1 and above. Click the link to get the following
reference designs: https://www.gowinsemi.com/en/document/.zip
IPUG516-1.5E

Gowin_EMPU\ref_design\MCU_RefDesign\Keil_RefDesign\mm

Gowin_EMPU\ref_design\MCU_RefDesign\GMD_RefDesign\mm
41(47)
15 AHB PSRAM
15.1 Features
15
AHB PSRAM
15.1 Features
There is one AHB PSRAM module accessed by AHB in
Gowin_EMPU(GW1NS-2C):












AHB interface
Compatible with interfaces of standard PSRAM devices;
Supports memory data path width of 8;
Supports memory chip of x8 data width;
Programmable burst length 16;
The clock rate is 1:2;
The initial latency is 6;
Supports the fixed latency mode;
Supports power-off option;
Drive strength is 50;
Self refresh area is full;
Refresh rate is normal.
15.2 Register Description
The AHB PSRAM register description is as shown in Table 15-1.
Table 15-1 AHB PSRAM Register Description
Name
Address Offset
Type
Width
Initial Value
Description
CMD
0x00
RW
1
0x0
Command register
[0] Operation type
0 = Read operation
1 = Write operation
ADDRESS
0x04
RW
21
0x0
Address register
[20:0] Address of reading and
IPUG516-1.5E
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15 AHB PSRAM
Name
15.2 Register Description
Address Offset
Type
Width
Initial Value
Description
writing data
WR_DATA0
0x08
RW
32
0x0
Write data register 0
[31:0] Write first 32bit data
WR_DATA1
0x0C
RW
32
0x0
Write data register 1
[31:0] Write second 32bit data
WR_DATA2
0x10
RW
32
0x0
Write data register 2
[31:0] Write third 32bit data
WR_DATA3
0x14
RW
32
Write data register 3
[31:0] Write fourth 32bit data
CMD_EN
0x18
WO
1
Command enable register
[0] Enable PSRAM
READ_DONE
0x1C
RW
1
Read status register
[0] Read done flag, auto set 1 if it
is done, and need MCU to clear
RD_DATA0
0x20
RO
32
Read data register 0
[31:0] Read first 32bit data
RD_DATA1
0x24
RO
32
Read data register 1
[31:0] Read second 32bit data
RD_DATA2
0x28
RO
32
Read data register 2
[31:0] Read third 32bit data
RD_DATA3
0x2C
RO
32
Read data register 3
[31:0] Read fourth 32bit data
INTI_DONE
0x30
RO
1
Initialization done register
[0] PSRAM hardware initialization
done flag
0 = Initialization failed
1 = Initialization done
IPUG516-1.5E
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15 AHB PSRAM
15.3 Usage of Drivers
15.3 Usage of Drivers
The usage of AHB PSRAM drivers is shown in Table 15-2 .
Table 15-2 Usage of AHB PSRAM Drivers
Name
Description
PSRAM_Check_Init_Status
Checks the status of PSRAM initialization
PSRAM_Mode_Set
Sets the mode for PSRAM write and read
PSRAM_Address_Set
Sets the address of PSRAM and save data into
this address
PSRAM_Read_Data_Buff
Reads data from the buffer of PSRAM
PSRAM_Cmd_Enable
Enable the command of PSRAM
PSRAM_Read_Done_Flag
Gets the flag of read PSRAM done
PSRAM_Clear_Read_Done_Flag
Clears the flag of read PSRAM done
PSRAM_Write_Data_Buff
Writes data into the buffer of PSRAM
PSRAM_Cmd_Unable
Disable the command of PSRAM
PSRAM_Write_Data_Package
Writes a package data into PSRAM
PSRAM_Read_Data_Package
Reads a package data from PSRAM
15.4 Reference Design
Gowin_EMPU(GW1NS-2C) supports AHB PSRAM reference design
in ARM Keil MDK V5.26 and above and GOWIN MCU Designer V1.1 and
above. Click the link to get the following reference designs:
https://www.gowinsemi.com/en/document/.zip


IPUG516-1.5E
Gowin_EMPU\ref_design\MCU_RefDesign\Keil_RefDesign\psram
Gowin_EMPU\ref_design\MCU_RefDesign\GMD_RefDesign\psram
44(47)
16 Embedded Real-time Operating System
16
16.1 uC/OS-III
Embedded Real-time Operating
System
Gowin_EMPU(GW1NS-2C) supports the embedded operating
system of uC/OS-III and FreeRTOS.
16.1 uC/OS-III
16.1.1 Features

The uC/OS-III is an extensible, romable, and preemptive real-time core.
There is no limit to the number of managed tasks.

uC/OS-III is the third generation core. It provides a real-time core
functions, including resource management, synchronization, and
inter-task communication, etc.

UC/os-iii provides many features that other real-time cores do not have.
For example, it can measure operating performance during runtime
and send signals or messages to tasks directly. Tasks can also wait for
multiple semaphores and message queues simultaneously.

Gowin_EMPU( GW1NS-2C) has supported uC/ III- III reference design;

uC/OS-III source code is available at Micrium website:
http://www.micrium.com
16.1.2 Operating System Version
Gowin_EMPU(GW1NS-2C) reference design is in the use of uC/OS-III
V3.03.00.
16.1.3 Operating System Configuration

IPUG516-1.5E
Users can modify UCOSIII_CONFIG\os_cfg.h and os_cfg_app.h to
configure uC/OS-III;
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16 Embedded Real-time Operating System

Users can modify UCOS_BSP\bsp.c
development board used;
16.2 FreeRTOS
and bsp.h to support the
16.1.4 Reference Design
Gowin_EMPU(GW1NS-2C) supports uC/OS-III software programming
reference design in ARM Keil MDK V5.26 and above and GOWIN MCU
Designer V1.1 and above. Click the link to get the following reference
designs: https://www.gowinsemi.com/en/document/.zip

Gowin_EMPU\ref_design\MCU_RefDesign\Keil_RefDesign\ucos_iii

Gowin_EMPU\ref_design\MCU_RefDesign\GMD_RefDesign\ucos_iii
16.2 FreeRTOS
16.2.1 Features

FreeRTOS is a lightweight real-time operating system.

FreeRTOS is a lightweight operating system. It offers functions of task
management, time management, semaphore, message queue,
memory management, recording, software timer, coroutines, etc. It can
basically meet the needs of small systems.；

FreeRTOS is a free operating system. It has features of open source,
portability, reducibility, and flexible scheduling policy.；

Gowin_EMPU(GW1NS-2C) has supported FreeRTOS reference
designs；

FreeRTOS source code is available at FreeRTOS website:
http://www.FreeRTOS.org.
16.2.2 Operating System Version
Gowin_EMPU(GW1NS-2C) reference design is in the use of
FreeRTOS V10.2.1.
16.2.3 Operating System Configuration
Users can modify include\FreeRTOSConfig.h to configure FreeRTOS.
16.2.4 Reference Design
Gowin_EMPU(GW1NS-2C) supports FreeRTOS software
programming reference design in ARM Keil MDK V5.26 and above and
GOWIN MCU Designer V1.1 and above. Click the link to get the following
reference designs: https://www.gowinsemi.com/en/document/.zip
IPUG516-1.5E
46(47)
16 Embedded Real-time Operating System
IPUG516-1.5E
16.2 FreeRTOS

Gowin_EMPU\ref_design\MCU_RefDesign\Keil_RefDesign\free_rtos

Gowin_EMPU\ref_design\MCU_RefDesign\GMD_RefDesign\free_rtos
47(47)