STMicroelectronics STLUX385A Datasheet

Section 12: Electrical characteristics on page 82

General purpose I/O 13

Alternate function 2

Alternate function 3

I 2 C data

C clock

UART data transmit

UART data receive

32/126 DocID027870 Rev 1

STLUX Pinout and pin description

Table 4. Pin description (continued)

TSSOP

Pin number

VFQFPN

TSSOP

Type

Pin name Main function

Alternate function 1

Alternate function 2

Alternate function 3

I/O

GPIO0[2]/I2C_sda/

HseOscout/Uart_TX

GPIO0[3]/I2C_scl/

HseOscin/Uart_RX

General purpose

I/O 02

General purpose

I/O 03

C data

C clock

I/O

20 PS

21 I

GPIO0[0]/Uart_TX/

I2C_sda

GPIO0[1]/Uart_RX/

I2C_scl

CPP[3]

CPP[2]

CPM3

CPP[1]

CPP[0]

VDDA

VSSA

ADCIN[7]

ADCIN[6]

ADCIN[5]

ADCIN[4]

ADCIN[3]

ADCIN[2]

ADCIN[1]

ADCIN[0]

General purpose

I/O 00

General purpose

I/O 01

Positive analog comparator input 3

Positive analog comparator input 2

Negative analog comparator input 3

Positive analog comparator input 1

Positive analog comparator input 0

Analog power supply

Analog ground

Analog input 7

Analog input 6

Analog input 5

Analog input 4

Analog input 3

Analog input 2

Analog input 1

Analog input 0

UART data transmit

UART data receive

1. The DIGIN3 and DGIN2 are connected together on the STLUX325A, DIGIN [3_2] pin.

2. Available only on the STUX325A.

3. Not available on the STUX285A.

Output crystal oscillator signal

Input crystal oscillator signal /input clock signal

UART data transmit

UART data receive

C data -

C clock

DocID027870 Rev 1 33/126

126

Pinout and pin description STLUX

The STLUX family includes three different I/O types:

 Normal I/Os configurable either at 2 or 10 MHz maximum frequency

 Fast I/O operating up to 12 MHz.

 High speed I/O operating up to 32 MHz

The STLUX I/Os are designed to withstand current injection. For a negative injection current of 4 mA, the resulting leakage current in the adjacent input does not exceed 1 µA; further details are available in

34/126 DocID027870 Rev 1

STLUX

7

I/O multifunction signal configuration

I/O multifunction signal configuration

Several I/Os have multiple functionalities selectable through the configuration mechanism

described from Section 7.1

Section 7.5 on page 41

. The STLUX I/Os are grouped into four different configurable ports: P0, P1, P2 and P3.

7.2

The STLUX supports either a cold or warm multifunction signal configuration policy according to the content of the EN_COLD_CFG bit field, a part of the GENCFG option byte register.

When the EN_COLD_CFG bit is set, the cold configuration is selected and the multifunction signals are configured according to the values stored in the option bytes; otherwise when the EN_COLD_CFG bit is cleared (default case), the warm configuration mode is chosen and the multifunction pin functionality is configured through the miscellaneous registers.

The configuration options and the proper configuration registers are detailed in

Table 5

Table 5. Multifunction configuration registers

EN_COLD_CFG Configuration policy Multifunction configuration registers

0 (default)

Cold

Warm

AFR_IOMXP0, AFR_IOMXP1 and AFR_IOMXP2

MSC_IOMXP0, MSC_IOMXP1 and MSC_IOMXP2

The warm configuration is volatile, thus not maintained after a device reset.

Port P0 I/O multifunction configuration signal

The Port P0 multiplexes several input/output functionalities, increasing the device flexibility.

The P0 port pins can be independently assigned to general purpose I/Os or to internal peripherals. All communication peripherals and the external oscillator are hosted by the Port

P0 pins.

In order to avoid electrical conflicts on the user application board, the P0 signals are configured at reset as GPIO0 inputs without pull-up resistors. Once the reset is released, the firmware application must initialize the inputs with the proper configuration according to the application needs.

The multifunction pins can be configured via one of the following two registers, depending on the overall configuration policy (warm/cold):

 Cold configuration: AFR_IOMXP0 option byte registers (refer to

Section 10: Option bytes on page 60 ). After the reset the P0 signals are configured in line with

AFR_IOMXP0 contents.

 Warm configuration: MSC_IOMXP0 miscellaneous register (refer to

Section 7.5 on page 41 ). After the reset, the P0 signals are configured as GPIO input lines with the

pull-up disabled.

DocID027870 Rev 1 35/126

126

I/O multifunction signal configuration STLUX

Table 6

summarizes the Port P0 configuration scheme. Both registers MSC_IOMXP0 and

AFR_IOMXP0 use the same register fields Sel_p054, Sel_p032 and Sel_p010 which respectively control the bits [5, 4], [3, 2] and [1, 0] of the Port P0.

Table 6. P0 internal multiplexing signals (1)

Port P0 multifunction configuration signal

MUX selection

Port pins Multifunction signal

Selection fields Value (binary)

P0[1,0]

(2)

P0[3,2]

P0[5,4]

GPIO0 [1]

UART_rx

C_scl

GPIO0 [0]

UART_tx

C_sda

RFU reserved encoding

GPIO0 [3]

C_scl

HseOscin

UART_rx

GPIO0[5]

DALI_rx

C_scl

UART_rx

GPIO0 [2]

C_sda

HseOscout

UART_tx

GPIO0[4]

DALI_tx

C_sda

UART_tx

Sel_P010

Sel_P032

Sel_P054

1. The Sel_p054, Sel_p032, Sel_p010 are register fields for both registers MSC_IOMXP0 and

AFR_IOMXP0.

The peripheral conflict (same resources selected on different pins at the same time) has to be prevented by SW configuration.

When the I 2 C interface is selected either on the GPIO0 [5:4] GPIO0 [3:2] or on GPIO0 [1:0] signals the related I/O port speed has to be configured at 10 MHz by programming the GPIO0 internal peripheral.

2. Available only on the STLUX385A and STLUX383A.

The primary I/Os can be used to trace the SMED's state evolution. This feature allows the debug of the complex SMED configurations. The trace selection can be enabled or disabled via the register MSC_IOMXSMD. The diagnostic signal selection through the

MSC_IOMXSMD register overrides the functional configuration of the MSC_IOMXP0 register.

The Port P0 [5:3] or P0 [2:0] can be configured to output one or two different SMEDs' current states.

The SMEDs FSM state signals (coded on three bits) may be multiplexed either on port bits

P0 [5:3] or P0 [2:0]; alternatively two different SMEDs signal states can be traced simultaneously on the same port bits. The SMED trace configuration is forbidden on the Port

P [2:0] when the external comparator reference voltage is programmed on the Port P0 [1, 0].

The Port 0 I/O signal availability depends on the STLUX device.

36/126 DocID027870 Rev 1

STLUX

7.2.3

I/O multifunction signal configuration

Port P0 I/O functional multiplexing signal

Figure 10

shows an outline view of the Port P0 multifunction multiplexing scheme.

Figure 10. Port P0 I/O functional multiplexing scheme

Note:

Where the “A/F(s) in” and “A/F(s) out” signals are defined in Section 6.2 on page 32 .

Verify pin availability in Table 4: Pin description on page 32

On the STLUX325A device:

 P0_ODR [1:0] bits must be keep clear.

 P0 [6] is a multifunction signal configurable through the MSC_IOMXP2 [7] and

AFR_IOMXP2 [7] register bits - for further details refer to Section 7.4

 Port P0 [6] signal is controlled by P0_ODR [6] and P0_IDR [6] GPIO0 registers.

On the STLUX285A device:

 P0_ODR [1:0] bits must be keep clear.

7.2.5

Port P0 signals may be configured to generate maskable (IRQ) and un-maskable (NMI) interrupts by programming the MSC_CFGP0<n> and the MSC_STSP0 registers (n = index port signal). This functionality is not applicable to the bit port P0 [6] on the STLUX325A and on the port P0:[1:0] on STLUX285A.

The interrupt request may be configured to wake-up the IC device from the WFI (wait for interrupt), AHalt (active Halt) and Halt power saving state.

P0 programmable pull-up and speed feature

The I/O speed and pad pull-up resistance (47 k ) of the port P0 may be configured through the GPIO0 internal registers.

The pull-up resistance of the multifunction signal P0 [6] is always enabled on the

STLUX325A.

DocID027870 Rev 1 37/126

126

I/O multifunction signal configuration

7.3 Port P1 I/O multifunction configuration signal

STLUX

The Port P1 I/O multifunction pins, similarly to the Port P0, can be individually configured through the following set of registers based on the selected device configuration policy:

 Cold configuration: AFR_IOMXP1 option byte register (refer to

Section 10 on page 60 ).

After reset the P1 signals are configured in line with AFR_IOMXP1 contents.

 Warm configuration: MSC_IOMXP1 miscellaneous register (refer to

Section 7.5

). After

reset the P1 signals are configured as PWM output lines.

Every Port1 I/O can be configured to operate as a PWM output pin or a GPIO. Differently from the port P0s, the pins are configured as PWM output signals by default after reset.

Table 7

summarizes the Port P1 configurations as selected by the register fields Sel_p15 …

Sel_p10 which respectively control the bits [5] … [0] of the Port P1 (verify resources availability in

Table 4 on page 32 ).

Table 7. Port P1 I/O multiplexing signal

(1)

Port P1 multifunction configuration signal

MUX selection

Output signal Multifunction signal

Selection bits Value (binary)

P1[0]

P1[1]

P1[2]

P1[3]

P1[4]

P1[5]

PWM[0]

GPIO1[0]

PWM[1]

GPIO1[1]

PWM[2]

GPIO1[2]

PWM[3]

GPIO1[3]

PWM[4]

GPIO1[4]

PWM[5]

GPIO1[5]

Sel_P10

Sel_P11

Sel_P12

Sel_P13

Sel_P14

Sel_P15

1. The Sel_p15…Sel_p10 are common register fields of both registers MSC_IOMXP1 and AFR_IOMXP1.

In cold configuration the P1x are configured as defined by the AFR_IOMXP1 option byte.

The PWM default polarity level is configured by the register option byte GENCFG.

Verify pin availability in

Table 4 on page 32

38/126 DocID027870 Rev 1

STLUX

7.3.1

I/O multifunction signal configuration

Port P1 I/O multiplexing signal

Figure 11

shows an outline view of the port P1 signal multiplexing scheme.

Figure 11. Port P1 I/O multiplexing scheme

Note:

7.3.2

7.4

The P1 [5:0] output signals may be read back from the P1_IDR register only when the pins are configured as GPIO out or PWM signals.

The PWM internal signal is read back also by its own SMED through the

SMD<n>_FSM_STS register.

Verify pin availability in device pin

Table 4 on page 32

P1 programmable pull-up feature

The pad pull-up resistances (47 k ) of the Port1 may be configured through the GPIO1 internal register.

Port P2 I/O multifunction configuration signal

The Port2 I/O multifunction pins, similarly to the Port0 and Port2, can be individually configured through the following set of registers based on the selected device configuration policy:

 Cold configuration: AFR_IOMXP2 option byte registers (refer to

Section 10: Option bytes on page 60 . After reset the P2 signals are configured in line with AFR_IOMXP2

contents.

 Warm configuration: MSC_IOMXP2 miscellaneous register (refer to

Section 7.5

). After

reset the P2 signals are configured as DIGIN input lines with the pull-up enabled.

Table 8

summarizes the port P2 configurations selected by the register fields

Sel_p25…Sel_p20 which respectively control the bits [5]… [0] of port P2. The P2 [0] is configured by the CCOEN bit field of the register CKC_CCOR. The SWIM alternate function signal (when available) is controlled by the Sel_SWIM bit field provided by registers

AFR_IOMXP2 [7] and MSC_IOMXP2 [7].

DocID027870 Rev 1 39/126

126

I/O multifunction signal configuration

Output signal

P2[0]

P2[4]

P2[5]

SWIM

STLUX

Table 8. Port P2 I/O multiplexing signal

Port P2 multifunction configuration signal

Multifunction signal

DIGIN[0]

CCO

DIGIN[4]

I 2 C_sda

DIGIN[5]

C_scl

GPIO0[6]

SWIM

CCOEN

Sel_P254

Sel_SWIM

MUX selection

Selection bits Value (binary)

Note: The Sel_P254 is a common register field of both registers MSC_IOMXP2 and

AFR_IOMXP2.

The peripheral conflict (same resources selected on different pins at the same time) has to be prevented by SW configuration.

The signal ports P2 [3:1] are exclusively interconnected with DIGIN [3:1] primary pins. When the I 2 C i/f is selected on DIGIN [5:4] signals the I/O speed is auto-configured at 10 MHz and the internal pull-up functionality is controlled by the MSC_INPP2AUX1 register.

The GPIO0 [6] signal is selected when both Sel_SWIM = '0' and CFG_GCR [0] = '1'.

SWIM signal function is selected when the CFG_GCR [0] = '0'.

After reset by default the P2 [0] is configured as the DIGIN [0] signal.

Verify pinout availability in

Table 4: Pin description on page 32

The P2 [0] is configured by the CCOEN field of the CKC_CCOR register as shown in

Table 8

7.4.2

Port P2 signals may be configured to generate maskable (IRQ) and un-maskable (NMI) interrupts by configuring the MSC_CFGP2<n> and the MSC_STSP2 registers (n = index port signal 0-5).

The interrupt request may be configured to wake-up the IC device from the WFI (wait for interrupt), AHalt (active Halt) and Halt power saving state.

P2 programmable pull-up feature

The pad pull-up resistances (47 k ) of Port2 signals are individually controllable by the

MSC_INPP2AUX1 register.

40/126 DocID027870 Rev 1

STLUX I/O multifunction signal configuration

7.5 Multifunction configuration registers

MSC_IOMXP0 (Port P1 I/O MUX control register)

Table 9. MSC_IOMXP0 (Port P1 I/O MUX control register)

Offset: 0x2A

7 6 5

Default value: 0x00

Sel_P054 [1:0] r/w

RFU r

1. Not available on the STLUX325A and STLUX285A.

3 2

Sel_P032 [1:0] r/w

1 0

Sel_P010 [1:0]

(1) r/w

The Port0 I/O multifunction signal configurations register (for functionality description refer to

Section 7.2 on page 35

Verify pinout availability in

Table 4: Pin description on page 32 .

Bit 1 - 0:

Sel_P010 [1:0] Port0 [1:0] I/O multiplexing scheme:

00: Port0 [1:0] are interconnected to GPIO0 [1:0] signals

01: Port0 [1:0] are interconnected to UART_rx and UART_tx signals

10: Port0 [1:0] are interconnected to I

C_scl and I

C_sda signals

11: RFU

Bit 3 - 2:

Sel_P032 [1:0] Port0 [3:2] I/O multiplexing scheme:

00: Port0 [3:2] are interconnected to GPIO0 [3:2] signals

01: Port0 [3:2] are interconnected to I

C_scl and I

C_sda signals

10: Port0 [3:2] are interconnected to HseOscin and HseOscout analog signals

11: Port0 [3:2] are interconnected to UART_rx and UART_tx signals

Bit 5 - 4:

Sel_P054 [1:0] Port0 [5:4] I/O multiplexing scheme:

00: Port0 [5:4] are interconnected to GPIO0 [5:4] signals

01: Port0 [5:4] are interconnected to DALI_rx and DALI_tx signals

10: Port0 [5:4] are interconnected to I

C_scl and I

C_sda signals

11: Port0 [5:4] are interconnected to UART_rx and UART_tx signals

Bit 7 - 6:

RFU reserved; in order to guarantee future compatibility, the bits are kept or set to 0 during register write operations.

DocID027870 Rev 1 41/126

126

I/O multifunction signal configuration STLUX

MSC_IOMXP1 (Port P1 I/O MUX control register)

Table 10. MSC_IOMXP1 (Port P1 I/O MUX control register)

Offset: 0x2B

Default value: 0x3F

RFU r

6 5

Sel_P15

(1)

(2)

Sel_P14

Section 7.3 on page 38 ).

3 2 1 0

Sel_P13 Sel_P12 Sel_P11 Sel_P10 r/w

1. Not available on the STLUX285A; these bits are set to 1 after reset, must be cleared by SW during the IC device initialization phase and during register write operations.

2. Not available on the STLUX325A; these bits are set to 1 after reset, must be cleared by SW during the IC device initialization phase and during register write operations.

The Port1 I/O multifunction signal configuration register (for functionality description refer to

Verify pinout availability in

Table 4: Pin description on page 32 .

Bit 0:

Sel_P10 Port1 [0] I/O multiplexing scheme:

0: Port1 [0] is interconnected to GPIO1 [0] signal

1: Port1 [0] is interconnected to PWM [0] signal

Bit 1:

Sel_P11 Port1 [1] I/O multiplexing scheme:

0: Port1 [1] is interconnected to GPIO1 [1] signal

1: Port1 [1] is interconnected to PWM [1] signal

Bit 2:

Sel_P12 Port1 [2] I/O multiplexing scheme:

0: Port1 [2] is interconnected to GPIO1 [2] signal

1: Port1 [2] is interconnected to PWM [2] signal

Bit 3:

Sel_P13 Port1 [3] I/O multiplexing scheme:

0: Port1 [3] is interconnected to GPIO1 [3] signal

1: Port1 [3] is interconnected to PWM [3] signal

Bit 4:

Sel_P14 Port1 [4] I/O multiplexing scheme:

0: Port1 [4] is interconnected to GPIO1 [4] signal

1: Port1 [4] is interconnected to PWM [4] signal

Bit 5:

Sel_P15 Port1 [5] I/O multiplexing scheme:

0: Port1 [5] is interconnected to GPIO1 [5] signal

1: Port1 [5] is interconnected to PWM [5] signal

42/126 DocID027870 Rev 1

STLUX I/O multifunction signal configuration

Bit 7 - 6:

RFU reserved; in order to guarantee future compatibility, the bits are kept or set to 0 during register write operations.

MSC_IOMXP2 (Port P2 I/O MUX control register)

Sel_SWIM r/w

Table 11. MSC_IOMXP2 (Port P2 I/O MUX control register)

Offset: 0x13 (indirect area)

RFU r

Default value: 0xFF

Sel_P254 r/w

3 2

RFU r

1 0

The Port1 I/O multifunction signal configurations register (for functionality description refer to

Section 7.5

). This register is not available on STLUX285A and must be kept set to its default value

Check device feature availability.

Bit 3 - 0:

RFU reserved; must be kept 0 during register writing for future compatibility

Bit 4:

Sel_P254 Port2 [5:4] I/O multiplexing scheme:

0: Port2 [5:4] are interconnected to I 2 C_scl and I 2 C_sda signals

1: Port2 [5:4] are interconnected to DIGIN [5:4] signals

Bit 6 - 5:

RFU reserved; in order to guarantee future compatibility, the bits are kept or set to 0 during register write operations.

Bit 7:

Sel_SWIM SWIM alternate function signal enable; this feature is active when the SWD field of the register CFG_GCR is set.

0: SWIM pin is configured with GPIO0 [6] signal.

1: SWIM functionality is preserved.

DocID027870 Rev 1 43/126

126

I/O multifunction signal configuration

MSC_INPP2AUX1 (INPP aux register)

RFU r

Table 12. MSC_INPP2AUX1 (INPP aux register)

Offset: 0x08 (indirect area)

Default value: 0x00

4 3 2

INPP2_PULCTR [5:0] r/w

Note:

STLUX

Bit 5 - 0:

INPP2_PULCTR [5:0].This register configures respectively the INPP2 [5:0] pull-up functionality as follows:

0: enable pad pull-up features (enabled by default for compatibility with the

STLUX385)

1: disable pad pull-up

Bit 7 - 6:

RFU reserved; in order to guarantee future compatibility, the bits are kept or set to 0 during register write operations.

The MSC_IOMXP2 and MSC_INPP2AUX1 are addressable in indirect mode.

On STLUX285A devices, due to DIGINs double bond interconnections the pull-up functionality must be configured in the same way for the two couple pins:

 DIGIN10 is controlled by register field NPP2_PULCTR[1:0].

 DIGIN32 is controlled by register field INPP2_PULCTR[3:2].

 DIGIN54 is controlled by register field INPP2_PULCTR[5:4].

44/126 DocID027870 Rev 1

STLUX

8

8.1

Memory and register map

Memory and register map

Memory map overview

This section describes the register map implemented in the STLUX devices family.

Table 13

shows the main memory map organization. All registers and memory spaces are configured within the first 64 Kbytes of memory, the remaining address spaces are kept reserved for the future use.

Address

00.0000h

00.07FFh

00.0800h

00.3FFFh

00.4000h

00.43FFh

00.4400h

00.47FFh

00.4800h

00.487Fh

00.4880h

00.4FFFh

00.5000h

00.57FFh

00.5800h

00.5FFFh

00.6000h

00.67FFh

00.6800h

00.7EFFh

00.7F00h

00.7FFFh

00.8000h

00.8080h

00.FFFFh

01.0000h

FF.FFFFh

Table 13. Internal memory map

Description

2-kB RAM

Stack

Reserved

1 kB data E

PROM

Reserved

128 option bytes

Reserved

Peripheral register region

Reserved

2-kB boot ROM

Reserved

Core register region

32 interrupt vectors

32-kB program Flash

Reserved

By default the stack address is initialized at 0x07FF and rolls over when it reaches the address value of 0x0400.

DocID027870 Rev 1 45/126

126

Memory and register map STLUX

8.2.1

8.2.2

Section 8.2.1

shows the STLUX memory map.

General purpose I/O GPIO0 register map

Address

0x00.5000

0x00.5001

0x00.5002

0x00.5003

0x00.5004

Table 14. General purpose I/O GPIO0 register map

Block Register name Register description

GPIO0

P0_ODR

P0_IDR

P0_DDR

P0_CR1

P0_CR2

Output data

Input data

Data direction

Control register 1

Control register 2

General purpose I/O GPIO1 register map

Address

0x00.5005

0x00.5006

0x00.5007

0x00.5008

0x00.5009

Table 15. General purpose I/O GPIO1 register map

Block Register name Register description

GPIO1

P1_ODR

P1_IDR

P1_DDR

P1_CR1

P1_CR2

Output data

Input data

Data direction

Control register 1

Control register 2

46/126 DocID027870 Rev 1

STLUX Memory and register map

Direct register address mode

Address

0x00.501D

0x00.501E

0x00.501F

0x00.5020

0x00.5021

0x00.5022

0x00.5023

0x00.5024

0x00.5025

0x00.5026

0x00.5027

0x00.5028

0x00.5010

0x00.5011

0x00.5012

0x00.5013

0x00.5014

0x00.5015

0x00.5016

0x00.5017

0x00.5018

0x00.5019

0x00.501A

0x00.501B

0x00.501C

0x00.5029

0x00.502A

0x00.502B

0x00.502C

0x00.502D

0x00.502E

0x00.502F

Table 16. Miscellaneous direct register address mode

Block Register name

MSC_CFGP00

MSC_CFGP01

MSC_CFGP02

Register description

P00 input line control

(1)

P01 input line control

Table 36 shows the STLUX internal controller's interrupt vector.

P02 input line control

MSC

MSC_CFGP03

MSC_CFGP04

MSC_CFGP05

MSC_CFGP20

MSC_CFGP21

MSC_CFGP22

MSC_CFGP23

MSC_CFGP24

MSC_CFGP25

MSC_STSP0

MSC_STSP2

MSC_INPP2

RFU

MSC_DACCTR

MSC_DACIN0

MSC_DACIN1

MSC_DACIN2

MSC_DACIN3

MSC_SMDCFG01

MSC_SMDCFG23

MSC_SMDCFG45

MSC_SMSWEV

MSC_SMUNLOCK

MSC_CBOXS0

MSC_CBOXS1

MSC_CBOXS2

MSC_CBOXS3

MSC_CBOXS4

MSC_CBOXS5

P03 input line control

P04 input line control

P05 input line control

P20 input line control

P21 input line control

P22 input line control

P23 input line control

P24 input line control

P25 input line control

Port0 status

Port2 status

Port2 read

Reserved for future use

Comparators and DAC configuration

DAC0 input data

DAC1 input data

DAC2 input data

DAC3 input data

SMED 0 - 1 behavior

SMED 2 - 3 behavior

SMED 4 - 5 behavior

SMED software events

SMED unlock

Connection matrix selection for SMED 0

Connection matrix selection for SMED 1

Connection matrix selection for SMED 2

Connection matrix selection for SMED 3

Connection matrix selection for SMED 4

Connection matrix selection for SMED 5

DocID027870 Rev 1 47/126

126

Memory and register map STLUX

Table 16. Miscellaneous direct register address mode (continued)

Address Block Register name Register description

SMED Trace multiplexing on port 0 0x00.5030

0x00.5031

0x00.5035

0x00.5036

0x00.5037

0x00.5038

0x00.5039

0x00.503A

0x00.503B

0x00.503C

0x00.503D

MSC

MSC_IOMXSMD

RFU

MSC_CFGP15

MSC_STSP1

RFU

MSC_INPP3

MSC_IOMXP0

MSC_IOMXP1

MSC_IDXADD

MSC_IDXDAT

1. Address not available for the STLUX285A and STLUX325A.

Reserved for future use

Aux timer interrupt configuration

Aux timer interrupt status

Reserved for future use

Port 3 (COMP) read

Port 0 alternate function MUX

Port 1 alternate function MUX

MSC indirect register

MSC indirect data

Indirect register address mode

Address (IDX)

Table 17. Miscellaneous indirect register address mode

Block Register name Register description

0x00 - 0x04

0x05

0x06

0x07

0x08

0x09

0x0A - 0x12

0x13

MSC

(indirect)

1. Register not available for the STLUX285A.

RFU

MSC_DALICKSEL

MSC_DALICKDIV

MSC_DALICONF

MSC_INPP2AUX1

MSC_INPP2AUX2

RFU

MSC_IOMXP2

Reserved for future use

DALI clock selection

DALI filter clock division factor

DALI filter mode configuration

INPP2 auxiliary configuration register 1

INPP2 auxiliary configuration register 2

Reserved for future use

Port2 alternate function MUX register

(1)

48/126 DocID027870 Rev 1

STLUX

8.2.4

Memory and register map

Flash and E

PROM non-volatile memories

Address

0x00.505A

0x00.505B

0x00.505C

0x00.505D

0x00.505E

0x00.505F

0x00.5062

0x00.5063

0x00.5064

0x00.5071

Table 18. Non-volatile memory register map

Block Register name Register description

MIF

FLASH_CR1

FLASH_CR2

FLASH_nCR2

FLASH_FPR

FLASH_nFPR

FLASH_IAPSR

FLASH_PUKR

RFU

FLASH_DUKR

FLASH_WAIT

Control register 1

Control register 2

Control register 2 (protection)

Memory protection

Memory protection (complemented reg.)

Flash status

Write memory protection removal key reg.

Reserved for future use

Write memory protection removal data

Time access wait-state reg.

Address

0x00.50B3

Table 19. RST_SR register map

Block Register name

RSTC RST_SR

Register description

Reset control status

DocID027870 Rev 1 49/126

126

Memory and register map

8.2.6 Clock and clock controller

STLUX

Address

0x00.50C2

0x00.50C3

0x00.50C4

0x00.50C5

0x00.50C6

0x00.50C7

0x00.50C8

0x00.50C9

0x00.50CA

0x00.50CB

0x00.50CC

0x00.50CD

0x00.50CE

0x00.50CF

0x00.50B4

0x00.50B5

0x00.50B6

0x00.50B7

0x00.50B8

0x00.50B9

0x00.50BA

0x00.50BB

0x00.50BC

0x00.50BD

0x00.50BE

0x00.50BF

0x00.50C0

0x00.50C1

Table 20. Clock and clock controller register map

Block Register name Register description

CKC

CLK_PLLR

CLK_CMSR

CLK_SWR

CLK_SWCR

CLK_CKDIVR

CLK_PCKENR1

CLK_CSSR

CLK_CCOR

CLK_PCKENR2

RFU

CLK_HSITRIMR

CLK_SWIMCCR

CLK_CCODIVR

CLK_ADCR

CLK_SMD0

CLK_SMD1

CLK_SMD2

CLK_SMD3

CLK_SMD4

CLK_SMD5

RFU

CLK_PLLDIV

CLK_AWUDIV

CLK_ICKR

CLK_ECKR

SMED 0 clock configuration

SMED 1 clock configuration

SMED 2 clock configuration

SMED 3 clock configuration

SMED 4 clock configuration

SMED 5 clock configuration

Reserved for future use

PLL clock divisor

AWU clock divisor

Internal clock control

External clock control

PLL control

Clock master

Clock switch

Switch control

Clock dividers

Peripherals clock enable

Clock security system

Configurable clock output

Peripherals clock enable

Reserved for future use

HSI calibration trimmer

SWIM clock division

CCO divider

ADC clock configuration

50/126 DocID027870 Rev 1

STLUX Memory and register map

Address

0x00.50D1

0x00.50D2

Table 21. WWDG timer register map

Block Register name

WWDG

WWDG_CR

WWDG_WR

Register description

Watchdog control

Watchdog window

Address

0x00.50E0

0x00.50E1

0x00.50E2

Address

0x00.50F0

0x00.50F1

0x00.50F2

Table 22. IWDG timer register map

Block Register name

IWDG

IWDG_KR

IWDG_PR

IWDG_RLR

Register description

Watchdog key

Watchdog time base

Watchdog counter value after reload

Table 23. AWU timer register map

Block Register name

AWU_CSR

AWU

AWU_APR

AWU_TBR

Register description

AWU control status

AWU asynchronous prescaler buffer

AWU time base selection

DocID027870 Rev 1 51/126

126

Memory and register map

8.2.10 Inter-integrated circuit interface (I

C)

Address

0x00.5210

0x00.5211

0x00.5212

0x00.5213

0x00.5214

0x00.5215

0x00.5216

0x00.5217

0x00.5218

0x00.5219

0x00.521A

0x00.521B

0x00.521C

0x00.521D

Table 24. I 2 C register map

Block Register name

C_CR1

C_CR2

C_FREQR

C_OARL

C_OARH

RFU

C_DR

C_SR1

C_SR2

C_SR3

C_ITR

C_CCRL

C_CCRH

C_TRISER

STLUX

Register description

C control register 1

C control register 2

C frequency register

C own add-low register

C own add-high register

Reserved for future use

C data register

C status register 1

C status register 2

C status register 3

C interrupt

C clock control

C rising edge

Address

0x00.5230

0x00.5231

0x00.5232

0x00.5233

0x00.5234

0x00.5235

0x00.5236

0x00.5237

Table 25. UART register map

Block Register name

UART

UART_SR

UART_DR

UART_BRR1

UART_BRR2

UART_CR1

UART_CR2

UART_CR3

UART_CR4

Register description

UART status

UART data

UART baud rate div. mantissa

[7:0]

UART baud rate div. mantissa

[11:8] SCIDIV FRACT [3:0]

UART control register 1

UART control register 2

UART control register 3

UART control register 4

52/126 DocID027870 Rev 1

STLUX Memory and register map

Address

0x00.5340

0x00.5341

0x00.5342

0x00.5343

0x00.5344

0x00.5345

0x00.5346

0x00.5347

0x00.5348

Table 26. System timer register map

Block Register name

STMR

STMR_CR1

STMR_IER

STMR_SR1

STMR_EGR

STMR_CNTH

STMR_CNTL

STMR_PSCL

STMR_ARRH

STMR_ARRL

Register description

Control register 1

Interrupt enable

Status register 1

Event generation

Counter high

Counter low

Prescaler low

Autoreload high

Autoreload low

8.2.13 Auxiliary timer registers

Address

0x00.5009

0x00.5036

0x00.5037

0x00.50C6

0x00.50C9

Table 27. Auxiliary timer register map

Block Register name

GPIO1

MSC

CKC

P1_CR2

MSC_CFGP15

MSC_STSP1

CLK_CCODIVR

CLK_CCOR

Register description

Control register 2

P15 input line control

Port 1 status

CCO clock dividers

Configurable clock output

Address

0x00.53C0

0x00.53C1

0x00.53C2

0x00.53C3

0x00.53C4

0x00.53C5

0x00.53C6

0x00.53C7

0x00.53C8

0x00.53C9

Table 28. DALI register map

Block Register name

DALI

DALI_CLK_L

DALI_CLK_H

DALI_FB0

DALI_FB1

DALI_FB2

DALI_BD

DALI_CR

DALI_CSR

DALI_CSR1

DALI_REVLN

Register description

Data rate control

Forward message

Backward message

Control

Control and status register

Control and status register 1

Control reverse signal line

DocID027870 Rev 1 53/126

126

Memory and register map STLUX

Address Offset

0x00.503C

0x05

0x00.503C

0x06

0x00.503C

0x07

Table 29. DALI filter register map

Block Register name

MSC (indirect)

MCS_DALICKSEL

MSC_DALICKDIV

MSC_DALICONF

Register description

DALI clock selection

DALI filter clock division factor

DALI filter mode configuration

Address

0x00.540B

0x00.540C

0x00.540D

0x00.540E

0x00.540F

0x00.5410

0x00.5411

0x00.5412

0x00.5413

0x00.5414

0x00.5415

0x00.5400

0x00.5401

0x00.5402

0x00.5403

0x00.5404

0x00.5405

0x00.5406

0x00.5407

0x00.5408

0x00.5409

0x00.540A

Table 30. ADC register map and reset value

Block Register name Register description

ADC

ADC_CFG

ADC_SOC

ADC_IER

ADC_SEQ

ADC_DATL_0

ADC_DATH_0

ADC_DATL_1

ADC_DATH_1

ADC_DATL_2

ADC_DATH_2

ADC_DATL_3

ADC_DATH_3

ADC_DATL_4

ADC_DATH_4

ADC_DATL_5

ADC_DATH_5

ADC_DATL_6

ADC_DATH_6

ADC_DATL_7

ADC_DATH_7

ADC_SR

ADC_DLYCNT

Configuration

Start of conversion

Interrupt enable

Sequencer

Low part data 0 converted

High part data 0 converted

Low part data 1 converted

High part data 1 converted

Low part data 2 converted

High part data 2 converted

Low part data 3 converted

High part data 3 converted

Low part data 4 converted

High part data 4 converted

Low part data 5 converted

High part data 5 converted

Low part data 6 converted

High part data 6 converted

Low part data 7 converted

High part data 7 converted

Status

SOC delay counter

54/126 DocID027870 Rev 1

STLUX Memory and register map

Address (offset)

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x12

0x13

0x14

0x15

0x16

0x17

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

The SMED<n> address register is:

ADD_REG = (5500h + (40h) * n) + offset where <n> is the SMED instance number 0 - 5.

SMD<n>_CTR

SMD<n>_CTR_TMR

SMD<n>_CTR_INP

SMD<n>_CTR_DTR

SMD<n>_TMR_T0L

SMD<n>_TMR_T0H

SMD<n>_TMR_T1L

SMD<n>_TMR_T1H

SMD<n>_TMR_T2L

SMD<n>_TMR_T2H

SMD<n>_TMR_T3L

SMD<n>_TMR_T3H

SMD<n>_PRM_ID0

SMD<n>_PRM_ID1

SMD<n>_PRM_ID2

SMD<n>_PRM_S00

SMD<n>_PRM_S01

SMD<n>_PRM_S02

SMD<n>_PRM_S10

SMD<n>_PRM_S11

SMD<n>_PRM_S12

SMD<n>_PRM_S20

SMD<n>_PRM_S21

SMD<n>_PRM_S22

SMD<n>_PRM_S30

SMD<n>_PRM_S31

SMD<n>_PRM_S32

SMD<n>_CFG

SMD<n>_DMP_L

SMD<n>_DMP_H

Block

Table 31. SMED register map

Register name

SMED<n>

Register description

Control

Control time

Control input

Dithering

Time T0 LSB

Time T0 MSB

Time T1 LSB

Time T1 MSB

Time T2 LSB

Time T2 MSB

Time T3 LSB

Time T3 MSB

IDLE state parameter0

IDLE state parameter1

IDLE state parameter2

S0 state parameter0

S0 state parameter1

S0 state parameter2

S1 state parameter0

S1 state parameter1

S1 state parameter2

S2 state parameter0

S2 state parameter1

S2 state parameter2

S3 state parameter0

S3 state parameter1

S3 state parameter2

Timer configuration register

Counter dump LSB

Counter dump MSB

DocID027870 Rev 1 55/126

126

Memory and register map

Address (offset)

0x1E

0x1F

0x20

0x21

0x22

0x23

Table 31. SMED register map (continued)

Block Register name Register description

SMED<n>

SMD<n>_GSTS

SMD<n>_IRQ

SMD<n>_IER

SMD<n>_ISEL

SMD<n>_DMP

SMD<n>_FSM_STS

General status

Interrupt request register

Interrupt enable register

External events control

Dump enable

FSM core status

STLUX

Address

0x00.7F00

0x00.7F01

0x00.7F02

0x00.7F03

0x00.7F04

0x00.7F05

0x00.7F06

0x00.7F07

0x00.7F08

0x00.7F09

0x00.7F0A

Block

CPU

Table 32. CPU register map

Register name

SPH

SPL

PCE

PCH

PCL

Register description

Accumulator

Program counter extended

Program counter high

Program counter low

X-index high

X-index low

Y-index high

Y-index low

Stack pointer high

Stack pointer low

Code condition

Note: Register space accessible in debug mode only.

8.2.19 Global configuration register

Address

0x00.7F60

Table 33. CFG_GCR register map

Block Register name Register description

GCR CFG_GCR Global configuration

56/126 DocID027870 Rev 1

STLUX Memory and register map

Address

0x00.7F70

0x00.7F71

0x00.7F72

0x00.7F73

0x00.7F74

0x00.7F75

0x00.7F76

0x00.7F77

Table 34. Interrupt software priority register map

Block Register name Register description

ITC

ITC_SPR0

ITC_SPR1

ITC_SPR2

ITC_SPR3

ITC_SPR4

ITC_SPR5

ITC_SPR6

ITC_SPR7

Interrupt SW priority register 0

Interrupt SW priority register 1

Interrupt SW priority register 2

Interrupt SW priority register 3

Interrupt SW priority register 4

Interrupt SW priority register 5

Interrupt SW priority register 6

Interrupt SW priority register 7

8.2.21 SWIM control register

Address

0x00.7F80

0x00.7F90

…

0x00.7F9B

Block

Table 35. SWIM register map

Register name

SWIM

SWIM_CSR

DM_BK1E

…

DM_VER

Register description

SWIM control status

DM internal registers

DocID027870 Rev 1 57/126

126

Interrupt table STLUX

RESET

TRAP

NMI

AWU

CKC

AUXTIM

SMED0

SMED1

RFU (3)

SMED2

SMED3

UART

RFU (3)

RFU

ADC

SYS-TMR

FLASH

DALI

SMED4

SMED5

Priority Source block

Table 36. Interrupt vector exception table

Description

Wakeup from

Halt

Wakeup from active halt

Yes Yes Reset

Software interrupt

NMI (not maskable interrupt)

Auto-wakeup from Halt

Clock controller

GPIO0 [5:0] external interrupts

Auxiliary timer

DIGIN [5:0] external interrupts

SMED-0 interrupt

SMED-1 control logic

Reserved for future use

SMED-2 control logic

SMED-3 control logic

Tx complete

Receive register DATA FULL

C interrupt

Reserved for future use

End of conversion

Update/overflow

EOP/WR_PG_DIS

DALI interrupt line

SMED-4 control logic

SMED-5 control logic

Yes

(1)

(2)

Indirect

(4)

Indirect

Indirect

Yes

Yes

Yes

Interrupt vector address

8054h

8058h

805Ch

8060h

8064h

8068h

803Ch

8040h

8044h

8048h

804Ch

8050h

806Ch

8070h

8074h

8024h

8028h

802Ch

8030h

8034h

8038h

8000h

8004h

8008h

800Ch

8010h

8014h

8018h

801Ch

8020h

58/126 DocID027870 Rev 1

STLUX Interrupt table

Priority Source block

Table 36. Interrupt vector exception table (continued)

Description

Wakeup from

Halt

Wakeup from active halt

RFU (3)

RFU

Refer to MSC_IOMXP0 miscellaneous register field description Section 8.2 on page

Reserved future use

1. The P [2, 0] [x] may be configured to generate a NMI requests.

2. The P [2, 0] [x] may be configured to generate an IRQ requests.

3. All RFU and unused interrupts should be initialized with 'IRET' for robust programming.

4. The P0 [x] may be configured to generate an IRQ and NMI request.

Interrupt vector address

8078h

807Ch

DocID027870 Rev 1 59/126

126

Option bytes STLUX

The user option byte is a memory E²PROM area allowing users to customize the IC device major functionalities:

 ROP: readout protection control field

 UBC: user boot code protection

 PWM: configurable reset output value

 WDG: internal watchdog HW configuration

 AFR: alternate multifunction signals configuration

 CKC: clock controller functionalities (PLL, HSE enable, AWU clock selection, etc.)

 HSE: clock stabilization counter

 WAIT: Flash and E²PROM wait state access time has to be configured with value 0x00

 BOOT: configurable internal boot sources

 BL: bootloader control sequences

Except the ROP byte all the other option bytes are stored twice in a regular (OPT) and complemented format (NOPT) for redundancy. The option byte can be programmed in ICP mode through the SWIM interface or in IAP mode by the application with the exception of the ROP byte that can be only configured via the SWIM interface.

For further information about Flash programming refer to the programming manual “How to program STM8S and STM8A Flash program memory and data EEPROM” (PM0051).

For information on SWIM programming procedures refer to the “STM8 SWIM communication protocol and debug module” user manual (UM0470).

60/126 DocID027870 Rev 1

Table 37. Option byte register overview - STLUX385A

Option bits

Address Option name

Default settings

7 6 5 4 3 2 1 0

4800h

4801h

4802h

4803h

ROP

UCB nUCB

GENCFG

ROP[7:0]

UBC[7:0] nUBC[7:0]

Rst_PWM2 Rst_PWM1 Rst_PWM0

00h

FFh

00h Rst_PWM5 Rst_PWM4 Rst_PWM3 COMP1_2 EN_COLD_CFG

4804h nGENCFG nRst_PWM5 nRst_PWM4 nRst_PWM3 nRst_PWM2 nRst_PWM1 nRst_PWM0 nCOMP1_2 nEN_COLD_CFG FFh

4805h MISCUOPT 1 LSI_EN IWdg_hw WWdg_hw WWDG_HALT 28h

4806h nMISCUOPT

4807h

4808h

4809h

CLKCTL nCLKCTL

HSESTAB

nCKAWUSEL1 nLSI_EN nIWdg_hw nWWdg_hw nWWDG_HALT

CKAWUSEL1 EXTCLK CKAWUSE L0 nEXTCLK nCKAWUS EL0

HSECNT[7:0]

PRSC[1:0] nPRSC [1:0]

D7h

09h

F6h

00h nHSECNT[7:0] 480Ah nHSESTAB

480Bh

RESERVED

480Ch

480Dh WAITSTATE

480Eh nWAITSTATE

480Fh AFR_IOMXP0

4810h nAFR_IOMXP0 -

4811h AFR_IOMXP1 AUXTMR

4812h nAFR_IOMXP1 nAUXTMR

4813h AFR_IOMXP2 -

4814h nAFR_IOMXP2 -

Sel_P054[1:0]

nSel_P054[1:0]

Sel_P15 nSel_P15

Sel_P14 nSel_P14

Sel_P254 nSel_P254

nSel_P032[1:0]

Sel_P13 nSel_P13

Sel_P032[1:0]

Sel_P12 nSel_P12

WaitStat [1:0] nWaitStat [1:0]

Sel_P010[1:0] nSel_P010[1:0]

Sel_P11 nSel_P11

Sel_P10 nSel_P10

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

10h

EFh

Address Option name

4815h MSC_OPT0

4816h nMSC_OPT0

4817h

487Dh

RESERVED

487Eh

487Fh

OPTBL nOPTBL

Note:

Table 37. Option byte register overview - STLUX385A (continued)

Option bits

5 4

UARTLine [1:0] nUARTLine [1:0]

BL [7:0] nBL [7:0]

1 0

BootSel [1:0] nBootSe l[1:0]

Default settings

01h

FEh

00h

FFh

The default setting values refer to the factory configuration. The factory configuration can be overwritten by the user in accordance with the target application requirements.

The factory configuration values are loosed after user programming fields or in case of the ROP unprotecting attempt causing a “Global Flash Erase”.

The predefined initialized bit-values (1 or 0) must be preserved during memory writing.

An undefined option bit must be keep 0 and the complement value at 1 during the memory writing sequence.

Table 38. Option byte register overview - STLUX383A

Option bits

Address Option name

Default settings

7 6 5 4 3 2 1 0

4800h

4801h

4802h

4803h

ROP

UCB nUCB

GENCFG

ROP [7:0]

UBC [7:0] nUBC [7:0]

Rst_PWM5 Rst_PWM4 Rst_PWM3 Rst_PWM2 Rst_PWM1 Rst_PWM0 COMP1_2 EN_COLD_CFG

4804h

4805h nGENCFG

MISCUOPT

4806h nMISCUOPT nRst_PWM5 nRst_PWM4 nRst_PWM3 nRst_PWM2

0 -

nRst_PWM1 nRst_PWM0 nCOMP1_2 nEN_COLD_CFG

LSI_EN nLSI_EN

IWdg_hw WWdg_hw WWDG_HALT

FFh

28h

D7h

4807h

4808h

CLKCTL nCLKCTL -

CKAWUSEL1 nCKAWUSEL1

EXTCLK nEXTCLK nIWdg_hw nWWdg_hw nWWDG_HALT

CKAWUSE

PRSC[1:0] nCKAWUS

EL0 nPRSC[1:0]

09h

F6h

4809h

480Ah

480Bh

HSESTAB nHSESTAB

RESERVED

480Ch

480Dh WAITSTATE -

HSECNT [7:0] nHSECNT [7:0]

WaitStat [1:0]

00h

FFh

00h

FFh

00h

FFh

00h

480Eh nWAITSTATE

480Fh AFR_IOMXP0

4810h nAFR_IOMXP0

4813h AFR_IOMXP2

4814h nAFR_IOMXP2

4815h MSC_OPT0 -

4811h AFR_IOMXP1 AUXTMR

4812h nAFR_IOMXP1 nAUXTMR

Sel_P054 [1:0]

nSel_P054 [1:0]

Sel_P15 nSel_P15

Sel_P14 nSel_P14

Sel_P254 nSel_P254

UARTLine [1:0] -

Sel_P032 [1:0]

nSel_P032 [1:0]

Sel_P13 Sel_P12 nSel_P13

nSel_P12

nWaitStat [1:0]

Sel_P010 [1:0] nSel_P010 [1:0]

Sel_P11 Sel_P10 nSel_P11

nSel_P10

BootSel [1:0]

C0h

10h

EFh

01h

FFh

00h

FFh

3Fh

Address Option name

4816h nMSC_OPT0

4817h

RESERVED

487Dh

487Eh OPTBL

487Fh nOPTBL

Note:

Table 38. Option byte register overview - STLUX383A (continued)

Option bits

5 4 nUARTLine [1:0]

BL [7:0] nBL [7:0]

1 nBootSel [1:0]

Default settings

FEh

00h

FFh

The default setting values refer to the factory configuration. The factory configuration can be overwritten by the user in accordance with the target application requirements.

The factory configuration values are loosed after user programming fields or in case of the ROP unprotecting attempt causing a “Global Flash Erase”.

The predefined initialized bit-values (1 or 0) must be preserved during memory writing.

An undefined option bit must be keep 0 and the complement value at 1 during the memory writing sequence.

. Table 39. Option byte register overview - STLUX325A

Option bits

Address Option name

Default settings

7 6 5 4 3 2 1 0

4800h

4801h

4802h

4803h

4804h

4805h

4806h

4807h

4808h

ROP

UCB nUCB

GENCFG nGENCFG

MISCUOPT nMISCUOPT

CLKCTL nCLKCTL

4809h

480Ah

480Bh

480Ch

480Dh

480Eh

480Fh

HSESTAB nHSESTAB

RESERVED

WAITSTATE nWAITSTATE

AFR_IOMXP0

4810h nAFR_IOMXP0

4811h AFR_IOMXP1 AUXTMR

4812h nAFR_IOMXP1 nAUXTMR

4813h AFR_IOMXP2 Sel_SWIM

4814h nAFR_IOMXP2 nSel_SWIM

4815h MSC_OPT0

4816h nMSC_OPT0 -

ROP [7:0]

UBC [7:0] nUBC [7:0]

Rst_PWM4 Rst_PWM3 Rst_PWM2 Rst_PWM1 Rst_PWM0 nRst_PWM4 nRst_PWM3 nRst_PWM2 nRst_PWM1 nRst_PWM0

1 LSI_EN IWdg_hw

CKAWUSEL1 nLSI_EN

EXTCLK nIWdg_hw

CKAWUSE L0

WWdg_hw nWWdg_hw

EN_COLD_CFG

WWDG_HALT nWWDG_HALT

PRSC [1:0]

00h

FFh

00h nEN_COLD_CFG FFh

28h

D7h

09h

nCKAWUSEL1 nEXTCLK nCKAWUS

EL0 nPRSC [1:0] F6h

HSECNT[7:0] nHSECNT[7:0]

Sel_P054[1:0] nSel_P054[1:0]

Sel_P14 nSel_P14

Sel_P254 nSel_P254

UARTLine [1:0] nUARTLine [1:0]

Sel_P032[1:0] nSel_P032[1:0]

Sel_P13 nSel_P13

Sel_P12 nSel_P12

WaitStat [1:0] nWaitStat [1:0]

Sel_P11 nSel_P11

Sel_P10 nSel_P10

BootSel [1:0] nBootSel [1:0]

00h

FFh

00h

FFh

00h

FFh

00h

FFh

1Fh

E0h

10h

EFh

01h

FEh

Address Option name

4817h

487Dh

487Eh

487Fh

RESERVED

OPTBL nOPTBL

Note:

Table 39. Option byte register overview - STLUX325A (continued)

Option bits

6 5 4 3 2 1

BL [7:0] nBL [7:0]

Default settings

00h

FFh

The default setting values refer to the factory configuration. The factory configuration can be overwritten by the user in accordance with the target application requirements.

The factory configuration values are loosed after user programming fields or in case of the ROP unprotecting attempt causing a “Global Flash Erase”.

The predefined initialized bit-values (1 or 0) must be preserved during memory writing.

An undefined option bit must be keep 0 and the complement value at 1 during the memory writing sequence.

Address Option name

7 6

4800h

4801h

4802h

4803h

4804h

4805h

4806h

4807h

ROP

UCB nUCB

GENCFG nGENCFG

MISCUOPT nMISCUOPT

CLKCTL

4808h

4809h

480Ah

480Bh nCLKCTL

HSESTAB nHSESTAB

RESERVED

480Ch

480Dh WAITSTATE

480Eh nWAITSTATE

480Fh AFR_IOMXP0 -

4810h nAFR_IOMXP0 -

4811h AFR_IOMXP1 AUXTMR

4812h nAFR_IOMXP1 nAUXTMR -

4813h AFR_IOMXP2 1

4814h nAFR_IOMXP2

4815h MSC_OPT0

4816h nMSC_OPT0

Table 40. Option byte register overview - STLUX285A

Option bits

5 4 3 2 1 0

ROP [7:0]

UBC [7:0] nUBC [7:0]

Rst_PWM1 Rst_PWM3 Rst_PWM2 Rst_PWM0 nRst_PWM3 nRst_PWM2 nRst_PWM1 nRst_PWM0

1 LSI_EN IWdg_HW

WWdg_HW

EN_COLD_CFG nEN_COLD_CFG

WWDG_HALT

CKAWUSEL1 nLSI_EN

EXTCLK nIWdg_HW

CKAWUSE L0

- nCKAWUSEL1 nEXTCLK nCKAWUS

HSECNT [7:0] nHSECNT [7:0] nWWdg_HW nWWDG_HALT

PRSC [1:0]

Sel_P054 [1:0]

nSel_P054 [1:0]

UARTLine [1:0] nUARTLine [1:0]

Sel_P032 [1:0]

nSel_P032 [1:0]

Sel_P13 Sel_P12 nSel_P13 nSel_P12

Sel_P11 nSel_P11

WaitStat [1:0] nWaitStat [1:0]

Sel_P10 nSel_P10

BootSel [1:0] nBootSel [1:0]

Default settings

FFh

40h

BFh

00h

F6h

00h

FFh

00h

FFh

28h

D7h

09h

00h

FFh

00h

FFh

0Fh

F0h

50h

AFh

01h

FEh

Address Option name

4817h

487Dh

487Eh

487Fh

RESERVED

OPTBL nOPTBL

Note:

Table 40. Option byte register overview - STLUX285A (continued)

Option bits

6 5 4 3 2 1

BL [7:0] nBL [7:0]

Default settings

00h

FFh

The default setting values refer to the factory configuration. The factory configuration can be overwritten by the user in accordance with the target application requirements.

The factory configuration values are loosed after user programming fields or in case of the ROP unprotecting attempt causing a “Global Flash Erase”.

The predefined initialized bit-values (1 or 0) must be preserved during memory writing.

An undefined option bit must be keep 0 and the complement value at 1 during the memory writing sequence.

STLUX

10.2 Option byte register description

The option byte registers are mapped inside the E²PROM data region.

ROP (memory readout protection register)

7 6

Table 41. ROP (memory readout protection register)

Offset: 0x004800

Default value: 0x00

ROP [7:0]

3 r/w

2 1

Option bytes

Bit 7 - 0:

ROP [7:0] memory readout protection:

0xAA: enable readout protection. When readout protection is enabled, reading or modifying the Flash program memory and DATA area in ICP mode (using the SWIM interface) is forbidden, whatever the write protection settings are.

UBC (UBC user boot code register)

7 6

Table 42. UBC (UBC user boot code register)

Offset: 0x004801

Default value: 0x00

4 3

UBC [7:0] r/w

2 1 0

Bit 7 - 0:

UBC [7:0] user boot code write protection memory size: 0x00: no UBC, no Flash memory write-protection

0x01: pages 0 to 1 defined as UBC; 1 Kbyte memory write-protected (0x00.8000-

0x00.83FF)

0x02: pages 0 to 3 defined as UBC; 2 Kbyte memory write-protected (0x00.8000-

0x00.87FF)

0x03: pages 0 to 4 defined as UBC; 2.5 Kbyte memory write-protected (0x00.8000-

0x00.89FF)

... (512 byte every page)

0x3E: pages 0 to 63 defined as UBC; 32 Kbyte memory write-protected (0x00.8000-

0x00.FFFF)

Other values: reserved.

DocID027870 Rev 1 69/126

126

Option bytes

nUBC (UBC user boot code register protection)

Table 43. nUBC (UBC user boot code register protection)

Offset: 0x004802

6 5

Default value: 0xFF

4 nUBC [7:0] r/w

3 2 1

STLUX

0 nUBC: not (UBC) EMC byte protection.

GENCFG (general configuration register)

Table 44. GENCFG (general configuration register)

Offset: 0x004803

Default value: 0x00

7 6 5 4

Rst_PWM [5:0]

3 2 r/w

1. Available only on the STLUX385A and STLUX383A, otherwise keep 0.

COMP1_2

(1) r/w

EN_COLD_C FG r/w

Note:

Bit 0:

EN_COLD_CFG enables IC cold configuration through the option byte register

AFR_IOMXP0, P1 and P2:

0: default case, the IC multifunction signal configuration is performed by the miscellaneous registers MSC_IOMXP0, MSC_IOMXP1 and MSC_IOMXP2 (warm configuration).

1: enables the multifunction signal configuration through the option byte registers

AFR_IOMXP0, AFR_IOMXP1 and AFR_IOMXP2 (cold configuration).

Bit 1:

COMP1_2 enables the complete backward compatibility with the STLUX385 IC device.

Bit 7:2:

Rst_PWM [5:0] configures the PWM [n] reset value after the NRST signal

0: PWM [n] output low level (native default value)

1: PWM [n] output high level.

The PWM signal programmed reset value is configured during the option byte loader phase, then before the NRST is released it assumes its proper initial values.

The Rst_PWM5 is not available only on the STLUX325A and must be kept 0.

The Rst_PWM5 and Rst_PWM4 are not available only on the STLUX325A and must be kept 0.

70/126 DocID027870 Rev 1

STLUX Option bytes

nGENCFG (general configuration register protection)

Table 45. nGENCFG (general configuration register protection)

Offset: 0x004804

6 5 4 nRst_PWM [5:0] r/w

Default value: 0xFF

3 2 1 0 nCOMP1_2 nEN_COLD_CFG r/w r/w nGENCFG: not (GENCFG) EMC byte protection.

MISCUOPT (miscellaneous configuration register)

RFU r

Table 46. MISCUOPT (miscellaneous configuration register)

Offset: 0x004805

Default value: 0x28 (factory configuration)

RFU r

LSI_EN r/w

2 lWdg_hw r/w

WWdg_hw r/w

WWDG_HALT r/w

Bit 0:

WWdg_HALT window watchdog reset on Halt: 0: no reset generated on Halt if WWDG is active 1: reset generated on Halt if WWDG is active.

Bit 1:

WWdg_hw window watchdog hardware enable: 0: window watchdog activation by SW

1: window watchdog activation by HW. Bit 2:

IWdg_hw independent watchdog hardware enable:

0: independent watchdog activation by SW 1: independent watchdog activation by HW.

Bit 3:

LSI_EN low speed internal RCOSC clock enable:

0: LSI clock is not available to CPU

1: LSI cock is enabled for CPU.

Bit 4:

RFU reserved; must be kept 0 during register writing for future compatibility.

Bit 5:

RFU reserved; must be kept 1 during register writing for future compatibility.

Bit 7 - 6:

RFU reserved; must be kept 0 during register writing for future compatibility.

DocID027870 Rev 1 71/126

126

Option bytes STLUX

nMISCUOPT (miscellaneous configuration register protection)

Table 47. nMISCUOPT (miscellaneous configuration register protection)

Offset: 0x004806 nRFU r

Default value: 0xD7 (factory configuration)

5 nRFU r

4 nRFU r

3 nLSI_EN r/w

2 1 0 nlWdg_hw nWWdg_hw nWWdg_HALT r/w r/w r/w nMISCUOPT: not (MISCUOPT) EMC byte protection.

CLKCTL (CKC configuration register)

7 6

RFU r

Table 48. CLKCTL (CKC configuration register)

Offset: 0x004807

Default value: 0x09 (factory configuration)

5 4 3 2

CKAWUSEL1 EXTCLK CKAWUSEL0 r/w r/w r/w

PRSC [1:0]

0 r/w

Bit 1 - 0:

PRSC [1:0] prescaler value for HSE to provide the AWU unit with the low speed clock:

00: 24 MHz to 128 kHz prescaler

01: 16 MHz to 128 kHz prescaler

10: 8 MHz to 128 kHz prescaler

11: 4 MHz to 128 kHz prescaler.

Bit 3:

EXTCLK external clock selection:

0: external crystal oscillator clock connected to the HseOscin and HseOscout signals

1: external direct drive clock connected to the HseOscin.

Bit 4, 2:

CKAWUSEL[1:0] AWU clock selection:

00: low speed internal clock used for AWU module

01: HSE high speed external clock with prescaler used for AWU module

10: reserved encoding value

11: reserved encoding value.

Bit 7 - 5:

RFU reserved; must be kept 0 during register writing for future compatibility.

72/126 DocID027870 Rev 1

STLUX Option bytes

nCLKCTL (CKC configuration register protection)

Table 49. nCLKCTL (CKC configuration register protection)

Offset: 0x004808

6 nRFU r

Default value: 0xF6 (factory configuration)

4 3 2 nCKAWUSEL1 nEXTCLK nCKAWUSEL0 r/w r/w r/w

1 0 nPRSC [1:0] r/w nCLKCTL: not (CLKCTL) EMC byte protection.

HSESTAB (HSE clock stabilization register)

Table 50. HSESTAB (HSE clock stabilization register)

Offset: 0x004809

6 5

Default value: 0x00

HSECNT [7:0] r/w

3 2 1

Bit 7 - 0:

HSECNT [7:0] HSE crystal oscillator stabilization cycles:

0x00: 2048 clock cycles

0xB4: 128 clock cycles

0xD2: 8 clock cycles

0xE1: 0.5 clock cycles.

nHSESTAB (HSE clock stabilization register protection)

Table 51. nHSESTAB (HSE clock stabilization register protection)

Offset: 0x00480A

6 5

Default value: 0xFF

4 3 nHSECNT [7:0] r/w

2 1 0

0 nHSESTAB: not (HSESTAB) EMC byte protection.

DocID027870 Rev 1 73/126

126

Option bytes STLUX

WAITSTATE (Flash wait state register)

Table 52. WAITSTATE (Flash wait state register)

Offset: 0x00480D

Default value: 0x00 or 0x40 according to the device

5 4 3 2

RFU r

1 0

WaitStat [1:0] r/w

Bit 1 - 0:

WaitStat [1:0] configures the E²PROM and Flash programmable delay read access time:

00: 0 no delay cycle (default case f

MASTER

at 16 MHz) 01: 1 delay cycles

10: 2 delay cycles

11: 3 delay cycles.

Bit 7 - 2:

RFU reserved; must be kept 0 during register writing for future compatibility.

nWAITSTATE (Flash wait state register protection)

Table 53. nWAITSTATE (Flash wait state register)

Offset: 0x00480E

Default value: 0xFF or BF according to the device

5 nRFU r

4 3 2 1 0 nWaitStat [1:0] r/w nWAITSTATE: not (WAITSTATE) EMC byte protection.

74/126 DocID027870 Rev 1

STLUX Option bytes

AFR_IOMXP0 (alternative Port0 configuration register)

Table 54. AFR_IOMXP0 (alternative Port0 configuration register)

Offset: 0x00480F

Default value: 0x00

RFU r

6 5 4

Sel_P054 [1:0] r/w

3 2

Sel_P032 [1:0] r/w

1. Available only on the STLUX385A and STLUX383A, otherwise keep 0.

1 0

Sel_P010 [1:0]

(1) r/w

Bit 5 - 0:

Bit 7 - 6:

RFU reserved; must be kept 0 during register writing for future compatibility.

nAFR_IOMXP0 (alternative Port0 configuration register protection)

Table 55. nAFR_IOMXP0 (alternative Port0 configuration register protection)

Offset: 0x004810

7 nRFU r

Default value: 0xFF

5 4 nSel_P054 [1:0] r/w

3 r/w

2 nSel_P032 [1:0]

1 0 nSel_P010 [1:0] r/w nAFR_IOMXP0: not (AFR_IOMXP0) EMC byte protection.

DocID027870 Rev 1 75/126

126

Option bytes STLUX

AFR_IOMXP1 (alternative Port1 configuration register)

Table 56. AFR_IOMXP1 (alternative Port1 configuration register)

Offset: 0x004811

Default value: 0x00 or 0x3F or 0x1F or 0x0F according to the device

AUXTMR r/w

RFU r

Sel_P15

(1) r/w

Sel_P14 r/w

(2)

Sel_P13 r/w

2 1 0

Sel_P12 Sel_P11 Sel_P10 r/w r/w r/w

1. Available only on the STLUX385A and STLUX383A, otherwise keep 0.

2. Available only on the STLUX385A, STLUX383A and STLUX325A, otherwise keep 0.

Bit 5 - 0:

Refer to MSC_IOMXP1 miscellaneous register field description Section 8.2.3 on page

Bit 6:

RFU reserved; must be kept 0 during register writing for future product compatibility.

Bit 7:

AUXTIM CCO aux timer compatibility features

0: CCO aux timer enabled

1: CCO aux timer disabled.

nAFR_IOMXP1 (alternative Port1 configuration register protection)

Table 57. nAFR_IOMXP1 (alternative Port1 configuration register protection)

Offset: 0x004812

Default value: 0xFF or 0xC0 or 0xE0 or 0xF0 depends on devices

7 6 5 4 3 2 1 nAUXTMR nRFU nSel_P15 nSel_P14 nSel_P13 nSel_P12 nSel_P11 r/w r r/w r/w r/w r/w r/w

0 nSel_P10 r/w nAFR_IOMXP1: not (AFR_IOMXP1) EMC byte protection.

76/126 DocID027870 Rev 1

STLUX Option bytes

AFR_IOMXP2 (alternative Port2 configuration register)

Table 58. AFR_IOMXP2 (alternative Port2 configuration register)

Offset: 0x004813

Sel_SWIM r/w

(1)

Default value: 0x10 or 0x50 according to the device

RFU r

5 4

Sel_P254 r/w

1. Available only on the STLUX325A, otherwise keep 0.

2. Not available on the STLUX285A, must be kept to 1.

(2)

RFU r

Bit 3 - 0:

RFU reserved; must be kept 0 during register writing for future product compatibility

Bit 4:

Refer to MSC_IOMXP2 miscellaneous register field description Section 7.4 on page

Bit 6 - 5:

RFU reserved; must be kept 0 during register writing for future product compatibility. On

STLUX285A devices bit 6 must be kept to 1.

Bit 7:

Refer to MSC_IOMXP2 miscellaneous register field description Section 7.4

nAFR_IOMXP2 (alternative Port2 configuration register protection)

Table 59. nAFR_IOMXP2 (alternative Port2 configuration register protection)

Offset: 0x004814

7 nSel_SWIM r/w

Default value: 0xEF or 0xAF according to the device

6 nRFU r

5 4 nSel_P254 r/w

3 nRFU r

2 nRFU r

1 nRFU r

0 nRFU r nAFR_IOMXP2: not (AFR_IOMXP2) EMC byte protection.

DocID027870 Rev 1 77/126

126

Option bytes STLUX

MSC_OPT0 (miscellaneous configuration reg0)

RFU r

Table 60. MSC_OPT0 (miscellaneous configuration reg0)

Offset: 0x004815

6 5

Default value: 0x01

UARTline [1:0] r/w

RFU r

2 1

BootSel [1:0] r/w

Bit 1 - 0:

BootSel [1:0] boot-ROM peripheral enables:

00: automatic scan boot sources; this selection enables the automatic scan configuration sequence of all possible initializing peripheral devices: Periph0 (UART),

Periph1 (RFU).

01: enable boot source: Periph0 10: enable boot source: Periph1

11: enable boot sources: Periph1, Periph0

Bit 3 - 2:

RFU reserved; must be kept 0 during register writing for future compatibility.

Bit 5 - 4:

UARTline [1:0] selects the UART port configuration pins involved during the bootload sequence in warm configuration mode; in case of cold configuration, this field is ignored since the UART port is selected by the register AFR_IOXP0.

00: boot sequence with the UART i/f configured in all possible UART multiplexed signal schemes. This sequence is used when UART i/f position is not specified.

01: boot sequence with UART i/f configured on P0 (1, 0) 10: boot sequence with UART i/f configured on P0 (3, 2) 11: boot sequence with UART i/f configured on P0 (5, 4).

Bit 7 - 6:

RFU reserved; must be kept 0 during register writing for future compatibility.

nMSC_OPT0 (miscellaneous configuration reg0 protection)

Table 61. nMSC_OPT0 (miscellaneous configuration reg0 protection)

Offset: 0x004816 nRFU r

6 5 nUARTline [1:0] r/w

Default value: 0xFE

4 3 nRFU r

2 1 nBootSel [1:0]

0 r/w nMSC_OPT0: not (MSC_OPT0) EMC byte protection.

78/126 DocID027870 Rev 1

STLUX

OPTBL (option byte bootloader)

7 6

Table 62. OPTBL (option byte bootloader)

Offset: 0x00487E

Default value: 0x00

4 3

BL [7:0] r/w

2 1

Option bytes

Bit 7 - 0:

BL [7:0] the bootloader field checked by the internal BootROM code during the STLUX initialization phase. The content of register locations 0x00487E, 0x00487F and

0x008000 determine the bootloader SW flow execution sequence.

nOPTBL (option byte boot loader protection)

Table 63. nOPTBL (option byte boot loader protection)

Offset: 0x00487F

6 5

Default value: 0xFF

4 nBL [7:0] r/w

3 2 1 0 nOPTBL: not (OPTBL) EMC byte protection.

DocID027870 Rev 1 79/126

126

Device identification STLUX

The STLUX family provides a 56-bit unique identifier code usable as a device identification number which can be used to increase the device security. The unique ID code is a frozen signature not alterable by user.

The unique device identifier is ideally used by the application software and is suited for:

 Serial code

 Security keys in conjunction with cryptographic software to increase the embedded

Flash code security

 Activating the secure boot sequence.

Address

48E0h

48E1h

48E2h

48E3h

48E4h

48E5h

48E6h

48E7h

Table 64. Unique ID register overview

Unique ID bits

Option name

7 6 5 4 3 2

UID0

UID1

UID2

UID3

UID4

UID5

UID6

UID7

WaferNum [4:0]

Xcoord [4:0]

Ycoord [4:0]

LotNum [7:0]

LotNum [15:8]

LotNum [23:16]

LotNum [31:24]

LotNum [39:32]

Xcoord [7:5]

Ycoord [7:5]

LotNum [42:40]

80/126

The STLUX family identification model is coded in the following register area and it cannot be altered by the user.

Address

4896h

4897h

4898h

4899h

1. See Table 66 .

Option name

Table 65. Dev ID register overview

Dev ID bits

7 6 5 4 3 2 1 0

DVD0 nDVD0

DVD1 nDVD1

RFU nRFU

DEV_ID[7:0] nDEV_ID[7:0]

Rev_ID [4:0] nRev_ID [4:0]

Default settings

(1)

DocID027870 Rev 1

STLUX

Note:

Device identification

The RFU and nRFU value are reserved and the value may be changed within devices.

DEV_ID[7:0]

0x00

0x10

0x02

0x20

Table 66. Device revision model overview

STLUX device revision model

Rev_ID[4:0]

0b00000

0b00001

Device name

STLUX385

STLUX385A

STLUX325A

STLUX383A

STLUX285A

The mask DVD1 and nDVD1 register with 0x1F when read the Rev_ID [4:0] field.

DocID027870 Rev 1 81/126

126

Electrical characteristics STLUX

Unless otherwise specified, all voltages are referred to V

SS connected to the same voltage value. V shortest wire loop.

and V

. V

DDA

and V

must be

SSA

must be connected together with the

12.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

A max. (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated according to each table specific notes and are not tested in production.

Unless otherwise specified, typical data are based on T

= 25 °C, V

and V

DDA

= 3.3 V.

They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range.

Unless otherwise specified, all typical curves are given as design guidelines only and are not tested.

For typical current consumption measurements, V

shown in Figure 12

and V

are connected together as

Figure 12. Supply current measurement conditions

82/126 DocID027870 Rev 1

STLUX Electrical characteristics

The loading conditions used for pin parameter measurement are shown in

Figure 13

Figure 13. Pin loading conditions

The input voltage measurement on a pin is described in Figure 14

Figure 14. Pin input voltage

DocID027870 Rev 1 83/126

126

Electrical characteristics STLUX

12.2 Absolute maximum ratings

Stresses above those listed as 'absolute maximum ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect the device reliability.

Symbol

Table 67. Voltage characteristics

Ratings

DDX

- V

SSX

- V

DDA

- V

SSA

Supply voltage (1)

Input voltage on any other pin

(2)

Variation between different power pins

Variation between all the different ground pins

(3)

Min.

-0.3

- 0.3

ESD

Electrostatic discharge voltage

Max.

6.5

+ 0.3

Unit

V mV

Refer to absolute maximum ratings (electrical sensitivity) in Section 11.4.1 on page 93

1. All power V power supply.

, V

DDA

) and ground V

SSX

, V

SSA

) pins must always be connected to the external

2. I

INJ(PIN)

must never be exceeded. This is implicitly insured if V injection is induced by V

> V

maximum is respected. If V

while a negative injection is induced by V

< V

maximum

value. A positive

3. V

and V

SSA

signals must be interconnected together with a short wire loop.

Table 68. Current characteristics

Symbol Ratings Max.

(1)

Unit

VDDX

VSSX

Total current into V

DDX

power lines

(2)

Total current out of V

SSX

power lines

Ref. to Table 82 on page 100

100

Output current sunk by any I/Os and control pin

Output current source by any I/Os and control pin

INJ(PIN)

(3)

(4)

INJ(TOT)

Table 70 . In addition, a full account must be taken for all physical capacitor characteristics

(5)

Injected current on any pin

Sum of injected currents

±4

±20

1. Data based on characterization results, not tested in production.

2. All power V power supply.

, V

DDA

) and ground V

SSX

, V

SSA

) pins must always be connected to the external

3. I

INJ(PIN)

must never be exceeded. This is implicitly insured if V

maximum is respected. If V cannot be respected, the injection current must be limited externally to the I injection is induced by V

> V

while a negative injection is induced by V

INJ(PIN)

< V

maximum

value. A positive

4. Negative injection disturbs the analog performance of the device.

5. When several inputs are submitted to a current injection, the maximum characterization with 

IINJ(PIN)

I

INJ(PIN)

is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on

maximum current injection on four I/O port pins of the device.

84/126 DocID027870 Rev 1

STLUX Electrical characteristics

Symbol

STG

Table 69. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Max.

-65 to 150

150

Unit

ºC

The device must be used in operating conditions that respect the parameters listed in

and tolerances.

Symbol

Table 70. General operating conditions

Parameter Conditions Min.

Typ.

Max.

Unit f

CPU

DD1

, V

DDA1

, V

DDA

Internal CPU clock frequency

Operating voltages

Nominal operating voltages

-40  T

 105 °C 0

(1)

3.3

(1)

5.5

(1)

MHz

OUT

Core digital power supply

CVOUT: capacitance of external capacitor

(3)

ESR of external capacitor

(2)

ESL of external capacitor

(2) at 1 MHz

470

0.05

1.8

(2)

3300

0.2

15 nF

 nH



(4)

FR4 multilayer PCB

TSSOP38

TSSOP28

VFQFPN32

°C/W

Ambient temperature Pd = 100 mW -40 105 °C

1. The external power supply can be within range from 3 V up to 5.5 V although IC performances are optimized for a power supply equal to 3.3 V.

2. Internal core power supply voltage.

3. Care should be taken when the capacitor is selected due to its tolerance, its dependency on temperature,

DC bias and frequency.

4. To calculate P

Dmax

), use the formula P

Dmax

= (T

Jmax

- T

)/ J

DocID027870 Rev 1 85/126

126

Electrical characteristics STLUX

Symbol

Table 71. Operating conditions at power-up/power-down

Parameter Conditions Min.

(1)

Typ.

Max.

(1)

VDD

rise time rate

fall time rate

Reset release delay t

TEMP

IT+

IT-

HYS(BOR)

Power-on reset threshold

Brownout reset threshold

Brownout reset hysteresis

1. Guaranteed by design, not tested in production.

2. Power supply ramp must be monotone.

rising

2 µs/V

2.65

2.58

2.8

2.73

1 sec./V

(2)

1 sec./V

is specified in Section 12.3: Operating conditions .

2.98

2.88

Unit ms

V mV

12.3.1 VOUT external capacitor

The stabilization of the main regulator is achieved by connecting an external capacitor

VOUT

(c)

to the VOUT pin. The C

VOUT

Care should be taken to limit the series inductance to less than 15 nH.

Figure 15. External capacitor C

VOUT

12.3.2 Supply current characteristics

The STLUX supply current is calculated by summing the supply base current in the desired operating mode as per

Table 72 , with the peripheral supply current value reported in

Table 74 on page 90

and Table Table 75 on page 92 .

For example, considering an application where:

 f

MASTER

= f

CPU

= 16 MHz provided by HSI internal RC oscillator

 CPU code execution in Flash

 All base peripheral actives: I

C, UART, DALI, ITC, GPIO0, SysTmrWWDG and IWDG

 ADC conversion frequency f

ADC

= 5.3 MHz

 ACU (comparator and DAC units) active

 6 PWM toggling at f

PWM

= 6).

= 0.5 MHz provided by 6 SMEDs running at f

SMED

= 12 MHz

86/126 c. ESR is the equivalent series resistance and ESL is the equivalent inductance.

DocID027870 Rev 1

STLUX Electrical characteristics

The total current consumption is given by

Equation 1 :

Equation 1

= I

DD(Run2)

+ I

DD(ADC2)

+ I

DD(ACU)

+ I

DD(PLL)

+ I

DD(PWM) where I

DD(PWM)

= I

DD(PWM1)

* N

PWM

More generally, the PWM current consumption has to be individually evaluated for each f

SMED

clock grouping, using

Equation 2 .

Equation 2



=  i = 1

SMED

XXXX  I



 N i

 where i = f

SMED

clock group index; N i

= PWM number of the i_th clock group;

N fSMED

= f

SMED

clock group number.

DocID027870 Rev 1 87/126

126

Electrical characteristics STLUX

IC supply base current consumption

Table 72 summarizes the current consumption measured on V

DD relevant operative conditions.

DDA supply pins in

Symbol

Table 72. Supply base current consumption at V

DDA

= 3.3/5 V

Code Clock Peripheral Consumption

(1)

Note

Op. mode

Code area f

MASTER f

CPU

Periph

(2)

Source MHz MHz Enb/Dis

(3)

Typ.

(4) mA

Max.

Description

DD(Run1)

DD(Run2)

DD(Run3)

Flash

RAM

HSI

All

2.3

9.4

4.2

2.77

Reset exit condition

11.3

5.1

DD(Run4)

DD(Run5)

Flash

RAM

HSE

(5)

All

10.0

10.6

4.6

5.2

12.1

DDA

= 3.3 V

12.74

DDA

= 5 V

5.53

DDA

= 3.3 V

6.63

DDA

= 5 V

4.33

DD(SLOW1)

DD(SLOW2)

Flash

RAM

HSI

All

3.6

2.9

3.5

DD(SLOW3)

Flash

16 2 All

3.9

4.5

4.7

5.5

DDA

= 3.3 V

DDA

= 5 V

DD(SLOW4)

Flash HSI 16 0.125

All 2.7

3.3

DD(SLOW5)

Flash

16 0.125

All

3.0

3.6

3.7

4.4

DDA

= 3.3 V

DDA

= 5 V

DD(SLOW6)

DD(WFI1)

Flash

LSI 0.153 0.153

HSI 16 16

All

1.5

2.6

1.9

3.2

DD(WFI2)

Flash

Table 73 summarizes the current consumption measured on V

16 16 All

3.1

3.8

5.6

DDA

= 3.3 V

DDA

= 5 V

1. Data based on characterization results not tested in production.

“ All ” means: I

C, UART, DALI, ITC, GPIO0, SysTmr, WWDG and IWDG peripherals active.

3. The peripheral current consumption is supplied by the VCORE voltage (1.8 V).

4. Temperature operating: T

= 25 °C.

5. HSE frequency provided by external quartz.

88/126 DocID027870 Rev 1

STLUX Electrical characteristics

IC low power current consumption

DD saving conditions.

DDA

supply pins in power

Symbol

Table 73. Supply low power consumption at V

DDA

= 3.3/5 V

Code Clock Peripheral Consumption

(1)

Op. mode

(2)

(3)

Code area f

MASTER

PROM

Source MHz Enable

(4)

MVRreg.

(5)

Enable

Typ.

(6)

(7)

Max.

(8)

mA mA

Note

Description

DD(AHLT1)

DD(AHLT2)

Flash

HSI

Enable

Disable

0.23

0.085

0.32

0.12

AWU clocked by LSI

DD(AHLT3)

DD(AHLT4)

Flash HSE

(9)

(10)

Flash HSE

(10)

Enable

Disable

0.73

1.4

0.65

1.2

0.90

1.7

0.95

1.45

DDA

= 3.3 V

DDA

= 5 V

DDA

= 3.3 V

DDA

= 5 V

DD(HLT1)

Flash HSI 16 Enable Disable 0.087

0.13

DD(HLT2)

Flash HSE

Table 74 summarizes the peripheral current consumption measured on V

(10)

16 Enable Disable

0.075

0.090

0.11

0.15

DDA

= 3.3 V

DDA

= 5 V

1. Data based on characterization results not tested in production.

2. Active halt op. mode: all peripherals except AWU and IWDG are disabled (clock gated).

3. HALT op. mode: all peripherals are disabled (clock gated).

4. E 2 PROM is considered always enabled.

VCORE main DC voltage regulator.

6. Temperature operating: T

= 25 °C.

7. All the analog input signals are connected to GND; the signals of the port P0, P1 and P2 are configured as input with the pull-up enabled.

8. Temperature operating: T

= 105 °C.

9. HSE frequency provided by external quartz.

10. AWU clocked by HSE source clock.

DocID027870 Rev 1 89/126

126

Electrical characteristics STLUX

IC peripheral current consumption (3.3 V)

DD pins.

DDA

supply

Symbol

Op.mode

DD(PLL)

DD(ACU)

DD(PWM1PLL96)

DD(PWM4PLL96)

DD(PWM5PLL96)

DD(PWM6PLL96)

DD(PWM1PLL48)

DD(PWM4PLL48)

DD(PWM5PLL48)

DD(PWM6PLL48)

DD(PWM1PLL24)

DD(PWM4PLL24)

DD(PWM5PLL24)

DD(PWM6PLL24

DD(PWM1PLL12)

DD(PWM4PLL12)

DD(PWM5PLL12)

DD(PWM6PLL12)

DD(PWM1PLL6)

DD(PWM4PLL6)

DD(PWM5PLL6)

DD(PWM6PLL6)

DD(PWM1HSI16)

DD(PWM4HSI16)

DD(PWM5HSI16)

DD(PWM6HSI16)

Table 74. Peripheral supply current consumption at V

DDA

= 3.3 V

Clock Peripherals Consumption

(1)

PLL

Enb/Dis

Enab

Disab

Enab

Enab f

SMED

(2)

MHz

16 f

PWM

(3)

MHz

0.5

ADC

(4)

MHz

ADC

(5)

Enb/Dis

Disab

ACU

(8)

Typ.

Enb/Dis mA

(9)

Disab

Enab

2.3

1.9

1.8

6.69

Disab

8.55

10.12

1.12

4.31

5.6

Disab

6.54

0.71

2.89

3.9

4.39

0.6

2.2

2.95

3.33

Disab

0.5

1.85

2.6

2.81

0.5

1.79

2.3

2.63

PWM

(6)

(7)

Num

0.6

2.26

3.2

3.4

0.6

2.19

3.3

4.7

5.27

0.7

2.69

3.6

10.4

12.2

1.4

5.31

6.8

7.85

0.9

3.54

Max.

Table 75 summarizes the peripheral current consumption measured on V

2.7

2.3

2.1

8.32

90/126 DocID027870 Rev 1

STLUX Electrical characteristics

Table 74. Peripheral supply current consumption at V

DDA

= 3.3 V (continued)

Symbol Clock Peripherals Consumption (1)

DD(PWM1HSI8)

DD(PWM4HSI8)

DD(PWM5HSI8)

DD(PWM6HSI8)

DD(PWM1HSI4)

DD(PWM4HSI4)

DD(PWM5HSI4)

DD(PWM6HSI4)

DD(PWM1HSI2)

DD(PWM4HSI2)

DD(PWM5HSI2)

DD(PWM6HSI2)

DD(ADC1)

DD(ADC2)

DD(ADC3)

Enab

Disab

Enab

0.5

5.3

Disab

Enab

1. Data based on characterization results not tested in production.

2. SMED frequency:

- 96 MHz and 6 MHz frequencies require the PLL enabled.

- Current table shows only a subset value of possible SMED frequencies.

3. PWM frequency:

- PWM toggle frequency is considered fixed to 500 kHz, close to the maximum applicative value.

4. 3.ADC frequency:

- 6 MHz frequency requires the PLL enabled.

- Current table shows only a subset value of possible ADC frequencies.

5. ADC configured in circular mode.

6. PWM pins are loaded with a CL (load capacitance) of 50 pF.

Number of active PWMs.

8. If enabled all DACs and comparator units are active.

9. Temperature operating: T

= 25 °C.

Disab

0.25

1.07

1.52

1.60

1.55

1.6

1.56

0.3

1.21

1.7

1.78

0.4

1.39

1.95

2.12

0.3

1.31

1.9

1.93

1.87

1.95

1.88

0.4

1.48

2.2

0.5

1.7

2.4

2.55

DocID027870 Rev 1 91/126

126

Electrical characteristics STLUX

IC peripheral current consumption (5 V)

DD pins.

VDDA

supply

Symbol

Op. mode

DD(PLL)

DD(ACU)

DD(PWM1PLL96)

DD(PWM4PLL96)

DD(PWM5PLL96)

DD(PWM6PLL96)

DD(PWM1PLL48)

DD(PWM4PLL48)

DD(PWM5PLL48)

DD(PWM6PLL48)

DD(PWM1PLL24)

DD(PWM4PLL24)

DD(PWM5PLL24)

DD(PWM6PLL24)

DD(PWM1PLL12)

DD(PWM4PLL12)

DD(PWM5PLL12)

DD(PWM6PLL12)

DD(PWM1PLL6)

DD(PWM4PLL6)

DD(PWM5PLL6)

DD(PWM6PLL6)

DD(PWM1HSI16)

DD(PWM4HSI16)

DD(PWM5HSI16)

DD(PWM6HSI16)

Table 75. Peripheral supply current consumption at V

VDDA

= 5 V

Clock Peripherals Consumption

(1)

PLL

Enb/Dis

Enab

Disab

Enab

Enab f

SMED

(2)

MHz

16 f

PWM

(3)

MHz

0.5

ADC

(4)

ADC

(5)

MHz Enb/Dis

Disab

PWM

(6)

(7)

Num

ACU

(8)

Enb/Dis

Disab

Enab

Disab

0.5

2.11

2.9

3.11

0.6

2.04

2.8

3.13

4.2

4.73

0.6

2.46

3.3

3.66

9.0

10.49

1.18

4.58

5.9

6.88

0.8

3.16

Typ.

(9) mA

2.32

2.22

1.81

6.98

0.6

2.58

3.6

3.75

0.7

2.49

3.4

3.78

5.2

5.68

0.7

3.01

4.2

4.4

10.8

12.52

1.42

5.65

7.5

8.26

0.95

3.88

Max.

Table 76 shows the wake-up time to resume the normal operating mode from the different

2.78

2.66

2.17

8.69

92/126 DocID027870 Rev 1

STLUX Electrical characteristics

Table 75. Peripheral supply current consumption at V

VDDA

= 5 V (continued)

Symbol Clock Peripherals Consumption (1)

DD(PWM1HSI8)

DD(PWM4HSI8)

DD(PWM5HSI8)

DD(PWM6HSI8)

DD(PWM1HSI4)

DD(PWM4HSI4)

DD(PWM5HSI4)

DD(PWM6HSI4)

DD(PWM1HSI2)

DD(PWM4HSI2)

DD(PWM5HSI2)

DD(PWM6HSI2)

DD(ADC1)

DD(ADC2)

DD(ADC3)

Enab

Disab

Enab

0.5

5.3

Disab

Enab

Disab

1. Data based on characterization results not tested in production.

2. SMED frequency:

- 96 MHz and 6 MHz frequencies require the PLL enabled.

- Current table shows only a subset value of possible SMED frequencies.

3. PWM frequency:

- PWM toggle frequency is considered fixed to 500 kHz, close to the maximum applicative value.

4. ADC frequency:

- 6 MHz frequency requires the PLL enabled.

- Current table shows only a subset value of possible ADC frequencies.

5. ADC configured in circular mode.

6. Number of active PWMs.

7. PWM pins are loaded with a CL (load capacitance) of 50 pF.

8. If enabled all DACs and comparator units are active.

9. Temperature operating: T

= 25 °C.

0.4

1.31

1.9

2.1

2.11

2.16

2.17

0.47

1.48

2.2

2.33

0.5

1.64

2.3

2.56

0.54

1.6

2.3

2.49

2.54

2.6

2.61

0.55

1.81

2.7

2.78

0.6

2.0

2.9

3.1

DocID027870 Rev 1 93/126

126

Electrical characteristics STLUX

PWM current consumption overview

From

Figure 16

to Figure 19

provide an outline view of PWM current consumption results.The consumptions are evaluated considering the maximum current at T

= 25 °C with different SMED operating frequencies. The charts summarize the measurements carried out from

Table 74 on page 90

and Table 75

allowing users to derive the PWM current consumption values.

Figure 16. PWM current consumption with f at V

VDDA

= 5 V

SMED

= PLL f

PWM

= 0.5 MHz

Figure 17. PWM current consumption with f

SMED at V

VDDA

= 5 V

= PLL f

PWM

= 0.5 MHz

94/126 DocID027870 Rev 1

STLUX Electrical characteristics

Figure 18. PWM current consumption with f

SMED at V

VDDA

= 3.3 V

= HSI f

PWM

= 0.5 MHz

Figure 19. PWM current consumption with f

SMED at V

VDDA

= 5 V

= HSI f

PWM

= 0.5 MHz

DocID027870 Rev 1 95/126

126

Electrical characteristics STLUX

Low power mode wake-up time

low power state.

Symbol Parameter

Table 76. Wake-up times

Conditions t

WU(WFI) t t

WU(AH)

WU(H)

Wake-up time from wait mode to run mode (2) f f

CPU

 f

= f

MASTER

= 0 to 16 MHz

= 16 MHz

Wake-up time active halt mode to run mode

MVR voltage regulator on

(4)

Flash in operating mode

(5)

Flash in power- down mode

MVR voltage regulator

off

Flash in operating mode

Flash in power- down mode

Flash in operating mode

Wake-up time from halt mode to run mode

Flash in power-down mode

The crystal characteristics have to be checked with Equation 3 :

1. Data based on characterization results, not tested in production.

2. Measured from the interrupt event to interrupt vector fetch.

3. t

WU(WFI)

= 2 x 1/f

MASTER

+ 7 x 1/f

CPU

4. Configured by the REGAH bit in the CLK_ICKR register.

5. Configured by the AHALT bit in the FLASH_CR1 register.

6. Plus 1 LSI clock depending on synchronization (f

LSI

= 153.6 kHz).

HSI

(after wake-up)

Typ.

(1)

Max.

(1)

Ref.

(3)

0.56

(6)

Unit

s

HSE user external clock

Subject to general operating conditions for V

and T

Symbol

Table 77. HSE user external clock characteristics

Parameter Conditions Min.

Max.

I f

HSE_ext

HSEH

(2)

User external clock source frequency

HSEOSCIN input pin high level voltage

HSEOSCIN input pin low level voltage

HSEOSCIN input pin leakage

-40 °C  T

 105 °C

 V

0.7 x V

-1

1. In case f

HSE

is configured as a direct clock for the SMED logics the maximum frequency can be 24 MHz.

2. Data based on characterization results, not tested in production.

(1)

0.3 x V

Unit

MHz

µA

96/126 DocID027870 Rev 1

STLUX

Figure 20. HSE external clock source

Electrical characteristics

HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied with a 1 to 24 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal resonator manufacturer for more details

(frequency, package, accuracy, etc.).

Symbol

Table 78. HSE crystal/ceramic resonator oscillator

Parameter Conditions Min. Typ.

Max.

Unit

I f

HSE

L1,

(2)

DD(HSE)

External high speed oscillator frequency

Feedback resistor

Recommended load capacitance

(3)

HSE oscillator power consumption

220

(1)

6 (startup)

2 (stabilized)

MHz k  pF mA g m t

SU(HSE)

(4)

Oscillator transconductance

Startup time V

is stabilized

2.8

mA/V ms

1. In case f

HSE

is configured as a direct clock for the SMED logic the maximum frequency can be 24 MHz.

2. The oscillator needs two load capacitors, CL1 and CL2, to act as load for the crystal. The total load capacitance (Cload) is (CL1 * CL2)/ (CL1 + CL2). If CL1 = CL2, Cload = CL1 / 2. Some oscillators have built-in load capacitors, CL1 and CL2.

3. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value.

4. t

SU(HSE)

is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

DocID027870 Rev 1 97/126

126

Electrical characteristics

Figure 21. HSE oscillator circuit diagram

STLUX

Equation 3 g m

» g mCritic where g mCritic

is calculated with the crystal parameters as follows:

Equation 4 g mCritic

= (2 * * f

HSE

)

* R m

(2C

+ C)

2 and where:

 R m

: motional resistance (d)

 L m

: motional inductance

(d)

 C m

: motional capacitance (d)

 C

: shunt capacitance

(d)

 C

= C

= C: grounded external capacitance

98/126 d. Refer to the application crystal specification.

DocID027870 Rev 1

STLUX Electrical characteristics

12.3.4 Internal clock sources and timing characteristics

HSI RC oscillator

Subject to general operating conditions for V

and T

Symbol Parameter

Table 79. HSI RC oscillator

Conditions f

HSI

Frequency

ACC

HSI

Accuracy of HSI oscillator

(factory calibrated)

(1)

(2)

= 3.3 V

= 25 ºC

= 3.3 V

-40 ºC  T

 105 ºC

= 5 V

-40 ºC  T

 105 ºC t

SU(HSI)

HSI oscillator wake-up time including calibration

1. Data based on characterization results, not tested in production.

2. Variation referred to f

HSI

nominal value.

Min.

(1)

Typ. Max.

(1)

Unit

16 MHz

-1%

-4%

+1%

+4%

µs

LSI RC oscillator

Subject to general operating conditions for V

and T

Symbol Parameter

Table 80. LSI RC oscillator

Conditions f

LSI

Frequency

ACC

LSI

Accuracy of LSI oscillator t

SU(LSI)

LSI oscillator wake-up time

1. Guaranteed by design, not tested in production.

3.3 V  V

-40 ºC  T

 5 V

 105 ºC

Min.

(1)

-10%

Typ.

Max.

(1)

153.6

Unit kHz

10% %

µs

PLL internal source clock

Symbol

Table 81. PLL internal source clock

Parameter Conditions f

IN f

OUT t lock

Input frequency

PLL lock time

(2)

Output frequency

3.3 V  V

-40 ºC  T

 5 V

 105 ºC

1. Data based on characterization results, not tested in production.

2. PLL maximum input frequency 16 MHz.

Min.

(1)

Typ.

Max.

(1)

200

Unit

MHz

µs

DocID027870 Rev 1 99/126

126

Electrical characteristics STLUX

Flash program and memory/data E

PROM memory

General conditions: T

= -40 °C to 105 °C.

Symbol

Table 82. Flash program memory/data E

PROM memory

Parameter Conditions Min.

(1)

Typ.

(1)

Max.

(1)

Unit t

PROG

Standard programming time (including erase) for byte/word/block (1 byte/4 bytes/128 bytes)

Fast programming time for 1 block (128 bytes)

6.6

3.3

ms t

ERASE

Erase time for 1 block (128 bytes)

Erase/write cycles

(2)

(program memory)

(data memory)

= 25 °C

= 85 °C

= 105 °C

10 K

100 K

35 K

3 3.3

Cycles

I t

RET

DDPRG

Data retention (program memory) after 10 K erase/write cycles at T

= 25 °C

Data retention (program memory) after 10 K erase/write cycles at T

= 25 °C

Data retention (data memory) after 100 K erase/write cycles at T

= 85 °C

Data retention (data memory) after 35 K erase/write cycles at T

= 105 °C

Supply current during program and erase cycles

RET

= 105 °C

RET

= 85 °C

= 105 °C

-40 ºC  T

 105 ºC

Years mA

1. Data based on characterization results, not tested in production.

2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte.

100/126 DocID027870 Rev 1

STLUX Electrical characteristics

12.3.6 I/O port pin characteristics

Subject to general operating conditions for V

DD input pins should not be left floating.

and T

A unless otherwise specified. Unused

Symbol

Table 83. Voltage DC characteristics

Description Min.

(1)

Typ.

Max.

(1)

OL1

OL2

OL3

OH1

OH2

OH3

Input low voltage

Input high voltage

(2)

Output low voltage at 3.3 V

(3)

(4)

Output low voltage at 5 V

Output high voltage at 5 V

Hysteresis input voltage

Pull-up resistor

(8)

Output low voltage high sink at 3.3 V / 5 V (2)

, (6)

Output high voltage at 3.3 V

Output high voltage high sink at 3.3 V / 5 V

, (7)

0.7 * V

-0.3

- 0.4

- 0.5

- 0.6

0.1 * V

0.3 * V

0.4

(5)

0.5

0.6

1. Data based on characterization result, not tested in production.

2. All signals are not 5 V tolerant (input signals can't be exceeded V

DDX

= V

, V

DDA

3. A high sink selectable by high speed configuration; the parameter applicable to signals: GPIO0 [5:0]

(product depending).

4. The parameter applicable to signals: GPIO1 [5:0]/PWM [5:0] (product depending).

5. Electrical threshold voltage not yet characterized at -40 ºC.

6. The parameter applicable to the signal: SWIM.

7. The parameter applicable to the signal: DIGIN [0]/CCO_clk.

8. Applicable to any digital inputs.

Unit

V k 

DocID027870 Rev 1 101/126

126

Electrical characteristics STLUX

Symbol

Table 84. Current DC characteristics

Description Min. Typ. Max.

(1)

Unit

OL1

OL2

OLhs1

OLhs2

OH1

OH2

OHhs1

OHhs2

LKg

_Inj

I_

Inj

Standard output low level current at 3.3 V and V

OL1

(2)

(3)

Standard output low level current at 5 V and V

OL2

High sink output low level current at 3.3 V and V

OL3

(4)

(5)

High sink output low level current at 5 V and V

OL3

(4) , (5)

Standard output high level current at 3.3 V and V

OH1

Standard output high level current at 5 V and V

OLH2

High sink output high level current at 3.3 V and V

High sink output high level current at 5 V and V

Input leakage current digital - analog V

 V

V

(6)

Injection current (7) , (8)

Total injection current (sum of all I/O and control pins)

1.5

7.75

1.5

7.75

± 1

± 4

± 20

1. Data based on characterization result, not tested in production.

2. A high sink selectable by high speed configuration; the parameter applicable to signals: GPIO0 [5:0] (product depending).

3. The parameter applicable to signals: GPIO1 [5:0]/PWM [5:0] (product depending).

4. The parameter applicable to the signal: SWIM.

5. The parameter applicable to the signal: DIGIN [0]/CCO_clk.

6. Applicable to any digital inputs.

7. Maximum value must never be exceeded.

8. Negative injection current on the ADCIN [7:0] signals (product depending) have to avoid since impact the ADC conversion accuracy.

µA mA

Symbol

Table 85. Operating frequency characteristics

Description Min.

Typ.

Max.

(1)

Unit f

IL1 f

IH1 f

IH2 f

OL1 f

OL2 f

OH1 f

OH2

Digital input signal operating frequency

(2)

(3)

Analog input signal operating frequency

(5)

(6)

(4)

High speed input signal operating frequency (7) , (8)

Standard output signal operating frequency with 50 pF max. load

High sink output signal operating frequency with 50 pF max. load

High speed output signal operating frequency with 50 pF max. load

NRST input low level voltage

(8)

128

1. Data based on characterization result, not tested in production.

2. A high sink selectable by high speed configuration; parameter applicable to signals: GPIO0 [5:0] (product depending).

3. The parameter applicable to the signal: SWIM.

4. The parameter applicable to signals: DIGIN [5:1] (product depending).

5. The parameter applicable to signals: GPIO0 [3:2] when configured as HSE_Oscin/Oscout.

6. The parameter applicable to any analog signals: ADCIN [7:0], CPP [3:0] and CPM3 (product depending).

7. The parameter applicable to signals: GPIO1 [5:0]/PWM [5:0] (product depending).

8. The parameter applicable to the signal: DIGIN [0]/CCO_clk.

MHz

102/126 DocID027870 Rev 1

STLUX Electrical characteristics

12.3.7 Typical output level curves

This section shows the typical output voltage level curves measured on a single output pin for the three pad family present in the STLUX family.

Standard pad

This pad is associated to the following signals: DIGIN [5:1], SWIM, GPIO0 [3:0], CPP [3:0],

CPM3 and ADCIN [7:0] when available.

Figure 22. V

standard pad at 3.3 V

Figure 23. V

standard pad at 3.3 V

DocID027870 Rev 1 103/126

126

Electrical characteristics

Figure 24. V

standard pad at 5 V

STLUX

Figure 25. V

standard pad at 5 V

104/126 DocID027870 Rev 1

STLUX Electrical characteristics

Fast pad

This pad is associated to the PWM [5:0] signals if the external pin is available.

Figure 26. V

fast pad at 3.3 V

Figure 27. V

fast pad at 3.3 V

DocID027870 Rev 1 105/126

126

Electrical characteristics

Figure 28. V

fast pad at 5 V

STLUX

Figure 29. V

fast pad at 5 V

106/126 DocID027870 Rev 1

STLUX Electrical characteristics

High speed pad

This pad is associated to the DIGIN [0] signals.

Figure 30. V

high speed pad at 3.3 V

Figure 31. V

high speed pad at 3.3 V

DocID027870 Rev 1 107/126

126

Electrical characteristics

Figure 32. V

high speed pad at 5 V

STLUX

Figure 33. V

high speed pad at 5 V

108/126 DocID027870 Rev 1

STLUX Electrical characteristics

Subject to general operating conditions for V

and T

unless otherwise specified.

Symbol

Table 86. NRST pin characteristics

Parameter Conditions Min.

(1)

IL(NRST)

IH(NRST)

OL(NRST)

PU(NRST) t

IFP(NRST) t

INFP(NRST) t

OP(NRST)

NRST input high level voltage

NRST output low level voltage

NRST not input filtered pulse

NRST pull-up resistor

(2)

NRST input filtered pulse (3)

NRST output filtered pulse

= 2 mA

1. Data based on characterization results, not tested in production.

2. The RPU pull-up equivalent resistor is based on a resistive transistor.

3. Data guaranteed by design, not tested in production.

-0.3

0.7 x V

500

Typ.

Max.

(1)

0.3 x V

+ 0.3

0.5

Unit

V k  ns

µs

12.3.9 I

C interface characteristics

Symbol

Table 87. I 2 C interface characteristics

Standard mode Fast mode

(1)

Parameter

Min.

(2)

Max.

(2)

Min.

(2)

Max.

(2)

Unit t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA)

t r(SCL) t f(SDA)

t f(SCL) t h(STA) t su(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time (V

= 3.3 to 5 V)

(4)

SDA and SCL fall time (V

= 3.3 to 5 V)

START condition hold time

Repeated START condition setup time

4.7

4.0

250

(3)

4.0

4.7

1000

300

1.3

0.6

100

0.6

900

300

µs ns

µs t su(STO)

STOP condition setup time 4.0

t w(STO:STA)

STOP to START condition time (bus free) 4.7

C b

Capacitive load for each bus line

(5)

1. f

MASTER

, must be at least 8 MHz to achieve maximum fast I

C speed (400 kHz).

2. Data based on standard I 2 C protocol requirement, not tested in production.

0.6

1.3

3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low time.

4. I 2 C multifunction signals require the high sink pad configuration and the interconnection of 1 K  pull-up resistances.

5. 50 pF is the maximum load capacitance value to meet the I

C std timing specifications.

µs

µs pF

DocID027870 Rev 1 109/126

126

Electrical characteristics STLUX

12.3.10 10-bit SAR ADC characteristics

Subject to general operating conditions for V

DDA specified.

, f

MASTER

, and T

unless otherwise

Symbol

Table 88. ADC characteristics

Parameter Conditions Min. Typ.

Max.

Unit

ADCIN f

ADC

IN1

IN2

V ref t

S t

STAB t t

CONV1

CONV2

Resolution

ADC input impedance

ADC Clock frequency

Conversion voltage range for gain x1

Conversion voltage range for gain x4 (4)

ADC main reference voltage

(5)

Sampling time

Wakeup time from ADC standby

Single conversion time including sampling time

Continuous conversion time including sampling time f

ADC

= 6 MHz f

ADC

= 6 MHz f

ADC

= 6 MHz

1.250

0.50

2.42

(1)

1.25

(2)

(3)

0.3125

(2) , (3)

bit

M 

MHz

1. Frequency generated selecting the PLL source clock.

2. Maximum input analog voltage cannot exceed V

DDA

3. Exceeding the maximum voltage on the ADCIN [7:0] signals (product depending) for the related conversion scale must be avoided since the ADC conversion accuracy can be impacted.

4. Product depending.

5. ADC reference voltage at T

= 25 °C.

µs

110/126 DocID027870 Rev 1

STLUX Electrical characteristics

ADC accuracy characteristics at V

/V

DDA

3.3 V

Symbol

Table 89. ADC accuracy characteristics at V

VDDA

3.3 V

Parameter Conditions

(1)

Typ.

(2)

Min.

(3)

Max.

(3)

Unit

| Total unadjusted error

(4)

(5)

(6)

| Gain error(

(7)

O+G

Offset + gain error

(8)

O+G

Offset + gain error

(9)

O+G

Offset + gain error

(10)

| Differential linearity error

| Integral linearity error

Total unadjusted error (4) , (5)

| Gain error

O+G

O+G

O+G

| Differential linearity error

Integral linearity error(

(5) , (6)

f f

ADC

= 6 MHz gain 1

= 6 MHz gain 4

(11)

2.8

0.3

0.4

0.5

1.4

2.8

0.3

0.4

0.5

1.4

-8.5

-11

-14.3

-12.7

-16.7

-19.2

9.3

11.3

15.5

18.8

LSB

1. Measured with RAIN < 10 k  (RAIN external series resistance interconnected between the AC signal generator and the

ADC input pin).

2. Temperature operating: T

= 25 °C.

3. Data based on characterization results, not tested in production.

4. ADC accuracy vs. negative injection current. Injecting negative current on any of the analog input pins should be avoided as this reduces the accuracy of the conversion being performed on another analog input. It is recommended a Schottky diode (pin to ground) to be added to standard analog pins which may potentially inject the negative current. Any positive injection current within the limits specified for I or V

IN2

INJ(PIN) and 

IINJ(PIN)

in the I/O port pin characteristic section does not affect the ADC accuracy. The ADC accuracy parameters may be also impacted exceeding the ADC maximum input voltage V

IN1

5. Results in manufacturing test mode.

6. Data aligned with trimming voltage parameters.

7. Gain error evaluation with the two point method.

8. Temperature operating range: 0 ºC  T

 85 ºC.

9. Temperature operating range: -25 ºC  T

 105 ºC.

10. Temperature operating range: -40 ºC  T

 105 ºC.

11. Product depending.

DocID027870 Rev 1 111/126

126

Electrical characteristics STLUX

ADC accuracy characteristics at V

/V

DDA

5 V

Symbol

Table 90. ADC accuracy characteristics at V

VDDA

5 V

Parameter Conditions

(1)

Typ.

(2)

Min.

(3)

Max.

(3)

Unit

| Total unadjusted error

(4)

(5)

(6)

| Offset error

| Gain error

, (7)

O+G

Offset + gain error

(8)

O+G

Offset + gain error

(9)

O+G

Offset + gain error

(10)

| Differential linearity error

Integral linearity error

Total unadjusted error (4)

| Offset error

| Gain error

O+G

Offset + gain error

(8)

O+G

Offset + gain error

O+G

Offset + gain error

(10)

| Differential linearity error

(4) , (5)

Integral linearity error

f f

ADC

= 6 MHz gain 1

= 6 MHz gain 4

(11)

TBD

0.5

0.4

0.8

2.0

TBD

1.2

0.2

0.8

2.0

-8.3

-10.9

-13.8

-12.2

-16.4

-18.8

8.9

10.9

15.3

18.5

LSB

1. Measured with RAIN < 10 k  (RAIN external series resistance interconnected between the AC signal generator and the

ADC input pin).

2. Temperature operating: T

= 25 °C.

3. Data based on characterization results, not tested in production.

4. ADC accuracy vs. negative injection current. Injecting negative current on any of the analog input pins should be avoided as this reduces the accuracy of the conversion being performed on another analog input. It is recommended a Schottky diode (pin to ground) to be added to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I

INJ(PIN)

and 

IINJ(PIN)

in the I/O port pin characteristic section does not affect the ADC accuracy. The ADC accuracy parameters may be also impacted exceeding the ADC maximum input voltage V or V

IN2

IN1

5. Results in manufacturing test mode.

6. Data aligned with trimming voltage parameters.

7. Gain error evaluation with the two point method.

8. Temperature operating range: 0 ºC  T

85 ºC.

9. Temperature operating range: -25 ºC  T

 105 ºC.

10. Temperature operating range: -40 ºC  T

 105 ºC.

11. Product depending.

112/126 DocID027870 Rev 1

STLUX Electrical characteristics

ADC equivalent input circuit

Figure 34

shows the ADC equivalent input circuit.

Figure 34. ADC equivalent input circuit

Note: Gain x1 ADC input analog voltage range is from 0 up to 1.25 V.

Gain x4 ADC input analog voltage range is from 0 up to 312.5 mV (product depending).

Maximum input analog voltage cannot exceed VDDA.

ADC input impedance > 1 M  .

The ADCIN [7:0] input pins (if available) are provided by the ESD protection diodes.

DocID027870 Rev 1 113/126

126

Electrical characteristics

ADC conversion accuracy

Figure 35. ADC conversion accuracy

STLUX

114/126

ADC accuracy parameter definitions:

 E

= total unadjusted error: maximum deviation between the actual and the ideal transfer curves.

 E

= offset error: deviation between the first actual transition and the first ideal one.

 E

= offset + gain error (1-point gain): deviation between the last ideal transition and the last actual one.

 E

= gain error (2-point gain): defined so that E

= E

O the deviation of the characteristic slope).

+ E

(parameter correlated to

 E

= differential linearity error: maximum deviation between actual steps and the ideal one.

 E

= integral linearity error: maximum deviation between any actual transition and the end-point correlation line.

DocID027870 Rev 1

STLUX Electrical characteristics

Symbol

Table 91. Analog comparator characteristics (1)

Parameter Conditions Min.

(2)

Typ.

Max.

(2)

Unit

CPP

CPM3

Comparator input voltage range

Comparator 3 external input voltage range

-40 ºC  T

 105 ºC 0

1.23

(4)

V offset t

COMP

Input capacitance

Comparator offset error

Comparison delay time

(5)

(6)

1. The comparator logic accuracy parameters may be also impacted exceeding the VCPP and VCPM3 maximum input voltage.

2. Data based on characterization results, not tested in production.

3. Maximum analog input voltage cannot exceed V

DDA

4. The comparator 3 can be configured with the external reference voltage signal CPM3.

5. The overdrive voltage is ± 50 mV.

6. This parameter doesn't consider the delay time of comparator signal synchronization stages and SMED logic.

pF mV ns

Symbol Parameter

Table 92. DAC characteristics

Conditions Min.

(1)

V full scale

V offset

V dac

LSB

INL

Resolution

DAC full scale

DAC offset

DAC out voltage

Integral non linearity

-40 ºC  T

 105 ºC

1. Data based on characterization results, not tested in production.

1.2

V offset

Typ.

Max.

(1)

1.26

V full scale

0.12

Unit bit

V mV mV mV

LSB

Equation 5

DocID027870 Rev 1 115/126

126

Electrical characteristics

Equation 6 where:

 Vf ullscale

= V fullscale

(sample, T)

 V offset

= Voffset (sample, T)

 INL = INL (sample, n)

STLUX

Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts * (n + 1) supply pin).

Symbol

Table 93. ESD absolute maximum ratings

Ratings Conditions

Maximum value

Unit

ESD(HBM)

ESD(CDM)

ESD(MM)

Electrostatic discharge voltage

(human body model)

Electrostatic discharge voltage

(charge device model)

Electrostatic discharge voltage

(machine model)

= 25 °C, conforming to

JEDEC/JESD22-A114E

= 25 °C, conforming to

ANSI/ESD STM 5.3.1 ESDA

= 25 °C, conforming to

JEDEC/JESD-A115-A

2000

500

200

Data based on characterization results, not tested in production.

Two complementary static tests are required on 10 parts to assess the latch-up performance.

A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard.

Symbol

Table 94. Electrical sensitivity

Parameter Conditions

Static latch-up class T

= 105 °C

Level

116/126 DocID027870 Rev 1

STLUX Thermal characteristics

STLUX functionality cannot be guaranteed when the device operating exceeds the maximum chip junction temperature (T

Jmax

, in degrees Celsius, may be calculated using

Equation 7

Equation 7

Jmax

= T

Amax

+ PD max

x 

) where:

Amax is the maximum ambient temperature in °C

 J

is the package junction to ambient thermal resistance in °C/W

Dmax

is the sum of P

INTmax and P

I/Omax

Dmax

= P

INTmax

+ PI/O max)

INTmax power.

is the product of I

and V

, expressed in watts. This is the maximum chip internal

I/Omax

I/Omax

represents the maximum power dissipation on output pins where:

= (V

* I

) +  [(V

- V

) * I

], taking into account the actual V

OL and V

of the I/Os at low and high level.

Table 95. Package thermal characteristics

Symbol Parameter Value Unit



TSSOP38 - Thermal resistance junction to ambient

(1)

VFQFPN32 - Thermal resistance junction to ambient

TSSOP28 - Thermal resistance junction to ambient