STMicroelectronics SR5E1E5 Reference Manual

RM0483
Reference manual
SR5E1x 32-bit Arm® Cortex®-M7 architecture microcontroller for
electrical vehicle applications
Overview
This document defines the functionality of the SR5E1x microcontroller for use by software
and hardware developers. The SR5E1x is built on Arm® architecture technology and
integrates technologies that are important for today’s and tomorrow’s electrical vehicle
applications.
SR5E1x applications include, amongst possible others:
• On-board charger
• DC/DC converters
• Traction inverter
• Advanced control motor
The information in this book is subject to change without notice, as described in the
disclaimer. As with any technical documentation, it is the reader’s responsibility to be sure
he or she is using the most recent version of the documentation.
To locate any published errata or updates for this document, visit the ST Web site at
http://www.st.com.
Audience
This manual is intended for system software and hardware developers and applications
programmers who want to develop products with the SR5E1x device. It is assumed that the
reader understands operating systems, microprocessor system design, basic principles of
software and hardware, and basic details of the Arm® architecture.
October 2024
RM0483 Rev 5
1/2075
www.st.com
1
Contents
RM0483
Contents
1
2
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
1.1
Document organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
1.2
Register conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
1.3
Acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
1.4
Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.1
3
5
2.1.1
Cortex®-M7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.1.2
Cortex®-M0+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.1.3
Memory hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.3
Features list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
System and memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.1
4
Overall architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.1.1
TCM buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.1.2
CPU buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.1.3
Bus master peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.1.4
TCM memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.2
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.3
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.4
Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.1
Production packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.2
Package pinouts and ballouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.1
Core modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.2
System modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.2.1
2/2075
Interconnect / bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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5.3
5.4
5.5
5.6
5.7
5.8
5.2.2
Hardware semaphore (HSEM2) configuration . . . . . . . . . . . . . . . . . . . . 85
5.2.3
System Memory Protection Unit (SMPU) configuration . . . . . . . . . . . . . 85
5.2.4
Nested Vectored Interrupt Controller configuration . . . . . . . . . . . . . . . . 86
5.2.5
EXTI configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.2.6
DMA controllers configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.2.7
DMA request multiplexer (DMAMUX) configuration . . . . . . . . . . . . . . . . 99
5.2.8
GPIO configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Memories and memory interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.3.1
Non-volatile memory platform controller (NVMPC) configuration . . . . 103
5.3.2
Platform RAM controller (PRAMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Analog modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.4.1
Temperature sensor configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.4.2
ADCx configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.4.3
SDADC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.4.4
DAC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.4.5
Comparator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
5.5.1
HRTIMx configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.5.2
TIMx timer overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.5.3
TIM1/TIM8 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.5.4
TIM2/TIM3/TIM4/TIM5 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.5.5
TIM15/TIM16 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.5.6
Timestamp timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.5.7
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.5.8
System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.5.9
RTC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.6.1
CAN subsystem configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.6.2
SPI configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.6.3
UART configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.6.4
I2C configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Reset and boot modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.7.1
Boot Assist Firmware (BAF) configuration . . . . . . . . . . . . . . . . . . . . . . 130
5.7.2
System Status and Configuration Module (SSCM) configuration . . . . 130
Safety modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.8.1
Cyclic Redundancy Check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
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Memory Error Management Unit (MEMU2) . . . . . . . . . . . . . . . . . . . . . 131
5.8.3
Indirect memory access (IMA) configuration . . . . . . . . . . . . . . . . . . . . 133
5.8.4
Fault Collection & Control Unit (FCCU) configuration . . . . . . . . . . . . . 135
5.8.5
CEM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.8.6
REG_PROT configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.8.7
STCU configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
5.8.8
ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Reset and Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.1
6.2
6.3
4/2075
5.8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.1.1
TEST flash memory block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.1.2
UTEST flash memory block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.1.3
Boot Assist Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Modules used in reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.2.1
Power Management Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.2.2
Reset and Clock Control Module (RCC) . . . . . . . . . . . . . . . . . . . . . . . 164
6.2.3
System Status and Configuration Module . . . . . . . . . . . . . . . . . . . . . . 165
6.2.4
Self-Test Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
6.3.1
Power-on and the Reset Generation Module . . . . . . . . . . . . . . . . . . . 165
6.3.2
Power-up phase: power stabilization . . . . . . . . . . . . . . . . . . . . . . . . . . 168
6.3.3
PHASE0 Phase: analog supply initial configuration . . . . . . . . . . . . . . 169
6.3.4
PHASE1[DEST] Phase: temporization setup . . . . . . . . . . . . . . . . . . . 169
6.3.5
PHASE2[DEST] Phase: flash initial configuration . . . . . . . . . . . . . . . . 169
6.3.6
PHASE3[DEST] Phase: device configuration . . . . . . . . . . . . . . . . . . . 170
6.3.7
IDLE[DEST] Phase: self-test execution . . . . . . . . . . . . . . . . . . . . . . . . 171
6.3.8
PHASE1[FUNC] Phase: temporization setup . . . . . . . . . . . . . . . . . . . 171
6.3.9
PHASE2[FUNC] Phase: flash initial configuration . . . . . . . . . . . . . . . . 172
6.3.10
PHASE3[FUNC] Phase: device configuration monitoring . . . . . . . . . . 172
6.3.11
IDLE[FUNC] Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
6.3.12
System start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
6.3.13
Waking-up the other CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.3.14
BAF serial bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.4
RESETN pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.5
Reset Sources Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.5.1
Destructive Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.5.2
Functional Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
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6.6
7
6.5.3
Functional reset escalation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.5.4
Destructive Reset Escalation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
RAM preservation upon reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Device configuration format (DCF) records . . . . . . . . . . . . . . . . . . . . 183
7.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
7.2
DCF clients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
7.3
DCF records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
7.3.1
7.4
8
DCF client table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.4.1
DCF client list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
7.4.2
Miscellaneous DCF records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.4.3
RCC DCF records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
8.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
8.1.1
Power management framework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
8.1.2
Power management supply description . . . . . . . . . . . . . . . . . . . . . . . . 209
8.1.3
Power management controller overview . . . . . . . . . . . . . . . . . . . . . . . 210
8.2
Flash power requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
8.3
Device trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
8.4
Supply monitoring (POR and LVDs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
8.5
9
UTEST DCF records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
8.4.1
Power-on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
8.4.2
Behavior of device LVD / HVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
8.4.3
Voltage detections (MVDs, LVDs, HVDs, UVDs) . . . . . . . . . . . . . . . . . 214
Power sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
8.5.1
Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
8.5.2
Power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
8.5.3
Brown-out management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
8.5.4
Low voltage requirement during crank . . . . . . . . . . . . . . . . . . . . . . . . . 224
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
9.1
Basic security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
9.2
Advanced security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
9.3
Detailed security information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
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Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
10.1
Debug and trace architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
10.2
Debug infrastructure features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
10.3
Debug access port functional description . . . . . . . . . . . . . . . . . . . . . . . . 228
10.3.1
Serial-wire and JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . 228
10.3.2
Access ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
10.4
NIC ports related to debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
10.5
Global timestamp generator (TSG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
10.6
Cross trigger interfaces (CTI) and matrix (CTM) . . . . . . . . . . . . . . . . . . 229
10.6.1
Embedded trace FIFO (ETF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
10.7
Trace port interface unit (TPIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
10.8
Cortex-M7 debug functional description . . . . . . . . . . . . . . . . . . . . . . . . . 231
10.9
Debug configuration in lockstep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
10.10 Additional requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
10.10.1 Capability of the debugger host to connect under system reset . . . . . 232
10.10.2 Capability to control debug features of cores and IPs . . . . . . . . . . . . . 233
10.10.3 Debug protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
10.11 DBGMCU module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
10.12 DBGMCU Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
10.13 DBGMCU register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
11
Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
11.1
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
11.2
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
11.2.1
External oscillator (XOSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
11.2.2
Internal RC oscillator (IRCOSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
11.2.3
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
11.2.4
Low speed internal RC oscillator (LSIRCOSC) . . . . . . . . . . . . . . . . . . 263
11.2.5
System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
11.2.6
System clock switching to IRCOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
11.2.7
ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
11.2.8
RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
11.2.9
LSICLK clock branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
11.2.10 Timer clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
11.2.11
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Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
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11.2.12 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
11.2.13 Internal/external clock measurement with TIM5/TIM15/TIM16 . . . . . . 265
11.2.14 Peripheral clock enable register
(RCC_AHBxENR, RCC_APBxENR) . . . . . . . . . . . . . . . . . . . . . . . . . . 267
11.3
11.4
12
Clock monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
11.3.1
CMU configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
11.3.2
PLL0 monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
11.3.3
External oscillator (XOSC) monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
11.3.4
Internal RC oscillator (IRCOSC) monitor . . . . . . . . . . . . . . . . . . . . . . . 270
11.3.5
System clock monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
11.3.6
Progressive system clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
11.4.1
Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
11.4.2
Core Sleep mode (CSleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
11.5
RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
11.6
RCC register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Dual PLL digital interface (PLLDIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
12.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
12.2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
12.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
12.4
Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
12.4.1
12.5
12.6
12.7
13
Normal mode with reference, PLL0 or both PLLs enabled . . . . . . . . . 329
Memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
12.5.1
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
12.5.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
12.5.3
Register classification for safety requirements . . . . . . . . . . . . . . . . . . 339
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
12.6.1
Input clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
12.6.2
Clock configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
12.6.3
Frequency modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Clock Monitor Unit (CMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
13.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
13.1.1
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
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13.2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
13.3
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
13.4
Memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
13.4.1
13.5
14
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
13.5.1
Frequency meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
13.5.2
CLKMN0_RMT supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
13.5.3
CLKMN1 supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Power management controller digital interface (PMC_Dig) . . . . . . . 353
14.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
14.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
14.2.1
Standard features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
14.3
IPS bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
14.4
Memory map/register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
14.5
Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
14.5.1
Event Pending Register (EPR_LV0) . . . . . . . . . . . . . . . . . . . . . . . . . . 358
14.5.2
Reset Event Enable Register (REE_LV0) . . . . . . . . . . . . . . . . . . . . . . 360
14.5.3
Reset Event Select Register (RES_LV0) . . . . . . . . . . . . . . . . . . . . . . . 361
14.5.4
Interrupt Enable (IE_LV0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
14.5.5
FCCU Event Enable Register (FEE_LV0) . . . . . . . . . . . . . . . . . . . . . . 365
14.5.6
Event Pending Register (EPR_LV1) . . . . . . . . . . . . . . . . . . . . . . . . . . 366
14.5.7
Reset Event Enable Register (REE_LV1) . . . . . . . . . . . . . . . . . . . . . . 367
14.5.8
Reset Event Select Register (RES_LV1) . . . . . . . . . . . . . . . . . . . . . . . 368
14.5.9
Interrupt Enable (IE_LV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
14.5.10 FCCU Event Enable Register (FEE_LV1) . . . . . . . . . . . . . . . . . . . . . . 370
14.5.11 Event Pending Register (EPR_HV0) . . . . . . . . . . . . . . . . . . . . . . . . . . 371
14.5.12 Reset Event Enable Register (REE_HV0) . . . . . . . . . . . . . . . . . . . . . . 373
14.5.13 Reset Event Select Register (RES_HV0) . . . . . . . . . . . . . . . . . . . . . . 376
14.5.14 Interrupt Enable (IE_HV0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
14.5.15 FCCU Event Enable Register (FEE_HV0) . . . . . . . . . . . . . . . . . . . . . . 380
14.5.16 Supply Gauge Status Register (GR_S) . . . . . . . . . . . . . . . . . . . . . . . . 382
14.5.17 Pending Gauge Status Register (GR_P) . . . . . . . . . . . . . . . . . . . . . . . 387
14.5.18 Global Interrupt Enable Register (IE_G) . . . . . . . . . . . . . . . . . . . . . . . 389
14.5.19 HPREG SMPS SELECT STATUS (HPREG_SMPS_SEL_S) . . . . . . . 391
14.5.20 Event Pending Register (EPR_TD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
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14.5.21 Reset Event Enable Register (REE_TD) . . . . . . . . . . . . . . . . . . . . . . . 393
14.5.22 Reset Event Select Register (RES_TD) . . . . . . . . . . . . . . . . . . . . . . . 394
14.5.23 Temperature Sensor Configuration Register (CTL_TD) . . . . . . . . . . . 395
14.5.24 Temperature Sensor FCCU Event Enable Register (FEE_TD) . . . . . . 396
14.5.25 BIST Mask Status register (BIST_MASK_STATUS) . . . . . . . . . . . . . . 397
14.5.26 User BIST Flags Phase1 register (BIST_FLAGS_PHASE1) . . . . . . . . 398
14.5.27 User BIST Flags Phase2 register (BIST_FLAGS_PHASE2) . . . . . . . . 399
14.5.28 User BIST Control register (BIST_CTRL) . . . . . . . . . . . . . . . . . . . . . . 400
14.5.29 User BIST Time1 and Time0 register (BIST_TIME10) . . . . . . . . . . . . . 401
14.5.30 User BIST Time3 and Time2 register (BIST_TIME32) . . . . . . . . . . . . . 402
14.5.31 User BIST Time6 and Time5 register (BIST_TIME65) . . . . . . . . . . . . . 403
14.5.32 User BIST VD Under Test Monitor register (BIST_DEBUG) . . . . . . . . 403
15
14.6
Temperature Sensor Interface Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
14.7
Power On Reset (RCC Phase Gates) . . . . . . . . . . . . . . . . . . . . . . . . . . 404
14.8
Flash interface (DCF client usage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
14.9
Voltage monitor BIST programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Platform RAM controller AXI (PRAMC_AXI) . . . . . . . . . . . . . . . . . . . . 408
15.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
15.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
15.3
Memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . 410
15.4
15.3.1
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
15.3.2
Register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
15.4.1
15.5
Initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
15.6
Safety considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
15.7
15.6.1
Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
15.6.2
MEMU2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
15.6.3
Memory feedback monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Exclusive monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
15.7.1
16
Read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Support for Exclusive monitor behavior . . . . . . . . . . . . . . . . . . . . . . . . 419
Non volatile memory platform controller (NVMPC) . . . . . . . . . . . . . . 421
16.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
16.1.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
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16.1.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
16.2
Block interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
16.3
Memory map and register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
16.4
16.3.1
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
16.3.2
NVM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
AXI4 global/read data/read address interface . . . . . . . . . . . . . . . . . . . . 430
16.4.1
16.5
Non-volatile-memory read interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
16.5.1
16.6
16.9
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
Non-volatile-memory write interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
16.7.1
16.8
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
AXI4 write data/write address/write response interface . . . . . . . . . . . . . 432
16.6.1
16.7
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
16.8.1
AXI4 read slave controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
16.8.2
AXI4 write slave controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
16.9.1
End2End ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
16.9.2
Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
16.10 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
16.10.1 Read NVM access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
16.10.2 Data flash management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
16.11 Over The Air (OTA-X1) support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
16.11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
16.11.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
17
Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
17.1
17.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
17.1.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
17.1.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
17.1.3
Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
Flash memory map and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
17.2.1
17.3
10/2075
Flash array memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Register memory maps and descriptions . . . . . . . . . . . . . . . . . . . . . . . . 453
17.3.1
Register memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
17.3.2
User register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
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17.4
18
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
17.4.1
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
17.4.2
Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
17.4.3
Modify mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
17.4.4
Alternate program and erase interface . . . . . . . . . . . . . . . . . . . . . . . . 524
17.4.5
User Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
17.4.6
Protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
Boot assist flash (BAF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
18.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
18.2
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
18.2.1
18.3
18.4
19
BAF image header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
18.3.1
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
18.3.2
Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
18.3.3
Flow of control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
18.3.4
Optionally wait for HSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
18.3.5
Initialization of BAF DCF clients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
18.3.6
Production disable activation protocol and implementation . . . . . . . . . 541
18.3.7
TDM diary operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
18.3.8
Optionally perform a serial boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
18.3.9
Serial boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
Resources accessed by BAF code execution . . . . . . . . . . . . . . . . . . . . 549
System status and configuration module (SSCM) . . . . . . . . . . . . . . . 551
19.1
19.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
19.1.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
19.1.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
19.1.3
Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
Memory map and registers definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
19.2.1
19.3
19.4
Registers descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
19.3.1
DCF mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
19.3.2
ECC error monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
19.3.3
Life Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
Initialization and application information . . . . . . . . . . . . . . . . . . . . . . . . . 561
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19.4.1
19.5
Additional safety measures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
19.5.1
20
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
Spurious reset protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
20.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
20.2
GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
20.3
GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
20.3.1
General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
20.3.2
I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 564
20.3.3
I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
20.3.4
I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
20.3.5
I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
20.3.6
GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
20.3.7
I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
20.3.8
External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
20.3.9
Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
20.3.10 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
20.3.11 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
20.3.12 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
20.3.13 Safe Mode Configuration (SMC) of GPIOs . . . . . . . . . . . . . . . . . . . . . 569
20.4
12/2075
GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
20.4.1
GPIO memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
20.4.2
Mode register (MODER)
(x =A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
20.4.3
Output type register (OTYPER)
(x = A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
20.4.4
Output speed register (OSPEEDR)
(x = A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
20.4.5
Pull-up/pull-down register (PUPDR)
(x = A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
20.4.6
Input data register (IDR)
(x = A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
20.4.7
Output data register (ODR)
(x = A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
20.4.8
Bit set/reset register (BSRR)
(x = A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
20.4.9
Configuration lock register (LCKR)
(x = A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
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20.4.10 Alternate function low register (AFRL)
(x = A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
20.4.11 Alternate function high register (AFRH)
(x = A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
20.4.12 Port Hysteresis Register (IHYSTR)
(x = A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
20.4.13 Port Input Buffer Enable Register (TRIGENR)
(x = A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
20.4.14 Safe IO Selection Register (SAFESELR)
(x = A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
20.4.15 Safe IO Output Value Register (SAFEVALR)
(x = A to I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
21
22
System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 579
21.1
SYSCFG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
21.2
SYSCFG Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
21.3
SYSCFG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
System memory protection unit (SMPU) . . . . . . . . . . . . . . . . . . . . . . . 598
22.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
22.2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
22.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
22.4
Memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
22.5
23
22.4.1
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
22.4.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
22.5.1
Access evaluation macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
22.5.2
Putting it all together and error terminations . . . . . . . . . . . . . . . . . . . . 611
22.6
Initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .611
22.7
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .611
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 614
23.1
DMA introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
23.2
DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
23.3
DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
23.3.1
DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
23.3.2
DMA internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
23.3.3
DMA overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
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23.3.4
DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
23.3.5
DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
23.3.6
Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
23.3.7
DMA streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
23.3.8
Source, destination and transfer modes . . . . . . . . . . . . . . . . . . . . . . . 618
23.3.9
Pointer incrementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
23.3.10 Circular mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
23.3.11 Double-buffer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
23.3.12 Programmable data width, packing/unpacking, endianness . . . . . . . . 624
23.3.13 Single and burst transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
23.3.14 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
23.3.15 DMA transfer completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
23.3.16 DMA transfer suspension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
23.3.17 Flow controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
23.3.18 Summary of the possible DMA configurations . . . . . . . . . . . . . . . . . . . 632
23.3.19 Stream configuration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
23.3.20 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
23.4
DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
23.5
DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
23.5.1
DMA memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
23.5.2
DMA low interrupt status register (DMA_LISR) . . . . . . . . . . . . . . . . . . 635
23.5.3
DMA high interrupt status register (DMA_HISR) . . . . . . . . . . . . . . . . . 636
23.5.4
DMA low interrupt flag clear register (DMA_LIFCR) . . . . . . . . . . . . . . 637
23.5.5
DMA high interrupt flag clear register (DMA_HIFCR) . . . . . . . . . . . . . 637
23.5.6
DMA stream x configuration register (DMA_SxCR) . . . . . . . . . . . . . . . 638
23.5.7
DMA stream x number of data register (DMA_SxNDTR) . . . . . . . . . . 641
23.5.8
DMA stream x peripheral address register (DMA_SxPAR) . . . . . . . . . 642
23.5.9
DMA stream x memory 0 address register
(DMA_SxM0AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
23.5.10 DMA stream x memory 1 address register
(DMA_SxM1AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
23.5.11 DMA stream x FIFO control register (DMA_SxFCR) . . . . . . . . . . . . . . 643
24
14/2075
DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . 645
24.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
24.2
DMAMUX main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
24.3
DMAMUX functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
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24.3.1
DMAMUX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
24.3.2
DMAMUX signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
24.3.3
DMAMUX channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
24.3.4
DMAMUX request line multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
24.3.5
DMAMUX request generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
24.4
DMAMUX interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
24.5
DMAMUX registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
24.5.1
DMAMUX memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
24.5.2
DMAMUX request line multiplexer channel x configuration register
(DMAMUX_CxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
24.5.3
DMAMUX request line multiplexer interrupt channel status register
(DMAMUX_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
24.5.4
DMAMUX request line multiplexer interrupt clear flag register
(DMAMUX_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
24.5.5
DMAMUX request generator channel x configuration register
(DMAMUX_RGxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
24.5.6
DMAMUX request generator interrupt status register
(DMAMUX_RGSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
24.5.7
DMAMUX request generator interrupt clear flag register
(DMAMUX_RGCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . 657
25.1
NVIC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
25.2
SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . 658
26.1
EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
26.2
EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
26.2.1
26.3
EXTI connections between peripherals and CPU . . . . . . . . . . . . . . . . 659
EXTI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
26.3.1
EXTI configurable event input CPU wakeup . . . . . . . . . . . . . . . . . . . . 660
26.3.2
EXTI configurable event input Any wakeup . . . . . . . . . . . . . . . . . . . . . 661
26.3.3
EXTI direct event input CPU wakeup . . . . . . . . . . . . . . . . . . . . . . . . . 662
26.3.4
EXTI direct event input Any wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . 664
26.4
EXTI event input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
26.5
EXTI functional behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
26.5.1
EXTI CPU interrupt procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
26.5.2
EXTI CPU event procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
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26.5.3
26.6
EXTI software interrupt/event trigger procedure . . . . . . . . . . . . . . . . . 666
EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
26.6.1
EXTI memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
26.6.2
Rising trigger selection register (RTSR1) . . . . . . . . . . . . . . . . . . . . . . 667
26.6.3
Falling trigger selection register (FTSR1) . . . . . . . . . . . . . . . . . . . . . . 668
26.6.4
Software interrupt event register (SWIER1) . . . . . . . . . . . . . . . . . . . . 669
26.6.5
Rising trigger selection register (RTSR2) . . . . . . . . . . . . . . . . . . . . . . 669
26.6.6
Falling trigger selection register (FTSR2) . . . . . . . . . . . . . . . . . . . . . . 670
26.6.7
Software interrupt event register (SWIER2) . . . . . . . . . . . . . . . . . . . . 670
26.6.8
Interrupt mask register (CnIMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
26.6.9
Event mask register (CnEMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
26.6.10 Pending register (CnPR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
26.6.11 Interrupt mask register (CnIMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
26.6.12 Event mask register (CnEMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
26.6.13 Pending register (CnPR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
27
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . 675
27.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
27.2
CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
27.3
CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
27.4
28
27.3.1
CRC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
27.3.2
CRC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
27.3.3
CRC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
27.4.1
CRC memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
27.4.2
CRC data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
27.4.3
CRC independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . 678
27.4.4
CRC control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
27.4.5
CRC initial value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
27.4.6
CRC polynomial (CRC_POL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
CORDIC coprocessor (CORDIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
28.1
CORDIC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
28.2
CORDIC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
28.3
CORDIC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
28.3.1
16/2075
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
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28.4
29
28.3.2
CORDIC functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
28.3.3
Fixed point representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
28.3.4
Scaling factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
28.3.5
Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
28.3.6
Zero-overhead mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
28.3.7
Polling mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
28.3.8
Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
28.3.9
DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
CORDIC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
28.4.1
CORDIC memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
28.4.2
CORDIC control/status register (CORDIC_CSR) . . . . . . . . . . . . . . . . 695
28.4.3
CORDIC argument register (CORDIC_WDATA) . . . . . . . . . . . . . . . . . 697
28.4.4
CORDIC result register (CORDIC_RDATA) . . . . . . . . . . . . . . . . . . . . . 698
Analog-to-digital converters (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
29.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
29.2
ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
29.3
ADC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
29.4
ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
29.4.1
ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
29.4.2
ADC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
29.4.3
ADC clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
29.4.4
Slave AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
29.4.5
ADC Deep-power-down mode (DEEPPWD) and ADC voltage
regulator (ADVREGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
29.4.6
Single-ended and differential input channels . . . . . . . . . . . . . . . . . . . . 706
29.4.7
Calibration (ADCAL, ADCALDIF, ADC_CALFACT) . . . . . . . . . . . . . . . 707
29.4.8
ADC on-off control (ADEN, ADDIS, ADRDY) . . . . . . . . . . . . . . . . . . . . 710
29.4.9
Constraints when writing the ADC control bits . . . . . . . . . . . . . . . . . . . 711
29.4.10 Channel selection (SQRx, JSQRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
29.4.11 Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . . 712
29.4.12 Single conversion mode (CONT = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 714
29.4.13 Continuous conversion mode (CONT = 1) . . . . . . . . . . . . . . . . . . . . . . 715
29.4.14 Starting conversions (ADSTART, JADSTART) . . . . . . . . . . . . . . . . . . . 715
29.4.15 ADC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
29.4.16 Stopping an ongoing conversion (ADSTP, JADSTP) . . . . . . . . . . . . . . 717
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29.4.17 Conversion on external trigger and trigger polarity
(EXTSEL, EXTEN,JEXTSEL, JEXTEN) . . . . . . . . . . . . . . . . . . . . . . . 719
29.4.18 Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
29.4.19 Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . . . . . . . . . 722
29.4.20 Queue of context for injected conversions . . . . . . . . . . . . . . . . . . . . . . 723
29.4.21 Programmable resolution (RES) - fast conversion mode . . . . . . . . . . 731
29.4.22 End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . 732
29.4.23 End of conversion sequence (EOS, JEOS) . . . . . . . . . . . . . . . . . . . . . 732
29.4.24 Timing diagrams example (Single/Continuous modes,
hardware/software triggers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
29.4.25 Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
29.4.26 Dynamic low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
29.4.27 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL,
AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) . . . . . 746
29.4.28 Oversampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
29.4.29 Dual ADC modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
30
29.5
ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
29.6
ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
29.6.1
ADC register memory map (for each ADC) . . . . . . . . . . . . . . . . . . . . . 772
29.6.2
ADC common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
Sigma-delta analog-to-digital converter
(SDADC) digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
30.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
30.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
30.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
30.4
Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
30.5
30.4.1
Differential input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
30.4.2
Single-ended input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
30.4.3
External modulator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
External signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
30.5.1
30.6
30.7
Memory map and register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .811
30.6.1
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
30.6.2
Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
30.7.1
18/2075
Detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
Differential input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
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30.7.2
Single-ended input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
30.7.3
External modulator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
30.7.4
Low consumption mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
30.7.5
Analog input multiplexing and bias support . . . . . . . . . . . . . . . . . . . . . 829
30.7.6
Programmable gain and decimation rate . . . . . . . . . . . . . . . . . . . . . . . 829
30.7.7
SD ADC Internal Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
30.7.8
High-pass filter support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
30.7.9
Data conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
30.7.10 Hardware triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
30.7.11 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
30.7.12 Interrupt/DMA request support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
30.7.13 Gain calibration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
30.7.14 Offset calibration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837
30.7.15 Global gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837
30.7.16 Timestamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838
30.8
Initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838
30.8.1
31
Data conversion step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
31.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
31.2
DAC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
31.3
DAC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
31.4
DAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
31.4.1
DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
31.4.2
DAC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
31.4.3
DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
31.4.4
DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
31.4.5
DAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
31.4.6
DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
31.4.7
DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
31.4.8
DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
31.4.9
DAC noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
31.4.10 DAC triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
31.4.11 DAC sawtooth wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
31.4.12 DAC channel modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856
31.4.13 DAC channel buffer calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859
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31.4.14 Dual DAC channel conversion modes (if dual channels are
available) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
31.5
DAC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
31.6
DAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
31.7
DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866
31.7.1
DAC memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866
31.7.2
DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
31.7.3
DAC software trigger register (DAC_SWTRGR) . . . . . . . . . . . . . . . . . 870
31.7.4
DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
31.7.5
DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
31.7.6
DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
31.7.7
DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
31.7.8
DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
31.7.9
DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
31.7.10 Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
31.7.11 Dual DAC 12-bit left aligned data holding register
(DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
31.7.12 Dual DAC 8-bit right aligned data holding register
(DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
31.7.13 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 876
31.7.14 DAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . . 876
31.7.15 DAC status register (DAC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
31.7.16 DAC calibration control register (DAC_CCR) . . . . . . . . . . . . . . . . . . . 878
31.7.17 DAC mode control register (DAC_MCR) . . . . . . . . . . . . . . . . . . . . . . . 879
31.7.18 DAC channel1 sample and hold sample time register
(DAC_SHSR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
31.7.19 DAC channel2 sample and hold sample time register
(DAC_SHSR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
31.7.20 DAC sample and hold time register (DAC_SHHR) . . . . . . . . . . . . . . . 881
31.7.21 DAC sample and hold refresh time register (DAC_SHRR) . . . . . . . . . 882
31.7.22 DAC channel1 sawtooth register (DAC_STR1) . . . . . . . . . . . . . . . . . . 883
31.7.23 DAC channel2 sawtooth register (DAC_STR2) . . . . . . . . . . . . . . . . . . 883
31.7.24 DAC sawtooth mode register (DAC_STMODR) . . . . . . . . . . . . . . . . . 884
20/2075
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Contents
Comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
32.1
COMP introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
32.2
COMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
32.2.1
COMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
32.2.2
COMP pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
32.2.3
COMP reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
32.2.4
COMP LOCK mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
32.2.5
COMP hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
32.2.6
COMP output blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
32.3
COMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
32.4
COMP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
32.5
COMP_Dig registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
32.5.1
COMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
32.5.2
Comparator x control and status register (COMP_CxCSR) . . . . . . . . 891
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
33.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
33.1.1
33.2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
33.2.1
33.3
34
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
Linear temperature sensor (analog output generation) . . . . . . . . . . . . 893
Temperature formula . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
33.3.1
Equations for converting TSENS voltages to junction temperature . . . 894
33.3.2
Equations for converting TSENS voltages into constant reference
(Digital Bandgap Voltage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
High-resolution timer (HRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
34.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
34.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
34.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
34.3.1
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
34.3.2
HRTIM pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
34.3.3
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902
34.3.4
Timer A..F timing units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
34.3.5
Master timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
34.3.6
Up-down counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928
34.3.7
Set/reset event priorities and narrow pulse management . . . . . . . . . . 935
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34.3.8
External events global conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
34.3.9
External event filtering in timing units . . . . . . . . . . . . . . . . . . . . . . . . . 944
34.3.10 Delayed protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
34.3.11 Register preload and update management . . . . . . . . . . . . . . . . . . . . . 956
34.3.12 PWM mode with “greater than” comparison . . . . . . . . . . . . . . . . . . . . 960
34.3.13 Events propagation within or across multiple timers . . . . . . . . . . . . . . 961
34.3.14 Output management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966
34.3.15 Burst mode controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
34.3.16 Chopper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976
34.3.17 Fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
34.3.18 Auxiliary outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
34.3.19 Synchronizing the HRTIM with other timers or HRTIM instances . . . . 984
34.3.20 ADC triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987
34.3.21 DAC triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
34.3.22 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
34.3.23 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997
34.3.24 HRTIM initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
34.3.25 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002
34.4
34.5
Application use cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
34.4.1
Buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
34.4.2
Buck converter with synchronous rectification . . . . . . . . . . . . . . . . . . 1004
34.4.3
Multiphase converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005
34.4.4
Transition mode power factor correction . . . . . . . . . . . . . . . . . . . . . . 1006
HRTIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
34.5.1
HRTIM register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
34.5.2
HRTIM master timer control register (HRTIM_MCR) . . . . . . . . . . . . . 1014
34.5.3
HRTIM master timer interrupt status register (HRTIM_MISR) . . . . . . 1017
34.5.4
HRTIM master timer interrupt clear register (HRTIM_MICR) . . . . . . . 1018
34.5.5
HRTIM master timer DMA interrupt enable register
(HRTIM_MDIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
34.5.6
HRTIM master timer counter register (HRTIM_MCNTR) . . . . . . . . . . 1020
34.5.7
HRTIM master timer period register (HRTIM_MPER) . . . . . . . . . . . . 1021
34.5.8
HRTIM master timer repetition register (HRTIM_MREP) . . . . . . . . . . 1021
34.5.9
HRTIM master timer compare 1 register (HRTIM_MCMP1R) . . . . . . 1021
34.5.10 HRTIM master timer compare 2 register (HRTIM_MCMP2R) . . . . . . 1022
34.5.11 HRTIM master timer compare 3 register (HRTIM_MCMP3R) . . . . . . 1022
34.5.12 HRTIM master timer compare 4 register (HRTIM_MCMP4R) . . . . . . 1023
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34.5.13 HRTIM timer x control register (HRTIM_TIMxCR) (x = A to F) . . . . . . 1023
34.5.14 HRTIM timer x interrupt status register (HRTIM_TIMxISR)
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
34.5.15 HRTIM timer x interrupt clear register (HRTIM_TIMxICR)
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
34.5.16 HRTIM timer x DMA interrupt enable register (HRTIM_TIMxDIER)
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
34.5.17 HRTIM timer x counter register (HRTIM_CNTxR) (x = A to F) . . . . . . 1033
34.5.18 HRTIM timer x period register (HRTIM_PERxR) (x = A to F) . . . . . . . 1034
34.5.19 HRTIM timer x repetition register (HRTIM_REPxR) (x = A to F) . . . . 1035
34.5.20 HRTIM timer x compare 1 register (HRTIM_CMP1xR) (x = A to F) . . 1035
34.5.21 HRTIM timer x compare 1 compound register (HRTIM_CMP1CxR)
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036
34.5.22 HRTIM timer x compare 2 register (HRTIM_CMP2xR) (x = A to F) . . 1037
34.5.23 HRTIM timer x compare 3 register (HRTIM_CMP3xR) (x = A to F) . . 1037
34.5.24 HRTIM timer x compare 4 register (HRTIM_CMP4xR) (x = A to F) . . 1038
34.5.25 HRTIM timer x capture 1 register (HRTIM_CPT1xR) (x = A to F) . . . 1039
34.5.26 HRTIM timer x capture 2 register (HRTIM_CPT2xR)
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
34.5.27 HRTIM timer x deadtime register (HRTIM_DTxR) (x = A to F) . . . . . . 1041
34.5.28 HRTIM timer x output 1 set register (HRTIM_SETx1R) (x = A to F) . 1042
34.5.29 HRTIM timer x output 1 reset register (HRTIM_RSTx1R) (x = A to F) 1044
34.5.30 HRTIM timer x output 2 set register (HRTIM_SETx2R) (x = A to F) . 1045
34.5.31 HRTIM timer x output 2 reset register (HRTIM_RSTx2R) (x = A to F) 1045
34.5.32 HRTIM timer x external event filtering register 1 (HRTIM_EEFxR1)
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
34.5.33 HRTIM timer x external event filtering register 2 (HRTIM_EEFxR2)
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
34.5.34 HRTIM timer A reset register (HRTIM_RSTAR) . . . . . . . . . . . . . . . . . 1049
34.5.35 HRTIM timer B reset register (HRTIM_RSTBR) . . . . . . . . . . . . . . . . 1051
34.5.36 HRTIM timer C reset register (HRTIM_RSTCR) . . . . . . . . . . . . . . . . 1053
34.5.37 HRTIM timer D reset register (HRTIM_RSTDR) . . . . . . . . . . . . . . . . 1055
34.5.38 HRTIM timer E reset register (HRTIM_RSTER) . . . . . . . . . . . . . . . . 1057
34.5.39 HRTIM timer F reset register (HRTIM_RSTFR) . . . . . . . . . . . . . . . . . 1059
34.5.40 HRTIM timer x chopper register (HRTIM_CHPxR) (x = A to F) . . . . . 1061
34.5.41 HRTIM timer A capture 1 control register (HRTIM_CPT1ACR) . . . . . 1062
34.5.42 HRTIM timer B capture 1 control register (HRTIM_CPT1BCR) . . . . . 1062
34.5.43 HRTIM timer C capture 1 control register (HRTIM_CPT1CCR) . . . . 1062
34.5.44 HRTIM timer D capture 1 control register (HRTIM_CPT1DCR) . . . . 1063
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34.5.45 HRTIM timer E capture 1 control register (HRTIM_CPT1ECR) . . . . . 1063
34.5.46 HRTIM timer F capture 1 control register (HRTIM_CPT1FCR) . . . . . 1063
34.5.47 HRTIM timer x capture 2 control register (HRTIM_CPT2xCR)
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
34.5.48 HRTIM timer x output register (HRTIM_OUTxR) (x = A to F) . . . . . . 1069
34.5.49 HRTIM timer x fault register (HRTIM_FLTxR) (x = A to F) . . . . . . . . . 1072
34.5.50 HRTIM timer x control register 2 (HRTIM_TIMxCR2) (x = A to F) . . . 1073
34.5.51 HRTIM timer x external event filtering register 3 (HRTIM_EEFxR3)
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075
34.5.52 HRTIM control register 1 (HRTIM_CR1) . . . . . . . . . . . . . . . . . . . . . . 1076
34.5.53 HRTIM control register 2 (HRTIM_CR2) . . . . . . . . . . . . . . . . . . . . . . 1077
34.5.54 HRTIM interrupt status register (HRTIM_ISR) . . . . . . . . . . . . . . . . . . 1079
34.5.55 HRTIM interrupt clear register (HRTIM_ICR) . . . . . . . . . . . . . . . . . . . 1080
34.5.56 HRTIM interrupt enable register (HRTIM_IER) . . . . . . . . . . . . . . . . . 1081
34.5.57 HRTIM output enable register (HRTIM_OENR) . . . . . . . . . . . . . . . . . 1082
34.5.58 HRTIM output disable register (HRTIM_ODISR) . . . . . . . . . . . . . . . . 1083
34.5.59 HRTIM output disable status register (HRTIM_ODSR) . . . . . . . . . . . 1084
34.5.60 HRTIM burst mode control register (HRTIM_BMCR) . . . . . . . . . . . . 1085
34.5.61 HRTIM burst mode trigger register (HRTIM_BMTRGR) . . . . . . . . . . 1087
34.5.62 HRTIM burst mode compare register (HRTIM_BMCMPR) . . . . . . . . 1089
34.5.63 HRTIM burst mode period register (HRTIM_BMPER) . . . . . . . . . . . . 1090
34.5.64 HRTIM timer external event control register 1 (HRTIM_EECR1) . . . 1090
34.5.65 HRTIM timer external event control register 2 (HRTIM_EECR2) . . . 1092
34.5.66 HRTIM timer external event control register 3 (HRTIM_EECR3) . . . 1093
34.5.67 HRTIM ADC trigger 1 register (HRTIM_ADC1R) . . . . . . . . . . . . . . . . 1094
34.5.68 HRTIM ADC trigger 2 register (HRTIM_ADC2R) . . . . . . . . . . . . . . . . 1095
34.5.69 HRTIM ADC trigger 3 register (HRTIM_ADC3R) . . . . . . . . . . . . . . . . 1095
34.5.70 HRTIM ADC trigger 4 register (HRTIM_ADC4R) . . . . . . . . . . . . . . . . 1097
34.5.71 HRTIM DLL control register (HRTIM_DLLCR) . . . . . . . . . . . . . . . . . . 1099
34.5.72 HRTIM fault input register 1 (HRTIM_FLTINR1) . . . . . . . . . . . . . . . . 1100
34.5.73 HRTIM fault input register 2 (HRTIM_FLTINR2) . . . . . . . . . . . . . . . . 1101
34.5.74 HRTIM burst DMA master timer update register
(HRTIM_BDMUPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1103
34.5.75 HRTIM burst DMA timer x update register (HRTIM_BDTxUPR)
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104
34.5.76 HRTIM burst DMA data register (HRTIM_BDMADR) . . . . . . . . . . . . 1106
34.5.77 HRTIM ADC extended trigger register (HRTIM_ADCER) . . . . . . . . . 1106
34.5.78 HRTIM ADC trigger update register (HRTIM_ADCUR) . . . . . . . . . . . 1108
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34.5.79 HRTIM ADC post scaler register 1 (HRTIM_ADCPS1) . . . . . . . . . . . 1109
34.5.80 HRTIM ADC post scaler register 2 (HRTIM_ADCPS2) . . . . . . . . . . . 1110
34.5.81 HRTIM fault input register 3 (HRTIM_FLTINR3) . . . . . . . . . . . . . . . . 1111
34.5.82 HRTIM fault input register 4 (HRTIM_FLTINR4) . . . . . . . . . . . . . . . . 1112
35
Advanced-control timers (TIM1/TIM8) . . . . . . . . . . . . . . . . . . . . . . . . 1114
35.1
TIM1/TIM8 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1114
35.2
TIM1/TIM8 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1114
35.3
TIM1/TIM8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115
35.3.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115
35.3.2
TIM1/TIM8 pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . 1116
35.3.3
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1118
35.3.4
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120
35.3.5
Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132
35.3.6
External trigger input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133
35.3.7
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134
35.3.8
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138
35.3.9
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140
35.3.10 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1141
35.3.11 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142
35.3.12 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1143
35.3.13 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144
35.3.14 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152
35.3.15 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1153
35.3.16 Combined 3-phase PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154
35.3.17 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . 1155
35.3.18 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1158
35.3.19 Bidirectional break inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164
35.3.20 Clearing the tim_ocxref signal on an external event . . . . . . . . . . . . . 1165
35.3.21 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167
35.3.22 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168
35.3.23 Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169
35.3.24 Pulse on compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1170
35.3.25 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1172
35.3.26 Direction bit output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1190
35.3.27 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191
35.3.28 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191
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35.3.29 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191
35.3.30 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193
35.3.31 ADC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197
35.3.32 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198
35.3.33 TIM1/TIM8 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199
35.3.34 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199
35.4
TIM1/TIM8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1199
35.5
TIM1/TIM8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1199
35.6
TIM1/TIM8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201
35.6.1
TIM1/TIM8 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201
35.6.2
TIMx control register 1 (TIMx_CR1)(x = 1, 8) . . . . . . . . . . . . . . . . . . 1202
35.6.3
TIMx control register 2 (TIMx_CR2)(x = 1, 8) . . . . . . . . . . . . . . . . . . 1203
35.6.4
TIMx slave mode control register (TIMx_SMCR)(x = 1, 8) . . . . . . . . 1207
35.6.5
TIMx DMA/interrupt enable register (TIMx_DIER)(x = 1, 8) . . . . . . . . 1211
35.6.6
TIMx status register (TIMx_SR)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . 1212
35.6.7
TIMx event generation register (TIMx_EGR)(x = 1, 8) . . . . . . . . . . . . 1215
35.6.8
TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1216
35.6.9
TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218
35.6.10 TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1221
35.6.11 TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1222
35.6.12 TIMx capture/compare enable register
(TIMx_CCER)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225
35.6.13 TIMx counter (TIMx_CNT)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . 1229
35.6.14 TIMx prescaler (TIMx_PSC)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . 1229
35.6.15 TIMx auto-reload register (TIMx_ARR)(x = 1, 8) . . . . . . . . . . . . . . . . 1230
35.6.16 TIMx repetition counter register (TIMx_RCR)(x = 1, 8) . . . . . . . . . . . 1230
35.6.17 TIMx capture/compare register 1 (TIMx_CCR1)(x = 1, 8) . . . . . . . . . 1231
35.6.18 TIMx capture/compare register 2 (TIMx_CCR2)(x = 1, 8) . . . . . . . . . 1231
35.6.19 TIMx capture/compare register 3 (TIMx_CCR3)(x = 1, 8) . . . . . . . . . 1232
35.6.20 TIMx capture/compare register 4 (TIMx_CCR4)(x = 1, 8) . . . . . . . . . 1233
35.6.21 TIMx break and dead-time register (TIMx_BDTR)(x = 1, 8) . . . . . . . 1234
35.6.22 TIMx capture/compare register 5 (TIMx_CCR5)(x = 1, 8) . . . . . . . . . 1238
35.6.23 TIMx capture/compare register 6 (TIMx_CCR6)(x = 1, 8) . . . . . . . . . 1239
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35.6.24 TIMx capture/compare mode register 3
(TIMx_CCMR3)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240
35.6.25 TIMx timer deadtime register 2 (TIMx_DTR2)(x = 1, 8) . . . . . . . . . . . 1241
35.6.26 TIMx timer encoder control register (TIMx_ECR)(x = 1, 8) . . . . . . . . 1242
35.6.27 TIMx timer input selection register (TIMx_TISEL)(x = 1, 8) . . . . . . . . 1243
35.6.28 TIMx alternate function option register 1 (TIMx_AF1)(x = 1, 8) . . . . . 1244
35.6.29 TIMx alternate function register 2 (TIMx_AF2)(x = 1, 8) . . . . . . . . . . 1247
35.6.30 TIMx DMA control register (TIMx_DCR)(x = 1, 8) . . . . . . . . . . . . . . . 1249
35.6.31 TIMx DMA address for full transfer (TIMx_DMAR)(x = 1, 8) . . . . . . . 1250
36
General-purpose timers (TIM2/TIM3/TIM4/TIM5) . . . . . . . . . . . . . . . . 1252
36.1
TIM2/TIM3/TIM4/TIM5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252
36.2
TIM2/TIM3/TIM4/TIM5 main features . . . . . . . . . . . . . . . . . . . . . . . . . . 1252
36.3
TIM2/TIM3/TIM4/TIM5 implementation . . . . . . . . . . . . . . . . . . . . . . . . 1253
36.4
TIM2/TIM3/TIM4/TIM5 functional description . . . . . . . . . . . . . . . . . . . . 1254
36.4.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254
36.4.2
TIM2/TIM3/TIM4/TIM5 pins and internal signals . . . . . . . . . . . . . . . . 1255
36.4.3
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257
36.4.4
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259
36.4.5
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270
36.4.6
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274
36.4.7
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1276
36.4.8
PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277
36.4.9
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1278
36.4.10 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1278
36.4.11 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280
36.4.12 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1288
36.4.13 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289
36.4.14 Clearing the tim_ocxref signal on an external event . . . . . . . . . . . . . 1290
36.4.15 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1292
36.4.16 Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1293
36.4.17 Pulse on compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1294
36.4.18 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296
36.4.19 Direction bit output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1314
36.4.20 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1315
36.4.21 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1315
36.4.22 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . 1315
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36.4.23 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1319
36.4.24 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1324
36.4.25 TIM2/TIM3/TIM4/TIM5 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . 1325
36.4.26 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1326
36.4.27 TIM2/TIM3/TIM4/TIM5 low-power modes . . . . . . . . . . . . . . . . . . . . . 1326
36.4.28 TIM2/TIM3/TIM4/TIM5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1326
36.5
TIM2/TIM3/TIM4/TIM5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1327
36.5.1
TIM2/TIM3/TIM4/TIM5 memory map . . . . . . . . . . . . . . . . . . . . . . . . . 1327
36.5.2
TIMx control register 1 (TIMx_CR1)(x = 2 to 5) . . . . . . . . . . . . . . . . . 1328
36.5.3
TIMx control register 2 (TIMx_CR2)(x = 2 to 5) . . . . . . . . . . . . . . . . . 1330
36.5.4
TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5) . . . . . . . 1332
36.5.5
TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5) . . . . . . 1336
36.5.6
TIMx status register (TIMx_SR)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . 1337
36.5.7
TIMx event generation register (TIMx_EGR)(x = 2 to 5) . . . . . . . . . . 1339
36.5.8
TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1340
36.5.9
TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1342
36.5.10 TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1344
36.5.11 TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1345
36.5.12 TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 5) . . . 1346
36.5.13 TIMx counter (TIMx_CNT)(x = 3, 4) . . . . . . . . . . . . . . . . . . . . . . . . . . 1348
36.5.14 TIMx counter (TIMx_CNT)(x = 2, 5) . . . . . . . . . . . . . . . . . . . . . . . . . . 1348
36.5.15 TIMx prescaler (TIMx_PSC)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . 1349
36.5.16 TIMx auto-reload register (TIMx_ARR)(x = 3, 4) . . . . . . . . . . . . . . . . 1349
36.5.17 TIMx auto-reload register (TIMx_ARR)(x = 2, 5) . . . . . . . . . . . . . . . . 1350
36.5.18 TIMx capture/compare register 1 (TIMx_CCR1)(x = 3, 4) . . . . . . . . . 1350
36.5.19 TIMx capture/compare register 1 (TIMx_CCR1)(x = 2, 5) . . . . . . . . . 1351
36.5.20 TIMx capture/compare register 2 (TIMx_CCR2)(x = 3, 4) . . . . . . . . . 1352
36.5.21 TIMx capture/compare register 2 (TIMx_CCR2)(x = 2, 5) . . . . . . . . . 1353
36.5.22 TIMx capture/compare register 3 (TIMx_CCR3)(x = 3, 4) . . . . . . . . . 1354
36.5.23 TIMx capture/compare register 3 (TIMx_CCR3)(x = 2, 5) . . . . . . . . . 1355
36.5.24 TIMx capture/compare register 4 (TIMx_CCR4)(x = 3, 4) . . . . . . . . . 1356
36.5.25 TIMx capture/compare register 4 (TIMx_CCR4)(x = 2, 5) . . . . . . . . . 1357
36.5.26 TIMx timer encoder control register (TIMx_ECR)(x = 2 to 5) . . . . . . . 1358
36.5.27 TIMx timer input selection register (TIMx_TISEL)(x = 2 to 5) . . . . . . 1359
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36.5.28 TIMx alternate function register 1 (TIMx_AF1)(x = 2 to 5) . . . . . . . . . 1360
36.5.29 TIMx alternate function register 2 (TIMx_AF2)(x = 2 to 5) . . . . . . . . . 1361
36.5.30 TIMx DMA control register (TIMx_DCR)(x = 2 to 5) . . . . . . . . . . . . . . 1362
36.5.31 TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5) . . . . . . 1363
37
Basic timers (TIM6/TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364
37.1
TIM6/TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364
37.2
TIM6/TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364
37.3
TIM6/TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1365
37.3.1
TIM6/TIM7 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1365
37.3.2
TIM6/TIM7 internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1365
37.3.3
TIM6/TIM7 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1366
37.3.4
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1366
37.3.5
Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368
37.3.6
UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1374
37.3.7
TIM6/TIM7 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375
37.3.8
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375
37.3.9
TIM6/TIM7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375
37.3.10 TIM6/TIM7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375
37.4
38
TIM6/TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375
37.4.1
TIM6/TIM7 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1376
37.4.2
TIMx control register 1 (TIMx_CR1)(x = 6 to 7) . . . . . . . . . . . . . . . . . 1376
37.4.3
TIMx control register 2 (TIMx_CR2)(x = 6 to 7) . . . . . . . . . . . . . . . . . 1378
37.4.4
TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) . . . . . . 1378
37.4.5
TIMx status register (TIMx_SR)(x = 6 to 7) . . . . . . . . . . . . . . . . . . . . 1379
37.4.6
TIMx event generation register (TIMx_EGR)(x = 6 to 7) . . . . . . . . . . 1379
37.4.7
TIMx counter (TIMx_CNT)(x = 6 to 7) . . . . . . . . . . . . . . . . . . . . . . . . 1379
37.4.8
TIMx prescaler (TIMx_PSC)(x = 6 to 7) . . . . . . . . . . . . . . . . . . . . . . . 1380
37.4.9
TIMx auto-reload register (TIMx_ARR)(x = 6 to 7) . . . . . . . . . . . . . . 1380
General-purpose timers (TIM15/TIM16) . . . . . . . . . . . . . . . . . . . . . . . 1381
38.1
TIM15/TIM16 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1381
38.2
TIM15 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1381
38.3
TIM16 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1382
38.4
TIM15/TIM16 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1383
38.4.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1383
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38.4.2
TIM15/TIM16 pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . 1384
38.4.3
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1385
38.4.4
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388
38.4.5
Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1392
38.4.6
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1393
38.4.7
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1395
38.4.8
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1397
38.4.9
PWM input mode (only for TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399
38.4.10 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400
38.4.11 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400
38.4.12 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1402
38.4.13 Combined PWM mode (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . . . 1407
38.4.14 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . 1408
38.4.15 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1411
38.4.16 Bidirectional break input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1414
38.4.17 Clearing the tim_ocxref signal on an external event . . . . . . . . . . . . . 1416
38.4.18 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1417
38.4.19 Retriggerable one pulse mode (TIM15 only) . . . . . . . . . . . . . . . . . . . 1418
38.4.20 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1419
38.4.21 Timer input XOR function (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . 1419
38.4.22 External trigger synchronization (TIM15 only) . . . . . . . . . . . . . . . . . . 1420
38.4.23 Slave mode – combined reset + trigger mode (TIM15 only) . . . . . . . 1422
38.4.24 Slave mode – combined reset + gated mode (TIM15 only) . . . . . . . . 1422
38.4.25 Timer synchronization (TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1423
38.4.26 Using timer output as trigger for other timers (TIM16) . . . . . . . . . . . . 1423
38.4.27 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1423
38.4.28 TIM15/TIM16 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424
38.4.29 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424
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38.5
TIM15/TIM16 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425
38.6
TIM15/TIM16 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425
38.7
TIM15/TIM16 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425
38.8
TIM15 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1427
38.8.1
TIM15 control register 1 (TIM15_CR1) . . . . . . . . . . . . . . . . . . . . . . . 1427
38.8.2
TIM15 control register 2 (TIM15_CR2) . . . . . . . . . . . . . . . . . . . . . . . 1428
38.8.3
TIM15 slave mode control register (TIM15_SMCR) . . . . . . . . . . . . . 1430
38.8.4
TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . . . . . . . . . 1431
38.8.5
TIM15 status register (TIM15_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1432
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Contents
38.8.6
TIM15 event generation register (TIM15_EGR) . . . . . . . . . . . . . . . . 1434
38.8.7
TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1435
38.8.8
TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1437
38.8.9
TIM15 capture/compare enable register (TIM15_CCER) . . . . . . . . . 1439
38.8.10 TIM15 counter (TIM15_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1442
38.8.11 TIM15 prescaler (TIM15_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1442
38.8.12 TIM15 auto-reload register (TIM15_ARR) . . . . . . . . . . . . . . . . . . . . . 1443
38.8.13 TIM15 repetition counter register (TIM15_RCR) . . . . . . . . . . . . . . . . 1443
38.8.14 TIM15 capture/compare register 1 (TIM15_CCR1) . . . . . . . . . . . . . . 1444
38.8.15 TIM15 capture/compare register 2 (TIM15_CCR2) . . . . . . . . . . . . . . 1445
38.8.16 TIM15 break and dead-time register (TIM15_BDTR) . . . . . . . . . . . . 1445
38.8.17 TIM15 timer deadtime register 2 (TIM15_DTR2) . . . . . . . . . . . . . . . . 1448
38.8.18 TIM15 input selection register (TIM15_TISEL) . . . . . . . . . . . . . . . . . 1449
38.8.19 TIM15 alternate function register 1 (TIM15_AF1) . . . . . . . . . . . . . . . 1450
38.8.20 TIM15 alternate function register 2 (TIM15_AF2) . . . . . . . . . . . . . . . 1452
38.8.21 TIM15 DMA control register (TIM15_DCR) . . . . . . . . . . . . . . . . . . . . 1453
38.8.22 TIM15 DMA address for full transfer (TIM15_DMAR) . . . . . . . . . . . . 1453
38.9
TIM16 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455
38.9.1
TIMx control register 1 (TIMx_CR1)(x = 16) . . . . . . . . . . . . . . . . . . . 1455
38.9.2
TIMx control register 2 (TIMx_CR2)(x = 16) . . . . . . . . . . . . . . . . . . . 1456
38.9.3
TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16) . . . . . . . . . 1457
38.9.4
TIMx status register (TIMx_SR)(x = 16) . . . . . . . . . . . . . . . . . . . . . . . 1458
38.9.5
TIMx event generation register (TIMx_EGR)(x = 16) . . . . . . . . . . . . . 1459
38.9.6
TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1460
38.9.7
TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1461
38.9.8
TIMx capture/compare enable register (TIMx_CCER)(x = 16) . . . . . 1463
38.9.9
TIMx counter (TIMx_CNT)(x = 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1466
38.9.10 TIMx prescaler (TIMx_PSC)(x = 16) . . . . . . . . . . . . . . . . . . . . . . . . . 1466
38.9.11 TIMx auto-reload register (TIMx_ARR)(x = 16) . . . . . . . . . . . . . . . . . 1467
38.9.12 TIMx repetition counter register (TIMx_RCR)(x = 16) . . . . . . . . . . . . 1467
38.9.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 16) . . . . . . . . . . 1468
38.9.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16) . . . . . . . . 1469
38.9.15 TIMx option register 1 (TIMx_OR1)(x = 16) . . . . . . . . . . . . . . . . . . . . 1472
38.9.16 TIMx timer deadtime register 2 (TIMx_DTR2)(x = 16) . . . . . . . . . . . . 1472
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38.9.17 TIMx input selection register (TIMx_TISEL)(x = 16) . . . . . . . . . . . . . 1473
38.9.18 TIMx alternate function register 1 (TIMx_AF1)(x = 16) . . . . . . . . . . . 1473
38.9.19 TIMx alternate function register 2 (TIMx_AF2)(x = 16) . . . . . . . . . . . 1476
38.9.20 TIMx DMA control register (TIMx_DCR)(x = 16) . . . . . . . . . . . . . . . . 1476
38.9.21 TIM16 DMA address for full transfer
(TIMx_DMAR)(x = 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477
39
Timestamp timer (TIM_TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478
39.1
TIM_TS introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478
39.2
TIM_TS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478
39.3
TIM_TS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478
39.3.1
TIM_TS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478
39.3.2
TIM_TS internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479
39.3.3
TIM_TS clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479
39.3.4
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1480
39.3.5
Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482
39.3.6
UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1488
39.3.7
TIM_TS DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1488
39.3.8
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
39.3.9
TIM_TS low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
39.3.10 TIM_TS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
39.4
40
TIM_TS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
39.4.1
TIM_TS memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
39.4.2
TIM_TS control register 1 (TIM_TS_CR1) . . . . . . . . . . . . . . . . . . . . . 1490
39.4.3
TIM_TS control register 2 (TIM_TS_CR2) . . . . . . . . . . . . . . . . . . . . . 1492
39.4.4
TIM_TS DMA/Interrupt enable register (TIM_TS_DIER) . . . . . . . . . . 1492
39.4.5
TIM_TS status register (TIM_TS_SR) . . . . . . . . . . . . . . . . . . . . . . . . 1493
39.4.6
TIM_TS event generation register (TIM_TS_EGR) . . . . . . . . . . . . . . 1493
39.4.7
TIM_TS counter (TIM_TS_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1493
39.4.8
TIM_TS prescaler (TIM_TS_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1494
39.4.9
TIM_TS auto-reload register (TIM_TS_ARR) . . . . . . . . . . . . . . . . . . 1494
Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495
40.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495
40.2
RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495
40.3
RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1496
40.3.1
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40.3.2
RTC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1497
40.3.3
Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1497
40.3.4
Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1498
40.3.5
Programmable alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1498
40.3.6
Periodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1499
40.3.7
RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 1499
40.3.8
Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1501
40.3.9
Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502
40.3.10 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502
40.3.11 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502
40.3.12 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504
40.4
RTC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505
40.5
RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505
40.6
RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505
40.6.1
RTC memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505
40.6.2
RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1506
40.6.3
RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507
40.6.4
RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . 1507
40.6.5
RTC initialization control and status register (RTC_ICSR) . . . . . . . . 1508
40.6.6
RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . 1509
40.6.7
RTC wakeup timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . 1510
40.6.8
RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1510
40.6.9
RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . 1512
40.6.10 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . 1513
40.6.11 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . 1514
40.6.12 RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . 1515
40.6.13 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . 1516
40.6.14 RTC status register (RTC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1516
40.6.15 RTC masked interrupt status register (RTC_MISR) . . . . . . . . . . . . . 1517
40.6.16 RTC status clear register (RTC_SCR) . . . . . . . . . . . . . . . . . . . . . . . . 1517
41
Universal asynchronous receiver transmitter (UART) . . . . . . . . . . . 1519
41.1
UART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1519
41.2
UART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1519
41.3
UART extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1520
41.4
UART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1520
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41.5
UART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1521
41.5.1
UART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1521
41.5.2
UART signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522
41.5.3
UART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522
41.5.4
UART FIFOs and thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1524
41.5.5
UART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1524
41.5.6
UART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1528
41.5.7
UART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1535
41.5.8
Tolerance of the UART receiver to clock deviation . . . . . . . . . . . . . . 1536
41.5.9
UART Auto baud rate detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1538
41.5.10 UART multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . 1540
41.5.11 UART Modbus communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1542
41.5.12 UART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1543
41.5.13 UART LIN (local interconnection network) mode . . . . . . . . . . . . . . . . 1544
41.5.14 UART single-wire Half-duplex communication . . . . . . . . . . . . . . . . . . 1546
41.5.15 UART receiver timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1546
41.5.16 UART IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547
41.5.17 Continuous communication using UART and DMA . . . . . . . . . . . . . . 1549
41.5.18 UART low-power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1552
41.6
UART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1555
41.7
UART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1557
41.7.1
UART memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1557
41.7.2
UART control register 1 [alternate] (UART_CR1) . . . . . . . . . . . . . . . 1558
41.7.3
UART control register 1 [alternate] (UART_CR1) . . . . . . . . . . . . . . . 1561
41.7.4
UART control register 2 (UART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . 1565
41.7.5
UART control register 3 (UART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . 1568
41.7.6
UART baud rate register (UART_BRR) . . . . . . . . . . . . . . . . . . . . . . . 1573
41.7.7
UART guard time and prescaler register (UART_GTPR) . . . . . . . . . 1573
41.7.8
UART receiver timeout register (UART_RTOR) . . . . . . . . . . . . . . . . 1574
41.7.9
UART request register (UART_RQR) . . . . . . . . . . . . . . . . . . . . . . . . 1575
41.7.10 UART interrupt and status register [alternate] (UART_ISR) . . . . . . . 1576
41.7.11 UART interrupt and status register [alternate] (UART_ISR) . . . . . . . 1581
41.7.12 UART interrupt flag clear register (UART_ICR) . . . . . . . . . . . . . . . . . 1586
41.7.13 UART receive data register (UART_RDR) . . . . . . . . . . . . . . . . . . . . . 1588
41.7.14 UART transmit data register (UART_TDR) . . . . . . . . . . . . . . . . . . . . 1588
41.7.15 UART prescaler register (UART_PRESC) . . . . . . . . . . . . . . . . . . . . . 1589
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Serial peripheral interface / integrated interchip sound (SPI/I2S) . 1590
42.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1590
42.2
SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1590
42.3
I2S main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1591
42.4
SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1591
42.5
SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1592
42.5.1
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1592
42.5.2
Communications between one master and one slave . . . . . . . . . . . . 1593
42.5.3
Standard multi-slave communication . . . . . . . . . . . . . . . . . . . . . . . . . 1595
42.5.4
Multi-master communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1596
42.5.5
Slave select (NSS) pin management . . . . . . . . . . . . . . . . . . . . . . . . . 1597
42.5.6
Communication formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1598
42.5.7
Configuration of SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1600
42.5.8
Procedure for enabling SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1601
42.5.9
Data transmission and reception procedures . . . . . . . . . . . . . . . . . . 1601
42.5.10 SPI status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1611
42.5.11 SPI error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612
42.5.12 NSS pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613
42.5.13 TI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613
42.5.14 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1614
42.6
SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1616
42.7
I2S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617
42.7.1
I2S general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617
42.7.2
Supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1618
42.7.3
Startup description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1625
42.7.4
Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1627
42.7.5
I2S master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1630
42.7.6
I2S slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631
42.7.7
I2S status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
42.7.8
I2S error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634
42.7.9
DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1635
42.8
I2S interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1635
42.9
SPI and I2S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1636
42.9.1
SPI and I2S memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1636
42.9.2
SPI control register 1 (SPIx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1636
42.9.3
SPI control register 2 (SPIx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1638
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42.9.4
SPI status register (SPIx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640
42.9.5
SPI data register (SPIx_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1642
42.9.6
SPI CRC polynomial register (SPIx_CRCPR) . . . . . . . . . . . . . . . . . . 1642
42.9.7
SPI Rx CRC register (SPIx_RXCRCR) . . . . . . . . . . . . . . . . . . . . . . . 1643
42.9.8
SPI Tx CRC register (SPIx_TXCRCR) . . . . . . . . . . . . . . . . . . . . . . . 1643
42.9.9
SPIx_I2S configuration register (SPIx_I2SCFGR) . . . . . . . . . . . . . . . 1644
42.9.10 SPIx_I2S prescaler register (SPIx_I2SPR) . . . . . . . . . . . . . . . . . . . . 1645
43
Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . 1647
43.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647
43.2
I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647
43.3
I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648
43.4
I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648
43.4.1
I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649
43.4.2
I2C pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650
43.4.3
I2C clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650
43.4.4
Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650
43.4.5
I2C initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651
43.4.6
Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1656
43.4.7
Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1657
43.4.8
I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1659
43.4.9
I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1668
43.4.10 I2C_TIMINGR register configuration examples . . . . . . . . . . . . . . . . . 1679
43.4.11 SMBus specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1681
43.4.12 SMBus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1684
43.4.13 SMBus: I2C_TIMEOUTR register configuration examples . . . . . . . . 1686
43.4.14 SMBus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1687
43.4.15 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1693
43.4.16 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1695
43.4.17 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1696
36/2075
43.5
I2C low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1696
43.6
I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697
43.7
I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697
43.7.1
I2C memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697
43.7.2
I2C control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698
43.7.3
I2C control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1701
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43.7.4
I2C own address 1 register (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . 1703
43.7.5
I2C own address 2 register (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . 1704
43.7.6
I2C timing register (I2C_TIMINGR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1705
43.7.7
I2C timeout register (I2C_TIMEOUTR) . . . . . . . . . . . . . . . . . . . . . . . 1706
43.7.8
I2C interrupt and status register (I2C_ISR) . . . . . . . . . . . . . . . . . . . . 1707
43.7.9
I2C interrupt clear register (I2C_ICR) . . . . . . . . . . . . . . . . . . . . . . . . 1709
43.7.10 I2C PEC register (I2C_PECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710
43.7.11 I2C receive data register (I2C_RXDR) . . . . . . . . . . . . . . . . . . . . . . . 1711
43.7.12 I2C transmit data register (I2C_TXDR) . . . . . . . . . . . . . . . . . . . . . . . 1711
44
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712
44.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712
44.2
IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712
44.3
IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712
44.4
45
44.3.1
IWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712
44.3.2
Window option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1713
44.3.3
Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714
44.3.4
Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714
44.3.5
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714
IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1715
44.4.1
IWDG memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1715
44.4.2
IWDG key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1715
44.4.3
IWDG prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . 1716
44.4.4
IWDG reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1717
44.4.5
IWDG status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1718
44.4.6
IWDG window register (IWDG_WINR) . . . . . . . . . . . . . . . . . . . . . . . 1719
System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . 1720
45.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1720
45.2
WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1720
45.3
WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1720
45.3.1
WWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1721
45.3.2
Enabling the watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1721
45.3.3
Controlling the down-counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1721
45.3.4
How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . 1721
45.3.5
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1722
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46
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45.4
WWDG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1723
45.5
WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1723
45.5.1
WWDG memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1723
45.5.2
WWDG control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . 1723
45.5.3
WWDG configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . 1724
45.5.4
WWDG status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . 1725
CAN subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1726
46.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1726
46.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1728
46.3
Controller area network (M_CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1728
46.4
DMA interface unit (DMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1728
46.5
Timestamping unit (TSU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1728
46.6
CAN RAM arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1728
46.7
46.6.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1729
46.6.2
Functional overview using examples . . . . . . . . . . . . . . . . . . . . . . . . . 1729
SRAM interface and memory organization . . . . . . . . . . . . . . . . . . . . . . 1729
46.7.1
ECC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1729
46.8
CAN nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1730
46.9
External Timestamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1731
46.10 External signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1732
46.11 Shared memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1732
47
Controller area network (M_CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1734
47.1
47.2
38/2075
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1734
47.1.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1735
47.1.2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1736
47.1.3
Dual clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1737
47.1.4
Dual interrupt lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1737
Memory map and register descriptions . . . . . . . . . . . . . . . . . . . . . . . . 1737
47.2.1
Hardware reset description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1737
47.2.2
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1737
47.2.3
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1740
47.2.4
Message RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1786
47.2.5
M_CAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1798
47.2.6
Timestamp generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1809
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47.2.7
Timeout counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1809
47.2.8
Rx handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1810
47.2.9
Dedicated Rx buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1817
47.2.10 Debug on CAN support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1818
47.2.11 Tx handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1820
47.2.12 FIFO acknowledge handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1825
48
DMA interface unit (DMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1826
48.1
48.2
48.3
49
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1826
48.1.1
M_CAN message handling (without DMU) . . . . . . . . . . . . . . . . . . . . 1826
48.1.2
Message handling with DMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1826
48.1.3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1827
Memory map and register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 1828
48.2.1
Hardware reset description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1828
48.2.2
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1828
48.2.3
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1829
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1843
48.3.1
DMU TX element (0x200–0x244) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1843
48.3.2
DMU RX element (0x280–0x2C4 and 0x300–0x344) . . . . . . . . . . . . 1844
48.3.3
TX Event Element (0x380–0x388) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1845
48.3.4
Exception Recovery at DMU Virtual Buffer . . . . . . . . . . . . . . . . . . . . 1845
48.3.5
Transferring timestamps from TSU . . . . . . . . . . . . . . . . . . . . . . . . . . 1845
48.3.6
M_CAN in CCE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1846
48.3.7
DMU service request signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1847
48.3.8
Software debugging support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1847
Timestamping unit (TSU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1850
49.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1850
49.2
Memory map and register descriptions . . . . . . . . . . . . . . . . . . . . . . . . 1850
49.3
49.4
49.2.1
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1850
49.2.2
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1850
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1856
49.3.1
M_CAN configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1856
49.3.2
TSU operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1856
TSU integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1858
49.4.1
TSU with internal 32-bit counter as timebase . . . . . . . . . . . . . . . . . . 1859
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49.4.2
49.5
50
40/2075
New features of M_CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1859
49.5.1
Generic parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1859
49.5.2
Additional interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1860
49.5.3
Timestamp control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1860
49.5.4
Modification of Tx buffer element . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1861
49.5.5
Modification of Rx Buffer and FIFO element . . . . . . . . . . . . . . . . . . . 1861
49.5.6
Modification of Tx event FIFO element . . . . . . . . . . . . . . . . . . . . . . . 1861
49.5.7
Modification of standard message ID Filter Element . . . . . . . . . . . . . 1861
49.5.8
Modification of extended message ID Filter Element . . . . . . . . . . . . 1862
Hardware semaphore (HSEM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1863
50.1
Hardware semaphore introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1863
50.2
Hardware semaphore main features . . . . . . . . . . . . . . . . . . . . . . . . . . 1863
50.3
HSEM2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1864
50.4
HSEM2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1864
50.5
51
TSU without internal timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1859
50.4.1
HSEM2 lock procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1864
50.4.2
HSEM2 write/read/readlock register address . . . . . . . . . . . . . . . . . . 1866
50.4.3
HSEM2 clear procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1866
50.4.4
HSEM2 COREID semaphore clear . . . . . . . . . . . . . . . . . . . . . . . . . . 1866
50.4.5
HSEM2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1867
50.4.6
AHB bus master ID verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1868
HSEM2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1869
50.5.1
HSEM2 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1869
50.5.2
HSEM2 register semaphore x (HSEM2_Rx) . . . . . . . . . . . . . . . . . . . 1870
50.5.3
HSEM2 read lock register semaphore x (HSEM2_RLRx) . . . . . . . . . 1871
50.5.4
HSEM2 interrupt enable register (HSEM2_IERn) (n=0 to 2) . . . . . . . 1872
50.5.5
HSEM2 interrupt clear register (HSEM2_ICRn) (n=0 to 2) . . . . . . . . 1872
50.5.6
HSEM2 interrupt status register (HSEM2_ISRn) (n=0 to 2) . . . . . . . 1872
50.5.7
HSEM2 interrupt status register (HSEM2_MISRn) (n=0 to 2) . . . . . . 1873
50.5.8
HSEM2 clear register (HSEM2_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 1873
50.5.9
HSEM2 interrupt clear register (HSEM2_KEYR) . . . . . . . . . . . . . . . . 1874
Fault collection and control unit (FCCU) . . . . . . . . . . . . . . . . . . . . . 1875
51.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1875
51.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1875
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51.2.1
Standard feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1876
51.3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1876
51.4
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1877
51.5
51.4.1
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1877
51.4.2
IPS bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1878
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1878
51.5.1
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1878
51.5.2
FSM description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1879
51.5.3
Reset interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1880
51.5.4
Fault priority scheme and nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . 1881
51.5.5
Fault recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1882
51.5.6
NMI/WKPU interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1884
51.5.7
FAULT interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1885
51.5.8
STCU interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1886
51.5.9
EOUT interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1887
51.5.10 Error signal flow for RF case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1892
51.6
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1894
51.6.1
FCCU Control Register (FCCU_CTRL) . . . . . . . . . . . . . . . . . . . . . . . 1896
51.6.2
FCCU CTRL Key Register (FCCU_CTRLK) . . . . . . . . . . . . . . . . . . . 1898
51.6.3
FCCU Configuration Register (FCCU_CFG) . . . . . . . . . . . . . . . . . . . 1899
51.6.4
FCCU RF Configuration Register n (FCCU_RF_CFGn) . . . . . . . . . . 1901
51.6.5
FCCU RFS Configuration Register n (FCCU_RFS_CFGn) . . . . . . . . 1902
51.6.6
FCCU RF Status register n (FCCU_RF_Sn) . . . . . . . . . . . . . . . . . . . 1903
51.6.7
FCCU RF Key register (FCCU_RFK) . . . . . . . . . . . . . . . . . . . . . . . . 1905
51.6.8
FCCU RF Enable Register n (FCCU_RF_En) . . . . . . . . . . . . . . . . . . 1906
51.6.9
FCCU RF Timeout Enable Register n (FCCU_RF_TOEn) . . . . . . . . 1907
51.6.10 FCCU RF Timeout Register (FCCU_RF_TO) . . . . . . . . . . . . . . . . . . 1908
51.6.11 FCCU CFG Timeout Register (FCCU_CFG_TO) . . . . . . . . . . . . . . . 1909
51.6.12 FCCU IO Control Register (FCCU_EINOUT) . . . . . . . . . . . . . . . . . . 1910
51.6.13 FCCU Status Register (FCCU_STAT) . . . . . . . . . . . . . . . . . . . . . . . . 1911
51.6.14 FCCU NA Freeze Status Register (N2AF_STATUS) . . . . . . . . . . . . . 1913
51.6.15 FCCU AF Freeze Status Register (A2FF_STATUS) . . . . . . . . . . . . . 1913
51.6.16 FCCU NF Freeze Status Register (N2FF_STATUS) . . . . . . . . . . . . . 1914
51.6.17 FCCU FA Freeze Status Register (F2A_STATUS) . . . . . . . . . . . . . . 1915
51.6.18 FCCU RF Fake Register (FCCU_RFF) . . . . . . . . . . . . . . . . . . . . . . . 1916
51.6.19 FCCU IRQ Status Register (FCCU_IRQ_STAT) . . . . . . . . . . . . . . . . 1917
51.6.20 FCCU IRQ Enable Register (FCCU_IRQ_EN) . . . . . . . . . . . . . . . . . 1918
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51.6.21 FCCU XTMR Register (FCCU_XTMR) . . . . . . . . . . . . . . . . . . . . . . . 1919
51.6.22 FCCU Transient Register (FCCU_TRANS_LOCK) . . . . . . . . . . . . . . 1920
51.6.23 FCCU Permanent Lock Register (FCCU_PERMNT_LOCK) . . . . . . . 1921
51.6.24 FCCU Delta T Register (FCCU_DELTA_T) . . . . . . . . . . . . . . . . . . . . 1921
51.6.25 FCCU IRQ Alarm Enable register n (FCCU_IRQ_ALARM_ENn) . . . 1922
51.6.26 FCCU NMI Enable registers n (FCCU_NMI_ENn) . . . . . . . . . . . . . . 1923
51.6.27 FCCU EOUT Signaling Enable registers n
(FCCU_EOUT_SIG_ENn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1924
51.6.28 FCCU NMI2 Enable registers n (FCCU_NMI2_ENn) . . . . . . . . . . . . 1925
52
51.7
FCCU Output Supervision Unit (FOSU) . . . . . . . . . . . . . . . . . . . . . . . . 1926
51.8
Use cases and limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1928
Misconfigurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1928
51.8.2
Recommendations to configure FCCU . . . . . . . . . . . . . . . . . . . . . . . 1928
Collective error manager (CEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1929
52.1
52.2
52.3
52.4
42/2075
51.8.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1929
52.1.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1929
52.1.2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1929
52.1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1930
System interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1930
52.2.1
System block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1931
52.2.2
Bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1931
52.2.3
IO interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1931
52.2.4
Interrupt interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1931
52.2.5
DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1932
52.2.6
Clock interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1932
52.2.7
Reset interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1932
52.2.8
Safety fault interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1932
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1932
52.3.1
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1932
52.3.2
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1933
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1938
52.4.1
CEM functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1938
52.4.2
CEM internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1938
52.4.3
CEM Programmable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1939
52.4.4
Clock and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1939
52.4.5
Asynchronous fault capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1939
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52.4.6
53
52.5
Safety mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1940
52.6
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1940
52.7
Programming guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1940
Memory error management unit 2 (MEMU2) . . . . . . . . . . . . . . . . . . . 1944
53.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1944
53.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1945
53.3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1945
53.4
Design overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1946
55
53.4.1
Memory to MEMU agent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1946
53.4.2
Error processing block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1947
53.4.3
Reporting table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1948
53.4.4
Register block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1948
53.4.5
ECC filtered reaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1949
53.5
External signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1952
53.6
Memory map and registers definition . . . . . . . . . . . . . . . . . . . . . . . . . . 1952
53.7
54
Debug mode behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1940
53.6.1
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1952
53.6.2
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1956
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1987
53.7.1
Initializing MEMU2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1987
53.7.2
Reading the reporting table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1988
53.7.3
Handling overflows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1989
Indirect Memory Access (IMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1990
54.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1990
54.2
Accessing memory through the IMA module . . . . . . . . . . . . . . . . . . . . 1990
54.2.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1991
54.2.2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1991
54.2.3
IMA Module Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . 1992
54.2.4
IMA module functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1999
54.2.5
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000
Self-test control unit (STCU3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2001
55.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2001
55.1.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2001
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55.1.2
55.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2003
55.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2004
55.4
55.5
56
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2001
55.3.1
FSM description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2004
55.3.2
DCF interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2005
55.3.3
Reset management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2005
55.3.4
BIST scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2005
55.3.5
PLL interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2007
55.3.6
Interrupt interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2007
55.3.7
Fault collector interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2007
55.3.8
Watchdog support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2007
55.3.9
CRC support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2008
Programming guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2008
55.4.1
Offline self-test sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2008
55.4.2
Bypass user mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2010
Memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . 2010
55.5.1
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2010
55.5.2
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2011
Tamper detection module (TDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2038
56.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2038
56.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2039
56.3
External signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2039
56.4
DCF client . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2039
56.4.1
Diary base address (DBA) DCF client . . . . . . . . . . . . . . . . . . . . . . . . 2040
56.4.2
Tamper region override (TO) DCF client . . . . . . . . . . . . . . . . . . . . . . 2041
56.4.3
One time programmable enable (OTPEN0) DCF client . . . . . . . . . . . 2041
56.4.4
One time programmable enable (OTPEN1) DCF client . . . . . . . . . . . 2042
56.4.5
One time programmable enable (OTPEN2) DCF client . . . . . . . . . . . 2043
56.4.6
One time programmable enable (OTPEN3) DCF client . . . . . . . . . . . 2043
56.4.7
Tamper region assignment DCF client (TDRn_LOCK0) . . . . . . . . . . 2044
56.4.8
Tamper region assignment DCF client (TDRn _LOCK1) . . . . . . . . . . 2045
56.4.9
Tamper region assignment DCF client (TDRn_LOCK2) . . . . . . . . . . 2046
56.4.10 Tamper region assignment DCF client (TDRn_LOCK3) . . . . . . . . . . 2046
56.5
Memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2047
56.5.1
44/2075
TDR status register (TDM_TDRSR) . . . . . . . . . . . . . . . . . . . . . . . . . 2047
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Contents
56.6
56.5.2
Last flash programmed address register (TDM_LFPAR) . . . . . . . . . . 2049
56.5.3
Diary base address (TDM_DBA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2050
56.5.4
Software tamper override key region (TDM_STO_KEYn) . . . . . . . . . 2050
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2051
56.6.1
Flash erase counter and tamper detection . . . . . . . . . . . . . . . . . . . . 2051
56.6.2
Assigning blocks to tamper detect regions (TDR) . . . . . . . . . . . . . . . 2052
56.6.3
Diary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2053
56.6.4
Specifying the diary base address . . . . . . . . . . . . . . . . . . . . . . . . . . . 2053
56.6.5
Diary base address verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2054
56.6.6
One time programmable (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2055
Appendix A Acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2056
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2060
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Preface
RM0483
1
Preface
1.1
Document organization
This document includes chapters that are divided into parts:
1.2
•
Part I includes chapters that describe the device as a whole or provide device-specific
information.
•
Part II includes chapters that describe the functionality of the individual modules on the
device.
Register conventions
Figure 1 and Table 1 provide the register conventions used throughout this manual.
Always
reads 1
1
Always
reads 0
0
R/W
Read- BIT
BIT
bit
only bit
Writeonly bit BIT
Write 1 BIT Self-clear
to clear w1c
bit
0
BIT
N/A
Figure 1. Key to register fields
Table 1. Register conventions
Convention
Description
Depending on its placement in the read or write row, indicates that the bit is not
readable or not writable.
FIELDNAME
Identifies the field. Its presence in the read or write row indicates that it can be read
or written.
Register field types
R
Read only. Writing this bit has no effect.
W
Write only
R/W
Standard read/write bit. Only software can change the bit’s value (other than a
hardware reset).
rwm
A read/write bit that may be modified by a hardware in some fashion other than by a
reset.
w1c
Write one to clear. A status bit that can be read, and is cleared by writing a one.
slfclr
Self-clearing bit. Writing a one has some effect on the module, but it always reads as
zero.
Reset values
46/2075
0
Resets to zero
1
Resets to one
—
Undefined at reset
RM0483 Rev 5
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1.3
Preface
Acronyms and abbreviations
Appendix A: Acronyms and abbreviations lists acronyms and abbreviations used in this
document.
1.4
Reference documents
In addition to this reference manual, the following documents provide additional information
on the operation of the SR5E1x:
•
IEEE 1149.1-2001 standard - IEEE Standard Test Access Port and Boundary-Scan
Architecture
Note:
For information on the CoreSight™ and Arm® Cortex®-M7 cores, refer to the CoreSight™
Architecture Specification v2.0 and Arm® Cortex®-M7 technical reference manual, available
from the www.arm.com website.
Note:
Arm is a registered trademark of Arm Limited (or its subsidiaries or affiliates) in the US
and/or elsewhere.
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47
Introduction
2
RM0483
Introduction
The SR5E1x belongs to a new generation of microcontroller family built on Arm®
Cortex®-M7 cores, bringing new level of performance, safety, and security for real-time
automotive applications.
The device especially targets analog performance platforms and fast digital control
applications, such as in the fields of:
•
DC/DC converter
•
On-board charger
•
Advanced motor control
Note:
The Arm word and logo are trademarks of Arm Limited (or its subsidiaries) in the US and/or
elsewhere. All rights reserved.
2.1
Overall architecture
The architecture is split between one cluster domain that performs various computational
and control functions and a HSM domain as shown in Figure 2: Block diagram. All
components are connected through a crossbar.
Cluster domain has 2 Arm® Cortex®-M7 cores that can work either in decoupled or lockstep
modes. Each core is identical in implementation and contains the same amount of
caches/Tightly Coupled Memory (TCM) memories that can be fully accessed even when
cores are working in lock-step modes.
The HSM includes one Arm® Cortex®-M0+.
Table 2. Processor cores
Core
Type
Cortex®-M7 Cluster 0
Main Core_1 (Boot)
Arm® Cortex®-M7
Main/Checker Core_2
Arm® Cortex®-M7
Hardware Security Module
Arm® Cortex®-M0+
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2.1.1
Introduction
Cortex®-M7
The Arm® Cortex®-M7 with double-precision FPU processor is a highly efficient highperformance core featuring:
•
Six-stage dual-issue pipeline
•
Dynamic branch prediction
•
Harvard architecture with L1 caches (8 Kbytes of I-cache and 16 Kbytes of D-cache)
•
64-bit AXI4 interface
•
64-bit ITCM interface
•
2x32-bit DTCM interfaces
The following memory interfaces are supported:
•
Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency
•
Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM
accesses
•
AXI Bus interface to optimize Burst transfers
•
Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.
The processor supports a set of DSP instructions, which allow efficient signal processing
and complex algorithm execution.
It also supports single and double precision FPU (floating-point unit) that speed up software
development by using metalanguage development tools, while avoiding saturation.
2.1.2
Cortex®-M0+
The Arm® Cortex®-M0+ processor is a low-power processor intended for deeply embedded
applications that require fast interrupt response features. It features low gate count, low
interrupt latency, and low-cost debug.
2.1.3
Memory hierarchy
The SR5E1x comprises different levels of memory hierarchy:
•
Memory private to each core: instruction cache, data cache and TCMs. TCMs are
unified. They provide fast access and have the most deterministic memory access
timing.
•
System RAM.
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2.2
RM0483
Features
•
AEC-Q100 automotive qualification
•
SR5 high-performance analog MCUs offering:
–
Digital and analog high-frequency control requested by new wide-bandgap
technologies (silicon carbide and GaN)
–
Superior real-time and functional safety performance (ASIL-D capability)
–
Built-in fast and cost optimized over-the-air (OTA) reprogramming capability (with
built-in dual image storage)
–
High-speed security cryptographic services (HSM)
Cores
•
2x 32-bit Arm® Cortex®-M7 with double-precision FPU, L1 cache and DSP instructions
running at up to 306.7 MHz to reach 1284 DMIPS/2.14 DMIPS/MHz/Core
(Dhrystone 2.1)
–
•
Split-lock configuration, allowing either two cores in parallel or one core in lockstep
configuration
2 DMA engines in lockstep configuration
Memories
•
Up to 2 MB on-chip flash memory with read while write support
–
1920 KB code flash memory split in two banks allowing 960 KB OTA (over-the-air)
reprogramming support
–
160 KB HSM dedicated code Flash memory
•
96 KB data Flash memory (64 KB + 32 KB dedicated to HSM)
•
488 KB on-chip general-purpose SRAM:
–
2× 32 KB instruction TCM + 2x 64 KB data TCM
–
256 KB system RAM
–
40 KB HSM dedicated system RAM
Security: hardware security module (HSM)
•
On-chip high performance security module with EVITA medium support with dedicated
RAM and flash
•
Based on Cortex®-M0+ cores running up to 153.35 MHz (half of the system frequency)
•
Hardware accelerator for symmetric cryptography
Safety
50/2075
•
Comprehensive new generation ASIL-D safety concept
•
State of the art safety measures at all level of the architecture for most efficient
implementation of ISO26262 ASIL-D functionalities
•
FCCU for collection and reaction to failure notifications with enhanced configurability
•
Memory error management unit (MEMU) for collection and reporting of error events in
memories
•
Cyclic redundancy check (CRC) unit
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Introduction
Enhanced peripherals for fast control loop capability
•
•
•
12 timers:
–
2× HRTIM (Hi-Resolution and complex waveform builder) in total: 12× 16-bit
counters, 104 ps resolution, 24 PWM
–
2× 16-bit 6-channel advanced control timers in total, with up to 12× PWM
–
2× 32-bit general purpose timers in total, with up to 8× IC/OC/PWM or pulse
counter and quadrature encoder input
–
4× 16-bit general purpose timers in total, with up to 11× PWM, 2 of which paired
–
2× 16-bit basic timers
Enhanced analog-to-digital converter system with:
–
5 separate 12-bit SAR analog converters, 8 channels each. Sampling rate up to
2.5 MSPS in single mode, 5 MSPS in dual mode
–
2 separate 16-bit sigma-delta analog converters
12-bit digital-to-analog converters (DAC)
–
2 buffered external channels 1 MSPS
–
8 unbuffered internal channels 15 MSPS
•
8 rail-to-rail analog comparators, 50 ns propagation delay
•
Hardware accelerator
–
1× CORDIC for trigonometric functions acceleration
Communication interfaces
•
4 modular controller area network (MCAN) modules, all supporting flexible data rate
(ISO CAN-FD)
•
3 UART modules with LIN functionality
•
4 serial peripheral interface (SPI) modules, 2 multiplexed with I²S interfaces
•
2 I²C modules
Advanced debug and trace for high performance automotive application
development
•
Built around Arm® CoreSight™-600
•
Debug interface: Arm® CoreSight™ JTAG (IEEE 1149.1) or SWD
•
4 KB Embedded Trace FIFO for both on- and off-chip tracing
•
Trace port for off-chip tracing: parallel trace port configurable from one to eight data
lines
Others
•
Power-efficiency management, through separate power modes for any selected cores,
peripherals, or memories
•
Boot assist flash (BAF) supports factory programming using a serial loader through
CAN or UART
•
Junction temperature range -40 °C to 150 °C
•
Integrated power supply scheme:
–
Integrated internal SMPS regulator
–
3.3 V supply & GPIOs
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Features list
The following table lists a summary of major features for the SR5E1x. A detailed description
of the functionality provided by each on-chip module is given later in this document.
Table 3. Features list
Feature
Description
Cortex®-M7 cluster 0
Number of cores / checker cores
2 decoupled cores in split mode / 1 core with checker core in lock
mode
Nominal frequency
300 MHz
Tightly coupled memory (TCM)
2 × 32 KB instruction in split mode or 1x 64 KB instruction in lock
mode
2 × 64 KB data in split mode or 1x 128 KB data in lock mode
Floating point unit
Single and double precision
Cache
8 KB instruction (2 ways)
16 KB data (4 ways)
System memories
On-chip code flash memory
2 MB
On-chip data flash memory
64 KB
Built-in memory replication for over the air
(OTA) reprogramming
Up to 960 KB Flash available
System RAM
2 × 128 KB (not including HSM dedicated data flash - see HSM)
Others
Multichannel DMA (paired in lockstep)
2 DMA engines, 8 streams each
Interrupt broadcasting system in lockstep
Up to 190 sources
Watchdogs
2 independent and 2 window watchdogs
Security: Hardware security module (HSM)
Core
Cortex®-M0+ @ 150 MHz, as half device frequency
C3 cryptography engine
Symmetric:
– AES-128/256, ECB, CBC, CMAC, GCM
– TRNG
Dedicated Flash memory
160 KB
Dedicated system RAM
40 KB
Dedicated data Flash
32 KB
Peripheral, IOs
Timer modules
High resolution timer
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2 modules, 6 × 16-bit channels each, 104 ps resolution
Up to 24× PWM signals (or 12× paired)
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Introduction
Table 3. Features list (continued)
Feature
Description
Advance control timer
2 modules, 16-bit timer
Up to 8 input capture, 12 output compare (8 of which paired)
General purpose timer
2 modules, 32-bit timer. Up to 8 input capture / output compare
4 modules, 16-bit timer. Up to 11 input capture / output compare (2 of
which paired)
Basic timer
2 modules, 16-bit timer
Enhanced analog-to-digital converter system
12-bit SAR analog converters
5 modules, 8 channels each
Fast conversion, up to 2.5 MSPS in single mode, 5 MSPS in dual
mode
16-bit sigma-delta analog converters
2 modules, 2 channels each (available only in QFP176 and QFP144
packages)
Output conversion rate of 333 ksps (OSR = 24)
12-bit analog comparators
8 modules, rail-to-rail, 50 ns propagation delay
12-bit digital-to-analog converters
2 buffered external channels, 1 MSPS
8 unbuffered internal digital-to-analog channels, 15 MSPS
HW accelerator
CORDIC (for trigonometric functions
acceleration)
1 module
Communication interfaces
UART modules (with LIN function)
3
MCAN supporting CAN-FD according to
ISO 11898-1 2015
4
CAN shared message RAM: 4 KB / MCAN (16 KB in total)
Serial peripheral interface (SPI)
4
I2C
2
SW development/emulation features
Arm® CoreSight™-600 libs
CoreSight™-600 libs for trace links, trace sink and control
components
CoreSight™-400 libs for debug and trace source components
Debug interfaces
Arm® CoreSight™-600 compliant
– Debug port (JTAG+SWD)
Trace types
Cortex®-M7 instruction and data trace
Off-chip trace
Arm® CoreSight™ parallel trace port
1 to 8 data lines
Advance cross trigger and performance
measurement
CoreSight-600™ CTI & CTM
Timestamp distribution
Arm® CoreSight™ timestamp generator
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Table 3. Features list (continued)
Feature
Description
Arm®
CoreSight™ authentication
Password challenge with HSM
Security
Debug controller
External tool-host CPU mailbox
Host-based debugging
Debug-under-reset
Others
Low power modes
Clock gating management for selected cores, peripherals, and/or
memories
Smart wake-up mechanisms through events or interrupts
Temperature sensor
Yes
Self test controller
Yes
PLL
2 individual PLLs: 1 with stable clock source for peripherals and 1
supporting frequency modulation for cores
Power supply
Single internal SMPS regulator for 3.3 V supply and GPIOs
Boot assisted Flash (BAF)
Supports factory programming using a serial loader through the
asynchronous CAN or UART
CRC channel(s)
1
2.4
Block diagram
The figure below shows the top-level block diagram.
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Introduction
Figure 2. Block diagram
Dashed Core is implemented as Split/Lock
configuration
All shadowed modules are in delayed
Lockstep configuration
Split/Lock
AF Mux + IOs Ring
AHBS
AHBS
Programmable Lockstep
I-Cache
Unit
NVIC
Unit
NVIC
Protocol Adapter
I-Cache
D-Cache
Protocol Adapter
Protocol Adapter
D-Cache
Protocol Adapter
DMA1
DMA2
FIFO
FIFO
Protocol Adapter
Debug Access Port
JTAG/SWD
Trace and Debug
Subsystem
Protocol Adapter
SMPU
Protocol Adapter
FLASH Bank1
Protocol Adapter
Protocol Adapter
Protocol Adapter
Protocol Adapter
AXI ITF
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Figure 3. Peripheral cluster source
RCC
CORDIC
DMA2
ADC3, ADC4, ADC5
DAC3
DAC4
COMP_ITF2
AHB2 – AHB Periphs Cluster 2 – 300 MHz
AHB1 – AHB Periphs Cluster 1 – 300 MHz
HSEM
CRC
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
GPIOG
GPIOH
GPIOI
DMA1
DMAMUX1
ADC1, ADC 2
BDAC
DAC1
DAC2
COMP_ITF1
WWDG 1
SYSCFG
WWDG 2
IWDG1
EXTI
SMPU
IWDG2
PRAMC1
CMU1,…,CMU5
PRAMC2
NVMPC1
RTC
TIM2
TIM3
NVMPC2
APB2 – APB Peripheral Cluster 2 – 150 MHz
APB1 – APB Peripheral Cluster 1 – 75 MHz
TIM6
TIM7
TIM_TS
I2C1
I2C2
SPI2
SPI3
UART2
UART3
MEMU2
IMA
CEM0... 14
FCCU
STCU3
Flash Reg Itf
Alt Flash Reg Itf
HSM2HOST Reg Itf
PLL_DIG
PMC_DIG
SSCM
PASS
TDM
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CMU0
TIM1_PWM
TIM8_PWM
TIM4
TIM5
TIM15
TIM16
SPI1
SPI4
UART1
SD_ADC1
SD_ADC2
CANSUBSYS
RM0483
System and memory overview
3
System and memory overview
3.1
System architecture
The main system consists of an AXI bus matrix that interconnects:
•
•
Up to 10 masters:
–
Cortex®-M7 core1 AXIM
–
Cortex®-M7 core1 AHB
–
Cortex®-M7 core2 AXIM
–
Cortex®-M7 core2 AHB
–
HSM
–
DMA1 AHB Master 1
–
DMA1 AHB Master 2
–
DMA2 AHB Master 1
–
DMA2 AHB Master 2
–
Trace and debug
Up to 14 slaves:
–
Internal flash memory on the dual ported flash Controller1
–
Internal flash memory on the dual ported flash controller2
–
Internal SRAM1
–
Internal SRAM2
–
AHB1 peripherals
–
AHB2 peripherals
–
APB1 peripherals
–
APB2 peripherals
–
HRTIM1 on AXI interface
–
HRTIM2 on AXI interface
–
Core1 and Core2 caches and TCMs via Cortex®-M7 AHBS buses
–
Trace and debug
The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously. This
architecture is shown in Figure 4:
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Figure 4. System architecture
Legend
AXIM
AHBP
DMA1
HSM
DTCM
64KB
32-bit bus
64-bit bus
AHB
AHB
DMA2
AHB
AHB
DAP
AHB
Bus multiplexer
Protocol Adaprter
AXI-AP
DMA2_AHBM2
DTCM
64KB
ITCM
32KB
DMA2_AHBM1
AHBP
Core2
Cortex-M7
I$
D$
8KB 16KB
DMA_MUX
DMA1_AHBM1
AXIM
ITCM
32KB
AHBS
DMA1_AHBM2
Core1
Cortex-M7
I$
D$
8KB 16KB
AHBS
TCM
AXI
AHB
APB
TCM
AXI
AHB
APB
Master interface
Slave interface
Flash Block1
1MB
Flash Block2
1MB
Sys RAM1
64KB
Sys RAM2
64KB
AHB1
bridge
AHB1
periphs
AHB2
bridge
AHB2
periphs
AHB-APB1
bridge
APB1
periphs
AHB-APB2
bridge
APB2
periphs
HRTIM1
HRTIM2
APBDEBUG
3.1.1
TCM buses
The DTCM and ITCM (data and instruction tightly coupled RAMs) are connected through
dedicated TCM buses directly to a Cortex®-M7 core. The DMA controllers can access the
DTCM and ITCM through AHBS, a specific CPU slave AHB. An ITCMx is accessed by its
related Cortex®-M7 corex at CPU clock speed, with zero wait states.
3.1.2
CPU buses
Cortex®-M7 AXIM bus
The Cortex®-M7 CPU uses the 64-bit AXIM bus to access all memories (excluding ITCM
and DTCM) and HRTIMs peripherals.
The AXIM bus connects the CPU to the AXI bus matrix.
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System and memory overview
Cortex®-M7 ITCM bus
The Cortex®-M7 CPU uses the 64-bit ITCM bus for fetching instructions from and accessing
data in the ITCM.
Cortex®-M7 DTCM bus
The Cortex®-M7 CPU uses the 2x32-bit DTCM bus for accessing data in the DTCM. The
2x32-bit DTCM bus allows load/load and load/store instruction pairs to be dual-issued on
the DTCM memory. It can also fetch instructions.
Cortex®-M7 AHBS bus
The Cortex®-M7 CPU uses the 32-bit AHBS slave bus to allow the DMA controller, and
other masters, to access the ITCM and the DTCM.
Cortex®-M7 AHBP bus
The Cortex®-M7 CPU uses the 32-bit AHBP bus for accessing AHB1, AHB2, APB1 and
APB2 peripherals.
3.1.3
Bus master peripherals
DMA1 and DMA2 controllers
Each DMA controller (DMA1 and DMA2) has 32-bit master bus interfaces connected to AXI
bus matrix.
The master bus interfaces allow DMA data transfers between two peripherals, between two
memories or between a peripheral and a memory. Through the system bus matrices, the
master bus interfaces can access all internal memories, including the ITCMs and DTCMs
and all AHB and APB peripherals.
HSM
The HSM has one 32-bit bus interface connected to the AXI bus matrix.
3.1.4
TCM memories
Each ITCM and DTCM memory is accessible in two areas through different paths:
•
•
3.2
Direct mode access, through the internal bus, providing a fast access to the core to its
TCMs:
–
ITCM for instruction fetching in the range 0x0000_0000 - 0x0000_FFFF.
–
DTCM for data accesses in the range 0x2000_0000 - 0x2001_FFFF.
Indirect mode access, through the interconnect matrix, providing access to external
masters (other core and DMA modules). Refer to Table 7.
Memory organization
Table 4 and Figure 5 show the device memory map for SR5E1x.
All addresses on the SR5E1x, including the reserved, are identified. The addresses
represent the physical address assigned to each region or module. If a memory access,
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either read or write, is attempted to any region marked as ‘Reserved’, then it results in a
transfer error.
Table 4. Memory map overview
Start address
End address
Description
0x0000_0000
0x1FFF_FFFF
Cortex block0 code area, see Table 5: Flash memory map
0x2000_0000
0x3FFF_FFFF
Cortex block1 SRAM area, see Table 6: RAMs memory map
0x4000_0000
0x5FFF_FFFF
Cortex block2 Peripherals area, see Table 7: Peripherals
memory map
0x6000_0000
0x7FFF_FFFF
Cortex block 3 area, see Table 8: CoreSight™ components
memory map
0x8000_0000
0x9FFF_FFFF
Reserved
0xA000_0000
0xBFFF_FFFF
Cortex block5 area, see Table 9: AXI interfaces memory
map
0xC000_0000
0xDFFF_FFFF
Reserved
0xE000_0000
0xFFFF_FFFF
Cortex M7 internal peripherals
Table 5 is the detailed flash memory map for the SR5E1x.
Table 5. Flash memory map
Description
Used size
[Kbyte]
Start address
End address
0x0000_0000
0x0000_7FFF
Alias region for ITCM (direct mode
access)(1)
—
0x0000_8000
0x0002_7FFF
Alias region for HSM code(2)
—
0x0002_8000
0x07FF_FFFF
Reserved
—
Flash code 1
0x0800_0000
0x0800_FFFF
Flash code 1 (low block B1F0)
64
0x0801_0000
0x0801_FFFF
Flash code 1 (low block B1F1)
64
0x0802_0000
0x0802_FFFF
Flash code 1 (low block B1F2)
64
0x0803_0000
0x0806_FFFF
Flash code 1 (A256 block B1F3)
256
0x0807_0000
0x080A_FFFF
Flash code 1 (A256 block B1F4)
256
0x080B_0000
0x080E_FFFF
Flash code 1 (A256 block B1F5)
256
Flash code 2
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0x080F_0000
0x080F_FFFF
Flash code 2 (low block B2F0)
64
0x0810_0000
0x0810_FFFF
Flash code 2 (low block B2F1)
64
0x0811_0000
0x0811_FFFF
Flash code 2 (low block B2F2)
64
0x0812_0000
0x0815_FFFF
Flash code 2 (A256 block B2F3)
256
0x0816_0000
0x0819_FFFF
Flash code 2 (A256 block B2F4)
256
0x081A_0000
0x081D_FFFF
Flash code 2 (A256 block B2F5)
256
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System and memory overview
Table 5. Flash memory map (continued)
Description
Used size
[Kbyte]
Start address
End address
0x081E_0000
0x08EF_FFFF
Reserved
—
0x08F0_0000
0x08F0_3FFF
Data Flash (high block, D0_00)
16
0x08F0_4000
0x08F0_7FFF
Data Flash (high block, D0_01)
16
0x08F0_8000
0x08F0_BFFF
Data Flash (high block, D0_02)
16
0x08F0_C000
0x08F0_FFFF
Data Flash (high block, D0_03)
16
0x08F1_0000
0x17FF_FFFF
Reserved
—
0x1800_0000
0x1800_7FFF
HSM code flash (B0F0)
32
0x1800_8000
0x1801_7FFF
HSM code flash (B0F1)
64
0x1801_8000
0x1802_7FFF
HSM code flash (B0F2)
64
0x1802_8000
0x18EF_FFFF
Reserved
—
0x18F0_0000
0x18F0_3FFF
HSM data flash (mid block, D0_04)
16
0x18F0_4000
0x18F0_7FFF
HSM data flash (mid block, D0_05)
16
0x18F0_8000
0x1FEF_FFFF
Reserved
—
0x1FF0_0000
0x1FF0_3FFF
BAF
16
0x1FF0_4000
0x1FF7_FFFF
Reserved
—
0x1FF8_0000
0x1FF8_3FFF
UTest
16
0x1FF8_4000
0x1FFB_C27F
Reserved
—
0x1FFB_C280
0x1FFB_C2FF
Error locations for RWR1
—
0x1FFB_C300
0x1FFF_FFFF
Reserved
—
1. Used size of 32 Kbytes (local region) with direct access by M7 core in split mode. When Core1 and Core2
are in lockstep mode, the Core2 ITCM is connected to the Core1 ITCM interface and remapped in order to
offer a continuous memory space of 64 Kbytes (local region: 0x0000_0000—0x0000_FFFF) of ITCM to
Core1. Reserved for other masters.
2. Used size of 160 Kbytes (local region: 0x0000_0000--0x0002_7FFF) with direct access by M0+ core of
HSM. Reserved for other masters. The HSM code is mapped and compiled in its local region and stored in
the flash (B0F0, B0F1, B0F2). When Core1 and Core2 are in lockstep mode, no conflict for access by the
HSM.
Table 6. RAMs memory map
Start address
End address
Description
Used size
[Kbyte]
0x2000_0000
0x2001_FFFF
Alias region for Cortex M7 DTCM (direct
mode access)
64
0x2002_0000
0x23FF_FFFF
Reserved
—
0x2400_0000
0x2401_FFFF
SRAM1
128
0x2402_0000
0x2403_FFFF
SRAM2
128
0x2404_0000
0x3FFF_FFFF
Reserved
—
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Table 7. Peripherals memory map
Start address
End address
Description
Used size
[Kbyte]
0x4000_0000
0x4001_FFFF
APB1 peripherals, see Table 10: APB1
peripherals mapping table.
128
0x4002_0000
0x41FF_FFFF
Reserved
—
0x4200_0000
0x4201_FFFF
APB2 peripherals, see Table 11: APB2
peripherals mapping table.
128
0x4202_0000
0x43FF_FFFF
Reserved
—
0x4400_0000
0x4400_FFFF
AHB1 peripherals, see Table 12: AHB1
peripherals mapping table.
64
0x4401_0000
0x47FF_FFFF
Reserved
—
0x4800_0000
0x4800_FFFF
AHB2 peripherals, see Table 13: AHB2
peripherals mapping table.
64
0x4801_0000
0x59FF_FFFF
Reserved
—
0x5A00_0000
0x5A00_7FFF
Core1 ITCM (indirect mode access)
32
0x5A00_8000
0x5A00_FFFF
Reserved (split mode)
Core1 ITCM extension (LS) (indirect
mode access)
32
0x5A01_00
0x5A03_FFFF
Reserved
—
0x5A04_0000
0x5A04_7FFF
Core2 ITCM (split mode) (indirect mode
access)
Reserved (LS)
32
0x5A04_8000
0x5BFF_FFFF
Reserved
—
0x5C00_0000
0x5C00_FFFF
Core1 DTCM (indirect mode access)
64
0x5C01_0000
0x5C01_FFFF
Reserved (split mode)
Core1 DTCM extension (LS) (indirect
mode access)
64
0x5C02_0000
0x5C03_FFFF
Reserved
—
0x5C04_0000
0x5C04_FFFF
Reserved
Core2 DTCM (split mode) (indirect mode
access)
64
0x5C05_0000
0x5FFF_FFFF
Reserved
—
Table 8. CoreSight™ components memory map
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Description
Used size
[Kbyte]
Start address
End address
0x6000_0000
—
DAP ROM Table
—
0x6010_0000
—
CoreSight™ ROM Table
—
0x7000_0000
—
DBGMCU
—
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System and memory overview
Table 9. AXI interfaces memory map
Description
Used size
[Kbyte]
Start address
End address
0xA000_0000
0xA000_3FFF
HRTIM1
—
0xA000_4000
0xA000_7FFF
HRTIM2
—
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Figure 5. Memory mapping
0xFFFF_FFFF
block7
Reserved
512-Mbyte
block7
Cortex®-M7 internal peripherals
0x2402_0000
0x2401_FFFF
block1
SRAM1 (128 KB)
0xE000_0000
0xDFFF_FFFF
Reserved
Alias region for M7 D-TCM
512-Mbyte
Reserved
block6
0xC000_0000
0xBFFF_FFFF
Reserved
Reserved for non-M7 master
Reserved
0x1FF8_4000
Utest(16 K)
Error locations for RWW0 (0x1FF8_0280 - 0x1FF0_02FF)
Reserved
HRTIM2
HRTIM1
0xA000_4000
0xA000_00000
0x2400_0000
0x23FF_FFFF
0x2002_0000
0x2001_FFFF
0x2000_0000
0x1FFF_FFFF
0x1FFB_C2FF
0x1FFB_C280
Error locations RWR1
0xA000_9000
block5
0x2404_0000
0x2403_FFFF
SRAM2 (128 KB)
0x1FF8_0000
0x1FF0_4000
BCS (16K)
x1FF0_0000
Reserved
0x9FFF_FFFF
0x18F0_8000
512-Mbyte
Reserved
block4
HSM data fash (32 KB)
0x1802_8000
HSM code flash (160 KB)
0x8000_0000
0x7FFF_FFFF
0x1800_0000
Reserved
Reserved
0x08F1_0000
Data flash (64 KB)
0x7000_1000
0x7000_0000
DBGMCU (*)
block3
0x18F0_0000
Reserved
block0
0x08F0_0000
Reserved
0x081E_0000
Flash code2 (960 KB)
Coresight® ROM table (from external tool and internal cores)
0x6010_0000
DAP ROM table (from external tool)
0x6000_0000
0x5FFF_FFFF
0x5C04_FFFF
0x5C04_0000
Reserved (64 KB) - NO_LS
DTCM1 (64 KB) - NO_LS
0x5C00_FFFF (NO_LS) / 0x5C01_FFFF (LS)
0x5C00_0000
0x0002_8000
Reserved for non-HSM master
Alias region for HSM code flash
DTCM2 (64 KB) - NO_LS
0x0800_0000
Reserved
Reserved
Reserved (LS)
0x080F_0000
Flash code1 (960 KB)
Alias region for
M7 ITCM
Reserved for non M7
master
0x0000_8000
0x0000_0000
Reserved
DTCM1 (128 KB) - LS
Reserved
0x5A04_8000
Reserved - LS
block2
ITCM2 (32 KB) - NO_LS
Reserved
Reserved - NO_LS
ITCM1 (32 KB) - NO_LS
ITCM1 (64 KB) - LS
0x5A04_0000
0x5A00_8000
0x5A00_7FFF (NO_LS) / 0x5A00_FFFF (LS)
0x5A00_0000
Reserved
AHB2 (64K)
AHB1 (64K)
APB2 (128KB)
APB1 (128KB)
64/2075
0x4801_0000
0x4800_FFFF
0x4800_0000
0x4401_0000
0x4400_FFFF
0x4400_0000
0x4202_0000
0x4201_FFFF
0x4200_0000
0x4002_0000
0x4001_FFFF
0x4000_0000
RM0483 Rev 5
(*) This is the address space of DBGMCU seen through a
system bus.
Note:
DBGMCU is a CoreSight™ component, addressable by
CoreSight™ ROM.
DBGMCU can be seen also at address 0x6000_0000 for
accesses via the debug interface following the debug ROM
table addressing (DAP ROM → APB-AP → DBGMCU).
Refer to the debug documentation for details.
RM0483
System and memory overview
Table 10. APB1 peripherals mapping table
Start address
End address
Index
Peripheral
0x4001 FC00
0x4001 FFFF
127
—
0x4001 F800
0x4001 FBFF
126
—
0x4001 F400
0x4001 F7FF
125
TDM
0x4001 F000
0x4001 F3FF
124
PASS
0x4001 EC00
0x4001 EFFF
123
SSCM
0x4001 E800
0x4001 EBFF
122
—
0x4001 E400
0x4001 E7FF
121
—
0x4001 E000
0x4001 E3FF
120
—
0x4001 DC00
0x4001 DFFF
119
—
0x4001 D800
0x4001 DBFF
118
PLL_DIG
0x4001 D400
0x4001 D7FF
117
—
0x4001 D000
0x4001 D3FF
116
PMU_DIG
0x4001 CC00
0x4001 CFFF
115
—
0x4001 C800
0x4001 CBFF
114
HSM2HOST itf (Host side)
0x4001 C400
0x4001 C7FF
113
—
0x4001 C000
0x4001 C3FF
112
AF Flash Reg interface
0x4001 BC00
0x4001 BFFF
111
—
0x4001 B800
0x4001 BBFF
110
—
0x4001 B400
0x4001 B7FF
109
—
0x4001 B000
0x4001 B3FF
108
—
0x4001 AC00
0x4001 AFFF
107
—
0x4001 A800
0x4001 ABFF
106
—
0x4001 A400
0x4001 A7FF
105
—
0x4001 A000
0x4001 A3FF
104
—
0x4001 9C00
0x4001 9FFF
103
—
0x4001 9800
0x4001 9BFF
102
—
0x4001 9400
0x4001 97FF
101
—
0x4001 9000
0x4001 93FF
100
—
0x4001 8C00
0x4001 8FFF
99
—
0x4001 8800
0x4001 8BFF
98
—
0x4001 8400
0x4001 87FF
97
—
0x4001 8000
0x4001 83FF
96
Flash Reg itf
0x4001 7C00
0x4001 7FFF
95
—
0x4001 7800
0x4001 7BFF
94
—
0x4001 7400
0x4001 77FF
93
—
RM0483 Rev 5
65/2075
77
System and memory overview
RM0483
Table 10. APB1 peripherals mapping table (continued)
66/2075
Start address
End address
Index
Peripheral
0x4001 7000
0x4001 73FF
92
—
0x4001 6C00
0x4001 6FFF
91
—
0x4001 6800
0x4001 6BFF
90
—
0x4001 6400
0x4001 67FF
89
—
0x4001 6000
0x4001 63FF
88
—
0x4001 5C00
0x4001 5FFF
87
—
0x4001 5800
0x4001 5BFF
86
—
0x4001 5400
0x4001 57FF
85
—
0x4001 5000
0x4001 53FF
84
—
0x4001 4C00
0x4001 4FFF
83
—
0x4001 4800
0x4001 4BFF
82
—
0x4001 4400
0x4001 47FF
81
—
0x4001 4000
0x4001 43FF
80
0x4001 3C00
0x4001 3FFF
79
0x4001 3800
0x4001 3BFF
78
0x4001 3400
0x4001 37FF
77
0x4001 3000
0x4001 33FF
76
0x4001 2C00
0x4001 2FFF
75
0x4001 2800
0x4001 2BFF
74
0x4001 2400
0x4001 27FF
73
0x4001 2000
0x4001 23FF
72
0x4001 1C00
0x4001 1FFF
71
0x4001 1800
0x4001 1BFF
70
0x4001 1400
0x4001 17FF
69
0x4001 1000
0x4001 13FF
68
0x4001 0C00
0x4001 0FFF
67
0x4001 0800
0x4001 0BFF
66
0x4001 0400
0x4001 07FF
65
0x4001 0000
0x4001 03FF
64
0x4000 FC00
0x4000 FFFF
63
FCCU
0x4000 F800
0x4000 FBFF
62
—
0x4000 F400
0x4000 F43F
0x4000 F440
0x4000 F47F
0x4000 F480
0x4000 F4BF
STCU3
CEM0
61
RM0483 Rev 5
CEM1
CEM2
RM0483
System and memory overview
Table 10. APB1 peripherals mapping table (continued)
Start address
End address
Index
0x4000 F4C0
0x4000 F4FF
CEM3
0x4000 F500
0x4000 F53F
CEM4
0x4000 F540
0x4000 F57F
CEM5
0x4000 F580
0x4000 F5BF
CEM6
0x4000 F5C0
0x4000 F5FF
CEM7
0x4000 F600
0x4000 F63F
0x4000 F640
0x4000 F67F
0x4000 F680
0x4000 F6BF
CEM10
0x4000 F6C0
0x4000 F6FF
CEM11
0x4000 F700
0x4000 F73F
CEM12
0x4000 F740
0x4000 F77F
CEM13
0x4000 F780
0x4000 F7BF
CEM14
0x4000 F000
0x4000 F3FF
60
IMA
0x4000 EC00
0x4000 EFFF
59
—
0x4000 E800
0x4000 EBFF
58
—
0x4000 E400
0x4000 E7FF
57
0x4000 E000
0x4000 E3FF
56
0x4000 DC00
0x4000 DFFF
55
0x4000 D800
0x4000 DBFF
54
0x4000 D400
0x4000 D7FF
53
0x4000 D000
0x4000 D3FF
52
0x4000 CC00
0x4000 CFFF
51
0x4000 C800
0x4000 CBFF
50
0x4000 C400
0x4000 C7FF
49
0x4000 C000
0x4000 C3FF
48
0x4000 BC00
0x4000 BFFF
47
—
0x4000 B800
0x4000 BBFF
46
—
0x4000 B400
0x4000 B7FF
45
—
0x4000 B000
0x4000 B3FF
44
—
0x4000 AC00
0x4000 AFFF
43
—
0x4000 A800
0x4000 ABFF
42
—
0x4000 A400
0x4000 A7FF
41
—
0x4000 A000
0x4000 A3FF
40
—
0x4000 9C00
0x4000 9FFF
39
—
0x4000 9800
0x4000 9BFF
38
—
61
RM0483 Rev 5
Peripheral
CEM8
CEM9
MEMU2
67/2075
77
System and memory overview
RM0483
Table 10. APB1 peripherals mapping table (continued)
68/2075
Start address
End address
Index
Peripheral
0x4000 9400
0x4000 97FF
37
—
0x4000 9000
0x4000 93FF
36
—
0x4000 8C00
0x4000 8FFF
35
—
0x4000 8800
0x4000 8BFF
34
—
0x4000 8400
0x4000 87FF
33
—
0x4000 8000
0x4000 83FF
32
—
0x4000 7C00
0x4000 7FFF
31
—
0x4000 7800
0x4000 7BFF
30
—
0x4000 7400
0x4000 77FF
29
—
0x4000 7000
0x4000 73FF
28
UART3
0x4000 6C00
0x4000 6FFF
27
UART2
0x4000 6800
0x4000 6BFF
26
—
0x4000 6400
0x4000 67FF
25
—
0x4000 6000
0x4000 63FF
24
SPI3
0x4000 5C00
0x4000 5FFF
23
SPI2
0x4000 5800
0x4000 5BFF
22
I2C2
0x4000 5400
0x4000 57FF
21
I2C1
0x4000 5000
0x4000 53FF
20
—
0x4000 4C00
0x4000 4FFF
19
TIM_TS
0x4000 4800
0x4000 4BFF
18
TIM7
0x4000 4400
0x4000 47FF
17
TIM6
0x4000 4000
0x4000 43FF
16
TIM3
0x4000 3C00
0x4000 3FFF
15
TIM2
0x4000 3800
0x4000 3BFF
14
—
0x4000 3400
0x4000 37FF
13
—
0x4000 3000
0x4000 33FF
12
—
0x4000 2C00
0x4000 2FFF
11
—
0x4000 2800
0x4000 2BFF
10
RTC
0x4000 2400
0x4000 27FF
9
—
0x4000 2000
0x4000 23FF
8
CMU1…CMU5
0x4000 1C00
0x4000 1FFF
7
—
0x4000 1800
0x4000 1BFF
6
—
0x4000 1400
0x4000 17FF
5
IWDG2
0x4000 1000
0x4000 13FF
4
IWDG1
0x4000 0C00
0x4000 0FFF
3
—
RM0483 Rev 5
RM0483
System and memory overview
Table 10. APB1 peripherals mapping table (continued)
Start address
End address
Index
Peripheral
0x4000 0800
0x4000 0BFF
2
—
0x4000 0400
0x4000 07FF
1
WWDG2
0x4000 0000
0x4000 03FF
0
WWDG1
Table 11. APB2 peripherals mapping table
Start address
End address
Index
Peripheral
0x4201 FC00
0x4201 FFFF
127
—
0x4201 F800
0x4201 FBFF
126
—
0x4201 F400
0x4201 F7FF
125
—
0x4201 F000
0x4201 F3FF
124
—
0x4201 EC00
0x4201 EFFF
123
—
0x4201 E800
0x4201 EBFF
122
—
0x4201 E400
0x4201 E7FF
121
—
0x4201 E000
0x4201 E3FF
120
—
0x4201 DC00
0x4201 DFFF
119
—
0x4201 D800
0x4201 DBFF
118
—
0x4201 D400
0x4201 D7FF
117
—
0x4201 D000
0x4201 D3FF
116
—
0x4201 CC00
0x4201 CFFF
115
—
0x4201 C800
0x4201 CBFF
114
—
0x4201 C400
0x4201 C7FF
113
—
0x4201 C000
0x4201 C3FF
112
—
0x4201 BC00
0x4201 BFFF
111
—
0x4201 B800
0x4201 BBFF
110
—
0x4201 B400
0x4201 B7FF
109
—
0x4201 B000
0x4201 B3FF
108
—
0x4201 AC00
0x4201 AFFF
107
—
0x4201 A800
0x4201 ABFF
106
—
0x4201 A400
0x4201 A7FF
105
—
0x4201 A000
0x4201 A3FF
104
—
0x4201 9C00
0x4201 9FFF
103
—
0x4201 9800
0x4201 9BFF
102
—
0x4201 9400
0x4201 97FF
101
—
0x4201 9000
0x4201 93FF
100
—
0x4201 8C00
0x4201 8FFF
99
—
RM0483 Rev 5
69/2075
77
System and memory overview
RM0483
Table 11. APB2 peripherals mapping table (continued)
70/2075
Start address
End address
Index
Peripheral
0x4201 8800
0x4201 8BFF
98
—
0x4201 8400
0x4201 87FF
97
—
0x4201 8000
0x4201 83FF
96
—
0x4201 7C00
0x4201 7FFF
95
—
0x4201 7800
0x4201 7BFF
94
—
0x4201 7400
0x4201 77FF
93
—
0x4201 7000
0x4201 73FF
92
—
0x4201 6C00
0x4201 6FFF
91
—
0x4201 6800
0x4201 6BFF
90
—
0x4201 6400
0x4201 67FF
89
—
0x4201 6000
0x4201 63FF
88
—
0x4201 5C00
0x4201 5FFF
87
—
0x4201 5800
0x4201 5BFF
86
—
0x4201 5400
0x4201 57FF
85
—
0x4201 5000
0x4201 53FF
84
—
0x4201 4C00
0x4201 4FFF
83
—
0x4201 4800
0x4201 4BFF
82
—
0x4201 4400
0x4201 47FF
81
—
0x4201 4000
0x4201 43FF
80
—
0x4201 3C00
0x4201 3FFF
79
—
0x4201 3800
0x4201 3BFF
78
—
0x4201 3400
0x4201 37FF
77
—
0x4201 3000
0x4201 33FF
76
—
0x4201 2C00
0x4201 2FFF
75
—
0x4201 2800
0x4201 2BFF
74
—
0x4201 2400
0x4201 27FF
73
—
0x4201 2000
0x4201 23FF
72
—
0x4201 1C00
0x4201 1FFF
71
—
0x4201 1800
0x4201 1BFF
70
—
0x4201 1400
0x4201 17FF
69
—
0x4201 1000
0x4201 13FF
68
—
0x4201 0C00
0x4201 0FFF
67
—
0x4201 0800
0x4201 0BFF
66
—
0x4201 0400
0x4201 07FF
65
—
0x4201 0000
0x4201 03FF
64
—
RM0483 Rev 5
RM0483
System and memory overview
Table 11. APB2 peripherals mapping table (continued)
Start address
End address
Index
0x4200 FC00
0x4200 FFFF
63
0x4200 F800
0x4200 FBFF
62
0x4200 F400
0x4200 F7FF
61
0x4200 F000
0x4200 F3FF
60
0x4200 EC00
0x4200 EFFF
59
0x4200 E800
0x4200 EBFF
58
0x4200 E400
0x4200 E7FF
57
0x4200 E000
0x4200 E3FF
56
0x4200 DC00
0x4200 DFFF
55
0x4200 D800
0x4200 DBFF
54
0x4200 D400
0x4200 D7FF
53
0x4200 D000
0x4200 D3FF
52
0x4200 CC00
0x4200 CFFF
51
0x4200 C800
0x4200 CBFF
50
0x4200 C400
0x4200 C7FF
49
0x4200 C000
0x4200 C3FF
48
0x4200 BC00
0x4200 BFFF
47
0x4200 B800
0x4200 BBFF
46
0x4200 B400
0x4200 B7FF
45
0x4200 B000
0x4200 B3FF
44
0x4200 AC00
0x4200 AFFF
43
0x4200 A800
0x4200 ABFF
42
0x4200 A400
0x4200 A7FF
41
0x4200 A000
0x4200 A3FF
40
0x4200 9C00
0x4200 9FFF
39
—
0x4200 9800
0x4200 9BFF
38
—
0x4200 9400
0x4200 97FF
37
—
0x4200 9000
0x4200 93FF
36
—
0x4200 8C00
0x4200 8FFF
35
—
0x4200 8800
0x4200 8BFF
34
—
0x4200 8400
0x4200 87FF
33
SD_ADC2
0x4200 8000
0x4200 83FF
32
SD_ADC1
0x4200 7C00
0x4200 7FFF
31
—
0x4200 7800
0x4200 7BFF
30
—
0x4200 7400
0x4200 77FF
29
—
RM0483 Rev 5
Peripheral
FDCANs Message RAM (16K)
FDCAN4
FDCAN3
FDCAN2
FDCAN1
71/2075
77
System and memory overview
RM0483
Table 11. APB2 peripherals mapping table (continued)
Start address
End address
Index
Peripheral
0x4200 7000
0x4200 73FF
28
—
0x4200 6C00
0x4200 6FFF
27
UART1
0x4200 6800
0x4200 6BFF
26
—
0x4200 6400
0x4200 67FF
25
—
0x4200 6000
0x4200 63FF
24
SPI4
0x4200 5C00
0x4200 5FFF
23
SPI1
0x4200 5800
0x4200 5BFF
22
—
0x4200 5400
0x4200 57FF
21
—
0x4200 5000
0x4200 53FF
20
—
0x4200 4C00
0x4200 4FFF
19
—
0x4200 4800
0x4200 4BFF
18
TIM16
0x4200 4400
0x4200 47FF
17
TIM15
0x4200 4000
0x4200 43FF
16
TIM5
0x4200 3C00
0x4200 3FFF
15
TIM4
0x4200 3800
0x4200 3BFF
14
—
0x4200 3400
0x4200 37FF
13
—
0x4200 3000
0x4200 33FF
12
TIM8_PWM
0x4200 2C00
0x4200 2FFF
11
TIM1_PWM
0x4200 2800
0x4200 2BFF
10
—
0x4200 2400
0x4200 27FF
9
—
0x4200 2000
0x4200 23FF
8
CMU0
0x4200 1C00
0x4200 1FFF
7
NVMPC2
0x4200 1800
0x4200 1BFF
6
NVMPC1
0x4200 1400
0x4200 17FF
5
PRAMC2
0x4200 1000
0x4200 13FF
4
PRAMC1
0x4200 0C00
0x4200 0FFF
3
0x4200 0800
0x4200 0BFF
2
0x4200 0400
0x4200 07FF
1
EXTI
0x4200 0000
0x4200 03FF
0
SYSCFG
SMPU
Table 12. AHB1 peripherals mapping table
72/2075
Start address
End address
Index
Peripheral
0x4400 FC00
0x4400 FFFF
63
—
0x4400 F800
0x4400 FBFF
62
—
0x4400 F400
0x4400 F7FF
61
—
RM0483 Rev 5
RM0483
System and memory overview
Table 12. AHB1 peripherals mapping table (continued)
Start address
End address
Index
Peripheral
0x4400 F000
0x4400 F3FF
60
—
0x4400 EC00
0x4400 EFFF
59
—
0x4400 E800
0x4400 EBFF
58
—
0x4400 E400
0x4400 E7FF
57
—
0x4400 E000
0x4400 E3FF
56
—
0x4400 DC00
0x4400 DFFF
55
—
0x4400 D800
0x4400 DBFF
54
—
0x4400 D400
0x4400 D7FF
53
—
0x4400 D000
0x4400 D3FF
52
—
0x4400 CC00
0x4400 CFFF
51
—
0x4400 C800
0x4400 CBFF
50
—
0x4400 C400
0x4400 C7FF
49
—
0x4400 C000
0x4400 C3FF
48
—
0x4400 BC00
0x4400 BFFF
47
—
0x4400 B800
0x4400 BBFF
46
—
0x4400 B400
0x4400 B7FF
45
—
0x4400 B000
0x4400 B3FF
44
COMP2_dig
(managing 4 compa ana)
0x4400 AC00
0x4400 AFFF
43
—
0x4400 A800
0x4400 ABFF
42
—
0x4400 A400
0x4400 A7FF
41
—
0x4400 A000
0x4400 A3FF
40
—
0x4400 9C00
0x4400 9FFF
39
—
0x4400 9800
0x4400 9BFF
38
DAC4 (CH1 + CH2) (Fast)
0x4400 9400
0x4400 97FF
37
DAC3 (CH1 + CH2) (Fast)
0x4400 9000
0x4400 93FF
36
—
0x4400 8C00
0x4400 8FFF
35
—
0x4400 8800
0x4400 8BFF
34
—
0x4400 8400
0x4400 87FF
33
—
0x4400 8000
0x4400 83FF
32
ADC3 - ADC4 - ADC5
0x4400 7C00
0x4400 7FFF
31
—
0x4400 7800
0x4400 7BFF
30
—
0x4400 7400
0x4400 77FF
29
—
0x4400 7000
0x4400 73FF
28
—
0x4400 6C00
0x4400 6FFF
27
—
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System and memory overview
RM0483
Table 12. AHB1 peripherals mapping table (continued)
Start address
End address
Index
Peripheral
0x4400 6800
0x4400 6BFF
26
—
0x4400 6400
0x4400 67FF
25
—
0x4400 6000
0x4400 63FF
24
—
0x4400 5C00
0x4400 5FFF
23
—
0x4400 5800
0x4400 5BFF
22
—
0x4400 5400
0x4400 57FF
21
—
0x4400 5000
0x4400 53FF
20
—
0x4400 4C00
0x4400 4FFF
19
—
0x4400 4800
0x4400 4BFF
18
—
0x4400 4400
0x4400 47FF
17
—
0x4400 4000
0x4400 43FF
16
DMA2
0x4400 3C00
0x4400 3FFF
15
—
0x4400 3800
0x4400 3BFF
14
—
0x4400 3400
0x4400 37FF
13
CORDIC
0x4400 3000
0x4400 33FF
12
CRC
0x4400 2C00
0x4400 2FFF
11
HSEM
0x4400 2800
0x4400 2BFF
10
—
0x4400 2400
0x4400 27FF
9
—
0x4400 2000
0x4400 23FF
8
—
0x4400 1C00
0x4400 1FFF
7
—
0x4400 1800
0x4400 1BFF
6
—
0x4400 1400
0x4400 17FF
5
—
0x4400 1000
0x4400 13FF
4
—
0x4400 0C00
0x4400 0FFF
3
—
0x4400 0800
0x4400 0BFF
2
—
0x4400 0400
0x4400 07FF
1
—
0x4400 0000
0x4400 03FF
0
RCC
Table 13. AHB2 peripherals mapping table
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Start address
End address
Index
Peripheral
0x4800 FC00
0x4800 FFFF
63
—
0x4800 F800
0x4800 FBFF
62
—
0x4800 F400
0x4800 F7FF
61
—
0x4800 F000
0x4800 F3FF
60
—
0x4800 EC00
0x4800 EFFF
59
—
RM0483 Rev 5
RM0483
System and memory overview
Table 13. AHB2 peripherals mapping table (continued)
Start address
End address
Index
Peripheral
0x4800 E800
0x4800 EBFF
58
—
0x4800 E400
0x4800 E7FF
57
—
0x4800 E000
0x4800 E3FF
56
—
0x4800 DC00
0x4800 DFFF
55
—
0x4800 D800
0x4800 DBFF
54
—
0x4800 D400
0x4800 D7FF
53
—
0x4800 D000
0x4800 D3FF
52
—
0x4800 CC00
0x4800 CFFF
51
—
0x4800 C800
0x4800 CBFF
50
—
0x4800 C400
0x4800 C7FF
49
—
0x4800 C000
0x4800 C3FF
48
—
0x4800 BC00
0x4800 BFFF
47
—
0x4800 B800
0x4800 BBFF
46
—
0x4800 B400
0x4800 B7FF
45
—
0x4800 B000
0x4800 B3FF
44
COMP1_dig
(managing 4 compa ana)
0x4800 AC00
0x4800 AFFF
43
—
0x4800 A800
0x4800 ABFF
42
—
0x4800 A400
0x4800 A7FF
41
—
0x4800 A000
0x4800 A3FF
40
—
0x4800 9C00
0x4800 9FFF
39
—
0x4800 9800
0x4800 9BFF
38
DAC2 (CH1 + CH2) (Fast)
0x4800 9400
0x4800 97FF
37
DAC1 (CH1 + CH2) (Fast)
0x4800 9000
0x4800 93FF
36
B-DAC1 (CH1 + CH2) (external)
0x4800 8C00
0x4800 8FFF
35
—
0x4800 8800
0x4800 8BFF
34
—
0x4800 8400
0x4800 87FF
33
—
0x4800 8000
0x4800 83FF
32
ADC1 - ADC2
0x4800 7C00
0x4800 7FFF
31
—
0x4800 7800
0x4800 7BFF
30
—
0x4800 7400
0x4800 77FF
29
—
0x4800 7000
0x4800 73FF
28
—
0x4800 6C00
0x4800 6FFF
27
—
0x4800 6800
0x4800 6BFF
26
—
0x4800 6400
0x4800 67FF
25
—
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System and memory overview
RM0483
Table 13. AHB2 peripherals mapping table (continued)
3.3
Start address
End address
Index
Peripheral
0x4800 6000
0x4800 63FF
24
—
0x4800 5C00
0x4800 5FFF
23
—
0x4800 5800
0x4800 5BFF
22
—
0x4800 5400
0x4800 57FF
21
—
0x4800 5000
0x4800 53FF
20
—
0x4800 4C00
0x4800 4FFF
19
—
0x4800 4800
0x4800 4BFF
18
—
0x4800 4400
0x4800 47FF
17
DMAMUX1
0x4800 4000
0x4800 43FF
16
DMA1
0x4800 3C00
0x4800 3FFF
15
—
0x4800 3800
0x4800 3BFF
14
—
0x4800 3400
0x4800 37FF
13
—
0x4800 3000
0x4800 33FF
12
—
0x4800 2C00
0x4800 2FFF
11
—
0x4800 2800
0x4800 2BFF
10
—
0x4800 2400
0x4800 27FF
9
—
0x4800 2000
0x4800 23FF
8
GPIOI
0x4800 1C00
0x4800 1FFF
7
GPIOH
0x4800 1800
0x4800 1BFF
6
GPIOG
0x4800 1400
0x4800 17FF
5
GPIOF
0x4800 1000
0x4800 13FF
4
GPIOE
0x4800 0C00
0x4800 0FFF
3
GPIOD
0x4800 0800
0x4800 0BFF
2
GPIOC
0x4800 0400
0x4800 07FF
1
GPIOB
0x4800 0000
0x4800 03FF
0
GPIOA
Embedded SRAM
The SR5E1x device features:
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•
256 Kbytes of system SRAM
•
128 Kbytes of data TCM RAM
•
64 Kbytes of instruction TCM RAM
RM0483 Rev 5
RM0483
System and memory overview
The embedded system RAM is divided in two blocks:
•
AXI SRAM1, 128 Kbytes is mapped at the address 0x2400_0000 and accessible by all
system masters.
•
AXI SRAM2, 128 Kbytes is mapped at the address 0x2402_0000 and accessible by all
system masters.
The system AXI SRAM can be accessed as bytes, half-words, words or doublewords (64-bit
units). These memories can be addressed at maximum system clock frequency without wait
state.
The TCM SRAMs are dedicated to the Cortex®-M7 cores:
•
DTCM1 on Core1 TCM interface is mapped at the address 0x5C00_0000 and
accessible by Cortex®-M7 Core1, and by DMAs or Core2 through the AHBS slave bus
of the Cortex®-M7 Core1.
•
DTCM2 on Core2 TCM interface is mapped at the address 0x5C04_0000 and
accessible by Cortex®-M7 Core2, and by DMAs or Core1 through the AHBS slave bus
of the Cortex®-M7 Core2.
The DTCMs can be used as a read-write segment to host critical real-time data (such as
stack and heap) for an application running on a Cortex®-M7 core.
•
ITCM1 on Core1 TCM interface is mapped at the address 0x5A00_0000 and
accessible by Cortex®-M7 Core1 and by the DMAs or the Core2 through the AHBS
slave bus of the Cortex®-M7 Core1.
•
ITCM2 on Core2 TCM interface is mapped at the address 0x5A04_0000 and
accessible by Cortex®-M7 Core2 and by the DMAs or the Core1 through the AHBS
slave bus of the Cortex®-M7 Core2.
The ITCMs can be used to host code for time-critical routines (such as interrupt handlers)
that requires deterministic execution.
Note:
When Core1 and Core2 are in lock-step mode, ITCM2 and DTCM2 are connected to Core1
TCM interfaces and remapped in order to offer a continuous range of 128 Kbytes of DTCM
and 64 Kbytes of ITCM to Core1.
3.4
Flash memory overview
Throughout the document, both flash and nonvolatile memory (NVM) are used indistinctly
because SR5E1x uses flash memory as a type of NVM. Note that for flash memory
controller PFLASHC and NVMC are used indistinctly in the document as well. The flash
memory controllers (NVMPC1, NVMPC2) manage CPU AXI accesses to the flash memory.
They implement the erase and program flash memory operations and the read and write
protection mechanisms.
The flash memory is organized as follows:
•
Two main memory blocks divided into sectors.
•
An information block:
–
System memory from which the device boots in system memory boot mode.
–
Option bytes to configure read and write protection.
Refer to Chapter 17: Embedded flash memory for more details.
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Signal description
4
Signal description
4.1
Production packages
RM0483
SR5E1x production packages (case number and outline drawings) are provided in the
SR5E1x Microcontroller datasheet.
4.2
Package pinouts and ballouts
®
The SR5E1x pin package pinouts and ballouts are contained in the Microsoft Excel
workbook file attached to the SR5E1x IO_Definition document.
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Device configuration
5
Device configuration
5.1
Core modules
The SR5E1x has three cores in two distinct modules:
•
a Cortex®-M0+ in the hardware security module (HSM), refer to SR5E1x security
reference manual.
•
two Cortex®-M7 in the main platform.
The two Cortex®-M7, aka Core1 and Core2, can be configured:
•
in decoupled mode, offering two processing units.
•
in lock-step mode, offering one processing unit.
The two Cortex®-M7 have the following features:
•
Single and double precision FPU.
•
16 regions of Core Memory Protection Unit (CMPU).
5.2
System modules
5.2.1
Interconnect / bus matrix
The SR5E1x device contains one bus matrix, based on NIC400. This bus matrix, or
interconnect, ensures and arbitrates concurrent accesses from multiple masters to multiple
slaves. This allows efficient and simultaneous operation from cores and DMAs to memories
and peripherals.
The arbitration uses a round-robin algorithm with Quality of Service (QoS) capability (least
recently- used (LRU) priority).
The interconnect has 9 functional Initiator ports (INIx) and one debug master port. These
ports are also referred to as ASIB (AMBA Slave Interface Block).
The interconnect has 13 functional Target ports (TARGx) and one debug slave port. These
ports are also referred to as AMIB (AMBA Master Interface Block).
5.2.1.1
Quality of Service
Traffic priority management (QoS - Quality of Service) is configured at start-up via device
configuration format (DCF) records, allowing the user to assign the right level of priority to
each initiator both in read and write.
The AXI switch matrix uses a priority-based arbitration when two initiators simultaneously
attempt to access the same target. Each initiator has programmable read channel and write
channel priorities, known as QoS, from 0 to 15, such that the higher the value, the higher the
priority.
The read channel QoS value is programmed in the AXI interconnect by INIx Read QoS
DCFs (AXI_INIx_READ_QOS_DCFy), and the write channel in the AXI interconnect by INIx
Write QoS DCFs (AXI_INIx_WRITE_QOS_DCFy).
Refer to Chapter 7: Device configuration format (DCF) records for detailed information on
the DCFs.
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Device configuration
RM0483
The following table shows the default QoS configuration after reset, when no DCFs are
programmed.
Table 14. Default QoS R/W value
Initiator port (INIx)
QoS value
Core1 - AXIM
0000
Core1 - AHBP
0000
Core2 - AXIM
0000
Core2 - AHBP
0000
DMA1 - AHBMEM
0001
DMA1 - AHBPER
0001
DMA2 - AHBMEM
0001
DMA2 - AHBPER
0001
HSM
0010
If two coincident transactions arrive at the same target, the higher priority transaction
passes before the lower priority. If the two transactions have the same QoS value, then a
least recently- used (LRU) priority scheme is adopted.
The QoS values are programmed according to the latency requirements for the application.
Setting a higher priority for an Initiator ensures a lower latency for transactions initiated by
the associated bus master.
INIx Read/Write QoS DCFs description
INIx Read QoS DCF0 description
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CORE2_AXIM_AR_QoS
CORE2_AHBP_AR_QoS
Reserved
HSM_AR_QoS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
CORE1_AXIM_AR_QoS
AXI_INIx_READ_QOS_DCF0
CORE1_AHBP_AR_QoS
5.2.1.2
0
RM0483
Reset:
Device configuration
0x0000_1111
31:28 HSM_AR_QoS
Read channel QoS setting for HSM
0x0: Lowest priority
0xF: Highest priority
27:16 Reserved
15:12 CORE2_AHBP_AR_QoS
Read channel QoS setting for Core2 AHBP
0x0: Lowest priority
0xF: Highest priority
11:8 CORE2_AXIM_AR_QoS
Read channel QoS setting for Core2 AXIM
0x0: Lowest priority
0xF: Highest priority
7:4 CORE1_AHBP_AR_QoS
Read channel QoS setting for Core1 AHBP
0x0: Lowest priority
0xF: Highest priority
3:0 CORE1_AXIM_AR_QoS
Read channel QoS setting for Core1 AXIM
0x0: Lowest priority
0xF: Highest priority
INIx Read QoS DCF1 description
RM0483 Rev 5
9
8
7
6
5
4
3
2
1
0
DMA1_AHBMEM_AR_QoS
DMA2_AHBMEM_AR_QoS
DMA2_AHBPER_AR_QoS
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DMA1_AHBPER_AR_QoS
AXI_INIx_READ_QOS_DCF1
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Device configuration
Reset:
RM0483
0x0000_1111
31:16 Reserved
15:12 DMA2_AHBPER_AR_QoS
Read channel QoS setting for DMA2 AHBPER
0x0: Lowest priority
0xF: Highest priority
11:8 DMA2_AHBMEM_AR_QoS
Read channel QoS setting for DMA2 AHBMEM
0x0: Lowest priority
0xF: Highest priority
7:4 DMA1_AHBPER_AR_QoS
Read channel QoS setting for DMA1 AHBPER
0x0: Lowest priority
0xF: Highest priority
3:0 DMA1_AHBMEM_AR_QoS
Read channel QoS setting for DAM1 AHBMEM
0x0: Lowest priority
0xF: Highest priority
INIx Write QoS DCF0 description
31:28 HSM_AW_QoS
Write channel QoS setting for HSM
0x0: Lowest priority
0xF: Highest priority
27:16 Reserved
15:12 CORE2_AHBP_AW_QoS
Write channel QoS setting for Core2 AHBP
0x0: Lowest priority
0xF: Highest priority
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9
8
7
6
5
4
3
2
1
CORE1_AXIIM_AW_QoS
0x2000_0000
CORE2_AXIIM_AW_QoS
Reserved
Reset:
CORE2_AHBP_Aw_QoS
HSM_AW_QoS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CORE1_AHBP_AW_QoS
AXI_INIx_WRITE_QOS_DCF0
0
RM0483
Device configuration
11:8 CORE2_AXIM_AW_QoS
Write channel QoS setting for Core2 AXIM
0x0: Lowest priority
0xF: Highest priority
7:4 CORE1_AHBP_AW_QoS
Write channel QoS setting for Core1 AHBP
0x0: Lowest priority
0xF: Highest priority
3:0 CORE1_AXIM_AW_QoS
Write channel QoS setting for Core1 AXIM
0x0: Lowest priority
0xF: Highest priority
INIx Write QoS DCFs1description
Reset:
9
8
7
6
5
4
3
2
1
0
DMA1_AHBMEM_AW_QoS
DMA2_AHBMEM_AW_QoS
DMA2_AHBPER_AW_QoS
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DMA1_AHBPER_AW_QoS
AXI_INIx_WRITE_QOS_DCF1
0x0000_1111
31:16 Reserved
15:12 DMA2_AHBPER_AW_QoS
Write channel QoS setting for DMA2 AHBPER
0x0: Lowest priority
0xF: Highest priority
11:8 DMA2_AHBMEM_AW_QoS
Write channel QoS setting for DMA2 AHBMEM
0x0: Lowest priority
0xF: Highest priority
7:4 DMA1_AHBPER_AW_QoS
Write channel QoS setting for DMA1 AHBPER
0x0: Lowest priority
0xF: Highest priority
3:0 DMA1_AHBMEM_AW_QoS
Write channel QoS setting for DAM1 AHBMEM
0x0: Lowest priority
0xF: Highest priority
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Device configuration
RM0483
AXI_WDG_DCF
AXI Transactions Watchdog DCF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
WDG_CNT
Reset:
0x00FF_FFFF
31:24 Reserved
23:0 WDG_CNT
Watchdog Counter Value
5.2.1.3
NIC and E2EECC protection
The connections between NIC masters and slaves (clients) are denoted as data paths. Data
corruption on all data paths between the Safety Masters and any client is detected with at
least 99% coverage via two main safety mechanisms: data from the replicated cores is
encoded using Error Correcting Code (ECC), which is implemented with a single-error
correction, double-error detection (SECDED) code with a Hamming distance of 4 and
includes coverage of addressing information; ECC is also applied to control signals and
address decoding, to verify that the data reaches all of the intended clients, from all possible
connections to these clients and the intended operation is performed on the target address.
The transactions are monitored by an AXI sniffer and watchdog, to avoid system stalls.
The following figure shows a general view of ECC schema and NIC protection.
Figure 6. NIC Protection and E2EECC schematic
Ű AXI4
Ű AHBLite
Ű APB2
HSM
Core #1
DMA #1
AXIM
AHBP
data e2e
check /
encoding
data e2e
check /
encoding
data e2e
check /
encoding
address +
control
e2e
encoding
address +
control
e2e
encoding
AHBP
AXIM
lockstep logic boundary
Core #2
DMA #2
AHBM
AHBP
data e2e
check /
encoding
data e2e
check /
encoding
data e2e
check /
encoding
data e2e
check /
encoding
address +
control
e2e
encoding
address +
control
e2e
encoding
address +
control
e2e
encoding
address +
control
e2e
encoding
AHBP
AHBM
upsizer
DAP600
APB-AP
data e2e
check /
encoding
data e2e
check /
encoding
SWJ-DP
ROM
Table
address +
control
e2e
encoding
address +
control
e2e
encoding
AXI-AP
axi sniffer /
watchdog
axi sniffer /
watchdog
address +
control
e2e
encoding
axi sniffer /
watchdog
axi sniffer /
watchdog
axi sniffer /
watchdog
axi sniffer /
watchdog
axi sniffer /
watchdog
axi sniffer /
watchdog
axi sniffer /
watchdog
64b AXI NIC
AXI_SMPU firewall
data e2e
encoding
data e2e
encoding
NVM
data e2e
check /
encoding
AXI2APB
converter
AXI2AHB
converter
data e2e
check /
encoding
data e2e
check /
encoding
APB-IC
data e2e
check /
encoding
address +
control
e2e
encoding
AHBS bus
bridge
AXI2APB
converter
AXI2APB
converter
data e2e
check /
encoding
address +
control
e2e
encoding
APB2
data e2e
check /
encoding
HRTIM1/2
data e2e
check /
encoding
APB1
address +
control
e2e
encoding
data e2e
check /
encoding
AHB1
data e2e
check /
encoding
address +
control
e2e
encoding
data e2e
check /
encoding
AXI2AHB
converter
NVMC2
AHB2
NVMC1
address +
control
e2e
encoding
address +
control
e2e
encoding
address +
control
e2e
encoding
AXI2AHB
converter
address +
address +
control
control
e2e
e2e
encoding
encoding
RAMC2
address + address +
control control
e2e
e2e
encoding encoding
control
e2e
encoding
RAMC1
address +
control
e2e
encodingaddress +
HW redundancy
ECC bits are generated on writes by NIC masters (including, but not limited to the Safety
Core) and checked on reads. The ECC correction bits are stored alongside the data in NVM
and RAM so, in principle, no ECC logic is necessary at the memories themselves. For this
reason, the ECC schema is referred to as End-to-End ECC (E2E ECC) in the following
sections. For NIC master and slaves, apart from memories, new ECC logic is added as
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RM0483
Device configuration
these clients cannot store or produce the ECC correction bits. This resolves the problem
where ECC needs to be calculated in real time before entering or exiting the ECC-protected
data path. This setup leaves the data path downstream of the ECC units (for example,
starting at, and downstream of, the peripheral bridges) unprotected by ECC. To detect
corruptions introduced in those unprotected data paths, the BRIDGEs and peripherals can
be used redundantly, or other mechanisms may be used to validate peripheral operation.
The E2E ECC schema provides high detection capabilities against failures affecting the
data content of the transaction. The inclusion of the target address in the computation of the
redundancy bits (8 ECC bits) does allow the partial detection of addressing faults as well. To
reach the desired integrity level, additional dedicated safety mechanisms are implemented
in the data path to:
•
Improve the detection capability over addressing failures (no/multiple/wrong address
selected), considering faults affecting address transmission (from master to client) as
well as the decoding of the address.
•
Provide coverage for control failures affecting, for example, the type (read vs. write) or
size of a transaction.
Though the safety mechanisms protecting the NIC, the RAM controller, or the Flash memory
controller are different, they are all based on the feedback of address and control
information from the target to the source of the transaction, which is responsible for
checking for consistency with respect to the intended transaction. Depending on the portion
of the data path covered by the specific safety mechanism, the source can be an NIC
master port rather than the NIC interface of the RAM or Flash controllers; the target is
respectively an NIC slave port, the RAM array, or the Flash module (refer to “NIC”, “Non
Volatile Memory Platform Controller (NVMPC)”, and “Platform RAM controller AXI
(PRAMC_AXI)” chapters).
5.2.2
Hardware semaphore (HSEM2) configuration
The peripheral platform includes a memory-mapped semaphore module (HSEM2) that
provides:
•
Robust hardware support needed in multi-core systems for implementing semaphores
•
A simple mechanism to achieve “lock/unlock” operations via a single write access
The hardware semaphore block provides 32 (32-bit) registers based semaphores.
The semaphores can be used to ensure synchronization between different processes
running between different cores.
5.2.3
System Memory Protection Unit (SMPU) configuration
The SR5E1x contains one instance of the System Memory Protection Unit (SMPU) with 24
regions.
This section summarizes how the module instance has been configured in the chip. For a
comprehensive description of the module itself, see the chapter for that module.
Table 15. Master ID assignments
SMPU logical bus master number
Bus master
0’b1000
Core1 (Cortex®-M7)
0’b0001
Core2 (Cortex®-M7)
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Device configuration
RM0483
Table 15. Master ID assignments (continued)
5.2.4
SMPU logical bus master number
Bus master
0’b0010
HSM
0’b1011
DMA1
0’b0100
DMA2
0’b1101
Debug Access Port (DAP)
Nested Vectored Interrupt Controller configuration
Both CPU1 (Cortex®-M7) and CPU2 (Cortex®-M7) cores have their own nested vector
interrupt controller (respectively NVIC1 and NVIC2).
Each CPU has its own exceptions connected to its Nested vectored interrupt controller
(NVIC): reset, NMI, HardFault, MemManage, Bus Fault, UsageFault, SVCall,
DebugMonitor, PendSV, SysTick.
Each CPU is able to generate an interrupt or trigger a wake-up to the other core through the
EXTI. Cortex®-M7 core features an output signal as a result of the Send Event (SEV)
instruction. The Core1_SEV is connected to Core2 NVIC (NVIC2) position 151, while
Core2_SEV is connected to Core1 NVIC (NVIC1) position 150.
Each CPU also has its own Floating Point Unit (FPU) interrupt connected to its Nested
Vectored Interrupt Controller (NVIC), in position 81.
The Window Watchdog 1 (WWDG1) interrupt is connected to the CPU1 NVIC (NVIC1)
position 0, while Window Watchdog 2 (WWDG2) interrupt is connected to the CPU2 NVIC
(NVIC2) position 0.
5.2.4.1
Interrupt and exception vectors
The gray rows in the following table describe the vectors without specific position.
Type of
priority
NVIC1 Position
NVIC2 Position
Table 16. SR5E1x vector table
Acronym
—
—
—
—
Fixed
—
—
Fixed
—
Fixed
Description
Address
Reserved
0x0000 0000
Reset
Reset
0x0000 0004
—
NMI
FCCU Non maskable interrupt
0x0000 0008
—
—
HardFault
All class of fault
0x0000 000C
Settable
—
—
MemManage
Memory management
0x0000 0010
Settable
—
—
BusFault
Pre-fetch fault; memory access fault
0x0000 0014
Settable
—
—
UsageFault
Undefined instruction or illegal state
0x0000 0018
86/2075
RM0483 Rev 5
RM0483
Device configuration
Type of
priority
NVIC1 Position
NVIC2 Position
Table 16. SR5E1x vector table (continued)
Acronym
—
—
—
—
Settable
—
—
SVCall
Settable
—
—
Debug Monitor
—
—
—
—
Settable
—
—
Settable
—
Settable
Description
Address
Reserved
0x0000 001C0x0000 002B
System Service call via SWI instruction
0x0000 002C
Debug Monitor
0x0000 0030
Reserved
0x0000 0034
PendSV
Pendable request for system service
0x0000 0038
—
Systick
System tick timer
0x0000 003C
0
—
WWDG1
Window Watchdog Early interrupt
0x0000 0040
—
—
0
WWDG2
Window Watchdog Early interrupt
0x0000 0040
Settable
1
1
RTC_ALARM
RTC Alarm interrupts through EXTI line 18
0x0000 0044
Settable
2
2
—
Reserved
0x0000 0048
Settable
3
3
RTC_WKPU
RTC_Wakeup through EXTI line 20 interrupt
0x0000 004C
Settable
4
4
FLASH
Flash global interrupt
0x0000 0050
Settable
5
5
RCC
RCC global interrupt
0x0000 0054
Settable
6
6
EXTI0
EXTI Line0 interrupt
0x0000 0058
Settable
7
7
EXTI1
EXTI Line1 interrupt
0x0000 005C
Settable
8
8
EXTI2
EXTI Line2 interrupt
0x0000 0060
Settable
9
9
EXTI3
EXTI Line3 interrupt
0x0000 0064
Settable
10
10
EXTI4
EXTI Line4 interrupt
0x0000 0068
Settable
11
11
DMA1_Stream0
DMA1 Stream0 global interrupt
0x0000 006C
Settable
12
12
DMA1_Stream1
DMA1 Stream1 global interrupt
0x0000 0070
Settable
13
13
DMA1_Stream2
DMA1 Stream2 global interrupt
0x0000 0074
Settable
14
14
DMA1_Stream3
DMA1 Stream3 global interrupt
0x0000 0078
Settable
15
15
DMA1_Stream4
DMA1 Stream4 global interrupt
0x0000 007C
Settable
16
16
DMA1_Stream5
DMA1 Stream5 global interrupt
0x0000 0080
Settable
17
17
DMA1_Stream6
DMA1 Stream6 global interrupt
0x0000 0084
Settable
18
18
DMA1_Stream7
DMA1 Stream7 global interrupt
0x0000 0088
Settable
19
19
TIM15
TIM15 global interrupt
0x0000 008C
Settable
20
20
TIM16
TIM16 global interrupt
0x0000 0090
Settable
21
21
—
Reserved
0x0000 0094
Settable
22
22
—
Reserved
0x0000 0098
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Device configuration
RM0483
Type of
priority
NVIC1 Position
NVIC2 Position
Table 16. SR5E1x vector table (continued)
Acronym
Settable
23
23
—
Settable
24
24
Settable
25
25
Settable
26
26
Settable
27
27
TIM1_CC
Settable
28
28
Settable
29
Settable
Description
Reserved
TIM1_BRK/TIM1_TER TIM1 Break interrupt/TIM1 Transition/TIM1 Index
R/TIM1_IERR
Error
TIM1_UP
Address
0x0000 009C
0x0000 00A0
TIM1 Update interrupt
0x0000 00A4
TIM1_TRG_COM/TIM TIM1 Trigger and Commutation interrupts/TIM1
1_DIR/TIM1_IDX
Direction Change/TIM1_Index
0x0000 00A8
TIM1 Capture Compare interrupt (OR of all
channels)
0x0000 00AC
TIM2
TIM2 global interrupt
0x0000 00B0
29
TIM3
TIM3 global interrupt
0x0000 00B4
30
30
TIM4
TIM4 global interrupt
0x0000 00B8
Settable
31
31
I2C1_EV
I2C1 event interrupt OR EXTI line 23 interrupt
0x0000 00BC
Settable
32
32
I2C1_ER
I2C1 error interrupt
0x0000 00C0
Settable
33
33
I2C2_EV
I2C2 event interrupt OR EXTI line 24 interrupt
0x0000 00C4
Settable
34
34
I2C2_ER
I2C2 error interrupt
0x0000 00C8
Settable
35
35
SPI1
SPI1 global interrupt
0x0000 00CC
Settable
36
36
SPI2
SPI2 global interrupt
0x0000 00D0
Settable
37
37
UART1
UART1 global interrupt OR EXTI line 25 interrupt
0x0000 00D4
Settable
38
38
UART2
UART2 global interrupt OR EXTI line 26 interrupt
0x0000 00D8
Settable
39
39
UART3
UART3 global interrupt OR EXTI line 28 interrupt
0x0000 00DC
Settable
40
40
EXTI9_5
EXTI Line[9:5] interrupts
0x0000 00E0
Settable
41
41
EXTI15_10
EXTI Line[15:10] interrupts
0x0000 00E4
Settable
42
42
—
Reserved
0x0000 00E8
Settable
43
43
Settable
44
44
Settable
45
45
Settable
46
46
TIM8_CC
Settable
47
47
Settable
48
Settable
49
88/2075
TIM8_BRK/TIM8_TER TIM8 Break interrupt/Tim8 Transition/TIM8 Index
R/TIM8_IERR
Error
TIM8_UP
0x0000 00EC
TIM8 Update interrupt
0x0000 00F0
TIM8_TRG_COM/TIM TIM8 Trigger and Commutation interrupt/TIM8
8_DIR/TIM8_IDX
Direction Change Interrupt/TIM8 Index
0x0000 00F4
TIM8 Capture Compare interrupt (OR of all
channels)
0x0000 00F8
TIM5
TIM5 global interrupt
0x0000 00FC
48
TIM6
TIM6 global interrupt
0x0000 0100
49
TIM7
TIM7 global interrupt
0x0000 0104
RM0483 Rev 5
RM0483
Device configuration
Type of
priority
NVIC1 Position
NVIC2 Position
Table 16. SR5E1x vector table (continued)
Acronym
Settable
50
50
TIM_TS
TIMTS_global interrupt
0x0000 0108
Settable
51
51
SPI3
SPI3 global interrupt
0x0000 010C
Settable
52
52
SPI4
SPI4 global interrupt
0x0000 0110
Settable
53
53
—
Reserved
0x0000 0114
Settable
54
54
—
Reserved
0x0000 0118
Settable
55
55
—
Reserved
0x0000 011C
Settable
56
56
DMA2_Stream0
DMA2 Stream0 global interrupt
0x0000 0120
Settable
57
57
DMA2_Stream1
DMA2 Stream1 global interrupt
0x0000 0124
Settable
58
58
DMA2_Stream2
DMA2 Stream2 global interrupt
0x0000 0128
Settable
59
59
DMA2_Stream3
DMA2 Stream3 global interrupt
0x0000 012C
Settable
60
60
DMA2_Stream4
DMA2 Stream4 global interrupt
0x0000 0130
Settable
61
61
DMA2_Stream5
DMA2 Stream5 global interrupt
0x0000 0134
Settable
62
62
DMA2_Stream6
DMA2 Stream6 global interrupt
0x0000 0138
Settable
63
63
DMA2_Stream7
DMA2 Stream7 global interrupt
0x0000 013C
Settable
64
64
DMAMUX_OVR
DMAMUX Overrun interrupt
0x0000 0140
Settable
65
65
—
Reserved
0x0000 0144
Settable
66
66
—
Reserved
0x0000 0148
Settable
67
67
HRTIM1_Master_Int
HRTIM1 Master Timer Interrupt (hrtim_it1)
0x0000 014C
Settable
68
68
HRTIM1_TIMA_Int
HRTIM1 Timer A Interrupt (hrtim_it2)
0x0000 0150
Settable
69
69
HRTIM1_TIMB_Int
HRTIM1 Timer B Interrupt (hrtim_it3)
0x0000 0154
Settable
70
70
HRTIM1_TIMC_Int
HRTIM1 Timer C Interrupt (hrtim_it4)
0x0000 0158
Settable
71
71
HRTIM1_TIMD_Int
HRTIM1 Timer D Interrupt (hrtim_it5)
0x0000 015C
Settable
72
72
HRTIM1_TIME_Int
HRTIM1 Timer E Interrupt (hrtim_it6)
0x0000 0160
Settable
73
73
Settable
74
74
HRTIM1_TIMF_Int
Settable
75
75
Settable
76
Settable
Description
HRTIM1_TIM_FLT_Int HRTIM1 Fault Interrupt (hrtim_it8)
Address
0x0000 0164
HRTIM1 Timer F Interrupt (hrtim_it7)
0x0000 0168
—
Reserved
0x0000 016C
76
—
Reserved
0x0000 0170
77
77
—
Reserved
0x0000 0174
Settable
78
78
—
Reserved
0x0000 0178
Settable
79
79
—
Reserved
0x0000 017C
Settable
80
80
—
Reserved
0x0000 0180
RM0483 Rev 5
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Device configuration
RM0483
Settable
81
NVIC2 Position
Type of
priority
NVIC1 Position
Table 16. SR5E1x vector table (continued)
—
Acronym
Description
Address
FPU1
CPU1 FPU
(FPIDC1 and FPU1_IT_EN(4)) or
(FPOFC1 and FPU1_IT_EN(3)) or
(FPUFC1 and FPU1_IT_EN(2)) or
(FPDZC1 and FPU1_IT_EN(1)) or
(FPIOC1 and FPU1_IT_EN(0));
0x0000 0184
CPU2 FPU
((FPIDC2 and FPU2_IT_EN(4)) or
(FPOFC2 and FPU2_IT_EN(3)) or
(FPUFC2 and FPU2_IT_EN(2)) or
(FPDZC2 and FPU2_IT_EN(1)) or
(FPIOC2 and FPU2_IT_EN(0));
0x0000 0184
Settable
—
81
FPU2
Settable
82
82
—
Reserved
0x0000 0188
Settable
83
83
—
Reserved
0x0000 018C
m_can_1_int0
Line 0 combined interrupt
CAN_SUBSYSTEM_1:
(M_CAN_1_IR[0] & ~M_CAN_1_ILS[0])| ... |
(M_CAN_1_IR[11] & ~M_CAN_1_ILS[11]) |
(M_CAN_1_IR[13] & ~M_CAN_1_ILS[13]) |
… | (M_CAN_1_IR[31] &
~M_CAN_1_ILS[31])
0x0000 0190
Line 1 combined interrupt
CAN_SUBSYSTEM_1:
(M_CAN_1_IR[0] & M_CAN_1_ILS[0])| ... |
(M_CAN_1_IR[11] & M_CAN_1_ILS[11]) |
(M_CAN_1_IR[13] & M_CAN_1_ILS[13]) |
… | (M_CAN_1_IR[31] &
M_CAN_1_ILS[31])
0x0000 0194
MCAN1 DMU Interrupt
0x0000 0198
Settable
84
84
Settable
85
85
m_can_1_int1
Settable
86
86
mcan_1_ dmu_int
90/2075
RM0483 Rev 5
RM0483
Device configuration
Settable
87
NVIC2 Position
Type of
priority
NVIC1 Position
Table 16. SR5E1x vector table (continued)
87
Acronym
m_can_2_int0
0x0000 019C
Line 1 combined interrupt
CAN_SUBSYSTEM_1:
(M_CAN_2_IR[0] & M_CAN_2_ILS[0])| ... |
(M_CAN_2_IR[11] & M_CAN_2_ILS[11]) |
(M_CAN_2_IR[13] & M_CAN_2_ILS[13]) |
… | (M_CAN_2_IR[31] &
M_CAN_2_ILS[31])
0x0000 01A0
MCAN2 DMU Interrupt
0x0000 01A4
m_can_3_int0
Line 0 combined interrupt
CAN_SUBSYSTEM_1:
(M_CAN_3_IR[0] & ~M_CAN_3_ILS[0])| ... |
(M_CAN_3_IR[11] & ~M_CAN_3_ILS[11]) |
(M_CAN_3_IR[13] & ~M_CAN_3_ILS[13]) |
… | (M_CAN_3_IR[31] &
~M_CAN_3_ILS[31])
0x0000 01A8
Line 1 combined interrupt
CAN_SUBSYSTEM_1:
(M_CAN_3_IR[0] & M_CAN_3_ILS[0])| ... |
(M_CAN_3_IR[11] & M_CAN_3_ILS[11]) |
(M_CAN_3_IR[13] & M_CAN_3_ILS[13]) |
… | (M_CAN_3_IR[31] &
M_CAN_3_ILS[31])
0x0000 01AC
MCAN3 DMU Interrupt
0x0000 01B0
88
88
m_can_2_int1
Settable
89
89
mcan_2_ dmu_int
90
90
Address
Line 0 combined interrupt
CAN_SUBSYSTEM_1:
(M_CAN_2_IR[0] & ~M_CAN_2_ILS[0])| ... |
(M_CAN_2_IR[11] & ~M_CAN_2_ILS[11]) |
(M_CAN_2_IR[13] & ~M_CAN_2_ILS[13]) |
… | (M_CAN_2_IR[31] &
~M_CAN_2_ILS[31])
Settable
Settable
Description
Settable
91
91
m_can_3_int1
Settable
92
92
mcan_3_ dmu_int
RM0483 Rev 5
91/2075
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Device configuration
RM0483
Settable
93
NVIC2 Position
Type of
priority
NVIC1 Position
Table 16. SR5E1x vector table (continued)
93
Acronym
Description
Address
m_can_4_int0
Line 0 combined interrupt
CAN_SUBSYSTEM_1:
(M_CAN_4_IR[0] & ~M_CAN_4_ILS[0])| ... |
(M_CAN_4_IR[11] & ~M_CAN_4_ILS[11]) |
(M_CAN_4_IR[13] & ~M_CAN_4_ILS[13]) |
… | (M_CAN_4_IR[31] &
~M_CAN_4_ILS[31])
0x0000 01B4
Line 1 combined interrupt
CAN_SUBSYSTEM_1:
(M_CAN_4_IR[0] & M_CAN_4_ILS[0])| ... |
(M_CAN_4_IR[11] & M_CAN_4_ILS[11]) |
(M_CAN_4_IR[13] & M_CAN_4_ILS[13]) |
… | (M_CAN_4_IR[31] &
M_CAN_4_ILS[31])
0x0000 01B8
MCAN3 DMU Interrupt
0x0000 01BC
Cordic Interrupt
0x0000 01C0
Reserved
0x0000 01C4
Settable
94
94
m_can_4_int1
Settable
95
95
mcan_4_ dmu_int
Settable
96
96
Cordic
Settable
97
97
—
Settable
98
98
HSEM_int1
Hardware semaphore interrupt to CORE1
0x0000 01C8
Settable
99
99
HSEM_int2
Hardware semaphore interrupt to CORE2
0x0000 01CC
Settable 100 100
—
Reserved
0x0000 01D0
Settable 101 101
—
Reserved
0x0000 01D4
Settable 102 102
—
Reserved
0x0000 01D8
Settable 103 103
—
Reserved
0x0000 01DC
Settable 104 104
HRTIM2_Master_Int
HRTIM2 Master Timer Interrupt (hrtim_it1)
0x0000 01E0
Settable 105 105
HRTIM2_TIMA_Int
HRTIM2 Timer A Interrupt (hrtim_it2)
0x0000 01E4
Settable 106 106
HRTIM2_TIMB_Int
HRTIM2 Timer B Interrupt (hrtim_it3)
0x0000 01E8
Settable 107 107
HRTIM2_TIMC_Int
HRTIM2 Timer C Interrupt (hrtim_it4)
0x0000 01EC
Settable 108 108
HRTIM2_TIMD_Int
HRTIM2 Timer D Interrupt (hrtim_it5)
0x0000 01F0
Settable 109 109
HRTIM2_TIME_Int
HRTIM2 Timer E Interrupt (hrtim_it6)
0x0000 01F4
Settable 110 110 HRTIM2_TIM_FLT_Int HRTIM2 Fault Interrupt (hrtim_it8)
0x0000 01F8
Settable 111 111
HRTIM2_TIMF_Int
HRTIM2 Timer F Interrupt (hrtim_it7)
0x0000 01FC
Settable 112 112
—
Reserved
0x0000 0200
92/2075
RM0483 Rev 5
RM0483
Device configuration
NVIC2 Position
Type of
priority
NVIC1 Position
Table 16. SR5E1x vector table (continued)
Acronym
Description
Address
Settable 113 113
—
Reserved
0x0000 0204
Settable 114 114
—
Reserved
0x0000 0208
Settable 115 115
—
Reserved
0x0000 020C
Settable 116 116
—
Reserved
0x0000 0210
Settable 117 117
—
Reserved
0x0000 0214
Settable 118 118
—
Reserved
0x0000 0218
Settable 119 119
—
Reserved
0x0000 021C
Settable 120 120
B-DAC1
B-DAC1 underrun global interrupt
0x0000 0220
Settable 121 121
DAC1
DAC1 underrun global interrupt
0x0000 0224
Settable 122 122
DAC2
DAC2 underrun global interrupt
0x0000 0228
Settable 123 123
DAC3
DAC3 underrun global interrupt
0x0000 022C
Settable 124 124
DAC4
DAC4 underrun global interrupt
0x0000 0230
Settable 125 125
—
Reserved
0x0000 0234
Settable 126 126
—
Reserved
0x0000 0238
Settable 127 127
—
Reserved
0x0000 023C
Settable 128 128
—
Reserved
0x0000 0240
Settable 129 129
COMP_1_2
COMP1 OR COMP2 through EXTI lines 21/22
interrupts
0x0000 0244
Settable 130 130
COMP_3_4
COMP3 OR COMP4 through EXTI lines 29/30
interrupts
0x0000 0248
Settable 131 131
COMP_5_6
COMP5 OR COMP6 through EXTI lines 31/32
interrupts
0x0000 024C
Settable 132 132
COMP7_8
COMP7 OR COMP8 through EXTI lines 33/34
interrupts
0x0000 0250
Settable 133 133
—
Reserved
0x0000 0254
Settable 134 134
—
Reserved
0x0000 0258
Settable 135 135
—
Reserved
0x0000 025C
Settable 136 136
—
Reserved
0x0000 0260
RM0483 Rev 5
93/2075
162
Device configuration
RM0483
NVIC2 Position
Type of
priority
NVIC1 Position
Table 16. SR5E1x vector table (continued)
Acronym
Description
Address
Settable 137 137
ADC1
ADC1 global interrupt
0x0000 0264
Settable 138 138
ADC2
ADC2 global interrupt
0x0000 0268
Settable 139 139
ADC3
ADC3 global interrupt
0x0000 026C
Settable 140 140
ADC4
ADC4 global interrupt
0x0000 0270
Settable 141 141
ADC5
ADC5 global interrupt
0x0000 0274
Settable 142 142
—
Reserved
0x0000 0278
Settable 143 143
—
Reserved
0x0000 027C
Settable 144 144
—
Reserved
0x0000 0280
Settable 145 145
SD_ADC1
SD_ADC1 global interrupt
0x0000 0284
Settable 146 146
SD_ADC2
SD_ADC2 global interrupt
0x0000 0288
Settable 147 147
—
Reserved
0x0000 028C
Settable 148 148
—
Reserved
0x0000 0290
Settable 149 149
—
Reserved
0x0000 0294
Settable 150
—
Core2_SEV
Cortex M7 Core2 Send Event interrupt to Core1
through EXTI line 45
0x0000 0298
Settable
151
Core1_SEV
Cortex M7 Core1 Send Event interrupt to Core2
through EXTI line 44
0x0000 029C
—
Settable 152 152
—
Reserved
0x0000 02A0
Settable 153 153
—
Reserved
0x0000 02A4
Settable 154 154
FCCU_int
FCCU_IRQ_STAT[ALARM_STAT or
CFG_TO_STAT]
0x0000 02A8
Settable 155 155
—
Reserved
0x0000 02AC
Settable 156 156
—
Reserved
0x0000 02B0
Settable 157 157
—
Reserved
0x0000 02B4
Settable 158 158
—
Reserved
0x0000 02B8
Settable 159 159
—
Reserved
0x0000 02BC
Settable 160 160
PMC_dig
PMC_dig global interrupt
0x0000 02C0
Settable 161 161
—
Reserved
0x0000 02C4
Settable 162 162
—
Reserved
0x0000 02C8
Settable 163 163
—
Reserved
0x0000 02CC
94/2075
RM0483 Rev 5
RM0483
Device configuration
NVIC2 Position
Type of
priority
NVIC1 Position
Table 16. SR5E1x vector table (continued)
Acronym
Description
Address
Settable 164 164
HSM2HST0_15
Ored(HSM2HT_it[15]...[HSM2HT_it[0])
0x0000 02D0
Settable 165 165
HSM2HST16_31
Ored(HSM2HT_it[31]...[HSM2HT_it[16])
0x0000 02D4
Settable 166 166
—
Reserved
0x0000 02D8
Settable 167 167
NVMPC
Requested Read from CoreX in Data Flash
available (Data memory collision function)
0x0000 02DC
Settable 168 168
DBGMCU
DBGMCU_MSR[DIN_INT] :OR:
DBGMCU_MSR[DOUT_INT]
0x0000 02E0
Settable 169 169
—
Reserved
0x0000 02E4
Settable 170 170
—
Reserved
0x0000 02E8
Settable 171 171
—
Reserved
0x0000 02EC
Settable 172 172
—
Reserved
0x0000 02F0
Settable 173 173
—
Reserved
0x0000 02F4
Settable 174 174
—
Reserved
0x0000 02F8
Settable 175 175
—
Reserved
0x0000 02FC
Settable 176 176
—
Reserved
0x0000 0300
Settable 177 177
—
Reserved
0x0000 0304
Settable 178 178
—
Reserved
0x0000 0308
Settable 179 179
—
Reserved
0x0000 030C
Settable 180 180
—
Reserved
0x0000 0310
Settable 181 181
—
Reserved
0x0000 0314
Settable 182 182
—
Reserved
0x0000 0318
Settable 183 183
—
Reserved
0x0000 031C
Settable 184 184
—
Reserved
0x0000 0320
Settable 185 185
—
Reserved
0x0000 0324
Settable 186 186
—
Reserved
0x0000 0328
Settable 187 187
—
Reserved
0x0000 032C
Settable 188 188
—
Reserved
0x0000 0330
Settable 189 189
—
Reserved
0x0000 0334
Settable 190 190
—
Reserved
0x0000 0338
Settable 191 191
—
Reserved
0x0000 033C
Settable 192 192
—
Reserved
0x0000 0340
Settable 193 193
—
Reserved
0x0000 0344
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NVIC2 Position
Type of
priority
NVIC1 Position
Table 16. SR5E1x vector table (continued)
Acronym
Description
Address
Settable 194 194
—
Reserved
0x0000 0348
Settable 195 195
—
Reserved
0x0000 034C
Settable 196 196
—
Reserved
0x0000 0350
Settable 197 197
—
Reserved
0x0000 0354
Settable 198 198
—
Reserved
0x0000 0358
Settable 199 199
—
Reserved
0x0000 035C
Settable 200 200
—
Reserved
0x0000 0360
5.2.5
EXTI configuration
The SR5E1x's EXTI features 33 interrupt/event lines.
In the following figure, the GPIOs are connected to 16 configurable interrupt/event lines.
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Device configuration
Figure 7. External interrupt/event GPIO mapping
EXTI0[3:0] bits in the SYSCFG _EXTICR1 register
PA0
PB0
PC0
EXTI0
PD0
PE0
PF0
PG0
PH0
PI0
EXTI1[3:0] bits in the SYSCFG _EXTICR1 register
PA1
PB1
PC1
EXTI1
PD1
PE1
PF1
PG1
PH1
PI1
.
.
.
EXTI15[3:0] bits in the SYSCFG _EXTICR4 register
PA15
PB15
PC15
PD15
EXTI15
PE15
PF15
PG15
PH15
PI15
The EXTI lines are connected as shown in the following table.
Table 17. EXTI event input mapping
Event
input
Source
Event input type
Connection to
NVICx
0-15
GPIOs
Configurable
1,2
16-17
Reserved
—
—
18
RTC alarm event
Configurable
1,2
19
Reserved
—
—
20
RTC Wakeup Timer
Configurable
1,2
21
COMP1 Output
Configurable
1,2
22
COMP2 Output
Configurable
1,2
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Table 17. EXTI event input mapping (continued)
5.2.6
Event
input
Source
Event input type
Connection to
NVICx
23
I2C1 wakeup
Direct
1,2
24
I2C2 wakeup
Direct
1,2
25
UART1
Direct
1,2
26
UART2
Direct
1,2
27
Reserved
—
—
28
UART3
Direct
1,2
29
COMP3 Output
Configurable
1,2
30
COMP4 Output
Configurable
1,2
31
COMP5 Output
Configurable
1,2
32
COMP6 Output
Configurable
1,2
33
COMP7 Output
Configurable
1,2
34
COMP8 Output
Configurable
1,2
35-43
Reserved
—
—
44
CPU1 SEV
Direct
2
45
CPU2 SEV
Direct
1
46
Reserved
—
—
DMA controllers configuration
The SR5E1x includes 2 Direct Memory Access (DMA) instances (DMA1 and DMA2) and a
DMA request multiplexer (DMAMUX). The Figure 8 below shows the DMA architecture.
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Device configuration
Figure 8. DMA and DMAMUX architecture
DMA lockstep
IRQ request (one per channel)
AHB Register Access
DMAMUX lockstep
DMA_1
8 channels
DMAMUX_1
Master port 1 (data transfer)
Channel 0
Master port 2 (data transfer)
Channel 7
Sources
DMA lockstep
Triggers
Channel 8
IRQ request (one per channel)
Channel 15
AHB Register Access
DMA_2
8 channels
Master port 1 (data transfer)
Master port 2 (data transfer)
Each DMA instance has the following features:
•
8 input streams
•
double buffer mode for each stream
•
4-word FIFO per stream
Each DMA instance has a replica that can be enabled in lockstep in order to reach a high
level of safety. The enabling of the replica is done at start-up via the Global System
Configuration DCF record.
5.2.7
DMA request multiplexer (DMAMUX) configuration
The SR5E1x includes one DMA request multiplexer (DMAMUX_1) with 16 output channels:
•
DMAMUX_1 channels 0 to 7 are connected to DMA_1 channels 0 to 7
•
DMAMUX_1 channels 8 to 15 are connected to DMA_2 channels 0 to 7
The DMAMUX_1 has a replica that can be enabled in lockstep at start-up via the Global
System Configuration DCF record.
5.2.7.1
DMAMUX instantiation
DMAMUX is instantiated with the hardware configuration parameters listed in the following
table.
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Table 18. DMAMUX instantiation
Feature
DMAMUX
Number of DMAMUX output request channels
16
Number of DMAMUX request generator channels
4
Number of DMAMUX request trigger inputs
21
Number of DMAMUX synchronization inputs
21
Number of DMAMUX peripheral request inputs
151(1)
1. Inputs 1 to 151 used but 33 unused inputs inside.
5.2.7.2
DMAMUX mapping
The mapping of resources to DMAMUX is hardwired.
DMAMUX is used with DMA1 and DMA2:
•
DMAMUX channels 0 to 7 are connected to DMA1 input streams 0 to 7.
•
DMAMUX channels 8 to 15 are connected to DMA2 input streams 0 to 7.
Table 19. DMAMUX: assignment of multiplexer inputs to resources
DMA
request
MUX input
Resource
DMA
request
MUX input
Resource
DMA
request
MUX input
Resource
1
DMAMUX_Req G0
55
TIM8_COM
109
Reserved
2
DMAMUX_Req G1
56
TIM2_CH1
110
Reserved
3
DMAMUX_Req G2
57
TIM2_CH2
111
Reserved
4
DMAMUX_Req G3
58
TIM2_CH3
112
Cordic_read
5
ADC1
59
TIM2_CH4
113
Cordic_write
6
B-DAC1_CH1
60
TIM2_UP
114
Reserved
7
B-DAC1_CH2
61
TIM3_CH1
115
Reserved
8
TIM6_UP
62
TIM3_CH2
116
HRTIM2_MASTER (hrtim_dma1)
9
TIM7_UP
63
TIM3_CH3
117
HRTIM2_TIMA (hrtim_dma2)
10
SPI1_RX
64
TIM3_CH4
118
HRTIM2_TIMB (hrtim_dma3)
11
SPI1_TX
65
TIM3_UP
119
HRTIM2_TIMC (hrtim_dma4)
12
SPI2_RX
66
TIM3_TRIG
120
HRTIM2_TIMD (hrtim_dma5)
13
SPI2_TX
67
TIM4_CH1
121
HRTIM2_TIME (hrtim_dma6)
14
SPI3_RX
68
TIM4_CH2
122
HRTIM2_TIMF (hrtim_dma7)
15
SPI3_TX
69
TIM4_CH3
123
Reserved
16
I2C1_RX
70
TIM4_CH4
124
Reserved
17
I2C1_TX
71
TIM4_UP
125
Reserved
18
I2C2_RX
72
TIM5_CH1
126
Reserved
19
I2C2_TX
73
TIM5_CH2
127
Reserved
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Device configuration
Table 19. DMAMUX: assignment of multiplexer inputs to resources (continued)
DMA
request
MUX input
Resource
DMA
request
MUX input
Resource
DMA
request
MUX input
Resource
20
Reserved
74
TIM5_CH3
128
Reserved
21
Reserved
75
TIM5_CH4
129
Reserved
22
Reserved
76
TIM5_UP
130
CAN_SUB_1_DMU_1_TX
23
Reserved
77
TIM5_TRIG
131
CAN_SUB_1_DMU_1_TXE
24
UART1_RX
78
TIM15_CH1
132
CAN_SUB_1_DMU_1_RX0
25
UART1_TX
79
TIM15_UP
133
CAN_SUB_1_DMU_1_RX1
26
UART2_RX
80
TIM15_TRIG
134
CAN_SUB_1_DMU_2_TX
27
UART2_TX
81
TIM15_COM
135
CAN_SUB_1_DMU_2_TXE
28
UART3_RX
82
TIM16_CH1
136
CAN_SUB_1_DMU_2_RX0
29
UART3_TX
83
TIM16_UP
137
CAN_SUB_1_DMU_2_RX1
30
Reserved
84
TIM_TS_UP
138
CAN_SUB_1_DMU_3_TX
31
Reserved
85
Reserved
139
CAN_SUB_1_DMU_3_TXE
32
Reserved
86
Reserved
140
CAN_SUB_1_DMU_3_RX0
33
Reserved
87
Reserved
141
CAN_SUB_1_DMU_3_RX1
34
Reserved
88
Reserved
142
CAN_SUB_1_DMU_4_TX
35
Reserved
89
Reserved
143
CAN_SUB_1_DMU_4_TXE
36
ADC2
90
Reserved
144
CAN_SUB_1_DMU_4_RX0
37
ADC3
91
DAC1_CH1
145
CAN_SUB_1_DMU_4_RX1
38
ADC4
92
DAC1_CH2
146
CAN_SUB_1_M_CAN_1
39
ADC5
93
DAC2_CH1
147
CAN_SUB_1_M_CAN_2
40
Reserved
94
DAC2_CH2
148
Reserved
41
Reserved
95
HRTIM1_MASTE
R (hrtim_dma1)
149
Reserved
42
TIM1_CH1
96
HRTIM1_TIMA
(hrtim_dma2)
150
SD_ADC1
43
TIM1_CH2
97
HRTIM1_TIMB
(hrtim_dma3)
151
SD_ADC2
44
TIM1_CH3
98
HRTIM1_TIMC
(hrtim_dma4)
152
Reserved
45
TIM1_CH4
99
HRTIM1_TIMD
(hrtim_dma5)
153
Reserved
46
TIM1_UP
100
HRTIM1_TIME
(hrtim_dma6)
154
Reserved
47
TIM1_TRIG
101
HRTIM1_TIMF
(hrtim_dma7)
155
Reserved
48
TIM1_COM
102
DAC3_CH1
156
Reserved
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Table 19. DMAMUX: assignment of multiplexer inputs to resources (continued)
DMA
request
MUX input
Resource
DMA
request
MUX input
Resource
DMA
request
MUX input
Resource
49
TIM8_CH1
103
DAC3_CH2
157
Reserved
50
TIM8_CH2
104
DAC4_CH1
158
Reserved
51
TIM8_CH3
105
DAC4_CH2
159
Reserved
52
TIM8_CH4
106
SPI4_RX
160
Reserved
53
TIM8_UP
107
SPI4_TX
-
—
54
TIM8_TRIG
108
Reserved
-
—
Table 20. DMAMUX: assignment of trigger inputs to resources
Trigger input
Resource
Trigger input
Resource
0
EXTI LINE0
16
DMAMUX1_ch0_event
1
EXTI LINE1
17
DMAMUX1_ch1_event
2
EXTI LINE2
18
DMAMUX1_ch2_event
3
EXTI LINE3
19
DMAMUX1_ch3_event
4
EXTI LINE4
20
Reserved
5
EXTI LINE5
21
Reserved
6
EXTI LINE6
22
Reserved
7
EXTI LINE7
23
Reserved
8
EXTI LINE8
24
Reserved
9
EXTI LINE9
25
Reserved
10
EXTI LINE10
26
Reserved
11
EXTI LINE11
27
Reserved
12
EXTI LINE12
28
Reserved
13
EXTI LINE13
29
Reserved
14
EXTI LINE14
30
Reserved
15
EXTI LINE15
31
Reserved
Table 21. DMAMUX: assignment of synchronization inputs to resources
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Sync. input
Resource
Sync. input
Resource
0
EXTI LINE0
16
DMAMUX1_ch0_event
1
EXTI LINE1
17
DMAMUX1_ch1_event
2
EXTI LINE2
18
DMAMUX1_ch2_event
3
EXTI LINE3
19
DMAMUX1_ch3_event
4
EXTI LINE4
20
Reserved
5
EXTI LINE5
21
Reserved
6
EXTI LINE6
22
Reserved
RM0483 Rev 5
RM0483
Device configuration
Table 21. DMAMUX: assignment of synchronization inputs to resources (continued)
5.2.8
Sync. input
Resource
Sync. input
Resource
7
EXTI LINE7
23
Reserved
8
EXTI LINE8
24
Reserved
9
EXTI LINE9
25
Reserved
10
EXTI LINE10
26
Reserved
11
EXTI LINE11
27
Reserved
12
EXTI LINE12
28
Reserved
13
EXTI LINE13
29
Reserved
14
EXTI LINE14
30
Reserved
15
EXTI LINE15
31
Reserved
GPIO configuration
The General-Purpose I/O modules control the MCU pad configuration, ports, generalpurpose input and output (GPIO) signals and alternate function configuration.
The IOs are organized as 16-bit ports: ports A to I, also known as GPIOA to GPIOI. GPIOG
contains 13 pins from channel 3 to 15. GPIOI contains 9 pins from channel 0 to 9. Up to 135
user pins are available in QFP176, 103 user pins in QFP144 and 61 user pins in QFP100.
For more details, refer to Chapter 20: General-purpose I/Os (GPIO).
5.3
Memories and memory interfaces
See the following chapters for detailed information on memories and memory interfaces.
Table 22. Memories and memory interface references
Topic
System memory map
Flash controller
5.3.1
Reference
Chapter 3: System and memory overview
Chapter 16: Non volatile memory platform controller (NVMPC)
Embedded flash memory
Chapter 17: Embedded flash memory
Platform RAM controller
Chapter 15: Platform RAM controller AXI (PRAMC_AXI)
Non-volatile memory platform controller (NVMPC) configuration
Two non-volatile memory controllers and arrays are implemented. The NVMPCs provide
flash configuration and control functions and manage the interface between the flash
memory array and the bus matrix.
5.3.2
Platform RAM controller (PRAMC)
Two RAM controllers and arrays are implemented. The PRAMCs provide RAM configuration
and manage the interface between the SRAM arrays and the system bus.
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5.4
Analog modules
5.4.1
Temperature sensor configuration
The temperature sensor is used to measure the temperature of the SR5E1x device. The
temperature sensor has the following outputs:
•
•
Two analog voltages
–
A voltage signal that is linearly increasing with internal junction temperature (PTAT
that is proportional to absolute temperature)
–
A voltage signal that is linearly decreasing with internal junction temperature
(CTAT that is complementary proportional to absolute temperature)
Three digital outputs that signal under- or over-temperature operating conditions.
During production testing of the device, the output voltages of the temperature sensor are
sampled by SARADCx of the onboard ADC module, (refer to Table 23: ADCx connectivity (x
= 1..5), at a predefined high temperature and also at a predefined low temperature. These
calibration parameters are stored during production test into UTEST Flash memory (See
Section UTEST in Chapter Flash Memory.)
By converting the two analog outputs of the temperature sensor through ADC, one can find
out a constant reference code which does not change with temperature or the ADC
reference values. It is also called 'Digital Bandgap Voltage'. See Section 33.3.2: Equations
for converting TSENS voltages into constant reference (Digital Bandgap Voltage) in
Chapter 33: Temperature Sensor.
For more details, see Chapter 33: Temperature Sensor.
5.4.2
ADCx configuration
ADCx inputs are connected to the external channels as well as internal sources as
described in the following table.
Table 23. ADCx connectivity (x = 1..5)
ADCx
channel
number
ADCx
channel
type
ADCx_IN0
fast
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ADCx
Analog
inputs
ADC channel source assignment
ADC1
ADC2
ADC3
ADC4
ADC5
Vinp[0]
Vssa
Vssa
Vssa
Vssa
Vssa
Vinn[0]
Vssa
Vssa
Vssa
Vssa
Vssa
RM0483 Rev 5
RM0483
Device configuration
Table 23. ADCx connectivity (x = 1..5) (continued)
ADCx
channel
number
ADCx
channel
type
ADCx_IN1
fast
ADCx_IN2
ADCx_IN3
ADCx_IN4
fast
fast
fast
ADCx_IN5
fast
ADCx_IN6
slow
ADCx_IN7
slow
ADCx_IN8
slow
ADCx_IN9
slow
ADCx
Analog
inputs
ADC1
ADC2
ADC3
ADC4
ADC5
Vinp[1]
PB2
PB7
PB12
PC3
PC9
PB3
PB8
PB13
PC4
PC10
PB4
PB9
PB14
PC6
PC11
PB5
PB10
PB15
PC7
PC12
PB6
PB11
PC0
PC8
PC13
Vinn[5]
Vssa
Vssa
Vssa
Vssa
Vssa
Vinp[6]
PD3
PD6
PC14
PD1
PE6
Vinn[6]
Vssa
Vssa
Vssa
Vssa
Vssa
Vinp[7]
PD4
PD9
PC15
PD2
PE7
Vinn[7]
Vssa
Vssa
Vssa
Vssa
Vssa
Vinp[8]
PD5
PE0
PD0
PE5
PE8
Vinn[8]
Vssa
Vssa
Vssa
Vssa
Vssa
Vinp[9]
PC1
(SAR_CAL1)
PC1
(SAR_CAL1)
PC1
(SAR_CAL1)
PC1
(SAR_CAL1)
PC1
(SAR_CAL1)
(1)
(1)
(1)
(1)
PC2
(SAR_CAL2)
PC2
(SAR_CAL2)
PC2
(SAR_CAL2)
PC2
(SAR_CAL2)
PC2
(SAR_CAL2)
(2)
(2)
(2)
(2)
Vinn[10]
Vssa
Vssa
Vssa
Vssa
Vssa
Vinp[11]
PC7
PB15
PB10
PB5
Vdd_lv
Vinn[11]
Vssa
Vssa
Vssa
Vssa
Vssa
Vinp[12]
PC8
PC0
PB11
PB6
Vdd_hv
Vinn[12]
Vssa
Vssa
Vssa
Vssa
Vssa
Vinp[13]
TempSens
CTAT
Vdd_lv
B-DAC_CH1
Vdd_lv
TempSens
CTAT
Vinn[13]
Vssa
Vssa
Vssa
Vssa
Vssa
Vinp[14]
TempSens
PTAT
Vdd_hv
B-DAC_CH2
Vdd_hv
TempSens
PTAT
Vinn[14]
Vssa
Vssa
Vssa
Vssa
Vssa
Vinp[15]
PC6
PB12
PB9
PB4
B-DAC_CH1
Vinn[15]
Vssa
Vssa
Vssa
Vssa
Vssa
Vinn[1]
Vinp[2]
Vinn[2]
Vinp[3]
Vinn[3]
Vinp[4]
Vinn[4]
Vinp[5]
Vinn[9]
ADCx_IN10
slow
ADCx_IN11
slow
ADCx_IN12
slow
ADCx_IN13
slow
ADCx_IN14
ADCx_IN15
slow
slow
Vinp[10]
ADC channel source assignment
(1)
(2)
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Table 23. ADCx connectivity (x = 1..5) (continued)
ADCx
channel
number
ADCx
channel
type
ADCx_IN16
slow
ADCx_IN17
slow
ADCx_IN18
Bias
test(3)
ADCx_IN19
slow
ADCx
Analog
inputs
ADC channel source assignment
ADC1
ADC2
ADC3
ADC4
ADC5
Vinp[16]
PA13
PB13
PA15
PB2
PB7
Vinn[16]
Vssa
Vssa
Vssa
Vssa
Vssa
Vinp[17]
PA14
PB14
PB0
PB3
PB8
Vinn[17]
Vssa
Vssa
Vssa
Vssa
Vssa
Vinp[18]
Vref, Vref/3,
Vref*2/3
Vref, Vref/3,
Vref*2/3
Vref, Vref/3,
Vref*2/3
Vref, Vref/3,
Vref*2/3
Vref, Vref/3,
Vref*2/3
Vinn[18]
Vssa
Vssa
Vssa
Vssa
Vssa
Vinp[19]
Reserved
Reserved
Reserved
Reserved
Reserved
Vinn[19]
Reserved
Reserved
Reserved
Reserved
Reserved
1. SAR_CAL1 means Common Analog Level 1 for all SAR instances.
2. SAR_CAL2 means Common Analog Level 2 for all SAR instances.
3. BIAS test uses the “internal reference voltages” selected by the SYS_CFG.ST_VREF_SEL2 register. For details, refer to
the System configuration controller (SYSCFG) chapter.
Table 24. ADCs trigger selection
ADC trigger selection
EXTSEL[4:0] or
JEXTSEL[4:0]
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ADC trigger signal assignment
ADC 1/2
ADC3/4/5
Regular
Injected
Regular
Injected
0
tim1_cc1
tim1_trgo
tim3_cc1
tim1_trgo
1
tim1_cc2
tim1_cc4
tim3_cc1
tim1_cc4
2
tim1_cc3
tim2_trgo
tim2_cc3
tim2_trgo
3
tim2_cc2
tim2_cc1
tim8_cc1
tim8_cc2
4
tim3_trgo
tim3_cc4
tim3_trgo
tim4_cc3
5
tim4_cc4
tim4_trgo
exti2
tim4_trgo
6
exti11
exti15
tim4_cc1
tim4_cc4
7
tim8_trgo
tim8_cc4
tim8_trgo
tim8_cc4
8
tim8_trgo2
tim1_trgo2
tim8_trgo2
tim1_trgo2
9
tim1_trgo
tim8_trgo
tim1_trgo
tim8_trgo
10
tim1_trgo2
tim8_trgo2
tim1_trgo2
tim8_trgo2
11
tim2_trgo
tim3_cc3
tim2_trgo
tim1_cc3
12
tim4_trgo
tim3_trgo
tim4_trgo
tim3_trgo
13
tim6_trgo
tim3_cc1
tim6_trgo
exti3
14
tim15_trgo
tim6_trgo
tim15_trgo
tim6_trgo
15
tim3_cc4
tim15_trgo
tim2_cc1
tim15_trgo
RM0483 Rev 5
RM0483
Device configuration
Table 24. ADCs trigger selection (continued)
ADC trigger selection
EXTSEL[4:0] or
JEXTSEL[4:0]
5.4.3
ADC trigger signal assignment
ADC 1/2
ADC3/4/5
Regular
Injected
Regular
Injected
16
hrtim1_adc_trg1
hrtim1_adc_trg2
hrtim1_adc_trg1
hrtim1_adc_trg2
17
hrtim1_adc_trg3
hrtim1_adc_trg4
hrtim1_adc_trg3
hrtim1_adc_trg4
18
hrtim1_adc_trg5
hrtim1_adc_trg5
hrtim1_adc_trg5
hrtim1_adc_trg5
19
hrtim1_adc_trg6
hrtim1_adc_trg6
hrtim1_adc_trg6
hrtim1_adc_trg6
20
hrtim1_adc_trg7
hrtim1_adc_trg7
hrtim1_adc_trg7
hrtim1_adc_trg7
21
hrtim1_adc_trg8
hrtim1_adc_trg8
hrtim1_adc_trg8
hrtim1_adc_trg8
22
hrtim1_adc_trg9
hrtim1_adc_trg9
hrtim1_adc_trg9
hrtim1_adc_trg9
23
hrtim1_adc_trg10
hrtim1_adc_trg10
hrtim1_adc_trg10
hrtim1_adc_trg10
24
hrtim2_adc_trg1
hrtim2_adc_trg2
hrtim2_adc_trg1
hrtim2_adc_trg2
25
hrtim2_adc_trg3
hrtim2_adc_trg4
hrtim2_adc_trg3
hrtim2_adc_trg4
26
hrtim2_adc_trg5
hrtim2_adc_trg5
hrtim2_adc_trg5
hrtim2_adc_trg5
27
hrtim2_adc_trg6
hrtim2_adc_trg6
hrtim2_adc_trg6
hrtim2_adc_trg6
28
hrtim2_adc_trg7
hrtim2_adc_trg7
hrtim2_adc_trg7
hrtim2_adc_trg7
29
hrtim2_adc_trg8
hrtim2_adc_trg8
hrtim2_adc_trg8
hrtim2_adc_trg8
30
hrtim2_adc_trg9
hrtim2_adc_trg9
hrtim2_adc_trg9
hrtim2_adc_trg9
31
hrtim2_adc_trg10
hrtim2_adc_trg10
hrtim2_adc_trg10
hrtim2_adc_trg10
SDADC configuration
The Sigma-Delta Analog-to-Digital Converter (SDADC) digital interface block controls the
on-chip SDADC and holds control and status registers accessible for application. It provides
the accurate conversion data for a wide range of applications.
SR5E1x includes two independent 16-bit SDADCs.
Each module features two inputs configurable as two single-ended channels or one
differential channel.
5.4.3.1
Sigma-Delta ADC clock sources
Each Sigma-Delta ADC digital interface has a register clock input, which is separate from
the module clock input. The register interface is clocked by the APB2 bridge clock PCLK2.
The module clock is sourced by the modulator clock (SD_CLK). The input clock for the
Sigma-Delta modulator is the SD_CLK.
Both the analog and digital blocks of the ADC contain an internal clock Mux for external
modulator mode. The external modulator clock (EXT_CLK) can be input to the device, or
generated from SD_CLK from the RCC. The pad input/output settings in the corresponding
GPIOx pad control registers determine the external modulator clock source to the ADC
blocks. The EXT_CLK pins are multiplexed on multiple external pins on the device.
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Device configuration
RM0483
Selection of the EXT_CLK pin to use for the external modulator clock for each ADC is done
in the GPIOx configuration registers. Each Sigma-Delta ADC has two external pins to select
from for an external modulator clock.
5.4.3.2
SDADC analog input channel selection
For the Sigma-Delta Mux inputs AN[x], the positive and negative input terminals are
selected in the Sigma-Delta ADC digital interface Channel Selection Register (CSR).
This section shows analog channel selections for each combination of module
configuration.
Register (MCR) field values MCR_MODE and MCR_VCOMSEL. The following table
provides a quick reference key to the MCR fields used in the SD ADC analog input selection
tables that follow it.
Table 25. Register fields for SDADC analog input selection
Field
Description
MCR_VCOMSEL
Common voltage bias selection
This bit selects the common voltage bias for the negative input
terminal of SD ADC during single-ended mode (MODE=1).
0 Negative input terminal is biased with VREFN.
1 Negative input terminal is biased with VREFP/2 (half scale bias).
MCR_MODE
CSR_ANCHSEL
Mode selection
0 Differential input mode is selected.
1 Single-ended input mode is selected.
Analog channel selection
Based on single-ended or differential mode of operation (MODE bit of
MCR), common mode voltage selection (VCOMSEL bit of MCR), this
bit field defines the connectivity of analog inputs to either positive or
negative polarity terminals of Sigma-Delta ADC, as shown in the
following tables:
– Table 26 for channel selection
– Table 27 for input source selection
Table 26. SDADC analog input selection
MCR_MODE
MCR_VCOMSEL
0
1
1
108/2075
CSR_ANCHSEL
INP (positive
terminal)
000
AN[0]
001
AN[1]
111 .. 010
reserved
000
AN[0]
001
AN[1]
111 .. 010
reserved
RM0483 Rev 5
INM (negative
terminal)
VREFN
VREFP/2
RM0483
Device configuration
Table 26. SDADC analog input selection (continued)
MCR_MODE
0
MCR_VCOMSEL
0/1
CSR_ANCHSEL
INP (positive
terminal)
INM (negative
terminal)
000
AN[0]
AN[1]
001
Reserved
010
Reserved
011
Reserved
100
VREFN
VREFN
101
VREFP/2
VREFP/2
110
VREFP
VREFN
111
VREFN
VREFP
Table 27. SDADCx analog input source
5.4.3.3
SDADC channel number
SDADC1 pin name
SDADC2 pin name
AN[0]
SDADC1_IN0
(PA13)
SDADC2_IN0
(PA15)
AN[1]
SDADC1_IN1
(PA14)
SDADC2_IN1
(PB0)
SDADC starting/triggering
Each Sigma-Delta ADC supports starting the converter with a software write to an enable bit
in a register in the digital interface.
A method to start multiple Sigma-Delta converters simultaneously by a single software write
to a control register is available on the device. In this case, “simultaneously” means that all
selected converters start sampling their inputs on the same SD_CLK clock edge.
The digital interface of the Sigma-Delta ADC contains the control register for simultaneous
start of the ADCs. When the register is written to start multiple converters, an output from
the digital interface is asserted. The hardware trigger input of each Sigma-Delta ADC is
connected to this simultaneous start output. This way, the user controls which ADCs are
selected by enabling the hardware trigger of the desired ADCs before writing to the starting
simultaneous converters.
The connections for the simultaneous start of the converters are given in the figure below:
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Device configuration
RM0483
Figure 9. Sigma-Delta ADC simultaneous start connectivity
S/W trigger key (STKR)
Trigger en (MCR)
trigger
Trigger select (MCR)
Modulator
SD digital interface 0
S/W trigger key (STKR)
Trigger en (MCR)
trigger
Trigger select (MCR)
Modulator
SD digital interface 1
S/W trigger key (STKR)
Trigger en (MCR)
trigger
Trigger select (MCR)
5.4.3.4
Modulator
SD digital interface n
Sigma-Delta Mux input advance and wraparound
The Mux wraparound feature is enabled and controlled in the digital interface of the SigmaDelta ADC. The advancing of the Mux can be controlled in the interface by software only.
5.4.3.5
Conversion result interrupt/DMA
A DMA or interrupt can be generated for each conversion for each ADC. The Sigma-Delta
ADC has an 8-deep result FIFO.
The Sigma-Delta ADC digital interface has an input signal that is used to disable interrupt
and DMA requests for conversion results. The input signal is connected to outputs from the
timers modules. The digital interface has a register bit for enabling and disabling the
interrupt/DMA gating feature.
When the signal from a timer is asserted, no interrupt or DMA request is generated for any
conversion results. The polarity of the gating signal is such that when the signal is high,
interrupt and DMA requests are passed. When the gating signal is low, interrupt and DMA
requests are blocked.
110/2075
RM0483 Rev 5
RM0483
Device configuration
The gating signal for each ADC is driven by several signals coming from the timer modules
as listed in Table 28. The selection is done via the register SDADCx_EXT_GATE_SEL of
the System Configuration controller (SYSCFG).
For both SDADC instances, the interrupt/DMA selectable gating signals are:
5.4.3.6
•
tim1_oc1
•
tim1_oc5
•
tim8_oc1
•
tim8_oc5
•
tim2_oc4
•
tim3_oc4
•
tim4_oc4
•
tim5_oc4
•
tim15_oc2
•
hrtim1_CHE1
•
hrtim1_CHF1
•
hrtim2_CHE1
•
hrtim2_CHF1
Conversion limit watchdog output to timers
Each Sigma-Delta ADC provides an optional conversion limit check for upper and lower
bounds. The enable bit and the two 16-bit limit registers for the feature are included in the
SD ADC wrapper. If a conversion result exceeds one of the limits, a flag bit is asserted in a
status register in the SD ADC wrapper. The flag bit is output to TIMx timer input signals for
each SD ADC. Refer to the TIMx configuration sections for the interconnection details.
5.4.3.7
SDADC_MCR[TRIGSEL] definitions
The following input triggers apply.
Table 28. SDADC input triggers
SD_ADC_x
MCR[TRIGSEL]
Trigger input selection(1)
0000
SD_ADC_1_sw_trig_out: SDADC1 software trigger
0001
SD_ADC_2_sw_trig_out: SDADC2 software trigger
0010
tim1_trgo
0011
tim1_trgo2
0100
tim8_trgo
0101
tim8_trgo2
0110
tim2_trgo
0111
tim3_trgo
1000
tim4_trgo
1001
tim15_trgo
1010
hrtim1_adctrig1
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Device configuration
RM0483
Table 28. SDADC input triggers (continued)
SD_ADC_x
MCR[TRIGSEL]
Trigger input selection(1)
1011
hrtim1_adctrig2
1100
hrtim1_adctrig3
1101
hrtim2_adctrig1
1110
hrtim2_adctrig2
1111
hrtim2_adctrig3
1. This field selects which input is used for hardware-triggered conversions
Note:
Selecting the input trigger source to be from the output trigger of the same SD ADC is not
prohibited by hardware, but is not supported, and results in the SD ADC never responding
to the input trigger.
5.4.4
DAC configuration
The SR5E1x embeds five DAC modules. Each module contains two channels.
One module is called B-DAC and provides output buffers allowing to connect the signals
outside the device. The other four modules (DAC1 .. DAC4) signals are connected inside
the device.
DAC Digital Interface is clocked on AHB clock.
DAC Digital Interface receives LSIRCOSC/32 clock for Sample and Hold Mode
5.4.5
Comparator configuration
The device embeds eight (8) analog comparators. They are grouped by 4 at the register
interface level. The implementation is as follows:
•
Group1, on AHB2, contains comparators 1 to 4 (named as COMP1 to COMP4 through
this document)
•
Group2, on AHB1, contains comparators 5 to 8 (named as COMP5 to COMP8)
5.5
Timers
5.5.1
HRTIMx configuration
The SR5E1x includes two instances of High-resolution timer (HRTIM).
Both instances are clocked at the system clock frequency.
5.5.1.1
External events mapping and associated features
There are 2 sets of sources, refer to Table 29: HRTIM1 external events mapping and
associated features for HRTIM1 and Table 30: HRTIM2 external events mapping and
associated features for HRTIM2.
112/2075
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RM0483
Device configuration
Table 29. HRTIM1 external events mapping and associated features
Comparator and input
sources available per
package
Fast mode
Digital filter
Balanced fault
timer A,B,C
Balanced fault
timer D,E,F
Source (EExSRC[1:0])
hrtim_eev1
[4:1]
Yes
—
—
—
HRTIM1_EEV1
(PD4, PG6)
COMP2
TIM1_
TRGO
ADC1_
AWD1
Comp &
Comp &
input
input
(PG6)
Comp
& input
hrtim_eev2
[4:1]
Yes
—
—
—
HRTIM1_EEV2
(PD9)
COMP4
TIM2_
TRGO
ADC1_ Comp & Comp &
AWD2
input
input
Comp
& input
hrtim_eev3
[4:1]
Yes
—
—
—
HRTIM1_EEV3
(PF7, PG3)
COMP6
TIM3_
TRGO
ADC1_
AWD3
Comp & Comp &
input
input
(PG3)
(PG3)
Comp
& input
hrtim_eev4
[4:1]
Yes
—
—
—
HRTIM1_EEV4
(PG5)
COMP1 COMP5
ADC2_ Comp & Comp &
AWD1
input
input
Comp
& input
hrtim_eev5
[4:1]
Yes
—
—
—
HRTIM1_EEV5
(PH7)
COMP3 COMP7
ADC2_
AWD2
Comp
Comp
Comp
& input
hrtim_eev6
[4:1]
—
Yes
Yes
—
HRTIM1_EEV6
(PD6, PE0)
COMP2 COMP1
ADC2_
AWD3
Comp
Comp
Comp
& input
hrtim_eev7
[4:1]
—
Yes
Yes
—
HRTIM1_EEV7
(PG8)
COMP4
ADC3_ Comp & Comp &
AWD1
input
input
Comp
& input
hrtim_eev8
[4:1]
—
Yes
—
Yes
HRTIM1_EEV8
(PF8, PG4)
COMP6 COMP3
ADC4_
AWD1
Comp &
Comp &
input
input
(PG4)
Comp
& input
hrtim_eev9
[4:1]
—
Yes
—
Yes
HRTIM1_EEV9
(PG7)
COMP5
TIM15_
TRGO
COMP4
Comp & Comp &
input
input
Comp
& input
hrtim_eev10
[4:1]
—
Yes
—
—
HRTIM1_EEV10
COMP7
(PH7)
TIM6_
TRGO
ADC5_
AWD1
External
event
channel
Src1
(00)
Src 2
(01)
Src3
(10)
Src4
(11)
100-pin 144-pin 176-pin
RM0483 Rev 5
TIM7_
TRGO
—
Comp
Comp
& input
113/2075
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Device configuration
RM0483
Table 30. HRTIM2 external events mapping and associated features
Comparator and input
sources available per
package
Fast mode
Digital filter
Balanc-ed fault
timer A,B,C
Balanc-ed fault
timer D,E,F
Source (EExSRC[1:0])
hrtim_eev1
Yes
[4:1]
—
—
—
HRTIM2_EEV1
(PC15, PG10)
COMP1
TIM1_
TRGO
ADC1_
AWD1
Comp &
Comp &
input
input
(PC15)
Comp
& input
hrtim_eev2
Yes
[4:1]
—
—
—
HRTIM2_EEV2
(PF6)
COMP3
TIM2_
TRGO
ADC1_
AWD2
Comp
Comp
Comp
& input
hrtim_eev3
Yes
[4:1]
—
—
—
HRTIM2_EEV3
(PF9, PH11)
COMP5
TIM3_
TRGO
ADC1_
AWD3
Comp
Comp &
input
Comp
& input
hrtim_eev4
Yes
[4:1]
—
—
—
HRTIM2_EEV4
(PG9)
COMP2
COMP6
_OUT
ADC2_
AWD1
Comp
Comp &
input
Comp
& input
hrtim_eev5
Yes
[4:1]
—
—
—
HRTIM2_EEV5
(PH9)
COMP4
COMP8
_OUT
ADC2_
AWD2
Comp
Comp
Comp
& input
hrtim_eev6
[4:1]
—
Yes
Yes
—
HRTIM2_EEV6
(PE13)
COMP1
COMP2
_OUT
ADC2_
AWD3
Comp
Comp
Comp
& input
hrtim_eev7
[4:1]
—
Yes
Yes
—
HRTIM2_EEV7
(PG11)
COMP3
TIM7_
TRGO
ADC3_ Comp & Comp &
AWD1
input
input
Comp
& input
hrtim_eev8
[4:1]
—
Yes
—
Yes
HRTIM2_EEV8
(PF10, PG12)
COMP5
COMP4
_OUT
ADC4_
AWD1
Comp & Comp &
input
input
(PG12) (PG12)
Comp
& input
hrtim_eev9
[4:1]
—
Yes
—
Yes
HRTIM2_EEV9
(PA2)
COMP6
TIM15_
TRGO
COMP4
_OUT
Comp
Comp
Comp
& input
hrtim_eev1
0[4:1]
—
Yes
—
—
HRTIM2_EEV10
COMP8
(PH9)
TIM6_
TRGO
ADC5_
AWD1
—
Comp
Comp
& input
5.5.1.2
HRTIM fault inputs
External
event
channel
Src1
(00)
Src 2
(01)
Src3
(10)
Src4
(11)
100-pin 144-pin 176-pin
Figure 10. hrtim_sys_flt connection
114/2075
RM0483 Rev 5
RM0483
Device configuration
Each HRTIM has a system fault input (hrtim_sys_flt) connected to the FCCU module and
the RCC module.
The hrtim_sys_flt is asserted when the FCCU is “in fault state” or when the RCC indicated
the switch of the system clock on safe clock. The enabling of HRTIM system fault individual
sources is SW programmable by the system configuration controller (SYSCFG) in the
HRTIMxFLT_TIMxBRK_EN register.
There are 2 sets of fault inputs, refer to Table 31: HRTIM1 fault inputs (protection) for
HRTIM1 and Table 32: HRTIM2 fault inputs (protection) for HRTIM2.
Table 31. HRTIM1 fault inputs (protection)
Fault channel
External Input
FLTxSRC[1:0] = 00
On-chip source
FLTxSRC[1:0] = 01
External Input
FLTxSRC[1:0] = 10
On-chip source
FLTxSRC[1:0] = 11
hrtim_flt1[4:1]
HRTIM_FLT1
(PA8/PI7)
Comparator output
(COMP2)
EEV1_muxout
HRTIM2_EEV1_muxout
hrtim_flt2[4:1]
HRTIM_FLT2
(PB1/PI5)
Comparator output
(COMP4)
EEV2_muxout
HRTIM2_EEV2_muxout
hrtim_flt3[4:1]
HRTIM_FLT3
(PI3)
Comparator output
(COMP6)
EEV3_muxout
HRTIM2_EEV3_muxout
hrtim_flt4[4:1]
HRTIM_FLT4
(PI1)
Comparator output
(COMP1)
EEV4_muxout
HRTIM2_EEV4_muxout
hrtim_flt5[4:1]
HRTIM_FLT5
(PI9)
Comparator output
(COMP3)
EEV5_muxout
HRTIM2_EEV5_muxout
hrtim_flt6[4:1]
HRTIM_FLT6
(PI8)
Comparator output
(COMP5)
EEV6_muxout
HRTIM2_EEV6_muxout
Table 32. HRTIM2 fault inputs (protection)
Fault channel
External Input
FLTxSRC[1:0] = 00
On-chip source
FLTxSRC[1:0] = 01
External Input
FLTxSRC[1:0] = 10
On-chip source
FLTxSRC[1:0] = 11
hrtim_flt1[4:1]
HRTIM_FLT1
(PD5)
Comparator output
(COMP1)
EEV1_muxout
HRTIM1_EEV1_muxout
hrtim_flt2[4:1]
HRTIM_FLT2
(PD3)
Comparator output
(COMP3)
EEV2_muxout
HRTIM1_EEV2_muxout
hrtim_flt3[4:1]
HRTIM_FLT3
(PD0)
Comparator output
(COMP5)
EEV3_muxout
HRTIM1_EEV3_muxout
hrtim_flt4[4:1]
HRTIM_FLT4
(PC14)
Comparator output
(COMP2)
EEV4_muxout
HRTIM1_EEV4_muxout
hrtim_flt5[4:1]
HRTIM_FLT5
(PD2)
Comparator output
(COMP4)
EEV5_muxout
HRTIM1_EEV5_muxout
hrtim_flt6[4:1]
HRTIM_FLT6
(PH10)
Comparator output
(COMP6)
EEV6_muxout
HRTIM1_EEV6_muxout
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Device configuration
5.5.1.3
RM0483
HRTIM DAC triggers connections
Table 33. HRTIM1 DAC triggers connections
HRTIM DAC triggers
DAC1_CH1
DAC1_CH2
DAC2_CH1
DAC2_CH2
DAC3_CH1
DAC3_CH2
DAC4_CH1
DAC4_CH2
hrtim_dac_trg1
Yes
—
—
—
hrtim_dac_trig2
—
Yes
—
—
hrtim_dac_reset_trg_A
hrtim_dac_step_trg_A
Yes
Yes
Yes
Yes
hrtim_dac_reset_trg_B
hrtim_dac_step_trg_B
Yes
Yes
Yes
Yes
hrtim_dac_reset_trg_C
hrtim_dac_step_trg_C
Yes
Yes
Yes
Yes
hrtim_dac_reset_trg_D
hrtim_dac_step_trg_D
Yes
Yes
Yes
Yes
hrtim_dac_reset_trg_E
hrtim_dac_step_trg_E
Yes
Yes
Yes
Yes
hrtim_dac_reset_trg_F
hrtim_dac_step_trg_F
Yes
Yes
Yes
Yes
Table 34. HRTIM2 DAC triggers connections
116/2075
HRTIM DAC triggers
DAC1_CH1
DAC1_CH2
DAC2_CH1
DAC2_CH2
DAC3_CH1
DAC3_CH2
DAC4_CH1
DAC4_CH2
hrtim_dac_trg1
—
—
Yes
—
hrtim_dac_trig2
—
—
—
Yes
hrtim_dac_reset_trg_A
hrtim_dac_step_trg_A
Yes
Yes
Yes
Yes
hrtim_dac_reset_trg_B
hrtim_dac_step_trg_B
Yes
Yes
Yes
Yes
hrtim_dac_reset_trg_C
hrtim_dac_step_trg_C
Yes
Yes
Yes
Yes
hrtim_dac_reset_trg_D
hrtim_dac_step_trg_D
Yes
Yes
Yes
Yes
hrtim_dac_reset_trg_E
hrtim_dac_step_trg_E
Yes
Yes
Yes
Yes
hrtim_dac_reset_trg_F
hrtim_dac_step_trg_F
Yes
Yes
Yes
Yes
RM0483 Rev 5
RM0483
5.5.1.4
Device configuration
HRTIM update and synchronization signals
Table 35. HRTIMx burst mode (x = {1; 2})
HRTIMx Burst mode trigger event/ clock
signal name
HRTIM Burst mode trigger event/ clock signal
assignment
hrtimx_bm_trg
tim7_trgo
hrtimx_bm_ck1
tim16_oc1
hrtimx_bm_ck2
Reserved
hrtimx_bm_ck3
tim7_trgo
hrtimx_bm_ck4
Reserved
Table 36. HRTIMx update enable signals (x = {1; 2})
HRTIM update enable signal
HRTIM update enable assignment
hrtim_upd_en1
tim16_oc1
hrtim_upd_en2
SW control, see HRTIMx_UPDATE_EN in
SYSCFG chapter
hrtim_upd_en3
tim6_trgo
Table 37. HRTIM1 synchronization input signals
HRTIM1 synchronization input
HRTIM1 synchronization signal source
hrtim1_in_sync1
Reserved (not used)
hrtim1_in_sync2
tim1_trgo
hrtim1_in_sync3
HRTIM_SCIN pin (pad PA3)
Table 38. HRTIM1 synchronization output signals
HRTIM1 synchronization output
HRTIM1 synchronization output destination
hrtim1_out_sync[1]
hrtim1_scout1 (internal signal to HRTIM2)
hrtim1_out_sync[2]
HRTIM1_SCOUT (pad PA2)
hrtim1_out_sync2 (internal signal to TIMx)
Table 39. HRTIM2 synchronization input signals
HRTIM2 synchronization input
HRTIM2 synchronization signal source
hrtim2_in_sync1
hrtim1_out_sync[1] (aka hrtim1_scout1)
hrtim2_in_sync2
tim1_trgo
hrtim2_in_sync3
HRTIM_SCIN (pad PA3)
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Device configuration
RM0483
Table 40. HRTIM2 synchronization output signals
5.5.2
HRTIM2 synchronization output
HRTIM2 synchronization output destination
hrtim2_out_sync[1]
Reserved (not used)
hrtim2_out_sync[2]
hrtim2_out_sync2 (internal signal to TIMx)
TIMx timer overview
The following section gives an overview of the features implemented in the various TIMx
Timer modules.
TIMx instances with x=2, 3, 6, 7, TS uses twice the APB1 clock as reference (that is half of
the system clock).
TIMx instances with x=1, 8, 4, 5, 15, 16 uses twice the APB2 clock as reference (that is the
system clock).
Table 41. TIMX instance features overview
TIM1
TIM8
TIM2
TIM3
TIM4
TIM5
TIM15
TIM16
16
16
Feature
Adv Control
Resolution
(bits)
16
16
General Purpose
32
16
Prescaler
Counter
direction
Number of
channels
32
16-bit
Up, Down,
Up&Down
Up, Down, Up&Down
6:
– CH1/1N..CH4/4N
– CH5 & CH6
– CH1..CH4
output only (not
on pads)
4:
Up
2:
1:
– CH1/1N – CH1/1
N
– CH2
Input capture
mode
Yes
Yes
PWM input
mode
Yes
Yes
Forced
output mode
Yes
Yes
Yes
Output
compare
mode
Yes
Yes
Yes
Standard
Asymmetric
Combined
Standard
Asymm. Standard
Combined
Yes
Yes
Standard
Asymmetric
PWM modes
Combined
Combined 3-phase
6-step PWM
PWM
dithering
118/2075
16
Yes
RM0483 Rev 5
Yes
Yes
No
RM0483
Device configuration
Table 41. TIMX instance features overview (continued)
TIM1
TIM8
TIM2
TIM3
TIM4
TIM5
TIM15
TIM16
Feature
Adv Control
General Purpose
Prog. deadtime
Yes: CH1..CH4
No
Yes: CH1
Break inputs
2x
Bidirectional
No
1x
Bidirectional
One-Pulse
Mode
Yes
Yes
Yes
Retrig. One
pulse mode
Yes
Yes
Yes
No
Encoder
interface
mode
Quadrature
Clock plus direction
Directional clock
Quadrature
Clock plus direction
Directional clock
No
No
Index input
Yes
Yes
No
Encoder
error
management
Yes
Yes
No
Timer input
XOR
function
Yes
Yes
DMA
Yes
Yes
Yes
No
Yes
Table 42. TIMx Basic & timestamp timer features overview
Feature
TIM6
TIM7
TIM_TS
Resolution (bits)
16
32
Prescaler
16-bit
16-bit
Counter direction
Up
Up
Number of channels
0
0
DMA
Yes
Yes
5.5.3
TIM1/TIM8 configuration
5.5.3.1
Interconnects to the tim_ti[1..4] input multiplexers
Table 43. Interconnect to the TIMx tim_ti1 input multiplexer (x=1, 8)
Sources
tim_ti1 input
TIM1
TIM8
tim_ti1_in0
TIM1_CH1
TIM8_CH1
tim_ti1_in1
comp1_out
comp1_out
RM0483 Rev 5
119/2075
162
Device configuration
RM0483
Table 43. Interconnect to the TIMx tim_ti1 input multiplexer (x=1, 8) (continued)
Sources
tim_ti1 input
TIM1
TIM8
tim_ti1_in2
comp2_out
comp2_out
tim_ti1_in3
comp3_out
comp3_out
tim_ti1_in4
comp4_out
comp4_out
tim_ti1_in5
sdadc1_watchdog
sdadc1_watchdog
tim_ti1_in6
sdadc2_watchdog
sdadc2_watchdog
tim_ti1_in7
sdadc1_data_available
sdadc1_data_available
tim_ti1_in8
sdadc2_data_available
sdadc2_data_available
Reserved
Reserved
tim_ti1_in[9..15]
Table 44. Interconnect to the TIMx tim_ti2 input multiplexer (x=1, 8)
Sources
tim_ti1 input
TIM1
TIM8
tim_ti2_in0
TIM1_CH2
TIM8_CH2
tim_ti2_in[1..15]
Reserved
Reserved
Table 45. Interconnect to the TIMx tim_ti3 input multiplexer (x=1, 8)
Sources
tim_ti1 input
TIM1
TIM8
tim_ti3_in0
TIM1_CH3
TIM8_CH3
tim_ti3_in1
sdadc1_watchdog
sdadc1_watchdog
tim_ti3_in2
sdadc2_watchdog
sdadc2_watchdog
tim_ti3_in3
sdadc1_data_available
sdadc1_data_available
tim_ti3_in4
sdadc2_data_available
sdadc2_data_available
Reserved
Reserved
tim_ti3_in[5..15]
Table 46. Interconnect to the TIMx tim_ti4 input multiplexer (x=1, 8)
Sources
tim_ti1 input
TIM1
TIM8
tim_ti4_in0
TIM1_CH4
TIM8_CH4
tim_ti4_in1
sdadc1_data_available
sdadc1_data_available
tim_ti4_in2
sdadc2_data_available
sdadc2_data_available
Reserved
Reserved
tim_ti4_in[3..15]
120/2075
RM0483 Rev 5
RM0483
5.5.3.2
Device configuration
Interconnects to the trigger input multiplexers
Table 47. TIMx internal trigger connection (x=1, 8)
TIMx
TIM1
TIM8
tim_itr0
Reserved
tim1_trgo
tim_itr1
tim2_trgo
tim2_trgo
tim_itr2
tim3_trgo
tim3_trgo
tim_itr3
tim4_trgo
tim4_trgo
tim_itr4
tim5_trgo
tim5_trgo
tim_itr5
tim8_trgo
Reserved
tim_itr6
tim15_trgo
tim15_trgo
tim_itr7
tim16_oc1
tim16_oc1
tim_itr8
Reserved
Reserved
tim_itr9
hrtim2_out_scout2
hrtim2_out_scout2
tim_itr10
hrtim1_out_scout2
hrtim1_out_scout2
tim_itr[11..15]
Reserved
Reserved
Table 48. TIMx external trigger connection (x=1, 8)
Timer external trigger
input signal
Timer external trigger signals assignment
TIM1
TIM8
tim_etr0
TIM1_ETR
TIM8_ETR
tim_etr1
comp1_out
comp1_out
tim_etr2
comp2_out
comp2_out
tim_etr3
comp3_out
comp3_out
tim_etr4
comp4_out
comp4_out
tim_etr5
comp5_out
comp5_out
tim_etr6
comp6_out
comp6_out
tim_etr7
comp7_out
comp7_out
tim_etr8
comp8_out
comp8_out
tim_etr9
adc1_awd1
adc2_awd1
tim_etr10
adc1_awd2
adc2_awd2
tim_etr11
adc1_awd3
adc2_awd3
tim_etr12
adc4_awd1
adc3_awd1
tim_etr13
adc4_awd2
adc3_awd2
tim_etr14
adc4_awd3
adc3_awd3
tim_etr15
Reserved
Reserved
RM0483 Rev 5
121/2075
162
Device configuration
5.5.3.3
RM0483
Interconnects to the break & break2 inputs
Table 49. TIMx break interconnect (x=1, 8)
tim_brk input
TIM1
TIM8
TIMx_BKIN
TIM1_BKIN pin
TIM8_BKIN pin
tim_brk_cmp1
comp1_out
comp1_out
tim_brk_cmp2
comp2_out
comp2_out
tim_brk_cmp3
comp3_out
comp3_out
tim_brk_cmp4
comp4_out
comp4_out
tim_brk_cmp5
comp5_out
comp5_out
tim_brk_cmp6
comp6_out
comp6_out
tim_brk_cmp7
comp7_out
comp7_out
tim_brk_cmp8
comp8_out
comp8_out
Table 50. TIMx break2 interconnect (x=1, 8)
5.5.3.4
tim_brk input
TIM1
TIM8
TIMx_BKIN2
TIM1_BKIN2 pin
TIM8_BKIN2 pin
tim_brk2_cmp1
comp1_out
comp1_out
tim_brk2_cmp2
comp2_out
comp2_out
tim_brk2_cmp3
comp3_out
comp3_out
tim_brk2_cmp4
comp4_out
comp4_out
tim_brk2_cmp5
comp5_out
comp5_out
tim_brk2_cmp6
comp6_out
comp6_out
tim_brk2_cmp7
comp7_out
comp7_out
tim_brk2_cmp8
comp8_out
comp8_out
Interconnects to the ocref_clr input multiplexer
Table 51. Interconnect to the TIMx ocref_clr input multiplexer (x=1, 8)
Timer OCREF clear signals assignment
Timer OCREF clear signal
122/2075
TIM1
TIM8
tim_ocref_clr0
comp1_out
comp1_out
tim_ocref_clr1
comp2_out
comp2_out
tim_ocref_clr2
comp3_out
comp3_out
tim_ocref_clr3
comp4_out
comp4_out
tim_ocref_clr4
comp5_out
comp5_out
tim_ocref_clr5
comp6_out
comp6_out
RM0483 Rev 5
RM0483
Device configuration
Table 51. Interconnect to the TIMx ocref_clr input multiplexer (x=1, 8) (continued)
Timer OCREF clear signals assignment
Timer OCREF clear signal
TIM1
TIM8
tim_ocref_clr6
comp7_out
comp7_out
tim_ocref_clr7
—
—
5.5.4
TIM2/TIM3/TIM4/TIM5 configuration
5.5.4.1
Interconnects to the tim_ti[1..4] input multiplexers
Table 52. Interconnect to the TIMx tim_ti1 input multiplexer (x=2..5)
Sources
tim_ti1 input
TIM2
TIM3
TIM4
TIM5
tim_ti1_in0
TIM2 external TI1
input pins
TIM3 external TI1
input pins
TIM4 external TI1
input pins
TIM5 external TI1
input pins
tim_ti1_in1
comp1_out
comp1_out
comp1_out
LSI
tim_ti1_in2
comp2_out
comp2_out
comp2_out
Reserved
tim_ti1_in3
comp3_out
comp3_out
comp3_out
comp1_out
tim_ti1_in4
comp4_out
comp4_out
comp4_out
comp2_out
tim_ti1_in5
comp5_out
comp5_out
comp5_out
comp3_out
tim_ti1_in6
sdadc1_watchdog
comp6_out
comp6_out
comp4_out
tim_ti1_in7
sdadc2_watchdog
comp7_out
comp7_out
comp5_out
tim_ti1_in8
sdadc1_data_
available
comp8_out
comp8_out
comp6_out
tim_ti1_in9
sdadc2_data_
available
sdadc1_watchdog
sdadc1_watchdog
comp7_out
tim_ti1_in10
Reserved
sdadc2_watchdog
sdadc2_watchdog
comp8_out
tim_ti1_in[11..15]
Reserved
Reserved
Reserved
Reserved
Table 53. Interconnect to the TIMx tim_ti2 input multiplexer (x=2..5)
Sources
tim_ti2 input
TIM2
TIM3
TIM4
TIM5
tim_ti2_in0
TIM2 external TI2
input pins
TIM3 external TI2
input pins
TIM4 external TI2
input pins
TIM5 external TI2
input pins
tim_ti2_in1
comp1_out
comp1_out
comp1_out
comp1_out
tim_ti2_in2
comp2_out
comp2_out
comp2_out
comp2_out
tim_ti2_in3
comp3_out
comp3_out
comp3_out
comp3_out
tim_ti2_in4
comp4_out
comp4_out
comp4_out
comp4_out
RM0483 Rev 5
123/2075
162
Device configuration
RM0483
Table 53. Interconnect to the TIMx tim_ti2 input multiplexer (x=2..5) (continued)
Sources
tim_ti2 input
TIM2
TIM3
TIM4
TIM5
tim_ti2_in5
comp5_out
comp5_out
comp5_out
comp5_out
tim_ti2_in6
comp6_out
comp6_out
comp6_out
comp6_out
tim_ti2_in7
comp7_out
comp7_out
comp7_out
comp7_out
tim_ti2_in8
comp8_out
comp8_out
comp8_out
comp8_out
tim_ti2_in[9..15]
Reserved
Reserved
Reserved
Reserved
Table 54. Interconnect to the TIMx tim_ti3 input multiplexer (x=2..5)
Sources
tim_ti3 input
TIM2
tim_ti3_in0
TIM3
TIM4
TIM5
TIM2 external TI3 input TIM3 external TI3 input TIM4 external TI3 input TIM5 external TI3 input
pins
pins
pins
pins
tim_ti3_in1
comp4_out
comp3_out
comp5_out
sdadc1_watchdog
tim_ti3_in2
sdadc1_watchdog
sdadc1_watchdog
sdadc1_watchdog
sdadc2_watchdog
tim_ti3_in3
sdadc2_watchdog
sdadc2_watchdog
sdadc2_watchdog
sdadc1_data_available
tim_ti3_in4
sdadc1_data_available sdadc1_data_available sdadc1_data_available sdadc2_data_available
tim_ti3_in5
sdadc2_data_available sdadc2_data_available sdadc2_data_available
tim_ti3_in
[6..15]
Reserved
—
Reserved
Reserved
Reserved
Table 55. Interconnect to the TIMx tim_ti4 input multiplexer (x=2..5)
Sources
tim_ti4 input
TIM2
tim_ti4_in0
TIM3
TIM4
TIM5
TIM2 external TI4 input TIM3 external TI4 input TIM4 external TI4 input TIM5 external TI4 input
pins
pins
pins
pins
tim_ti4_in1
comp1_out
sdadc1_data_available
comp6_out
sdadc1_data_available
tim_ti4_in2
comp2_out
sdadc2_data_available
sdadc1_watchdog
sdadc2_data_available
tim_ti4_in3
sdadc1_watchdog
Reserved
sdadc2_watchdog
Reserved
tim_ti4_in4
sdadc2_watchdog
Reserved
sdadc1_data_available
Reserved
tim_ti4_in5
sdadc1_data_available
Reserved
sdadc2_data_available
Reserved
tim_ti4_in6
sdadc2_data_available
Reserved
Reserved
Reserved
tim_ti4_in
[7..15]
Reserved
Reserved
Reserved
Reserved
124/2075
RM0483 Rev 5
RM0483
5.5.4.2
Device configuration
Interconnects to the trigger input multiplexers
Table 56. TIMx internal trigger connection (x=2..5)
TIMx
TIM2
TIM3
TIM4
TIM5
tim_itr0
tim1_trgo
tim1_trgo
tim1_trgo
tim1_trgo
tim_itr1
Reserved
tim2_trgo
tim2_trgo
tim2_trgo
tim_itr2
tim3_trgo
Reserved
tim3_trgo
tim3_trgo
tim_itr3
tim4_trgo
tim4_trgo
Reserved
tim4_trgo
tim_itr4
tim5_trgo
tim5_trgo
tim5_trgo
Reserved
tim_itr5
tim8_trgo
tim8_trgo
tim8_trgo
tim8_trgo
tim_itr6
tim15_trgo
tim15_trgo
tim15_trgo
tim15_trgo
tim_itr7
tim16_oc1
tim16_oc1
tim16_oc1
tim16_oc1
tim_itr8
Reserved
Reserved
Reserved
Reserved
tim_itr9
hrtim2_out_scout2
hrtim2_out_scout2
hrtim2_out_scout2
hrtim2_out_scout2
tim_itr10
hrtim1_out_scout2
hrtim1_out_scout2
hrtim1_out_scout2
hrtim1_out_scout2
tim_itr[11..15]
Reserved
Reserved
Reserved
Reserved
Table 57. TIMx external trigger connection (x=2..5)
Timer external
trigger input signal
Timer external trigger signals assignment
TIM2
TIM3
TIM4
TIM5
tim_etr0
TIM2_ETR
TIM3_ETR
TIM4_ETR
TIM5_ETR
tim_etr1
comp1_out
comp1_out
comp1_out
comp1_out
tim_etr2
comp2_out
comp2_out
comp2_out
comp2_out
tim_etr3
comp3_out
comp3_out
comp3_out
comp3_out
tim_etr4
comp4_out
comp4_out
comp4_out
comp4_out
tim_etr5
comp5_out
comp5_out
comp5_out
comp5_out
tim_etr6
comp6_out
comp6_out
comp6_out
comp6_out
tim_etr7
comp7_out
comp7_out
comp7_out
comp7_out
tim_etr8
comp8_out
comp8_out
comp8_out
comp8_out
tim_etr9
tim3_etr
tim2_etr
tim3_etr
tim2_etr
tim_etr10
tim4_etr
tim4_etr
tim5_etr
tim3_etr
tim_etr11
tim5_etr
Reserved
adc1_awd1
adc1_awd1
tim_etr12
adc1_awd1
adc2_awd1
adc2_awd1
adc2_awd1
tim_etr13
adc2_awd1
adc2_awd2
adc3_awd1
adc3_awd1
tim_etr14
adc3_awd1
adc2_awd3
adc4_awd1
adc4_awd1
tim_etr15
adc4_awd1
Reserved
adc5_awd1
adc5_awd1
RM0483 Rev 5
125/2075
162
Device configuration
5.5.4.3
RM0483
Interconnects to the ocref_clr input multiplexer
Table 58. Interconnect to the TIMx ocref_clr input multiplexer (x=2..5)
Timer OCREF clear
signal
Timer OCREF clear signals assignment
TIM2
TIM3
TIM4
TIM5
tim_ocref_clr0
comp1_out
comp1_out
Reserved
Reserved
tim_ocref_clr1
comp2_out
comp2_out
Reserved
Reserved
tim_ocref_clr2
comp3_out
comp3_out
Reserved
Reserved
tim_ocref_clr3
comp4_out
comp4_out
Reserved
Reserved
tim_ocref_clr4
comp5_out
comp5_out
Reserved
Reserved
tim_ocref_clr5
comp6_out
comp6_out
Reserved
Reserved
tim_ocref_clr6
comp7_out
comp7_out
Reserved
Reserved
tim_ocref_clr7
—
—
Reserved
Reserved
5.5.5
TIM15/TIM16 configuration
5.5.5.1
Interconnects to the tim_ti[1..4] input multiplexers
Table 59. Interconnect to the TIMx tim_ti1 input multiplexer (x=15, 16)
Sources
tim_ti1 input
126/2075
TIM15
TIM16
tim_ti1_in0
TIM15 external TI1 input pins
TIM16 external TI1 input pins
tim_ti1_in1
Reserved
comp6_out
tim_ti1_in2
comp1_out
MCO
tim_ti1_in3
comp2_out
HSE_Div32
tim_ti1_in4
comp5_out
Reserved
tim_ti1_in5
comp7_out
LSI
tim_ti1_in6
sdadc1_data_available
sdadc1_watchdog
tim_ti1_in7
sdadc2_data_available
sdadc2_watchdog
tim_ti1_in8
Reserved
sdadc1_data_available
tim_ti1_in9
Reserved
sdadc2_data_available
tim_ti1_in[10..15]
Reserved
Reserved
RM0483 Rev 5
RM0483
Device configuration
Table 60. Interconnect to the TIMx tim_ti2 input multiplexer (x=15)
Source
tim_ti1 input
TIM15
5.5.5.2
tim_ti2_in0
TIM15 external TI2 input pins
tim_ti2_in1
comp2_out
tim_ti2_in2
comp3_out
tim_ti2_in3
comp6_out
tim_ti2_in4
comp7_out
tim_ti2_in5
sdadc1_watchdog
tim_ti2_in6
sdadc2_watchdog
tim_ti2_in7
sdadc1_data_available
tim_ti2_in8
sdadc2_data_available
tim_ti2_in[9..15]
Reserved
Interconnects to the trigger input multiplexers
Table 61. TIM15 internal trigger connection
5.5.5.3
TIMx
TIM15
tim_itr0
tim1_trgo
tim_itr1
tim2_trgo
tim_itr2
tim3_trgo
tim_itr3
tim4_trgo
tim_itr4
tim5_trgo
tim_itr5
tim8_trgo
tim_itr6
Reserved
tim_itr7
tim16_oc1
tim_itr8
Reserved
tim_itr9
hrtim2_out_scout2
tim_itr10
hrtim1_out_scout2
tim_itr[11..15]
Reserved
Interconnects to the break inputs
Table 62. TIMx break interconnect (x=15, 16)
tim_brk input
TIM15
TIM16
TIMx_BKIN
TIM15_BKIN pin
TIM16_BKIN pin
tim_brk_cmp1
comp1_out
comp1_out
RM0483 Rev 5
127/2075
162
Device configuration
RM0483
Table 62. TIMx break interconnect (x=15, 16) (continued)
5.5.5.4
tim_brk input
TIM15
TIM16
tim_brk_cmp2
comp2_out
comp2_out
tim_brk_cmp3
comp3_out
comp3_out
tim_brk_cmp4
comp4_out
comp4_out
tim_brk_cmp5
comp5_out
comp5_out
tim_brk_cmp6
comp6_out
comp6_out
tim_brk_cmp7
comp7_out
comp7_out
tim_brk_cmp8
comp8_out
comp8_out
Interconnects to the ocref_clr input multiplexer
Table 63. Interconnect to the TIMx ocref_clr input multiplexer (x=15, 16)
Timer OCREF clear signals assignment
Timer OCREF clear signal
5.5.6
TIM15
TIM16
tim_ocref_clr0
comp1_out
comp1_out
tim_ocref_clr1
comp2_out
comp2_out
tim_ocref_clr2
comp3_out
comp3_out
tim_ocref_clr3
comp4_out
comp4_out
tim_ocref_clr4
comp5_out
comp5_out
tim_ocref_clr5
comp6_out
comp6_out
tim_ocref_clr6
comp7_out
comp7_out
tim_ocref_clr7
—
—
Timestamp timer configuration
The SR5E1x features one 32-bit timestamp timer (TIM_TS).
TIM_TS generates timestamp information for the SDADC and CAN modules.
TIM_TS is clocked by the APB1 clock (PCLK1).
5.5.7
Independent watchdog (IWDG)
The SR5E1x includes two IWDG: IWDG1 and IWDG2.
Both IWDG instances are clocked by the internal RC Oscillator (IRCOSC, 16 MHz) and by
default disabled.
They can be enabled by hardware after reset via the bits IWDG1_HW and IWDG2_HW of
the UTEST Miscellaneous DCF record.
5.5.8
System window watchdog (WWDG)
The SR5E1x includes two WWDG: WWDG1 and WWDG2.
128/2075
RM0483 Rev 5
RM0483
Device configuration
Both instances are clocked at the APB1 bridge frequency.
The WWDGs can trigger an early warning interrupt (WWDG1 to Core1, WWDG2 to Core2).
5.5.9
RTC configuration
The real-time clock (RTC) is an independent Binary-Coded Decimal (BCD) timer/counter.
It can be used for counting long time intervals, but it cannot be used as real RTC as data is
not maintained in an ALWAYS_ON domain.
The RTC clock source is configured by the Reset and clock control module (RCC). The
possible clock sources are:
•
the internal low speed RC oscillator (LSI), with a configurable prescaler
•
the external clock (XOSC), with a configurable prescaler
The RTC events (Alarm, WakeUp Timer) can generate an interrupt, passing through the
EXTI module.
5.6
Communication interfaces
5.6.1
CAN subsystem configuration
For the CAN subsystem configuration refer to Chapter 46: CAN subsystem.
5.6.2
SPI configuration
The SR5E1x contains four Serial peripheral interface (SPI/I2S) modules.
The instances SPI2 and SPI3 feature in addition to the / inter-IC sound (I2S) protocol.
SPI1 and SPI4 are connected on the APB2 peripheral bridge and clocked by PCLK2 clock.
SPI2 and SPI3 are connected on the APB1 peripheral bridge and clocked by PCLK1 clock.
5.6.3
UART configuration
The SR5E1x contains three Universal asynchronous receiver transmitter (UART) modules,
supporting the local interconnection network (LIN) protocol.
Each UART receives two clock signals: a kernel clock and a register interface clock.
For all instances, the kernel clock is the UART_CLK provided by the RCC.
UART1 is connected on the APB2 peripheral bridge and its register interface is clocked by
PCLK2 clock.
UART2 and UART3 are connected on the APB1 peripheral bridge and their register
interfaces are clocked by PCLK1 clock.
5.6.4
I2C configuration
The SR5E1x contains two inter-integrated circuits (I2C).
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I2C1 and I2C2 are connected on the APB1 peripheral bridge. They receive two clocks:
•
I2CCLK the kernel clock from the RCC (configurable between PLL0, XOSC and
IRCOSC).
•
APB1 clock (PCLK1) for register access.
5.7
Reset and boot modules
5.7.1
Boot Assist Firmware (BAF) configuration
The BAF is executed out of reset by the boot core (Core1). BAF uses the following
resources.
Table 64. RAM used by the BAF
Start
End
0x2000_0000
0x2000_068F
Description
Boot CPU (Core1) DMEM: used for stack and variables
Table 65. Pins used by the BAF for serial boot mode
5.7.2
Pin name
Pad configuration
Function
PA[4]
Input, pull-up
Rx signal for CAN1, configured at start of serial boot
mode
PA[5]
Output, push-pull mode,
medium speed
Tx signal for CAN1, configured after reception of a
valid message
PF[2]
Input, pull-up
Rx signal for UART1, configured at start of serial
boot mode
PF[3]
Output, push-pull mode,
medium speed
Tx signal for UART1, configured after reception of a
valid message on UART1
System Status and Configuration Module (SSCM) configuration
This section summarizes the SSCM configuration in the device. For a comprehensive
description of the SSCM, please refer to the SSCM’s dedicated chapter.
5.7.2.1
SSCM instantiation
There is one SSCM instance in the device. The SSCM is part of the reset and boot subsystem and is clocked by the IRCOSC.
The SSCM reads the DCF records from the Flash in order to configure the reset vector for
the Boot CPU and the information to start the other CPUs.
5.7.2.2
Device-specific features
The SSCM allows Boot Assist from Flash (BAF), and utilizes PASS security concept.
Table 66 shows the address locations that the SSCM uses to search for startup information.
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Device configuration
Table 66. SSCM startup information addresses
Value
Description
0x1FF8_0000
The location at which the SSCM looks for the UTEST DCF records
0x1FF0_0000
Location of the BAF in flash
5.8
Safety modules
5.8.1
Cyclic Redundancy Check (CRC)
The device embeds one CRC module. The CRC is connected on the AHB1 bridge and
receives the AHB clock (system clock).
5.8.2
Memory Error Management Unit (MEMU2)
5.8.2.1
MEMU2 system connections
Figure 11. MEMU2 system connections
Flash memory
System RAMs
MEMU2
FCCU
Peripheral RAMs
5.8.2.2
MEMU2 error sources
Table 67 shows the MEMU error sources for each instance configured on this device.
Table 67. MEMU2 error sources
Instance
Value
Number of system RAM unique error sources
45
Number of peripheral RAM unique error sources
38
Number of flash memory unique error sources
1
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5.8.2.3
RM0483
Reporting tables implementation
There are 3 categories of error reporting for the MEMU2:
•
Flash error reporting
•
System RAMs error reporting
•
Peripheral RAM error reporting
Each category of error reporting has two tables associated with it, these are:
•
Correctable error reporting table
•
Uncorrectable error reporting table
Each entry in a reporting table corresponds to a unique error event. The number of entries
supported by each table depends upon the error source.
The table below describes the number of entries in each reporting table for the different
error sources.
Table 68. Number of entries for each MEMU reporting table
Error source
Entries in single correctable
error reporting table
Entries in double
correctable error reporting
table
Entries in uncorrectable
error reporting table
Flash
32
1
1
System RAMs
10
—
1
Peripheral RAMs
2
—
1
Table 69. Corresponding error sources for system RAM OFLW0 registers
Source number
SYS_RAM_OFLWn
bit field position (bit)
0
0
SRAM1/SRAM2
1
1
Cortex®-M7_1 Instruction Cache
2
2
Cortex®-M7_1 Data Cache
3
3
Cortex®-M7_1 ITCM
4
4
Cortex®-M7_1 DTCM
5
5
Cortex®-M7_2 Instruction Cache
6
6
Cortex®-M7_2 Data Cache
7
7
Cortex®-M7_2 ITCM
8
8
Cortex®-M7_2 DTCM
Error source
Reserved
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32
32
MBIST Cortex®-M7 Core 1 Instruction Cache
33
33
MBIST Cortex®-M7_1 Data Cache 0
34
34
MBIST Cortex®-M7_1 Data Cache 1
35
35
MBIST Cortex®-M7_1 Data Cache tag
36
36
MBIST Cortex®-M7_1 ITCM
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RM0483
Device configuration
Table 69. Corresponding error sources for system RAM OFLW0 registers (continued)
Source number
SYS_RAM_OFLWn
bit field position (bit)
37
37
MBIST Cortex®-M7_1 DTCM
38
38
MBIST Cortex®-M7 Core 2 Instruction Cache
39
39
MBIST Cortex®-M7_2 Data Cache 0
40
40
MBIST Cortex®-M7_2 Data Cache 1
41
41
MBIST Cortex®-M7_2 Data Cache tag
42
42
MBIST Cortex®-M7_2 ITCM
43
43
MBIST Cortex®-M7_2 DTCM
44
44
MBIST SRAM1/SRAM2
Error source
Table 70. Corresponding error sources for PERIPH_RAM_OFLWn registers
Source number
PERIPH_RAM_OFLWn
bit field position (bit)
0
0
CAN RAM
1
1
HSM RAM
2
2
HSM SBI Cache (Instruction Cache)
Error source
Reserved
32
32
MBIST CAN RAM
33
33
Flash RAM
34
34
HSM PRAM
35
35
HSM SBI Cache
36
36
HSM MPAES
37
37
ETF RAM
Table 71. Corresponding error sources for NVM_OFLWn registers
5.8.3
Source number
NVM_OFLWn
bit field position (bit)
Error source
0
0
NVMC1 for RWR0 - Code correctable (single)
NVMC2 for RWR1 - Code correctable (single)
Indirect memory access (IMA) configuration
The IMA refers to the alteration of memory data values during system development and test
activities. This section provides details about what memory locations can be accessed,
either via processor core access or via the IMA module, and how they are configured.
For more details, refer to Chapter 54: Indirect Memory Access (IMA).
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5.8.3.1
RM0483
Memory accessible via the IMA modules
The SRAM arrays are accessible via the IMA modules. Refer to the table below.
Table 72. Memory arrays accessible via IMA
IMA array select
Block
0
None
Words
Data bits ECC bits
IMA disabled
—
—
—
1
ICache_0
512
64
8
2
ICache_1
512
64
8
3
ICache_Tag_0
128
21
7
4
ICache_Tag_1
128
21
7
5
DCache_0_0
512
32
7
6
DCache_0_1
512
32
7
7
DCache_0_2
512
32
7
8
DCache_0_3
512
32
7
9
DCache_1_0
512
32
7
10
DCache_1_1
512
32
7
DCache_1_2
512
32
7
12
DCache_1_3
512
32
7
13
DCache_Tag0
128
24
7
14
DCache_Tag1
128
24
7
15
DCache_Tag2
128
24
7
16
DCache_Tag3
128
24
7
17
ITCM
4096
64
8
18
DTCM array A(1)
4096
32
7
19
DTCM array B(2)
4096
32
7
20
(3)
4096
32
7
(4)
4096
32
7
11
21
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Function
Core1
DTCM array C
DTCM array D
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RM0483
Device configuration
Table 72. Memory arrays accessible via IMA (continued)
IMA array select
Block
Function
Words
Data bits ECC bits
22
ICache_0
512
64
8
23
ICache_1
512
64
8
24
ICache_Tag_0
128
21
7
25
ICache_Tag_1
128
21
7
26
DCache_0_0
512
32
7
27
DCache_0_1
512
32
7
28
DCache_0_2
512
32
7
29
DCache_0_3
512
32
7
30
DCache_1_0
512
32
7
31
DCache_1_1
512
32
7
DCache_1_2
512
32
7
33
DCache_1_3
512
32
7
34
DCache_Tag0
128
24
7
35
DCache_Tag1
128
24
7
36
DCache_Tag2
128
24
7
37
DCache_Tag3
128
24
7
38
ITCM
4096
64
8
39
DTCM array A(1)
4096
32
7
40
DTCM array B(2)
4096
32
7
41
(3)
4096
32
7
(4)
DTCM array D
4096
32
7
CAN Message RAM
4096
32
7
32
Core2
DTCM array C
42
43
CAN
1. Gives the access to the first 32-bit word of the first 32 kilobytes block, that is offset 0x0 - 0x8 - 0x10, and so
on.
2. Gives the access to the first 32-bit word of the last 32 kilobytes block, that is offset 0x8000 - 0x8008 0x8010, and so on.
3. Gives the access to the second 32-bit word of the first 32 kilobytes block, that is offset 0x4 - 0xC - 0x14,
and so on.
4. Gives the access to the second 32-bit word of the last 32 kilobytes block, that is offset 0x8004 - 0x800C 0x8014, and so on.
5.8.4
Fault Collection & Control Unit (FCCU) configuration
5.8.4.1
Available FCCU output signals
The following table shows the available FCCU output signals implemented on this chip.
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Table 73. FCCU input, output signals
5.8.4.1.1
FCCU signal name
Description
Device signal name
EOUT[0], FI[0],
ERROR0 F0
bidirectional signal, can be configured as output only
EOUT0
EOUT0
(PA9)
EOUT[1], FI[1],
ERROR1 F1
bidirectional signal, can be configured as output only
EOUT1
EOUT1
(PA10)
EIN[0]
Unidirectional input error signal
EIN0
(PD9)
EIN[1]
Unidirectional input error signal
EIN1
(PH13)
External error indication
Failure of the MCU is signaled to one or two pins, FCCU_ERR0 (PA[9]) and FCCU_ERR1
(PA[10]). External failure to MCU is signaled from FCCU_EIN0 (PA[9] or PD[9]) or
FCCU_EIN1 (PA[10] or PH[13]) (refer to “Fault collection and control unit (FCCU)” chapter,
and “FCCU configuration” section of the “Device configuration” chapter, for details on the
fault output signals). PA[9] and PA[10] pins are dedicated to FCCU while the pins PD[9] and
PH[13] can be multiplexed with other functions with different values.
The error indication on pins FCCU_ERR0 (PA[9]) and FCCU_ERR1 (PA[10]) is controlled
by GPIO port and FCCU. The mapping of the FCCU output signals on the relevant pins and
the associated electrical characteristics are enabled by the GPIO port registers (refer to
Chapter 20: General-purpose I/Os (GPIO) for signal mapping details). Once the FCCU is
mapped onto the pin, the logic level is driven by the FCCU.
The input function FCCU_EIN0 on PA[9] is configured at startup by default. The other FCCU
pins are floating at startup (see the IO_Archi for the default configuration of these pins).
Since it is possible to reset FCCU and GPIO port independently, the behavior of FCCU pins
is the result of the combined state of GPIO port registers and the FCCU. (refer to section
“Reset interface” in chapter “Fault collection and control unit (FCCU)” for FCCU reset
details, and chapter “Reset and Boot” for the state of the FCCU relative to the system during
different reset phases).
During functional reset, the application only considers the PAD PA[9] as FCCU error pin.
The other FCCU pins are not enabled during functional reset.
The FCCU_STAT[ESTAT] error status flag can be read to show whether the FCCU is in an
error state. This flag is written by software to either a 1 (fault) or 0 (operational) when the
FCCU is in operational state.
FCCU_EINOUT(EINO): the value of this register depends on the state of the pad. If the
input buffer is enabled, the register bit reflects the physical status of the pin as seen by the
input buffer. In case the protocol selected for EOUT interface is a toggling one (Dual rail or
Time switching), this may not be true due to synchronization in the safety clock domain.
The register reflects the physical status of the pin from application point of view (external
status).
FCCU_STAT(PhysicalErrorPin): this register field indicates the actual status of the Error pin
as driven by FCCU to the pad based on different FCCU configurations and state of the
failure input channels. The value reported in the FCCU_STAT (PhysicalErrorPin) can be
different from what is seen at the pad.
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5.8.4.1.2
Device configuration
Failure handling
The FCCU is an autonomous module that is responsible for reacting to failure indicators. A
different reaction can be configured for each failure source. Overall failure reaction time
requires time for detecting, processing, and indicating the error. During this time, SR5E1x
can provide wrong results to the system.
Failure sources include:
•
All failure indication signals from modules within the MCU.
•
Control logic and signals monitored by the FCCU itself (refer to chapter “Fault
collection and control unit (FCCU)”).
•
Software-initiated failure indications. For example, software signals the FCCU that it
has evidence of a failure. Keep in mind that software can also directly influence the
state of the FCCU pins.
•
External failure input.
Available failure reactions are:
•
Assertion of an interrupt (maskable or non-maskable)
•
Resetting the MCU
•
Changing the state of the failure indication pins
•
Disabling the transmission capabilities of communication controllers (CAN). Note that,
it is only possible in conjunction with changing the state of the failure indication pins
•
No reaction
Software can read the failure source that caused a fault, either before or after a functional
reset (the condition indicators are not volatile). Software can also reset the failure, but the
external failure indication stays in failure mode for a configurable minimum time. If
necessary, software can also reset the MCU.
5.8.4.2
FCCU registers reset values
The following table shows the reset values of selected FCCU registers, where the reset
value is not fully defined in the Fault collection and control unit (FCCU) chapter.
Table 74. Reset values of selected FCCU registers
Register
Reset value
FCCU_CTRL
0x000000C0
FCCU_RF_CFG0
0xFFEBFFFF
FCCU_RF_CFG1
0xFEFFF7FF
FCCU_RF_CFG2
0x0003FFFF
FCCU_RF_CFG3
0x00000000
FCCU_RFS_CFG0
0x00020800
FCCU_RFS_CFG1
0x00000000
FCCU_RFS_CFG2
0x00000000
FCCU_RFS_CFG3
0x00000000
FCCU_RFS_CFG4
0x00000000
FCCU_RFS_CFG5
0x00000000
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Table 74. Reset values of selected FCCU registers (continued)
Register
Reset value
FCCU_RFS_CFG6
0x00000000
FCCU_RFS_CFG7
0x00000000
FCCU_RF_S0..S2
0x00000000
FCCU_RF_E0
0x00000120
FCCU_RF_E1..E2
0x00000000
FCCU_RF_TOE0 .. TOE2
0x00000000
FCCU_EINOUT
0x00000030(1)
1. EIN pads are pulled up in testbench.
5.8.4.2.1
FCCU failure inputs from other modules
The following table shows the different failure input signals of the FCCU and how they can
be tested. Refer to Table 74 for the default configuration after reset.
Failure Description
Error Injection check
TEMP_ERROR
Temperature
detector
FCCU Fake Fault
Injection.
1
2
—
—
—
—
—
Pulse signal. No
SW intervention
needed to clear it.
LVD_ERROR
Voltage out of
range from
LVDs (nondestructive
reset)
FCCU Fake Fault
Injection.
—
Pulse signal. No
SW intervention
needed to clear it.
HVD_ERROR
Voltage out of
range from
LVDs (nondestructive
reset)
FCCU Fake Fault
Injection.
—
Pulse signal. No
SW intervention
needed to clear it.
FCCU Fake Fault
Injection.
—
Persistent Till Error
Negation. The
recommended clear
mechanism is
device reset.
Error Injection done
inside the PMC.
—
Pulse signal. No
SW intervention
needed to clear it.
3
—
—
DPMC_DCF_SAFETY_ERR
Digital PMC
DCF Safety
Error
4
—
—
DPMC_VD_BIST
Digital PMC
Voltage
detector BIST
138/2075
Clear mechanism
Failure
—
in the Fault Source
CEM reg bit
—
Reference Manual
CEM instance
0
related information
FCCU Channel
Table 75. FCCU failure inputs
RM0483 Rev 5
RM0483
Device configuration
6
—
—
FCCU Fake Fault
Injection.
Clear mechanism
in the Fault Source
Reference Manual
related information
FLASH_FATAL_ERR
Flash memory
initialization
error
Error Injection check
CEM reg bit
—
Failure Description
—
Failure
5
CEM instance
FCCU Channel
Table 75. FCCU failure inputs (continued)
—
Persistent Till Error
Negation. The
recommended clear
mechanism is
device reset.
—
Persistent Till Error
Negation. The
recommended clear
mechanism is
device reset.
Flash Reset Error
The pin/flag
signals the
following
unrecoverable
errors:
– ECC errors
on flash
internal
reads
during
configuratio
n loading
(startup)
– ECC errors
FCCU Fake Fault
on flash
Injection.
internal
reads
during fw
copy
(startup)
– Double
ECC errors
on KRAM
during
internal selfcheck
routine
(always
running)
FCCU Fake Fault
Injection.
—
Persistent Till Error
Negation. The
recommended clear
mechanism is
device reset.
7
—
—
FLASH_REF_ERR
FLASH read
reference
error
8
—
—
IWDG1_ResetReq
Independent
WDG1 Reset
Request
FCCU Fake Fault
Injection.
—
Pulse signal. No
SW intervention
needed to clear it.
9
—
—
IWDG2_ResetReq
Independent
WDG2 Reset
Request
FCCU Fake Fault
Injection.
—
Pulse signal. No
SW intervention
needed to clear it.
WWDG1_ResetReq
Window
watchdog1
Reset
Request
FCCU Fake Fault
Injection.
—
Pulse signal. No
SW intervention
needed to clear it.
10
—
—
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RM0483
11
12
—
—
—
—
WWDG2_ResetReq
FM_PLL_0
Clear mechanism
in the Fault Source
Reference Manual
related information
Error Injection check
Failure Description
Failure
CEM reg bit
CEM instance
FCCU Channel
Table 75. FCCU failure inputs (continued)
Window
watchdog2
Reset
Request
FCCU Fake Fault
Injection.
—
Pulse signal. No
SW intervention
needed to clear it.
PLL0 Loss of
Lock
(Interrupt)
Error injection
mechanism
available or
programming the
PLL dividers inside
RCC.
—
Clear status in
PLLDIG
—
Clear status in
PLLDIG
13
—
—
FM_PLL_1
PLL1 Loss of
Lock
(Interrupt)
Error injection
mechanism
available or
programming the
PLL dividers inside
RCC.
14
—
—
CMU_0_OSC
XOSC less
than IRC
Error injection
mechanism
available
—
Clear status in
CMU
15
—
—
CMU_0_PLL0
PLL0 out of
frequency
Error injection
mechanism
available
—
Clear status in
CMU
Error injection
mechanism
available
—
Clear status in
CMU
Error injection
mechanism
available
—
Clear status in
CMU
—
—
—
Pulse signal. No
SW intervention
needed to clear it.
16
—
—
CMU_Platform
Sysclk
frequency out
of range
(including
HRTIM clock)
17
—
—
CMU_other
Monitoring
other internal
clocks
18
—
—
—
—
—
19
—
—
STCU_RF
Bist result wrong
signature
(STCU
Recoverable
Fault)
20
—
—
—
—
—
—
—
21
—
—
SYS_RAM_TRIG_0
—
Error injection done
inside the MEMU
—
Pulse signal. No
SW intervention
needed to clear it.
22
—
—
SYS_RAM_TRIG_1
—
Error injection done
inside the MEMU
—
Pulse signal. No
SW intervention
needed to clear it.
140/2075
FCCU Fake Fault
Injection.
RM0483 Rev 5
RM0483
Device configuration
Failure Description
Error Injection check
SYS_RAM_TRIG_2
—
Error injection done
inside the MEMU
—
Pulse signal. No
SW intervention
needed to clear it.
24
—
—
SYS_RAM_TRIG_3
—
Error injection done
inside the MEMU
—
Pulse signal. No
SW intervention
needed to clear it.
25
—
—
PERIPH_RAM_TRIG_0
—
Error injection done
inside the MEMU
—
Pulse signal. No
SW intervention
needed to clear it.
26
—
—
PERIPH_RAM_TRIG_1
—
Error injection done
inside the MEMU
—
Pulse signal. No
SW intervention
needed to clear it.
27
—
—
PERIPH_RAM_TRIG_2
—
Error injection done
inside the MEMU
—
Pulse signal. No
SW intervention
needed to clear it.
28
—
—
PERIPH_RAM_TRIG_3
—
Error injection done
inside the MEMU
—
Pulse signal. No
SW intervention
needed to clear it.
29
—
—
NVM_TRIG_0
—
Error injection done
inside the MEMU
—
Pulse signal. No
SW intervention
needed to clear it.
30
—
—
NVM_TRIG_1
—
Error injection done
inside the MEMU
—
Pulse signal. No
SW intervention
needed to clear it.
31
—
—
NVM_TRIG_2
—
Error injection done
inside the MEMU
—
Pulse signal. No
SW intervention
needed to clear it.
32
—
—
NVM_TRIG_3
—
Error injection done
inside the MEMU
—
Pulse signal. No
SW intervention
needed to clear it.
RM0483 Rev 5
Clear mechanism
Failure
—
in the Fault Source
CEM reg bit
—
Reference Manual
CEM instance
23
related information
FCCU Channel
Table 75. FCCU failure inputs (continued)
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MEMU2_SYS_RAM_UC_OVF
2
Periph RAM
MEMU2_PERIPH_RAM_SB_O Single Bit
Error Table
VF
overflow
3
Periph
MEMU2_PERIPH_RAM_UC_O Uncorrectable
Error Table
VF
overflow
MEMU2_NVM_SB_OVF
NVM Single
Bit Error Table
overflow
5
MEMU2_NVM_UC_OVF
NVM
Uncorrectable
Error Table
overflow
6
MEMU2_NVM_DBL_OVF
NVM Double
correctable
Table overflow
4
142/2075
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in the Fault Source
—
Clear status in
MEMU. SW can
write '0' on the Valid
bit of any entry of
the table, and the
MEMU full
indication is
cleared.
Reference Manual
Error Injection check
Error injection done
inside the MEMU
Clear mechanism
1
Sys RAM
Uncorrectable
Error Table
overflow
related information
CEM_
10
Failure Description
MEMU2_SYS_RAM_SB_OVF
Sys RAM
Single Bit
Error Table
overflow
0
33
Failure
CEM reg bit
CEM instance
FCCU Channel
Table 75. FCCU failure inputs (continued)
RM0483
Device configuration
SYS_RAM_OVRFLOW_FIF0_2
3
SYS_RAM_OVRFLOW_FIF0_3
4
SYS_RAM_OVRFLOW_FIF0_4
5
SYS_RAM_OVRFLOW_FIF0_5
6
SYS_RAM_OVRFLOW_FIF0_6
7
SYS_RAM_OVRFLOW_FIF0_7
8
SYS_RAM_OVRFLOW_FIF0_8
9
SYS_RAM_OVRFLOW_FIF0_3
2
10
SYS_RAM_OVRFLOW_FIF0_3
3
11
SYS_RAM_OVRFLOW_FIF0_3
4
12
SYS_RAM_OVRFLOW_FIF0_3
5
13
SYS_RAM_OVRFLOW_FIF0_3
6
14
SYS_RAM_OVRFLOW_FIF0_3
7
15
SYS_RAM_OVRFLOW_FIF0_3
8
16
SYS_RAM_OVRFLOW_FIF0_3
9
17
SYS_RAM_OVRFLOW_FIF0_4
0
18
SYS_RAM_OVRFLOW_FIF0_4
1
19
SYS_RAM_OVRFLOW_FIF0_4
2
20
SYS_RAM_OVRFLOW_FIF0_4
3
21
SYS_RAM_OVRFLOW_FIF0_4
4
—
Error Injection done
inside the CEM.
RM0483 Rev 5
—
Clear mechanism
2
in the Fault Source
SYS_RAM_OVRFLOW_FIF0_1
Reference Manual
1
related information
SYS_RAM_OVRFLOW_FIF0_0
Error Injection check
0
Failure Description
Failure
CEM_
11
CEM reg bit
34
CEM instance
FCCU Channel
Table 75. FCCU failure inputs (continued)
Persistent till error
negation.
143/2075
162
Device configuration
RM0483
FCCU Fake Fault
Injection.
—
Persistent till error
negation.
Error Injection done
inside the CEM.
—
Persistent Till Error
Negation. The
recommended clear
mechanism is
device reset.
FCCU Fake Fault
Injection.
—
Persistent till error
negation from HW
FCCU Fake Fault
Injection.
—
Persistent Till Error
Negation
PERIPH_RAM_OVRFLOW_FI
F0_1
2
PERIPH_RAM_OVRFLOW_FI
F0_2
3
PERIPH_RAM_OVRFLOW_FI
F0_32
4
PERIPH_RAM_OVRFLOW_FI
F0_33
5
PERIPH_RAM_OVRFLOW_FI
F0_34
6
PERIPH_RAM_OVRFLOW_FI
F0_35
7
PERIPH_RAM_OVRFLOW_FI
F0_36
8
PERIPH_RAM_OVRFLOW_FI
F0_37
—
FLASH_OVRFLOW_FIFO_0
0
SSCM_XFER_ERR
SSCM transfer
error
1
MEMORY REPAIR DCF
SAFETY ERROR
Memory
Repair Safety
Error
2
TDM_DCF_SAFETY_ERR
TDM DCF
Safety Error
RCC_DCF_SAFETY_ERR
RCC DCFs +
Security
Miscellaneous
DCF
3
38
—
—
ERRIN1
Error from
unidirectional
input error
signal
(external
failure to
MCU)
39
—
—
IMA SoC
IMA SoC
Active
144/2075
RM0483 Rev 5
Clear mechanism
Persistent till error
negation.
1
in the Fault Source
—
PERIPH_RAM_OVRFLOW_FI
F0_0
Reference Manual
Error Injection done
inside the CEM.
0
related information
Error Injection check
CEM_
9
Failure Description
37
—
—
Failure
36
CEM_
12
CEM reg bit
35
CEM instance
FCCU Channel
Table 75. FCCU failure inputs (continued)
RM0483
Device configuration
41
CEM_
13
0
Unexpected
SPURIOUS_DEBUG_ACTIVAT activation of
JTAG or
ION
debug signals
1
SPURIOUS_SSCM_ACTIVATI
ON
Unexpected
activation of
SSCM CS to
DCF clients
during run
time
2
SPURIOUS STCU3
ACTIVATION
Unexpected
activation of
STCU3 during
run time
Test circuitry
Group
spurious
activation
—
42
—
—
SPURIOUS DFT signals
ACTIVATION
43
—
—
—
44
45
46
—
—
—
—
Compensation Disable
Error injection
mechanism
available
—
Clear mechanism
in the Fault Source
Reference Manual
related information
SAFE_SWITCH_TO_HSI
Transition to
RCOSC in
case of critical
faults on clock
sources
Error Injection check
CEM reg bit
—
Failure Description
—
Failure
40
CEM instance
FCCU Channel
Table 75. FCCU failure inputs (continued)
Clear status in
RCC.
—
Error injection done
inside the CEM.
—
Pulse signal. No
SW intervention
needed to clear it.
—
—
Persistent Till Error
Negation.
—
—
Indication of
undesired
deactivation of
pad
compensation.
FCCU Fake Fault
Fault can
Injection.
affect a
distorted
transmissions
on I/Os
associated.(1)
—
Persistent till error
negation from HW.
FCCU Fake Fault
Injection.
—
Persistent till error
negation from HW.
FCCU Fake Fault
Injection.
—
Persistent Till Error
Negation. No SW
intervention needed
to clear it.
—
ERRIN0
Error from
bidirectional
input error
signal
(external or
internal failure
to MCU)
—
Core lock/split change state
alarm
Edge detector
after dcf
loading
FCCU Fake Fault
Injection.
—
RM0483 Rev 5
145/2075
162
Device configuration
RM0483
Clear mechanism
FCCU Fake Fault
Injection.
in the Fault Source
Error Injection check
Edge detector
after dcf
loading
Reference Manual
Failure Description
—
Dma lock/split change state
alarm
related information
Failure
—
CEM reg bit
47
CEM instance
FCCU Channel
Table 75. FCCU failure inputs (continued)
—
Persistent Till Error
Negation. No SW
intervention needed
to clear it.
2 errors:
– Boot: no injection
available,
– NVMC1/2: Fault
Injection inside
NVMC through
internal registers.
—
Persistent Till Error
Negation. No SW
intervention needed
to clear it.
48
—
—
OTA change state alarm
Edge detector
after dcf
loading
49
—
—
SMPU region
MPU region
violation
Error Injection done
inside the SMPU.
—
Pulse signal. No
SW intervention
needed to clear it.
SMPU protocol
The SMPU
monitors that
the SMPU
logic does not
alter any
signal by
comparing in
versus out
signals.
FCCU Fake Fault
Injection.
—
Pulse signal. No
SW intervention
needed to clear it.
EDC_ECC_Code
EDC after
ECC for code
NVMC1.
Error injection done
inside the NVMC1
through internal
registers.
—
Pulse signal. Clear
status in NVMC1.
EDC_ECC_Data
EDC after
ECC for data
NVMC1.
Error injection done
inside the NVMC1
through internal
registers.
—
Pulse signal. Clear
status in NVMC1.
ENC_ERR_FLASH
Flash
Encoding
Error –
Indication of
hardware fault
resulting in
corrupted
flash memory
access.
Error injection done
inside the NVMC1
through internal
registers.
—
Pulse signal. Clear
status in NVMC1.
50
51
52
53
—
—
—
—
146/2075
—
—
—
—
RM0483 Rev 5
RM0483
Device configuration
54
—
Clear mechanism
in the Fault Source
Reference Manual
related information
Error Injection check
Failure Description
Failure
CEM reg bit
CEM instance
FCCU Channel
Table 75. FCCU failure inputs (continued)
—
PFlashC
Address
Feedback
Error - alarm
indicating the
flash controller
detected a
ADDR_FDBK_ERR_FLASH_C transaction
monitor
TL
mismatch
when
compared to
the flash
safety
feedback
outputs.
Error injection done
inside the NVMC1
through internal
registers.
—
Pulse signal. Clear
status in NVMC1.
Error injection done
inside the NVMC2
through internal
registers.
—
Pulse signal. Clear
status in NVMC2.
55
—
—
EDC_ECC_Code
EDC after
ECC for Code
NVMC2
56
—
—
—
—
—
—
—
ENC_ERR_FLASH
Flash
Encoding
Error –
Indication of
hardware fault
resulting in
corrupted
flash memory
access.
Error injection done
inside the NVMC2
through internal
registers.
—
Pulse signal. Clear
status in NVMC2.
ADDR_FDBK_ERR_FLASH
_CTL
PFlashC
Address
Feedback
Error - alarm
indicating the
flash controller
detected a
transaction
monitor
mismatch
when
compared to
the flash
safety
feedback
outputs
Error injection done
inside the NVMC2
through internal
registers.
—
Pulse signal. Clear
status in NVMC2.
57
58
—
—
—
—
RM0483 Rev 5
147/2075
162
Device configuration
RM0483
Pulse signal. No
SW intervention
needed to clear it.
e2eECC NVMPC2 Protocol
Error
Can be
implemented
in flash ctl
OR of the
protocol error
on the 2 ports
of NVMC2
FCCU Fake Fault
Injection.
—
Pulse signal. No
SW intervention
needed to clear it.
EDC after
SRAMC1 EDC after ECC Error ECC FCCU
Alarm
FCCU Fake Fault
Injection.
—
Pulse signal. No
SW intervention
needed to clear it.
FCCU RAM
alarm
FCCU Fake Fault
Injection.
—
Pulse signal. No
SW intervention
needed to clear it.
Address/Contr
ol EDC/Parity FCCU Fake Fault
Injection.
check FCCU
Alarm
—
Pulse signal. No
SW intervention
needed to clear it.
Clear mechanism
—
in the Fault Source
FCCU Fake Fault
Injection.
Reference Manual
e2eECC NVMPC1 Protocol
Error
Can be
implemented
in flash ctl
OR of the
protocol error
on the 2 ports
of NVMC1
related information
Error Injection check
CEM reg bit
—
Failure Description
—
Failure
59
CEM instance
FCCU Channel
Table 75. FCCU failure inputs (continued)
60
—
—
61
—
—
62
—
—
FCCU RAM alarm
63
—
—
Address/Control EDC/Parity
check FCCU Alarm
64
—
—
EDC after
SRAMC2 EDC after ECC Error ECC FCCU
Alarm
FCCU Fake Fault
Injection.
—
Pulse signal. No
SW intervention
needed to clear it.
65
—
—
FCCU RAM alarm
FCCU RAM
alarm
FCCU Fake Fault
Injection.
—
Pulse signal. No
SW intervention
needed to clear it.
—
Address/Control EDC/Parity
check FCCU Alarm
Address/Contr
ol EDC/Parity FCCU Fake Fault
Injection.
check FCCU
Alarm
—
Pulse signal. No
SW intervention
needed to clear it.
66
—
148/2075
RM0483 Rev 5
RM0483
Device configuration
e2eECC Data Correctable Error
Core2 AXIM
3
e2eECC Data Correctable Error
Core2 AHBM
4
e2eECC Data Correctable Error
HSM AHB
5
e2eECC Data Correctable Error
DMA1 AHB Memory
6
e2eECC Data Correctable Error
DMA1 AHB Peripheral
7
e2eECC Data Correctable Error
DMA2 AHB Memory
8
e2eECC Data Correctable Error
DMA2 AHB Peripheral
0
e2eECC Data Uncorrectable
Error Core1 AXIM
1
e2eECC Data Uncorrectable
Error Core1 AHBM
2
e2eECC Data Uncorrectable
Error Core2 AXIM
3
e2eECC Data Uncorrectable
Error Core2 AHBM
4
e2eECC Data Uncorrectable
Error HSM AHB
5
e2eECC Data Uncorrectable
Error DMA1 AHB Memory
6
e2eECC Data Uncorrectable
Error DMA1 AHB Peripheral
7
e2eECC Data Uncorrectable
Error DMA2 AHB Memory
8
e2eECC Data Uncorrectable
Error DMA2 AHB Peripheral
—
Error Injection done
inside the CEM.
—
Pulse signal. No
SW intervention
needed to clear it.
—
Error Injection done
inside the CEM.
—
Pulse signal. No
SW intervention
needed to clear it.
RM0483 Rev 5
Clear mechanism
2
in the Fault Source
e2eECC Data Correctable Error
Core1 AHBM
Reference Manual
1
related information
e2eECC Data Correctable Error
Core1 AXIM
Error Injection check
0
Failure Description
CEM_
1
Failure
68
CEM_
0
CEM reg bit
67
CEM instance
FCCU Channel
Table 75. FCCU failure inputs (continued)
149/2075
162
Device configuration
RM0483
150/2075
e2eECC Protocol Error Core2
AXIM
3
e2eECC Protocol Error Core2
AHBM
4
e2eECC Protocol Error HSM
AHB
5
e2eECC Protocol Error DMA1
AHB Memory
6
e2eECC Protocol Error DMA1
AHB Peripheral
7
e2eECC Protocol Error DMA2
AHB Memory
8
e2eECC Protocol Error DMA2
AHB Peripheral
—
AXI watchdog
0
e2eECC Data Correctable Error
Cores AHBP
1
e2eECC Data Correctable Error
AHB1
2
e2eECC Data Correctable Error
AHB2
3
e2eECC Data Correctable Error
APB1
4
e2eECC Data Correctable Error
APB2
5
e2eECC Data Correctable Error
HRTIM1 AXI
6
e2eECC Data Correctable Error
HRTIM2 AXI
—
Error Injection done
inside the CEM.
—
Pulse signal. No
SW intervention
needed to clear it.
—
No Injection
Mechanism
Available.
—
Pulse signal. No
SW intervention
needed to clear it.
—
Error Injection done
inside the CEM.
—
Pulse signal. No
SW intervention
needed to clear it.
RM0483 Rev 5
Clear mechanism
2
in the Fault Source
e2eECC Protocol Error Core1
AHBM
Reference Manual
1
related information
e2eECC Protocol Error Core1
AXIM
Error Injection check
CEM_
3
0
Failure Description
71
—
Failure
70
CEM_
2
CEM reg bit
69
CEM instance
FCCU Channel
Table 75. FCCU failure inputs (continued)
RM0483
Device configuration
76
—
—
e2eECC Data Uncorrectable
Error AHB2
3
e2eECC Data Uncorrectable
Error APB1
4
e2eECC Data Uncorrectable
Error APB2
5
e2eECC Data Uncorrectable
Error HRTIM1 AXI
6
e2eECC Data Uncorrectable
Error HRTIM2 AXI
0
e2eECC Protocol Error Cores
AHBP
1
e2eECC Protocol Error AHB1
2
e2eECC Protocol Error AHB2
3
e2eECC Protocol Error APB1
4
e2eECC Protocol Error APB2
5
e2eECC Protocol Error HRTIM1
AXI
6
e2eECC Protocol Error HRTIM2
AXI
0
Protection violation AHB1
1
Protection violation AHB2
2
Protection violation APB1
3
Protection violation APB2
—
—
—
Error Injection done
inside the CEM.
—
Pulse signal. No
SW intervention
needed to clear it.
—
Error Injection done
inside the CEM.
—
Pulse signal. No
SW intervention
needed to clear it.
—
Error Injection done
inside the CEM.
—
Pulse signal. No
SW intervention
needed to clear it.
—
Persistent till error
negation. No SW
intervention needed
to clear it.
—
Persistent till error
negation. No SW
intervention needed
to clear it.
RCCU_CORE_alarm
RCCUS for
Cores
lockstep
FCCU Fake Fault
Injection.
RCCU_DMA_alarm
RCCUS for
DMA lockstep
FCCU Fake Fault
Injection.
RM0483 Rev 5
Clear mechanism
2
in the Fault Source
e2eECC Data Uncorrectable
Error AHB1
Reference Manual
1
related information
e2eECC Data Uncorrectable
Error Cores AHBP
Error Injection check
75
CEM_
6
0
Failure Description
74
CEM_
5
Failure
73
CEM_
4
CEM reg bit
72
CEM instance
FCCU Channel
Table 75. FCCU failure inputs (continued)
151/2075
162
Device configuration
RM0483
APB1_Bridge_Alarm
3
APB2_Bridge_Alarm
4
AHBS_Bridge_Alarm
5
HRTIM1_Bridge_Alarm
6
HRTIM2_Bridge_Alarm
7
NVMC1_Bridge_Alarm
8
NVMC2_Bridge_Alarm
9
RAMC1_Bridge_Alarm
10
RAMC2_Bridge_Alarm
from RCCUSs
for Slaves
Dataless
Duplication
lockstep
Error Injection done
inside the CEM.
—
Persistent till error
negation. No SW
intervention needed
to clear it.
Clear mechanism
2
in the Fault Source
AHB2_Bridge_Alarm
Reference Manual
1
related information
AHB1_Bridge_Alarm
Error Injection check
0
Failure Description
Failure
CEM_
77
7
CEM reg bit
CEM instance
FCCU Channel
Table 75. FCCU failure inputs (continued)
78
—
—
CORE1_LOCKUP
—
FCCU Fake Fault
Injection.
—
Persistent till next
reset.
79
—
—
CORE2_LOCKUP
—
FCCU Fake Fault
Injection.
—
Persistent till next
reset.
0
I-TCM Core1 Address feedback
Err
1
D0-TCM Core1 Address
feedback Err
2
D1-TCM Core1 Address
feedback Err
3
I-TCM Core1 EDC after ECC
4
D0-TCM Core1 EDC after ECC
5
D1-TCM Core1 EDC after ECC
Error Injection done
inside the CEM.
—
6
I-TCM Core2 Address feedback
Err
—
Pulse signal. No
SW intervention
needed to clear it.
7
D0-TCM Core2 Address
feedback Err
8
D1-TCM Core2 Address
feedback Err
9
I-TCM Core2 EDC after ECC
10
D0-TCM Core2 EDC after ECC
11
D1-TCM Core2 EDC after ECC
80
CEM_
8
152/2075
RM0483 Rev 5
RM0483
Device configuration
Upsizer error - HSM
3
Upsizer error - DMA1 AHBP
4
Upsizer error - DMA1 AHBM
5
Upsizer error - DMA2 AHBP
6
Upsizer error - DMA2 AHBM
Fault triggered
Decode error
Error Injection done
response is
inside the CEM.
seen on the
bus.
—
Clear mechanism
2
in the Fault Source
Upsizer error - Core2 AHB
Reference Manual
1
related information
Upsizer error - Core1 AHB
Error Injection check
0
Failure Description
Failure
CEM_
14
CEM reg bit
81
CEM instance
FCCU Channel
Table 75. FCCU failure inputs (continued)
Pulse signal. No
SW intervention
needed to clear it.
1. Compensation cell reduces the spread of some circuit parameters (slew rate of the output signal and the output
impedance) in the IO buffers over temperature, process and voltage. Compensation cell can remain disabled until supplies
have reached LVD290 threshold.
5.8.5
CEM Configuration
The SR5E1x contains 15 CEM instances (CEM0 to CEM14). Each instance has only one
group (Group0).
5.8.6
REG_PROT configuration
The AHB and APB bridges include a hardware mechanism to protect module registers from
unwanted modifications.
The protection is applied at the level of the memory slots in the AHB and APB bridges. The
memory space reserved for each slot is 1 KB, that in most cases corresponds with the
memory space reserved for an IP module. Inside each IP slot, registers are protected with
32-bit granularity.
The protection mechanism works like a firewall for write operations, basing on the lock
status of the register. For this reason, the Register Protection feature is also referred to as
Register Hardware Lock.
In order to write in a protected register, the software has to first unlock it by writing a
password equal to the register address.
The modification of a protected register consists of a two-step write operation, as shown in
Figure 12:
•
The first write (WRITE1) has to be performed on the register, providing as data the
address of the register. This unlocks the register for write.
•
The second write (WRITE2) is the effective write to the register with the desired data.
RM0483 Rev 5
153/2075
162
Device configuration
RM0483
Figure 12. Register hardware lock for writes
LOCKED
Register Locked for Write
WRITE1
WDATA == REG_ADDR
UNLOCKED
Register Unlocked for Write
WRITE2
WDATA == REG_DATA
Note:
If a register is unlocked by bus master1 and another master (that is master2) tries to write in
it, master2 gets an error response.
The protected registers for each IP have been selected at design time. The list of protected
register in each module is shown from Table 76: Protected GPIOx registers to Table 85:
MBIST partitions.
The register protection mechanism is not enabled by default. An enable bit for each AHB
and APB bridge is present in REG_HWLOCK_DCF (see REG_HWLOCK_DCF).
5.8.6.1
GPIOx protected registers
The following table lists the GPIOx, x=A..I, registers that can be protected.
154/2075
RM0483 Rev 5
RM0483
Device configuration
Table 76. Protected GPIOx registers
5.8.6.2
Register
Register size
(bits)
Offset from module base
address
MODER
—
0x00000000
OTYPER
—
0x00000004
OSPEEDR
—
0x00000008
PUPDR
—
0x0000000C
AFRL
—
0x00000020
AFRH
—
0x00000024
RCC protected registers
The following table lists the Reset & Clock Control (RCC) protected registers.
Table 77. Protected RCC registers
Register
Register size
(bits)
Offset from module base
address
RCC_CR
—
0x00000000
RCC_ICSR
—
0x00000004
RCC_CFGR
—
0x00000008
RCC_PLLCFGR
—
0x0000000C
RCC_CIER
—
0x00000018
RCC_CIFR
—
0x0000001C
RCC_CICR
—
0x00000020
RCC_CCIPR1
—
0x00000024
RCC_CCIPR2
—
0x00000028
RCC_LSCFGR
—
0x0000002C
RCC_CRRCR
—
0x00000030
RCC_AHB1LRSTR
—
0x00000050
RCC_AHB1HRSTR
—
0x00000054
RCC_AHB2LRSTR
—
0x00000058
RCC_AHB2HRSTR
—
0x0000005C
RCC_APB1LRSTR
—
0x00000060
RCC_APB2LRSTR
—
0x00000068
RCC_APB2HRSTR
—
0x0000006C
RCC_AHB1LENR
—
0x00000070
RCC_AHB1HENR
—
0x00000074
RCC_AHB2LENR
—
0x00000078
RCC_AHB2HENR
—
0x0000007C
RM0483 Rev 5
155/2075
162
Device configuration
RM0483
Table 77. Protected RCC registers (continued)
Register
Register size
(bits)
Offset from module base
address
RCC_APB1LENR
—
0x00000080
RCC_APB2LENR
—
0x00000088
RCC_APB2HENR
—
0x0000008C
RCC_AHB1LSMENR
—
0x00000090
RCC_AHB1HSMENR
—
0x00000094
RCC_AHB2LSMENR
—
0x00000098
RCC_AHB2HSMENR
—
0x0000009C
RCC_APB1LSMENR
—
0x000000A0
RCC_APB2LSMENR
—
0x000000A8
RCC_APB2HSMENR
—
0x000000AC
The following table lists the Clock Monitoring Units (CMU) protected registers.
Table 78. Protected CMUx, x= 0..1, registers
Register
Register size
(bits)
Offset from module base
address
CSR
—
0x00000000
HFREFR
—
0x00000008
LFREFR
—
0x0000000C
ISR
—
0x00000010
The following table lists the Power Management Controller (PMC) protected registers.
Table 79. Protected PMC registers
156/2075
Register
Register size
(bits)
Offset from module base
address
REE_LV0
—
0x00000004
RES_LV0
—
0x00000008
FEE_LV0
—
0x00000010
REE_LV1
—
0x00000024
RES_LV1
—
0x00000028
FEE_LV1
—
0x00000030
REE_HV0
—
0x00000044
RES_HV0
—
0x00000048
FEE_HV0
—
0x00000050
VSIO
—
0x00000104
RM0483 Rev 5
RM0483
Device configuration
Table 79. Protected PMC registers (continued)
Register
Register size
(bits)
Offset from module base
address
MISC_CTRL_REG
—
0x00000248
REE_TD
—
0x00000304
RES_TD
—
0x00000308
CTL_TD
—
0x0000030C
FEE_TD
—
0x00000318
BIST_CTRL
—
0x000003D4
The following table lists the (MEMU) protected registers.
Table 80. Protected MEMU registers
Register
Register size
(bits)
Offset from module base
address
MEMU_CTRL
—
0x00000000
The following table lists the Indirect Memory Adressing (IMA) protected registers.
Table 81. Protected IMA registers
Register
Register size
(bits)
Offset from module base
address
IMA_ENABLE
—
0x00000004
The following table lists the System Control (SYSCTRL) protected registers.
Table 82. Protected SYSCTRL registers
Register
Register size
(bits)
Offset from module base
address
EXTICR_3_0
—
0x00000008
EXTICR_7_4
—
0x0000000C
EXTICR_11_8
—
0x00000010
EXTICR_15_12
—
0x00000014
The following table lists the PLL protected registers.
Table 83. Protected PLL registers
Register
Register size
(bits)
Offset from module base
address
PLL0CR
—
0x00000000
PLL0SR
—
0x00000004
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Table 83. Protected PLL registers (continued)
5.8.7
Register
Register size
(bits)
Offset from module base
address
PLL0DV
—
0x00000008
PLL1CR
—
0x00000020
PLL1SR
—
0x00000024
PLL1DV
—
0x00000028
PLL1FM
—
0x0000002C
PLL1FD
—
0x00000030
STCU configuration
The following table lists the CBIST collectors (Built-in Self Test on RCCUs monitoring
duplicated logic).
Table 84. CBIST collectors
CBIST DCF
Comparators protected by CBIST
CBIST ID
STCU_CBIST0_PTR
Core1, Core2, ITCMs, DTCMs
0
STCU_CBIST1_PTR
DMA1, DMA2
1
STCU_CBIST2_PTR
AHB1, AHB2
2
STCU_CBIST3_PTR
APB1
3
STCU_CBIST4_PTR
APB2
4
STCU_CBIST5_PTR
HRTimer_1
5
STCU_CBIST6_PTR
HRTimer_2
6
STCU_CBIST7_PTR
Flash controllers: NVMC1, NVMC2
7
STCU_CBIST8_PTR
RAM controllers: RAMC1, RAMC2
8
STCU_CBIST9_PTR
MEMU
9
The following table lists the MBIST partitions (Built-in Self Test on memory cuts).
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Table 85. MBIST partitions
MBIST number
Location
Partition
Addressable
0
ICache_1
No
1
ICache_0
No
2
ICache_Tag_1
No
3
ICache_Tag_0
No
4
DCache_0_3
No
5
DCache_0_2
No
6
DCache_0_1
No
DCache_0_0
No
DCache_1_3
No
9
DCache_1_2
No
10
DCache_1_1
No
11
DCache_1_0
No
12
DCache_Tag3
No
13
DCache_Tag2
No
14
DCache_Tag1
No
15
DCache_Tag0
No
16
ICache_1
No
17
ICache_0
No
18
ICache_Tag_1
No
19
ICache_Tag_0
No
20
DCache_0_3
No
21
DCache_0_2
No
22
DCache_0_1
No
DCache_0_0
No
DCache_1_3
No
25
DCache_1_2
No
26
DCache_1_1
No
27
DCache_1_0
No
28
DCache_Tag3
No
29
DCache_Tag2
No
30
DCache_Tag1
No
31
DCache_Tag0
No
CAN Subsystem 0
RAM
Yes
7
8
23
24
32
Core1
Core2
CAN SUB0
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Start address in
MEMU
End address in
MEMU
0x6000_0000
0x6000_FFFF
0x6001_0000
0x6001_FFFF
0x6002_0000
0x6002_FFFF
0x6003_0000
0x6003_FFFF
0x6004_0000
0x6004_FFFF
0x6005_0000
0x6005_FFFF
0x6006_0000
0x6006_FFFF
0x6007_0000
0x6007_FFFF
0x6008_0000
0x6008_FFFF
0x6009_0000
0x6009_FFFF
0x4200_C000
0x4200_FFFF
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Table 85. MBIST partitions (continued)
Addressable
Start address in
MEMU
End address in
MEMU
RAM
No
0x600C_0000
0x600C_27FF
Flash
ROM
—
—
—
ETF
ETF RAM
No
0x600E_0000
0x600E_FFFF
36
PRAM_0
Yes
0x0100_0000
0x0100_1FFF
37
PRAM_2
Yes
38
PRAM_1
Yes
0x0100_2000
0x0100_9FFF
SBI_Cache_1
No
SBI_Cache_0
No
0x600A_0000
0x600A_0FFF
41
SBI_Tag_1
No
42
SBI_Tag_0
No
0x600B_0000
0x600B_07FF
43
MPAES
No
0x600D_0000
0x600D_FFFF
MBIST number
Location
33
Flash
34
35
39
40
HSM
Partition
44
—
System RAM_1_1
Yes
0x2401_0000
0x2401_FFFF
45
—
System RAM_1_0
Yes
0x2400_0000
0x2400_FFFF
46
—
System RAM_2_1
Yes
0x2403_0000
0x2403_FFFF
47
—
System RAM_2_0
Yes
0x2402_0000
0x2402_FFFF
48
I_TCM
Yes
0x5A00_0000
0x5A00_7FFF
49
D0_TCM_1
Yes
0x5C00_4000
0x5C00_7FFF
D0_TCM_0
Yes
0x5C00_0000
0x5C00_3FFF
51
D1_TCM_1
Yes
0x5C00_C000
0x5C00_FFFF
52
D1_TCM_0
Yes
0x5C00_8000
0x5C00_BFFF
I_TCM (NO_LS)
Yes
0x5A04_0000
0x5A04_7FFF
I_TCM (LS)
Yes
0x5A00_8000
0x5A00_FFFF
D0_TCM_1
(NO_LS)
Yes
0x5C04_4000
0x5C04_7FFF
D0_TCM_1 (LS)
Yes
0x5C01_4000
0x5C01_7FFF
D0_TCM_0
(NO_LS)
Yes
0x5C04_0000
0x5C04_3FFF
D0_TCM_0 (LS)
Yes
0x5C01_0000
0x5C01_3FFF
D1_TCM_1
(NO_LS)
Yes
0x5C04_C000
0x5C04_FFFF
D1_TCM_1 (LS)
Yes
0x5C01_C000
0x5C01_FFFF
D1_TCM_0
(NO_LS)
Yes
0x5C04_8000
0x5C04_BFFF
D1_TCM_0 (LS)
Yes
0x5C01_8000
0x5C01_BFFF
50
Core1
53
54
55
56
57
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5.8.8
Device configuration
ECC
Error correcting codes are used for end-to-end protection from cores to system storage as
well as for individual protection of peripheral RAMs.
5.8.8.1
ECC for storage
All storage used in normal operation is protected by ECC with:
•
SEC/DED (single bit error correction and double bit error detection) for core, local
memory, peripheral RAM.
•
SEC/DED (single bit error correction, double bit error detection) for CODE Flash
memory.
•
DEC/TED (double bit error correction, triple bit error detection) for DATA Flash memory.
The following exceptions exist:
•
SRAM is protected by SEC/DEC ECC in PRAM controller only during partial writes
(RMW operations) otherwise it is protected by E2E-ECC mechanism.
•
The HSM’s AES program extension RAM are not protected by ECC.
A list showing the implementation of RAMs with ECC (including address protection) and for
SR5E1x is shown in the following table.
Table 86. ECC RAM implementations
Location
Cortex®-M7
Core 1
Cortex®-M7
Core 2
CAN
HSM
Platform
Memory
MEMU
classification
ECC
Address is
ECC
Muxing
Factor
Reacts to
uncorrectable
error
I-Cache
System RAM
SEC/DED
No
4
Y
ITAG
System RAM
SEC/DED
No
4
Y
D-Cache
System RAM
SEC/DED
No
4
Y
DTAG
System RAM
SEC/DED
No
4
Y
ITCM
System RAM
SEC/DED
No
8
Y
DTCM
System RAM
SEC/DED
No
8
Y
I-Cache
System RAM
SEC/DED
No
4
Y
ITAG
System RAM
SEC/DED
No
4
Y
D-Cache
System RAM
SEC/DED
No
4
Y
DTAG
System RAM
SEC/DED
No
4
Y
ITCM
System RAM
SEC/DED
No
8
Y
DTCM
System RAM
SEC/DED
No
8
Y
CAN
Peripheral
SEC/DED
No
8
Y
PRAM
Peripheral
SEC/DED
No
8
Y
I-Cache
Peripheral
SEC/DED
No
4
Y
ITAG
Peripheral
SEC/DED
No
4
Y
C3
Peripheral
—
No
4
N
No
16
Y
SRAM
System RAM
E2E_ECC
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1. SEC/DEC for partial write operation (RMW).
As shown in Table 86: ECC RAM implementations, some memories, particularly system
storage, use an ECC computed over data to detect faults (no/wrong/multiple selection). In
addition, these same memories include dedicated measures against addressing and control
faults (such as address/control feedback). This is different for storage related to PeMos.
PeMos, in general, do not include additional measures to detect them. All ECC calculations
for RAMs in PeMos are accomplished by logic outside of the RAM, not in the RAM block.
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6
Reset and Boot
6.1
Introduction
This chapter describes the reset and boot phase, from the time a power on or reset is
applied, till the completion of the Boot Assist Flash (BAF) code.
After reset, Core_1 is woken-up, Core_2 and HSM may be woken-up (refer to details in
Chapter 7: Device configuration format (DCF) records).
The following memory elements are involved in the boot-up process:
• UTEST flash memory
• TEST flash memory
• Boot Assist Flash (BAF)
6.1.1
TEST flash memory block
The TEST flash memory block contains Device Configuration Format (DCF) records used to
hold trim values and other variables, as well as general device configuration information.
The trim values are for:
• Adjusting low-voltage and high-voltage detect circuit trip points
• Temperature sensor adjustments
• Power-on reset voltage trip point
• Analog-to-digital adjustments
• Internal RC oscillator (IRCOSC) trim values
• Power management configuration, for the devices supporting different regulation
schemes
Note:
The DCF records are written by the device manufacturer and programmed into TEST flash
memory during production testing. Further programming of the TEST flash is disabled at the
end of the factory test cycle.
6.1.2
UTEST flash memory block
The UTEST flash memory block also contains DCF records. Some UTEST DCF records are
written by the factory and programmed during production testing. Others are written by the
end user and programmed at the same time application code is programmed into the flash
memory. UTEST DCF records are used to set up various control and configuration registers,
including the Self-test control unit (STCU3) and default memory configuration.
6.1.3
Boot Assist Flash
The Boot Assist Flash (BAF) contains factory code to facilitate the device boot-up
procedure.
Refer to Chapter 18: Boot assist flash (BAF) for further details on this procedure.
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Modules used in reset sequence
The modules involved in the SR5E1x reset sequence are:
• Power management controller (PMC)
• Reset and clock control module (RCC)
• System status and configuration module (SSCM)
• Self-test control unit (STCU3)
6.2.1
Power Management Controller
The Power management controller (PMC) controls and monitors:
• Its own supply voltage
• The supply voltages to all the high- and low-voltage detect circuits
• The trip points for all the high- and low-voltage detect circuits
• The power supplies and reference voltages to the analog-to-digital converter
• The major power supplies to the SR5E1x
6.2.2
Reset and Clock Control Module (RCC)
The reset and clock control module (RCC) is a complex state machine that begins
sequencing the SR5E1x through the initial steps of the reset process. The RCC does not
execute program code, it is a state machine that centralizes the different reset sources and
manages the reset sequence. Reset sources are organized into two categories: destructive
and functional.
The RCC is responsible for configuring the execution mode, including the delivery of reset
vectors to all the SR5E1x cores.
Refer to Figure 13: Reset sequence for more information on the RCC reset sequence.
6.2.2.1
Destructive resets
A destructive reset source is related to a critical error or dysfunction, usually caused by a
hardware malfunction. When a destructive reset event occurs, software recovery is not
possible and the contents of memory are assumed unknown. A full device reset sequence
starting from PHASE0 is therefore applied to the device, ensuring a safe startup state for
both digital and analog modules.
Examples of destructive resets are:
• Power-on reset
• External reset
• Low voltage detection
• Reset escalation (when too many functional resets occur simultaneously)
6.2.2.2
Functional resets
A functional reset source is related to a less critical error or dysfunction usually not
associated with hardware malfunction. When a functional reset event occurs, a partial reset
sequence is applied to the device starting with PHASE1[FUNC]: most digital modules are
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reset normally and the state of analog modules, specific digital modules (for example, debug
and flash memory modules) and system memory content is preserved.
Examples of functional resets are:
• Software reset from RCC
• Boundary scan instructions
• Alarm thresholds from low voltage and temperature detection
6.2.3
System Status and Configuration Module
During the reset phase, the SSCM reads the DCF records in the TEST and UTEST flash
memory areas in order to distribute within the device the pre-assigned configuration.
The DCF records are primarily for setting up the memory, configuring the self-test control
unit (STCU3), and providing initial device configuration values.
The boot vectors for the cores are loaded inside RCC as DCF records by the SSCM. The
start addresses are written into the RCC registers, which, in turn, pass them to the proper
CPU at the end of the reset phase.
6.2.4
Self-Test Control Unit
The self-test control unit (STCU3) is a self-contained module that runs a specific logic builtin self-test (CBIST) and a memory built-in self-test (MBIST). The DCF record can be used to
select which individual tests are run for CBIST and MBIST and disable tests for modules
and memory elements that are not going to be used in user applications, thus shortening
device boot-up time.
6.3
Reset sequence
The power-up reset sequence always begins with the application of power and follows
different sequences depending on the condition of the SR5E1x device and whether various
modes are enabled from settings in the DCF records. For instance, the SR5E1x device
enters Serial Boot mode (the Serial Boot Loader receives startup code and begins program
execution) if there is not a valid address in C1_APPLI_ADDR DCF.
6.3.1
Power-on and the Reset Generation Module
When power is applied to the SR5E1x, the Reset and Clock Control Module (RCC)
advances the device through a series of steps shown in Figure 13: Reset sequence.
Reset and clock control module (RCC) starts the system status and control module (SSCM),
which continues the boot-up process after the RCC enters the IDLE state.
The STCU3 is reset and offline self-test (if enabled) is triggered on any power-on, or
destructive reset (including external reset through RESETN pad).
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Figure 13. Reset sequence
Power on Reset
Power up
Destructive reset
or
External reset
Phase 0 Destructive
Phase 1 Destructive
Phase 2 Destructive
Phase 3 Destructive
NO
Self test
enabled ?
YES
Idle Destructive
Self Test
completed ?
YES
Long functional reset
Phase 1 Functional
Phase 2 Functional
Short functional reset
(No sscm reset,
No DCFs loading,
No PLL reset)
Phase 3 Functional
Idle Functional
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Table 87. Module status during reset phases
Phase
Module
Power
Up
Destructive
Functional
P0
P1
P2
P3
IDLE(1)
P1
P2
P3
IDLE
Internal
RCOSC
RESET
ON
ON
ON
ON
ON
ON
ON
ON
ON
PMC
ON(2)
ON
ON
ON
ON
ON
ON
ON
ON
ON
RCC (Reset
State
Machine)
RESET ON(3)
ON
ON
ON
ON
ON
ON
ON
ON
Temperature
Thresholds
RESET
ON
ON
ON
ON
ON
ON
ON
ON
NVM
Running
NVM
RESET RESET
reset
phase
ON
ON
BIST
RESET
ON
ON
ON
XOSC
RESET RESET RESET
RESET
(ON(4))
(ON(4))
(ON(4))
(ON(4))
(ON(4))
(ON(4))
PLL
RESET RESET RESET
RESET
RESET
ON(5)
RESET
RESET
RESET OR
ON(6)
RESET
OR
ON(6)
Device
HOLD
Configuration
RESET RESET Reset
(for example
Value
DCF)
HOLD
Reset
Value
HOLD
HOLD
Loaded
Loaded Loaded
from NVM
Value
Value
HOLD
Loaded
Value
HOLD
Loaded
Value
HOLD
Loaded
Value
SSCM
RESET RESET RESET
RESET
ON
ON
RESET
RESET
ON
ON
FCCU
RESET RESET RESET
ON
ON
ON
ON
ON
ON
ON
CEMs
RESET RESET RESET
ON
ON
ON
ON
ON
ON
ON
MEMU2
RESET RESET RESET
ON
ON
ON
ON
ON
ON
ON
STCU
RESET RESET RESET CONFIG CONFIG
ON
IDLE
IDLE
IDLE
IDLE
Boot CPU
RESET RESET RESET
RESET RESET RESET
RESET
RESET
ON
ON
ON
ON
PASS
(7)
RESET
ON
ON
ON
RESET
ON
ON
ON
ON
IWDGs
RESET RESET RESET
RESET
RESET RESET RESET
RESET
RESET
ON/
IDLE(8)
Other cores
RESET RESET RESET
RESET
RESET
BIST
RESET
RESET
RESET
OFF
Other
modules
RESET RESET RESET
RESET
RESET
BIST
RESET
RESET
RESET
OFF
1. Self test is run if enabled via DCF, upon a Destructive Reset, including external reset from pad.
2. Set of voltage monitors used to detect when the minimum levels are reached.
3. RCC Reset State Machine is reset only upon a power-on.
4. XOSC activation is set via DCF.
5. PLL0 can be enabled during the offline self-test execution.
6. PLL setting is maintained in case of a Short Functional reset.
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7. PASS is reset upon a power-on, as it must be active in order to maintain the debug enabling status across a reset
sequence.
8. IWDGs can be activated in HW via DCF.
6.3.2
Power-up phase: power stabilization
When a power-on reset event occurs (initial application of power), the reset and clock
control module (RCC) causes the device to enter the power-up phase of the reset sequence
(refer to Figure 13: Reset sequence). The only method to enter the power-up phase is from
a power-on reset event.
The device remains in the power-up phase until the power management controller module
(PMC) determines that all power supplies are in their respective operational ranges.
The supplies for initial configuration are:
• VDD_HV_IO: high voltage supply for IOs and core module, including power management
unit, internal RC oscillator (IRCOSC).
• VDD_LV: low voltage supply for digital module, including low voltage supply for flash
module
• VDD_HV_FLA: high voltage supply for flash module.
Peripheral supplies such as VDD_HV_SAR, VDD_HV_SD_DAC_COMP, VDD_HV_ODC do
not gate the power-up process. The low- and high-voltage detect circuits for these and other
power supplies are managed by the PMC, which provides enable and status bits for these
voltage detection circuits.
The PMC sends a signal to the reset and clock control module (RCC) when power
stabilization has been achieved. The RCC module then advances to the PHASE0 state
(refer to Figure 13: Reset sequence). During the power-up phase, the PMC does the
following:
• Drives to a logic ‘0’ all VDs (voltage detectors) signals monitored by the power
management control (PMC) module.
• Monitors its own power supply voltage (VDD_HV_PMC) to determine that the applied
voltage is within a specified range.
• Monitors the core power supply voltage (VDD_LV) to determine that the applied voltage
is within a specified range.
• Monitors the low- and high-voltage detect circuit power supply voltage to determine that
the applied voltage is within a specified range.
• Holds the outputs of the internal low- and high-voltage detect circuits at a ground state
until the PMC determines that all power supplies needed for correct device initialization
and configuration are within their respective functional voltage ranges.
• Determines that all power supplies needed for correct device initialization and
configuration are within their respective functional voltage ranges.
• Enables all low- and high-voltage detect circuits once all power supplies are at their
functional levels.
• Begins to monitor the various power supplies using the high- and low-voltage detect
circuits.
• Provides status information to the reset and clock control module (RCC) indicating
whether or not power is properly applied.
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To exit power-up and enter PHASE0:
• All enabled destructive resets must be processed.
• All power supplies must be at their functional voltages.
• The PMC must signal the RCC that all power supplies are at the required levels.
6.3.3
PHASE0 Phase: analog supply initial configuration
This phase is entered:
• On exit from power-up phase.
• On a Destructive Reset event, including RESETN pin falling edge detection except for the
initial power-up sequence.
–
As soon as a destructive reset is detected, the reset state machine goes in
PHASE0, immediately from PHASE1[DEST], PHASE2[DEST], PHASE3[DEST],
IDLE[DEST], PHASE1[FUNC], PHASE2[FUNC], PHASE3[FUNC] or IDLE[FUNC].
During PHASE0:
• All digital modules are reset, including safety, security, and test modules.
• All trimming bits for analog modules are reset.
• Startup of the internal analog modules (IRCOSC, Flash memory, and I/Os) begins:
–
PMC determines that proper voltages are applied.
–
I/O pins are ensured correctly configured
To exit PHASE0 and enter PHASE1[DEST]:
• All enabled destructive resets must be processed.
• Gating PHASE0 must be released.
• All processes initiated in PHASE0 must be completed. This generally includes startup of
the internal analog modules: PMC, IRCOSC, and I/Os.
Note:
The core voltage must rise above LVD119 upper threshold to exit PHASE0. This ensures
significant hysteresis on low voltage supply avoiding spurious low voltage detection during
the power-up process.
6.3.4
PHASE1[DEST] Phase: temporization setup
This phase is entered on exit from PHASE0.
During PHASE1[DEST]: temporization to allow correct NVM reset is applied.
Test modules are available during PHASE1[DEST], but their functionality is limited by the
security module.
All PHASE1[DEST] tasks must be completed before entering PHASE2[DEST].
6.3.5
PHASE2[DEST] Phase: flash initial configuration
This phase is entered on exit from PHASE1[DEST].
During PHASE2[DEST]:
• Reset is released to the flash memory module by the Reset Generation Module.
• The flash memory module starts its initial configuration process.
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• The flash memory initialization is performed by a state machine internal to the flash
module.
• A Boot Timeout inside RCC monitors the flash memory configuration execution so that a
reset occurs in the event of configuration failure.
Note:
The RCC Boot Timeout is hardware configured to generate destructive reset in case of flash
memory failure during flash boot process. In this case the software can read the cause of
the reset by the RCC register flag DESR.D_SWT_Boot.
All PHASE2[DEST] tasks must be completed before entering PHASE3[DEST].
6.3.6
PHASE3[DEST] Phase: device configuration
This phase is entered on exit from PHASE2[DEST].
During PHASE3[DEST], the system status and configuration module (SSCM) starts by
retrieving the device configuration format (DCF) record from the TEST and UTEST flash
memory areas, and uses the configuration and initialization information therein to:
• Configure the self-test control unit (STCU3) and the initial memory map of the device. This
information enables tests that the STCU runs and also provides the memory map setup
information so that the STCU can test memory.
• Transfer reset vectors for the various cores, programmed as DCF records, to the reset
and clock control module (RCC).
• Write trim values for analog modules including the analog-to-digital converter, low- and
high-voltage detect circuits, and the temperature sensor to their respective registers.
The DCF record programmed into the TEST flash memory area is written by the
manufacturer. The portion of the DCF record programmed into the UTEST flash memory is
usually written by the customer, although there is a default DCF record programmed into
both the TEST and the UTEST flash memory areas during device production testing.
The DCF record also provides configuration information for the following:
• Trimming of the analog modules (for example, voltage regulator, voltage detectors, I/Os,
and oscillator)
–
Trim values are in DCF records in the TEST flash memory area
–
Trim values are determined during production test and programmed into the TEST
flash memory area
–
Security configuration
• Application configuration bits:
–
Watchdog configuration
–
Safety execution directives (self-test, CBIST/MBIST)
–
Boot Assist Flash options
–
Oscillator startup during reset sequence configuration
To exit PHASE3[DEST]: All processes that need to be completed in PHASE3[DEST] must
be finished.
This phase depends on actual trim values, especially those used for safety execution
directives. This device configuration is maintained until the next internal power-on reset.
Each time a destructive reset event occurs, the SSCM takes values from the DCF record
and writes them to the applicable registers.
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During this phase, the internal STCU watchdog is started and is only cleared after
completion of STCU configuration.
If self-test execution is the configuration information from the DCF record requests, the
device moves to IDLE[DEST] and the STCU3 begins self-test. At the end of the test, the
STCU3 asserts a functional interrupt causing the Reset Generation Module to move to
PHASE1[FUNC]. If self-test execution is not requested, the device moves directly to
IDLE[FUNC]. The Reset Generation Module determines whether self-test execution is
enabled or not by examining an entry in the DCF record stored in the UTEST flash memory.
Note:
When self-test execution is not requested, it is possible to maintain the device in
PHASE3[DEST] by forcing RESETN pin low. This can be used for debugging purposes by
allowing external test/development equipment to connect through JTAG to the internal
debugger.
6.3.7
IDLE[DEST] Phase: self-test execution
This phase is entered upon exit from PHASE3[DEST] if the execution of self-test is enabled.
During the IDLE[DEST] phase:
• Dedicated watchdog is configured to monitor self-test execution completion within
expected time. The length of this phase is variable depending on the self-test
requirements.
• The self-test control unit (STCU3) executes all tests specified by the DCF information
retrieved in PHASE3[DEST].
• The self-test engine updates the self-test completion flag and triggers an associated
functional reset on completion of self-test.
The length of this phase is variable depending on the self-test requirements.
Note:
When the SSCM is decoding the Device Configuration field, it sets and clears various flags
in STCU registers and memory that can later be examined by the SSCM to determine which
self-test directives must be run.
Exiting IDLE[DEST] and moving to PHASE1[FUNC]:
• The IDLE[DEST] phase is automatically exited when the self-test code generates a
functional reset on completion.
• The functional reset causes the reset generation module to move to the PHASE1[FUNC]
phase.
Note:
In the case of unrecoverable fault detected during the execution of the offline BIST, the
STCU requests a destructive reset and device re-enters PHASE0[DEST].
In the case of a permanent fault, when the reset escalation is reached, the hardware keeps
the device in PHASE0[DEST] until a Power On Reset occurs.
Whereas in the case of a transient fault, the software can read the cause of the reset by
reading the RCC register flag DESR.D_STCU_CF.
6.3.8
PHASE1[FUNC] Phase: temporization setup
This phase is entered either:
• On exit from IDLE[DEST].
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• Immediately from PHASE2[FUNC], PHASE3[FUNC], or on IDLE[FUNC] when a nonmasked external or functional reset event occurs, providing the source of the reset event
has not been configured to trigger a ‘short’ reset sequence.
During PHASE1[FUNC]:
• Temporization to allow correct NVM reset is applied.
To exit PHASE1[FUNC] and enter PHASE2 [FUNC]:
• All enabled, non-shortened functional resets must be processed.
• All processes started in PHASE1[FUNC] must be completed.
During this phase, test modules are available.
6.3.9
PHASE2[FUNC] Phase: flash initial configuration
This phase is entered on exit from PHASE1[FUNC].
During the PHASE2[FUNC] phase:
• The reset signal is released to the flash memory.
• Flash initialization and configuration begins using a state machine that is internal to the
flash memory module.
• A Timeout watchdog inside RCC monitors flash initialization to ensure a reset in case of
flash memory configuration failure.
The reset state machine exits PHASE2[FUNC] and enters PHASE3[FUNC] on verification
that all processes started in PHASE2[FUNC] are completed.
6.3.10
PHASE3[FUNC] Phase: device configuration monitoring
PHASE3[FUNC] is entered:
• On exit from PHASE2[FUNC].
• Immediately from IDLE[FUNC] when an enabled, short functional reset event occurs.
During PHASE3[FUNC], configuration information contained within the UTEST flash
memory sector is checked against information extracted during PHASE3[DEST] and written
to the Self-Test Control Unit (STCU3). In case of mismatches, a dedicated boot fault is
triggered within the FCCU which, if enabled, can cause a system reset. The purpose of
PHASE3[FUNC] is to verify that the DCF information transferred to the STCU, RCC and
other modules, in PHASE3[DEST], was performed correctly and has not been corrupted.
The Reset Generation Module exits PHASE3[FUNC] and enters the IDLE[FUNC] on
verification of the following:
• All processes started in PHASE3[FUNC] are completed.
• RESETN is not forced low externally.
• A minimum number of cycles have elapsed since the last enabled, shortened functional
reset event.
After all PHASE3[FUNC] internal actions have been completed, it is possible to maintain the
device within PHASE3[FUNC] by forcing RESETN pin low. This can be used for debugging
purposes in order to connect through the JTAG port to the internal debugger.
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6.3.11
Reset and Boot
IDLE[FUNC] Phase
This is the Reset Generation Module’s final phase of the reset sequence. It is entered either
on exit from PHASE3[DEST] (if self-test was not enabled) or at the completion of
PHASE3[FUNC]. When the IDLE[FUNC] phase is reached, the RCC releases control of the
system to the system status and control module. The SSCM, which started in
PHASE3[FUNC], (or in PHASE3[DEST] in case no self-test was enabled) runs and waits for
a signal from the RCC indicating that the reset state machine is now in the IDLE state. The
RCC then waits for new reset events that can trigger a reset sequence.
6.3.12
System start-up
At the start-up, only one processor (from now on called Boot CPU) and, if enabled, the
Security Module CPU wake up.
6.3.12.1
Boot CPU reset vector
After the reset phase is completed, the Boot CPU starts executing at the value forced onto
its reset vector. The reset vector is driven by the RCC peripheral, according to the value
stored into the RCC register C1_VTOR_INIT_REG.
The RCC register C1_VTOR_INIT_REG for the Boot CPU is initialized basing on life cycle
and the system startup configuration data, stored in Flash and read by the SSCM from the
Flash during the reset. Also the enabling of the Security Module CPU is written by the
SSCM, basing on the content of the related DCF record.
6.3.12.2
Boot CPU start-up
The Boot CPU startup configuration comprises of the following settings:
• BAF_BYP configuration DCF bit inside Core1 Alternate Configuration DCF. It is used to
decide whether the BAF code (stored by the manufacturer in the Flash BAF block) is
skipped or executed. The customer Alternate BAF start address is also set within the
same DCF.
• Core1 User Application Address DCF (programmed by the customer). It is used to set the
customer application entry point after reset or after the BAF execution (if enabled).
The target for this device is to let the customer choose either the BAF code or directly the
customer application software to be started after the reset phase using the same sales part
number.
The Core1 Alternate Configuration DCF, that is used to set the BAF configuration, must be
permanently written into the UTest block.
If the BAF_BYP configuration DCF bit is not programmed, the default value for the reset
start address depends on the Life Cycle.
If the BAF_BYP configuration DCF bit is programmed, its value determines whether the
CPU starts directly from the BAF code (programmed by ST in the Flash BAF block) or at the
Alternate BAF Address entry point defined by the customer.
The application entry point is retrieved in HW by the SSCM and written inside the RCC
register C1_VTOR_ADDR_REG. This register is read by the BAF, to jump to Application
start address, at the end of BAF execution itself. The BAF makes some checks about the
validity of the Application address, loaded by SSCM inside RCC.
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The RCC register C1_VTOR_ADDR_REG can be updated by the user for a maximum of 4
times during the device lifetime, writing the corresponding DFC record inside the flash.
The field UPDATES_COUNT inside the RCC register C1_VTOR_ADDR_REG reports how
many times the register has been written by the SSCM during the reset sequence, indicating
how many updates of the Application address has been stored inside NVM memory.
6.3.12.2.1 Start-up flow chart
The setting of the Boot CPU start address is performed through a Hard Ware flow, based on
the device life cycle and the value of some Device Configuration Format (DCF) records.
The flow followed by the Reset State machine to determine the Boot CPU start address is
depicted in Figure 14: Boot CPU start-up sequence.
In case the NVM is not initialized or if the test mode is entered, the Boot CPU reset vector is
set at the start address of the System RAM (0x2400_0000h).
In case the BAF (Boot Assist Flash) is not bypassed, the Boot CPU starts from the BAF
default address (0x1FF0_0000), that contains the BAF code provided by
STMicroelectronics device manufacturer.
In this case, at the end of BAF execution, a jump is done at the User Application Code start
address, stored during boor phase inside the RCC register C1_VTOR_ADDR_REG.
In case the BAF is bypassed, the Boot CPU start address is set accordingly to the field
C1_AL_VTOR_BAF_INIT of Core1 Alternate Configuration DCF record. The code at this
address must be provided by the user and must take care of security and safety
configurations of the device, in a similar way as the manufacturer BAF code.
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Figure 14. Boot CPU start-up sequence
RESET
YES
Is NVM Not Initialized?
NO
(*) only in the lifecycles
in which test mode is
allowed
YES
SRAM execution
forced via TCU during
reset phase ?
(*)
NO
NO
Is
C1_AL_BAF_ADDR
programmed ?
YES
YES
Shall BAF be executed ?
NO
Start
address
= =
Core1
VTOR
content
SRAM First location
6.3.12.3
Execute BAF
(BAF_ADDR default value)
Start from user defined address
(C1_AL_BAF_ADDR user
programmed value)
Security Module CPU start-up
The Security Module CPU is also woken up after a reset, if the hardware security module is
enabled by DCF record. The security module CPU start address is at fixed location as it is
not possible to provide a programmable Init Vector to the Security Module CPU.
If HSM is not enabled to wake up in parallel to Boot CPU, it can be woken up also by
Application SW, writing inside the RCC register HSM_SW_CTRLR. HSM SW enabling is
conditioned by a Security DCF (See the security reference manual for additional
information).
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6.3.13
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Waking-up the other CPU
The process of waking-up the other CPU (Core_2) is handled by writing some registers
within the reset and clock control module (RCC) registers.
The start address of Core_2 CPU is loaded from NVM during reset phase by SSCM.
The value of Core2 Vector Table Offset DCF is copied by SSCM inside the RCC register
C2_VTOR_INIT_REG.
If the BAF code is executed, it reads form the RCC register SYS_CFG_REG if Core_2 has
to be started. The Core_2 can be woken up by writing inside the RCC register
C2_BOOT_CTRL_REG.
If the BAF code is not executed, it is responsibility of the user code to properly write the
RCC module registers and in order to wake up the other CPU form the intended addresses.
6.3.14
BAF serial bootloader
The BAF code includes a way to upload via CAN or UART some code into the system RAM
and execute it. The possibility to execute the bootloader is conditioned by the Life Cycle
status, which regulates what can or cannot be done according to the stage of the microcontroller. If the bootloader is allowed by the Life Cycle, then it is executed whenever the
Boot CPU executing code in the BAF does not find a valid content in the RCC register
C1_VTOR_ADDR_REG. This register content is defined by the Core1 User Application
Address DCF record. This mode uses a defined protocol to receive a program over a serial
port via UART or CAN. The Boot CPU then jumps to the first instruction of the uploaded
program and begins execution.
The BAF bootloader code includes the following steps:
1.
Configure UART or M_CAN module and external pins
2.
Wait for START WORD
3.
Receive START WORD
4.
Receive START ADDRESS
5.
Receive DOWNLOAD SIZE
6.
Receive CODE
7.
Branch to START ADDRESS
Note:
There is a software watchdog timer that is started by the BAF code. If a program is not
received before the watchdog timer timeout, a reset occurs.
6.4
RESETN pin functionality
The device has one reset pad:
• RESETN: it can be configured as reset input/output.
The settings of RESETN pad are determined at device power-on and depend on Life cycle
and on RESET_CFG DCF, as shown in Figure 15: RESETN Settings and Figure 16:
RESETN Flow Chart.
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Figure 15. RESETN Settings
Input conditions
Behavior (set at power-on)
DCF RESET_CFG
[RESN_PDOWN_EN]
Life Cycle
From Power on
till DCFs are read
Any non-Power On
reset phase (either
Destructive or Functional )
after internal RESETOUT
release
Description :
SW
Run time
RESETN PullDown Enable
ST Production , Customer
Delivery
NOT programmed
Strong pull -down
Bidirectional with Weak pull -up
Pad level as forced from outside
OEM Production , In-Field ,
Failure analysis
NOT programmed
Strong pull -down
Bidirectional with Weak pull -down
Pad level as forced from outside
Don’t care
Programmed to 0
Strong pull -down
Bidirectional with Weak pull -down
Pad level as forced from outside
Figure 16. RESETN Flow Chart
Power-on
RESETN = Bi-directional
with Strong Pull-down
(default value when the
RESET_CFG DCF is not
programmed)
RESETN
configuration logic
NO
Phase 0 DEST
Is RESET_CFG
programmed ?
YES
Phase 1 DEST
Phase 2 DEST
ST PROD or
CUSTOMER DELIVERY
Life Cycle
OEM PRODUCTION,
IN FIELD, or FA
Phase 3 DEST
(read Life Cycle)
Phase 3 DEST
(read RESET_CFG)
RESETN
configuration logic
IDLE DEST
RESETN = Bi-directional
with Weak Pull-up
RESETN = Bi-directional
with Weak Pull-down
FUNCT phase
The waveforms associated to RESETN configuration at Power-on are shown in Figure 17:
RESETN behavior set-up at POR.
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Figure 17. RESETN behavior set-up at POR
Power-on
Destructive phases
After DCF are read
Functional phases
Before DCF are read
RESETN
SW
Run-time
Bi-directional Configuration
External pull-up needed when Life Cycle > Customer delivery
RESET_CFG[PDOWN_EN]= 0
Strong pull-down
If Life Cycle <= Customer Delivery and the RESET_CFG DCF is not
programmed, then Weak pull-up otherwise Weak-pull-down
As RESETN pad is bidirectional, it has the capability to report in output the POR reset plus
the enabled destructive and long functional resets.
The RESETN input buffer is always enabled.
When the RESETN pad reports in output the reset of the device generated by an internal
source, the pad output buffer is enabled too, while the input from pad is masked towards the
internal of the device.
The functionality of reporting an internal reset in output is called RESETOUT and is
identified also as “strong pull-down active” (due to the fact that the output buffer of the pad is
enabled).
The behavior of the RESETN pad, in case of RESETOUT, is depicted in Figure 18:
RESETOUT behavior for the various type of internal resets: POR reset (always reported),
destructive (always reported) and long functional resets (reported, if enabled).
When internal pull-down is enabled, the external pull-up has to be chosen in order to win the
internal weak pull-down, and to allow to see the RESETOUT outside.
A transition from high to low of the RESETN pad has to trigger a destructive reset. Once the
falling edge is detected, the actual value of RESETN pad has no effect till the end of RESET
PHASE3, where a low value from outside or from internal weak pull-down can stretch the
exit from PHASE3 and the overall reset duration.
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Figure 18. RESETOUT behavior
Example of Power-on Reset
Power-up
Self Test Enabled (*)
RESETN
RESETOUT
behavior
PH0D
PH1D
PH2D
PH3D
IdleD
PH1F
PH2F
PH3F
IdleF
RESETOUT driven for
fixed duration (100us)
PH0D including RCOSC stabilization
RESETOUT driven till end of PH3D
Example of Internal
Functional reset
Example of Internal
Destructive reset
Internal Destructive
Reset Event
Internal Functional
Reset Event
Power is stable
Self Test Enabled (*)
RESETN
RESETOUT
behavior
PH0D
PH1D
PH2D
PH3D
RESETOUT driven till end of PH3D
IdleD
PH1F
PH2F
PH3F
IdleF
RESETOUT driven for
fixed duration (100us)
PH1F
PH2F
PH3F
IdleF
RESETOUT driven for
fixed duration (100us)
Strong pull-down = Driven from RESETN PAD Output Buffer
External Pull-up
(*) Functional Reset following SelfTest Execution
The RESETN pad settings are regulated by RESET_CFG DCF.
RESET_CFG DCF client is reset by a power-on reset only.
This DCF has to be programmed to make effective the activation of the pull-down, otherwise
the pull-up/pull-down configuration of the RESETN pad is regulated by the life cycle.
6.5
Reset Sources Mapping
Table 88: Destructive Reset Sources shows the various destructive reset events and
Table 89: Functional Reset Sources shows the various functional reset events.
The following symbols are used within the tables:
D: Feature is disabled and cannot be enabled
E: Feature is enabled and cannot be disabled
P[D]: Feature is programmable, default is set to: disabled
P[E]: Feature is programmable, default is set to: enabled
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6.5.1
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Destructive Reset Sources
This section describes the destructive reset sources.
Table 88. Destructive Reset Sources
Reset source
Name
Configuration
Description
Input
RESETN
OUT(1)
Escalation
D_POR
Device Power On-Reset (POR)
POR
E
—
D_RESETN
RESETN pin
D[1]
E
—
Reserved
Reserved
D[2]
—
—
D_RCC_SW
Software destructive reset from RCC
D[3]
E
—
D_FCCU
FOSU reset
D[4]
E
—
D_STCU_CF
STCU critical failure indicated by
STCU_CF trigger(2)
D[5]
E
—
Reserved
Reserved
D[6:7]
—
—
D_EDR
Escalation destructive reset
D[8]
E
—
D_SWT_Boot(3)
Boot watchdog timeout during NVM
initialization
D[9]
E
—
D_JTAG
JTAG destructive reset request
D[10]
P[E]
—
Reserved
Reserved
D[11:13]
—
—
D_SSCM
SSCM destructive reset
D[14]
E
—
D_HSM(4)
HSM destructive reset request
D[15]
E
—
D_TSENS
Temperature sensor
D[16]
E
—
Reserved
Reserved
D[17:23]
—
—
D_VD
Voltage out of range from LVDs and/or
HVDs
D[24]
E
—
Reserved
Reserved
D[25:31]
—
—
1. This column shows how the RESETN reports in output the internal destructive reset, if reset source is enabled.
2. Same UF signal sent to the FCCU.
3. This trigger is generated by the watchdog only in case of timeout happening during the reset phase. When the reset phase
is completed, this trigger is internally disabled by the RCC.
4. The possibility to trigger a destructive reset controlled by the HSM can be enabled or disabled via DCF.
6.5.2
Functional Reset Sources
This section describes the functional reset sources.
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Table 89. Functional Reset Sources
Configuration
Reset source
Functional
Reset type (1)
Input
Name
Description
Long
Reset
Short
Reset
RESETN
OUT(2)
Escalation
Reserved
Reserved
F[1:0]
—
—
—
—
F_ST_DONE
Self-test functional reset
F[2]
E
D
E
—
F_RCC_SW
Software functional reset from RCC
F[3]
P[E]
P[D]
P[D]
—
Reserved
Reserved
F[4]
—
—
—
—
F_FCCU_LONG
Long functional reset
F[5]
E
D
P[D]
—
F_FCCU_SHORT Short functional reset
F[6]
D
E
D
—
Reserved
Reserved
F[7:9]
—
—
—
—
F_JTAG
JTAG reset
F[10]
P[E]
P[D]
P[D]
—
Reserved
Reserved
F[11:14]
—
—
—
—
F_HSM(3)
HSM Functional Reset
F[15]
E
P[D]
P[D]
—
F_TSENS
Temperature sensor
F[16]
P[E]
P[D]
P[D]
—
Reserved
Reserved
F[17:23]
—
—
—
—
F_VD
Voltage detector for Peripheral
Domain
F[24]
P[E]
P[D]
P[D]
—
Reserved
Reserved
F[25:28]
—
—
—
—
Reserved
Reserved
D[30:31]
—
—
—
—
1. Set by specific RCC register (FORER register)
2. This column shows how the RESETN reports in output the internal functional reset: only enabled long functional resets are
reported in output on RESETN pad. If the reset source is programmed to generate a short functional reset, the internal
reset is not brought in output.
3. The possibility to trigger a functional reset controlled by the HSM can be enabled or disabled via DCF
6.5.3
Functional reset escalation
‘Functional' reset escalation can be used to generate a 'destructive' reset if a number of
'functional' resets, triggered by any of the functional reset input signals, have occurred
between software writes to a specific RCC register.
This function is enabled by writing a non-zero value in a specific RCC register (FRETR
register). Default value at reset of this register is 15.
Once 'functional' reset escalation has been enabled, the RCC increases a counter on each
'functional' or external reset which causes a reset sequence to be initiated (that is an
entrance into PHASE 1 or PHASE 3 from the IDLE phase). This counter is cleared on a
write of any value to the specific RCC register and on any power-on or 'destructive' reset. If
the counter reaches the value set into a specific RCC register, the RCC starts a destructive
reset sequence at PHASE 0.
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6.5.4
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Destructive Reset Escalation
'Destructive' reset escalation can be used to keep the chip in the reset state until a new
power-on triggers a reset sequence if a number of 'destructive' resets, triggered by any of
the destructive reset input signals, has occurred between software writes to a specific RCC
register.
This function is enabled by writing a non-zero value to a specific RCC register (DRETR
register). The default value at reset for this register is 15.
Once 'destructive' reset escalation has been enabled, the RCC increases a counter on each
'destructive' reset which causes a reset sequence to be initiated (that is entrance into
PHASE 0 from the IDLE phase) or an ongoing reset sequence to restart (that is entrance
into PHASE 0 from PHASE 1, PHASE 2, or PHASE 3).
This counter is cleared on a write of any value in the specific RCC register and on any
power-on reset. If the counter reaches the value set into the specific RCC register, the RCC
enters reset PHASE 0 and stays there until the next power-on reset occurs.
6.6
RAM preservation upon reset
The content of some RAM modules of the device is preserved in case of:
• all long functional resets
• all short functional resets
RAM preservation is implemented for Core1 and Core2 ITCMs and DTCMs and for the
System RAM.
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Device configuration format (DCF) records
7
Device configuration format (DCF) records
7.1
Introduction
Device configuration format (DCF) records are used to configure certain registers in the
device during system boot while the reset signal is asserted. An individual DCF record is 64
bits long. It consists of a pointer to the location of a register internal to the device and the
respective data.
There are two broad categories of DCF records: TEST DCF records and UTEST DCF
records.
•
Note:
–
Program registers involved in trimming trip points for voltage comparators
–
Adjusting analog to digital voltage supplies
–
Trim oscillator frequencies
–
Enable RAM repair
The TEST DCF records are programmed into TEST Flash during production and cannot be
modified. TEST Flash is not visible to the user.
•
Note:
TEST DCF records are programmed by the MCU manufacturer. They are used mainly
to:
UTEST DCF records can be either:
–
Factory programmed during production testing.
–
User programmed when application code is written into the Flash memory. Usersupplied UTEST DCF records start at the next location in the UTEST memory map
following the factory UTEST DCF records. The user-defined DCF records set up
the initial memory map, define which tests are executed by the Self-Test Control
Unit (STCU) during the boot sequence, enable the HSM, assign Flash memory
blocks to specific tamper detect regions, assign memory blocks as OTP and
assign Flash blocks to be associated with specific password groups.
DCF records are HW processed by SSCM during reset.
Soft DCF records are SW processed by BAF code execution. Please see Section 18.3.5.1:
‘Soft’ DCF clients in Chapter 18: Boot assist flash (BAF).
System boot is a complex process requiring a considerable amount of initialization to take
place before releasing reset. Before the device can be used in an application, the user
application code, reset vectors for all of the CPUs and the DCF records must be properly
programmed into their respective Flash memories.
7.2
DCF clients
DCF clients are 32-bit hardware registers inside a module that receive and store the data
from a DCF record. This stored data is used to initialize registers and to configure features.
DCF clients have a default value before any DCF records are written and may have special
writing constraints like ‘Write Once’ or only allowing bits to be written from ‘1’ to ‘0’ or vice
versa.
A list of DCF clients is shown in Table 92. (TEST DCF record only clients are not shown as
these are not accessible by the user).
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The DCF records select the target DCF client via a 30-bit field in the DCF record consisting
of:
7.3
•
A 15-bit chip-select field: each module that includes DCF clients is assigned a chip
select during chip definition.
•
A 15-bit address field: the address field is only relevant to the address decoding within
that module and may not necessarily relate to the address of a register visible to
software.
DCF records
DCF records are contiguous double-word (64 bits) entries programmed in a reserved area
of OTP UTEST Flash memory beginning at 0x1FF8_0300. The ECC granularity is 64 bits
(complete with a dummy DCF if needed). Address alignment is on 64 bits.
Caution:
Once a stop record is detected, the SSCM stops scanning for further records.
The structure of a DCF record is shown in the figure below.
PAR
STOP
Field
CS15
CS14
CS13
CS12
CS11
CS10
CS9
CS8
CS7
CS6
CS5
CS4
CS3
CS2
CS1
CS0
Bit n° 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
ADDR
Bit n° 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
Field
DATA_MSW
DATA_LSW
4
3
2
1
0
Figure 19. DCF record structure
Table 90. DCF record field description
Field
Description
63:48
CSn
Chip select n
1 Chip select is asserted
0 Chip select is negated
Note: Only assert one bit per DCF record to select the target module for the DC client.
All other chip selects must be negated.
47:34
ADDR
Address (client selection)
The address field determines which client, within the target IP, has to receive the
data.
33
PAR
DCF record parity
This field is used to set even parity calculation for the data field DCF record.
The DCF client reports an error for any calculated parity that does not match the
value of this bit.
32
STOP
Stop bit
This bit determines if the SSCM keeps on scanning the current DCF area beyond the
current DCF or stop the reading.
0 SSCM keeps on scanning.
1 SSCM stops scanning and move to the next DCF area.
31:0
DATA_MSW
DATA_LSW
184/2075
Payload
This field contains the DCF data, which is used by the client to drive its output
signals.
RM0483 Rev 5
RM0483
Device configuration format (DCF) records
The following structure must be present:
•
The first record must be a start record.
•
DCF records containing configuration data must immediately follow the start record
with no blank records between an unprogrammed record is interpreted as a stop record
and no DCF records following that record are processed.
•
The end of the configuration records are indicated by the presence of a bit in the DCF
record (stop record).
Each record is 64 bits long. Figure 20 shows the DCF start record.
Caution:
The start record must be placed at the beginning of the DCF area in UTEST Flash memory
to indicate that the following data records must be processed.
Figure 20. DCF start record
0x00
0:31
0x04
32:63
0x05AA55AF
0x00000000
During system boot, while the reset signal is asserted, the SSCM reads the device
configuration records and writes the data to the appropriate internal module registers. Many
operational aspects of the device are therefore already configured when the reset signal is
released and normal device operation begins.
Some device configuration records are calculated during production testing and
programmed into the TEST Flash memory area. Other DCF records are developed by the
user and programmed into the UTEST Flash area.
The stop bit designates the last device configuration record in a set of records. If it is set to
‘1’ within a DCF, then this DCF is the last one being read during the reset phase. A DCF can
have the stop bit set to ‘1’ in two modes:
a)
The Flash memory location of a DCF is not programmed (that is all the bits are set
to ‘1’).
b)
A DCF is programmed and the stop bit is set to ‘1’.
When the device is shipped from the factors, some DCF records are already programmed
and the Flash memory location after the last DCF is left unprogrammed to make it possible
to add additional DCF records.
Due to the Flash programming memory resolution, which is twice the length of a DCF
record, in case an odd number of DCF must be written but additional DCF must be
programmed later on, then a dummy DCF must be written to pad the last 64 bits of the
programming data.
A dummy DCF can be one of the following:
a)
The same DCF record written within the 128 bits (that is the DCF record is written
two times).
b)
A DCF record with an invalid Chips Select (refer to the Table 92 for a list of used
Chip Selects).
RM0483 Rev 5
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Device configuration format (DCF) records
RM0483
The padded DCF must have the stop bit set to ‘0’ in order to be able to add new DCF
records.
The general format of the stop record is shown in Figure 21. Only the stop bit needs to be ‘1’
in order to form a stop record, all other bits are ignored. An unprogrammed location in
UTEST Flash is interpreted as a stop record.
Figure 21. DCF stop record
0:31
32:62
63
Reserved
Reserved
1
If n data records are to be stored in UTEST, the data structure must be as shown in
Table 91.
Table 91. Series of DCF records in UTEST Flash memory
ADDR offset
DATA
0x00
0x05AA55AF
0x04
0x00000000
0x08
0x0C
WDATA[31:0]
CS[14:0]
ADDR[16:2]
0x10
0x14
PRTY
STOP=0
PRTY
STOP=0
WDATA[31:0]
CS[14:0]
ADDR[16:2]
...
...
8n + 0x0
Reserved
8n + 0x4
Reserved
8(n+1) + 0x0
STOP=1
—
8(n+1) + 0x4
Caution:
STOP=0
There must never be an unprogrammed record in the DCF data structure, as it is interpreted
as a stop record and subsequent records are ignored.
Records programmed in several sessions are shown in Figure 22, appending new records
to the end of the list each time.
186/2075
RM0483 Rev 5
RM0483
Device configuration format (DCF) records
Figure 22. Appending DCF records
0xFFFF FFFF FFFF FFFF
Start Record
Start Record
0xFFFF FFFF FFFF FFFF
Data Record - CS1, Ad = 0
Data Record - CS1, Ad = 0
0xFFFF FFFF FFFF FFFF
Data Record - CS2, Ad = 0
Data Record - CS2, Ad = 0
0xFFFF FFFF FFFF FFFF
Data Record - CS0, Ad = 0
Data Record - CS0, Ad = 0
0xFFFF FFFF FFFF FFFF
0xFFFF FFFF FFFF FFFF
Data Record - CS2, Ad = 0
0xFFFF FFFF FFFF FFFF
0xFFFF FFFF FFFF FFFF
0xFFFF FFFF FFFF FFFF
0xFFFF FFFF FFFF FFFF
0xFFFF FFFF FFFF FFFF
0xFFFF FFFF FFFF FFFF
0xFFFF FFFF FFFF FFFF
0xFFFF FFFF FFFF FFFF
0xFFFF FFFF FFFF FFFF
Empty Flash
→ No action
Initial Programming
Extension
It is possible for several DCF Records to write to the same DCF client. The later record
usually overrides a DCF client value set by a previous record. However, not all DCF clients
allow overwrites; this depends on the DCF client implementation.
7.3.1
UTEST DCF records
UTEST DCF records are located in the UTEST Flash memory area (refer to UTEST Flash
memory map in the Memory map chapter). Some UTEST DCF records are programmed at
the factory and the user may add USER DCF records from the first unprogrammed location
following the factory programmed UTEST DCF records.
When programming UTEST DCF records, the records must start at the first address in the
UTEST Flash memory area and be continuous: one UTEST DCF record must immediately
follow the previous UTEST DCF record. An unprogrammed location in the UTEST Flash
memory area is interpreted by the SSCM as the end of the UTEST DCF records. When this
happens, the SSCM passes control of the boot sequence to the RCC module.
7.4
DCF client table
A list of DCF clients is shown in Table 92. Various attributes of the DCF clients are listed in
these tables:
•
DCF Chip Select [14:0]: the CS field is a 15-bit field with each bit acting as a module
select signal for the internal modules. Only one bit in this field must be set in a DCF
record.
•
DCF address [16:2]: the 15-bit ADDR field specifies an internal address for a DCF
client. These addresses are only used by the SSCM when interpreting DCF records
and writing data to specified modules.
•
DCF client description: the name of the DCF clients.
•
Reset value of DCF client: the reset value of DCF client before being written by the
SSCM with the associated DCF record.
•
IPS read: this column specifies whether or not a DCF client can be read by user
software after the release of reset.
•
DCF client special strategy: registers are designated as DCF clients if they need to be
written with a DCF record. Other features that must be designated for DCF clients
RM0483 Rev 5
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Device configuration format (DCF) records
RM0483
include different write strategies listed below. The following list defines the special
strategies:
•
–
None: no special DCF strategy is used.
–
Write Once: a DCF client can only be written once. The DCF client ignores
subsequent writes.
–
Triple Voted: DCF clients have three copies of the register. The SSCM writes to all
three registers in a single write cycle. The outputs of the three registers are
majority voted together to determine the correct data value. Triple voting allows for
‘bit-flip’ error tolerance without changing the DCF client output data.
–
Write 0 only: a bit in a DCF client can only be written from a logic 1 to a logic 0. An
attempt to write a logic 1 is ignored.
–
Write 1 only: a bit in a DCF client can only be written from a logic 0 to a logic 1. An
attempt to write a logic 0 is ignored.
DCF order dependency in Flash memory
DCF order dependency in Flash memory: this column details whether or not there are
special conditions on the location of a particular DCF record in Flash memory.
7.4.1
DCF client list
(1)
No
Triple
Voted+
chk_wr2+
wr_once
No
Triple
Voted+
0
write up to
4 times
0x00000000
No
Triple
Voted+
0
write up to
4 times
0x08000000
No
Triple
Voted+
wr_once
DCF
address
[9:2]
DCF client
description
Reset value
of DCF
client
(Binary)
DCF order dependency in
Flash
DCF
address
[16:10]
DCF client special strategy
DCF CS
[14:0]
IPS read direct access
Table 92. DCF client list
RCC
000_0001_0000_0000 0000000 00000000
Core Enable and LS
Configuration
000_0001_0000_0000 0000000 00000010
Core2 Vector Table
Offset
000_0001_0000_0000 0000000 00000011
Core1 User VTOR
Address DCF
000_0001_0000_0000 0000000 00000100
Core1 Alternate
Configuration DCF
000_0001_0000_0000 0000000
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00000101Reserved
00001111
RM0483 Rev 5
0x00000000
0x00000000
0
0
RM0483
Device configuration format (DCF) records
(1)
DCF client
description
Reset value
of DCF
client
RESET_CFG DCF
0x00001000
No
Triple
Voted
DCF
address
[9:2]
(Binary)
000_0001_0000_0000 0000000 00010000
000_0001_0000_0000 0000000
DCF order dependency in
Flash
DCF
address
[16:10]
DCF client special strategy
DCF CS
[14:0]
IPS read direct access
Table 92. DCF client list (continued)
0
00010001Reserved
00011111
NIC and System configuration
000_0010_0000_0000 0000000 00100000
AXI_INIx_READ_
QOS_DCF0
0x20000000
No
Triple
Voted+
wr_once
000_0010_0000_0000 0000000 00100001
AXI_INIx_READ_
QOS_DCF1
0x00001111
No
Triple
Voted+
wr_once
000_0010_0000_0000 0000000
00100010Reserved
00100011
000_0010_0000_0000 0000000 00100100
AXI_INIx_WRITE_
QOS_DCF0
0x20000000
No
Triple
Voted+
wr_once
000_0010_0000_0000 0000000 00100101
AXI_INIx_WRITE_
QOS_DCF1
0x00001111
No
Triple
Voted+
wr_once
000_0010_0000_0000 0000000 00100110
AXI_WDG
0x00FFFFFF No
Triple
Voted+
wr_once
000_0010_0000_0000 0000000 00100111
REG_HWLOCK
0x00000000
Triple
Voted+
wr_once
000_0010_0000_0000 0000000
No
00101000Reserved
11111111
RM0483 Rev 5
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Device configuration format (DCF) records
RM0483
(1)
DCF
address
[9:2]
DCF client
description
Reset value
of DCF
client
(Binary)
DCF order dependency in
Flash
DCF
address
[16:10]
DCF client special strategy
DCF CS
[14:0]
IPS read direct access
Table 92. DCF client list (continued)
STCU(2)
000_0000_0000_0100 0000000 00000010
STCU_SKC
0x00000000
yes None
First
Record
among
STCU,
Key1/Ke
y2 dcf
record
sequenc
e; Write
Key2
every
(1024-8)
clock
edges
000_0000_0000_0100 0000000 00000000
STCU_RUN
0x00000000
yes None
None
000_0000_0000_0100 0000000 00000100
STCU_CFG
0x00000000
yes None
None
000_0000_0000_0100 0000000 00000101
STCU_RUN_DELAY
0x00000000
yes None
None
000_0000_0000_0100 0000000 00000110
STCU_PLL_CFG
0x00000000
yes None
None
000_0000_0000_0100 0000000 00001111
STCU_WDG
0x0000FFFF
yes None
None
000_0000_0000_0100 0000000 00010010
STCU_CRCE
0x00000000
yes None
None
000_0000_0000_0100 0000000 00010101
STCU_ERR_FM
0x00000000
yes None
None
000_0000_0000_0100 0000010 00010001
STCU_MB0_UFM0[31
0x00000000
:0]
yes None
None
000_0000_0000_0100 0000010 00010010
STCU_MB0_UFM1[31
0x00000000
:0]
yes None
None
000_0000_0000_0100 0000001 10000001
STCU_MB0_TM
0x00000000
yes None
None
000_0000_0000_0100 0001011 11100100
STCU_CB_UFM
0x00000000
yes None
None
000_0000_0000_0100 0001100 00010000
STCU_MBIST0_PTR
0x00000000
yes None
None
000_0000_0000_0100 0001100 00010001
STCU_MBIST1_PTR
0x00000000
yes None
None
000_0000_0000_0100 0001100 00010010
STCU_MBIST2_PTR
0x00000000
yes None
None
000_0000_0000_0100 0001100 00010011
STCU_MBIST3_PTR
0x00000000
yes None
None
190/2075
RM0483 Rev 5
RM0483
Device configuration format (DCF) records
Table 92. DCF client list (continued)
Reset value
of DCF
client
IPS read direct access
DCF client special strategy
DCF order dependency in
Flash
DCF
address
[16:10]
DCF client
description
000_0000_0000_0100 0001100 00010100
STCU_MBIST4_PTR
0x00000000
yes None
None
000_0000_0000_0100 0001100 00010101
STCU_MBIST5_PTR
0x00000000
yes None
None
000_0000_0000_0100 0001100 00010110
STCU_MBIST6_PTR
0x00000000
yes None
None
000_0000_0000_0100 0001100 00010111
STCU_MBIST7_PTR
0x00000000
yes None
None
000_0000_0000_0100 0001100 00011000
STCU_MBIST8_PTR
0x00000000
yes None
None
000_0000_0000_0100 0001100 00011001
STCU_MBIST9_PTR
0x00000000
yes None
None
000_0000_0000_0100 0001100 00011010
STCU_MBIST10_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00011011
STCU_MBIST11_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00011100
STCU_MBIST12_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00011101
STCU_MBIST13_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00011110
STCU_MBIST14_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00011111
STCU_MBIST15_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00100000
STCU_MBIST16_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00100001
STCU_MBIST17_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00100010
STCU_MBIST18_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00100011
STCU_MBIST19_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00100100
STCU_MBIST20_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00100101
STCU_MBIST21_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00100110
STCU_MBIST22_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00100111
STCU_MBIST23_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00101000
STCU_MBIST24_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00101001
STCU_MBIST25_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00101010
STCU_MBIST26_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00101011
STCU_MBIST27_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00101100
STCU_MBIST28_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00101101
STCU_MBIST29_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00101110
STCU_MBIST30_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00101111
STCU_MBIST31_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00110000
STCU_MBIST32_PTR 0x00000000
yes None
None
DCF CS
[14:0]
(1)
DCF
address
[9:2]
(Binary)
RM0483 Rev 5
191/2075
207
Device configuration format (DCF) records
RM0483
Table 92. DCF client list (continued)
DCF order dependency in
Flash
STCU_MBIST33_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00110010
STCU_MBIST34_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00110011
STCU_MBIST35_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00110100
STCU_MBIST36_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00110101
STCU_MBIST37_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00110110
STCU_MBIST38_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00110111
STCU_MBIST39_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00111000
STCU_MBIST40_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00111001
STCU_MBIST41_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00111010
STCU_MBIST42_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00111011
STCU_MBIST43_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00111100
STCU_MBIST44_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00111101
STCU_MBIST45_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00111110
STCU_MBIST46_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 00111111
STCU_MBIST47_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 01000000
STCU_MBIST48_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 01000001
STCU_MBIST49_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 01000010
STCU_MBIST50_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 01000011
STCU_MBIST51_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 01000100
STCU_MBIST52_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 01000101
STCU_MBIST53_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 01000110
STCU_MBIST54_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 01000111
STCU_MBIST55_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 01001000
STCU_MBIST56_PTR 0x00000000
yes None
None
000_0000_0000_0100 0001100 01001001
STCU_MBIST57_PTR 0x00000000
yes None
None
000_0000_0000_0100 0010000 00100000
STCU_CBIST0_PTR
0x00000001
yes None
None
000_0000_0000_0100 0010000 00100001
STCU_CBIST1_PTR
0x00000002
yes None
None
000_0000_0000_0100 0010000 00100010
STCU_CBIST2_PTR
0x00000003
yes None
None
000_0000_0000_0100 0010000 00100011
STCU_CBIST3_PTR
0x00000004
yes None
None
192/2075
RM0483 Rev 5
(1)
DCF
address
[9:2]
DCF client
description
Reset value
of DCF
client
(Binary)
IPS read direct access
DCF client special strategy
DCF
address
[16:10]
000_0000_0000_0100 0001100 00110001
DCF CS
[14:0]
RM0483
Device configuration format (DCF) records
Table 92. DCF client list (continued)
Reset value
of DCF
client
IPS read direct access
DCF client special strategy
DCF order dependency in
Flash
DCF
address
[16:10]
DCF client
description
000_0000_0000_0100 0010000 00100100
STCU_CBIST4_PTR
0x00000005
yes None
None
000_0000_0000_0100 0010000 00100101
STCU_CBIST5_PTR
0x00000006
yes None
None
000_0000_0000_0100 0010000 00100110
STCU_CBIST6_PTR
0x00000007
yes None
None
000_0000_0000_0100 0010000 00100111
STCU_CBIST7_PTR
0x00000008
yes None
None
000_0000_0000_0100 0010000 00101000
STCU_CBIST8_PTR
0x00000009
yes None
None
000_0000_0000_0100 0010000 00101001
STCU_CBIST9_PTR
0x00000010
yes None
None
DCF CS
[14:0]
(1)
DCF
address
[9:2]
(Binary)
PASS
000_0000_0000_1000 0000000
00101000Reserved
00101011
000_0000_0000_1000 0000000 00101100
Censorship
0x0
Yes None
None
000_0000_0000_1000 0000000 00101101
Password Slot Access
0x0
Yes wr_once
None
0x0
Yes wr_once
None
0x1
Yes wr_once
None
000_0000_0000_1000 0000000
0010111000101111
000_0000_0000_1000 0000000 00110000
000_0000_0000_1000 0000000
Production Disable
00110001Reserved
00110111
000_0000_0000_1000 0000000 00111000
000_0000_0000_1000 0000000
Reserved
0011100100111111
Fuse Bypass Enable
Reserved
000_0000_0000_1000 0000000 01000000
LOCK0_PG0
0xFFFFFFFF No
None
None
000_0000_0000_1000 0000000 01000001
LOCK1_PG0
0xFFFFFFFF No
None
None
000_0000_0000_1000 0000000 01000010
LOCK2_PG0
0xFFFFFFFF No
None
None
000_0000_0000_1000 0000000 01000011
LOCK3_PG0
0xFFFFFFFF No
None
None
000_0000_0000_1000 0000000 01000100
LOCK0_PG1
0xFFFFFFFF No
None
None
000_0000_0000_1000 0000000 01000101
LOCK1_PG1
0xFFFFFFFF No
None
None
000_0000_0000_1000 0000000 01000110
LOCK2_PG1
0xFFFFFFFF No
None
None
000_0000_0000_1000 0000000 01000111
LOCK3_PG1
0xFFFFFFFF No
None
None
000_0000_0000_1000 0000000 01001000
LOCK0_PG2
0xFFFFFFFF No
None
None
000_0000_0000_1000 0000000 01001001
LOCK1_PG2
0xFFFFFFFF No
None
None
000_0000_0000_1000 0000000 01001010
LOCK2_PG2
0xFFFFFFFF No
None
None
RM0483 Rev 5
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Device configuration format (DCF) records
RM0483
Table 92. DCF client list (continued)
IPS read direct access
DCF client special strategy
DCF order dependency in
Flash
DCF
address
[16:10]
000_0000_0000_1000 0000000 01001011
LOCK3_PG2
0xFFFFFFFF No
None
None
000_0000_0000_1000 0000000 01001100
LOCK0_PG3
0xFFFFFFFF No
None
None
000_0000_0000_1000 0000000 01001101
LOCK1_PG3
0xFFFFFFFF No
None
None
000_0000_0000_1000 0000000 01001110
LOCK2_PG3
0xFFFFFFFF No
None
None
000_0000_0000_1000 0000000 01001111
LOCK3_PG3
0xFFFFFFFF No
None
None
0xFFFFFFFF No
wr_once+
wr0_only
None
DCF CS
[14:0]
(1)
DCF
address
[9:2]
DCF client
description
Reset value
of DCF
client
(Binary)
000_0000_0000_1000 0000000
01001100Reserved
11111111
Tamper Detect
000_0000_0001_0000 0000000 00000000
000_0000_0001_0000 0000000
Diary Base Address
00000001Reserved
00000111
000_0000_0001_0000 0000000 00001000
OTP_EN0
0x00000000
No
Triple
Voted+
wr1_only
None
000_0000_0001_0000 0000000 00001001
OTP_EN1
0x00000000
No
Triple
Voted+
wr1_only
None
000_0000_0001_0000 0000000 00001010
OTP_EN2
0x00000000
No
Triple
Voted+
wr1_only
None
000_0000_0001_0000 0000000 00001011
OTP_EN3
0x00000000
No
Triple
Voted+
wr1_only
None
000_0000_0001_0000 0000000
00001100Reserved
00010011
000_0000_0001_0000 0000000 00010100
TDR0_LOCK0
0x00000000
No
wr_once+
wr1_only
None
000_0000_0001_0000 0000000 00010101
TDR0_LOCK1
0x00000000
No
wr_once+
wr1_only
None
000_0000_0001_0000 0000000 00010110
TDR0_LOCK2
0x00000000
No
wr_once+
wr1_only
None
000_0000_0001_0000 0000000 00010111
TDR0_LOCK3
0x00000000
No
wr_once+
wr1_only
None
194/2075
RM0483 Rev 5
RM0483
Device configuration format (DCF) records
Table 92. DCF client list (continued)
IPS read direct access
DCF client special strategy
DCF order dependency in
Flash
DCF
address
[16:10]
000_0000_0001_0000 0000000 00011000
TDR1_LOCK0
0x00000000
No
wr_once+
wr1_only
None
000_0000_0001_0000 0000000 00011001
TDR1_LOCK1
0x00000000
No
wr_once+
wr1_only
None
000_0000_0001_0000 0000000 00011010
TDR1_LOCK2
0x00000000
No
wr_once+
wr1_only
None
000_0000_0001_0000 0000000 00011011
TDR1_LOCK3
0x00000000
No
wr_once+
wr1_only
None
000_0000_0001_0000 0000000 00011100
TDR2_LOCK0
0x00000000
No
wr_once+
wr1_only
None
000_0000_0001_0000 0000000 00011101
TDR2_LOCK1
0x00000000
No
wr_once+
wr1_only
None
000_0000_0001_0000 0000000 00011110
TDR2_LOCK2
0x00000000
No
wr_once+
wr1_only
None
000_0000_0001_0000 0000000 00011111
TDR2_LOCK3
0x00000000
No
wr_once+
wr1_only
None
000_0000_0001_0000 0000000 00100000
TDR3_LOCK0
0x00000000
No
wr_once+
wr1_only
None
000_0000_0001_0000 0000000 00100001
TDR3_LOCK1
0x00000000
No
wr_once+
wr1_only
None
000_0000_0001_0000 0000000 00100010
TDR3_LOCK2
0x00000000
No
wr_once+
wr1_only
None
000_0000_0001_0000 0000000 00100011
TDR3_LOCK3
0x00000000
No
wr_once+
wr1_only
None
000_0000_0001_0000 0000000 00100100
TDR4_LOCK0
0x00000000
No
wr_once+
wr1_only
None
000_0000_0001_0000 0000000 00100101
TDR4_LOCK1
0x00000000
No
wr_once+
wr1_only
None
000_0000_0001_0000 0000000 00100110
TDR4_LOCK2
0x00000000
No
wr_once+
wr1_only
None
000_0000_0001_0000 0000000 00100111
TDR4_LOCK3
0x00000000
No
wr_once+
wr1_only
None
000_0000_0001_0000 0000000 00101000
TDR5_LOCK0
0x00000000
No
wr_once+
wr1_only
None
DCF CS
[14:0]
(1)
DCF
address
[9:2]
DCF client
description
Reset value
of DCF
client
(Binary)
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Device configuration format (DCF) records
RM0483
Table 92. DCF client list (continued)
IPS read direct access
DCF client special strategy
DCF order dependency in
Flash
DCF
address
[16:10]
000_0000_0001_0000 0000000 00101001
TDR5_LOCK1
0x00000000
No
wr_once+
wr1_only
None
000_0000_0001_0000 0000000 00101010
TDR5_LOCK2
0x00000000
No
wr_once+
wr1_only
None
000_0000_0001_0000 0000000 00101011
TDR5_LOCK3
0x00000000
No
wr_once+
wr1_only
None
0x00010C76
No
Triple
Voted
None
0x0000000E
No
None
None
0x00000000
No
Triple
Voted
None
DCF CS
[14:0]
(1)
DCF
address
[9:2]
DCF client
description
Reset value
of DCF
client
(Binary)
000_0000_0001_0000 0000000
00101100Reserved
11111111
MISCELLANEOUS
000_0000_1000_0000 0000000 00000000
000_0000_1000_0000 0000000
00000010Reserved
00000110
000_0000_1000_0000 0000000 00000111
000_0000_1000_0000 0000000
000_0000_1000_0000
JTAG Pin Config
00001000Reserved
01000111
000_0000_1000_0000 0000000 01001001
000_0000_1000_0000 0000000
UTEST Miscellaneous
PMC REE_BUS
01001011Reserved
11111110
0000001 00000000Reserved
-1111111 11111111
SOFT DCF CLIENTS (BAF)
100_0000_0000_0000 0000000
00000000Reserved
11111111
100_0000_0000_0000 0000001
00000000Reserved
11111111
100_0000_0000_0000 0000010 00000000
ADDR
None
100_0000_0000_0000 0000010 00000001
DATA32
None
100_0000_0000_0000 0000010 00000010
DATA16
None
100_0000_0000_0000 0000010 00000011
DATA8
None
100_0000_0000_0000 0000010
196/2075
00000100Reserved
00001111
RM0483 Rev 5
RM0483
Device configuration format (DCF) records
Reset value
of DCF
client
DCF client
description
(Binary)
DCF order dependency in
Flash
(1)
DCF
address
[9:2]
IPS read direct access
DCF
address
[16:10]
DCF CS
[14:0]
DCF client special strategy
Table 92. DCF client list (continued)
100_0000_0000_0000 0000010 00010000
CALLBACK
None
100_0000_0000_0000 0000010 00010001
USER_SERIAL_
BOOT
None
100_0000_0000_0000 0000010
100_0000_0000_0000
00010001Reserved
11111111
0000011 00000000Reserved
-1111111 11111111
1. DCF programming must start from address 0x00400208.
2. The STCU DCF description is aligned with the register description in the STCU3 chapter.
7.4.2
Miscellaneous DCF records
28
27
26
25
22
21
20
19
7
6
5
4
3
XOSC_EXT_CLOAD
29
XOSC_EN
30
IWDG1_HW
31
Access: DCF Client
IWDG2_HW
Offset: 00000000
24
23
18
17
16
Reserved
XOSC_IBIAS_SEL[1:0]
W
Reserved
Reserved
R
2
1
15
14
13
Reserved
XOSC_ALC_DIS
Reserved
Reset Value is chip-specific; refer to Table 92: DCF client list.
12
11
10
9
8
0
Reserved
XOSC_LOAD_
CAP_SEL[4:0]
Reserved
XOSC_FREQ_SEL[1:0]
W
Reserved
R
Reset Value is chip-specific; refer to Table 92: DCF client list.
Figure 23. UTEST Miscellaneous DCF Client
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Device configuration format (DCF) records
RM0483
Table 93. UTEST Miscellaneous DCF Client field descriptions
Field
29
IWDG2_HW
1: IWDG2 is enabled by HW after reset
0: IWDG2 is disabled by HW after reset (SW to enable it)
28
IWDG1_HW
1: IWDG1 is enabled by HW after reset
0: IWDG1 is disabled by HW after reset (SW to enable it)
17:16
XOSC_IBIAS_SEL[1:0]
14
XOSC_ALC_DIS
11:10
XOSC_FREQ_SEL[1:0]
7
XOSC_EN
6
XOSC_EXT_CLOAD
5:1
XOSC_LOAD_CAP_SEL[0:4]
198/2075
Description
Allows to change oscillation margin (default “10”) - User to keep default value of
“10”
Active high to disable Automatic Level Controller
This selects the different frequency settings of XOSC.
00 4 MHz – 10 MHz
01 10 MHz – 20 MHz
10 20 MHz – 30 MHz
11 30 MHz – 40 MHz
Enable XOSC
0 XOSC disabled
1 XOSC enabled
XOSC EXT CLOAD
0 Selects XOSC internal cap (recommended for 20 MHz – 40 MHz operation)
1 Selects XOSC external cap (recommended for 4 MHz – 20 MHz operation)
Note: It is always recommended to verify the required size of the capacitances
with the crystal supplier.
XOSC LOAD CAP SEL [0:4]
Five trim bits program the load capacitance. The formula to calculate the
capacitance offered is Ctot = Cfix+n.Cu
where:
Fixed Capacitance Cfix = 11.0pF (variation ±15%)
Unit capacitance Cu = 0.49pF (variation ±15%)
n = load_cap_sel[4] * 24 + load_cap_sel[3] * 23 + load_cap_sel[2] * 22 +
load_cap_sel[1] * 21 + load_cap_sel[0] * 20
RM0483 Rev 5
RM0483
Device configuration format (DCF) records
Offset: 00000111
31
Access: DCF Client
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
Reserved
W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
0
R
JTAG_PIN_CFG_ILS[1:0]
0
JTAG_PIN_TMS_SRE
Reset
Reserved
W
Reset
0
0
0
0
0
0
0
0
Figure 24. JTAG Pin Configuration
Table 94. JTAG Pin Configuration field descriptions
Field
Description
29
JTAG_PIN_CFG_HYSE
JTAG pins hysteresis
0 JTAG pins hysteresis not enabled.
1 JTAG pins hysteresis enabled.
Default: JTAG pins hysteresis not enabled.
30:31
JTAG_PIN_CFG_ILS
JTAG pins mode
00 JTAG pins configured for CMOS mode.
01 JTAG pins configured for AUTO mode.
10 JTAG pins configured for TTL mode.
11 JTAG pins configured for TTL mode.
Default: JTAG pins configured for TTL mode.
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207
Device configuration format (DCF) records
RM0483
Offset: 01001001
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HVD140_C
Reserved
LVD119_FL
LVD119_C
16
LVD290_C
17
LVD119_RC
18
LVD290_FL
19
UVD145_RC
R Reserved
20
LVD290_IO1
21
LVD119_DD
22
LVD290_IO0
23
LVD119_PLL0
24
LVD290_AS
25
LVD119_PLL1
26
LVD290_AD
27
LVD290_DACCMP
28
LVD290_OSC
29
UVD380_AS
30
UVD380_DACCMP
31
Access: DCF Client
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
W
Reset
R
Reserved
W
Reset
0
0
0
0
Figure 25. PMC_REE_BUS
Table 95. PMC_REE_BUS field descriptions
Field
200/2075
Description
0
LVD119_C
This bit defines whether an LVD assertion on the core low voltage supply
generates a system reset.
0: Reset event disabled
1: Reset event enabled
1
LVD119_FL
This bit defines whether an LVD assertion on the flash low voltage supply
generates a system reset.
0: Reset event disabled
1: Reset event enabled
3
HVD140_C
This bit defines whether an HVD assertion on the core low voltage supply
generates a system reset.
0: Reset event disabled
1: Reset event enabled
4
LVD290_C
This bit defines whether an LVD assertion on the core high voltage supply
generates a system reset.
0: Reset event disabled
1: Reset event enabled
5
LVD290_FL
This bit defines whether an LVD assertion on the flash low voltage supply
generates a system reset.
0: Reset event disabled
1: Reset event enabled
6
LVD290_IO1
This bit defines whether an LVD assertion on the I/O supply generates a system
reset.
0: Reset event disabled
1: Reset event enabled
RM0483 Rev 5
RM0483
Device configuration format (DCF) records
Table 95. PMC_REE_BUS field descriptions (continued)
Field
Description
7
LVD290_IO0
This bit defines whether an LVD assertion on the I/O supply generates a system
reset.
0: Reset event disabled
1: Reset event enabled
8
LVD290_AS
This bit defines whether an LVD assertion on the SAR ADCs supply generates a
system reset.
0: Reset event disabled
1: Reset event enabled
9
LVD290_AD
This bit defines whether an LVD assertion on the SD ADCs supply generates a
system reset.
0: Reset event disabled
1: Reset event enabled
21
LVD119_RC
This bit defines whether an LVD assertion on the IRCOSC supply generates a
system reset.
0: Reset event disabled
1: Reset event enabled
22
UVD145_RC
This bit defines whether an HVD assertion on the IRCOSC supply generates a
system reset.
0: Reset event disabled
1: Reset event enabled
23
LVD119_DD
This bit defines whether an LVD assertion on the HRTimers' DLL supply generates
a system reset.
0: Reset event disabled
1: Reset event enabled
24
LVD119_PLL0
This bit defines whether an LVD assertion on the PLL0 supply generates a system
reset.
0: Reset event disabled
1: Reset event enabled
25
LVD119_PLL1
This bit defines whether an LVD assertion on the PLL1 supply generates a system
reset.
0: Reset event disabled
1: Reset event enabled
This bit defines whether an LVD assertion on the DACs and Comparators supply
26
generates a system reset.
LVD290_DACC 0: Reset event disabled
MP
1: Reset event enabled
27
LVD290_OSC
This bit defines whether an LVD assertion on the XOSC supply generates a
system reset.
0: Reset event disabled
1: Reset event enabled
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207
Device configuration format (DCF) records
RM0483
Table 95. PMC_REE_BUS field descriptions (continued)
Field
Description
28
UVD380_AS
This bit defines whether an HVD assertion on the SAR-ADCs supply generates a
system reset.
0: Reset event disabled
1: Reset event enabled
This bit defines whether an HVD assertion on the DACs and Comparators supply
29
generates a system reset.
UVD380_DACC
0: Reset event disabled
MP
1: Reset event enabled
Offset: 000000000000000
31
30
29
Access: DCF Client
28
27
26
25
R
24
23
22
21
20
19
18
17
16
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FTMPL
Reset
eFE
W
0
0
0
0
0
0
1
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
Figure 26. Flash test mode protection
Table 96. Flash test mode protection field descriptions
Field
30
eFE
31
FTMPL
7.4.3
Description
0 Efuse system is disabled.
1 Efuse system is enabled.
Default: Efuse system is enabled.
0 FTMP is not locked.
1 FTMP is locked.
Default: FTMP is not locked.
RCC DCF records
Global System Configuration DCF
This DCF is used to configure:
202/2075
•
Cores to be started by hardware upon reset
•
Lockstep configuration of the cores and DMAs
•
Flash OTA mode
RM0483 Rev 5
RM0483
Device configuration format (DCF) records
Access: DCF Client
29
28
27
26
25
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
LS_CORE1_2
0
Reserved
Reserved
0
Reserved
Reset
23
CORE2_EN
Reserved
Reset
24
LS_DMA
30
OTA_EN
31
0
0
0
0
0
0
0
0
Reserved
0
0
0
0
Figure 27. Global System Configuration
Table 97. Global System Configuration field descriptions
Field
31:25
24
OTA_EN
23:17
16
LS_DMA
15:9
8
LS_CORE1_2
7:2
1
CORE2_EN
0
Description
Reserved
Enables OTA on flash
0: OTA disabled (default)
1: OTA enabled
Reserved
Enables lockstep replicas for DMA1, DMA2 and DMAMUX
0: Lockstep for DMA1, DMA2 and DMAMUX disabled (default)
1: Lockstep for DMA1, DMA2 and DMAMUX enabled
Reserved
Enables lockstep configuration for Core1 and 2
0: Lockstep for Core1 and Core2 disabled - Split Configuration (default)
1: Lockstep for Core1 and Core2 enabled - Lock configuration
Note: : Only C1_VTOR DCF has to be considered as starting address
Reserved
Core2 enabled
0: Core2 is not enabled
1: Core2 is enabled by HW and started by using C2_VTOR DCF data
Reserved
Core2 Vector Table Offset DCF
The C2_VTOR DCF configures the address of vector table of the core2 after reset release.
RM0483 Rev 5
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207
Device configuration format (DCF) records
RM0483
Access: DCF Client
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
3
2
1
0
0
0
0
VTOR_INIT[31:16]
Reset(1)
0
0
0
15
14
13
R
0
0
0
0
0
0
0
0
0
12
11
10
9
8
7
6
5
4
VTOR_INIT[15_7]
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 28. Core2 Vector Table Offset
1. Alias for ITCM of Cortex®-M7
Table 98. Core2 Vector Table Offset field descriptions
Field
Description
31:7
VTOR_INIT
Address of vector table of the M7 Core2 after reset release.
6:0
Reserved
The associated DCF client is triple voted and can be overwritten up to 4 times, allowing to
update the VTOR_INIT address for a maximum of 4 times.
Core1 User VTOR Address DCF
This DCF defines the address of the vector table of the core1 after BAF is executed. The
DCF content is mirrored as the reset value of the RCC register C1_VTOR_ADDR_REG.
Access: DCF Client
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
3
2
1
0
0
0
0
C1_VTOR_ADDR[31:16]
Reset
0
0
0
15
14
13
0
0
0
0
0
0
0
0
0
12
11
10
9
8
7
6
5
4
C1_VTOR_ADDR[15_7]
Reset
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
Figure 29. Core1 User VTOR Address
Table 99. Core1 User VTOR Address field description
Field
31:7
C1_VTOR_ADDR
6:0
Description
Address of core1 vector table for user application.
Reserved
The associated DCF client is triple voted and can be overwritten up to 4 times, allowing to
update the Core1 Application address for a maximum of 4 times.
204/2075
RM0483 Rev 5
RM0483
Device configuration format (DCF) records
Core1 Alternate Configuration DCF
In case the User wants to bypass the BAF execution, this DCF has to be programmed. The
Boot CPU starts execution from this user defined address.
Access: DCF Client
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
C1_ALT_VTOR_INIT[31:16]
Reset(1)
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C1_ALT_VTOR_INIT[15:7]
Reset
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
BAF
_BY
P
0
0
0
Figure 30. Core1 Alternate Configuration
1. Flash1 start address
Table 100. Core1 Alternate Configuration field description
Field
31:7
C1_ALT_VTOR_INIT
6:1
0
BAF_BYP
Description
Address of vector table of the Core1 if BAF_BYP bit is programmed.
Reserved
0: BAF is not bypassed
1: BAF is bypassed and the new address for boot core start is given by
C1_ALT_VTOR_INIT field
This DCF is mirrored as reset value of RCC register C1_VTOR_INIT register when
BAF_BYP bit is set to 1.
This DCF is write-once, triple voted and checked at second write during functional reset.
RESET_CFG_DCF
This DCF configures the activation of the pull-down of the RESETN pad, otherwise the pullup/pull-down configuration is regulated by the life cycle.
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Device configuration format (DCF) records
RM0483
Access: DCF Client
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
RESN_PDOWN_EN
Reset
Reserved
Reset
0
0
0
0
0
0
0
0
0
Figure 31. RESET_CFG DCF
Table 101. RESET_CFG DCF field description
Field
Description
31:1
Reserved
0: This bit has to be programmed to 0 to make effective the enable of
the Pull down on RESETN PAD basing on Life Cycle
1: No effect
0
RESN_PDOWN_EN
REG_HWLOCK_DCF
Access: DCF Client
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
HWLOCK3
Reserved
HWLOCK2
Reserved
HWLOCK1
Reset
HWLOCK4
Reserved
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reset
0
0
0
0
0
Figure 32. REG_HWLOCK_DCF
Table 102. REG_HWLOCK_DCF field description
Field
31:7
6
HWLOCK4
5
206/2075
Description
Reserved
0: HW Lock register protection for APB Bridge2 not enabled
1: HW Lock register protection for APB Bridge2 enabled
Reserved
RM0483 Rev 5
RM0483
Device configuration format (DCF) records
Table 102. REG_HWLOCK_DCF field description (continued)
Field
4
HWLOCK3
3
2
HWLOCK2
1
0
HWLOCK1
Description
0: HW Lock register protection for APB Bridge1 not enabled
1: HW Lock register protection for APB Bridge1 enabled
Reserved
0: HW Lock register protection for AHB Bridge2 not enabled
1: HW Lock register protection for AHB Bridge2 enabled
Reserved
0: HW Lock register protection for AHB Bridge1 not enabled
1: HW Lock register protection for AHB Bridge1 enabled
RM0483 Rev 5
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207
Power management
RM0483
8
Power management
8.1
Overview
SR5E1x microcontrollers include a robust power management infrastructure that enables
applications to monitor internal voltages for high- and low-voltage conditions. The
monitoring capability is also used to ensure supply voltages and internal voltages are within
the required ranges before the microcontroller can leave reset. This chapter gives an
overview of the built-in power management features.
The power management infrastructure comprises the following modules:
•
Reset and Clock Controller (RCC)
•
Power Management Controller (PMC)
•
Power Management Controller Digital Interface (PMC_Dig)
This chapter describes these modules in brief. For complete details, see the respective
module chapters.
The RCC generates reference clocks for all the chip blocks. It works in conjunction with
internal clock gating logic to implement low power modes. RCC controls chip operational
modes and mode transition sequences. It also contains configuration, control and status
registers accessible for the application.
The PMC module contains all the internal voltage regulator and monitors of the device: refer
to Section 8.1.3: Power management controller overview.
The PMC_Dig module is the digital interface of the PMC, and contains all the registers to
control the PMC during reset and power mode changes.
8.1.1
Power management framework
The power management framework supports a variety of configuration options. See
Figure 33: Device power management framework for more details. SR5E1x implements a
unique core voltage power domain. There are no separate functional power domains.
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Figure 33. Device power management framework
VSS
VDD_HV_IO
(HV power-bar)
VDD_HV_IO
VDD_HV_IO
VDD_HV_FLA
SMPS
NMOS
VDD_LV
VDD_HV_IO
SMPS
VLX
SMPS
PMOS
VDD_HV_IO
(HV power-bar)
VDD_HV_IO
SMPS
HSM
HSM-RAMs
VDD_HV_IO
PMU
FLASH
VDD_LV
(LV power-bar)
Peripherals
APB-Low
Bridges
VDD_LV
(LV power-bar)
SMPU
TEMP
SENSOR
ADC-SDs (x2)
HV_REFL_SD
HV_REFH_SAR
Buffered-DACs SAR
(x2)
Bias
VDD_HV_SAR
HV_REFH_
DAC_COMP
SD COMP
Bias Bias
Fast-DACs (x8)
HV_REFL_
DAC_COMP
COMPARATORs (x8)
VDD_HV_SD_
DAC_COMP
VSS
VDD_HV_IO
8.1.2
NIC
DMAs (x2)
ADC-SARs (x5)
HV_REFL_SAR
Peripherals
APB-High
VDD_HV_IO
Core1
Core2
AnalogSS
Digital
interfaces
CORE
RAMs
VDD_LV
(LV power-bar)
Peripherals
AHB-Low
PLL1
Peripherals
AHB-High
VDD_HV_IO
PLL2
XOSC
IRCOSC16M
VDD_HV_IO
VDD_HV_OSC
VSS_HV_OSC
VDD_LV
(LV power-bar)
VDD_HV_IO
Delay (x6)
DLL1
Delay (x6)
HV_REFH_SD
System
RAMs
RCC
VDD_HV_IO
VSS
Delay (x6)
DLL2
Delay (x6)
VDD_HV_IO
VDD_HV_IO
VSS
Power management supply description
The following table provides an overview of the PMC supply signals.
Table 103. Device power management controller external signals
Name
Type
Description
HV_REFH_SD
Reference
Voltage reference of ADC Σ/Δ module
HV_REFL_SD
Reference
Ground reference of ADC Σ/Δ modules
HV_REFH_SAR
Reference
Voltage reference of ADC SAR module
HV_REFL_SAR
Reference
Ground reference of ADC SAR modules
HV_REFH_DAC_COMP
Reference
Voltage reference of all Fast-DAC, for all Buffered-DAC and for all
COMPARATOR modules
HV_REFL_DAC_COMP
Reference
Ground reference of all Fast-DAC, for all Buffered-DAC and for all
COMPARATOR modules
VDD_HV_SD_DAC_COMP
Supply
High Voltage power supply for all ADC-SD, DAC and COPARATOR
modules
VDD_HV_SAR
Supply
High voltage supply for the ADC-SAR modules
VDD_HV_FLA
Supply
Supply pin for Flash
VDD_HV_IO
Supply
High voltage power supply for I/O and for PMU/SMPS
VDD_LV
Supply
Low voltage power supply for the core area generated by internal
regulator by SMPS circuitary and external FET
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Table 103. Device power management controller external signals (continued)
Name
Type
Description
VSS
Ground
Ground supply for the device / I/O. This is covering both VSS_LV and
VSS_HV (exposed pad device)
VDD_HV_OSC
Supply
High Voltage power supply for Oscillator
VSS_HV_OSC
Supply
Ground supply for Oscillator
Caution:
There are constraints on some input voltages relative to other input voltages. Please refer to
the device data sheet for detailed information.
8.1.3
Power management controller overview
The power management controller unit (PMC) contains the device internal voltage regulator
and all the voltage monitors. The power management unit manages the power requirements
of the device by generating and monitoring regulated voltage required for the correct
operation of the device.
The power management unit performs many functions, like:
•
Correct power up /power down of the device,
•
Generate the regulated voltage (1.28 V) for core by switching regulator, which is part of
the PMC IP,
•
Monitor multiple supplies.
Refer to the data sheet for the electrical characteristics of the regulators and the monitors
and the list of external components required. The list of functionalities of the monitors is
described further in this chapter.
The following figure describes the top level block diagram of power management unit.
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Figure 34. Power management controller block diagram overview
VDDREG
VDD1P2D
from SoC
LV2HV
monitors
digital outputs
monitpr o/ps
Ref1
Regulator
gate control
to ballasts
different references
regulator ref.
To SoC
HV2LV
monitors
D ig ita l H V
Reference
module
Ref2
sense i/p
vddreg
Monitors
T
monitors outputs
TESTMODE
F
to analog
& digital
channel
Temperature
Tsense
Threshold
por031 o/p
A
por031
POR_vddreg
R
VDD1P2D
Smps
VDD1P2D
D
POR_vddreg o/p
RC Regulator
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Figure 35. Voltage Monitor Coverage
VOLTAGE [V]
VDD_HV_IOx
VDD_HV_ADV
(SD ADC)
VDD_HV_FLA
POR
MVD
LVD
UVD
MVD
LVD
UVD
UVD380_C
UVD380_IO0
LVD
VDD_HV_ADV
(SAR ADC)
LVD
UVD380_FL
VDD_HV_DACCMP
UVD
LVD
UVD
VDD_HV_OSC
LVD
UVD380_DACCMP
UVD380_AS
HV Supply Range
LVD290_C
LVD290_IO0
LVD290_IO1
LVD290_FL
MVD270_C
POR200_C
LVD290_AD
LVD290_AS
LVD290_DACCMP
LVD290_OSC
MVD270_FL
MVD240T_C
MVD240_SMPS
VDD_LV (Core logic)
VDD_LV Others
(PLL0, PLL1, DLL-DelayLane, RC)
VDD_LV_FLA (Flash)
POR
MVD
LVD
HVD
UVD
MVD
LVD
UVD
LVD
UVD145_C
UVD
UVD145_RC
HVD140_C
LV Supply Range
LVD119_FL
LVD119C
MVD114_C
LVD119_PLL0/1/DD/RC
MVD114_FL
MVD102T_C
POR031_C
Note:
See Table 104: Voltage monitors description for VDs descriptions
Voltage levels for all VDs are given in the data sheet
VDD_HV_IO is redundant, ensuring that single pin failure does not prevent device from
functioning correctly. Full specification may not be guaranteed.
VDD_LV is redundant, ensuring that single pin failure does not prevent the device from
functioning correctly.
8.2
Flash power requirements
During start-up operation, the flash module operates from an untrimmed regulator, which
has a slightly larger variation than the ideal case. During this start-up phase, the flash can
still be read, but it must be read at a slower rate. While operating in this slower read mode,
the flash can operate at a much reduced voltage.
Following completion of the start-up phase the regulator is in its trimmed condition, and
subsequently the flash module reference current has also been trimmed. Therefore when
entering normal operation the flash can be read in the normal access manner and support
the full flash specification.
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8.3
Power management
Device trimming
During the initialization phase the device defaults to a pre-determined state for each of the
LVDs, HVDs and the internal regulators. As the flash becomes available the differential read
process allows the trimmed data to be available for trimming the internal LVDs, HVDs and
regulators.
Please refer to Section 8.5: Power sequence for further details.
8.4
Supply monitoring (POR and LVDs)
The function of the POR and LVD circuits is to hold the device in reset regardless of how
slow the supply voltage rise is, until the point at which the POR and LVDs are released.
The POR and LVD circuits function correctly even if the input voltage is non monotonic.
8.4.1
Power-on reset (POR)
The PMC implements two internal power-on reset circuits:
•
POR031_C monitors the voltage on the Low Voltage input supply. It is monitoring the
VDD_LV pin. The POR031_C asserts a reset when the input supply is below the defined
values.
•
POR200_C monitors the voltage on the High Voltage input supply. It is monitoring the
VDD_HV_IO pin. The POR trip point is high enough to make sure all the LVD circuits are
functional.
See Chapter 6: Reset and Boot for RESETn pin functionality.
8.4.2
Behavior of device LVD / HVD
Although there is an option to disable the LVD and HVD following reset (see Section 8.4.3:
Voltage detections (MVDs, LVDs, HVDs, UVDs)), they are capable of being used in a
‘monitor’ only mode and also capable of generating a safe / interrupt event. The diagram in
the following figure illustrates the behavior of these internal LVD / HVD circuits during the
power on phase, through into device initialization and subsequently in ‘normal’ run /
operating mode.
The LVDs/HVDs can also be configured after device initialization preventing reset to happen
when supply crosses the LVD threshold, effectively providing a higher voltage operating
range. It is the responsibility of the application to ensure that the device remains in the
functional range.
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Figure 36. Internal LVD and HVD in configuration example during power-up
High
Voltage
Supply
LVD119 assertion point
Low
Voltage
Supply
MVD114 de-assertion point
LVD119 threshold
MVD114 threshold
8.4.3
Voltage detections (MVDs, LVDs, HVDs, UVDs)
The internal LVD circuits monitor when the voltage on the corresponding supply is below the
defined values and either assert a reset or an interrupt. The LVDs also support hysteresis in
the falling and rising trip points.
8.4.3.1
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LVD and HVD implementation
•
All LVDs and HVDs are capable of generating either an RCC or FCCU event (or both).
•
All LVDs and HVD configured for reset generation can cause functional or destructive
reset. RCC PHASE0 is not exited until all destructive reset conditions are cleared.
•
The appropriate bits in the PMC registers are set by LVD and HVD events. Please refer
to Power management controller digital interface chapter (PMC_Dig).
•
The LVDs and HVDs control is protected by the register protection scheme. Therefore
it is configurable as long as the scheme is followed. Please refer to Section 5.8.6:
REG_PROT configuration.
•
SR5E1x implements REE (Reset event enable) DCF records to allow to associate
“configurable” LVDs/HVDs to a RESET event. This is a write mechanism managed by
SSCM during device initialization. When RESET event is selected through REE DCF
record, it cannot be changed until next RESET event. When RESET event is not
selected through REE DCF record, LVDs/HVDs trigger event default to FCCU event.
Please refer to Chapter 7: Device configuration format (DCF) records.
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Note:
Power management
The full list of voltage monitors is provided in Table 104: Voltage monitors description. The
functionality and configurability are reported in Figure 37: Voltage monitors functionality and
Table 105: Voltage monitors configurability.
•
Note:
When the LVD or the HVD is enabled for destructive reset generation and a
subsequent trigger event is detected, the external RESETn pin is driven low.
MVDs/UVDs are not configurable
Table 104. Voltage monitors description
Monitor name
Voltage
reference
number
Description
Monitor sensing
POWER MANAGEMENT UNIT VOLTAGE MONITORS: LOW VOLTAGE SUPPLIES
POR031_C
VD0
Low voltage supply power-on reset voltage
monitor
MVD102T_C
VD1
LV supply core minimum voltage detector
VDD_LV
MVD114_C
VD2
LV supply core low range minimum voltage
detector
VDD_LV
MVD114_FA
VD2
LV supply flash minimum voltage detector
VDD_LV_FLA
LVD119_C
VD3
LV supply core low voltage detector
VDD_LV
LVD119_FL
VD3
LV supply flash low voltage detector
VDD_LV_FLA
LVD119_PLL0
VD3
LV supply PLL0 low voltage detector
VDD_LV_PLL0
LVD119_PLL1
VD3
LV supply PLL1 low voltage detector
VDD_LV_PLL1
LVD119_DD
VD3
LV supply DLL & DelayLanes low voltage
detector
VDD_LV_DD
LVD119_RC
VD3
LV supply RCOSC low voltage detector
VDD_LV
HVD140_C
VD6
LV supply core high voltage detector
VDD_LV
UVD145_C
VD7
LV supply core upper voltage detector
VDD_LV
UVD145_RC
VD7
LV supply RCOSC upper voltage detector
VDD_LV
POWER MANAGEMENT UNIT VOLTAGE MONITORS: HIGH VOLTAGE SUPPLIES
POR200_C
VD8
High voltage supply power-on reset voltage
monitor
MVD240T_C
VD8
HV supply core minimum voltage monitor
VDD_HV_PMU
MVD240_SMPS
VD8
HV supply core minimum voltage monitor
VDD_HV_PMU
MVD270_C
VD10
HV supply core minimum voltage monitor
VDD_HV_PMU
MVD270_FL
VD10
HV supply flash minimum voltage monitor
VDD_HV_FLA
LVD290_C
VD11
HV supply core low voltage monitor
VDD_HV_PMU
LVD290_FL
VD11
HV supply flash low voltage monitor
VDD_HV_FLA
LVD290_AD
VD11
HV supply SD-ADC low voltage monitor
VDD_HV_SD
LVD290_AS
VD11
HV supply SAR-ADC low voltage monitor
VDD_HV_SAR
LVD290_DACCMP
VD11
HV supply DAC & COMP low voltage monitor
VDD_HV_DAC
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Table 104. Voltage monitors description (continued)
Monitor name
Voltage
reference
number
Description
Monitor sensing
LVD290_OSC
VD11
HV supply OSC low voltage monitor
VDD_HV_OSC
LVD290_IO1
VD11
HV supply I/O low voltage monitor
VDD_HV_IO1 segment
LVD290_IO0
VD11
HV supply I/O low voltage monitor
VDD_HV_IO0 segment
UVD380_C
VD15
HV supply core upper voltage monitor
VDD_HV_PMU
UVD380_FL
VD15
HV supply flash upper voltage monitor
VDD_HV_FLA
UVD380_IO0
VD15
HV supply I/O upper voltage monitor
VDD_HV_IO0 segment
UVD380_AS
VD15
HV supply SAR-ADC upper voltage monitor
VDD_HV_SAR
UVD380_DACCMP
VD15
HV supply DAC & COMP upper voltage monitor VDD_HV_DAC
The following figure provides the functionality of monitors depending on configuration.
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Voltage
Detector
Figure 37. Voltage monitors functionality
Power ON
exit
PH0D exit
PH2D to PH3D
Including trimming steps
PH1D
PH1F to PH3F
Run-time
VD disabling
UVD600_IF
UVD600_IJ
VD15
Test mode
Destructive Reset (can be masked via Test Mode only)
UVD600_FL
UVD600_C
LVD400_IF
LVD400_IJ
VD14
LVD400_AS
LVD400_AD
LVD400_IM
HVD400_IF
NA
VD13
Destructive Reset can be configured via DCF.
(If no DCF is programmed then no reset reaction occurs)
FCCU reaction is disabled.
Interrupt reaction is disabled.
HVD400_IJ
HVD400_C
Reset-, FCCU- and Interrupt-reaction
can be changed via PMUdig and FCCU
registers
Test mode or SW
LVD290_IF
LVD290_IJ
Trimming done
LVD290_AS
VD11
LVD290_AD
LVD290_FL
NA
LVD290_C
Destructive
Reset (can be
masked via Test
Mode only)
NA
MVD270_FL
VD10
Destructive Reset (can be masked via Test Mode only)
Test mode
Destructive Reset
NA
Destructive Reset (can be masked via Test Mode only)
Test mode
MVD270_C
VD8
POR200_C
UVD140_FL
VD7
UVD140_C
VD6
HVD134_C
(HSM)
NA
LVD100_FL
VD3
NA
LVD100_C
Destructive Reset
(can be masked
via Test Mode
only)
Destructive Reset can be configured via DCF.
(If no DCF is programmed then no reset reaction occurs)
FCCU reaction is disabled.
Interrupt reaction is disabled.
NA
Reset-, FCCU- and Interrupt-reaction
can be changed via PMUdig and FCCU
registers
Test mode or SW
MVD094_FA/FB
VD2
MVD094_C
Destructive Reset (can be masked via Test Mode only)
Test mode
Destructive Reset
NA
MVD082_B
VD1
MVD082T_C
VD0
POR031_C
The following table provides the monitor status depending on configuration.
Table 105. Voltage monitors configurability
Reset Event
Enable(1)
Reset Event
Select(1)
Event
Pending
Register(1)
Interrupt
Enable(1)
FCCU Event
Enable(1)
Reset Event
Enable
DCF(1)
MVDs
No
No
No
No
No
No
LVDs
Yes
Yes
Yes
Yes
Yes
Yes
HVDs
Yes
Yes
Yes
Yes
Yes
Yes
UVDs
No
No
No
No
No
No
Monitor
type
1. Refer to the Power management controller digital interface (PMC_Dig) chapter.
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8.5
RM0483
Power sequence
The following sections describe the power sequence and the relation among the different
supplies during power-up and power-down.
The device is considered to be in a power sequence (or POWERUP state) when it is either
not supplied or partially supplied. An internal power-on signal is used to identify POWERUP
state. This signal is released high on exit of power sequence. The power-on signal is a
combination of the LVDs monitoring the following supplies:
•
VDD_LV
•
VDD_HV_IO
•
VDD_HV_FLA
The actual threshold used for each LVD is dependent on the configuration of the device.
This is configurable by hardware (flash option bits content) or by software (LVD event
configuration through register interface). Once power-on signal has been asserted, device
configuration is reset to default power-up configuration.
8.5.1
Power-up sequence
In this section it is assumed that all supplies are low when entering the power-up sequence.
Brown-out and power down sequences are managed in specific sections.
8.5.1.1
POWERUP state
At the beginning of power-up, the internal power-on signal remains low due to internal
parasitics diodes. As soon as minimum threshold is reached on VDD_LV and VDD_HV supply,
the internal power-on signal is forced low until power-up LVDs reach upper not trimmed
threshold (refer to datasheet).
The different supplies can rise independently as long as the constraints described in the
device datasheet are met.
During power-up, all functional terminals are maintained into a known state as described in
the device datasheet.
8.5.1.2
POWERUP exit
The POWERUP state can be exited when both VDD_LV and VDD_HV are above the internal
LVD thresholds.
8.5.1.2.1
VDD_LV conditions and LVD trimming/enabling sequence
During POWERUP, only the following low voltage VDs are enabled:
•
MVD102T_C, MVD114_C, MVD114_FL, UVD145_C,
The VDD_LV conditions to exit POWERUP are the following:
•
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Power management
Figure 38. VDD_LV monitored voltages during power-up
DEVICE
(cold point)
VDD_LV pin
All monitors are
placed on Cold point
(hot point)
After the POWERUP exit conditions (low voltage, high voltage conditions) have been
verified, the internal power-on signal is released to all analog modules.
The internal RC oscillator module (IRCOSC) starts initialization and provides clock to the
system after tRCSTARTUP. PMC digital interface reset is released after two RC clock cycles
and LVD119_C is masked. Only MVD114_C remains active.
MVD114_C and LVD119_C share the same reference. This difference provides margin with
respect to maximum internal resistive drop and hysteresis addressing external supply.
The device proceeds through the reset sequence through RCC phase PHASE0,
PHASE1[DEST], PHASE2[DEST] and PHASE3[DEST].
Voltage detector (LVD/HVD) modules are trimmed at the beginning of PHASE3[DEST].
Trimming of LVDs/HVDs are stored as internal DCF records. They are read by SSCM at low
voltage, using the differential flash read accesses and applied to each LVDs/HVDs module.
After analog delay (tLVDTRIM) has elapsed, the PMC acknowledges that all LVDs/HVDs have
been trimmed and supply is above threshold, the SSCM proceeds with the reset sequence,
eventually running full speed accesses to the flash to read the option bits required to
complete device configuration.
The configurable LVD/HVD modules can optionally be unmasked at the end of
PHASE3[DEST]. Mask information is read as DCF record from the flash UTEST option bits.
When LVD119_C and LVD290_C are masked by the application using the flash user option
bits, the device relies on RESETn signal to detect a voltage failure during power-up. The
device must wait for RESETn to be released high before proceeding with the power-up
sequence.This may increase the amount of time necessary to complete the reset sequence.
The following figure provides an example of VDD_LV and VDD_HV power-up sequence before
and after the monitor trimming.
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Figure 39. Example of VDD_LV power-up sequencing
V
Trimming
phase
3.108V
LVD290 variation range
3.003V
3.012V
2.898V
2.906V
2.792V
2.794V
MVD270 variation range
2.697V
2.160V
POR200 variation range
1.760V
V
1.241V
LVD119 variation range
1.157V
1.188V
1.167V
1.119V
1.043V
1.222V
1.133V
MVD114 variation range
0.850V
POR031 variation range
0.290V
The following figure provides an example of VDD_LV power-up sequence before and after the
monitor trimming including UVD and HVD monitors.
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Figure 40. Threshold variation during power-up sequence
V
Including UVD145 and HVD140
Trimming
phase
1.451V
UVD145
HVD140
variation range
UVD
HVD
1.365V
1.309V
(transient only)
1.305V
1.285V
Voltage regulator
range
1.241V
1.215V
1.265V
(transient only)
LVD119 variation range
1.157V
1.225V
1.222V
1.188V
1.167V
1.119V
1.043V
1.449V
1.411V
1.399V
1.361V
1.345V
1.133V
MVD114 variation range
0.850V
POR031 variation range
0.290V
8.5.1.2.2
VDD_HV conditions and LVD trimming/enabling sequence
During POWERUP, the following high voltage MVDs are enabled:
•
MVD270_C
•
MVD270_FL
The VDD_HV conditions to exit POWERUP are the following:
•
LVD290_C
•
LVD290_FL
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Figure 41. VDD_HV monitored voltages during power-up
VDD_HV_IO
(HV power-bar)
VDD_HV_FLA
VDD_HV_FLA
VDD_HV_PMU
LVD290_FL
LVD290_C
VDD_HV_IO1
VDD_HV_SAR
LVD290_IO1
VDD_HV_IO
LVD290_AS
VDD_HV_SAR
VDD_HV_OSC
VDD_HV_SD
LVD290_AD
LVD290_OSC
VDD_HV_OSC
VDD_HV_SD_
DAC_COMP
LVD290_DACCMP
VDD_HV_DAC
LVD290_IO0
VDD_HV_IO0
VDD_HV_IO
The IRCOSC module starts initialization and provides the clock to the system after
tRCSTARTUP. PMC digital interface reset is released after two RC clock cycles.
Device proceeds through the reset sequence through RCC phase PHASE0,
PHASE1[DEST], PHASE2[DEST], PHASE3[DEST].
LVD/HVD modules are trimmed at the beginning of PHASE3[DEST]. Trimming is done by
SSCM at low voltage, using the differential flash read accesses. After trimming is
completed, SSCM waits for PMC acknowledgement before proceeding with reset sequence.
Configurable LVD/HVD modules are optionally enabled at the end of PHASE3[DEST].
The following figure provides the threshold variation of VDD_HV LVDs monitor during powerup sequence from POWERUP before and after trimming.
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Power management
Figure 42. Threshold variation during power-up sequence
Trimming
phase
Including UVD
V
4.004V
UVD380 variation range
3.799V
3.651V
3.596V
3.45V
3.3V
3.15V
3.108V
LVD290 variation range
3.003V
2.898V
2.906V
2.792V
2.697V
3.012V
2.794V
MVD270 variation range
2.160V
POR200 variation range
1.760V
The device needs to fulfill all conditions described in this section to recover.
8.5.2
Power-down sequence
In case LVDs/HVDs are configured to generate destructive reset, either LVD is below
threshold or HVD is above threshold, the device enters PHASE0 phase.
Power-down sequence is actually entered as soon as the threshold of MVD114 and
MVD270 is crossed. The device enters the POWERUP state. The internal power-on signal
is asserted.
On power-on signal assertion, all modules reach their safe state.
Device supplies may then proceed to drop down to ground either through device leakage or
external pull-down. During power-down, all supplies comply with supply constraints.
8.5.3
Brown-out management
During brown-out, the device re-enters the POWERUP phase as soon as the threshold of
either MVD114 or MVD270 is crossed. The internal power-on signal is asserted.
Note:
The device correctly starts independently from any residual voltage. Below MVD270
threshold the device is under POWERUP state. Above the MVD270 threshold, the device is
into a RESET state as defined by Voltage monitor or external RESETn pin or active state
when all have been released.
On internal power-on signal assertion, all analog modules reach their safe state.
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Low voltage requirement during crank
The device can continue operation to the minimum input voltage during crank.
In order to proceed with execution during cranking and prevent device reset, it is important
to correctly configure the high voltage LVDs.
During device switch-off the external LVDs monitoring may not be activated quickly enough
(external assertion of the RESETn pin) and hence the −10% level is crossed before POR is
asserted. Malfunction is possible in this case, but reliability is not impacted. In particular the
flash is not corrupted.
Internal LVDs that monitor the supply ensure that the flash content is protected.
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9
Security
Security
All family devices have a comprehensive set of customer-configurable security features
designed to protect code and data from unauthorized access. Some security features are
available in all device configurations while other more advanced security features are not
available in all device configurations. These more advanced features require more than
simply being turned on or off; they require significant involvement for implementation.
Consequently, they provide an important opportunity to define the security level of the
device.
9.1
Basic security
The SR5E1x device has the following basic set of security features.
9.2
•
Device security feature based on the life cycle model with code and data access
progressively more restricted as device matures through defined life cycle steps
•
Memory security features:
–
NVM censorship support, password protection, one-time-programmable (OTP)
flash memory areas, Flash erase counter and tamper detection
–
SRAM and caches initialized to a constant value after reset (power-on reset, when
in a test mode, when not booting from internal flash memory); MBIST functionality
used in case of power-on and destructive resets to initialize RAMs selected via
configuration in UTEST flash; BAF software routines to initialize RAMs when not
booting from internal flash memory
•
Monitoring of operating conditions
•
Unique ID for each device: each SR5E1x device has a unique identification number
stored in an OTP flash memory area which can be read by any of the cores on the
device
•
Secure watchdog timer
•
Debugger access control
Advanced security
Depending on the device configuration, the following features are available:
•
Customer programmable Hardware Security Module (HSM): a dedicated security
subsystem that includes a processor core, dedicated SRAM, an encryption module,
and exclusive access to secure areas of device flash memory; HSM runs code
independently from the main device processor cores and can be used to implement
advanced security and monitoring functions
•
Advanced debugger access control
•
Boot modes:
–
Trusted/secure boot support
–
Handshake with BAF supported
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9.3
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Detailed security information
Details of most of the SR5E1x security features are published in a separate SR5E1x
Microcontroller Security Reference Manual, which is only available to qualified customers.
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Debug support (DBG)
10
Debug support (DBG)
10.1
Debug and trace architecture
The debug and trace architecture is shown in the figure below.
Figure 43. Debug and Trace architecture
Test Only
TCU
Public Registers
Trace & debug
subsystem
Core1-Cortex-M7 debug
ROM
Table
DWT
FPB
ITM
Legend
AHB-AP
Coresight component
AHB-D
APB-D / AHB-D
(System debug bus)
ROM
Table
Cortex-M7
core
JTAG-AP
JTAG /
Serial Wire Port
DAPBUS
Debug
Access Port
CTI
ETM
ATB (Debug Bus)
JTMS/SWDIO
CTM
(Cross Triggering Matrix)
ROM
Table
SWJ-DP
APB-AP
JTCK/SWCLK
nJTRST
AXI-AP
Core1
Core2
HSM
DWT
FPB
ITM
Timestamp
Signals
AHB-AP
JTDI
JTDO
Debug APB-Interconnect
Core2-Cortex-M7 debug
ROM
Table
AHB-D
ROM
Table
Cortex-M7
Cortex-M7
core
core
CTI
ETM
HSM Cortex-M0+ debug
AXI_M
ROM
Table
DWT
BPU
AHB-AP
System bus
matrix
AXI_S
To System
AHB-D
Cortex-M0+
core
ROM
Table
CTI
AXI2APB
CSTF
TSG
CTM
Sys ROM
Table 1
ETF
SRAM
DBGMCU
(with JDC)
Trace-port
TRACECK
Sys
CTI
10.2
TPIU
TRACED[7:0]
Debug infrastructure features
A comprehensive set of trace and debug features is provided to support software
development and system integration:
•
Independent breakpoint debugging of each CPU core in the system
•
Code execution tracing for M7 cores
•
Data Tracing for M7 cores
•
Software instrumentation
•
Cross-triggering
•
JTAG debug port
•
Serial-wire debug port
•
Trace port
•
Arm® CoreSight™ debug and trace components
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Debug access port functional description
The debug access port (DAP) is a debug subsystem comprising serial-wire and JTAG
debug port (SWJ-DP) and two access ports.
10.3.1
Serial-wire and JTAG debug port (SWJ-DP)
The SWJ-DP is a CoreSight component that implements an external access port for
connecting debugging equipment.
The port can be configured as:
•
a 4-pin standard JTAG debug port (JTAG-DP)
•
a 2-pin (clock + data) “serial-wire” debug port (SW-DP)
The two modes are mutually exclusive, since they share the same IO pins.
By default, the JTAG-DP is selected upon a system or power-on reset. The five IOs are
configured by hardware in debug alternative function mode.
The SWJ-DP incorporates pullup resistors on the JTDI and JTMS/SWDIO lines, as well as
pull-down resistors on the JTCK/SWCLK and JCOMP lines.
10.3.2
Access ports
There are the following access ports (AP) attached to the DP:
•
10.4
APB-AP: for connection to APB-Interconnect, that provides access to Cores Debug
Access Port and to the all system level CoreSight™ components.
–
Three AHB-APs are present between APB debug and each AHBD port of cores.
AHBD port give access to the debug and trace features integrated in the cores
(which means in Cortex-M7 processor cores and in Cortex-M0+ processor).
–
A branch of APB-Interconnect allows the access to the debug and trace features
on the system APB debug bus for all components not included in processor cores.
•
AXI-AP: allows access of the debug to the NIC as master. This gives visibility of system
memories and peripherals. No CoreSight™ components are accessible through this
port.
•
JTAG_AP: non user port, connected to public TCU registers, that allows to have
visibility to device status, monitoring what happens during reset phases.
NIC ports related to debug
The NIC has an initiator AXI port for the access from the DAP to all device resources
(memories, peripherals).
The NIC has an APB slave port for the access from Core1 and Core2 and CoreH to the
APB-Debug, that allows the programming of the debug components.
10.5
Global timestamp generator (TSG)
The global timestamp generator contains a 64-bit counter that provides a common timing
reference for all of the trace sources in the system, namely the ETM and ITM in each
processor core.These components insert timestamps in the trace streams that allow the
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Debug support (DBG)
trace analyzer to recover the chronological order of trace packets, which can be lost when
multiple trace sources are multiplexed into one stream at the funnels.
The TSG registers are accessible over the APB-D. This allows the debugger or debug
software to:
•
Start and stop the timestamp incrementing
•
Read the current timestamp value
•
Change the current timestamp value
–
•
The timestamp counter must be halted while it is changed. When the timestamp
value is changed, the timestamp generator resynchronizes all the trace sources.
change the reported timestamp increment
The timestamp is distributed to the all Cortex-M7 cores.
Timestamp structure is shown in the figure below.
Figure 44. Timestamp structure
10.6
Cross trigger interfaces (CTI) and matrix (CTM)
The cross trigger interfaces (CTI) and cross trigger matrix (CTM) together form the
CoreSight embedded cross trigger feature. There are four CTI components, one at system
level, two dedicated to each Cortex-M7 and one dedicated to the CortexM0+ inside HSM.
The four CTIs are connected to each other via the CTM.
The system-level CTI is accessible to the debugger via the system access port and
associated APB-D.
The Cortex- M7 CTI is physically integrated in the Cortex-M7 core, and is accessible via the
Cortex-M7 access port and associated AHBD.
The Cortex- M0+ CTI is physically integrated in the Cortex-M0+ core, and is accessible via
the Cortex-M0+ access port and associated AHBD.
Two internal trigger sources are managed by CTM network: Halt and Restart.
No external triggers have to be managed.
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In addition, TPIU and ETF triggers are connected to the system CTI. For more details about
the triggers, refer to Arm® CoreSight™ System-on-Chip SoC-600 revision r4p0.
Furthermore, the dp_eventstatus has been used: a generic trigger can be mapped on the
dp_eventstatus to quickly inform the external tool through the DP when the particular trigger
is received.
The figure below shows the cross triggering matrix.
Figure 45. Cross triggering matrix
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10.6.1
Debug support (DBG)
Embedded trace FIFO (ETF)
The ETF is a 4 Kbyte memory that captures trace data from four trace sources, namely the
ETM and ITM of each M7- CPU core. The ETF is a design configuration of the CoreSight™
trace memory controller component.
The ETF can be used in three modes (selected in the mode register):
1.
10.7
Hardware FIFO mode
2.
Software FIFO mode
3.
Circular buffer mode
Trace port interface unit (TPIU)
The TPIU is a CoreSight™ component that formats the trace stream and outputs it on the
external trace port signals. The TPIU has a single ATB slave port for incoming trace data.
The trace port is a synchronous parallel port, comprising a clock output, TRACECK, and up
to eight data outputs, TRACED(7:0). The trace port width is programmable in the range 1 to
8.
Using a smaller port width reduces the number of test points/connector pins needed, and
frees up IOs for other purposes. However it restricts the bandwidth of the trace port and
hence the quantity of trace information that can be output in real time.
TRACECK frequency is programmable and max frequency is 50MHz.
10.8
Cortex-M7 debug functional description
The Cortex-M7 subsystem features the following CoreSight™ components:
•
ROM tables
•
System control space (SCS)
•
Breakpoint unit (FPB)
•
Data watchpoint and trace unit (DWT)
•
Instrumentation trace macrocell (ITM)
•
Embedded trace macrocell (ETM)
•
Cross trigger interface (CTI)
These components are accessible by the debugger via the Cortex-M7 AHB-AP and its
associated AHBD bus.
ETM has to be configured in order to trace both instruction and data.
10.9
Debug configuration in lockstep
When lockstep is enabled, only Core1 is accessible for debug.
The port AHB-AP of Core2 is closed by gating with lockstep information.
When lockstep feature is enabled, the user must ensure the correspondent ATB Funnel
slave interfaces are disabled to avoid funnel switching activity and trace bandwidth
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reducing. Therefore, when lockstep is enabled, FUNNELCONTROL[7:3] must be equal to
0x0.
Table 106. Slave mapping
Funnel control [bits]
Slave interface
[0]
Core1_ITM_Trace_Data
[1]
Core1_ETM_Trace_Instruction
[2]
Core1_ETM_Trace_Data
[3]
Core2_ITM_Trace_Data
[4]
Core2_ETM_Trace_Instruction
[5]
Core2_ETM_Trace_Data
Note:
For information on the CoreSight™ registers, refer to the documentation available on the
arm website.
10.10
Additional requirements
10.10.1
Capability of the debugger host to connect under system reset
The Cortex®-M7 differentiates the reset of the debug part (generally PORRESETn) and the
other one (SYSRESETn).
This way, it is possible for the debugger to connect under system reset, programming the
core debug registers to halt the core when fetching the reset vector.
Then the host must release the system reset and the core immediately halts without having
executed any instructions.
Note:
The debugger host can always connect under system reset with the Boot CPU (Core1)
while for Core2 the enable of core is mandatory by means of DCF Global System
Configuration[CORE2_EN].
In addition, it must be possible to program any debug features under system reset.
Note:
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The possibility to program debug features under reset has some limitations in SR5E1x,
agreed with Design Team and listed below like:
–
Trace components (TPIU, EFT, Funnel) cannot be programmed under reset
–
Programming is possible only from external tool, not from cores
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10.10.2
Debug support (DBG)
Capability to control debug features of cores and IPs
The capability to control debug features of cores and IPs includes the possibility to:
•
Maintain the clock to the processor cores when in low-power modes (C-sleep mode).
•
Maintain the clock to the system debug and trace components when in low power
modes.
•
Stop the clock to certain peripherals (CAN, SMBUS timeout, Watchdogs, Timers, RTC)
when one of the processor cores is stopped in debug mode.
•
For timers having complementary outputs (TIM1/8/15/16), the outputs must be disabled
(as if the MOE bit was reset) for safety purposes when the counter is stopped
(TIM1/8/15/16).
These functionalities are implemented inside DBGMCU.
10.10.3
Debug protection
Debug access has to be controlled by life cycle mechanism.
For details, refer to Stellar E security reference manual.
10.11
DBGMCU module
DBGMCU allows to control the behavior of the peripherals during a breakpoint.
During a breakpoint, it is necessary to choose how the counter of timers, RTC and
watchdog must behave:
•
They can continue to count inside a breakpoint. This is usually required when a PWM is
controlling a motor, for example.
•
They can stop to count inside a breakpoint. This is required for watchdog purposes.
For the I2C, the user can choose to block the SMBUS timeout during a breakpoint.
See also requirements in Section 10.10.2: Capability to control debug features of cores and
IPs.
The DBGMCU freeze registers can be written by the debugger under system reset.
Two sets of freeze registers must be implemented, one for each core, for all the peripherals
that support freeze feature.
When the FRZ bit related to a peripheral is set, the peripheral is frozen when the
corresponding core (Core1 or Core2) is halted in debug mode.
For the mapping of freeze registers, refer to Section 10.13: DBGMCU register descriptions.
10.12
DBGMCU Register Summary
Table 107. DBGMCU register list
Offset
Register Name
0x0000
APB1_C1_FZ_REG
0x0004
APB2_C1_FZ_REG
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Table 107. DBGMCU register list (continued)
Offset
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Register Name
0x0008
AXI_C1_FZ_REG
0x0010
APB1_C2_FZ_REG
0x0014
APB2_C2_FZ_REG
0x0018
AXI_C2_FZ_REG
0x0020
DBG_RST_REG
0x0024
DOUT_REG
0x0028
DIN_REG
0x002C
DMCR
0x0030
DMSR
0x0040
CTI_TRG_SEL
0x0044
DBG_SLEEP_CFG
0x0FBC
DEVARCH
0x0FCC
DEVTYPE
0x0FD0
PIDR4
0x0FD4
PIDR5
0x0FD8
PIDR6
0x0FDC
PIDR7
0x0FE0
PIDR0
0x0FE4
PIDR1
0x0FE8
PIDR2
0x0FEC
PIDR3
0x0FF0
CIDR0
0x0FF4
CIDR1
0x0FF8
CIDR2
0x0FFC
CIDR3
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10.13
Debug support (DBG)
DBGMCU register descriptions
APB1_C1_FZ_REG
APB1 Debug Freeze Register Core 1
IWDG2_FRZ
IWDG1_FRZ
RESERVED0
WWDG2_FRZ
WWDG1_FRZ
0
RESERVED1
1
RTC_FRZ
2
RESERVED2
3
TIM2_FRZ
4
TIM3_FRZ
5
TIM6_FRZ
6
TIM7_FRZ
R
W
7
TIM_TS_FRZ
I2C2_FRZ
R
8
I2C1_FRZ
RESERVED4
R
W
9
RESERVED3
FCCU_DBG
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
W
R
R
W
R
W
R
W
R
W
R
W
R
R
W
R
R
W
R
W
R
R
W
R
W
Address:
DBGMCUBaseAddress + 0x0000
Type:
RW
Reset:
0x0000
Description:
This register is used to enable the debug freeze feature of APB1 memory mapped IPs
for the core 1. This register can be written and read only if DBGEN is active DBGMCU invasive debug.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
[31] FCCU_DBG: “FCCU Debug Mode”
0x0: “FCCU Normal Operation”
0x1: “FCCU in debug mode when core 1 is halted. When FCCU_CTRL[DEBUG] is asserted
and this bit is set, FCCU moves into debug state and suspends the transition of the FSM by
suspending timer elapse time effect.”
[30:23] RESERVED4: “This field is reserved. It must be kept to zero by the software.”
[22] I2C2_FRZ: “I2C 2 SMBUS Timeout Freeze”
0x0: “I2C 2 SMBUS Timeout is not blocked when Core 1 is halted.”
0x1: “I2C 2 SMBUS Timeout is blocked when Core 1 is halted.”
[21] I2C1_FRZ: “I2C 1 SMBUS Timeout Freeze”
0x0: “I2C 1 SMBUS Timeout is not blocked when Core 1 is halted.”
0x1: “I2C 1 SMBUS Timeout is blocked when Core 1 is halted.”
[20] RESERVED3: “This field is reserved. It must be kept to zero by the software.”
[19] TIM_TS_FRZ: “Timer TS Debug Freeze”
0x0: “Timer TS is not disabled when Core 1 is halted.”
0x1: “Timer TS is disabled when Core 1 is halted.”
[18] TIM7_FRZ: “Timer 7 Debug Freeze”
0x0: “Timer 7 is not disabled when Core 1 is halted.”
0x1: “Timer 7 is disabled when Core 1 is halted.”
[17] TIM6_FRZ: “Timer 6 Debug Freeze”
0x0: “Timer 6 is not disabled when Core 1 is halted.”
0x1: “Timer 6 is disabled when Core 1 is halted.”
[16] TIM3_FRZ: "Timer 3 Debug Freeze"
0x0: "Timer 3 is not disabled when Core 1 is halted."
0x1: "Timer 3 is disabled when Core 1 is halted."
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[15] TIM2_FRZ: "Timer 2 Debug Freeze"
0x0: "Timer 2 is not disabled when Core 1 is halted."
0x1: "Timer 2 is disabled when Core 1 is halted."
[14:11] RESERVED2: "This field is reserved. It must be kept to zero by the software."
[10] RTC_FRZ: "RTC Debug Freeze"
0x0: "RTC is not disabled when Core 1 is halted."
0x1: "RTC is disabled when Core 1 is halted."
[9:6] RESERVED1: "This field is reserved. It must be kept to zero by the software."
[5] IWDG2_FRZ: "Independent WDG 2 Debug Freeze"
0x0: "Independent watchdog 2 is not disabled when Core 1 is halted."
0x1: "Independent watchdog 2 is disabled when Core 1 is halted."
[4] IWDG1_FRZ: "Independent WDG 1 Debug Freeze"
0x0: "Independent watchdog 1 is not disabled when Core 1 is halted."
0x1: "Independent watchdog 1 is disabled when Core 1 is halted."
[3:2] RESERVED0: "This field is reserved. It must be kept to zero by the software."
[1] WWDG2_FRZ: "Window WDG 2 Debug Freeze"
0x0: "Window watchdog 2 is not disabled when Core 1 is halted."
0x1: "Window watchdog 2 is disabled when Core 1 is halted."
[0] WWDG1_FRZ: "Window WDG 1 Debug Freeze"
0x0: "Window watchdog 1 is not disabled when Core 1 is halted."
0x1: "Window watchdog 1 is disabled when Core 1 is halted."
APB2_C1_FZ_REG
APB2 Debug Freeze Register Core 1
TIM5_PWM_FRZ
TIM4_PWM_FRZ
RESERVED1
TIM8_PWM_FRZ
TIM1_PWM_FRZ
RESERVED0
TSU_CAN4_DIS_MORD
TSU_CAN3_DIS_MORD
TSU_CAN2_DIS_MORD
TSU_CAN1_DIS_MORD
0
TIM15_PWM_FRZ
1
TIM16_PWM_FRZ
2
RESERVED2
3
SDADC1_DBG_FRZ
4
SDADC2_DBG_FRZ
5
RESERVED3
6
FDCAN1_DIS_MORD
7
FDCAN2_DIS_MORD
8
FDCAN3_DIS_MORD
9
FDCAN4_DIS_MORD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
W
R
W
R
W
R
W
R
R
W
R
W
R
R
W
R
W
R
W
R
W
R
R
W
R
W
R
R
W
R
W
R
W
R
W
Address:
DBGMCUBaseAddress + 0x0004
Type:
RW
Reset:
0x0000
Description:
This register is used to enable the debug freeze feature of APB2 memory mapped IPs
for the core 1. This register can be written and read only if DBGEN is active DBGMCU invasive debug.
access_size: 32
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min_write_access_size: 32
min_read_access_size: 32
[31] FDCAN4_DIS_MORD: "FDCAN 4 Disable Modify Read"
0x0: "See FDCAN 1 Disable Modify Read."
0x1: "See FDCAN 1 Disable Modify Read."
[30] FDCAN3_DIS_MORD: "FDCAN 3 Disable Modify Read"
0x0: "See FDCAN 1 Disable Modify Read."
0x1: "See FDCAN 1 Disable Modify Read."
[29] FDCAN2_DIS_MORD: "FDCAN 2 Disable Modify Read"
0x0: "See FDCAN 1 Disable Modify Read."
0x1: "See FDCAN 1 Disable Modify Read."
[28] FDCAN1_DIS_MORD: "FDCAN 1 Disable Modify Read"
0x0: "FDCAN modify read is not disabled when Core 1 is halted."
0x1: "FDCAN modify read is disabled when Core 1 is halted: it means that the register bit fields
that change after a read operation in normal mode are frozen in debug mode. Therefore a read
operation of this register does not change the content."
[27:26] RESERVED3: "This field is reserved. It must be kept to zero by the software."
[25] SDADC2_DBG_FRZ: "SDADC 2 Debug Freeze"
0x0: "Timer 16 is not disabled when Core 1 is halted."
0x1: "Timer 16 is disabled when Core 1 is halted."
[24] SDADC1_DBG_FRZ: "SDADC 1 Debug Freeze"
0x0: "Timer 16 is not disabled when Core 1 is halted."
0x1: "Timer 16 is disabled when Core 1 is halted."
[23:19] RESERVED2: "This field is reserved. It must be kept to zero by the software."
[18] TIM16_PWM_FRZ: "Timer 16 PWM Debug Freeze"
0x0: "Timer 16 is not disabled when Core 1 is halted."
0x1: "Timer 16 is disabled when Core 1 is halted."
[17] TIM15_PWM_FRZ: "Timer 15 PWM Debug Freeze"
0x0: "Timer 15 is not disabled when Core 1 is halted."
0x1: "Timer 15 is disabled when Core 1 is halted."
[16] TIM5_PWM_FRZ: "Timer 5 PWM Debug Freeze"
0x0: "Timer 5 is not disabled when Core 1 is halted."
0x1: "Timer 5 is disabled when Core 1 is halted."
[15] TIM4_PWM_FRZ: "Timer 4 PWM Debug Freeze"
0x0: "Timer 4 is not disabled when Core 1 is halted."
0x1: "Timer 4 is disabled when Core 1 is halted."
[14:13] RESERVED1: "This field is reserved. It must be kept to zero by the software."
[12] TIM8_PWM_FRZ: "Timer 8 PWM Debug Freeze"
0x0: "Timer 8 is not disabled when Core 1 is halted."
0x1: "Timer 8 is disabled when Core 1 is halted."
[11] TIM1_PWM_FRZ: "Timer 1 PWM Debug Freeze"
0x0: "Timer 1 is not disabled when Core 1 is halted."
0x1: "Timer 1 is disabled when Core 1 is halted."
[10:4] RESERVED0: "This field is reserved. It must be kept to zero by the software."
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[3] TSU_CAN4_DIS_MORD: "FDCAN TSU 4 Disable Modify Read"
0x0: "See FDCAN TSU 1 Disable Modify Read."
0x1: "See FDCAN TSU 1 Disable Modify Read."
[2] TSU_CAN3_DIS_MORD: "FDCAN TSU 3 Disable Modify Read"
0x0: "See FDCAN TSU 1 Disable Modify Read."
0x1: "See FDCAN TSU 1 Disable Modify Read."
[1] TSU_CAN2_DIS_MORD: "FDCAN TSU 2 Disable Modify Read"
0x0: "See FDCAN TSU 1 Disable Modify Read."
0x1: "See FDCAN TSU 1 Disable Modify Read."
[0] TSU_CAN1_DIS_MORD: "FDCAN TSU 1 Disable Modify Read"
0x0: "FDCAN TSU 1 modify read is not disabled when Core 1 is halted."
0x1: "FDCAN TSU 1 modify read is disabled when Core 1 is halted: it means that theTSU
register bit fields that change after a read operation in normal mode are frozen in debug mode.
Therefore a read operation of this register does not change the content."
1
0
RESERVED0
HRTIMER1_FRZ
AXI Debug Freeze Register Core 1
HRTIMER2_FRZ
AXI_C1_FZ_REG
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
R
R
W
R
W
Address:
DBGMCUBaseAddress + 0x0008
Type:
RW
Reset:
0x0000
Description:
This register is used to enable the debug freeze feature of AXI memory mapped IPs
for the core 1. This register can be written and read only if DBGEN is active DBGMCU invasive debug.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
[31:2] RESERVED0: "This field is reserved. It must be kept to zero by the software."
[1] HRTIMER2_FRZ: "HRTimer 2 Debug Freeze"
0x0: "HRTimer 2 is not disabled when Core 1 is halted."
0x1: "HRTimer 2 is disabled when Core 1 is halted."
[0] HRTIMER1_FRZ: "HRTimer 1 Debug Freeze"
0x0: "HRTimer 1 is not disabled when Core 1 is halted."
0x1: "HRTimer 1 is disabled when Core 1 is halted."
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APB1_C2_FZ_REG
APB1 Debug Freeze Register Core 2
IWDG2_FRZ
IWDG1_FRZ
RESERVED0
WWDG2_FRZ
WWDG1_FRZ
0
RESERVED1
1
RTC_FRZ
2
RESERVED2
3
TIM2_FRZ
4
TIM3_FRZ
5
TIM6_FRZ
6
TIM7_FRZ
R
W
7
TIM_TS_FRZ
I2C2_FRZ
R
8
I2C1_FRZ
RESERVED4
R
W
9
RESERVED3
FCCU_DBG
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
W
R
R
W
R
W
R
W
R
W
R
W
R
R
W
R
R
W
R
W
R
R
W
R
W
Address:
DBGMCUBaseAddress + 0x0010
Type:
RW
Reset:
0x0000
Description:
This register is used to enable the debug freeze feature of APB1 memory mapped IPs
for the core 2. This register can be written and read only if DBGEN is active DBGMCU invasive debug.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
[31] FCCU_DBG: "FCCU Debug Mode"
0x0: "FCCU Normal Operation"
0x1: "FCCU in debug mode when core 2 is halted. When FCCU_CTRL[DEBUG] is asserted
and this bit is set, FCCU moves into debug state and suspends the transition of the FSM by
suspending timer elapse time effect."
[30:23] RESERVED4: "This field is reserved. It must be kept to zero by the software."
[22] I2C2_FRZ: "I2C 2 Debug Freeze"
0x0: "I2C 2 is not disabled when Core 2 is halted."
0x1: "I2C 2 is disabled when Core 2 is halted."
[21] I2C1_FRZ: "I2C 1 Debug Freeze"
0x0: "I2C 1 is not disabled when Core 2 is halted."
0x1: "I2C 1 is disabled when Core 2 is halted."
[20] RESERVED3: "This field is reserved. It must be kept to zero by the software."
[19] TIM_TS_FRZ: "Timer TS Debug Freeze"
0x0: "Timer TS is not disabled when Core 2 is halted."
0x1: "Timer TS is disabled when Core 2 is halted."
[18] TIM7_FRZ: "Timer 7 Debug Freeze"
0x0: "Timer 7 is not disabled when Core 2 is halted."
0x1: "Timer 7 is disabled when Core 2 is halted."
[17] TIM6_FRZ: "Timer 6 Debug Freeze"
0x0: "Timer 6 is not disabled when Core 2 is halted."
0x1: "Timer 6 is disabled when Core 2 is halted."
[16] TIM3_FRZ: "Timer 3 Debug Freeze"
0x0: "Timer 3 is not disabled when Core 2 is halted."
0x1: "Timer 3 is disabled when Core 2 is halted."
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[15] TIM2_FRZ: "Timer 2 Debug Freeze"
0x0: "Timer 2 is not disabled when Core 2 is halted."
0x1: "Timer 2 is disabled when Core 2 is halted."
[14:11] RESERVED2: "This field is reserved. It must be kept to zero by the software."
[10] RTC_FRZ: "RTC Debug Freeze"
0x0: "RTC is not disabled when Core 2 is halted."
0x1: "RTC is disabled when Core 2 is halted."
[9:6] RESERVED1: "This field is reserved. It must be kept to zero by the software."
[5] IWDG2_FRZ: "Independent WDG 2 Debug Freeze"
0x0: "Independent watchdog 2 is not disabled when Core 2 is halted."
0x1: "Independent watchdog 2 is disabled when Core 2 is halted."
[4] IWDG1_FRZ: "Independent WDG 1 Debug Freeze"
0x0: "Independent watchdog 1 is not disabled when Core 2 is halted."
0x1: "Independent watchdog 1 is disabled when Core 2 is halted."
[3:2] RESERVED0: "This field is reserved. It must be kept to zero by the software."
[1] WWDG2_FRZ: "Window WDG 2 Debug Freeze"
0x0: "Window watchdog 2 is not disabled when Core 2 is halted."
0x1: "Window watchdog 2 is disabled when Core 2 is halted."
[0] WWDG1_FRZ: "Window WDG 1 Debug Freeze"
0x0: "Window watchdog 1 is not disabled when Core 2 is halted."
0x1: "Window watchdog 1 is disabled when Core 2 is halted."
APB2_C2_FZ_REG
APB2 Debug Freeze Register Core 1
TIM5_PWM_FRZ
TIM4_PWM_FRZ
RESERVED1
TIM8_PWM_FRZ
TIM1_PWM_FRZ
RESERVED0
TSU_CAN4_DIS_MORD
TSU_CAN3_DIS_MORD
TSU_CAN2_DIS_MORD
TSU_CAN1_DIS_MORD
0
TIM15_PWM_FRZ
1
TIM16_PWM_FRZ
2
RESERVED2
3
SDADC1_DBG_FRZ
4
SDADC2_DBG_FRZ
5
RESERVED3
6
FDCAN1_DIS_MORD
7
FDCAN2_DIS_MORD
8
FDCAN3_DIS_MORD
9
FDCAN4_DIS_MORD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
W
R
W
R
W
R
W
R
R
W
R
W
R
R
W
R
W
R
W
R
W
R
R
W
R
W
R
R
W
R
W
R
W
R
W
Address:
DBGMCUBaseAddress + 0x0014
Type:
RW
Reset:
0x0000
Description:
This register is used to enable the debug freeze feature of APB2 memory mapped IPs
for the core 2. This register can be written and read only if DBGEN is active DBGMCU invasive debug.
access_size: 32
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min_write_access_size: 32
min_read_access_size: 32
[31] FDCAN4_DIS_MORD: "FDCAN 4 Disable Modify Read"
0x0: "See FDCAN 1 Disable Modify Read."
0x1: "See FDCAN 1 Disable Modify Read."
[30] FDCAN3_DIS_MORD: "FDCAN 3 Disable Modify Read"
0x0: "See FDCAN 1 Disable Modify Read."
0x1: "See FDCAN 1 Disable Modify Read."
[29] FDCAN2_DIS_MORD: "FDCAN 2 Disable Modify Read"
0x0: "See FDCAN 1 Disable Modify Read."
0x1: "See FDCAN 1 Disable Modify Read."
[28] FDCAN1_DIS_MORD: "FDCAN 1 Disable Modify Read"
0x0: "FDCAN modify read is not disabled when Core 2 is halted."
0x1: "FDCAN modify read is disabled when Core 2 is halted: it means that the register bit fields
that change after a read operation in normal mode are frozen in debug mode. Therefore a read
operation of this register does not change the content."
[27:26] RESERVED3: "This field is reserved. It must be kept to zero by the software."
[25] SDADC2_DBG_FRZ: "SDADC 2 Debug Freeze"
0x0: "Timer 16 is not disabled when Core 2 is halted."
0x1: "Timer 16 is disabled when Core 2 is halted."
[24] SDADC1_DBG_FRZ: "SDADC 1 Debug Freeze"
0x0: "Timer 16 is not disabled when Core 2 is halted."
0x1: "Timer 16 is disabled when Core 2 is halted."
[23:19] RESERVED2: "This field is reserved. It must be kept to zero by the software."
[18] TIM16_PWM_FRZ: "Timer 16 PWM Debug Freeze"
0x0: "Timer 16 is not disabled when Core 2 is halted."
0x1: "Timer 16 is disabled when Core 2 is halted."
[17] TIM15_PWM_FRZ: "Timer 15 PWM Debug Freeze"
0x0: "Timer 15 is not disabled when Core 2 is halted."
0x1: "Timer 15 is disabled when Core 2 is halted."
[16] TIM5_PWM_FRZ: "Timer 5 PWM Debug Freeze"
0x0: "Timer 5 is not disabled when Core 2 is halted."
0x1: "Timer 5 is disabled when Core 2 is halted."
[15] TIM4_PWM_FRZ: "Timer 4 PWM Debug Freeze"
0x0: "Timer 4 is not disabled when Core 2 is halted."
0x1: "Timer 4 is disabled when Core 2 is halted."
[14:13] RESERVED1: "This field is reserved. It must be kept to zero by the software."
[12] TIM8_PWM_FRZ: "Timer 8 PWM Debug Freeze"
0x0: "Timer 8 is not disabled when Core 2 is halted."
0x1: "Timer 8 is disabled when Core 2 is halted."
[11] TIM1_PWM_FRZ: "Timer 1 PWM Debug Freeze"
0x0: "Timer 1 is not disabled when Core 2 is halted."
0x1: "Timer 1 is disabled when Core 2 is halted."
[10:4] RESERVED0: "This field is reserved. It must be kept to zero by the software."
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[3] TSU_CAN4_DIS_MORD: "FDCAN TSU 4 Disable Modify Read"
0x0: "See FDCAN TSU 1 Disable Modify Read."
0x1: "See FDCAN TSU 1 Disable Modify Read."
[2] TSU_CAN3_DIS_MORD: "FDCAN TSU 3 Disable Modify Read"
0x0: "See FDCAN TSU 1 Disable Modify Read."
0x1: "See FDCAN TSU 1 Disable Modify Read."
[1] TSU_CAN2_DIS_MORD: "FDCAN TSU 2 Disable Modify Read"
0x0: "See FDCAN TSU 1 Disable Modify Read."
0x1: "See FDCAN TSU 1 Disable Modify Read."
[0] TSU_CAN1_DIS_MORD: "FDCAN TSU 1 Disable Modify Read"
0x0: "FDCAN TSU 1 modify read is not disabled when Core 2 is halted."
0x1: "FDCAN TSU 1 modify read is disabled when Core 2 is halted: it means that theTSU
register bit fields that change after a read operation in normal mode are frozen in debug mode.
Therefore a read operation of this register does not change the content."
1
0
RESERVED0
HRTIMER1_FRZ
AXI Debug Freeze Register Core 2
HRTIMER2_FRZ
AXI_C2_FZ_REG
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
R
R
W
R
W
Address:
DBGMCUBaseAddress + 0x0018
Type:
RW
Reset:
0x0000
Description:
This register is used to enable the debug freeze feature of AXI memory mapped IPs
for the core 2. This register can be written and read only if DBGEN is active DBGMCU invasive debug.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
[31:2] RESERVED0: "This field is reserved. It must be kept to zero by the software."
[1] HRTIMER2_FRZ: "HRTimer 2 Debug Freeze"
0x0: "HRTimer 2 is not disabled when Core 2 is halted."
0x1: "HRTimer 2 is disabled when Core 2 is halted."
[0] HRTIMER1_FRZ: "HRTimer 1 Debug Freeze"
0x0: "HRTimer 1 is not disabled when Core 2 is halted."
0x1: "HRTimer 1 is disabled when Core 2 is halted."
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1
0
RESERVED
FPD_DEST
Debug Force Reset Register
FPD_FUNC
DBG_RST_REG
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
R
R
W
R
W
Address:
DBGMCUBaseAddress + 0x0020
Type:
RW
Reset:
0x0000
Description:
This register is used to perform both functional and destructive reset. It is replacing
DCI jtag reset source defined for other M40 devices. This register can be written and
read only if DBGEN is active - DBGMCU invasive debug.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
[1] FPD_DEST: "Force Destructive Reset Bit. This field must be written and cleared by the
software."
0x0: "Do not force destructive reset"
0x1: "Force destructive reset."
[0] FPD_FUNC: "Force Functional Reset Bit. This field must be written and cleared by the
software."
0x0: "Do not force functional reset"
0x1: "Force functional reset."
DOUT_REG
DBGMCU Output Data Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DOUT
RW
Address:
DBGMCUBaseAddress + 0x0024
Type:
RW
Reset:
0x0000
Description:
This register can be written by the software to implement the JTAG Password or
Challenge/Response authentication protocol. It is replacing JOUT_IPS JDC register.
This register can be only written by the cores while it is read-only for the external tool.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
[31:0] DOUT: "This register can be written by the software to implement the JTAG Password or
Challenge/Response authentication protocol. This register can be only written by the secure
master and it is RO for the other masters."
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DIN_REG
DBGMCU Input Data Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DIN
RW
Address:
DBGMCUBaseAddress + 0x0028
Type:
RW
Reset:
0x0000
Description:
This register can be written by the external tool to implement the JTAG Password or
Challenge/Response authentication protocol. It is replacing JIN_IPS JDC register.
This register can be only written by the external tool while it is read-only for the other
masters.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
[31:0] DIN: "This register can be written by the external tool to implement the JTAG Password or
Challenge/Response authentication protocol. This register can be only written by the external
tool and it is RO for the other masters."
DMCR
DBGMCU Module Control Register
R
8
7
6
5
4
3
2
1
0
RESERVED0
DOUT_IE
RESERVED1
9
DIN_IE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
W
R
R
W
Address:
DBGMCUBaseAddress + 0x002C
Type:
RW
Reset:
0x0000
Description:
This register is can be written to enable DIN and DOUT interrupt. It is replacing MCR
JDC register. This register is always accessible.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
[31:17] RESERVED1: "This field is reserved. It must be kept to zero by the software."
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[16] DIN_IE: "This bit is written and cleared by the software. It is used to enable or disable DIN
interrupt flag."
0x0: "DIN interrupt flag is disabled."
0x1: "DIN interrupt flag is enabled. An interrupt is generated if a new data is received in DIN
register."
[15:1] RESERVED0: "This field is reserved. It must be kept to zero by the software."
[0] DOUT_IE: "This bit is written and cleared by the software. It is used to enable or disable DOUT
interrupt flag."
0x0: "DOUT interrupt flag is disabled."
0x1: "DOUT interrupt flag is enabled. An interrupt is generated if a new data is received in
DOUT register."
DMSR
DBGMCU Module Status Register
1
0
DOUT_RDY
2
RESERVED0
3
DOUT_IF
4
RESERVED1
5
DIN_RDY
6
RESERVED2
7
DIN_IF
8
RESERVED3
9
DEVICE_EN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
W
R
R
R
R
W
R
R
Address:
DBGMCUBaseAddress + 0x0030
Type:
RW
Reset:
0x0000
Description:
This register shows when DOUT and DIN data are ready in the corresponding
registers. It also shows if the interrupt flags for DOUT and DIN data are generated. It
is replacing MSR JDC register. This register is always accessible.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
[31] DEVICE_EN: "This bit is set if DBGEN&NIDEN = 1; it means DBGMCU is in full debug."
[30:25] RESERVED3: "This field is reserved. It must be kept to zero by the software."
[24] DIN_IF: "This bit is set if a new data is received in the DIN_REG and the correspondent bit in
the DMCR is set. It must be cleared by the software writing this bit field to 0x1."
[23:17] RESERVED2: "This field is reserved. It must be kept to zero by the software."
[16] DIN_RDY: "This bit is set if a new data is ready in the DIN_REG. It is automatically cleared by
the hardware when DIN_REG is read."
[15:9] RESERVED1: "This field is reserved. It must be kept to zero by the software."
[8] DOUT_IF: "This bit is set if a new data is received in the DOUT_REG and the correspondent bit
in the DMCR is set. It must be cleared by the software writing this bit field to 0x1."
[7:1] RESERVED0: "This field is reserved. It must be kept to zero by the software."
[0] DOUT_RDY: "This bit is set if a new data is ready in the DOUT_REG. It is automatically cleared
by the hardware when DOUT_REG is read."
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RM0483
CTI_TRG_SEL
CTI Trigger Selection Register
R
8
7
6
5
4
3
2
1
RESERVED0
TINIDENSEL
RESERVED1
9
TODBGENSEL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RW
R
RW
0
Address:
DBGMCUBaseAddress + 0x0040
Type:
RW
Reset:
0x0000
Description:
This register is written and cleared by the software; it can be used to configure
TINDENSEL and TODGBENSEL of system CTI. This register can be written and read
only if DBGEN is active - DBGMCU invasive debug.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
[31:21] RESERVED1: "This field is reserved. It must be kept to zero by the software."
[20:16] TODBGENSEL: "When dbgen (CTI) is HIGH, all event_out[n] outputs are enabled. When
dbgen is LOW:
• event_out[n] is enabled if todbgensel[n] is HIGH
• event_out[n] is masked if todbgensel[n] is LOW"
[15:4] RESERVED0: "This field is reserved. It must be kept to zero by the software."
[3:0] TINIDENSEL: "When niden (CTI) is HIGH, all event_in[n] inputs are enabled. When niden is
LOW:
• event_in[n] is enabled if tinidensel[n] is HIGH
• event_in[n] is masked if tinidensel[n] is LOW"
9
8
7
RESERVED1
DBG_SLEEPH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED0
R
R
W
R
6
5
4
3
2
1
0
DBG_SLEEP1
DBGMCU Debug Sleep Configuration Register
DBG_SLEEP2
DBG_SLEEP_CFG
R
W
R
W
Address:
DBGMCUBaseAddress + 0x0044
Type:
RW
Reset:
0x0000
Description:
This register can be written to set the DBG_SLEEP bit for Core 1, Core 2 and Core H
access_size: 32
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min_write_access_size: 32
min_read_access_size: 32
[31:17] RESERVED1: "This field is reserved. It must be kept to zero by the software."
[16] DBG_SLEEPH: "This bit is written and cleared by the software. It is used to set the debug
sleep for Core H."
0x0: "Normal operation - processor clock is stopped automatically when WFI/WFE are
executed."
0x1: "Automatic clock stop disabled - processor clock continues to run, allowing full debug
capability."
[15:2] RESERVED0: "This field is reserved. It must be kept to zero by the software."
[1] DBG_SLEEP2: "This bit is written and cleared by the software. It is used to set the debug sleep
for Core 2."
0x0: "Normal operation - processor clock is stopped automatically when WFI/WFE are
executed."
0x1: "Automatic clock stop disabled - processor clock continues to run, allowing full debug
capability."
[0] DBG_SLEEP1: "This bit is written and cleared by the software. It is used to set the debug sleep
for Core 1."
0x0: "Normal operation - processor clock is stopped automatically when WFI/WFE are
executed."
0x1: "Automatic clock stop disabled - processor clock continues to run, allowing full debug
capability."
DEVARCH
Device Architecture Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DEV_ARCH
R
Address:
DBGMCUBaseAddress + 0x0FBC
Type:
R
Reset:
0x0410 0000
Description:
CS Device Architecture Register. See CoreSight Architecture Spec for further details.
This register can be read only if NIDEN is active - DBGMCU non-invasive debug.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
[31:0] DEV_ARCH: "This field is used to identifies the architect and the architecture of the CS
component."
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DEVTYPE
Device Type Register
9
8
7
6
5
4
3
RESERVED0
DEV_TYPE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
2
1
Address:
DBGMCUBaseAddress + 0x0FCC
Type:
R
Reset:
0x0004
Description:
CS Device Type Register. See CoreSight Architecture Spec for further details. This
register can be read only if NIDEN is active - DBGMCU non-invasive debug.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
0
[31:8] RESERVED0: "This field is reserved. It must be kept to zero by the software."
[7:0] DEV_TYPE: "This field is used to identifies the type of CS component: 0x4 to identifies a
generic debug control component."
PIDR4
Peripheral Identification Register 4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PIDR4_VAL
R
Address:
DBGMCUBaseAddress + 0x0FD0
Type:
R
Reset:
0x0000
Description:
CS Peripheral Identification Register 4. See CoreSight Architecture Spec for further
details. This register can be read only if NIDEN is active - DBGMCU non-invasive
debug.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
[31:0] PIDR4_VAL: "Peripheral Identification Register 4"
PIDR5
Peripheral Identification Register 5
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PIDR5_VAL
R
Address:
DBGMCUBaseAddress + 0x0FD4
Type:
R
Reset:
0x0000
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8
7
6
5
4
3
2
1
0
RM0483
Debug support (DBG)
Description:
CS Peripheral Identification Register 5. See CoreSight Architecture Spec for further
details. This register can be read only if NIDEN is active - DBGMCU non-invasive
debug.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
[31:0] PIDR5_VAL: "Peripheral Identification Register 5"
PIDR6
Peripheral Identification Register 6
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PIDR6_VAL
R
Address:
DBGMCUBaseAddress + 0x0FD8
Type:
R
Reset:
0x0000
Description:
CS Peripheral Identification Register 6. See CoreSight Architecture Spec for further
details. This register can be read only if NIDEN is active - DBGMCU non-invasive
debug.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
[31:0] PIDR6_VAL: "Peripheral Identification Register 6"
PIDR7
Peripheral Identification Register 7
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PIDR7_VAL
R
Address:
DBGMCUBaseAddress + 0x0FDC
Type:
R
Reset:
0x0000
Description:
CS Peripheral Identification Register 7. See CoreSight Architecture Spec for further
details. This register can be read only if NIDEN is active - DBGMCU non-invasive
debug.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
[31:0] PIDR7_VAL: "Peripheral Identification Register 7"
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Debug support (DBG)
RM0483
PIDR0
Peripheral Identification Register 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PIDR0_VAL
R
Address:
DBGMCUBaseAddress + 0x0FE0
Type:
R
Reset:
0x0000
Description:
CS Peripheral Identification Register 0. See CoreSight Architecture Spec for further
details. This register can be read only if NIDEN is active - DBGMCU non-invasive
debug.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
[31:0] PIDR0_VAL: "Peripheral Identification Register 0"
PIDR1
Peripheral Identification Register 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PIDR1_VAL
R
Address:
DBGMCUBaseAddress + 0x0FE4
Type:
R
Reset:
0x0000
Description:
CS Peripheral Identification Register 1. See CoreSight Architecture Spec for further
details. This register can be read only if NIDEN is active - DBGMCU non-invasive
debug.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
[31:0] PIDR1_VAL: "Peripheral Identification Register 1"
PIDR2
Peripheral Identification Register 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PIDR2_VAL
R
Address:
DBGMCUBaseAddress + 0x0FE8
Type:
R
Reset:
0x000A
Description:
CS Peripheral Identification Register 2. See CoreSight Architecture Spec for further
details. This register can be read only if NIDEN is active - DBGMCU non-invasive
debug.
access_size: 32
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RM0483
Debug support (DBG)
min_write_access_size: 32
min_read_access_size: 32
[31:0] PIDR2_VAL: "Peripheral Identification Register 2"
PIDR3
Peripheral Identification Register 3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PIDR3_VAL
R
Address:
DBGMCUBaseAddress + 0x0FEC
Type:
R
Reset:
0x0000
Description:
CS Peripheral Identification Register 3. See CoreSight Architecture Spec for further
details. This register can be read only if NIDEN is active - DBGMCU non-invasive
debug.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
[31:0] PIDR3_VAL: "Peripheral Identification Register 3"
CIDR0
Component Identification Register 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CIDR0_VAL
R
Address:
DBGMCUBaseAddress + 0x0FF0
Type:
R
Reset:
0x000D
Description:
CS Component Identification Register 0. See CoreSight Architecture Spec for further
details. This register can be read only if NIDEN is active - DBGMCU non-invasive
debug.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
[31:0] CIDR0_VAL: "Component Identification Register 0"
CIDR1
Component Identification Register 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CIDR1_VAL
R
Address:
DBGMCUBaseAddress + 0x0FF4
Type:
R
Reset:
0x0090
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Debug support (DBG)
Description:
RM0483
CS Component Identification Register 1. See CoreSight Architecture Spec for further
details. This register can be read only if NIDEN is active - DBGMCU non-invasive
debug.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
[31:0] CIDR1_VAL: "Component Identification Register 1"
CIDR2
Component Identification Register 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CIDR2_VAL
R
Address:
DBGMCUBaseAddress + 0x0FF8
Type:
R
Reset:
0x0005
Description:
CS Component Identification Register 2. See CoreSight Architecture Spec for further
details. This register can be read only if NIDEN is active - DBGMCU non-invasive
debug.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
[31:0] CIDR2_VAL: "Component Identification Register 2"
CIDR3
Component Identification Register 3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CIDR3_VAL
R
Address:
DBGMCUBaseAddress + 0x0FFC
Type:
R
Reset:
0x00B1
Description:
CS Component Identification Register 3. See CoreSight Architecture Spec for further
details. This register can be read only if NIDEN is active - DBGMCU non-invasive
debug.
access_size: 32
min_write_access_size: 32
min_read_access_size: 32
[31:0] CIDR3_VAL: "Component Identification Register 3"
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RM0483
Reset and clock control (RCC)
11
Reset and clock control (RCC)
11.1
Reset
There are two types of reset, defined as destructive reset and functional reset.
Refer to Chapter 6: Reset and Boot for detailed information.
The reset source can be identified by checking the flags in the destructive event status
register (DESR) and functional event status register (FESR).
11.2
Clocks
Five different clock sources can be used to drive the system clock (SYSCLK):
• Internal RC oscillator 16 MHz (IRCOSC)
• External crystal oscillator 4-40 MHz (XOSC)
• PLL0 clock
• PLL1 clock
• SSCG - Speed Spectrum Clock Generator (FM)
The IRCOSC is used as system clock source after startup from Reset.
The devices have the following additional clock sources: 1 MHz low speed internal RCOSC
(LSIRCOSC) which can drive the RTC and the UARTs.
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
Fixed prescalers are configuring the frequencies of the AHB, APB1 and APB2 domains.
All the peripheral kernel clocks are derived from their bus clock (HCLK, PCLK1 or PCLK2)
except:
• The ADCs clock which is derived (selected by software) from one of the following sources:
–
PLL0 clock
–
PLL1 clock
–
XOSC clock
• The UARTs clocks which are derived (selected by software) from one of the four following
sources:
–
PLL0
–
IRCOSC clock
–
XOSC clock
–
LSICLK clock
2
• The I Cs clocks which are derived (selected by software) from one of the three following
sources:
–
PLL0 clock
–
IRCOSC clock
–
XOSC clock
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Reset and clock control (RCC)
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• The RTC clock which is derived (selected by software) from one of the following sources:
–
LSICLK clock
–
XOSC clock divided by 32
• The IWDG clock which is always the IRCOSC clock.
• The FDCAN1 clock, which is derived (selected by software) from one of the two following
sources:
–
XOSC clock
–
PLL0 clock
The FCCU clock is always the IRCOSC clock. The STCU clock is always SYSCLK clock.
The RCC feeds the Cortex® System Timer (SysTick) external clock with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or directly with the Cortex®
clock (HCLK), configurable in the SysTick Control and Status Register.
FCLK acts as Cortex®-M7 free-running clock. For more details refer to the Cortex®-M7
technical reference manual (see http://infocenter.arm.com).
Table 108. Maximum IP clock frequencies
IP clock
Peripherals
Clock selector
Max division
factor
Division factor
at reset
Max frequency
(MHz)
UART_CLK
UART
UART_SEL
32
3
100
I2C_CLK
I2C
I2C_SEL
32
3
100
I2S_CLK
I2S
I2S_SEL
32
3
100
FDCAN_CLK
FDCAN
FDCAN_SEL
32
4
80
ADC_CLK
ADC
ADC_SEL
126
6
40
SD_ADC_CLK
SD_ADC
SD_ADC_SEL
126
18
16
HRTIM_CLK
HRTIM
System clock
switch
—
—
FSYS (max)
APB1_CLK
APB1
—
—
—
FSYS (max) / 4
APB2_CLK
APB2
—
—
—
FSYS (max) / 2
TIMx_CLK
x = 2, 3, 6, 7, TS
TIMx
x = 2, 3, 6, 7, TS
—
—
—
FSYS (max) / 2
TIMy_CLK
y = 1, 4, 5, 8, 15,
16
TIMy
y = 1, 4, 5, 8, 15,
16
—
—
—
FSYS (max)
HSM_CLK
HSM
—
—
—
FSYS (max) / 2
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RM0483
Reset and clock control (RCC)
Figure 46. Clock tree
Legenda:
CMU = clock monitoring unit
PRCD = pseudo random clock divider
EXTAL
XOSC
4-40MHz
PLL0:PHI
PHI
XOSC
PLL0
IRCOSC
XTAL
IRCOSC
IRCOSC
16MHz
PLL0:PHI1
PHI1
XOSC
PLL0:PHI
16 MHz
to IWDGx, FCCU
PLL1:PHI
PLL1
(SSCG)
PHI
PLL1:PHI
XOSC
IRCOSC
IRCOSC
PLL0
LSICLK
to STCU
XOSC
PLL0:PHI
CMU_0
CMU_1
IRCOSC
to COREx clocks
XOSC
PLL0:PHI
Progressive
Clock
Switching
(PCS)
SYSCLK
SYS_DIV
/1,2,3,4,…,512
SYSCLK_DIV
to CHKR_COREx clocks
to COREx Systick clock
/8
PLL1:PHI
to AXI and AHB bus, memories and DMAs
to HRTIMx
PLL0:PHI
to HSM
IRCOSC
XOSC
/2
/1,2,3,…,32
to UARTx
LSICLK
APB1 DIV
/4
PCLK1
APB2 DIV
/2
PCLK2
CMU_2
to APB1 peripherals
x2
PLL0:PHI
IRCOSC
to I2Cx
/1,2,3…,32
to APB2 peripherals
x2
XOSC
to TIMx
x=2,3,6,7,TS
to TIMx
x=1,8,4,5,15,16
CMU_3
ATB_TPIU_CLK
PLL0:PHI
APB2 DIV
/1,2,…,8
IRCOSC
XOSC
I2S_CKIN
/1,2,3…,32
LSICLK
to I2S2/3
(used only by SPI with I2S mode)
IRCOSC
MCO
XOSC
PLL0:PHI
/1,2,…,64
Jitter enable
PLL0:PHI
XOSC
/1,2,3,…,32
PRCD
to FDCAN
PLL1:PHI
PLL0:PHI
CMU_4
PLL1:PHI
to ADC analog
50% duty cycle
XOSC
LSICLK
LSI
RC 1MHz
/1,2,3,…,126
/1,2,…,32
XOSC
to RTC
/32
PLL0:PHI
CMU_5
PLL1:PHI
LSCO
/1,2,3,…,126
XOSC
Note:
to SD analog
50% duty cycle
For full details about the internal and external clock source characteristics, refer to the
“Electrical characteristics” section in the device datasheet.
The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a
programmable factor (1, 2 or 4). When the programmable factor is ‘1’, the AHB prescaler
must be equal to ‘1’.
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Reset and clock control (RCC)
11.2.1
RM0483
External oscillator (XOSC)
The external crystal oscillator clock signal (XOSC) can be generated from two possible
clock sources:
• XOSC external crystal
• XOSC user external clock
The external crystal and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
Table 109. XOSC clock sources
Clock source
Hardware configuration
XTAL
EXTAL
External clock
External
source
MSv31915V1
EXTAL
Crystal
XTAL
CL2
CL1
Load
capacitors
MSv31916V1
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RM0483
Reset and clock control (RCC)
External crystal
The 4 to 40 MHz external oscillator has the advantage of producing a very accurate rate on
the main clock.
The associated hardware configuration is shown in Table 109. Refer to the electrical
characteristics section of the datasheet for more details.
The XOSCRDY flag in the Clock Sources Control Register (CR) indicates if the XOSC
oscillator is stable or not. Once enabled, the clock is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the Clock Interrupt / Fault Enable
(CIER).
The XOSC Crystal can be switched on and off using the XOSCON bit in the Clock Sources
Control Register (CR).
External source (bypass)
In this mode, an external clock source must be provided. You select this mode by setting the
XOSCBYP and XOSCON bits in the Clock Sources Control Register (CR). The external
clock signal has to drive the EXTAL pin (refer to the datasheet for the proper values). See
Table 109.
Automatic level control (ALC)
The function of the ALC block is to provide high drive current during oscillator start up, and
reduce current after oscillation to reduce power, distortion, RFI, and to avoid overdriving the
crystal. ALC block can be controlled with DCF by configuring the UTEST miscellaneous bit
14 [XOSC_ALC_DIS]. Comparing the configurations with ALC disabled against the case
with ALC enabled, there are the following attributes:
•
Higher oscillation amplitudes at crystal.
•
Distorted oscillation with several harmonics.
•
Increased EMI.
•
Higher crystal drive level.
•
Less susceptible to noise.
The ALC enable configuration is suitable for most applications. The amplitude of oscillations
is lower, hence there are less distortion in oscillations, less EMI, and less crystal drive level.
Feedback resistor is integrated. It does not require external resistors by offering a lower cost
solution and simpler PCB design.
Note:
It is recommended to make ALC feature enabled (that is, XOSC_ALC_DIS = 0) for low
dissipation in crystal (crystal drive level).
11.2.2
Internal RC oscillator (IRCOSC)
The IRCOSC clock signal is generated from an internal 16 MHz RC Oscillator.
The IRCOSC RC oscillator has the advantage of providing a clock source at low cost (no
external components). It also has a faster startup time than the XOSC crystal oscillator
however, even with calibration the frequency is less accurate than an external crystal
oscillator.
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Reset and clock control (RCC)
RM0483
Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated. Refer to the device datasheet for
calibration accuracy.
After reset, the factory calibration value is loaded in the IRCOSC_TRIM[7:0] bits in the
Internal Clock Sources Calibration Register (ICSR).
If the application is subject to voltage or temperature variations this may affect the RC
oscillator speed. You can trim the IRCOSC frequency in the application using the
IRCOSC_TRIM_USER[6:0] in the Internal Clock Sources Calibration Register (ICSR).
For more details on how to measure the IRCOSC frequency variation, refer to
Section 11.2.13: Internal/external clock measurement with TIM5/TIM15/TIM16.
The IRCOSCRDY flag in the Clock Sources Control Register (CR) indicates if the IRCOSC
oscillator is stable or not. At startup, the IRCOSC output clock is not released until this bit is
set by hardware.
Frequency Trimming
In order to compensate for the process variation of Resistor and Capacitor, an 8-bit
frequency trimming is used. The pins used for this purpose are TRIM_BIT<7:0>. Out of
these, TRIM_BIT<7:5> are used as course trimming bits, which are provided as input to
cap- trimming circuitry. Further, TRIM_BIT<4:0> are used as fine trimming bits, which are
provided as input to res-trimming circuitry. Along with TRIM_BIT<7:0> user is also provided
with a trimming capability. TRIM_BIT_USER<4:0> is in user control to trim the frequency.
Table 110. Course Trimming
S. No.
TRIM_BIT<7:5>
Frequency
1
100
F + 62.0%
2
101
F + 44.1%
3
110
F + 28.2%
4
111
F + 12.8%
5
000
F
6
001
F - 11.2%
7
010
F - 21.8%
8
011
F - 30.9%
Table 111. FINE Trimming
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S. No.
TRIM_BIT<4:0>
Frequency
1
10000
F + 11.1%
2
10001
F + 10.3%
3
10010
F + 9.6%
4
10011
F + 8.8%
5
10100
F + 8.1%
RM0483 Rev 5
RM0483
Reset and clock control (RCC)
Table 111. FINE Trimming (continued)
S. No.
TRIM_BIT<4:0>
Frequency
6
10101
F + 7.3%
7
10110
F + 6.6%
8
10111
F + 5.9%
9
11000
F + 5.2%
10
11001
F + 4.5%
11
11010
F + 3.8%
12
11011
F + 3.2%
13
11100
F + 2.5%
14
11101
F + 1.8%
15
11110
F + 1.2%
16
11111
F + 0.6%
17
00000
F
18
00001
F - 0.6%
19
00010
F - 1.2%
20
00011
F - 1.8%
21
00100
F - 2.4%
22
00101
F - 3.0%
23
00110
F - 3.6%
24
00111
F - 4.2%
25
01000
F - 4.7%
26
01001
F - 5.3%
27
01010
F - 5.9%
28
01011
F - 6.4%
29
01100
F - 7.0%
30
01101
F - 7.5%
31
01110
F - 8.1%
32
01111
F - 8.6%
31
01110
F - 8.1%
32
01111
F - 8.6%
When simulated at Typical Corner of DK_cmosm40_1.1.2, at AVDD12=1.2 V and
Temperature of 27 °C, the frequency at TRIM_BIT<7:0> = <00000000> was found to be
14.828 MHz. This value is subject to process, supply and temperature values. In order to
guarantee frequency trimmability across process, default value around 15 MHz has been
chosen with respect to nominal 16 MHz.
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Reset and clock control (RCC)
RM0483
User Trimming
User trim code consists of two parts, MSB represents the sign bit (current source or sink)
while TRIM_BIT_USER<4:0> represents the actual code. If MSB is kept zero, then
increasing the TRIM_BIT_USER<4:0> by one step decreases the frequency stepwise.
Similarly if MSB is kept 1, then increasing the TRIM_BIT_USER<4:0> by one step increases
the frequency stepwise.
Table 112 summarizes the expected variation on output frequency.
Table 112. USER Trimming
260/2075
S. No.
TRIM_BIT_USER<5:0>
Frequency
-32
100000
F1+5.16%
-31
100001
F1+5.16%
-30
100010
F1+5.16%
-29
100011
F1+5.16%
-28
100100
F1+5.16%
-27
100101
F1+5.16%
-26
100110
F1+5.16%
-25
100111
F1+5.16%
-24
101000
F1+5.16%
-23
101001
F1+5.16%
-22
101010
F1+5.16%
-21
101011
F1+5.16%
-20
101100
F1+5.16%
-19
101101
F1+5.16%
-18
101110
F1+5.16%
-17
101111
F1+5.16%
-16
110000
F1+5.16%
-15
110001
F1+4.83%
-14
110010
F1+4.50%
-13
110011
F1+4.17%
-12
110100
F1+3.84%
-11
110101
F1+3.51%
-10
110110
F1+3.19%
-9
110111
F1+2.86%
-8
111000
F1+2.54%
-7
111001
F1+2.22%
-6
111010
F1+1.89%
-5
111011
F1+1.57%
RM0483 Rev 5
RM0483
Reset and clock control (RCC)
Table 112. USER Trimming (continued)
S. No.
TRIM_BIT_USER<5:0>
Frequency
-4
111100
F1+1.25%
-3
111101
F1+0.94%
-2
111110
F1+0.62%
-1
111111
F1+0.31%
0
000000
F1=16MHz
1
000001
F1-0.29%
2
000010
F1-0.58%
3
000011
F1-0.87%
4
000100
F1-1.17%
5
000101
F1-1.45%
6
000110
F1-1.74%
7
000111
F1-2.02%
8
001000
F1-2.30%
9
001001
F1-2.59%
10
001010
F1-2.87%
11
001011
F1-3.15%
12
001100
F1-3.43%
13
001101
F1-3.71%
14
001110
F1-3.98%
15
001111
F1-4.26%
16
010000
F1-4.53%
17
010001
F1-4.53%
18
010010
F1-4.53%
19
010011
F1-4.53%
20
010100
F1-4.53%
21
010101
F1-4.53%
22
010110
F1-4.53%
23
010111
F1-4.53%
24
011000
F1-4.53%
25
011001
F1-4.53%
26
011010
F1-4.53%
27
011011
F1-4.53%
28
011100
F1-4.53%
29
011101
F1-4.53%
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Reset and clock control (RCC)
RM0483
Table 112. USER Trimming (continued)
11.2.3
S. No.
TRIM_BIT_USER<5:0>
Frequency
30
011110
F1-4.53%
31
011111
F1-4.53%
PLL
The Dual PLL provides separate system and peripheral clocks as shown in Figure 46: Clock
tree.
The PLLs are disabled after power is cycled and must be enabled by software.
The block diagram for the Dual PLL structure is shown in Figure 47.
Figure 47. Dual PLL structure
EXTAL
XOSC
XTAL
RCC
PLL0
Clock Source
Selector
RCC
PLL1
Clock Source
Selector
PHI1
PLL0
PLL1
PHI
Lock
pll1_cl
PHI
Lock
16 MHz
IRC
OSC
pll0_cl
PREDIV RFD1 RFD2 MFD
Control/Status
Registers
RFD
MFD
PLLDIG
PLL0: base PLL (non-FM)
This primary PLL provides a clock that is not Frequency Modulated to the peripheral IPs and
the reference clock to PLL1.
The input clock sources for PLL0 are:
– XOSC
– IRCOSC
– The external reference clock (input on the EXTAL pin)
The output clocks from PLL0 are:
– PHI: drives the peripheral clock and the system clock when PLL1 is not locked or
active.
– PHI1: provides the input reference clock for PLL1.
PLL1: FMPLL
PLL1 is a Frequency Modulated PLL (FMPLL) that is used to drive the system clock.
The input clocks to PLL1 are:
– PHI1 output clock from PLL0
– XOSC
The output clock from PLL1 is:
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Reset and clock control (RCC)
– PHI: drives the system clock. The PHI output clock contains a fractional divider that
can be applied to the loop divide of the PLL to achieve good granularity in the PLL1
PHI output clock frequency.
PLL register interface
This device has a single digital interface for the dual PLLs. The digital interface provides
register control of all features of the PLLs. Details are provided in the Chapter 12: Dual PLL
digital interface (PLLDIG).
Loss of clock detection
Loss of clock detection must be enabled at all times when the PLLs are enabled.
XOSC loss of Clock event from CMU0 and loss of lock events from PLL0 and PLL1 are
routed as fault to FCCU, where there is a software option to generate a reset or interrupt
related to each fault condition.
Software may enable or disable an optional backup switch to safe clock in case of XOSC
loss of clock or PLLs loss of lock, setting the corresponding bits in CRRCR.
PLLs initialization sequence
Refer to Section 12.7: Initialization information in Chapter 12: Dual PLL digital interface
(PLLDIG) for the initialization sequence of PLL0 and PLL1 at device start-up.
11.2.4
Low speed internal RC oscillator (LSIRCOSC)
The LSI RC can clock the RTC through a programmable prescaler. The clock frequency is
1 MHz. For more details, refer to the electrical characteristics section of the datasheet.
The LSI RC can be switched on and off using the LSION bit in the Clock Sources Control
Register (CR).
The LSIRDY flag in the Clock Sources Control Register (CR) indicates if the LSI oscillator is
stable or not. At startup, the clock is not released until this bit is set by hardware. An
interrupt can be generated if enabled in the Clock Interrupt / Fault Enable (CIER).
11.2.5
System clock (SYSCLK) selection
Four different clock sources can be used to drive the system clock (SYSCLK):
Note:
–
IRCOSC oscillator
–
XOSC oscillator
–
PLL0
–
PLL1
Refer to SR5E1x Datasheet for actual electrical parameters and characteristics.
After a system reset, the IRCOSC oscillator is selected as system clock. When a clock
source is used directly or through the PLL as a system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is
selected, the switch occurs when the clock source becomes ready. Status bits in the Internal
Clock Sources Calibration Register (ICSR) indicate which clock(s) is (are) ready and which
clock is currently used as a system clock.
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To switch from low speed to high speed or from high speed to low speed system clock, it is
recommended to use a transition state with medium speed clock, for at least 1 µs.
Clock source switching conditions:
• Switching from XOSC or IRCOSC to PLL with AHB frequency (HCLK) higher than 80 MHz
• Switching from PLL with HCLK higher than 80 MHz to XOSC or IRCOSC
Transition state:
• Set the AHB prescaler HPRE[3:0] bits to divide the system frequency by 2
• Switch system clock to PLL
• Wait for at least 1 µs and then reconfigure AHB prescaler bits to the needed HCLK
frequency
11.2.6
System clock switching to IRCOSC
In case of unrecoverable failures involving the clocks that can bring to the loss of system
clock, the main system clock can be switched on IRCOSC.
The RCC_CRRCR allows to control which event can generate a Switching to IRCOSC
clock. Default value is disabled for each event.
Switching on IRCOSC is routed as fault event to FCCU.
The switch of the system clock to IRCOSC must happen in case one of the following events
occurs and if the system clock is derived from the clock source, interested by the fail:
• XOSC loss, signaled by CMU_0. In addition, this signal is routed separately to FCCU too.
• PLL0 loss of lock. In addition, this signal is routed separately to FCCU too.
• PLL1 loss of lock. In addition, this signal is routed separately to FCCU too.
• CMU1 out of range. In addition, this signal is routed separately to FCCU too.
11.2.7
ADC clock
The ADC clock is derived from the XOSC, the PLL0 or the PLL1 via a prescaler. It can reach
306 MHz and can be divided by the following prescalers values: 1, 2, 4, 6, 8, 10,... 126 by
configuring the ADC_PRE field of CCIPR2 register. It is asynchronous to the AHB clock.
Alternatively, the ADC clock can be derived from the AHB clock of the ADC bus interface,
divided by a programmable factor (1, 2 or 4). This programmable factor is configured using
the CKMODE bit fields in the ADCx_CCR.
If the programmed factor is ‘1’, the AHB prescaler must be set to ‘1’.
11.2.8
RTC clock
The RTCCLK clock source can be either the XOSC/32 or LSI clock. It is selected by
programming the RTCSEL[1:0] bits in the Low Speed Clock Configuration register
(LSCFGR). This selection cannot be modified without resetting the RTC domain. The
system must always be configured so as to get a PCLK frequency greater than or equal to
the RTCCLK frequency for a proper operation of the RTC.
Note:
If LSI is selected as the RTC clock:
The RTC state is not guaranteed if the VDD supply is powered off.
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Note:
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If the XOSC clock divided by a prescaler is used as the RTC clock:
The RTC state is not guaranteed if the VDD supply is powered off or if the internal voltage
regulator is powered off (removing power from the VCORE domain).
When the RTC clock is LSI, the RTC remains clocked and functional under system reset.
11.2.9
LSICLK clock branch
LSICLK clock is the LSIRCOSC clock divided by a prescaler configured by LSI_PRE field of
LSCFGR RCC register.
11.2.10
Timer clock
The timer clock frequencies are automatically defined by hardware. They are set to twice
(×2) the frequency of the APB domain.
11.2.11
Watchdog clock
IWDG kernel clock is the IRCOSC that is always on.
11.2.12
Clock-out capability
• M2CO
The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. One of the five clock signals can be selected as the MCO clock:
–
LSIRCOSC
–
IRCOSC
–
XOSC
–
PLL0
–
PLL1
The selection is controlled by the MCOSEL[3:0] bits of the Clock Configuration Register
(CFGR). The selected clock can be divided with the MCOPRE[2:0] field of the Clock
Configuration Register (CFGR).
• LSCO
Another output (LSCO) allows one of the following low speed clocks to be output onto
the external LSCO pin:
–
LSI can be divided by its dedicated prescaler
–
XOSC/32
The selection is controlled by the LSCOSEL, and enabled with the LSCOEN in the Low
Speed Clock Configuration register (LSCFGR).
The MCO clock output requires the corresponding alternate function selected on the MCO
pin, the LSCO pin must be left in default POR state.
11.2.13
Internal/external clock measurement with TIM5/TIM15/TIM16
It is possible to indirectly measure the frequency of all on-board clock sources by means of
the TIM5, TIM15, TIM16 channel 1 input capture, as represented in Figure 48 and
Figure 49.
The input capture channel of the Timer 15 can be a GPIO line.
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TIM15 Channel1 is connected to the GPIO. Refer to the alternate function mapping in the
SR5E1x pinout Microsoft Excel® file attached to the IO_Definition document.
Figure 48. Frequency measurement with TIM16 in capture mode
TIM 16
TI1SEL in
TIM16_TISEL
GPIO
LSI
TI1
Reserved
HSE/32
MCO
MS48964V1
The input capture channel of the Timer 16 can be a GPIO line or an internal clock of the
MCU.
The possibilities are the following ones:
• TIM16 Channel1 is connected to the GPIO. Refer to the alternate function mapping in the
SR5E1x pinout Microsoft Excel® file attached to the IO_Definition document.
• TIM16 Channel1 is connected to the LSI clock.
• TIM16 Channel1 is connected to the XOSC/32 clock.
• TIM16 Channel1 is connected to the MCO.
Figure 49. Frequency measurement with TIM5 in capture mode
TIM 5
TI1SEL in
TIM5_TISEL
GPIO
LSI
TI1
Reserved
MSv45853V1
The input capture channel of the Timer 5 can be a GPIO line or an internal clock of the
MCU.
The possibilities are the following ones:
• TIM5 Channel1 is connected to the GPIO. Refer to the alternate function mapping in the
SR5E1x pinout Microsoft Excel® file attached to the IO_Definition document.
• TIM5 Channel1 is connected to the LSI Clock.
Calibration of the IRCOSC
For TIM16, the primary purpose of connecting the XOSC/32 to the channel 1 input capture
is to be able to precisely measure the IRCOSC system clocks (for this, the IRCOSC must be
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used as the system clock source). The number of IRCOSC clock counts between
consecutive edges of the XOSC/32 signal provides a measure of the internal clock period.
Taking advantage of the high precision of XOSC/32 crystals (typically a few tens of ppm’s), it
is possible to determine the internal clock frequency with the same resolution, and trim the
source to compensate for manufacturing, process, temperature and/or voltage related
frequency deviations.
The IRCOSC oscillator has dedicated user-accessible calibration bits for this purpose.
The basic concept consists in providing a relative measurement (for example the ratio
between IRCOSC and XOSC/32): the precision is therefore closely related to the ratio
between the two clock sources. The higher the ratio is, the better the measurement is.
11.2.14
Peripheral clock enable register
(RCC_AHBxENR, RCC_APBxENR)
Each peripheral clock can be enabled by the xxxxEN bit of the RCC_AHBxENR,
RCC_APBxENR registers.
When the peripheral clock is not active, the peripheral registers read or write accesses are
not supported.
The enable bit has a synchronization mechanism to create a glitch free clock for the
peripheral. After the enable bit is set, there is a 2 clock cycles delay before the clock is
active.
Caution:
Just after enabling the clock for a peripheral, software must wait for a delay before
accessing the peripheral registers.
11.3
Clock monitoring
For all safety relevant clocks the microcontroller uses clock monitoring units (CMUs) to
detect a missing clock or incorrect frequency.
Each CMU is programmed independently (refer to Figure 46 for CMU distribution) and uses
the IRCOSC or XOSC as the clock monitor reference.
Detailed information on the CMUs can be found in the Clock Monitor Unit chapter.
11.3.1
CMU configuration
This section explains the CMU configuration.
Figure 50 shows the block diagram for CMU0 on the SR5E1x.
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Figure 50. CMU0 block diagram
CMU_CSR[CKSEL1]
CLKMT1 (LSIRCOSC) 01
CMU_MDR
CLK_SEL
N/A 10
CLKMT0_RMN (IRCOSC)
00,11
Frequency Meter
CMU_FDR
CLKMN0_RMT (XOSC)
(from RCC)
CLKMN0_RMT_ACTIVE
CLKMN0_RMT Supervisor
fCLKMN0_RMT < fCLKMT0_RMN / 2RCDIV
OLR
CLKMN1 Supervisor
Fixed
Prescaler
/4
CMU_HREF
fCLKMN1 > hfref
CLKMN1
(monitored clock)
FHH
fCLKMN1 < lfref
FLL
CMU_LFREF
CLKMN1_ACTIVE
(from RCC)
Figure 51 shows the block diagram for the other CMUs on the SR5E1x.
Figure 51. Other CMUs block diagram
CLKMT0_RMN (IRCOSC)
CLKMN1 Supervisor
Fixed
Prescaler
/4
CLKMN1
(monitored clock)
CMU_HREF
fCLKMN1> hfref
fCLKMN1 < lfref
FHH
FLL
CMU_LFREF
CLKMN1_ACTIVE
(from RCC)
11.3.1.1
Clock input sources
Table 113 shows the clocks that are monitored by each CMU. These signals are connected
internally on the chip, but are not accessible via pins on the boundary of the device.
IRCOSC is the reference clock for all clock monitors. Only CMU0 implements the XOSC
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monitor. CMU0 uses the IRCOSC clock to measure if the XOSC is too low. CMU0 can also
be used to calibrate the IRCOSC frequency using the XOSC. All other CMUs are configured
identically.
Table 113. Clock input sources
Clock module
Monitored clock
CMU group
CMU_0_PLL0_XOSC_IRCOSC
PLL0:PHI, XOSC, IRCOSC, LSIRCOSC
—
CMU_1_CORE
SYS_CLK
CMU_Platform
CMU_2_APB1
APB1_CLK
CMU_Platform
CMU_3_APB2
APB2_CLK
CMU_Platform
CMU_4_SARADC
SARADC_CLK
CMU_other
CMU_5_SDADC
SDADC_CLK
CMU_other
Table 114. CMU clock signals
Clock
signals
Functions
CLKMT1
Measured clock against
CLKMN0_RMT.
CLKMN1
Monitored clock (CLKMT0_RMN as
reference).
CMU_0
CMU_1
CMU_3
LSIRCOSC
CMU_4
CMU_5
—
Refer to Table 113: Clock input sources.
– Reference clock for CLKMN1
monitoring.
CLKMT0_
RMN
– Measured clock against
CLKMN0_RMT.
IRCOSC
– Reference clock for
CLKMT0_RMN measure.
CLKMN0_
RMT
– Monitored clock, lower limit only
(CLKMNT0_RMN as reference).
11.3.1.2
CMU_2
XOSC
—
CMU registers and field availability
Table 115 specifies which registers and fields are available for a given CMU.
Table 115. CMU register availability
Address
offset
Register
CMU
Note
0x0000
CMU_CSR
All
CMU_CSR[SFM] and CMU_CSR[CKSEL1] in CMU0 only.
0x0004
CMU_FDR
CMU0
—
0x0008
CMU_HFREFR
All
—
0x000C
CMU_LFREFR
All
—
0x0010
CMU_ISR
All
CMU_ISR[OLRI] in CMU0 only.
0x0014
Reserved
—
—
0x0018
CMU_MDR
CMU0
—
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11.3.1.3
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CMU register write protection
The CMU registers defined in Table 116 have write protection with:
• Soft locking: can be unlocked by software after being previously locked.
• Hard locking: can only be unlocked by a reset once locked.
The REG_PROT module is used to implement the CMU register write protection (refer to
Section 5.8.6: REG_PROT configuration in Chapter 5: Device configuration for details).
Table 116. CMU register write protection
Register(1)
Offset
0x0000
CMU Control Status Register (CMU_CSR)
0x0004
CMU Frequency Display Register (CMU_FDR)
0x0008
CMU High Frequency Reference Register CLKMN1 (CMU_HFREFR)
0x000C
CMU Low Frequency Reference Register CLKMN1 (CMU_LFREFR)
0x0010
CMU Interrupt Status Register (CMU_ISR)
0x0014
Reserved
0x0018
CMU Measurement Duration Register (CMU_MDR)
1. Refer to Register Protection chapter for bit field details.
11.3.2
PLL0 monitor
Software can program an upper and lower limit on the expected PLL0 PHI output clock
frequency. If the monitor is enabled and the measured frequency is above or below the
limits, a flag bit is set and an interrupt, if enabled, is generated. The default condition of the
clock monitor is disabled.
11.3.3
External oscillator (XOSC) monitor
The XOSC frequency is compared with a minimum value limit. If the measured XOSC
frequency is below the limit, a flag is set and an interrupt, if enabled, is generated.
11.3.4
Internal RC oscillator (IRCOSC) monitor
The period of the IRCOSC can be measured in CMU0, using the XOSC as a reference. This
allows for application trimming of the IRCOSC frequency.
11.3.5
System clock monitors
A CMU is assigned to monitor the frequency of the peripheral bridges, peripheral, and ADC
clocks (refer to Figure 46).
11.3.6
Progressive system clock switching
In order to prevent sudden voltage drops and overshoots due to frequency and load
changes, the RCC can ramp the system clock frequency down and/or up based on the
power level values of the current and target modes.
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During ramp-down, the rate of the frequency change is based on the RCC_PCS_SDUR,
RCC_PCS_DIVCn, and RCC_PCS_DIVEn registers, where n corresponds to the current
system clock source selection.
During ramp-up, the rate of the frequency change is based on the RCC_PCS_SDUR,
RCC_PCS_DIVCn, and RCC_PCS_DIVSn registers, where n corresponds to the target
system clock source selection.
11.3.6.1
Generic clock change requirements
For a maximum allowed change of the frequency (fchg) and for a given source clock
frequency fsrc (current or target clock source), the maximum allowed frequency change rate
amax is given in Equation 1: .
Equation 1
f chg
a max = --------f src
11.3.6.2
Configuration of RCC_PCS_SDUR
The switch duration field RCC_PCS_SDUR[SDUR] defines the duration of one system clock
switch step in terms of 16 MHz int. RC osc.. After the expiration of this time, the module
changes the clock divider value which changes the frequency of the system clock.
11.3.6.3
Configuration of RCC_PCS_DIVCn[RATE]
For a given maximum allowed frequency change rate amax the value d to be programmed
into the PCS_DIVCn[RATE] register is given in Table 117.
Table 117. RCC_PCS_DIVCn[RATE] values
11.3.6.4
amax
d
RCC_PCS_DIVCn[RATE]
0.05
0.012
12
0.10
0.048
48
0.15
0.112
112
0.20
0.184
184
Generic clock change properties
The number k of required steps to reach or leave the divided system clock with frequency
fdiv from the source clock with frequency fsrc is given in Equation 2: .
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Equation 2
k =
11.3.6.5
f src
2  1 – -------------------
16MHz
0.5 + 0.25 – ------------------------------------d
Clock ramp-down
The clock ramp-down starts with the divider value 1 and with the given divider increment
value PCD_DIVCn[RATE] and ends with the given divider value PCS_DIVEn[DIVE].
The divider end value for clock ramp-down is given in Equation 3: .
Equation 3
f src
PCS_DIVEn[DIVE] = ------------------- × 1000 – 1
16MHz
Where fcurr is the frequency of the currently selected system clock source.
Figure 52. System clock ramp-down timing (k = 6 example)
f
fcurr
≤ a × fcurr
RCC_PCS_SDUR
fcurr ÷ PCS_DIVEn[DIVE]
16MHz
1
11.3.6.6
2
3
busy
4
5
6
steps
Clock ramp-up
The clock ramp-up starts with the given divider value PCS_DIVSn[DIVS] and with the given
divider decrement value PCD_DIVCn[INIT] and ends with the divider value 1.
The initial divider change start value PCS_DIVCn[INIT] for system clock ramp-up is given in
Equation 4: .
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Equation 4
PCS_DIVCn[INIT] = d × k × 1000 – 1
Where k is calculated from Equation 2: using the target system clock source frequency ftarg.
The divider start value for clock ramp-up is given in Equation 5: .
Equation 5
k(k + 1)
PCS_DIVSn[DIVS] =  1 + d -------------------- × 1000 – 1

2 
Figure 53. System Clock Ramp-Up Timing (k = 6 example)
f
ftarg
RCC_PCS_SDUR
≤ a × ftarg
16MHz
ftarg ÷ PCS_DIVSn[DIVS]
1
2
11.4
Low-power modes
11.4.1
Peripheral clock gating
3
busy
4
5
steps
6
The clocks of unused AHB and APB peripherals can be disabled by software via the
AHBxxENR and APBxxENR registers of the RCC.
By default after reset all peripherals clocks are disabled.
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11.4.2
RM0483
Core Sleep mode (CSleep)
CSleep mode stops the CPU clock. Each core can enter CSleep independently by
executing Wait For Interrupt/Event (WFI, WFE) instruction.
To further reduce power consumption in CSleep mode, each core can disable the clocks of
the peripherals it is handling (and therefore may not be active when the core is in CSleep).
Each core has a set of Corex APB/AHB Sleep Mode Enable registers (Cx_AHBxxSMENR,
Cx_APBxxSMENR) that allows the clock gating of the peripherals that are disabled together
with the core, when CSleep mode is entered.
Each set of RCC registers can be written only by the associated core (that is
C1_AxxxSMENR registers can only be written by Core1).
The status of the clock of a peripheral is determined by the corresponding bit settings in the
registers that control the clock in RCC, as summarized in Table 118: IP Clock status basing
on the corresponding bits in RCC Clock enable registers.
Table 118. IP Clock status basing on the corresponding bits in RCC Clock enable
registers
Core 1
Core 2
ON
ON
SLEEP
ON
ON
SLEEP
SLEEP
Note:
SLEEP
AxxxENR[IPn]
C1_AxxSMENR
[IPn]
C2_AxxxSMEN
[IPn]
IPn Clock
0
-
-
OFF
1
-
-
ON
1
0
-
OFF
1
1
-
ON
1
-
0
OFF
1
-
1
ON
1
0
-
OFF
1
-
0
OFF
1
1
1
ON
From application point of view, one peripheral has to be controlled only by one core.
For example, only one of the two bits C1_AHBxxSMENR[UART1] and
C2_AHBxxSMENR[UART1] has to be at 0, to put the peripheral in sleep mode.
In case both C1_AHBxxSMENR[UART1] and C2_AHBxxSMENR[UART1] are at 0
(meaning peripheral clock must be stopped), the peripheral stops as soon as one of the two
cores goes in sleep.
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11.5
Reset and clock control (RCC)
RCC registers
Table 119. RCC memory map
Offset
Register Name
Register Title
Reset
0x0
CR
Clock Sources Control Register
0x0000 0000
0x4
ICSR
Internal Clock Sources Calibration Register
0x0000 0000
0x8
CFGR
Clock Configuration Register
0x0000 0024
0xC
PLLCFGR
PLL Configuration Register
0x0000 0000
0x18
CIER
Clock Interrupt / Fault Enable
0x0000 0000
0x1C
CIFR
Clock Interrupt / Fault Flag
0x0000 0000
0x20
CICR
Clock Interrupt / Fault Clear
0x0000 0000
0x24
CCIPR1
Peripherals independent clock configuration
(selection) register 1
0x0000 0000
0x28
CCIPR2
Peripherals independent clock configuration
(prescaler) register 2
0x2431 8842
0x2C
LSCFGR
Low Speed Clock Configuration register
0x0000 0000
0x30
CRRCR
Clock recovery RC register
0x0000 0000
0x50
AHB1LRSTR
AHB1 peripherals resets [Low Word]
0x0000 0000
0x54
AHB1HRSTR
AHB1 peripherals resets [High Word]
0x0000 0000
0x58
AHB2LRSTR
AHB2 peripherals resets [Low Word]
0x0000 0000
0x5C
AHB2HRSTR
AHB2 peripherals resets [High Word]
0x0000 0000
0x60
APB1LRSTR
APB1 peripherals resets [Low Word]
0x0000 0000
0x68
APB2LRSTR
APB2 peripherals resets [Low Word]
0x0000 0000
0x6C
APB2HRSTR
APB2 peripherals resets [High Word]
0x0000 0000
0x70
AHB1LENR
AHB1 peripherals clock enables [Low Word]
0x0000 0000
0x74
AHB1HENR
AHB1 peripherals clock enables [High Word]
0x0000 0000
0x78
AHB2LENR
AHB2 peripherals clock enables [Low Word]
0x0000 0000
0x7C
AHB2HENR
AHB2 peripherals clock enables [High Word]
0x0000 0000
0x80
APB1LENR
APB1 peripherals clock enables [Low Word]
0x0000 0030
0x88
APB2LENR
APB2 peripherals clock enables [Low Word]
0x0000 0000
0x8C
APB2HENR
APB2 peripherals clock enables [High Word]
0x0000 0000
0x90
C1_AHB1LSMENR
Core 1 AHB1 peripherals sleep mode clock
enables [Low Word]
0x0003 3800
0x94
C1_AHB1HSMENR
Core 1 AHB1 peripherals sleep mode clock
enables [High Word]
0x3000 1061
0x98
C1_AHB2LSMENR
Core 1 AHB2 peripherals sleep mode clock
enables [Low Word]
0x0003 01FF
0x9C
C1_AHB2HSMENR
Core 1 AHB2 peripherals sleep mode clock
enables [High Word]
0x0000 1071
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Table 119. RCC memory map (continued)
Offset
Register Name
Register Title
Reset
0xA0
C1_APB1LSMENR
Core 1 APB1 peripherals sleep mode clock
enables [Low Word]
0x19EF 8433
0xA8
C1_APB2LSMENR
Core 1 APB2 peripherals sleep mode clock
enables [Low Word]
0x0987 9805
0xAC
C1_APB2HSMENR
Core 1 APB2 peripherals sleep mode clock
enables [High Word]
0x0001 5503
0xB0
C2_AHB1LSMENR
Core 2 AHB1 peripherals sleep mode clock
enables [Low Word]
0x0003 3800
0xB4
C2_AHB1HSMENR
Core 2 AHB1 peripherals sleep mode clock
enables [High Word]
0x3000 1061
0xB8
C2_AHB2LSMENR
Core 2 AHB2 peripherals sleep mode clock
enables [Low Word]
0x0003 01FF
0xBC
C2_AHB2HSMENR
Core 2 AHB2 peripherals sleep mode clock
enables [High Word]
0x0000 1071
0xC0
C2_APB1LSMENR
Core 2 APB1 peripherals sleep mode clock
enables [Low Word]
0x19EF 8433
0xC8
C2_APB2LSMENR
Core 2 APB2 peripherals sleep mode clock
enables [Low Word]
0x0987 9805
0xCC
C2_APB2HSMENR
Core 2 APB2 peripherals sleep mode clock
enables [High Word]
0x0001 5503
0xD0
DBGCR
Debug Clock Control Register
0x0005 033F
0xD4
CMUR
Clock Monitor Unit Control Register
0x0000 0300
0xD8
HSM_SW_CTRLR
HSM SW Control Register
0x0000 0000
0x100
DSWRR
Destructive Software Reset Register
0x0000 0000
0x104
DRETR
Destructive Reset Escalation Threshold Register
0x0000 000F
0x108
DESR
Destructive Event Status Register
0x0000 0000
0x10C
DORER
Destructive Output Reset Enable Register
0x0101 C73B
0x200
FSWRR
Functional Software Reset Register
0x0000 0000
0x204
FRETR
Functional Reset Escalation Threshold Register
0x0000 000F
0x208
FESR
Functional Event Status Register
0x0000 0000
0x20C
FORER
Functional Output Reset Enable Register
0x0000 0004
0x210
FERDR
Functional Event Reset Disable Register
0x0000 0000
0x214
FESSR
Functional Event Short Sequence Register
0x0000 0040
0x300
SYS_CFG_REG
Global System Configuration Register
0x0000 0001
0x304
C1_VTOR_INIT_REG
Core1 Vector Table Offset Init Register
0x1FF0 0100
0x308
C2_VTOR_INIT_REG
Core2 Vector Table Offset Init Register
0x0000 0000
0x30C
C1_VTOR_ADDR_REG
Core1 User VTOR Address Register
0x0000 0000
0x310
C1_BOOT_CTRL_REG
Core1 Boot Control Register
0x0000 0003
276/2075
RM0483 Rev 5
RM0483
Reset and clock control (RCC)
Table 119. RCC memory map (continued)
Offset
Register Name
Register Title
Reset
0x314
C2_BOOT_CTRL_REG
Core2 Boot Control Register
0x0000 0000
0x318
C_SLEEP_STS_REG
Cores Sleep Status register
0x0000 0000
0x380
PCS_CTRL_REG
PCS Control Register
0x0000 0002
0x384
PCS_SDUR_REG
PCS Switch Duration Register
0x0000 0000
0x388
PCS_DIVC_XOSC_REG
PCS Divider Change XOSC Register
0x03E7 0000
0x38C
PCS_DIVE_XOSC_REG
PCS Divider End XOSC Register
0x0000 03E7
0x390
PCS_DIVS_XOSC_REG
PCS Divider Start XOSC Register
0x0000 03E7
0x394
PCS_DIVC_PLL0_REG
PCS Divider Change PLL0 Register
0x03E7 0000
0x398
PCS_DIVE_PLL0_REG
PCS Divider End PLL0 Register
0x0000 03E7
0x39C
PCS_DIVS_PLL0_REG
PCS Divider Start PLL0 Register
0x0000 03E7
0x3A0
PCS_DIVC_PLL1_REG
PCS Divider Change PLL1 Register
0x03E7 0000
0x3A4
PCS_DIVE_PLL1_REG
PCS Divider End PLL1 Register
0x0000 03E7
0x3A8
PCS_DIVS_PLL1_REG
PCS Divider Start PLL1 Register
0x0000 03E7
11.6
RCC register descriptions
R
R
W
R
8
7
6
5
RESERVED
IRCOSCRDY
R
W
9
XOSCON
R
XOSCRDY
R
RESERVED
XOSCBYP
R
W
PLL0ON
R
RESER
VED
PLL0LOCK
R
PLL1ON
RESER
VED
PLL1LOCK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R
W
R
R
R
Address:
RCC_REGMAPBaseAddress + 0x0
Type:
RW
Reset:
0x0000 0000
4
3
2
1
0
LSION
Clock Sources Control Register
LSIRDY
CR
R
R
W
Description:Clock Sources Control Register
Register reset: long functional reset (PHASE1 reset)
[29] PLL1LOCK: PLL1 Lock Status
0: PLL1 is unlocked
1: PLL1 is locked
[28] PLL1ON: PLL1 Enable (active HIGH). Write 0 allowed only if System PLL is not used as
system clock
[25] PLL0LOCK: PLL0 Lock Status
0: PLL0 is unlocked
1: PLL0 is locked
RM0483 Rev 5
277/2075
327
Reset and clock control (RCC)
RM0483
[24] PLL0ON: PLL0 Enable (active HIGH). Write 0 allowed only if System PLL is not used as
system clock
[18] XOSCBYP: High Speed External Clock Bypass
0: External crystal mode
1: External source mode (bypass)
[17] XOSCRDY: High Speed External Clock ready status
0: XOSC oscillator is not stable
1: XOSC oscillator is stable
[16] XOSCON: High Speed External Clock Enable (active HIGH). Write 0 allowed only if SYSCLK is
not derived from XOSC
[10] IRCOSCRDY: High Speed Internal Clock ready status
0: IRCOSC oscillator is not stable
1: IRCOSC oscillator is stable
[1] LSIRDY: Low Speed Internal Clock ready status
0: LSI oscillator is not stable
1: LSI oscillator is stable
[0] LSION: Low Speed Internal Clock Enable (active HIGH)
ICSR
Internal Clock Sources Calibration Register
RW
8
7
6
5
4
3
2
RESERVED
IRCOSC_FT_CODE
R
9
IRCOSC_TRIM
RESER
VED
IRCOSC_TRIM_USER
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
Address:
RCC_REGMAPBaseAddress + 0x4
Type:
RW
Reset:
0x0000 0000
Description:Internal clock sources calibration register. Refer to Section 11.2.2: Internal RC
oscillator (IRCOSC).
Register reset: power on reset (POR)
[29:24] IRCOSC_TRIM_USER: IRCOSC software trimming bits
[23:16] IRCOSC_TRIM: IRCOSC trimming bits from DCF
[5:0] IRCOSC_FT_CODE: IRCOSC fine trimming code from parabolic interpolator
278/2075
RM0483 Rev 5
1
0
RM0483
Reset and clock control (RCC)
CFGR
Clock Configuration Register
7
6
5
4
3
2
1
RESERVED
SYSPRE
RESER
VED
SW
RW
8
SWS
R
9
MCOSEL
RESER
VED
MCOPRE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RW
R
RW
R
R
RW
Address:
RCC_REGMAPBaseAddress + 0x8
Type:
RW
Reset:
0x0000 0024
0
Description:Clock Configuration Register
Register reset: short functional reset (PHASE3 reset)
[29:24] MCOPRE: Monitor Clock Output Prescaler. Div Factor = MCOPRE x2
0x0: no division
0x1: Div Factor = 2
0x2: Div Factor = 4
...
0x3F: Div Factor = 126
Reset value: 0x0
[23:20] MCOSEL: Monitor Clock Output Selector
Note: MCOSEL must be updated only when MCOPRE = 0
0x8: LSI
0x9: IRCOSC
0xA: XOSC
0xB: PLL0
0xC: PLL1
Reset value: 0x0
[16:8] SYSPRE: System Clock Prescaler. Div Factor = SYSPRE+1
0x0: no division
0x1: Div Factor = 2
0x2: Div Factor = 3
...
0x1FF: Div Factor = 512
Reset value: 0x0
[5:3] SWS: System Clock Switch Status. Report the actual System Clock source. Refer to SW bit
field.
Reset value: 0x4
[2:0] SW: System Clock Switch
A write access to this bit field loads the PCS Control. Refer to PCS_CTRL_REG
0x4: internal 16 MHz (IRCOSC) oscillator selected as system clock
0x5: external 4-40 MHz (XOSC) oscillator selected as system clock
0x6: PLL0 selected as system clock
0x7: PLL1 selected as system clock
others: not allowed (a write operation on SW bit field has effect only if SW[2]=1)
Reset value: 0x4
RM0483 Rev 5
279/2075
327
Reset and clock control (RCC)
RM0483
PLL Configuration Register
RESERVED
R
Address:
RCC_REGMAPBaseAddress + 0xC
Type:
RW
Reset:
0x0000 0000
9
8
7
6
5
4
3
2
1
0
RESERVED
PLL0SRC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PLL1SRC
PLLCFGR
RW
R
RW
Description:PLL Configuration Register
Register reset: long functional reset (PHASE1 reset)
[9:8] PLL1SRC: PLL1 Source Clock Selector. Write allowed only if PLL1 is disabled
0x0: None
0x1: None
0x2: PLL0:PHI
0x3: XOSC
[1:0] PLL0SRC: PLL0 Source Clock Selector. Write allowed only if PLL0 is disabled
0x0: None
0x1: None
0x2: IRCOSC
0x3: XOSC
R
W
R
Address:
RCC_REGMAPBaseAddress + 0x18
Type:
RW
Reset:
0x0000 0000
Description:Clock Interrupt / Fault Enable (active HIGH)
Register reset: short functional reset (PHASE3 reset)
[16] SAFEMODE_FE: SafeMode FCCU Fault Enable
[6] PLL1LOCK_IE: PLL1 Lock Interrupt Enable
[5] PLL0LOCK_IE: PLL0 Lock Interrupt Enable
[4] XOSCRDY_IE: XOSC Ready Interrupt Enable
[0] LSIRDY_IE: LSI Ready Interrupt Enable
280/2075
RM0483 Rev 5
7
6
5
4
LSIRDY_IE
R
8
RESERVED
RESERVED
9
XOSCRDY_IE
RESERVED
SAFEMODE_FE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PLL0LOCK_IE
Clock Interrupt / Fault Enable
PLL1LOCK_IE
CIER
3
2
1
0
R
W
R
W
R
W
R
R
W
RESERVED
R
R
R
Address:
RCC_REGMAPBaseAddress + 0x1C
Type:
R
Reset:
0x0000 0000
9
8
7
6
5
4
LSIRDY_IF
RESERVED
SAFEMODE_FF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Clock Interrupt / Fault Flag
XOSCRDY_IF
CIFR
PLL0LOCK_IF
Reset and clock control (RCC)
PLL1LOCK_IF
RM0483
3
2
1
0
R
R
R
R
R
Description:Clock Interrupt / Fault Flag (active HIGH)
Register reset: short functional reset (PHASE3 reset)
[16] SAFEMODE_FF: SafeMode Fault Flag. This flag is set by hardware when System Clock
source is switched to IRCOSC
[6] PLL1LOCK_IF: PLL1 Lock Interrupt Flag. This flag is set by hardware when PLL1 is locked.
[5] PLL0LOCK_IF: PLL0 Lock Interrupt Flag. This flag is set by hardware when PLL0 is locked.
[4] XOSCRDY_IF: XOSC Ready Interrupt Flag. This flag is set by hardware when XOSC oscillator
is stable.
[0] LSIRDY_IF: LSI Ready Interrupt Flag. This flag is set by hardware when LSI oscillator is stable.
W
R
Address:
RCC_REGMAPBaseAddress + 0x20
Type:
W
Reset:
0x0000 0000
7
6
5
4
LSIRDY_IC
R
8
RESERVED
RESERVED
9
XOSCRDY_IC
RESERVED
SAFEMODE_FC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PLL0LOCK_IC
Clock Interrupt / Fault Clear
PLL1LOCK_IC
CICR
3
2
1
0
W
W
W
R
W
Description:Clock Interrupt / Fault Clear
Register reset: short functional reset (PHASE3 reset)
[16] SAFEMODE_FC: Safemode Fault Clear.
Writing 1 to this bit clears the relative CIFR bit
Reset by HW
[6] PLL1LOCK_IC: PLL1 Lock Interrupt Clear.
Writing 1 to this bit clears the relative CIFR bit
Reset by HW
RM0483 Rev 5
281/2075
327
Reset and clock control (RCC)
RM0483
[5] PLL0LOCK_IC: PLL0 Lock Interrupt Clear.
Writing 1 to this bit clears the relative CIFR bit
Reset by HW
[4] XOSCRDY_IC: XOSC Ready Interrupt Clear.
Writing 1 to this bit clears the relative CIFR bit
Reset by HW
[0] LSIRDY_IC: LSI Ready Interrupt Clear.
Writing 1 to this bit clears the relative CIFR bit
Reset by HW
CCIPR1
Peripherals independent clock configuration
(selection) register 1
Address:
RCC_REGMAPBaseAddress + 0x24
Type:
RW
Reset:
0x0000 0000
RW
R
[18:16] ADC_SEL: SAR ADC Clock Source selection
0x4: XOSC
0x5: PLL0
0x6: PLL1
others: None
[14:12] FDCAN_SEL: FDCAN Clock Source selection
0x4: XOSC
0x5: PLL0
others: None
[10:8] I2S23_SEL: I2S23 Clock Source selection
0x4: IRCOSC
0x5: XOSC
0x6: PLL0
0x7: I2S Pad
others: None
282/2075
RM0483 Rev 5
5
4
3
2
1
RE
SE
RV
ED
RW
R
RW
R
RW
Description:Register reset: short functional reset (PHASE3 reset)
[22:20] SD_ADC_SEL: Sigma Delta ADC Clock Source selection
0x4: XOSC
0x5: PLL0
0x6: PLL1
others: None
6
UART_SEL
R
7
RESERVED
RW
8
I2C_SEL
R
RE
SE
RV
ED
9
I2S23_SEL
RW
RE
SE
RV
ED
FDCAN_SEL
R
RE
SE
RV
ED
ADC_SEL
RESERVED
SD_ADC_SEL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0
RM0483
Reset and clock control (RCC)
[6:4] I2C_SEL: I2C Clock Source selection
0x4: IRCOSC
0x5: XOSC
0x6: PLL0
others: None
[2:0] UART_SEL: UART Clock Source selection
0x4: IRCOSC
0x5: XOSC
0x6: PLL0
0x7: LSI
others: None
CCIPR2
Peripherals independent clock configuration
(prescaler) register 2
4
3
2
UART_PRE
5
I2C_PRE
6
I2S23_PRE
7
FDCAN_PRE
8
ADC_PRE
9
SD_ADC_PRE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RW
RW
RW
RW
RW
RW
Address:
RCC_REGMAPBaseAddress + 0x28
Type:
RW
Reset:
0x2431 8842
1
0
Description:Register reset: short functional reset (PHASE3 reset)
[31:26] SD_ADC_PRE: Sigma Delta ADC Clock Prescaler. Div Factor = PRE x 2
0x0: no division
0x1: Div Factor = 2
0x2: Div Factor = 4
...
0x3F: Div Factor = 126
Reset value: 0x9
[25:20] ADC_PRE: SAR ADC Clock Prescaler. Div Factor = PRE x 2
0x0: no division
0x1: Div Factor = 2
0x2: Div Factor = 4
...
0x3F: Div Factor = 126
Reset value: 0x3
RM0483 Rev 5
283/2075
327
Reset and clock control (RCC)
RM0483
[19:15] FDCAN_PRE: FDCAN Clock Prescaler. Div Factor = PRE + 1
0x0: no division
0x1: Div Factor = 2
0x2: Div Factor = 3
...
0x1F: Div Factor = 32
Reset value: 0x3
[14:10] I2S23_PRE: I2S23 Clock Prescaler. Div Factor = PRE + 1
0x0: no division
0x1: Div Factor = 2
0x2: Div Factor = 3
...
0x1F: Div Factor = 32
Reset value: 0x2
[9:5] I2C_PRE: I2C Clock Prescaler. Div Factor = PRE + 1
0x0: no division
0x1: Div Factor = 2
0x2: Div Factor = 3
...
0x1F: Div Factor = 32
Reset value: 0x2
[4:0] UART_PRE: UART Clock Prescaler. Div Factor = PRE + 1
0x0: no division
0x1: Div Factor = 2
0x2: Div Factor = 3
...
0x1F: Div Factor = 32
Reset value: 0x2
Low Speed Clock Configuration register
6
5
RW
RESERVED
RESERVED
R
W
R
RW
R
R
Address:
RCC_REGMAPBaseAddress + 0x2C
Type:
RW
Reset:
0x0000 0000
Description:Register reset: short functional reset (PHASE3 reset)
[26:25] LSCOSEL: Low Speed Clock Output Monitor Source selection
0x0: None
0x1: None
0x2: LSI_DIVn : LSI after LSIPRE prescaler division
0x3: XOSC divided by 32
284/2075
7
RTCSTS
RW
8
RTCSEL
R
9
LSCOEN
RESERVED
LSCOSE
L
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LSIPRE
LSCFGR
RM0483 Rev 5
4
3
2
1
0
RM0483
Reset and clock control (RCC)
[24] LSCOEN: Low Speed Clock Output Monitor clock enable (active HIGH)
[10:9] RTCSEL: Real Time Clock Source selection
0x0: None
0x1: None
0x2: LSI_DIVn : LSI after LSIPRE prescaler division
0x3: XOSC divided by 32
[8] RTCSTS: Real Time Clock Status: if 1, RTC kernel clock is active and the relative reset is
released
[4:0] LSIPRE: Low Speed Internal Oscillator prescaler. Div Factor = PRE x 2
0x0: no division
0x1: Div Factor = 2
0x2: Div Factor = 4
...
0x1F: Div Factor = 62
Clock recovery RC register
R
R
W
R
Address:
RCC_REGMAPBaseAddress + 0x30
Type:
RW
Reset:
0x0000 0000
R
W
7
6
5
4
3
2
1
0
RESERVED
XOSC_LOC_SAFE_EN
RESERVED
8
PLL0_LOL_SAFE_EN
SYSCLK_FOR_SAFE_EN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
9
PLL1_LOL_SAFE_EN
CRRCR
R
W
R
R
W
Description:Register reset: short functional reset (PHASE3 reset)
[16] SYSCLK_FOR_SAFE_EN: SYSCLK Out of Range SafeMode Enable
1: switch SYSCLK to RCOSC if a SYSCLK is out of defined range
[9] PLL1_LOL_SAFE_EN: PLL1 Loss Of Lock SafeMode Enable
1: switch SYSCLK to RCOSC if SYSCLK is derived from PLL1 and a PLL1 LOL occurs
[8] PLL0_LOL_SAFE_EN: PLL0 Loss Of Lock SafeMode Enable
1: switch SYSCLK to RCOSC if SYSCLK is derived from PLL0 and a PLL0 LOL occurs
[0] XOSC_LOC_SAFE_EN: XOSC Loss Of Clock SafeMode Enable
1: switch SYSCLK to RCOSC if SYSCLK is derived from XOSC and a XOSC LOC occurs
RM0483 Rev 5
285/2075
327
Reset and clock control (RCC)
RM0483
AHB1LRSTR
AHB1 peripherals resets [Low Word]
6
5
4
RESER
VED
XOSCM
7
CRC
R
8
CORDIC
RESERVED
9
DMA2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R
W
R
R
W
R
W
R
W
R
Address:
RCC_REGMAPBaseAddress + 0x50
Type:
RW
Reset:
0x0000 0000
3
2
1
0
Description:AHB1 peripherals resets [Low Word].
0: does not reset
1: reset the relative peripheral
Register reset: short functional reset (PHASE3 reset)
[16] DMA2: DMA2 reset
[13] CORDIC: CORDIC reset
[12] CRC: CRC reset
[11] HSEM: HSEM reset
R
W
R
W
R
R
W
R
Address:
RCC_REGMAPBaseAddress + 0x54
Type:
RW
Reset:
0x0000 0000
Description:AHB1 peripherals resets [High Word].
0: does not reset
1: reset the relative peripheral
Register reset: short functional reset (PHASE3 reset)
[29] HRTIMER2: HRTIMER2 reset
[28] HRTIMER1: HRTIMER1 reset
[12] COMP2_DIG: Digital 2 reset
[6] DAC4: DAC4 reset
[5] DAC3: DAC3 reset
286/2075
RM0483 Rev 5
6
5
ADC3_ADC4_ADC5
RESERVED
7
RESERVED
RESERVED
COMP2_DIG
R
8
HRTIMER1
RESER
VED
9
HRTIMER2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DAC3
AHB1 peripherals resets [High Word]
DAC4
AHB1HRSTR
4
3
2
1
0
R
W
R
W
R
R
W
RM0483
Reset and clock control (RCC)
[0] ADC3_ADC4_ADC5: SAR ADC345 reset
Address:
RCC_REGMAPBaseAddress + 0x58
Type:
RW
Reset:
0x0000 0000
4
3
2
1
0
GPIOB
GPIOA
R
5
GPIOC
R
W
6
GPIOE
R
W
7
GPIOD
R
8
GPIOF
DMA1
RESERVED
9
GPIOG
RESERVED
DMAMUX1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
GPIOH
AHB2 peripherals resets [Low Word]
GPIOI
AHB2LRSTR
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Description:AHB2 peripherals resets [Low Word].
0: does not reset
1: reset the relative peripheral
Register reset: short functional reset (PHASE3 reset)
[17] DMAMUX1: DMAMUX1 reset
[16] DMA1: DMA1 reset
[8] GPIOI: GPIOI reset
[7] GPIOH: GPIOH reset
[6] GPIOG: GPIOG reset
[5] GPIOF: GPIOF reset
[4] GPIOE: GPIOE reset
[3] GPIOD: GPIOD reset
[2] GPIOC: GPIOC reset
[1] GPIOB: GPIOB reset
[0] GPIOA: GPIOA reset
RESERVED
R
R
W
R
Address:
RCC_REGMAPBaseAddress + 0x5C
Type:
RW
Reset:
0x0000 0000
RM0483 Rev 5
6
5
4
ADC1_ADC2
RESERVED
7
RESERVED
8
BDAC1
9
COMP1_DIG
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DAC1
AHB2 peripherals resets [High Word]
DAC2
AHB2HRSTR
3
2
1
0
R
W
R
W
R
W
R
R
W
287/2075
327
Reset and clock control (RCC)
RM0483
Description:AHB2 peripherals resets [High Word].
0: does not reset
1: reset the relative peripheral
Register reset: short functional reset (PHASE3 reset)
[12] COMP1_DIG: COMP1 reset
[6] DAC2: DAC2 reset
[5] DAC1: DAC1 reset
[4] BDAC1: BDAC1 reset
[0] ADC1_ADC2: ADC12 reset
R
W
R
W
RESERVED
R
W
R
R
W
R
Address:
RCC_REGMAPBaseAddress + 0x60
Type:
RW
Reset:
0x0000 0000
Description:APB1 peripherals resets [Low Word].
0: does not reset
1: reset the relative peripheral
Register reset: short functional reset (PHASE3 reset)
[28] UART3: UART3 reset
[27] UART2: UART2 reset
[24] SPI3: SPI3 reset
[23] SPI2: SPI2 reset
[22] I2C2: I2C2 reset
[21] I2C1: I2C1 reset
[19] TIM_TS: TIM_TS reset
[18] TIM7: TIM7 reset
[17] TIM6: TIM6 reset
[16] TIM3: TIM3 reset
[15] TIM2: TIM2 reset
[10] RTC: RTC reset
[5] IWDG2: IWDG2 reset
[4] IWDG1: IWDG1 reset
288/2075
RM0483 Rev 5
5
4
R
R
1
0
WWDG1
R
W
RESERVED
6
WWDG2
R
W
7
RESERVED
R
8
RTC
R
W
9
TIM2
R
W
TIM3
R
W
TIM6
R
W
TIM7
R
RE
SE
RV
ED
TIM_TS
I2C2
R
W
I2C1
SPI2
R
W
RESER
VED
SPI3
R
UART2
RESERVED
UART3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IWDG1
APB1 peripherals resets [Low Word]
IWDG2
APB1LRSTR
3
2
R
R
R
RM0483
Reset and clock control (RCC)
[1] WWDG2: WWDG2 reset
[0] WWDG1: WWDG1 reset
R
W
R
W
6
5
RESER
VED
RESERVED
R
W
R
R
W
R
W
R
Address:
RCC_REGMAPBaseAddress + 0x68
Type:
RW
Reset:
0x0000 0000
4
3
2
1
0
SYSCFG
R
W
7
TIM1_PWM
R
8
TIM8_PWM
R
W
9
TIM4
TIM5
R
W
TIM15
R
RESERVED
TIM16
R
W
SPI1
R
RESER
VED
SPI4
RESERVED
UART1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
APB2 peripherals resets [Low Word]
SMPU
APB2LRSTR
R
W
R
R
W
Description:APB2 peripherals resets [Low Word].
0: does not reset
1: reset the relative peripheral
Register reset: short functional reset (PHASE3 reset)
[27] UART1: UART1 reset
[24] SPI4: SPI4 reset
[23] SPI1: SPI1 reset
[18] TIM16: TIM16 reset
[17] TIM15: TIM15 reset
[16] TIM5: TIM5 reset
[15] TIM4: TIM4 reset
[12] TIM8_PWM: TIM8_PWM reset
[11] TIM1_PWM: TIM1_PWM reset
[2] SMPU: SMPU reset
[0] SYSCFG: SYSCFG reset
R
W
R
Address:
RCC_REGMAPBaseAddress + 0x6C
Type:
RW
RM0483 Rev 5
RE
SE
RV
ED
RE
SE
RV
ED
R
W
R
R
W
R
1
0
RESERVED
SD_ADC1
R
8
FDCAN2
R
W
RE
SE
RV
ED
9
FDCAN3
R
RE
SE
RV
ED
FDCAN4
RESERVED
FDCAN_MRAM
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SD_ADC2
APB2 peripherals resets [High Word]
FDCAN1
APB2HRSTR
7
6
5
4
3
2
R
W
R
R
W
R
W
289/2075
327
Reset and clock control (RCC)
Reset:
RM0483
0x0000 0000
Description:APB2 peripherals resets [High Word].
0: does not reset
1: reset the relative peripheral
Register reset: short functional reset (PHASE3 reset)
[16] FDCAN_MRAM: FDCAN_MRAM reset
[14] FDCAN4: FDCAN4 reset
Set by HW if APB2HRSTR[ FDCAN_MRAM ] = 1
Can be cleared only writing 0 also to APB2HRSTR[ FDCAN_MRAM ]
[12] FDCAN3: FDCAN3 reset
Set by HW if APB2HRSTR[ FDCAN_MRAM ] = 1
Can be cleared only writing 0 also to APB2HRSTR[ FDCAN_MRAM ]
[10] FDCAN2: FDCAN2 reset
Set by HW if APB2HRSTR[ FDCAN_MRAM ] = 1
Can be cleared only writing 0 also to APB2HRSTR[ FDCAN_MRAM ]
[8] FDCAN1: FDCAN1 reset
Set by HW if APB2HRSTR[ FDCAN_MRAM ] = 1
Can be cleared only writing 0 also to APB2HRSTR[ FDCAN_MRAM ]
[1] SD_ADC2: SD_ADC2 reset
[0] SD_ADC1: SD_ADC1 reset
AHB1LENR
AHB1 peripherals clock enables [Low Word]
5
4
HSEM
6
RESER
VED
RESERVED
R
W
R
R
W
R
W
R
W
R
Address:
RCC_REGMAPBaseAddress + 0x70
Type:
RW
Reset:
0x0000 0000
Description:AHB1 peripherals clock enables [Low Word].
0: clock disabled
1: clock enabled
[16] DMA2: DMA2 clock enable
[13] CORDIC: CORDIC clock enable
[12] CRC: CRC clock enable
[11] HSEM: HSEM clock enable
290/2075
7
CRC
R
8
CORDIC
RESERVED
9
DMA2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RM0483 Rev 5
3
2
1
0
RM0483
Reset and clock control (RCC)
R
W
R
W
R
R
W
R
Address:
RCC_REGMAPBaseAddress + 0x74
Type:
RW
Reset:
0x0000 0000
6
5
ADC3_ADC4_ADC5
RESERVED
7
RESERVED
RESERVED
COMP2_DIG
R
8
HRTIMER1
RESER
VED
9
HRTIMER2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DAC3
AHB1 peripherals clock enables [High Word]
DAC4
AHB1HENR
4
3
2
1
0
R
W
R
W
R
R
W
Description:AHB1 peripherals clock enables [High Word].
0: clock disabled
1: clock enabled
Register reset: short functional reset (PHASE3 reset)
[29] HRTIMER2: HRTIMER2 clock enable
[28] HRTIMER1: HRTIMER1 clock enable
[12] COMP2_DIG: Digital Comparetor 2 clock enable
[6] DAC4: DAC4 clock enable
[5] DAC3: DAC3 clock enable
[0] ADC3_ADC4_ADC5: SAR ADC345 clock enable
Address:
RCC_REGMAPBaseAddress + 0x78
Type:
RW
Reset:
0x0000 0000
4
3
2
1
0
GPIOB
GPIOA
R
5
GPIOC
R
W
6
GPIOE
R
W
7
GPIOD
R
8
GPIOF
DMA1
RESERVED
9
GPIOG
RESERVED
DMAMUX1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
GPIOH
AHB2 peripherals clock enables [Low Word]
GPIOI
AHB2LENR
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Description:AHB2 peripherals clock enables [Low Word].
0: clock disabled
1: clock enabled
Register reset: short functional reset (PHASE3 reset)
[17] DMAMUX1: DMAMUX1 clock enable
[16] DMA1: DMA1 clock enable
[8] GPIOI: GPIOI clock enable
RM0483 Rev 5
291/2075
327
Reset and clock control (RCC)
RM0483
[7] GPIOH: GPIOH clock enable
[6] GPIOG: GPIOG clock enable
[5] GPIOF: GPIOF clock enable
[4] GPIOE: GPIOE clock enable
[3] GPIOD: GPIOD clock enable
[2] GPIOC: GPIOC clock enable
[1] GPIOB: GPIOB clock enable
[0] GPIOA: GPIOA clock enable
RESERVED
R
R
W
R
Address:
RCC_REGMAPBaseAddress + 0x7C
Type:
RW
Reset:
0x0000 0000
5
4
ADC1_ADC2
7
RESERVED
6
RESERVED
8
BDAC1
9
COMP1_DIG
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DAC1
AHB2 peripherals clock enables [High Word]
DAC2
AHB2HENR
3
2
1
0
R
W
R
W
R
W
R
R
W
Description:AHB2 peripherals clock enables [High Word].
0: clock disabled
1: clock enabled
Register reset: short functional reset (PHASE3 reset)
[12] COMP1_DIG: COMP1 clock enable
[6] DAC2: DAC2 clock enable
[5] DAC1: DAC1 clock enable
[4] BDAC1: BDAC1 clock enable
[0] ADC1_ADC2: ADC12 clock enable
R
W
R
W
RESERVED
R
W
R
R
W
R
Address:
RCC_REGMAPBaseAddress + 0x80
Type:
RW
292/2075
RM0483 Rev 5
5
4
R
R
1
0
WWDG1
R
W
RESERVED
6
WWDG2
R
W
7
RESERVED
R
8
RTC
R
W
9
TIM2
R
W
TIM3
R
W
TIM6
R
W
TIM7
R
RE
SE
RV
ED
TIM_TS
I2C2
R
W
I2C1
SPI2
R
W
RESER
VED
SPI3
R
UART2
RESERVED
UART3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IWDG1
APB1 peripherals clock enables [Low Word]
IWDG2
APB1LENR
3
2
R
R R
W W
1S 1S
RM0483
Reset and clock control (RCC)
Reset:
0x0000 0030
Description:APB1 peripherals clock enables [Low Word].
0: clock disabled
1: clock enabled
Register reset: short functional reset (PHASE3 reset)
[28] UART3: UART3 clock enable
[27] UART2: UART2 clock enable
[24] SPI3: SPI3 clock enable
[23] SPI2: SPI2 clock enable
[22] I2C2: I2C2 clock enable
[21] I2C1: I2C1 clock enable
[19] TIM_TS: TIM_TS clock enable
[18] TIM7: TIM7 clock enable
[17] TIM6: TIM6 clock enable
[16] TIM3: TIM3 clock enable
[15] TIM2: TIM2 clock enable
[10] RTC: RTC clock enable
[5] IWDG2: IWDG2 clock enable
Reset value: 0x1
[4] IWDG1: IWDG1 clock enable
Reset value: 0x1
[1] WWDG2: WWDG2 clock enable
Note: This bit is set by SW and cleared by HW.
[0] WWDG1: WWDG1 clock enable
Note: This bit is set by SW and cleared by HW.
R
W
R
W
6
RESER
VED
RESERVED
R
W
R
R
W
R
W
R
Address:
RCC_REGMAPBaseAddress + 0x88
Type:
RW
Reset:
0x0000 0000
5
4
3
2
1
0
SYSCFG
R
W
7
TIM1_PWM
R
8
TIM8_PWM
R
W
9
TIM4
TIM5
R
W
TIM15
R
RESERVED
TIM16
R
W
SPI1
R
RESER
VED
SPI4
RESERVED
UART1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
APB2 peripherals clock enables [Low Word]
SMPU
APB2LENR
R
W
R
R
W
Description:APB2 peripherals clock enables [Low Word].
0: clock disabled
1: clock enabled
RM0483 Rev 5
293/2075
327
Reset and clock control (RCC)
RM0483
Register reset: short functional reset (PHASE3 reset)
[27] UART1: UART1 clock enable
[24] SPI4: SPI4 clock enable
[23] SPI1: SPI1 clock enable
[18] TIM16: TIM16 clock enable
[17] TIM15: TIM15 clock enable
[16] TIM5: TIM5 clock enable
[15] TIM4: TIM4 clock enable
[12] TIM8_PWM: TIM8_PWM clock enable
[11] TIM1_PWM: TIM1_PWM clock enable
[2] SMPU: SMPU clock enable
[0] SYSCFG: SYSCFG clock enable
R
W
R
Address:
RCC_REGMAPBaseAddress + 0x8C
Type:
RW
Reset:
0x0000 0000
RE
SE
RV
ED
RE
SE
RV
ED
R
W
R
R
W
R
Description:APB2 peripherals clock enables [High Word].
0: clock disabled
1: clock enabled
Register reset: short functional reset (PHASE3 reset)
[16] FDCAN_MRAM: FDCAN_MRAM clock enable
Set by HW if at least one the FDCANx_EN = 1
[14] FDCAN4: FDCAN4 clock enable
[12] FDCAN3: FDCAN3 clock enable
[10] FDCAN2: FDCAN2 clock enable
[8] FDCAN1: FDCAN1 clock enable
[1] SD_ADC2: SD_ADC2 clock enable
[0] SD_ADC1: SD_ADC1 clock enable
294/2075
RM0483 Rev 5
1
0
RESERVED
SD_ADC1
R
8
FDCAN2
R
RE
SE
RV
ED
9
FDCAN3
R
RE
SE
RV
ED
FDCAN4
RESERVED
FDCAN_MRAM
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SD_ADC2
APB2 peripherals clock enables [High Word]
FDCAN1
APB2HENR
7
6
5
4
3
2
R
W
R
R
W
R
W
RM0483
Reset and clock control (RCC)
C1_AHB1LSMENR
Core 1 AHB1 peripherals sleep mode clock enables
[Low Word]
6
5
4
RESER
VED
HSEM
7
CRC
R
8
CORDIC
RESERVED
9
DMA2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R
W
R
R
W
R
W
R
W
R
Address:
RCC_REGMAPBaseAddress + 0x90
Type:
RW
Reset:
0x0003 3800
3
2
1
0
Description:Core 1 AHB1 peripherals sleep mode clock enables [Low Word].
0: clock disabled, when Core 1 goes in Sleep mode
1: clock enabled if the relative bit of registers AxxxENR and C2_AxxxSMENR is 1,
when Core 1 goes in Sleep mode. Write access allowed only for Core 1
Register reset: short functional reset (PHASE3 reset)
[16] DMA2: DMA2 sleep mode clock enable
Reset value: 0x1
[13] CORDIC: CORDIC sleep mode clock enable
Reset value: 0x1
[12] CRC: CRC sleep mode clock enable
Reset value: 0x1
[11] HSEM: HSEM sleep mode clock enable
Reset value: 0x1
R
W
R
W
R
R
W
R
Address:
RCC_REGMAPBaseAddress + 0x94
Type:
RW
Reset:
0x3000 1061
6
5
ADC3_ADC4_ADC5
RESERVED
7
RESERVED
RESERVED
COMP2_DIG
R
8
HRTIMER1
RESER
VED
9
HRTIMER2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DAC3
Core 1 AHB1 peripherals sleep mode clock enables
[High Word]
DAC4
C1_AHB1HSMENR
4
3
2
1
0
R
W
R
W
R
R
W
Description:Core 1 AHB1 peripherals sleep mode clock enables [High Word].
0: clock disabled, when Core 1 goes in Sleep mode
1: clock enabled if the relative bit of registers AxxxENR and C2_AxxxSMENR is 1,
when Core 1 goes in Sleep mode. Write access allowed only for Core 1
RM0483 Rev 5
295/2075
327
Reset and clock control (RCC)
RM0483
Register reset: short functional reset (PHASE3 reset)
[29] HRTIMER2: HRTIMER2 sleep mode clock enable
Reset value: 0x1
[28] HRTIMER1: HRTIMER1 sleep mode clock enable
Reset value: 0x1
[12] COMP2_DIG: Digital Comparetor 2 sleep mode clock enable
Reset value: 0x1
[6] DAC4: DAC4 sleep mode clock enable
Reset value: 0x1
[5] DAC3: DAC3 sleep mode clock enable
Reset value: 0x1
[0] ADC3_ADC4_ADC5: SAR ADC345 sleep mode clock enable
Reset value: 0x1
Address:
RCC_REGMAPBaseAddress + 0x98
Type:
RW
Reset:
0x0003 01FF
4
3
2
1
0
GPIOB
GPIOA
R
5
GPIOC
R
W
6
GPIOE
R
W
7
GPIOD
R
8
GPIOF
DMA1
RESERVED
9
GPIOG
RESERVED
DMAMUX1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
GPIOH
Core 1 AHB2 peripherals sleep mode clock enables
[Low Word]
GPIOI
C1_AHB2LSMENR
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Description:Core 1 AHB2 peripherals sleep mode clock enables1 [Low Word].
0: clock disabled, when Core 1 goes in Sleep mode
1: clock enabled if the relative bit of registers AxxxENR and C2_AxxxSMENR is 1,
when Core 1 goes in Sleep mode. Write access allowed only for Core 1
Register reset: short functional reset (PHASE3 reset)
[17] DMAMUX1: DMAMUX1 sleep mode clock enable
Reset value: 0x1
[16] DMA1: DMA1 sleep mode clock enable
Reset value: 0x1
[8] GPIOI: GPIOI sleep mode clock enable
Reset value: 0x1
[7] GPIOH: GPIOH sleep mode clock enable
Reset value: 0x1
[6] GPIOG: GPIOG sleep mode clock enable
Reset value: 0x1
296/2075
RM0483 Rev 5
RM0483
Reset and clock control (RCC)
[5] GPIOF: GPIOF sleep mode clock enable
Reset value: 0x1
[4] GPIOE: GPIOE sleep mode clock enable
Reset value: 0x1
[3] GPIOD: GPIOD sleep mode clock enable
Reset value: 0x1
[2] GPIOC: GPIOC sleep mode clock enable
Reset value: 0x1
[1] GPIOB: GPIOB sleep mode clock enable
Reset value: 0x1
[0] GPIOA: GPIOA sleep mode clock enable
Reset value: 0x1
RESERVED
R
R
W
R
Address:
RCC_REGMAPBaseAddress + 0x9C
Type:
RW
Reset:
0x0000 1071
6
5
4
ADC1_ADC2
RESERVED
7
RESERVED
8
BDAC1
9
COMP1_DIG
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DAC1
Core 1 AHB2 peripherals sleep mode clock enables
[High Word]
DAC2
C1_AHB2HSMENR
3
2
1
0
R
W
R
W
R
W
R
R
W
Description:Core 1 AHB2 peripherals sleep mode clock enables [High Word].
0: clock disabled, when Core 1 goes in Sleep mode
1: clock enabled if the relative bit of registers AxxxENR and C2_AxxxSMENR is 1,
when Core 1 goes in Sleep mode. Write access allowed only for Core 1
Register reset: short functional reset (PHASE3 reset)
[12] COMP1_DIG: COMP1 sleep mode clock enable
Reset value: 0x1
[6] DAC2: DAC2 sleep mode clock enable
Reset value: 0x1
[5] DAC1: DAC1 sleep mode clock enable
Reset value: 0x1
[4] BDAC1: BDAC1 sleep mode clock enable
Reset value: 0x1
[0] ADC1_ADC2: ADC12 sleep mode clock enable
Reset value: 0x1
RM0483 Rev 5
297/2075
327
Reset and clock control (RCC)
RM0483
R
W
R
W
RESERVED
R
W
R
R
W
R
Address:
RCC_REGMAPBaseAddress + 0xA0
Type:
RW
Reset:
0x19EF 8433
5
4
R
W
R
W
1
0
WWDG1
R
W
RESERVED
6
WWDG2
R
W
7
RESERVED
R
8
RTC
R
W
9
TIM2
R
W
TIM3
R
W
TIM6
R
W
TIM7
R
RE
SE
RV
ED
TIM_TS
I2C2
R
W
I2C1
SPI2
R
W
RESER
VED
SPI3
R
UART2
RESERVED
UART3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IWDG1
Core 1 APB1 peripherals sleep mode clock enables
[Low Word]
IWDG2
C1_APB1LSMENR
3
2
R
R
R
Description:Core 1 APB1 peripherals sleep mode clock enables [Low Word].
0: clock disabled, when Core 1 goes in Sleep mode
1: clock enabled if the relative bit of registers AxxxENR and C2_AxxxSMENR is 1,
when Core 1 goes in Sleep mode. Write access allowed only for Core 1
Register reset: short functional reset (PHASE3 reset)
[28] UART3: UART3 sleep mode clock enable
Note: If AxxxSMNER bit is 0, the IP can directly enable its clock in Sleep Mode (through a clock
request) only if the relative AxxxENR bit is 1.
Reset value: 0x1
[27] UART2: UART2 sleep mode clock enable
Note: If AxxxSMNER bit is 0, the IP can directly enable its clock in Sleep Mode (through a clock
request) only if the relative AxxxENR bit is 1.
Reset value: 0x1
[24] SPI3: SPI3 sleep mode clock enable
Reset value: 0x1
[23] SPI2: SPI2 sleep mode clock enable
Reset value: 0x1
[22] I2C2: I2C2 sleep mode clock enable
Note: If AxxxSMNER bit is 0, the IP can directly enable its clock in Sleep Mode (through a clock
request) only if the relative AxxxENR bit is 1.
Reset value: 0x1
[21] I2C1: I2C1 sleep mode clock enable
Note: If AxxxSMNER bit is 0, the IP can directly enable its clock in Sleep Mode (through a clock
request) only if the relative AxxxENR bit is 1.
Reset value: 0x1
[19] TIM_TS: TIM_TS sleep mode clock enable
Reset value: 0x1
[18] TIM7: TIM7 sleep mode clock enable
Reset value: 0x1
[17] TIM6: TIM6 sleep mode clock enable
Reset value: 0x1
298/2075
RM0483 Rev 5
RM0483
Reset and clock control (RCC)
[16] TIM3: TIM3 sleep mode clock enable
Reset value: 0x1
[15] TIM2: TIM2 sleep mode clock enable
Reset value: 0x1
[10] RTC: RTC sleep mode clock enable
Reset value: 0x1
[5] IWDG2: IWDG2 sleep mode clock enable
Reset value: 0x1
[4] IWDG1: IWDG1 sleep mode clock enable
Reset value: 0x1
[1] WWDG2: WWDG2 sleep mode clock enable
Reset value: 0x1
[0] WWDG1: WWDG1 sleep mode clock enable
Reset value: 0x1
R
W
R
W
6
RESER
VED
RESERVED
R
W
R
R
W
R
W
R
Address:
RCC_REGMAPBaseAddress + 0xA8
Type:
RW
Reset:
0x0987 9805
5
4
3
2
1
0
SYSCFG
R
W
7
TIM1_PWM
R
8
TIM8_PWM
R
W
9
TIM4
TIM5
R
W
TIM15
R
RESERVED
TIM16
R
W
SPI1
R
RESER
VED
SPI4
RESERVED
UART1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Core 1 APB2 peripherals sleep mode clock enables
[Low Word]
SMPU
C1_APB2LSMENR
R
W
R
R
W
Description:Core 1 APB2 peripherals sleep mode clock enables [Low Word].
0: clock disabled, when Core 1 goes in Sleep mode
1: clock enabled if the relative bit of registers AxxxENR and C2_AxxxSMENR is 1,
when Core 1 goes in Sleep mode. Write access allowed only for Core 1
Register reset: short functional reset (PHASE3 reset)
[27] UART1: UART1 sleep mode clock enable
Note: If AxxxSMNER bit is 0, the IP can directly enable its clock in Sleep Mode (through a clock
request) only if the relative AxxxENR bit is 1.
Reset value: 0x1
[24] SPI4: SPI4 sleep mode clock enable
Reset value: 0x1
[23] SPI1: SPI1 sleep mode clock enable
Reset value: 0x1
[18] TIM16: TIM16 sleep mode clock enable
Reset value: 0x1
RM0483 Rev 5
299/2075
327
Reset and clock control (RCC)
RM0483
[17] TIM15: TIM15 sleep mode clock enable
Reset value: 0x1
[16] TIM5: TIM5 sleep mode clock enable
Reset value: 0x1
[15] TIM4: TIM4 sleep mode clock enable
Reset value: 0x1
[12] TIM8_PWM: TIM8_PWM sleep mode clock enable
Reset value: 0x1
[11] TIM1_PWM: TIM1_PWM sleep mode clock enable
Reset value: 0x1
[2] SMPU: SMPU sleep mode clock enable
Reset value: 0x1
[0] SYSCFG: SYSCFG sleep mode clock enable
Reset value: 0x1
R
W
R
Address:
RCC_REGMAPBaseAddress + 0xAC
Type:
RW
Reset:
0x0001 5503
RE
SE
RV
ED
RE
SE
RV
ED
R
W
R
R
W
R
1
0
RESERVED
SD_ADC1
R
8
FDCAN2
R
RE
SE
RV
ED
9
FDCAN3
R
RE
SE
RV
ED
FDCAN4
RESERVED
FDCAN_MRAM
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SD_ADC2
Core 1 APB2 peripherals sleep mode clock enables
[High Word]
FDCAN1
C1_APB2HSMENR
7
6
5
4
3
2
R
W
R
R
W
R
W
Description:Core 1 APB2 peripherals sleep mode clock enables [High Word].
0: clock disabled, when Core 1 goes in Sleep mode
1: clock enabled if the relative bit of registers AxxxENR and C2_AxxxSMENR is 1,
when Core 1 goes in Sleep mode. Write access allowed only for Core 1
Register reset: short functional reset (PHASE3 reset)
[16] FDCAN_MRAM: FDCAN_MRAM sleep mode clock enable
Set by HW if at least one the FDCANx_SMEN = 1
Reset value: 0x1
[14] FDCAN4: FDCAN4 sleep mode clock enable
Reset value: 0x1
[12] FDCAN3: FDCAN3 sleep mode clock enable
Reset value: 0x1
[10] FDCAN2: FDCAN2 sleep mode clock enable
Reset value: 0x1
300/2075
RM0483 Rev 5
RM0483
Reset and clock control (RCC)
[8] FDCAN1: FDCAN1 sleep mode clock enable
Reset value: 0x1
[1] SD_ADC2: SD_ADC2 sleep mode clock enable
Reset value: 0x1
[0] SD_ADC1: SD_ADC1 sleep mode clock enable
Reset value: 0x1
C2_AHB1LSMENR
Core 2 AHB1 peripherals sleep mode clock enables
[Low Word]
6
5
4
RESER
VED
HSEM
7
CRC
R
8
CORDIC
RESERVED
9
DMA2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R
W
R
R
W
R
W
R
W
R
Address:
RCC_REGMAPBaseAddress + 0xB0
Type:
RW
Reset:
0x0003 3800
3
2
1
0
Description:Core 2 AHB1 peripherals sleep mode clock enables [Low Word].
0: clock disabled, when Core 2 goes in Sleep mode
1: clock enabled if the relative bit of registers AxxxENR and C1_AxxxSMENR is 1,
when Core 2 goes in Sleep mode. Write access allowed only for Core 2
Register reset: short functional reset (PHASE3 reset)
[16] DMA2: DMA2 sleep mode clock enable
Reset value: 0x1
[13] CORDIC: CORDIC sleep mode clock enable
Reset value: 0x1
[12] CRC: CRC sleep mode clock enable
Reset value: 0x1
[11] HSEM: HSEM sleep mode clock enable
Reset value: 0x1
R
W
R
W
R
R
W
R
Address:
RCC_REGMAPBaseAddress + 0xB4
RM0483 Rev 5
6
5
ADC3_ADC4_ADC5
RESERVED
7
RESERVED
RESERVED
COMP2_DIG
R
8
HRTIMER1
RESER
VED
9
HRTIMER2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DAC3
Core 2 AHB1 peripherals sleep mode clock enables
[High Word]
DAC4
C2_AHB1HSMENR
4
3
2
1
0
R
W
R
W
R
R
W
301/2075
327
Reset and clock control (RCC)
Type:
RW
Reset:
0x3000 1061
RM0483
Description:Core 2 AHB1 peripherals sleep mode clock enables [High Word].
0: clock disabled
1: clock enabled if the relative bit of registers AxxxENR and C1_AxxxSMENR is 1
Write access allowed only for Core 2
Register reset: short functional reset (PHASE3 reset)
[29] HRTIMER2: HRTIMER2 sleep mode clock enable
Reset value: 0x1
[28] HRTIMER1: HRTIMER1 sleep mode clock enable
Reset value: 0x1
[12] COMP2_DIG: Digital Comparetor 2 sleep mode clock enable
Reset value: 0x1
[6] DAC4: DAC4 sleep mode clock enable
Reset value: 0x1
[5] DAC3: DAC3 sleep mode clock enable
Reset value: 0x1
[0] ADC3_ADC4_ADC5: SAR ADC345 sleep mode clock enable
Reset value: 0x1
Address:
RCC_REGMAPBaseAddress + 0xB8
Type:
RW
Reset:
0x0003 01FF
4
3
2
1
0
GPIOB
GPIOA
R
5
GPIOC
R
W
6
GPIOE
R
W
7
GPIOD
R
8
GPIOF
DMA1
RESERVED
9
GPIOG
RESERVED
DMAMUX1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
GPIOH
Core 2 AHB2 peripherals sleep mode clock enables
[Low Word]
GPIOI
C2_AHB2LSMENR
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Description:Core 2 AHB2 peripherals sleep mode clock enables [Low Word].
0: clock disabled
1: clock enabled if the relative bit of registers AxxxENR and C1_AxxxSMENR is 1
Write access allowed only for Core 2
Register reset: short functional reset (PHASE3 reset)
[17] DMAMUX1: DMAMUX1 sleep mode clock enable
Reset value: 0x1
[16] DMA1: DMA1 sleep mode clock enable
Reset value: 0x1
302/2075
RM0483 Rev 5
RM0483
Reset and clock control (RCC)
[8] GPIOI: GPIOI sleep mode clock enable
Reset value: 0x1
[7] GPIOH: GPIOH sleep mode clock enable
Reset value: 0x1
[6] GPIOG: GPIOG sleep mode clock enable
Reset value: 0x1
[5] GPIOF: GPIOF sleep mode clock enable
Reset value: 0x1
[4] GPIOE: GPIOE sleep mode clock enable
Reset value: 0x1
[3] GPIOD: GPIOD sleep mode clock enable
Reset value: 0x1
[2] GPIOC: GPIOC sleep mode clock enable
Reset value: 0x1
[1] GPIOB: GPIOB sleep mode clock enable
Reset value: 0x1
[0] GPIOA: GPIOA sleep mode clock enable
Reset value: 0x1
RESERVED
R
R
W
R
Address:
RCC_REGMAPBaseAddress + 0xBC
Type:
RW
Reset:
0x0000 1071
6
5
4
ADC1_ADC2
RESERVED
7
RESERVED
8
BDAC1
9
COMP1_DIG
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DAC1
Core 2 AHB2 peripherals sleep mode clock enables
[High Word]
DAC2
C2_AHB2HSMENR
3
2
1
0
R
W
R
W
R
W
R
R
W
Description:Core 2 AHB2 peripherals sleep mode clock enables [High Word].
0: clock disabled, when Core 2 goes in Sleep mode
1: clock enabled if the relative bit of registers AxxxENR and C1_AxxxSMENR is 1,
when Core 2 goes in Sleep mode. Write access allowed only for Core 2
Register reset: short functional reset (PHASE3 reset)
[12] COMP1_DIG: COMP1 sleep mode clock enable
Reset value: 0x1
[6] DAC2: DAC2 sleep mode clock enable
Reset value: 0x1
[5] DAC1: DAC1 sleep mode clock enable
Reset value: 0x1
RM0483 Rev 5
303/2075
327
Reset and clock control (RCC)
RM0483
[4] BDAC1: BDAC1 sleep mode clock enable
Reset value: 0x1
[0] ADC1_ADC2: ADC12 sleep mode clock enable
Reset value: 0x1
R
W
R
W
RESERVED
R
W
R
R
W
R
Address:
RCC_REGMAPBaseAddress + 0xC0
Type:
RW
Reset:
0x19EF 8433
5
4
R
W
R
W
1
0
WWDG1
R
W
RESERVED
6
WWDG2
R
W
7
RESERVED
R
8
RTC
R
W
9
TIM2
R
W
TIM3
R
W
TIM6
R
W
TIM7
R
RE
SE
RV
ED
TIM_TS
I2C2
R
W
I2C1
SPI2
R
W
RESER
VED
SPI3
R
UART2
RESERVED
UART3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IWDG1
Core 2 APB1 peripherals sleep mode clock enables
[Low Word]
IWDG2
C2_APB1LSMENR
3
2
R
R
R
Description:Core 2 APB1 peripherals sleep mode clock enables [Low Word].
0: clock disabled, when Core 2 goes in Sleep mode
1: clock enabled if the relative bit of registers AxxxENR and C1_AxxxSMENR is 1,
when Core 2 goes in Sleep mode. Write access allowed only for Core 2
Register reset: short functional reset (PHASE3 reset)
[28] UART3: UART3 sleep mode clock enable
Note: If AxxxSMNER bit is 0, the IP can directly enable its clock in Sleep Mode (through a clock
request) only if the relative AxxxENR bit is 1.
Reset value: 0x1
[27] UART2: UART2 sleep mode clock enable
Note: If AxxxSMNER bit is 0, the IP can directly enable its clock in Sleep Mode (through a clock
request) only if the relative AxxxENR bit is 1.
Reset value: 0x1
[24] SPI3: SPI3 sleep mode clock enable
Reset value: 0x1
[23] SPI2: SPI2 sleep mode clock enable
Reset value: 0x1
[22] I2C2: I2C2 sleep mode clock enable
Note: If AxxxSMNER bit is 0, the IP can directly enable its clock in Sleep Mode (through a clock
request) only if the relative AxxxENR bit is 1.
Reset value: 0x1
[21] I2C1: I2C1 sleep mode clock enable
Note: If AxxxSMNER bit is 0, the IP can directly enable its clock in Sleep Mode (through a clock
request) only if the relative AxxxENR bit is 1.
Reset value: 0x1
[19] TIM_TS: TIM_TS sleep mode clock enable
Reset value: 0x1
304/2075
RM0483 Rev 5
RM0483
Reset and clock control (RCC)
[18] TIM7: TIM7 sleep mode clock enable
Reset value: 0x1
[17] TIM6: TIM6 sleep mode clock enable
Reset value: 0x1
[16] TIM3: TIM3 sleep mode clock enable
Reset value: 0x1
[15] TIM2: TIM2 sleep mode clock enable
Reset value: 0x1
[10] RTC: RTC sleep mode clock enable
Reset value: 0x1
[5] IWDG2: IWDG2 sleep mode clock enable
Reset value: 0x1
[4] IWDG1: IWDG1 sleep mode clock enable
Reset value: 0x1
[1] WWDG2: WWDG2 sleep mode clock enable
Reset value: 0x1
[0] WWDG1: WWDG1 sleep mode clock enable
Reset value: 0x1
R
W
R
W
6
RESER
VED
RESERVED
R
W
R
R
W
R
W
R
Address:
RCC_REGMAPBaseAddress + 0xC8
Type:
RW
Reset:
0x0987 9805
5
4
3
2
1
0
SYSCFG
R
W
7
TIM1_PWM
R
8
TIM8_PWM
R
W
9
TIM4
TIM5
R
W
TIM15
R
RESERVED
TIM16
R
W
SPI1
R
RESER
VED
SPI4
RESERVED
UART1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Core 2 APB2 peripherals sleep mode clock enables
[Low Word]
SMPU
C2_APB2LSMENR
R
W
R
R
W
Description:Core 2 APB2 peripherals sleep mode clock enables [Low Word].
0: clock disabled
1: clock enabled if the relative bit of registers AxxxENR and C1_AxxxSMENR is 1
Write access allowed only for Core 2
Register reset: short functional reset (PHASE3 reset)
[27] UART1: UART1 sleep mode clock enable
Note: If AxxxSMNER bit is 0, the IP can directly enable its clock in Sleep Mode (through a clock
request) only if the relative AxxxENR bit is 1.
Reset value: 0x1
[24] SPI4: SPI4 sleep mode clock enable
Reset value: 0x1
RM0483 Rev 5
305/2075
327
Reset and clock control (RCC)
RM0483
[23] SPI1: SPI1 sleep mode clock enable
Reset value: 0x1
[18] TIM16: TIM16 sleep mode clock enable
Reset value: 0x1
[17] TIM15: TIM15 sleep mode clock enable
Reset value: 0x1
[16] TIM5: TIM5 sleep mode clock enable
Reset value: 0x1
[15] TIM4: TIM4 sleep mode clock enable
Reset value: 0x1
[12] TIM8_PWM: TIM8_PWM sleep mode clock enable
Reset value: 0x1
[11] TIM1_PWM: TIM1_PWM sleep mode clock enable
Reset value: 0x1
[2] SMPU: SMPU sleep mode clock enable
Reset value: 0x1
[0] SYSCFG: SYSCFG sleep mode clock enable
Reset value: 0x1
R
W
R
Address:
RCC_REGMAPBaseAddress + 0xCC
Type:
RW
Reset:
0x0001 5503
RE
SE
RV
ED
RE
SE
RV
ED
R
W
R
R
W
R
1
0
RESERVED
SD_ADC1
R
8
FDCAN2
R
RE
SE
RV
ED
9
FDCAN3
R
RE
SE
RV
ED
FDCAN4
RESERVED
FDCAN_MRAM
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SD_ADC2
Core 2 APB2 peripherals sleep mode clock enables
[High Word]
FDCAN1
C2_APB2HSMENR
7
6
5
4
3
2
R
W
R
R
W
R
W
Description:Core 2 APB2 peripherals sleep mode clock enables [High Word].
0: clock disabled, when Core 2 goes in Sleep mode
1: clock enabled if the relative bit of registers AxxxENR and C1_AxxxSMENR is 1,
when Core 2 goes in Sleep mode. Write access allowed only for Core 2
Register reset: short functional reset (PHASE3 reset)
[16] FDCAN_MRAM: FDCAN_MRAM sleep mode clock enable
Set by HW if at least one the FDCANx_SMEN = 1
Reset value: 0x1
[14] FDCAN4: FDCAN4 sleep mode clock enable
Reset value: 0x1
306/2075
RM0483 Rev 5
RM0483
Reset and clock control (RCC)
[12] FDCAN3: FDCAN3 sleep mode clock enable
Reset value: 0x1
[10] FDCAN2: FDCAN2 sleep mode clock enable
Reset value: 0x1
[8] FDCAN1: FDCAN1 sleep mode clock enable
Reset value: 0x1
[1] SD_ADC2: SD_ADC2 sleep mode clock enable
Reset value: 0x1
[0] SD_ADC1: SD_ADC1 sleep mode clock enable
Reset value: 0x1
Address:
RCC_REGMAPBaseAddress + 0xD0
Type:
RW
Reset:
0x0005 033F
4
3
2
1
0
RESER
VED
DGB_CLK_0
R
5
DGB_CLK_1
RW
6
DGB_CLK_2
R
7
DGB_CLK_3
R
W
8
DGB_CLK_4
RESERVED
9
DGB_CLK_5
R
RESERVED
ATB_TPIU_PRE
RESERVED
DBG_RST
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ATB_CLK
Debug Clock Control Register
ATB_TPIU_CLK
DBGCR
R
W
R
W
R
R
W
R
W
R
W
R
W
R
W
R
W
Description:Register reset: power-on reset
[24] DBG_RST: Debug reset: If 1, nDBGPOR is asserted
Note: nDBGPOR can be asserted also by DAP_RESET_REQ.
nDBGPOR is released only if DBG_RST=0 and DAP_RESET_REQ=0
Reset value: 0x0
[18:16] ATB_TPIU_PRE: ATB TPIU prescaler. Div Factor = PRE + 1
0x0: no division
0x1: Div Factor = 2
...
0x7: Div Factor = 8
Reset value: 0x5
[9] ATB_TPIU_CLK: ATB TPIU clock enable
0: Clock disabled
1: Clock enabled
Reset value: 0x1
[8] ATB_CLK: ATB clock enable
0: Clock disabled
1: Clock enabled
Reset value: 0x1
RM0483 Rev 5
307/2075
327
Reset and clock control (RCC)
RM0483
[5] DGB_CLK_5: Debug 5 clock enable
0: Clock disabled
1: Clock enabled
Reset value: 0x1
[4] DGB_CLK_4: Debug 4 clock enable
0: Clock disabled
1: Clock enabled
Reset value: 0x1
[3] DGB_CLK_3: Debug 3 clock enable
0: Clock disabled
1: Clock enabled
Reset value: 0x1
[2] DGB_CLK_2: Debug 2 clock enable
0: Clock disabled
1: Clock enabled
Reset value: 0x1
[1] DGB_CLK_1: Debug 1 clock enable
0: Clock disabled
1: Clock enabled
Reset value: 0x1
[0] DGB_CLK_0: Debug 0 clock enable
0: Clock disabled
1: Clock enabled
Reset value: 0x1
3
2
1
0
CMU3RST
CMU2RST
CMU1RST
CMU0RST
R
W
R
W
R
W
R
W
R
W
R
W
CMU0EN
4
CMU1EN
5
CMU2EN
6
CMU3EN
7
CMU4EN
8
RESERVED
RESER
VED
R
R
W
R
W
R
W
R
W
R
W
R
W
R
Address:
RCC_REGMAPBaseAddress + 0xD4
Type:
RW
Reset:
0x0000 0300
Description:Register reset: short functional reset (PHASE3 reset)
[13] CMU5EN: CMU5 clock enable
0: Clock disabled
1: Clock enabled
Reset value: 0x0
[12] CMU4EN: CMU4 clock enable
0: Clock disabled
1: Clock enabled
Reset value: 0x0
308/2075
9
CMU5EN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CMU4RST
Clock Monitor Unit Control Register
CMU5RST
CMUR
RM0483 Rev 5
RM0483
Reset and clock control (RCC)
[11] CMU3EN: CMU3 clock enable
0: Clock disabled
1: Clock enabled
Reset value: 0x0
[10] CMU2EN: CMU2 clock enable
0: Clock disabled
1: Clock enabled
Reset value: 0x0
[9] CMU1EN: CMU1 clock enable
0: Clock disabled
1: Clock enabled
Reset value: 0x1
[8] CMU0EN: CMU0 clock enable
0: Clock disabled
1: Clock enabled
Reset value: 0x1
[5] CMU5RST: CMU5 reset
0: Does not reset
1: Reset the relative peripheral
Reset value: 0x0
[4] CMU4RST: CMU4 reset
0: Does not reset
1: Reset the relative peripheral
Reset value: 0x0
[3] CMU3RST: CMU3 reset
0: Does not reset
1: Reset the relative peripheral
Reset value: 0x0
[2] CMU2RST: CMU2 reset
0: Does not reset
1: Reset the relative peripheral
Reset value: 0x0
[1] CMU1RST: CMU1 reset
0: Does not reset
1: Reset the relative peripheral
Reset value: 0x0
[0] CMU0RST: CMU0 reset
0: Does not reset
1: Reset the relative peripheral
Reset value: 0x0
RM0483 Rev 5
309/2075
327
Reset and clock control (RCC)
RM0483
HSM_SW_CTRLR
HSM SW Control Register
9
8
7
6
5
4
3
2
1
0
RESERVED
HSM_SW_EN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
W
1S
Address:
RCC_REGMAPBaseAddress + 0xD8
Type:
RW
Reset:
0x0000 0000
Description:This register allows to activate HSM via SW. The setting of HSM_SW_EN bit
releases reset and clock to HSM (that is to HSM secure core).
Register reset: short functional reset (PHASE3 reset)
[0] HSM_SW_EN: Reset release bit
0: HSM and secure core not activated by SW
1: HSM and secure core SW enable.
Note: This bit has effect only if HSM is not already enabled by DCF.
The writing of this bit is allowed under conditions reported in Security ADD.
Note: This bit is set by SW and cleared by HW.
Reset value: 0x0
DSWRR
Destructive Software Reset Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DSWR
W
Address:
RCC_REGMAPBaseAddress + 0x100
Type:
W
Reset:
0x0000 0000
Description:Writing 0x2EA055F8 to this register triggers a destructive reset
Register reset: destructive reset (PHASE0 reset)
[31:0] DSWR: Reset value: 0x0
DRETR
Destructive Reset Escalation Threshold Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
7
6
5
4
3
2
1
DRET
R
RW
Address:
RCC_REGMAPBaseAddress + 0x104
Type:
RW
310/2075
9
RESERVED
RM0483 Rev 5
0
RM0483
Reset and clock control (RCC)
Reset:
0x0000 000F
Description:This register sets the threshold for destructive reset escalation to keep the chip in the
reset state until the next power-on reset triggers a new reset sequence.
Writing any value to this register resets the destructive reset counter
Register reset: power-on reset
[3:0] DRET: Destructive reset escalation threshold - If the value of this field is 0, the destructive reset
escalation function is disabled. Any other value is the number of destructive resets which keep
the chip in the reset state until the next power-on reset triggers a new reset sequence if the
DRET register is not written to beforehand.
Reset value: 0xf
Address:
RCC_REGMAPBaseAddress + 0x108
Type:
RW
Reset:
0x0000 0000
1
0
D_POR
R
5
D_RESET_IN
RESER
VED
W W W
1C 1C 1C
6
RESERVED
7
4
3
2
D_FCCU
R
8
D_RCC_SW
W W W
1C 1C 1C
9
W W W
1C 1C 1C
D_STCU_CF
R
RESERVED
D_JTAG
W
1C
D_SSCM
R
D_HSM
RESERVED
D_TSENS
RESERVED
D_VD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
D_EDR
Destructive Event Status Register
D_SWT_Boot
DESR
R
W W
1C 1C
Description:This register contains the status of the destructive reset sources. Register bits are
cleared on write 1
0: No destructive reset event has occurred since either the last clear or the last
power-on reset assertion
1: A destructive reset event has occurred
Register reset: power-on reset
[24] D_VD: Voltage out of range from LVDs and/or HVDs
Reset value: 0x0
[16] D_TSENS: Temperature sensor
Reset value: 0x0
[15] D_HSM: HSM destructive reset request
Reset value: 0x0
[14] D_SSCM: SSCM error during data reading
Reset value: 0x0
[10] D_JTAG: JTAG destructive reset request
Reset value: 0x0
[9] D_SWT_Boot: Boot watchdog timeout during NVM
initialization
Reset value: 0x0
[8] D_EDR: Escalation destructive reset
Reset value: 0x0
RM0483 Rev 5
311/2075
327
Reset and clock control (RCC)
RM0483
[5] D_STCU_CF: STCU critical failure indicated by STCU_CF
trigger
Reset value: 0x0
[4] D_FCCU: FOSU reset
Reset value: 0x0
[3] D_RCC_SW: Software destructive reset from RCC
Reset value: 0x0
[1] D_RESET_IN: RESET_IN pin
Reset value: 0x0
[0] D_POR: Power-On reset
Reset value: 0x0
5
4
3
2
1
0
D_FCCU
RESERVED
D_RESET_IN
D_POR
R
6
R
R
R
R
R
R
RESERVED
D_EDR
R
7
D_SWT_Boot
R
8
D_JTAG
R
9
D_SSCM
D_HSM
R
RESERVED
D_TSENS
RESERVED
D_VD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
D_RCC_SW
Destructive Output Reset Enable Register
D_STCU_CF
DORER
RESER
VED
R
R
R
W
R
R
R
Address:
RCC_REGMAPBaseAddress + 0x10C
Type:
RW
Reset:
0x0101 C73B
Description:This register enables the report of a destructive reset on the RESET_OUT pad.
Register reset: power-on reset
[24] D_VD: Voltage out of range from LVDs and/or HVDs
Reset value: 0x1
[16] D_TSENS: Temperature sensor
Reset value: 0x1
[15] D_HSM: HSM destructive reset request
Reset value: 0x1
[14] D_SSCM: SSCM error during data reading
Reset value: 0x1
[10] D_JTAG: JTAG destructive reset request
Reset value: 0x1
[9] D_SWT_Boot: Boot watchdog timeout during NVM initialization
Reset value: 0x1
[8] D_EDR: Escalation destructive reset (generated by functional reset escalation)
Reset value: 0x1
[5] D_STCU_CF: STCU critical failure indicated by STCU_CF trigger
Reset value: 0x1
312/2075
RM0483 Rev 5
RM0483
Reset and clock control (RCC)
[4] D_FCCU: FOSU reset
Reset value: 0x1
[3] D_RCC_SW: Software destructive reset from RCC
Reset value: 0x1
[1] D_RESET_IN: RESET_IN pin
Reset value: 0x1
[0] D_POR: Power-On reset
Reset value: 0x1
FSWRR
Functional Software Reset Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
FSWR
W
Address:
RCC_REGMAPBaseAddress + 0x200
Type:
W
Reset:
0x0000 0000
Description:Writing 0xF41B84D1 to this register triggers a functional reset
Register reset: short functional reset (PHASE3 reset)
[31:0] FSWR: Reset value: 0x0
FRETR
Functional Reset Escalation Threshold Register
9
8
7
6
5
4
3
2
1
RESERVED
FRET
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
RW
Address:
RCC_REGMAPBaseAddress + 0x204
Type:
RW
Reset:
0x0000 000F
0
Description:This register sets the threshold for functional reset escalation to a destructive reset.
Writing any value to this register resets the functional reset counter.
Register reset: destructive reset (PHASE0 reset)
[3:0] FRET: Functional reset escalation threshold - If the value of this field is 0, the functional reset
escalation function is disabled. Any other value is the number of functional resets which cause
a destructive reset (if func_rst_escalation is connected to one of the dest_rst inputs) if the
FRET register is not written to beforehand.
Reset value: 0xf
RM0483 Rev 5
313/2075
327
Reset and clock control (RCC)
RM0483
R
W
1C
R
RCC_REGMAPBaseAddress + 0x208
Type:
R
Reset:
0x0000 0000
2
RESERVED
RESERVED
3
F_ST_DONE
RESERVED
W W
1C 1C
Address:
7
RESERVED
R
8
F_RCC_SW
W
1C
9
F_JTAG
R
F_HSM
RESERVED
F_TSENS
RESERVED
F_VD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
6
5
4
F_FCCU_LONG
Functional Event Status Register
F_FCCU_SHORT
FESR
W W
1C 1C
1
0
R
W W
1C 1C
R
Description:This register contains the status of the functional reset sources. Register bits are
cleared on write 1
0: No functional reset event has occurred since either the last clear or the last poweron reset assertion
1: A functional reset event has occurred
Register reset: power-on reset
[24] F_VD: Voltage detector for peripheral domain
Reset value: 0x0
[16] F_TSENS: Temperature sensor
Reset value: 0x0
[15] F_HSM: HSM functional reset request
Reset value: 0x0
[10] F_JTAG: JTAG functional reset request
Reset value: 0x0
[6] F_FCCU_SHORT: Short functional reset
Reset value: 0x0
[5] F_FCCU_LONG: Long functional reset
Reset value: 0x0
[3] F_RCC_SW: Software functional reset from RCC
Reset value: 0x0
[2] F_ST_DONE: Self-test functional reset
Reset value: 0x0
314/2075
RM0483 Rev 5
6
5
4
3
2
RESERVED
R
W
7
F_ST_DONE
R
8
R
R
W
R
R
W
R
R
RESERVED
F_JTAG
R
W
9
F_HSM
R
RESERVED
F_TSENS
RESERVED
F_VD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Functional Output Reset Enable Register
F_RCC_SW
FORER
F_FCCU_LONG
Reset and clock control (RCC)
F_FCCU_SHORT
RM0483
RESERVED
R
W
R
R
W
R
Address:
RCC_REGMAPBaseAddress + 0x20C
Type:
RW
Reset:
0x0000 0004
1
0
Description:This register enables the report of a functional reset on the RESET_OUT pad.
Register reset: destructive reset (PHASE0 reset)
[24] F_VD: Voltage detector for peripheral domain
Reset value: 0x0
[16] F_TSENS: Temperature sensor
Reset value: 0x0
[15] F_HSM: HSM functional reset request
Reset value: 0x0
[10] F_JTAG: JTAG functional reset request
Reset value: 0x0
[6] F_FCCU_SHORT: Short functional reset
Reset value: 0x0
[5] F_FCCU_LONG: Long functional reset
Reset value: 0x0
[3] F_RCC_SW: Software functional reset from RCC
Reset value: 0x0
[2] F_ST_DONE: Self-test functional reset
Reset value: 0x1
Address:
4
R
R
R
R
W
On
ce
R
RESERVED
5
R
F_ST_DONE
6
RESERVED
2
RESERVED
R
W
On
ce
7
RESERVED
3
F_RCC_SW
R
8
F_JTAG
R
W
On
ce
9
F_HSM
R
RESERVED
F_TSENS
RESERVED
F_VD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
F_FCCU_LONG
Functional Event Reset Disable Register
F_FCCU_SHORT
FERDR
1
0
R
R
W
On
ce
R
R
RCC_REGMAPBaseAddress + 0x210
RM0483 Rev 5
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327
Reset and clock control (RCC)
Type:
RWOnce
Reset:
0x0000 0000
RM0483
Description:This register provides dedicated bits to disable functional reset sources.
0: functional reset event triggers a reset sequence
1: functional reset event is masked
Register reset: destructive reset (PHASE0 reset)
[24] F_VD: Voltage detector for peripheral domain
Reset value: 0x0
[16] F_TSENS: Temperature sensor
Reset value: 0x0
[15] F_HSM: HSM functional reset - always enabled
Reset value: 0x0
[10] F_JTAG: JTAG functional reset request
Reset value: 0x0
[6] F_FCCU_SHORT: Short functional reset - always enabled
Reset value: 0x0
[5] F_FCCU_LONG: Long functional reset - always enabled
Reset value: 0x0
[3] F_RCC_SW: Software functional reset from RCC
Reset value: 0x0
[2] F_ST_DONE: Self-test functional reset - always enabled
Reset value: 0x0
RCC_REGMAPBaseAddress + 0x214
Type:
RWOnce
Reset:
0x0000 0040
4
R
R
R
W
On
ce
R
RESERVED
5
R
2
F_ST_DONE
6
RESERVED
R R
W W
On On
ce ce
Address:
7
RESERVED
3
RESERVED
R
8
F_RCC_SW
R
W
On
ce
9
F_JTAG
R
F_HSM
RESERVED
F_TSENS
RESERVED
F_VD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
F_FCCU_LONG
Functional Event Short Sequence Register
F_FCCU_SHORT
FESSR
1
0
R
R
W
On
ce
R
R
Description:This register defines if the functional reset event triggers a LONG or SHORT reset
sequence.
0: LONG reset sequence starting from PHASE1
1: SHORT reset sequence starting from PHASE3
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RM0483
Reset and clock control (RCC)
Register reset: destructive reset (PHASE0 reset)
[24] F_VD: Voltage detector for peripheral domain
Reset value: 0x0
[16] F_TSENS: Temperature sensor
Reset value: 0x0
[15] F_HSM: HSM functional reset request
Reset value: 0x0
[10] F_JTAG: JTAG functional reset request
Reset value: 0x0
[6] F_FCCU_SHORT: Short functional reset - it always triggers a short reset sequence
Reset value: 0x1
[5] F_FCCU_LONG: Long functional reset - it always triggers a long reset sequence
Reset value: 0x0
[3] F_RCC_SW: Software functional reset from RCC
Reset value: 0x0
[2] F_ST_DONE: Self-test functional reset - it always triggers a long reset sequence
Reset value: 0x0
R
R
8
7
6
5
4
RESERVED
LS_CORE1_2
R
RESERVED
9
LS_DMA
RESERVED
OTA_EN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R
R
R
R
Address:
RCC_REGMAPBaseAddress + 0x300
Type:
R
Reset:
0x0000 0001
3
2
1
0
BOOT_CORE1
Global System Configuration Register
BOOT_CORE2
SYS_CFG_REG
R
R
Description:This read-only register mirrors the Boot Core configuration done by the
corresponding Write Once DCF.
It reports the cores that have to be started by HW in parallel to the Boot CPU (Core1),
that is always enabled.
Register reset: destructive reset (PHASE0 reset)
[24] OTA_EN: Enables OTA on flash
0: OTA disabled (default)
1: OTA enabled
Reset value: 0x0
[16] LS_DMA: Enables lockstep replicas for DMA1, DMA2 and DMAMUX
0: Lockstep for DMA1, DMA2 and DMAMUX disabled (default)
1: Lockstep for DMA1, DMA2 and DMAMUX enabled
Reset value: 0x0
RM0483 Rev 5
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Reset and clock control (RCC)
RM0483
[8] LS_CORE1_2: Enables lockstep configuration for Core1 and 2
Core2 has to be started together with Core1 (respecting lockstep delay constraints)
0: Lockstep for Core1 and Core2 disabled (default)
1: Lockstep for Core1 and Core2 enabled
Note: Only C1_VTOR dcf has to be considered as starting address
Reset value: 0x0
[1] BOOT_CORE2: Core2 enabled
0: Core2 is not enabled
1: Core2 is enabled
Reset value: 0x0
[0] BOOT_CORE1: Core1 enabled
1: Core1 enabled to start as Boot CPU
Reset value: 0x1
C1_VTOR_INIT_REG
Core1 Vector Table Offset Init Register
9
8
7
6
5
4
3
C1_VTOR_INIT
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RW
R
Address:
RCC_REGMAPBaseAddress + 0x304
Type:
RW
Reset:
0x1FF0 0100
2
1
0
Description:This register reports the VTOR address for Boot CPU, at reset release.
After reset it reports the address from which the Boot CPU has started fetching. It
depends on device state and BAF configuration.
Reset Value: BAF start address
Value after short functional reset assertion:
- When the flash is virgin, VTOR of the Boot CPU has to be the starting address of
SRAM1.
- When flash is not virgin:
-- if BAF (Boot Assist Flash) is enabled (default), the VTOR has to be set to starting
address of the BAF (Boot Assist Flash);
-- if BAF is bypassed by DCF setting, the VTOR has to be taken from Alternate Core1
User Address DCF.(Write Once DCF).
Register reset: destructive reset (PHASE0 reset)
[31:7] C1_VTOR_INIT: After reset it reports the address from which the Boot CPU has started
fetching. It depends on device state and BAF configuration.
Default Value: BAF start address
Reset Value: See Section 6.3.12.1: Boot CPU reset vector.
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RM0483
Reset and clock control (RCC)
C2_VTOR_INIT_REG
Core2 Vector Table Offset Init Register
8
7
6
5
4
3
2
1
C2_VTOR_INIT
UPDATE_COUNTS
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RW
R
R
Address:
RCC_REGMAPBaseAddress + 0x308
Type:
RW
Reset:
0x0000 0000
0
Description:This register defines the VTOR_INIT address of Core2.
Reset Value: 0x0000_0000
Value after short functional reset assertion: Default Value or Value of Corex Vector
Table Offset DCF, if programmed
Register reset: destructive reset (PHASE0 reset)
[31:7] C2_VTOR_INIT: Address of vector table of the M7 CORE2 after reset release
[2:0] UPDATE_COUNTS: Reports the number of times the DCF has been overwritten.
Max allowed is 4
C1_VTOR_ADDR_REG
Core1 User Vector Table - Offset Init Register
8
7
6
5
4
3
2
1
C1_VTOR_ADDR
UPDATE_COUNTS
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
R
R
Address:
RCC_REGMAPBaseAddress + 0x30C
Type:
R
Reset:
0x0000 0000
0
Description:This read-only register reports the address to be used by BAF to jump to the
application code.
Reset Value: 0x0000_0000
Register reset: destructive reset (PHASE0 reset)
[31:7] C1_VTOR_ADDR: Address of user code vector table.
[2:0] UPDATE_COUNTS: Reports the number of times the DCF has been overwritten.
Max allowed is 4
RM0483 Rev 5
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Reset and clock control (RCC)
RM0483
1
0
RESERVED
C1_CPU_WAIT_RELEASE
C1_RES_RELEASE
Core1 Boot Control Register
C1_LOCK
C1_BOOT_CTRL_REG
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
W
R
R
W
R
W
Address:
RCC_REGMAPBaseAddress + 0x310
Type:
RW
Reset:
0x0000 0003
9
8
7
6
5
4
3
2
Description:This register allows to control the behavior of Cores at reset release and allows the
Boot CPU to wake up the other cores via SW in case no HW wake-up has been
programmed.
Register reset: destructive reset (PHASE0 reset)
[31] C1_LOCK: Lock bit
0: Register Content is writable
1: Lock the register content till next reset
NOTE: Lock bit also locks the content of C1_VTOR_REG
Reset value: 0x0
[1] C1_CPU_WAIT_RELEASE: CPU_WAIT_RELEASE bit
0: CPU is in 'CPU WAIT' state
1: CPU WAIT is released
Reset value: 0x1
[0] C1_RES_RELEASE: Reset release bit
0: Corex is under reset
1: Corex reset is released
Reset value: 0x1
1
0
RESERVED
C2_CPU_WAIT_RELEASE
C2_RES_RELEASE
Core2 Boot Control Register
C2_LOCK
C2_BOOT_CTRL_REG
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
W
R
R
W
R
W
Address:
320/2075
RCC_REGMAPBaseAddress + 0x314
RM0483 Rev 5
9
8
7
6
5
4
3
2
RM0483
Reset and clock control (RCC)
Type:
RW
Reset:
0x0000 0000
Description:This register allows to control the behavior of Cores at reset release and allows the
Boot CPU to wake up the other cores via SW in case no HW wake-up has been
programmed.
Register reset: destructive reset (PHASE0 reset)
[31] C2_LOCK: Lock bit
0: Register Content is writable
1: Lock the register content till next reset
NOTE: Lock bit also locks the content of C2_VTOR_REG
Reset value: 0x0
[1] C2_CPU_WAIT_RELEASE: CPU_WAIT_RELEASE bit
0: CPU is in 'CPU WAIT' state
1: CPU WAIT is released
Reset value: 0x0
[0] C2_RES_RELEASE: Reset release bit
0: Corex is under reset
1: Corex reset is released
Reset value: 0x0
Cores Sleep Status register
RESERVED
R
Address:
RCC_REGMAPBaseAddress + 0x318
Type:
R
Reset:
0x0000 0000
9
8
7
6
5
4
3
2
1
0
RESERVED
C1_SLEEP_MODE_STS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
C2_SLEEP_MODE_STS
C_SLEEP_STS_REG
R
R
R
Description:This register reports the Sleep Mode status of the Cores
[8] C2_SLEEP_MODE_STS: Core 2 Sleep Mode Status
1: Core is in Sleep Mode
Reset value: 0x0
[0] C1_SLEEP_MODE_STS: Core 1 Sleep Mode Status
1: Core is in Sleep Mode
Reset value: 0x0
RM0483 Rev 5
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327
Reset and clock control (RCC)
RM0483
PCS Control Register
RESERVED
R
Address:
RCC_REGMAPBaseAddress + 0x380
Type:
RW
Reset:
0x0000 0002
9
8
7
6
5
4
3
2
1
RESERVED
PCS_CTL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PCS_BUSY
PCS_CTRL_REG
R
R
RW
0
Description:This register allows to control the behavior of the progressive clock switching module.
Register reset: power-on reset
[8] PCS_BUSY: PCS busy status
[2:0] PCS_CTL: PCS control:
-000: Idle
-001: ramp-up (allowed only after ramp-down)
-010: clock switch
-011: clock switch followed by ramp-up
-100: ramp-down
-101: ramp-down followed by ramp-up
-110: ramp-down followed by clock switch
-111: ramp-down followed by clock switch followed by ramp-up
PCS controls load request is generated upon a write access to CFGR[SW] register.
If PCS_CTL[1]=1 (clock switch enabled) the PCS controls are loaded only if the selected
source is different from the current source, that is CFGR[SW] written is different from
CFGR[SWS].
Reset value: 0x2
PCS_SDUR_REG
PCS Switch Duration Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SDUR
RESERVED
RW
R
Address:
RCC_REGMAPBaseAddress + 0x384
Type:
RW
Reset:
0x0000 0000
9
8
7
6
5
4
3
2
1
0
Description:This register contains the progressive system clock switching duration for each step.
Register reset: power-on reset
[31:24] SDUR: Switch duration
This value defines the duration of one PCS clock switch step in terms of IRCOSC clock cycles
Reset value: 0x0
322/2075
RM0483 Rev 5
RM0483
Reset and clock control (RCC)
PCS_DIVC_XOSC_REG
PCS Divider Change XOSC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
INIT
RESERVED
RATE
RW
R
RW
Address:
RCC_REGMAPBaseAddress + 0x388
Type:
RW
Reset:
0x03E7 0000
2
1
0
Description:These registers define the rate of frequency change and initial change value on
frequency ramp-up for the progressive system clock switching when system clock
source is XOSC.
Register reset: power-on reset
[31:16] INIT: Divider change initial value
This is initial change value of the clock divider for the clock ramp-up phase
Byte write accesses are not allowed. Such an access does not result in an exception (that is
ips_xfr_err is not asserted), however the value is not loaded with the new value.
Reset value: 0x3e7
[7:0] RATE: Divider change rate
This value controls the change value of the clock divider for the clock ramp-up and ramp-down
phase.
Reset value: 0x0
PCS_DIVE_XOSC_REG
PCS Divider End XOSC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
RESERVED
DIVE
R
RW
Address:
RCC_REGMAPBaseAddress + 0x38C
Type:
RW
Reset:
0x0000 03E7
8
7
6
5
4
3
2
1
0
Description:These registers define the final division value on frequency ramp-down for the
progressive system clock switching when system clock source is XOSC.
Register reset: power-on reset
[19:0] DIVE: Divider end value
This is the clock divider end value for the clock ramp-down phase.
Byte and half-word write accesses are not allowed for this register. Such an access does not
result in an exception (that is ips_xfr_err is not asserted), however the value is not loaded with
the new value.
Reset value: 0x3e7
RM0483 Rev 5
323/2075
327
Reset and clock control (RCC)
RM0483
PCS_DIVS_XOSC_REG
PCS Divider Start XOSC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
RESERVED
DIVS
R
RW
Address:
RCC_REGMAPBaseAddress + 0x390
Type:
RW
Reset:
0x0000 03E7
8
7
6
5
4
3
2
1
0
Description:These registers define the initial division value on frequency ramp-up for the
progressive system clock switching when system clock source is XOSC.
Register reset: power-on reset
[19:0] DIVS: Divider start value
This is the start value of the clock divider for the clock ramp-up phase.
Byte and half-word write accesses are not allowed for this register. Such an access does not
result in an exception (that is ips_xfr_err is not asserted), however the value is not loaded with
the new value.
Reset value: 0x3e7
PCS_DIVC_PLL0_REG
PCS Divider Change PLL0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
INIT
RESERVED
RATE
RW
R
RW
Address:
RCC_REGMAPBaseAddress + 0x394
Type:
RW
Reset:
0x03E7 0000
2
1
0
Description:These registers define the rate of frequency change and initial change value on
frequency ramp-up for the progressive system clock switching when system clock
source is PLL0.
Register reset: power-on reset
[31:16] INIT: Divider change initial value
This is initial change value of the clock divider for the clock ramp-up phase
Byte write accesses are not allowed. Such an access does not result in an exception (that is
ips_xfr_err is not asserted), however the value is not loaded with the new value.
Reset value: 0x3e7
[7:0] RATE: Divider change rate
This value controls the change value of the clock divider for the clock ramp-up and ramp-down
phase.
Reset value: 0x0
324/2075
RM0483 Rev 5
RM0483
Reset and clock control (RCC)
PCS_DIVE_PLL0_REG
PCS Divider End PLL0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
RESERVED
DIVE
R
RW
Address:
RCC_REGMAPBaseAddress + 0x398
Type:
RW
Reset:
0x0000 03E7
8
7
6
5
4
3
2
1
0
Description:These registers define the final division value on frequency ramp-down for the
progressive system clock switching when system clock source is PLL0.
Register reset: power-on reset
[19:0] DIVE: Divider End Value
This is the clock divider end value for the clock ramp-down phase.
Byte and half-word write accesses are not allowed for this register. Such an access does not
result in an exception (that is ips_xfr_err is not asserted), however the value is not loaded with
the new value.
Reset value: 0x3e7
PCS_DIVS_PLL0_REG
PCS Divider Start PLL0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
RESERVED
DIVS
R
RW
Address:
RCC_REGMAPBaseAddress + 0x39C
Type:
RW
Reset:
0x0000 03E7
8
7
6
5
4
3
2
1
0
Description:These registers define the initial division value on frequency ramp-up for the
progressive system clock switching when system clock source is PLL0.
Register reset: power-on reset
[19:0] DIVS: Divider Start Value
This is the start value of the clock divider for the clock ramp-up phase.
Byte and half-word write accesses are not allowed for this register. Such an access does not
result in an exception (that is ips_xfr_err is not asserted), however the value is not loaded with
the new value.
Reset value: 0x3e7
PCS_DIVC_PLL1_REG
PCS Divider Change PLL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
INIT
RESERVED
RATE
RW
R
RW
Address:
RCC_REGMAPBaseAddress + 0x3A0
Type:
RW
RM0483 Rev 5
2
1
0
325/2075
327
Reset and clock control (RCC)
Reset:
RM0483
0x03E7 0000
Description:These registers define the rate of frequency change and initial change value on
frequency ramp-up for the progressive system clock switching when system clock
source is PLL1.
Register reset: power-on reset
[31:16] INIT: Divider Change Initial Value
This is initial change value of the clock divider for the clock ramp-up phase
Byte write accesses are not allowed. Such an access does not result in an exception (that is
ips_xfr_err is not asserted), however the value is not loaded with the new value.
Reset value: 0x3e7
[7:0] RATE: Divider Change Rate
This value controls the change value of the clock divider for the clock ramp-up and ramp-down
phase.
Reset value: 0x0
PCS_DIVE_PLL1_REG
PCS Divider End PLL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
RESERVED
DIVE
R
RW
Address:
RCC_REGMAPBaseAddress + 0x3A4
Type:
RW
Reset:
0x0000 03E7
8
7
6
5
4
3
2
1
0
Description:These registers define the final division value on frequency ramp-down for the
progressive system clock switching when system clock source is PLL1.
Register reset: power-on reset
[19:0] DIVE: Divider End Value
This is the clock divider end value for the clock ramp-down phase.
Byte and half-word write accesses are not allowed for this register. Such an access does not
result in an exception (that is ips_xfr_err is not asserted), however the value is not loaded with
the new value.
Reset value: 0x3e7
PCS_DIVS_PLL1_REG
PCS Divider Start PLL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
RESERVED
DIVS
R
RW
Address:
RCC_REGMAPBaseAddress + 0x3A8
Type:
RW
Reset:
0x0000 03E7
8
7
6
5
4
3
Description:These registers define the initial division value on frequency ramp-up for the
progressive system clock switching when system clock source is PLL1.
326/2075
RM0483 Rev 5
2
1
0
RM0483
Reset and clock control (RCC)
Register reset: power-on reset
[19:0] DIVS: Divider Start Value
This is the start value of the clock divider for the clock ramp-up phase.
Byte and half-word write accesses are not allowed for this register. Such an access does not
result in an exception (that is ips_xfr_err is not asserted), however the value is not loaded with
the new value.
Reset value: 0x3e7
RM0483 Rev 5
327/2075
327
Dual PLL digital interface (PLLDIG)
RM0483
12
Dual PLL digital interface (PLLDIG)
12.1
Introduction
The MCU provides a user interface and control over the dual PLL system composed of
PLL0 and PLL1 blocks (PLLDIG). The two analog PLL blocks are cascaded, with the PHI1
output of PLL0 feeding the clock input of PLL1 as shown in Chapter 6: Reset and Boot. The
key feature of the dual PLL architecture is the ability to drive peripherals from the PLL0 PHI
output, which is non-modulated and independent of the core clock frequency. The core and
platform clocks are driven by PLL1 PHI frequency modulated output.
Note:
For chip-specific implementation details, refer to Chapter 6: Reset and Boot.
12.2
Block diagram
Figure 54 shows the block diagram of the PLL digital interface.
Figure 54. Dual PLL digital interface block diagram
* PLL0
EXTAL
XTAL
XTAL
OSC
PLL1
RCSEL
MXCTRL
Pre-Divider
PREDIV
Phase
Detector
Charge
Pump
Low Pass
Filter
VCO
Divider
MFD
DIV 2
Charge
Pump
Low Pass
Filter
Phase
Detector
Out Divider1
RFD
Out Divider2
RFD
Out Divider
RFD
Divider
MFD
PREDIV RFD1 RFD2 MFD Lock
PHI1
PHI RFD MFD
2
3
Control/Status Registers
PLL
Failure
*
pll1_clkout
Enable
Backup
Clock
Selection
**
PHI
Clock Quality Monitor
1
PLLDIG
PCS
*
Lock
Reference
Failure
RC
OSC
VCO
PCS
*
pll0_clkout
Enable
* Features in red are not included in all configurations (refer to the Clocking chapter).
** “Backup Clock Selection” block in blue is not implemented.
328/2075
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RM0483
12.3
Dual PLL digital interface (PLLDIG)
Features
The Dual PLLDIG has the following features:
•
Supports dual PLL in cascaded mode with PLL0 clock out as reference clock to PLL1.
•
Reference clock pre-divider for finer frequency synthesis resolution.
•
Reduced frequency divider for reducing the PLL0/PLL1 output clock frequency without
causing the PLLs to lose lock.
•
•
•
Programmable frequency modulation on PLL1.
The frequency range after the prescaler is required to be 8-20 Mhz.
Lock detect circuitry reports when the PLLs have achieved frequency lock, and
continuously monitors lock status to report loss of lock conditions.
–
User-selectable ability to generate a fault request upon loss of lock.
–
The loss of lock indication is sent to the FCCU.
Note:
Please refer to the device datasheet for information on the input and output clock frequency
range.
12.4
Modes of operation
The operating mode of the PLLs is determined by the value of PLLnCR[CLKCFG]. The
mode of operation for the PLL is defined below:
Normal mode with reference, and either PLL0 or both PLLs enabled.
Normal mode is defined as the mode where the clocks are driven by the PLL. When using a
crystal for the clock reference, reset must remain asserted until the oscillator has stabilized.
When PLL0 is powered down and working in bypass mode, PLL1 must be bypassed and
powered down. PLL1 must be configured to work in normal mode only after PLL0 has
achieved lock (for example, bypass with PLL0 running or PLL0 in normal mode,
PLLnSR[LOCK] = 1).
12.4.1
Normal mode with reference, PLL0 or both PLLs enabled
In the normal mode, PLL0 receives an input clock from the reference and the pre-divider.
PLL0 multiplies the frequency to create the PLL0 output clock. The user must supply a
crystal that is within the appropriate frequency range, the crystal manufacturer
recommended external support circuitry and short signal route from the MCU to the crystal.
PLL0 generates a non-modulated clock which drives PLL0_PHI1. PLL1 can generate a
frequency modulated clock or a non-modulated clock (for example, locked on a single
frequency). The modulation rate, modulation depth, output divider (Reduced Frequency
Divider) and whether the PLL1 is modulated or not can be programmed by writing to the
PLL1FM register, Section 12.5.2.7: PLL1 frequency modulation register (PLL1FM).
Note:
While powering down the PLLs, user must ensure that PLL1 is powered down first followed
by powering down PLL0 for proper shut off.
Note:
Only when the PLL0 achieves lock must PLL1 be configured to work in either mode by
programming the appropriate RCC_CR and RCC_PLLCFCR registers (see Section 12.7:
Initialization information).
RM0483 Rev 5
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Dual PLL digital interface (PLLDIG)
12.5
RM0483
Memory map and register definition
This section provides the memory map and detailed descriptions of all registers for
configuring the PLLs.
12.5.1
Memory map
Table 120 shows the memory map. Addresses are given as offsets from the module base
address. All registers can be accessed using 8-bit, 16-bit or 32-bit addressing.
Table 120. Dual PLL digital interface memory map
Offset
(hex)
Register
0x0000
PLL0 Control Register (PLL0CR)
Section 12.5.2.1
0x0004
PLL0 Status Register (PLL0SR)
Section 12.5.2.2
0x0008
PLL0 Divider Register (PLL0DV)
Section 12.5.2.3
0x000C–0x001F
Reserved
0x0020
PLL1 Control Register (PLL1CR)
Section 12.5.2.4
0x0024
PLL1 Status Register (PLL1SR)
Section 12.5.2.5
0x0028
PLL1 Divider Register (PLL1DV)
Section 12.5.2.6
0x002C
PLL1 Frequency Modulation Register (PLL1FM)
Section 12.5.2.7
0x0030
PLL1 Fractional Divide Register (PLL1FD)
Section 12.5.2.8
0x0034–0x003F
12.5.2
Section
Reserved
Register descriptions
Some of the register reset values are specifically configured for each unique device by
external configuration signals or parameters.
330/2075
RM0483 Rev 5
RM0483
Dual PLL digital interface (PLLDIG)
12.5.2.1
PLL0 control register (PLL0CR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
CLKCFG
0(1)
0(1)
0(1)
LOLIE(2)
0(1)
0(1)
0(1)
R
Access: User read/write
0(1)
Offset: 0x0000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
0
1. This field can be written at any time, but writes are ignored. Reads return previously written value.
2. Refer to the Clocking chapter for details on loss of lock management.
Figure 55. PLL0 control register (PLL0CR)
Table 121. PLL0CR field descriptions
Field
Description
9:8
CLKCFG
Clock configuration
This field indicates the operational state of PLL.
00 PLL off.
01 Reserved
10 Reserved.
11 Normal mode with PLL running
When PLLs are externally powered down the CLKCFG field changes to 00b. When
external power down is removed, these bits read 11b.
Note: In cascaded PLL configuration (PLL0 driving the reference clock for PLL1) the
external power down signal for PLL1 must be removed only when PLL0 has
locked, PLL0SR[LOCK] = 1.
3
LOLIE
Loss of lock FAULT enable
The LOLIE bit enables a loss of lock FAULT request when PLL0SR[LOLF] = 1. If
PLL0SR[LOLF] = 0 or PLL0CR[LOLIE] = 0, the FAULT request is ignored. The FAULT
request only occurs in normal mode.
0 Ignore loss of lock. FAULT not requested
1 Enable FAULT request upon loss of lock
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Dual PLL digital interface (PLLDIG)
12.5.2.2
RM0483
PLL0 status register (PLL0SR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
LOCK
0
R
Access: User read/write
LOLF
Offset: 0x0004
0
W
Reset
R
W
*(1)
w1c
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1. This field is reserved, read only.
Figure 56. PLL0 status register (PLL0SR)
Table 122. PLL0SR field descriptions
12.5.2.3
Field
Description
3
LOLF
Loss of lock flag. W1C to erase the FAULT source.
This bit provides the FAULT flag for the loss of lock condition. Software must write 1 to
LOLF to clear it, writing 0 has no effect. The flag is set when the PLL loses lock or when
the divider/modulation registers are changed on the fly. This flag bit is sticky in the
sense that if lock is reacquired, the bit remains set until cleared by either writing 1 or
asserting reset.
0 No loss of lock detected. FAULT service not requested
1 Loss of lock detected. FAULT service requested
2
LOCK
Lock status bit
Indicates whether PLL has acquired lock.
0 PLL is unlocked
1 PLL is locked
PLL0 divider register (PLL0DV)
The PLL0DV register provides the PHI/PHI1 output clock reduced frequency dividers, predivider, and loop divider.
The values of PREDIV and MFD must not be changed when the PLL is on and locked
(working in Normal mode). If these fields are changed without powering down the PLL, the
PLL loses lock and generates either a reset or an interrupt, based on which is enabled.
The reduced frequency divider fields (RFDPHI, RFDPHI1) can be modified at anytime, but
the changes only become effective after PLL0 is disabled, then re-enabled.
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RM0483 Rev 5
RM0483
Dual PLL digital interface (PLLDIG)
Offset: 0x0008
31
R
Access: User read/write
30
29
0
R
26
25
24
23
22
0
0
0
0
0
21
20
19
18
17
16
RFDPHI
0
–(1)
–(1)
–(1)
–(1)
0
0
0
0
0
–(1)
–(1)
–(1)
–(1)
–(1)
–(1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
–(1)
–(1)
–(1)
0
PREDIV
W
Reset
27
RFDPHI1
W
Reset
28
0
–(1)
–(1)
–(1)
MFD
–(1)
–(1)
–(1)
–(1)
1. Refer to the Clocking chapter for default reset value information.
Figure 57. PLL0 divider register (PLL0DV)
Table 123. PLL0DV field descriptions
Field
Description
PHI1 reduced frequency divider
This 4-bit field determines the VCO/2 clock post divider for driving the PHI1 output clock.
00xx Reserved
30:27
0100 Divide by 4
RFDPHI1 0101 Divide by 5
...
1110 Divide by 14
1111 Divide by 15
21:16
RFDPHI
PHI reduced frequency divider
This 6-bit field determines the VCO clock post divider for driving the PHI output clock.
00 Reserved
01 Divide by 1
02 Divide by 2
03 Divide by 3
...
3E Divide by 62
3F Divide by 63
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RM0483
Table 123. PLL0DV field descriptions (continued)
12.5.2.4
Field
Description
14:12
PREDIV
Input clock pre-divider
This 3-bit field controls the value of the divider on the input clock. The output of the predivider circuit generates the reference clock to the PLL analog loop. The PREDIV value
000b causes the input clock to be inhibited.
000 Clock inhibit
001 Divide by 1
010 Divide by 2
...
110 Divide by 6
111 Divide by 7
6:0
MFD
Loop multiplication factor divider
This 7-bit field controls the value of the divider in the feedback loop. The value specified
by the MFD bits establishes the multiplication factor applied to the reference frequency.
00 Reserved
...
07 Reserved
08 Divide by 8
...
7E Divide by 126
7F Divide by 127
PLL1 control register (PLL1CR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0(1)
0(1)
0(1)
LOLIE(2)
0(1)
0(1)
0(1)
R
Access: User read/write
0(1)
Offset: 0x0020
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
R
W
Reset
0(1)
W
0
CLKCFG
0
0
1. This field can be written at any time, but writes are ignored. Reads return previously written value.
2. Refer to the Clocking chapter for details on loss of lock management.
Figure 58. PLL1 control register (PLL1CR)
334/2075
RM0483 Rev 5
RM0483
Dual PLL digital interface (PLLDIG)
Table 124. PLL1CR field descriptions
12.5.2.5
Field
Description
9:8
CLKCFG
Clock configuration
This field indicates the operational state of PLL.
00 PLL off
01 Reserved
10 Reserved
11 Normal mode with PLL running
When PLLs are externally powered down the CLKCFG field changes to 00b. When
external power down is removed, these bits read 11b.
Note: In cascaded PLL configuration (PLL0 driving the reference clock for PLL1) the
external power down signal for PLL1 must be removed only when PLL0 has
locked, PLL0SR[LOCK] = 1.
3
LOLIE
Loss of lock FAULT enable
The LOLIE bit enables a loss of lock FAULT request when PLL1SR[LOLF] = 1. If
PLL1SR[LOLF] = 0 or PLL1CR[LOLIE] = 0, the FAULT request is ignored. The FAULT
request only occurs in normal mode.
0 Ignore loss of lock. FAULT not requested
1 Enable FAULT request upon loss of lock and enable the FCCU failure "Loss of clock
flag PLL1"
PLL1 status register (PLL1SR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
LOLF
LOCK
R
Access: User read/write
0(1)
Offset: 0x0024
0
0
W
Reset
R
*(1)
W
Reset
0
0
0
0
0
0
0
0
0
0
0
*(1)
w1c
0
0
0
0
0
1. This field is reserved, read only.
Figure 59. PLL1 status register (PLL1SR)
RM0483 Rev 5
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Dual PLL digital interface (PLLDIG)
RM0483
Table 125. PLL1SR field descriptions
12.5.2.6
Field
Description
3
LOLF
Loss of lock flag. W1C for erasing the FAULT source.
This bit provides the FAULT flag for the loss of lock condition. Software must write 1 to
LOLF to clear it, writing 0 has no effect. The flag is set when the PLL loses lock or
when the divider/modulation registers are changed on the fly. This flag bit is sticky in
the sense that if lock is reacquired, the bit remains set until cleared by either writing 1
or asserting reset.
0 No loss of lock detected. FAULT service not requested
1 Loss of lock detected. FAULT service requested
2
LOCK
Lock status bit
Indicates whether PLL has acquired lock.
0 PLL is unlocked
1 PLL is locked
PLL1 divider register (PLL1DV)
The PLL1DV register provides the output clock reduced frequency dividers and loop divider
values.
The value of MFD must not be changed when the PLL is on and locked (working in Normal
mode). If the field is changed without powering down the PLL, the PLL loses lock and
generates either a reset or an interrupt, based on which is enabled.
The reduced frequency divider field (RFDPHI) can be modified at anytime, but the changes
only become effective after PLL1 is disabled, then reenabled.
Offset: 0x0028
R
Access: User read/write
31
30
29
28
27
26
25
24
23
22
0
0
0
0
0
0
0
0
0
0
21
20
0
0
–(1)
–(1)
–(1)
–(1)
–(1)
–(1)
0
0
–(1)
–(1)
–(1)
15
14
13
12
11
10
9
8
7
6
5
4
3
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–(1)
–(1)
1. Refer to the Clocking chapter for default reset value information.
Figure 60. PLL1 divider register (PLL1DV)
336/2075
RM0483 Rev 5
17
16
–(1)
–(1)
–(1)
2
1
0
–(1)
–(1)
–(1)
MFD(1)
W
Reset
18
RFDPHI(1)
W
Reset
19
–(1)
–(1)
RM0483
Dual PLL digital interface (PLLDIG)
Table 126. PLL1DV field descriptions
Field
12.5.2.7
Description
21:16
RFDPHI
PHI reduced frequency divider
This 6-bit field determines the VCO clock post divider for driving the PHI output
clock.
0x00 Reserved
0x01 Divide by 1
0x02 Divide by 2
...
0x3E Divide by 62
0x3F Divide by 63
6:0
MFD
Loop multiplication factor divider
This 7-bit field controls the value of the divider in the feedback loop. The value
specified by the MFD bits establishes the multiplication factor applied to the
reference frequency.
0x10 Divide by 16
0x11 Divide by 17
....
0x21 Divide by 33
0x22 Divide by 34
All other settings are reserved
PLL1 frequency modulation register (PLL1FM)
The PLL1FM register enables frequency modulation on PLL1 and provides controls for the
FM spread spectrum, modulation depth and modulation rate. This register must be written
when PLL1CR[CLKCFG] = 00b (PLL1 powered down).
Changing the values of PLL1FM[MODEN] and PLL1FM[MODSEL] fields once the PLL is
running, and has locked, can result in the PLL losing its lock and the device being reset if
proper FCCU reaction is programmed. The PLL would then require power cycling to regain
normal functionality.
The modulation period (PLL1FM[MODPRD]) and increment step fields (PLL1FM[INCSTP])
can be changed without losing lock, however, the output clock from PLL may have an
incorrect frequency for a few cycles after either of these updates (as defined in the
datasheet).
Offset: 0x002C
30
29
0
R
27
26
25
24
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
MODPRD
0
INCSTP
W
Reset
23
0
W
Reset
28
MODSEL
31
MODEN
R
Access: User read/write
0
0
0
0
0
0
0
0
0
Figure 61. PLL1 frequency modulation register (PLL1FM)
RM0483 Rev 5
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Dual PLL digital interface (PLLDIG)
RM0483
Table 127. PLL1FM field descriptions
Field
Description
30
MODEN
Modulation enable
This bit enables the frequency modulation.
0 Frequency modulation disabled
1 Frequency modulation enabled
29
MODSEL
Modulation selection
This bit selects whether modulation is centered around the nominal frequency or
spread below the nominal frequency.
0 Modulation centered around nominal frequency
1 Modulation spread below nominal frequency
Modulation period
This 13-bit field is the binary equivalent of the modulation period variable derived from
the formula:
28:16
MODPRD
f ref
-)
MODPRD = round(------------------4 × f mod
where fref represents the frequency of the feedback divider and fmod represents the
modulation frequency (refer to equation in Section 12.6.3).
14:0
INCSTP
Increment step
This 15-bit field is the binary equivalent of the INCSTP variable derived from the
formula:
15
2 – 1 ) × MD × PLL1CR [ MFD ]-)
INCSTEP = round((--------------------------------------------------------------------------------------100 × 5 × MODPRD
where md represents the peak modulation depth in percentage (+/- MD for centered
modulation, -2*MD for modulation below nominal frequency), and MFD represents the
nominal value of the feedback loop divider (refer to equation in Section 12.6.3).
12.5.2.8
PLL1 fractional divider register (PLL1FD)
The PLL1FD register provides the enable and fractional divide factor for the loop divider.
This register must be written when PLL1CR[CLKCFG] = 00b (PLL1 powered down).
Changing the values of FDEN once the PLL is running, and has locked, can result in the
PLL losing its lock and the device being reset if proper FCCU reaction is programmed. The
PLL would then require power cycling to regain normal functionality.
The dither disable and fractional divider fields can be changed without losing lock, however,
the output clock from PLL can have an incorrect frequency for a few cycles after either of
these updates.
338/2075
RM0483 Rev 5
RM0483
Dual PLL digital interface (PLLDIG)
31
R
30
29
28
27
26
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
Access: User read/write
FDEN
Offset: 0x0030
16
DTHDIS
FRCDIV
W
Reset
17
0
0
0
0
0
0
0
Figure 62. PLL1 fractional divider register (PLL1FD)
Table 128. PLL1FD field descriptions
Field
Description
30
FDEN
Fractional divide enable
This bit enables the fractional divider in the loop divider for PLL1.
0 Fractional divide disabled
1 Fractional divide enabled
17:16
DTHDIS
Dither disable
Bit 17 and bit 16 control noise of SSCG and Fractional controller.
00 Increase PLL multiplication factor by 1/2^13 and has maximum noise control of SSCG and
Fractional controller.
01 Increase PLL multiplication factor by 1/2^13 and has some noise control of SSCG and Fractional
controller.
10 No influence on PLL multiplication factor and has some noise control of SSCG and Fractional
controller.
11 No influence on PLL multiplication factor and no noise control of SSCG and Fractional controller.
11:0
FRCDIV
Fractional divide input
When the fractional divide is disabled, the VCO clock frequency is the product of the input clock and
the loop divide factor (MFD). When fractional divide is enabled, the mean VCO clock frequency is
given by:
12
VCO Frequency = InputClock × ( PLL1DV [ MFD ] + ( FRCDIV ÷ 2 ) )
where FRCDIV is the decimal equivalent of the FRCDIV bits (refer to Section 12.6.2).
Note: Depending on DTHDIS value the multiplication factor can change as described in DTHDIS field
description.
12.5.3
Register classification for safety requirements
This module is classified as a safety Vital Module (ViMo). Hence, the registers of this
module have been classified as shown in the SR5E1x Reference Manual “Functional
Safety” chapter.
12.6
Functional description
This section explains the operation and configuration of the Dual PLLDIG module.
RM0483 Rev 5
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Dual PLL digital interface (PLLDIG)
12.6.1
RM0483
Input clock frequency
PLL0 and PLL1 are designed to operate over an input clock frequency range. The operating
ranges for each PLL are discussed in detail in the SR5E1x datasheet.
12.6.2
Clock configuration
The relationship between input and output frequency is determined by programming the
PLL0DV, PLL1DV and PLL1FD registers, and calculated according to the following
equations:
Equation 6
PLL0DV [ MFD ]
f pll0_phi = f pll0_ref × -----------------------------------------------------------------------------------------------------------------PLL0DV [ PREDIV ] × PLL0DV [ RFDPHI ]
Equation 7
PLL0DV [ MFD ]
f pll0_phi1 = f pll0_ref × -------------------------------------------------------------------------------------------------------------------PLL0DV [ PREDIV ] × PLL0DV [ RFDPHI1 ]
Equation 8
PLL1FD [ FRCDIV ]
 PLL1DV [ MFD ] + ----------------------------------------------------- 
12


2
-----------------------------------------------------------------------------------------------------f pll1_phi = f pll1_ref × 

2 × PLL1DV [ RFDPHI ]




Note:
Depending on the DTHDIS value the multiplication factor of Equation 8 can change as
described in the PLL1DV[DTHDIS] field description (refer to Table 128).
The relationship between the VCO frequency f VCO and the output frequency of the PLLs is
determined by the configuration of the PLL0DV, PLL1DV and PLL1FD registers, according
to the following equations:
Equation 9
f pll0_ref × PLL0DV [ MFD ] × 2
f pll0_VCO = -------------------------------------------------------------------------------PLL0DV [ PREDIV ]
Equation 10
PLL1FD [ FRCDIV ]
f pll1_VCO = f pll1_ref ×  PLL1DV [ MFD ] + -----------------------------------------------------
12


2
340/2075
RM0483 Rev 5
RM0483
Dual PLL digital interface (PLLDIG)
Note:
Depending on DTHDIS value the multiplication factor of Equation 10 can change as
described in PLL1DV[DTHDIS] field description (refer to Table 128).
Note:
fpll0_phi1 is the reference clock generated by PLL0 for PLL1.
When programming the PLLs, user software must not violate the maximum system clock
frequency or max/min VCO frequency specification for PLL0 or PLL1 (refer to the device
datasheet). Furthermore, the PLL0DV[PREDIV] value must not be set to any value that
causes the input frequency to the phase detector of analog PLL blocks to go below the
prescribed ranges.
The lock signal and PLLnSR[LOCK] flag are immediately negated if the fields of PLLnDV
are changed without powering down the analog PLLs.
When any of these events occur, an internal timer is initialized to count 64 cycles of the PLL
input clock. During this period (64 cycles and a few extra clock cycles for synchronization,
for example, 64 to 72 cycles), the PLLnSR[LOCK] flag is held negated. After the timer
expires, the PLLnSR[LOCK] flag reflects the value coming from the PLL lock detection
circuitry.
The recommended procedure to program the PLLs and engage normal mode is shown in
Section 12.7.
12.6.3
Frequency modulation
Frequency modulation uses a triangular profile as shown in Figure 63. The modulation
frequency and depth are controlled using PLL1FM[MODPRD] and PLL1FM[INCSTP].
Figure 63. Triangular frequency modulation
fpll1_phi = PLL nominal frequency
MD = Modulation depth percentage
fpll1_phi
fpll1_phi
MD
Center spread
2 x MD
Down spread
Note: The device maximum operating frequency includes the frequency modulation. If center modulation is
selected, the fsys must be below fmax by MD percentage such that fmax = fsys(1 + MD%). Refer to the
Analog PLL chapter for more details.
The following equations define how to calculate PLL1FM[MODPRD] (Equation 11) and
PLL1FM[INCSTP] (Equation 12) based on the frequency of the feedback divider (fpll1_ref),
the modulation frequency (fmod) and the modulation depth percentage (MD):
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Equation 11
 f pll1_ref 
PLL1FM[MODPRD] = round  -----------------------
 4 × f mod
Equation 12
15
( 2 – 1 ) × MD × PLL1DV[MFD]
PLL1FM[INCSTP] = round  -----------------------------------------------------------------------------------
 100 × 5 × PLL1FM[MODPRD] 
PLL1FM[MODPRD] and PLL1FM[INCSTP] are subject to the following restriction:
Equation 13
( PLL1FM[MODPRD] × PLL1FM[INCSTP] ) < 2
15
Because of the above rounding operations, the effective modulation depth applied to the
FMPLL is given by the following formula:
Equation 14
PLL1FM [ MODPRD ] × PLL1FM [ INCSTP ] × 100 × 5
ModulationDepth = round  ----------------------------------------------------------------------------------------------------------------------------------------------15


( 2 – 1 ) × PLL1DV [ MFD ]
As an example, suppose the following configuration:
•
Input frequency: 40 MHz
•
Loop divider (PLL1DV[MFD]): 20
•
Input divider: 1
•
Output divider RFD: 5
•
VCO frequency: 40 MHz × 20 = 800 MHz
•
PLL output frequency: 800 MHz / 2*RFD = 800 MHz / 10 = 80 MHz
•
Center spread (PLL1FM[MODSEL] = 0)
•
Modulation frequency: 200 kHz
•
Modulation depth: ± 1.9% (3.8% peak-to-peak)
•
PLL1FM[MODPRD] = Round[(40 × 106) / (4 × 200 × 103)] = Round[50] = 50
•
PLL1FM[INCSTP] = Round[((215 − 1) × 1.9× 20) / (100 × 5 × 50)] = Round[49.8] = 50
•
PLL1FM[MODPRD] × PLL1FM[INCSTP] = 50 × 50 = 2500 (which is less than 215)
•
MD (quantized) = ((50 × 50 × 100 × 5) / ((215 − 1) × 20) = 1.90740%
In this example, the modulation error is 0.00740%.
The FM parameters do not get reset when PLL0 loses its lock. These parameters get reset
on destructive reset. Whenever PLL0 gets relocked FM modulation starts with the previous
values. The sequence for reprogramming the FM is:
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12.7
Dual PLL digital interface (PLLDIG)
1.
Power down PLL1(a)
2.
Program the PLL1FM while PLL1 is powered down
3.
Power up the PLL1(b)
Initialization information
Coming out of reset the PLLs are disabled. The recommended procedure to program the
PLLs is:
1.
2.
3.
Configure PLL0 and related modules.
a)
With PLL0 disabled, program PLL0 clock source in RCC_PLLCFGR[PLL0SRC].
Default source is none.
b)
Program PLL0DV[PREDIV], PLL0DV[RFDPHI1], PLL0DV[MFD] and
PLL0DV[RFDPHI].
c)
If necessary, modify the CMU frequency meter values (CMU_MDR and
CMU_FDR) used to monitor the XOSC frequency. XOSC frequency is compared
to the IRCOSC source when XOSC is turned on.
Turn on XOSC and PLL0.
a)
Set bit RCC_CR[HSEON] and wait for RCC_CR[HSERDY].
b)
Set bit RCC_CR[PLL0ON] and wait for RCC_CR[PLL0LOCK].
Select system clock if you want PLL0 as system clock.
a)
4.
Configure PLL1 and related modules
a)
5.
With PLL1 disabled, program PLL1 clock source in RCC_PLLCFGR[PLL1SRC].
Default is none.
b)
Program PLL1DV[MFD] and PLL1DV[RFDPHI].
c)
If required, program the PLL1FM register with the desired frequency modulation
parameters and enable FM modulation, PLL1FM[MODEN] = 1. The PLL1FM
register must not be written after PLL1 is enabled and operating in normal mode.
Turn on PLL1
a)
6.
Out of reset and up to this point the system clock is 16 MHz HSI. If desired, it is
possible to switch system clock to PLL0, by writing RCC_CFGR[SW] and wait until
RCC_CFGR[SWS] == RCC_CFGR[SW]. This is not the recommended clock
configuration.
Set bit RCC_CR[PLL1ON] and wait for RCC_CR[PLL1LOCK].
Select PLL1 as system clock.
a)
Out of reset and up to this point the system clock is 16 MHz HSI.
b)
Write RCC_CFGR[SW] and wait until RCC_CFGR[SWS] == RCC_CFGR[SW].
This is the recommended clock configuration.
a. By writing RCC_CR [PLL1ON] = 0b.
b. By writing RCC_CR [PLL1ON] = 1b.
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13
Clock Monitor Unit (CMU)
13.1
Introduction
The Clock Monitor Unit (CMU), also referred to as clock quality checker or clock fault
detector, serves three purposes:
•
Measures the frequency of clock sources CLKMT0_RMN/CLKMT1 with
CLKMN0_RMT as the reference clock
•
Monitors CLKMN0_RMT frequency with CLKMT0_RMN as reference clock
•
Monitors CLKMN1 frequency with CLKMT0_RMN as reference clock and also detects
if the monitored clock frequency leaves an upper or lower frequency boundary
One of the tasks is to supervise the integrity of the various clock sources on the chip, for
example CLKMN0_RMT or CLKMN1. If the monitored clock frequency is less than the
reference clock, or it violates an upper or lower frequency boundary, the CMU detects and
reports this event. These events signal the FCCU, which can take the necessary corrective
actions as its configuration dictates.
The CMU can monitor CLKMN0_RMT, which must have a frequency higher than that of
CLKMT0_RMN divided by the division factor shown in CMU_CSR[RCDIV], and reports this
event. The CMU can also monitor CLKMN1 and generate events when the CLKMN1
frequency is less than the CLKMT0_RMN frequency divided by four or if CLKMN1 leaves an
upper or lower frequency boundary. The upper and lower frequency boundaries are defined
by the CMU High Frequency Reference Register (CMU_HFREFR) and CMU Low
Frequency Reference Register (CMU_LFREFR).
The second task of the CMU is to provide a frequency meter, which allows measuring the
frequency of one clock source against a reference clock. This is useful to allow the
calibration of the metered clocks (such as CLKMT0_RMN, CLKMT1), as well as to be able
to correct/calculate the time deviation of a counter that is clocked by the metered clocks.
Note:
Refer to the clocking chapter for the number of instances of the CMU in this device.
13.1.1
Main features
13.2
•
CLKMT0_RMN, CLKMT1 frequency measurement with CLKMN0_RMT as the
reference clock.
•
CLKMN0_RMT monitoring with respect to CLKMT0_RMN/n clock.
•
Upper or lower frequency boundary monitoring of CLKMN1 with respect to
CLKMT0_RMN / 4.
•
Event generation for various failures detected inside monitoring unit.
Block diagram
The block diagram of the CMU module(s) is shown in the clocking chapter of this reference
manual.
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13.3
Clock Monitor Unit (CMU)
Signals
Table 129 describes the signals on the boundary of the CMU (in alphabetical order).
Table 129. Signal description
Signal
I/O
Description
CLKMN0_RMT
I
Monitored Clock Signal 0/Metered Clock Signal Reference: Receives a
clock signal that the CMU compares to a specified low-limit frequency to
determine whether the frequency of the clock signal is greater than the
specified limit. Also provides a reference clock signal for all metered clock
signals.
CLKMN1
I
Monitored Clock Signal 1: Receives a clock signal that the CMU compares
to specified low-limit and high-limit frequencies to determine whether the
frequency of the clock signal is between the specified limits.
CLKMT0_RMN
I
Metered Clock Signal 0/Monitored Clock Signal Reference: Receives a
clock signal that the CMU measures against a reference clock frequency.
Also provides a reference clock signal for all monitored clock signals.
CLKMT1
I
Metered Clock Signal 1: Receives a clock signal that the CMU measures
against a reference clock frequency.
Note:
Refer to the clocking chapter for device specific clock sources of each CMU.
13.4
Memory map and register definition
This section describes in address order all the CMU registers. Each description includes a
standard register diagram with an associated figure number. The CMU memory map is
listed in Table 130.
Table 130. CMU memory map
Address offset
Register
Location
0x0000
CMU Control Status Register (CMU_CSR)
Section 13.4.1.1
0x0004
CMU Frequency Display Register (CMU_FDR)
Section 13.4.1.2
0x0008
CMU High Frequency Reference Register CLKMN1 (CMU_HFREFR)
Section 13.4.1.3
0x000C
CMU Low Frequency Reference Register CLKMN1 (CMU_LFREFR)
Section 13.4.1.4
0x0010
CMU Interrupt Status Register (CMU_ISR)
Section 13.4.1.5
0x0014–0x0017
0x0018
Note:
Reserved
CMU Measurement Duration Register (CMU_MDR)
Section 13.4.1.6
See Clocking chapter for register and field availability details.
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13.4.1
Register descriptions
13.4.1.1
CMU Control Status Register (CMU_CSR)
R
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
SFM(1)
Offset: 0x0000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
CKSEL1(1)
0
0
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
RCDIV(1)
0
CME
0
0
1. Not all CMU blocks utilize this feature. Refer to the clocking chapter for device specific CMU implementation
details.
Figure 64. CMU Control Status Register (CMU_CSR)
Table 131. CMU_CSR field descriptions
Field
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Description
23
SFM
Start Frequency Measure
The software can only set this bit to start a clock frequency measure. It is reset by
hardware when the measure is ready in the CMU_FDR register.
CMU_MDR[MD] must be written before enabling frequency measurement
(CMU_CSR[SFM] = 1). Do not write CMU_MDR[MD] while CMU_CSR[SFM] = 1.
Software must only read the value of CMU_FDR[FD] bits once the hardware has
cleared the CMU_CSR[SFM] bit.
0 Frequency measurement is completed or not yet started.
1 Frequency measurement is not completed.
9:8
CKSEL1
Frequency measure clock selection bit
CKSEL1 selects the clock to be measured by the frequency meter. This only effects
CMU instances that utilizes clock metering.
Not all CMU blocks utilize this feature. See the “Clocking” chapter for device specific
CMU implementation details.
00 CLKMT0_RMN is selected.
01 CLKMT1 is selected.
10 Reserved.
11 CLKMT0_RMN is selected.
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Clock Monitor Unit (CMU)
Table 131. CMU_CSR field descriptions (continued)
13.4.1.2
Field
Description
2:1
RCDIV
CLKMT0_RMN division factor
These bits specify the CLKMT0_RMN division factor. The output clock frequency is
fCLKMT0_RMN divided by the factor 2RCDIV. This output clock is used as reference clock
to compare with CLKMN0_RMT for crystal clock monitor feature.
Ensure clock source for CLKMN0_RMT is off before writing CMU_CSR[RCDIV]
otherwise the operation can lead to a spurious OLR event.
The clock division coding is as follows:
00 CLKMT0_RMN divided by 1 (No division).
01 CLKMT0_RMN divided by 2.
10 CLKMT0_RMN divided by 4.
11 CLKMT0_RMN divided by 8.
0
CME
CLKMN1 monitor enable
CMU_HFREF and CMU_LFREF registers must be written before enabling the clock
monitoring (CMU_CSR[CME] =1)
0 CLKMN1 monitor is disabled.
1 CLKMN1 monitor is enabled.
CMU Frequency Display Register (CMU_FDR)
The FDR is used to determine the measured frequency being monitored by the CMU.
Offset: 0x0004
R
Access: User read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
0
0
0
0
18
17
16
0
0
0
3
2
1
0
0
0
0
0
FD
W
Reset
R
FD
W
Reset
0
0
0
0
0
0
0
0
Figure 65. CMU Frequency Display Register (CMU_FDR)
Table 132. CMU_FDR field descriptions
Field
Description
19:0
FD
Measured frequency bits
This register displays the measured frequency (fsel) with respect to the reference clock
(fCLKMN0_RMT). The measured value is given by the following formula:
fsel = (fCLKMN0_RMT × CMU_MDR[MD]) / CMU_FDR[FD]
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13.4.1.3
RM0483
CMU High Frequency Reference Register CLKMN1 (CMU_HFREFR)
The HFREFR is configured for the high frequency reference that the CMU uses for
comparing against the monitored clock. Figure 66 and Table 133 show the CMU_HFREFR
register.
Offset: 0x0008
R
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
W
Reset
R
HFREF
W
Reset
1
1
1
1
1
1
1
Figure 66. CMU High Frequency Reference Register CLKMN1 (CMU_HFREFR)
Table 133. CMU_HFREFR field descriptions
Field
11:0
HFREF
13.4.1.4
Description
High Frequency reference value
These bits determine the high reference value for the CLKMN1 frequency. The
reference value is given by:
(HFREF / 16) × (fCLKMT0_RMN / 4)
CMU Low Frequency Reference Register CLKMN1 (CMU_LFREFR)
The LFREFR is configured for the low frequency reference that the CMU uses for
comparing against the monitored clock. Figure 67 and Table 134 show the CMU_LFREFR
register.
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Clock Monitor Unit (CMU)
Offset 0x000C
R
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
LFREF
W
Reset
0
0
0
0
0
0
0
Figure 67. CMU Low Frequency Reference Register CLKMN1 (CMU_LFREFR)
Table 134. CMU_LFREFR field descriptions
Field
11:0
LFREF
13.4.1.5
Description
Low Frequency reference value
These bits determine the low reference value for the CLKMN1 frequency. The
reference value is given by:
(LFREF / 16) × (fCLKMT0_RMN / 4)
CMU Interrupt Status Register (CMU_ISR)
Offset: 0x0010
R
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
FLCI FHHI FLLI
OLRI(1)
W
w1c
w1c
w1c
w1c
0
0
0
0
1. Not all CMU blocks utilize this feature. See Clocking chapter for device specific CMU implementation details.
Figure 68. CMU Interrupt Status Register (CMU_ISR)
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Table 135. CMU_ISR field descriptions
Note:
Field
Description
3
FLCI
CLKMN1 frequency less than reference clock event status
This bit is set by hardware when CLKMN1 frequency becomes lower than reference
clock frequency (fCLKMT0_RMN/4) value and CLKMN1 is ‘ON’ as signaled by the
RCC. It can be cleared by software by writing ‘1’.
0 No FLC event
1 FLC event occurred
2
FHHI
CLKMN1 frequency higher than high reference event status
This bit is set by hardware when CLKMN1 frequency becomes higher than HFREF
value and CLKMN1 is ‘ON’ as signaled by the RCC. It can be cleared by software by
writing ‘1’.
0 No FHH event
1 FHH event occurred
1
FLLI
CLKMN1 frequency less than low reference event status
This bit is set by hardware when CLKMN1 frequency becomes lower than LFREF
value and CLKMN1 is ‘ON’ as signaled by the RCC. It can be cleared by software by
writing ‘1’.
0 No FLL event
1 FLL event occurred
0
OLRI
Oscillator frequency less than fCLKMT0_RMN / 2RCDIV event status
This bit is set by hardware when the fCLKMN0_RMT is less than fCLKMT0_RMN / 2RCDIV
frequency and CLKMN0_RMT is ‘ON’ as signaled by the RCC. It can be cleared by
software by writing ‘1’.
0 No OLR event
1 OLR event occurred
All the flags in CMU_ISR are set asynchronously. This register must be read only after a
fault event is triggered by the CMU and mapped on FCCU.
Otherwise, the read access on this register may fetch an incorrect value.
Before entering low-power stop modes, all clock frequency measurements in CMU must be
disabled. Failing to do so may result in spurious interrupts.
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Clock Monitor Unit (CMU)
13.4.1.6
CMU Measurement Duration Register (CMU_MDR)
Offset: 0x0018
R
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
0
0
0
0
18
17
16
0
0
0
3
2
1
0
0
0
0
0
MD
W
Reset
R
MD
W
Reset
0
0
0
0
0
0
0
0
Figure 69. CMU Measurement Duration Register (CMU_MDR)
Table 136. CMU_MDR field descriptions
13.5
Field
Description
19:0
MD
Measurement duration bits
This field displays the measurement duration in terms of selected clock
(CLKMT0_RMN, CLKMT1) cycles. This value is loaded in the frequency meter
down-counter. The down-counter starts counting when CMU_CSR [SFM] = 1. The
application software must program CMU_MDR[MD] with a value that does not
saturate CMU_FDR[FD] to 20'hFFFFF.
Functional description
This section describes the functionality of the CMU.
13.5.1
Frequency meter
The purpose of frequency meter is to evaluate the deviation from the nominal metered
source (such as, CLKMT0_RMN, CLKMT1) frequencies. This in turn allows either
recalibration of these clocks or other timing corrections. Programming of the
CMU_CSR[CKSEL1] field is used to select one of metered clocks from a multiplexer that
drives a simple Frequency Meter (see the CMU Block Diagram in the Clocking chapter). The
reference clock for the Frequency Meter is the CLKMN0_RMT signal. The measurement
starts when CMU_CSR[SFM] = 1. The measurement duration is given by the contents of
CMU_MDR[MD] in terms of number of clock cycles of the selected metered clock. The
CMU_CSR[SFM] bit is cleared by hardware once the frequency measurement is complete
and the count is loaded in CMU_FDR[FD]. The frequency of the selected clock (fsel) can be
derived from the value loaded in the CMU_FDR as shown in the following equation:
Equation 15
fsel = (fCLKMN0_RMT x MDR[MD]) / FDR[FD]
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13.5.2
RM0483
CLKMN0_RMT supervisor
If frequency of CLKMN0_RMT is smaller than frequency of CLKMT0_RMN divided by
2CMU_CSR[RCDIV] and CLKMN0_RMT is ‘ON’ as signaled by the RCC, then:
13.5.3
•
The CMU writes 1 to CMU_ISR[OLRI].
•
The CMU asserts the OLR signal.
CLKMN1 supervisor
The frequency of CLKMN1(fCLKMN1) can be monitored by programming
CMU_CSR[CME] = 1. CLKMN1 monitoring starts as soon as CMU_CSR[CME] = 1. This
monitor can be disabled at any time by programming CMU_CSR[CME] = 0.
If fCLKMN1 is greater than the reference value determined by field CMU_HFREFR[HFREF]
and CLKMN1 is ‘ON’ as signaled by the RCC, then:
Note:
Note:
•
The CMU writes 1 to CMU_ISR[FHHI].
•
The CMU asserts the FHH signal.
The high reference value must be programmed considering the following factors:
•
2 cycles of fCLKMN1 which is the built-in tolerance of the monitor implementation.
•
Frequency variation% of fCLKMT0_RMN across PVT.
An example of determining the HFREFActual value is as follows. Assume a
fCLKMT0_RMN = 16 MHz with an accuracy of +/-5%. In order to monitor
fCLKMN1 = 200 MHz, the ideal HFREFIdeal = 800. The actual HFREF value is 842 when
the accuracy is taken into consideration (HFREFActual = (HFREFIdeal + 2) × 1.05).
If fCLKMN1 is less than a reference clock frequency (fCLKMT0_RMN/4) and the CLKMN1 is
‘ON’ as signaled by the RCC, then:
The CMU writes 1 to kCMU_ISR[FLCI].
fCLKMN1 must be greater than fCLKMT0_RMN / 4 by at least 0.5 MHz in order to guarantee the
correct CLKMN1 monitoring.
If fCLKMN1 is lower than CMU_LFREFR[LFREF] and CLKMN1 is ‘ON’ as signaled by the
RCC, then:
Note:
•
The CMU writes 1 to CMU_ISR[FLLI].
•
The CMU asserts the FLL signal.
The low reference value must be programmed considering the following factors:
•
Two cycles of fCLKMN1 which is the built-in tolerance of the monitor implementation
•
Frequency variation % of fCLKMT0_RMN across PVT
For example, assuming fCLKMT0_RMN is 16 MHz with +/-5% variation, in order to monitor the
fCLKMN1 (200 MHz), the ideal LFREFIdeal is 800. The adjusted value considering the
tolerances is 758 (LFREFActual = (LFREFIdeal - 2) x 0.95).
The minimum value that can be programmed in CMU_LFREFR[LFREF] is 3. The minimum
frequency that can be monitored using the CLKMN1 supervisor is >= fCLKMT0_RMN / 16.
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Power management controller digital interface (PMC_Dig)
14
Power management controller digital interface
(PMC_Dig)
14.1
Introduction
The Control PMU manages the PMU at reset and during run. It checks the LVD or HVD
accuracy.
The PMC analog block interfaces the digital part of the device by the PMC_Dig block.
This chapter describes the digital block of the PMU.
The PMC_Dig contains all of the registers and digital logic to generate all of the enable
signals, two stage trim control bits, power on reset (POR) generation and test mode logic for
the analog block. The PMU digital logic also contains the controls for PMU analog outputs to
be sensed with the ADC module.
In addition, the PMU digital logic contains the enable signals, trim bits and other registers for
the temperature sensor for SOC and a dedicated temperature sensor for RC regulator.
There are also several custom interfaces to various other blocks: the Reset and Clock
Control (RCC) block receives the LVD values during POR to use for phase transition
conditions.
There is one custom interface to Flash memory via the SSCM (and DCF client blocks) that
is used to load the trim values during initial POR.
The PMU digital block generates a transfer error event to the system if the selected address
is out of range of PMU digital memory map. A transfer error is not generated if an unused
address within the PMU digital memory space is accessed. Figure 70 shows the top level
block diagram of the digital PMU and its interfaces to the device modules.
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Figure 70. Digital PMU block diagram
ADC
Digital
Interface
Temp
Sensor
Flash
Memory
ADC
Analog
Switches
PMU
Digital
Interface
PMU
Analog
full_volt
DCF
Clients
SSCM
Reset and
Phase Exit
Generation
rstb_phase_gate
RCC
ipg_hard_async_reset_por_b
Shadow
Register
Test
Signals
Test
Registers
lvd_hvd_override
354/2075
ipg_por_b
Phase resets
TCU
Pads
PORST
ADC
Analog
PMU
Register
Bits
OKins
RM0483 Rev 5
RM0483
14.2
14.2.1
Power management controller digital interface (PMC_Dig)
Main features
•
PMU management at a main reset
•
Resets signal generation
Standard features
•
14.3
IPS bus interface
IPS bus interface
The IPS bus interface is a slave bus used for configuration purposes via CPU. The following
bus operations (contiguous byte enables) are supported:
–
Word (32 bits) data write/read operations to any registers
–
Low and high half-words (16 bits, data[31:16] or data[15:0]) data write/read
operations to any registers
–
Byte (8 bits, data[31:24] or data[23:16] or data[15:8] or data[7:0]) data write/read
operations to any registers
–
Any other operation (free byte enables or other operations) must be avoided
The PMC_Dig block generates a transfer error in the following cases:
–
The PMU digital block generates a transfer error event to the system if the
selected address is out of range of PMU digital memory map. A transfer error is
not generated if an unused address within the PMU digital memory space is
accessed
–
Any write/read operation different from byte/hword/word (free byte enables or
other operations) on each register
The registers of the PMC_Dig block are accessible (read/write) in each access mode: user,
supervisor or test.
About the Reset used among the registers:
14.4
–
The POR reset is used on EPR_LVx, EPR_HVx, REE_LVx, REE_HVx, RES_LVx
and RES_HVx registers
–
The destructive reset is used on REE_TD, RES_TD, FEE_LVx, FEE_HVx and
FEE_TD registers
–
The functional reset is used on IE_HVx, IE_LVx, IE_G, CTL_TD registers
Memory map/register definition
Table 137 shows the PMU memory map. The PMU includes many registers for configuring
and monitoring LVD monitors and some other control registers.
Table 137. Power Management Controller Memory Map
Offset
Register name
Location
0x0000
Event Pending Register LV0 (EPR_LV0)
Section 14.5.1
0x0004
Reset Event Enable LV0 (REE_LV0)
Section 14.5.2
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Table 137. Power Management Controller Memory Map (continued)
Offset
Register name
0x0008
Reset Event Select LV0 (RES_LV0)
Section 14.5.3
0x000C
Interrupt Enable LV0 (IE_LV0)
Section 14.5.4
0x0010
FCCU Event Enable LV0 (FEE_LV0)
Section 14.5.5
0x0014–0x001F
Reserved
0x0020
Event Pending Register LV1 (EPR_LV1)
Section 14.5.6
0x0024
Reset Event Enable LV1 (REE_LV1)
Section 14.5.7
0x0028
Reset Event Select LV1 (RES_LV1)
Section 14.5.8
0x002C
Interrupt Enable LV1 (IE_LV1)
Section 14.5.9
0x0030
FCCU Event Enable LV1 (FEE_LV1)
Section 14.5.10
0x0034–0x003F
Reserved
0x0040
Event Pending Register HV0 (EPR_HV0)
Section 14.5.11
0x0044
Reset Event Enable HV0 (REE_HV0)
Section 14.5.12
0x0048
Reset Event Selection HV0 (RES_HV0)
Section 14.5.13
0x004C
Interrupt Enable HV0 (IE_HV0)
Section 14.5.14
0x0050
FCCU Event Enable HV0 (FEE_HV0)
Section 14.5.15
0x0054–0x007F
Reserved
0x0080
Supply Gauge Status Register (GR_S)
Section 14.5.16
0x0084
Pending Gauge Status Register (GR_P)
Section 14.5.17
0x0088
Global Interrupt Enable Register (IE_G)
Section 14.5.18
0x008C–0x0243
0x0244
Reserved
HPREG SMPS Sel Status Register
(HPREG_SMPS_SEL_S)
0x0248–0x02FF
Section 14.5.19
Reserved
0x0300
Temperature Event Pending register (EPR_TD)
Section 14.5.20
0x0304
Temperature Reset Event Enable register
(REE_TD)
Section 14.5.21
0x0308
Temperature Reset Event Selection register
(RES_TD)
Section 14.5.22
0x030C
Temperature sensor configuration register
(CTL_TD)
Section 14.5.23
0x0310–0x0317
0x0318
Reserved
Temperature FCCU Event Enable register
(FEE_TD)
0x031C–0x03C7
0x03C8
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Location
Section 14.5.24
Reserved
BIST Mask Status register
(BIST_MASK_STATUS)
RM0483 Rev 5
Section 14.5.25
RM0483
Power management controller digital interface (PMC_Dig)
Table 137. Power Management Controller Memory Map (continued)
Offset
Register name
Location
0x03CC
User BIST Flags register
phase1(BIST_FLAGS_PHASE1)
Section 14.5.26
0x03D0
User BIST Flags register
phase2(BIST_FLAGS_PHASE2)
Section 14.5.27
0x03D4
User BIST Control register (BIST_CTRL)
Section 14.5.28
0x03D8
User BIST Time1 and Time0 register
(BIST_TIME10)
Section 14.5.29
0x03DC
User BIST Time3 and Time2 register
(BIST_TIME32)
Section 14.5.30
0x03E0
User BIST Time6 and Time5 register
(BIST_TIME65)
Section 14.5.31
0x03E4
User BIST VD Under Test Monitor Register
(BIST_DEBUG)
Section 14.5.32
Table 138 shows how the 32-bit registers for LV0, LV1, and HV0 are organized.
Table 138. 32-bit registers LV0, LV1, HV0 arrangement table
Register
class
BYTE 3(1)
(bits [31:24])
BYTE 2(1)
(bits [23:16])
BYTE 1(1)
(bits [15:8])
BYTE 0(1)
(bits [7:0])
LV0
VD3 =
LVD119_C_FL_DD
LVD119_RC_PLL0/1
VD2 =
Reserved
VD1 =
Reserved
VD0 =
Reserved
LV1
VD7 =
UVD145_RC
VD6 =
HVD140_C
VD5 =
Not implemented
VD4 =
Not implemented
HV0
VD11 =
LVD290_AD_AS
LVD290_FL_C_IO0_IO1
VD10 =
LVD290_DACCMP_
OSC
UVD380_AS_DACCMP
VD9 =
Not implemented
VD8 =
Reserved
1. Refer to Section 14.5: Registers description.
Table 139 shows the correspondence between VD number and VD name, where HV means
a 3.3 V supply and LV means a 1.2 V supply.
Table 139. VD number versus VD name
VD
number
VD name
VD meaning
VD0
POR031_C
LV detector asserts when PMU supply < 0.31 V
VD1
MVD102T_C
LV detector asserts when PMU supply < 1.02 V
VD2
MVD114_C
LV detector asserts when PMU supply < 1.14 V
VD2
MVD114_FA
LV detector asserts when Flash supply < 1.14 V
VD3
LVD119_C
LV detector asserts when PMU supply < 1.19 V
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Table 139. VD number versus VD name (continued)
VD
number
VD name
VD meaning
VD3
LVD119_FL
LV detector asserts when Flash supply < 1.19 V
VD6
HVD140_C
LV detector asserts when PMU supply > 1.40 V
VD7
UVD145_C
LV detector asserts when PMU supply > 1.45 V
VD7
UVD145_RC
LV detector asserts when RCOSC supply > 1.45 V
VD8
POR200_C
HV detector asserts when PMU supply < 2.00 V
VD9
MVD240T_C
HV detector asserts when PMU supply < 2.40 V
VD10
MVD270_C
HV detector asserts when PMU supply < 2.70 V
VD10
MVD270_FL
HV detector asserts when Flash supply < 2.70 V
VD11
LVD290_DACCMP
HV detector asserts when DAC/CMP supply < 2.90V
VD11
LVD290_OSC
HV detector asserts when OSC supply < 2.90V
VD11
LVD290_AD
HV detector asserts when sigma delta ADC supply < 2.90 V
VD11
LVD290_AS
HV detector asserts when SAR ADC supply < 2.90 V
VD11
LVD290_C
HV detector asserts when PMU supply < 2.90 V
VD11
LVD290_FL
HV detector asserts when Flash supply < 2.90 V
VD11
LVD290_IO0
HV detector asserts when IO RING0 supply < 2.90 V
VD11
LVD290_IO1
HV detector asserts when IO RING1 supply < 2.90 V
VD15
UVD380_C
HV detector asserts when PMU supply > 3.80 V
VD15
UVD380_FL
HV detector asserts when Flash supply > 3.80 V
VD15
UVD380_IO0
HV detector asserts when IO RING0 supply > 3.80 V
VD15
UVD380_AS
HV detector asserts when SARADC supply > 3.80 V
VD15
UVD380_DACCMP
HV detector asserts when DAC/CMP supply > 3.80V
14.5
Registers description
14.5.1
Event Pending Register (EPR_LV0)
This Event Pending Register indicates the present and past state of the voltage detect
signals in LOW VOLTAGE 0 range. If the voltage detect event has ever passed the trigger
event since the last clearing event, the flag bit is set. In order to clear the flag, a one must be
written to the flag bit that needs to be cleared.
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Power management controller digital interface (PMC_Dig)
Access: User read/write, Supervisor read/write, Test read/write
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LVD3_FL
27
LVD3_DD
28
LVD3_RC
29
LVD3_PLL0
30
LVD3_PLL1
31
LVD3_C
Offset: 0x0000
W w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
Reset
R
w1c
0
0
W
Reset
Figure 71. Event Pending Register (EPR_LV0)
Table 140. EPR_LV0 field descriptions
Field
Description
LVD3_PLL1 flag. This bit is the low-voltage status flag associated with LVD119_PLL1
VD, the voltage level detect for the low voltage PLL1 1.19 V supply. It is asserted when
the supply falls below its corresponding Voltage Detector 3 threshold, and clears when
31
the supply rises above its corresponding LVD3 threshold and a ‘1’ is written to this bit
LVD3_PLL1 location.
0 Currently no occurrence
1 VD occurrence detected on the low voltage 1.19 V point supply
LVD3_PLL0 flag. This bit is the low-voltage status flag associated with LVD119_PLL0
VD, the voltage level detect for the low voltage PLL0 1.19 V supply. It is asserted when
the supply falls below its corresponding Voltage Detector 3 threshold, and clears when
30
the supply rises above its corresponding LVD3 threshold and a ‘1’ is written to this bit
LVD3_PLL0 location.
0 Currently no occurrence
1 VD occurrence detected on the low voltage 1.19 V point supply
29
LVD3_RC
LVD3_RC flag. This bit is the low-voltage status flag associated with LVD119_RC VD,
the voltage level detect for the low voltage RCOSC 1.19 V supply. It is asserted when
the supply falls below its corresponding Voltage Detector 3 threshold, and clears when
the supply rises above its corresponding LVD3 threshold and a ‘1’ is written to this bit
location.
0 Currently no occurrence
1 VD occurrence detected on the low voltage 1.19 V point supply
27
LVD3_DD
LLVD3_DD flag. This bit is the low-voltage status flag associated with LVD119_DD VD,
the voltage level detect for the low voltage DLL 1.19 V supply. It is asserted when the
supply falls below its corresponding Voltage Detector 3 threshold, and clears when the
supply rises above its corresponding LVD3 threshold and a ‘1’ is written to this bit
location.
0 Currently no occurrence
1 VD occurrence detected on the low voltage 1.19 V point supply
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RM0483
Table 140. EPR_LV0 field descriptions (continued)
14.5.2
Field
Description
26
LVD3_FL
LVD3_FL flag. This bit is the low-voltage status flag associated with LVD119_FL VD,
the voltage level detect for the low voltage Flash 1.19 V supply. It is asserted when the
supply falls below its corresponding Voltage Detector 3 threshold, and clears when the
supply rises above its corresponding LVD3 threshold and a ‘1’ is written to this bit
location.
0 Currently no occurrence
1 VD occurrence detected on the low voltage 1.19 V point supply
24
LVD3_C
LVD3_C flag
This bit is the low-voltage status flag associated with LVD119_C VD, the voltage level
detect for the low voltage CORE 1.19 V supply. It is asserted when the supply falls
below its corresponding Voltage Detector 3 threshold, and clears when the supply rises
above its corresponding LVD3 threshold and a ‘1’ is written to this bit location.
0 Currently no occurrence
1 VD occurrence detected on the low voltage 1.19 V point supply
Reset Event Enable Register (REE_LV0)
This Reset Event Enable Register controls whether the voltage detect signal event causes a
reset. If the desired flag bit is enabled, the voltage detect event causes a reset to be
generated when the selected voltage passes the trigger event. These bits are loaded from
the Flash during the boot sequence. If the Flash loaded bits are programmed to be enabled
(set), these bits cannot be disabled (cleared).
Offset: 0x0004
27
26
25
0
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
REE3_C
REE3_FL
0
REE3_DD
R
28
REE3_RC
Reset
29
REE3_PLL0
W
30
REE3_PLL1
31
R
Access: User read/write, Supervisor read/write, Test read/write
0
W
Reset
Figure 72. Reset Event Enable Register (REE_LV0)
360/2075
RM0483 Rev 5
RM0483
Power management controller digital interface (PMC_Dig)
Table 141. REE_LV0 field descriptions
14.5.3
Field
Description
31
REE3_PLL1
REE3_PLL1 reset enable
This bit defines whether LVD119_PLL1 VD, the voltage level detect for the low
voltage of 1.19 V on PLL1 supply, generates a system reset. The RES3_PLL1 bit
determines whether the reset is functional or destructive.
0 Disabled. LVD assertion on the supply of the cold point does not cause system
reset.
1 Enabled. LVD assertion on the supply of the cold point causes system reset.
30
REE3_PLL0
REE3_PLL0 reset enable
This bit defines whether LVD119_PLL0 VD, the voltage level detect for the low
voltage of 1.19 V on PLL0 supply, generates a system reset. The RES3_PLL0 bit
determines whether the reset is functional or destructive.
0 Disabled. LVD assertion on the supply of the cold point does not cause system
reset.
1 Enabled. LVD assertion on the supply of the cold point causes system reset.
29
REE3_RC
REE3_RC reset enable
This bit defines whether LVD119_RC VD, the voltage level detect for the low voltage
of 1.19 V on RCOSC supply, generates a system reset. The RES3_RC bit
determines whether the reset is functional or destructive.
0 Disabled. LVD assertion on the supply of the cold point does not cause system
reset.
1 Enabled. LVD assertion on the supply of the cold point causes system reset.
27
REE3_DD
REE3_DD reset enable
This bit defines whether LVD119_DD VD, the voltage level detect for the low voltage
of 1.19 V on DLL supply, generates a system reset. The RES3_DLL bit determines
whether the reset is functional or destructive.
0 Disabled. LVD assertion on the supply of the cold point does not cause system
reset.
1 Enabled. LVD assertion on the supply of the cold point causes system reset.
26
REE3_FL
REE3_FL reset enable
This bit defines whether LVD119_FL VD, the voltage level detect for the low voltage
of 1.19 V on Flash supply, generates a system reset. The RES3_FL bit determines
whether the reset is functional or destructive.
0 Disabled. LVD assertion on the supply of the cold point does not cause system
reset.
1 Enabled. LVD assertion on the supply of the cold point causes system reset.
24
REE3_C
REE3_C reset enable
This bit defines whether LVD119_C VD, the voltage level detect for the low voltage
Core 1.19 V supply, generates a system reset. The RES3_C bit determines whether
the reset is functional or destructive.
0 Disabled. LVD assertion on the supply of the cold point does not cause system
reset.
1 Enabled. LVD assertion on the supply of the cold point causes system reset.
Reset Event Select Register (RES_LV0)
This Reset Event Select Register controls, in LOW VOLTAGE 0 range, whether the voltage
detect signal event causes a destructive or functional reset. If the desired flag bit is enabled,
RM0483 Rev 5
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RM0483
the voltage detect event causes either a destructive or functional reset to be generated
when the selected voltage passes the trigger event. These bits are loaded from the Flash
during the boot sequence.
Offset: 0x0008
27
26
25
0
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RES3_C
RES3_FL
0
RES3_DD
R
28
RES3_RC
Reset
29
RES3_PLL0
W
30
RES3_PLL1
31
R
Access: User read/write, Supervisor read/write, Test read/write
0
W
Reset
Figure 73. Reset Event Select Register (RES_LV0)
Table 142. RES_LV0 field descriptions
362/2075
Field
Description
31
RES3_PLL1
RES3_PLL1 reset event select
This bit defines whether LVD119_PLL1 VD, the voltage level detect for the low
voltage PLL1 1.19 V supply of the cold point, generates a destructive reset or a
functional reset. The REE3_PLL1 bit determines whether the reset event is enabled.
0 Destructive Reset Generated. LVD assertion on the supply of the cold point causes
a destructive system reset.
1 Functional Reset Generated. LVD assertion on the supply of the cold point causes
a functional system reset.
30
RES3_PLL0
RES3_PLL0 reset event select
This bit defines whether LVD119_PLL0 VD, the voltage level detect for the low
voltage PLL0 1.19 V supply of the cold point, generates a destructive reset or a
functional reset. The REE3_PLL0 bit determines whether the reset event is enabled.
0 Destructive Reset Generated. LVD assertion on the supply of the cold point causes
a destructive system reset.
1 Functional Reset Generated. LVD assertion on the supply of the cold point causes
a functional system reset.
29
RES3_RC
RES3_RC reset event select
This bit defines whether LVD119_RC VD, the voltage level detect for the low voltage
RCOSC 1.19 V supply of the cold point, generates a destructive reset or a functional
reset. The REE3_RC bit determines whether the reset event is enabled.
0 Destructive Reset Generated. LVD assertion on the supply of the cold point causes
a destructive system reset.
1 Functional Reset Generated. LVD assertion on the supply of the cold point causes
a functional system reset.
RM0483 Rev 5
RM0483
Power management controller digital interface (PMC_Dig)
Table 142. RES_LV0 field descriptions (continued)
14.5.4
Field
Description
27
RES3_DD
RES3_DD reset event select
This bit defines whether LVD119_DD VD, the voltage level detect for the low voltage
DLL 1.19 V supply of the cold point, generates a destructive reset or a functional
reset. The REE3_DD bit determines whether the reset event is enabled.
0 Destructive Reset Generated. LVD assertion on the supply of the cold point causes
a destructive system reset.
1 Functional Reset Generated. LVD assertion on the supply of the cold point causes
a functional system reset.
26
RES3_FL
RES3_FL reset event select
This bit defines whether LVD119_FL VD, the voltage level detect for the low voltage
Flash 1.19 V supply of the cold point, generates a destructive reset or a functional
reset. The REE3_FL bit determines whether the reset event is enabled.
0 Destructive Reset Generated. LVD assertion on the supply of the cold point causes
a destructive system reset.
1 Functional Reset Generated. LVD assertion on the supply of the cold point causes
a functional system reset.
24
RES3_C
RES3_C reset event select
This bit defines whether LVD119_C VD, the voltage level detect for the low voltage
Core 1.19 V supply of the cold point, generates a destructive reset or a functional
reset. The REE3_C bit determines whether the reset event is enabled.
0 Destructive Reset Generated. LVD assertion on the supply of the cold point causes
a destructive system reset.
1 Functional Reset Generated. LVD assertion on the supply of the cold point causes
a functional system reset.
Interrupt Enable (IE_LV0)
This configuration register contains a set of LV0 interrupt Enable bits that correspond to
each of the LV0 Event Pending Registers (EPR_LV0). These bits indicate whether an
interrupt is enabled waiting for a potential voltage event. A ‘0’ indicates that no interrupt is
enabled, and a ‘1’ indicates that an interrupt is enabled. These bits are replicated as a readonly monitor in the register (IE_G) at address 0x0088. The IE_LV0 bits can be read or
written at any time.
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Power management controller digital interface (PMC_Dig)
Offset: 0x000C
28
27
26
25
0
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VD3IE_C
VD3IE_FL
0
VD3IE_DD
R
29
VD3IE_RC
Reset
30
VD3IE_PLL0
W
Access: User read/write, Supervisor read/write, Test read/write
VD3IE_PLL1
31
R
RM0483
0
W
Reset
Figure 74. Interrupt Enable Register (IE_LV0)
Table 143. IE_LV0 field descriptions
Field
Description
VD3IE_PLL1 Interrupt Enable
This bit determines whether an interrupt is enabled or disabled for the LVD119_PLL1
31
VD, the voltage level detect for the low voltage PLL1 1.19 V supply event.
VD3IE_PLL1
0 Interrupt disabled
1 Interrupt enabled
VD3IE_PLL0 Interrupt Enable
This bit determines whether an interrupt is enabled or disabled for the LVD119_PLL0
30
VD, the voltage level detect for the low voltage PLL0 1.19 V supply event.
VD3IE_PLL0
0 Interrupt disabled
1 Interrupt enabled
364/2075
29
VD3IE_RC
VD3IE_RC Interrupt Enable
This bit determines whether an interrupt is enabled or disabled for the LVD119_RC
VD, the voltage level detect for the low voltage RCOSC 1.19 V supply event.
0 Interrupt disabled
1 Interrupt enabled
27
VD3IE_DD
VD3IE_DD Interrupt Enable
This bit determines whether an interrupt is enabled or disabled for the LVD119_DD
VD, the voltage level detect for the low voltage DLL 1.19 V supply event.
0 Interrupt disabled
1 Interrupt enabled
26
VD3IE_FL
VD3IE_FL Interrupt Enable
This bit determines whether an interrupt is enabled or disabled for the LVD119_FL
VD, the voltage level detect for the low voltage Flash 1.19 V supply event.
0 Interrupt disabled
1 Interrupt enabled
24
VD3IE_C
VD3IE_C Interrupt Enable
This bit determines whether an interrupt is enabled or disabled for the LVD119_C VD,
the voltage level detect for the low voltage Core 1.19 V supply event.
0 Interrupt disabled
1 Interrupt enabled
RM0483 Rev 5
RM0483
Power management controller digital interface (PMC_Dig)
14.5.5
FCCU Event Enable Register (FEE_LV0)
This FCCU Event Enable Register LV0 controls whether the voltage detect signal events
cause an event signal to be sent to the FCCU (Fault Collection and Control Unit). If the
desired flag bit is enabled, the voltage detect event causes an FCCU event to be generated
when the selected voltage passes the trigger event.
Offset: 0x0010
27
26
25
0
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FEE3_C
FEE3_FL
0
FEE3_DD
R
28
FEE3_RC
Reset
29
FEE3_PLL0
W
30
FEE3_PLL1
31
R
Access: User read/write, Supervisor read/write, Test read/write
0
W
Reset
Figure 75. FCCU Event Enable Register (FEE_LV0)
Table 144. FEE_LV0 field descriptions
Field
Description
FEE3_PLL1 FCCU event enable
This bit defines whether a VD assertion of LVD119_PLL1 VD, the voltage level detect
31
for the low voltage PLL1 1.19 V supply, generates an FCCU event.
FEE3_PLL1 0 Disabled. A VD assertion of LV0 on the supply of the PLL1 does not cause an FCCU
event.
1 Enabled. A VD assertion of LV0 on the supply of the PLL1 causes an FCCU event.
FEE3_PLL0 FCCU event enable
This bit defines whether a VD assertion of LVD119_PLL0 VD, the voltage level detect
30
for the low voltage PLL0 1.19 V supply, generates an FCCU event.
FEE3_PLL0 0 Disabled. A VD assertion of LV0 on the supply of the PLL0 does not cause an FCCU
event.
1 Enabled. A VD assertion of LV0 on the supply of the PLL0 causes an FCCU event.
29
FEE3_RC
FEE3_RC FCCU event enable
This bit defines whether a VD assertion of LVD119_RC VD, the voltage level detect for
the low voltage RCOSC 1.19 V supply, generates an FCCU event.
0 Disabled. A VD assertion of LV0 on the supply of the RCOSC does not cause an
FCCU event.
1 Enabled. A VD assertion of LV0 on the supply of the RCOSC causes an FCCU event.
27
FEE3_DD
FEE3_DD FCCU event enable
This bit defines whether a VD assertion of LVD119_DD VD, the voltage level detect for
the low voltage DLL 1.19 V supply, generates an FCCU event.
0 Disabled. A VD assertion of LV0 on the supply of the DLL does not cause an FCCU
event.
1 Enabled. A VD assertion of LV0 on the supply of the DLL causes an FCCU event.
RM0483 Rev 5
365/2075
407
Power management controller digital interface (PMC_Dig)
RM0483
Table 144. FEE_LV0 field descriptions (continued)
14.5.6
Field
Description
26
FEE3_FL
FEE3_FL FCCU event enable
This bit defines whether a VD assertion of LVD119_FL VD, the voltage level detect for
the low voltage Flash 1.19 V supply, generates an FCCU event.
0 Disabled. A VD assertion of LV0 on the supply of the Flash does not cause an FCCU
event.
1 Enabled. A VD assertion of LV0 on the supply of the Flash causes an FCCU event.
24
FEE3_C
FEE3_C FCCU event enable
This bit defines whether a VD assertion of LVD119_C VD, the voltage level detect for
the low voltage Core 1.19 V supply, generates an FCCU event.
0 Disabled. A VD assertion of LV0 on the supply of the Core does not cause an FCCU
event.
1 Enabled. A VD assertion of LV0 on the supply of the Core causes an FCCU event.
Event Pending Register (EPR_LV1)
This Event Pending Register indicates the present and past state of the voltage detect
signals in LOW VOLTAGE 1 range. If the voltage detect event has ever passed the trigger
event since the last clearing event, the flag bit is set. In order to clear the flag, a ‘1’ must be
written to the flag bit that needs to be cleared.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
w1c
16
HVD6_C
R
Access: User read/write, Supervisor read/write, Test read/write
UVD7_RC
Offset: 0x0020
w1c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Figure 76. Event Pending Register (EPR_LV1)
366/2075
RM0483 Rev 5
RM0483
Power management controller digital interface (PMC_Dig)
Table 145. EPR_LV1 field descriptions
14.5.7
Field
Description
29
UVD7_RC
UVD7_RC flag
This bit is the low-voltage status flag associated with UVD145_RC VD, the voltage
level detect for the low voltage RCOSC 1.45 V supply. It is asserted when the supply
rises above its corresponding Voltage Detector 7 threshold, and clears when the falls
below above its corresponding UVD7 threshold and a ‘1’ is written to this bit location.
0 Currently no occurrence
1 VD occurrence detected on the low voltage 1.45 V point supply
16
HVD6_C
HVD6_C flag
This bit is the low-voltage status flag associated with HVD140_C VD, the voltage
level detect for the low voltage Core 1.40 V supply. It is asserted when the supply
rises above its corresponding Voltage Detector 6 threshold, and clears when the
supply falls below its corresponding HVD6 threshold and a ‘1’ is written to this bit
location.
0 Currently no occurrence
1 VD occurrence detected on the low voltage 1.40 V point supply
Reset Event Enable Register (REE_LV1)
This Reset Event Enable Register controls, in LOW VOLTAGE 1 range, whether the voltage
detect signal event causes a reset. If the desired flag bit is enabled, the voltage detect event
causes a reset to be generated when the selected voltage passes the trigger event. These
bits are loaded from the Flash during the boot sequence. If the Flash loaded bits are
programmed to be enabled (set), these bits cannot be disabled (cleared).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
0
0
0
0
0
0
0
0
0
0
0
0
0
0
REE6_C
R
Access: User read/write, Supervisor read/write, Test read/write
REE7_RC
Offset: 0x0024
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
16
W
Reset
Figure 77. Reset Event Enable Register (REE_LV1)
RM0483 Rev 5
367/2075
407
Power management controller digital interface (PMC_Dig)
RM0483
Table 146. REE_LV1 field descriptions
Field
Description
REE7_RC reset enable
This bit defines whether a UVD145_RC VD, the voltage level detect for the low voltage
29
RCOSC 1.45 V supply of the cold point, generates a system reset.
REE7_RC RES_LV1[RES7_RC] determines whether the reset is functional or destructive.
0 Disabled. HVD assertion on the supply of the cold point does not cause system reset.
1 Enabled. HVD assertion on the supply of the cold point causes system reset.
REE6_C reset enable
This bit defines whether a HVD140_C VD, the voltage level detect for the low voltage
Core 1.40 V supply of the cold point, generates a system reset. RES_LV1[RES6_C]
determines whether the reset is functional or destructive.
0 Disabled. HVD assertion on the supply of the cold point does not cause system reset.
1 Enabled. HVD assertion on the supply of the cold point causes system reset.
16
REE6_C
14.5.8
Reset Event Select Register (RES_LV1)
This Reset Event Select Register controls, in LOW VOLTAGE 1 range, whether the voltage
detect signal event causes a destructive or functional reset. If the desired flag bit is enabled,
the voltage detect event causes either a destructive or functional reset to be generated
when the selected voltage passes the trigger event. These bits are loaded from the Flash
during the boot sequence.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RES6_C
R
Access: User read/write, Supervisor read/write, Test read/write
RES7_RC
Offset: 0x0028
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
16
W
Reset
Figure 78. Reset Event Select Register (RES_LV1)
368/2075
RM0483 Rev 5
RM0483
Power management controller digital interface (PMC_Dig)
Table 147. RES_LV1 field descriptions
Field
Description
RES7_RC event select
This bit defines whether a UVD145_RC VD, the voltage level detect for the low voltage
RCOSC 1.45 V supply of the cold point, generates a destructive reset or a functional
29
reset. REE_LV1[REE7_RC] bit determines whether the reset event is enabled.
RES7_RC 0 Destructive Reset Generated. LVD assertion on the supply of the cold point causes a
destructive system reset.
1 Functional Reset Generated. LVD assertion on the supply of the cold point causes a
functional system reset.
RES6_C event select
This bit defines whether a HVD140_C VD, the voltage level detect for the low voltage
Core 1.40 V supply of the cold point, generates a destructive reset or a functional reset.
REE_LV1[REE6_C] bit determines whether the reset event is enabled.
0 Destructive Reset Generated. LVD assertion on the supply of the cold point causes a
destructive system reset.
1 Functional Reset Generated. LVD assertion on the supply of the cold point causes a
functional system reset.
16
RES6_C
14.5.9
Interrupt Enable (IE_LV1)
This configuration register contains a set of LV1 interrupt Enable bits that correspond to
each of the LV1 Event Pending Registers (EPR_LV1). These bits indicate whether an
interrupt is enabled waiting for a potential voltage event. A ‘0’ indicates that no interrupt is
enabled, and a ‘1’ indicates that an interrupt is enabled. These bits are replicated as a readonly monitor in the register (IE_G) at address 0x0088. The IE_LV1 bits can be read or
written at any time.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HVD6IE_C
R
Access: User read/write, Supervisor read/write, Test read/write
UVD7IE_RC
Offset: 0x002C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
16
W
Reset
Figure 79. Interrupt Enable Register (IE_LV1)
RM0483 Rev 5
369/2075
407
Power management controller digital interface (PMC_Dig)
RM0483
Table 148. IE_LV1 field descriptions
14.5.10
Field
Description
29
UVD7IE_RC
UVD7IE_RC Interrupt Enable
This bit determines whether an interrupt is enabled or disabled for the UVD145_RC
VD, the voltage level detect for the low voltage RCOSC 1.45 V supply the voltage
event occurs.
0 Interrupt disabled
1 Interrupt enabled
16
HVD6IE_C
HVD6IE_C Interrupt Enable
This bit determines whether an interrupt is enabled or disabled for the HVD140_C
VD, the voltage level detect for the low voltage Core 1.40 V supply the voltage event
occurs.
0 Interrupt disabled
1 Interrupt enabled
FCCU Event Enable Register (FEE_LV1)
This FCCU Event Enable Register LV1 controls whether the voltage detect signal events
cause an event signal to be sent to the FCCU (Fault Collection and Control Unit). If the
desired flag bit is enabled, the voltage detect event causes an FCCU event to be generated
when the selected voltage passes the trigger event.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FEE6_C
R
Access: User read/write, Supervisor read/write, Test read/write
FEE7_RC
Offset: 0x0030
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
16
W
Reset
Figure 80. FCCU Event Enable Register (FEE_LV1)
370/2075
RM0483 Rev 5
RM0483
Power management controller digital interface (PMC_Dig)
Table 149. FEE_LV1 field descriptions
Field
14.5.11
Description
29
FEE7_RC
FEE7_RC FCCU event enable
This bit defines whether a UVD145_RC VD assertion of RCOSC 1.45 V supply
generates an FCCU event.
0 Disabled. A VD assertion of LV1 on the supply of the RCCU does not cause an
FCCU event.
1 Enabled. A VD assertion of LV1 on the supply of the RCOSC causes an FCCU
event.
16
FEE6_C
FEE6_C FCCU event enable
This bit defines whether a HVD140_C VD assertion of Core 1.40 V supply generates
an FCCU event.
0 Disabled. A VD assertion of LV1 on the supply of the Core does not cause an FCCU
event.
1 Enabled. A VD assertion of LV1 on the supply of the Core causes an FCCU event.
Event Pending Register (EPR_HV0)
This Event Pending Register indicates the present and past state of the voltage detect
signals in HIGH VOLTAGE 0 range. If the voltage detect event has ever passed the trigger
event since the last clearing event, the flag bit is set. In order to clear the flag, a ‘1’ must be
written to the flag bit that needs to be cleared.
25
24
23
22
21
20
0
0
0
0
0
0
R
18
17
16
w1c
w1c
w1c
w1c
0
0
0
0
w1c
w1c
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LVD11_C
w1c
LVD11_FL
w1c
W
Reset
19
LVD11_DACCMP
26
LVD11_OSC
27
UVD15_AS
28
LVD11_IO1
29
LVD11_IO0
30
LVD11_AS
31
LVD11_AD
R
Access: User read/write, Supervisor read/write, Test read/write
UVD15_DACCMP
Offset: 0x0040
w1c
w1c
0
0
0
0
0
0
W
Reset
Figure 81. Event Pending Register (EPR_HV0)
RM0483 Rev 5
371/2075
407
Power management controller digital interface (PMC_Dig)
RM0483
Table 150. EPR_HV0 field descriptions
372/2075
Field
Description
30
LVD11_AD
LVD11_AD flag
This bit is the high-voltage status flag associated with LVD290_AD, the voltage
level detect for the high voltage Sigma Delta ADC 2.90 V supply. It is asserted
when the supply falls below its corresponding Voltage Detector 11 threshold,
and clears when the supply rises above its corresponding LVD11 threshold
and a ‘1’ is written to this bit location.
0 Currently no occurrence
1 VD occurrence detected on the high voltage 2.90 V point supply
29
LVD11_AS
LVD11_AS flag
This bit is the high-voltage status flag associated with LVD290_AS, the voltage
level detect for the high voltage SAR ADC 2.90 V supply. It is asserted when
the supply falls below its corresponding Voltage Detector 11 threshold, and
clears when the supply rises above its corresponding LVD11 threshold and a
‘1’ is written to this bit location.
0 Currently no occurrence
1 VD occurrence detected on the high voltage 2.90 V point supply
28
LVD11_IO0
LVD11_IO0 flag
This bit is the high-voltage status flag associated with LVD290_IO0, the
voltage level detect for the high voltage IO Ring0 2.90 V supply. It is asserted
when the supply falls below its corresponding Voltage Detector 11 threshold,
and clears when the supply rises above its corresponding LVD11 threshold
and a ‘1’ is written to this bit location.
0 Currently no occurrence
1 VD occurrence detected on the high voltage 2.90 V point supply
27
LVD11_IO1
LVD11_IO1 flag
This bit is the high-voltage status flag associated with LVD290_IO1, the
voltage level detect for the high voltage IO Ring1 2.90 V supply. It is asserted
when the supply falls below its corresponding Voltage Detector 11 threshold,
and clears when the supply rises above its corresponding LVD11 threshold
and a ‘1’ is written to this bit location.
0 Currently no occurrence
1 VD occurrence detected on the high voltage 2.90 V point supply
25
LVD11_FL
LVD11_FL flag
This bit is the high-voltage status flag associated with LVD290_FL VD, the
voltage level detect for the high voltage assertion on the Flash 2.90 V supply. It
is asserted when the supply falls below its corresponding Voltage Detector 11
threshold, and clears when the supply rises above its corresponding LVD11
threshold and a ‘1’ is written to this bit location.
0 Currently no occurrence
1 VD occurrence detected on the high voltage 2.90 V point supply
24
LVD11_C
LVD11_C flag
This bit is the high-voltage status flag associated with LVD290_C VD, the
voltage level detect for the high voltage Core 2.90 V supply. It is asserted
when the supply falls below its corresponding Voltage Detector 11 threshold,
and clears when the supply rises above its corresponding LVD11 threshold
and a ‘1’ is written to this bit location.
0 Currently no occurrence
1 VD occurrence detected on the high voltage 2.90 V point supply
RM0483 Rev 5
RM0483
Power management controller digital interface (PMC_Dig)
Table 150. EPR_HV0 field descriptions (continued)
14.5.12
Field
Description
19
UVD15_DACCMP
UVD15_DACCMP flag
This bit is the high-voltage status flag associated with UVD380_DACCMP VD,
the voltage level detect for the high voltage DAC/CMP 3.80 V supply. It is
asserted when the supply rises above its corresponding Voltage Detector 15
threshold, and clears when the supply falls below its corresponding UVD15
threshold and a ‘1’ is written to this bit location.
0 Currently no occurrence
1 VD occurrence detected on the high voltage 3.80 V point supply
18
UVD15_AS
UVD15_AS flag
This bit is the high-voltage status flag associated with UVD380_AS VD, the
voltage level detect for the high voltage SAR ADC 3.80 V supply. It is asserted
when the supply rises above its corresponding Voltage Detector 15 threshold,
and clears when the supply falls below its corresponding UVD15 threshold and
a ‘1’ is written to this bit location.
0 Currently no occurrence
1 VD occurrence detected on the high voltage 3.80 V point supply
17
LVD11_OSC
LVD11_OSC flag
This bit is the high-voltage status flag associated with LVD290_OSC VD, the
voltage level detect for the high voltage OSC 2.90 V supply. It is asserted when
the supply falls below its corresponding Voltage Detector 11 threshold, and
clears when the supply rises above its corresponding LVD11 threshold and a
‘1’ is written to this bit location.
0 Currently no occurrence
1 VD occurrence detected on the high voltage 2.90 V point supply
17
LVD11_DACCMP
LVD11_DACCMP flag
This bit is the high-voltage status flag associated with LVD290_DACCMP VD,
the
voltage level detect for the high voltage DAC/CMP 2.90 V supply. It is asserted
when the supply falls below its corresponding Voltage Detector 11 threshold,
and clears when the supply rises above its corresponding LVD11 threshold
and a ‘1’ is written to this bit location.
0 Currently no occurrence
1 VD occurrence detected on the high voltage 2.90 V point supply
Reset Event Enable Register (REE_HV0)
This Reset Event Enable Register controls whether the voltage detect signal event causes a
reset. If the desired flag bit is enabled, the voltage detect event causes a reset to be
generated when the selected voltage passes the trigger event. These bits are loaded from
the Flash during the boot sequence. If the Flash loaded bits are programmed to be enabled
(set), these bits cannot be disabled (cleared).
RM0483 Rev 5
373/2075
407
Power management controller digital interface (PMC_Dig)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
REE11_AS
REE11_IO0
REE11_IO1
0
REE11_FL
REE11_C
0
0
0
0
REE15_DACCMP
REE15_AS
REE11_OSC
REE11_DACCMP
R
Access: User read/write, Supervisor read/write, Test read/write
REE11_AD
Offset: 0x0044
RM0483
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Figure 82. Reset Event Enable Register (REE_HV0)
Table 151. REE_HV0 field descriptions
374/2075
Field
Description
30
REE11_AD
LVD11_AD reset enable
This bit defines whether LVD290_AD VD, the voltage level detect for the high
voltage assertion on the Sigma Delta ADC 2.90 V supply generates a system
reset. The RES11_AD bit determines whether a system reset is enabled or
not.
0 Disabled. VD assertion on the supply of the cold point does not cause
system reset.
1 Enabled. VD assertion on the supply of the cold point causes system reset.
29
REE11_AS
LVD11_AS reset enable
This bit defines whether LVD290_AS VD, the voltage level detect for the high
voltage assertion on the SAR ADC 2.90 V supply generates a system reset.
The RES11_AS bit determines whether a system reset is enabled or not.
0 Disabled. VD assertion on the supply of the cold point does not cause
system reset.
1 Enabled. VD assertion on the supply of the cold point causes system reset.
28
REE11_IO0
LVD11_IO0 reset enable
This bit defines whether LVD290_IO0 VD, the voltage level detect for the high
voltage assertion on the IO Ring0 2.90 V supply generates a system reset.
The RES11_IO0 bit determines whether a system reset is enabled or not.
0 Disabled. VD assertion on the supply of the cold point does not cause
system reset.
1 Enabled. VD assertion on the supply of the cold point causes system reset.
27
REE11_IO1
LVD11_IO1 reset enable
This bit defines whether LVD290_IO1 VD, the voltage level detect for the high
voltage assertion on the IO Ring1 2.90 V supply generates a system reset.
The RES11_IO1 bit determines whether a system reset is enabled or not.
0 Disabled. VD assertion on the supply of the cold point does not cause
system reset.
1 Enabled. VD assertion on the supply of the cold point causes system reset.
RM0483 Rev 5
RM0483
Power management controller digital interface (PMC_Dig)
Table 151. REE_HV0 field descriptions (continued)
Field
Description
25
REE11_FL
LVD11_FL reset enable
This bit defines whether LVD290_FL VD, the voltage level detect for the high
voltage assertion on the Flash 2.90 V supply of the cold point generates a
system reset. The RES11_FL bit determines whether a system reset is
enabled or not.
0 Disabled. LVD assertion on the supply of the cold point does not cause
system reset.
1 Enabled. LVD assertion on the supply of the cold point causes system reset.
24
REE11_C
LVD11_C reset enable
This bit defines whether LVD290_C VD, the voltage level detect for the high
voltage Core 2.90 V supply, of the cold point generates a system reset. The
RES11_C bit determines whether a system reset is enabled or not.
0 Disabled. LVD assertion on the supply of the cold point does not cause
system reset.
1 Enabled. LVD assertion on the supply of the cold point causes system reset.
19
REE15_DACCMP
UVD15_DACCMP reset enable
This bit defines whether UVD380_DACCMP VD, the voltage level detect for
the high voltage DAC/CMP 3.80 V supply, of the cold point generates a
system reset. The RES15_DACCMP bit determines whether a system reset is
enabled or not.
0 Disabled. UVD assertion on the supply of the cold point does not cause
system reset.
1 Enabled. UVD assertion on the supply of the cold point causes system reset.
18
REE15_AS
UVD15_AS reset enable
This bit defines whether UVD380_AS VD, the voltage level detect for the high
voltage SAR ADC 3.80 V supply, of the cold point generates a system reset.
The RES15_AS bit determines whether a system reset is enabled or not.
0 Disabled. UVD assertion on the supply of the cold point does not cause
system reset.
1 Enabled. UVD assertion on the supply of the cold point causes system reset.
17
REE11_OSC
LVD11_OSC reset enable
This bit defines whether LVD290_OSC VD, the voltage level detect for the
high voltage OSC 2.90 V supply, of the cold point generates a system reset.
The RES11_OSC bit determines whether a system reset is enabled or not.
0 Disabled. LVD assertion on the supply of the cold point does not cause
system reset.
1 Enabled. LVD assertion on the supply of the cold point causes system reset.
17
REE11_DACCMP
LVD11_DACCMP reset enable
This bit defines whether LVD290_DACCMP VD, the voltage level detect for
the high voltage DAC/CMP 2.90 V supply, of the cold point generates a
system reset. The RES11_DACCMP bit determines whether a system reset is
enabled or not.
0 Disabled. LVD assertion on the supply of the cold point does not cause
system reset.
1 Enabled. LVD assertion on the supply of the cold point causes system reset.
RM0483 Rev 5
375/2075
407
Power management controller digital interface (PMC_Dig)
14.5.13
RM0483
Reset Event Select Register (RES_HV0)
This Reset Event Select Register controls, in HIGH VOLTAGE 0 range, whether the voltage
detect signal event causes a destructive or functional reset. If the desired flag bit is enabled,
the voltage detect event causes either a destructive or functional reset to be generated
when the selected voltage passes the trigger event. These bits are loaded from the Flash
during the boot sequence.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
RES11_AS
RES11_IO0
RES11_IO1
0
RES11_FL
RES11_C
0
0
0
0
RES15_DACCMP
RES15_AS
RES11_OSC
RES11_DACCMP
R
Access: User read/write, Supervisor read/write, Test read/write
RES11_AD
Offset: 0x0048
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Figure 83. Reset Event Select Register (RES_HV0)
Table 152. RES_HV0 field descriptions
376/2075
Field
Description
30
RES11_AD
RES11_AD reset event select
This bit defines whether an LVD assertion on the Sigma Delta ADC 2.90 V
supply of the cold point generates a destructive reset or a functional reset. The
REE11_ad bit determines whether the reset event is enabled.
0 Destructive Reset Generated. LVD assertion on the supply of the cold point
causes a destructive system reset.
1 Functional Reset Generated. LVD assertion on the supply of the cold point
causes a functional system reset.
29
RES11_AS
RES11_AS reset event select
This bit defines whether an LVD assertion on the SAR ADC 2.90 V supply of
the cold point generates a destructive reset or a functional reset. The
REE11_AS bit determines whether the reset event is enabled.
0 Destructive Reset Generated. LVD assertion on the supply of the cold point
causes a destructive system reset.
1 Functional Reset Generated. LVD assertion on the supply of the cold point
causes a functional system reset.
RM0483 Rev 5
RM0483
Power management controller digital interface (PMC_Dig)
Table 152. RES_HV0 field descriptions (continued)
Field
Description
28
RES11_IO0
RES11_IO0 reset event select
This bit defines whether an LVD assertion on the IO Ring0 2.90 V supply of
the cold point generates a destructive reset or a functional reset. The
REE11_IO0 bit determines whether the reset event is enabled.
0 Destructive Reset Generated. LVD assertion on the supply of the cold point
causes a destructive system reset.
1 Functional Reset Generated. LVD assertion on the supply of the cold point
causes a functional system reset.
27
RES11_IO1
RES11_IO1 reset event select
This bit defines whether an LVD assertion on the IO Ring1 2.90 V supply of
the cold point generates a destructive reset or a functional reset. The
REE11_IO1 bit determines whether the reset event is enabled.
0 Destructive Reset Generated. LVD assertion on the supply of the cold point
causes a destructive system reset.
1 Functional Reset Generated. LVD assertion on the supply of the cold point
causes a functional system reset.
25
RES11_FL
RES11_FL reset event select
This bit defines whether an LVD assertion on the Flash 2.90 V supply of the
cold point generates a destructive reset or a functional reset. The REE11_FL
bit determines whether the reset event is enabled.
0 Destructive Reset Generated. LVD assertion on the supply of the cold point
causes a destructive system reset.
1 Functional Reset Generated. LVD assertion on the supply of the cold point
causes a functional system reset.
24
RES11_C
RES11_C reset event select
This bit defines whether an LVD assertion on the Core 2.90 V supply of the
cold point generates a destructive reset or a functional reset. The REE11_C
bit determines whether the reset event is enabled.
0 Destructive Reset Generated. LVD assertion on the supply of the cold point
causes a destructive system reset.
1 Functional Reset Generated. LVD assertion on the supply of the cold point
causes a functional system reset.
19
RES15_DACCMP
RES15_DACCMP reset event select
This bit defines whether an UVD assertion on the DAC/CMP 3.80 V supply of
the cold point generates a destructive reset or a functional reset. The
REE15_DACCMP bit determines whether the reset event is enabled.
0 Destructive Reset Generated. UVD assertion on the supply of the cold point
causes a destructive system reset.
1 Functional Reset Generated. UVD assertion on the supply of the cold point
causes a functional system reset.
18
RES15_AS
RES15_AS reset event select
This bit defines whether an UVD assertion on the SAR ADC 3.80 V supply of
the cold point generates a destructive reset or a functional reset. The
REE15_AS bit determines whether the reset event is enabled.
0 Destructive Reset Generated. UVD assertion on the supply of the cold point
causes a destructive system reset.
1 Functional Reset Generated. UVD assertion on the supply of the cold point
causes a functional system reset.
RM0483 Rev 5
377/2075
407
Power management controller digital interface (PMC_Dig)
RM0483
Table 152. RES_HV0 field descriptions (continued)
14.5.14
Field
Description
17
RES11_OSC
RES11_OSC reset event select
This bit defines whether an LVD assertion on the OSC 2.90 V supply of the
cold point generates a destructive reset or a functional reset. The
REE11_OSC bit determines whether the reset event is enabled.
0 Destructive Reset Generated. LVD assertion on the supply of the cold point
causes a destructive system reset.
1 Functional Reset Generated. LVD assertion on the supply of the cold point
causes a functional system reset.
17
RES11_DACCMP
RES11_DACCMP reset event select
This bit defines whether an LVD assertion on the DAC/CMP 2.90 V supply of
the cold point generates a destructive reset or a functional reset. The
REE11_DACCMP bit determines whether the reset event is enabled.
0 Destructive Reset Generated. LVD assertion on the supply of the cold point
causes a destructive system reset.
1 Functional Reset Generated. LVD assertion on the supply of the cold point
causes a functional system reset.
Interrupt Enable (IE_HV0)
This configuration register contains a set of HV0 interrupt Enable bits that correspond to
each of the HV0 Event Pending Registers (EPR_HV0). These bits indicate whether an
interrupt is enabled, waiting for a potential voltage event. A ‘0’ indicates that no interrupt is
enabled, and a ‘1’ indicates that an interrupt is enabled. These bits are replicated as a readonly monitor in the register (IE_G) at address 0x0088. The IE_HV0 bits can be read or
written at any time.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
LVD11IE_AS
LVD11IE_IO0
LVD11IE_IO1
0
LVD11IE_FL
LVD11IE_C
0
0
0
0
UVD15IE_DACCMP
UVD15IE_AS
LVD11IE_OSC
LVD11IE_DACCMP
R
Access: User read/write, Supervisor read/write, Test read/write
LVD11IE_AD
Offset: 0x004C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Figure 84. Interrupt Enable Register (IE_HV0)
378/2075
RM0483 Rev 5
RM0483
Power management controller digital interface (PMC_Dig)
Table 153. IE_HV0 field descriptions
Field
Description
30
LVD11IE_AD
LVD11IE_AD Interrupt Enable
This bit determines whether an interrupt is enabled or disabled for the
LVD290_AD VD, the voltage level detect for the high voltage assertion on
the Sigma Delta ADC 2.90 V supply event occurs.
0 Interrupt disabled
1 Interrupt enabled
29
LVD11IE_AS
LVD11IE_AS Interrupt Enable
This bit determines whether an interrupt is enabled or disabled for the
LVD290_AS VD, the voltage level detect for the high voltage assertion on
the SAR ADC 2.90 V supply event occurs.
0 Interrupt disabled
1 Interrupt enabled
28
LVD11IE_IO0
LVD11IE_IO0 Interrupt Enable
This bit determines whether an interrupt is enabled or disabled for the
LVD290_IO0 VD, the voltage level detect for the high voltage assertion on
the IO Ring0 2.90 V supply event occurs.
0 Interrupt disabled
1 Interrupt enabled
27
LVD11IE_IO1
LVD11IE_IO1 Interrupt Enable
This bit determines whether an interrupt is enabled or disabled for the
LVD290_IO1 VD, the voltage level detect for the high voltage assertion on
the IO Ring1 2.90 V supply event occurs.
0 Interrupt disabled
1 Interrupt enabled
25
LVD11IE_FL
LVD11IE_FL Interrupt Enable
This bit determines whether an interrupt is enabled or disabled for the
LVD290_FL VD, the voltage level detect for the high voltage assertion on the
Flash 2.90 V supply event occurs.
0 Interrupt disabled
1 Interrupt enabled
24
LVD11IE_C
LVD11IE_C Interrupt Enable
This bit determines whether an interrupt is enabled or disabled for the
LVD290_C VD, the voltage level detect for the high voltage Core 2.90 V
supply event occurs.
0 Interrupt disabled
1 Interrupt enabled
19
UVD15IE_DACCMP
UVD15IE_DACCMP Interrupt Enable
This bit determines whether an interrupt is enabled or disabled for the
UVD380_DACCMP VD, the voltage level detect for the high voltage
DAC/CMP 3.80 V supply event occurs.
0 Interrupt disabled
1 Interrupt enabled
RM0483 Rev 5
379/2075
407
Power management controller digital interface (PMC_Dig)
RM0483
Table 153. IE_HV0 field descriptions (continued)
Field
Description
18
UVD15IE_AS
UVD15IE_AS Interrupt Enable
This bit determines whether an interrupt is enabled or disabled for the
UVD380_AS VD, the voltage level detect for the high voltage SAR ADC
3.80 V supply event occurs.
0 Interrupt disabled
1 Interrupt enabled
17
LVD11IE_OSC
LVD11IE_OSC Interrupt Enable
This bit determines whether an interrupt is enabled or disabled for the
LVD290_OSC VD, the voltage level detect for the high voltage OSC 2.90 V
supply event occurs.
0 Interrupt disabled
1 Interrupt enabled
17
LVD11IE_DACCMP
14.5.15
LVD11IE_DACCMP Interrupt Enable
This bit determines whether an interrupt is enabled or disabled for the
LVD290_DACCMP VD, the voltage level detect for the high voltage
DAC/CMP 2.90 V supply event occurs.
0 Interrupt disabled
1 Interrupt enabled
FCCU Event Enable Register (FEE_HV0)
This FCCU Event Enable Register HV0 controls whether the voltage detect signal events
cause an event signal to be sent to the FCCU (Fault Collection and Control Unit). If the
desired flag bit is enabled, the voltage detect event causes an FCCU event to be generated
when the selected voltage passes the trigger event.
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
FEE11_DACCMP
27
FEE11_OSC
28
0
0
0
0
0
0
0
0
FEE11_IO1
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FEE11_C
FEE11_IO0
0
FEE11_FL
FEE11_AS
0
FEE11_AD
R
29
0
W
Reset
30
0
FEE15_AS
31
R
Access: User read/write, Supervisor read/write, Test read/write
FEE15_DACCMP
Offset: 0x0050
0
0
W
Reset
Figure 85. FCCU Event Enable Register (FEE_HV0)
380/2075
RM0483 Rev 5
RM0483
Power management controller digital interface (PMC_Dig)
Table 154. FEE_HV0 field descriptions
Field
Description
30
FEE11_AD
FEE11_AD FCCU event enable
This bit defines whether a LVD290_AD VD, the voltage level detect for the
high voltage assertion on the Sigma Delta ADC 2.90 V supply assertion
generates an FCCU event.
0 Disabled. A VD assertion of HV0 on the supply of the ADC does not cause
an FCCU event.
1 Enabled. A VD assertion of HV0 on the supply of the ADC causes an FCCU
event.
29
FEE11_AS
FEE11_AS FCCU event enable
This bit defines whether a LVD290_AS VD, the voltage level detect for the
high voltage assertion on the SAR ADC 2.90 V supply assertion generates an
FCCU event.
0 Disabled. A VD assertion of HV0 on the supply of the ADC does not cause
an FCCU event.
1 Enabled. A VD assertion of HV0 on the supply of the ADC causes an FCCU
event.
28
FEE11_IO0
FEE11_IO0 FCCU event enable
This bit defines whether a LVD290_IO0 VD, the voltage level detect for the
high voltage assertion on the IO Ring0 2.90 V supply assertion generates an
FCCU event.
0 Disabled. A VD assertion of HV0 on the supply of the IO Ring0 does not
cause an FCCU event.
1 Enabled. A VD assertion of HV0 on the supply of the IO Ring0 causes an
FCCU event.
27
FEE11_IO1
FEE11_IO1 FCCU event enable
This bit defines whether a LVD290_IO1 VD, the voltage level detect for the
high voltage assertion on the IO Ring1 2.90 V supply assertion generates an
FCCU event.
0 Disabled. A VD assertion of HV0 on the supply of the IO Ring1 does not
cause an FCCU event.
1 Enabled. A VD assertion of HV0 on the supply of the IO Ring1 causes an
FCCU event.
25
FEE11_FL
FEE11_FL FCCU event enable
This bit defines whether a LVD290_FL VD, the voltage level detect for the
high voltage assertion on the Flash 2.90 V supply assertion generates an
FCCU event.
0 Disabled. A VD assertion of HV0 on the supply of the Flash does not cause
an FCCU event.
1 Enabled. A VD assertion of HV0 on the supply of the Flash causes an FCCU
event.
24
FEE11_C
FEE11_C FCCU event enable
This bit defines whether a LVD290_C VD, the voltage level detect for the high
voltage assertion on the Core 2.90 V supply assertion generates an FCCU
event.
0 Disabled. A VD assertion of HV0 on the supply of the Core does not cause
an FCCU event.
1 Enabled. A VD assertion of HV0 on the supply of the Core causes an FCCU
event.
RM0483 Rev 5
381/2075
407
Power management controller digital interface (PMC_Dig)
RM0483
Table 154. FEE_HV0 field descriptions (continued)
14.5.16
Field
Description
19
FEE15_DACCMP
FEE15_DACCMP FCCU event enable
This bit defines whether a UVD380_DACCMP VD, the voltage level detect for
the high voltage assertion on the DAC/CMP 3.80 V supply assertion
generates an FCCU event.
0 Disabled. A VD assertion of HV0 on the supply of the DAC/CMP does not
cause an FCCU event.
1 Enabled. A VD assertion of HV0 on the supply of the DAC/CMP causes an
FCCU event.
18
FEE15_AS
FEE15_AS FCCU event enable
This bit defines whether a UVD380_AS VD, the voltage level detect for the
high voltage assertion on the SAR ADC 3.80 V supply assertion generates an
FCCU event.
0 Disabled. A VD assertion of HV0 on the supply of the SAR ADC does not
cause an FCCU event.
1 Enabled. A VD assertion of HV0 on the supply of the SAR ADC causes an
FCCU event.
17
FEE11_OSC
FEE11_OSC FCCU event enable
This bit defines whether a LVD290_OSC VD, the voltage level detect for the
high voltage assertion on the OSC 2.90 V supply assertion generates an
FCCU event.
0 Disabled. A VD assertion of HV0 on the supply of the OSC does not cause
an FCCU event.
1 Enabled. A VD assertion of HV0 on the supply of the OSC causes an FCCU
event.
17
FEE11_DACCMP
FEE11_DACCMP FCCU event enable
This bit defines whether a LVD290_DACCMP VD, the voltage level detect for
the high voltage assertion on the DAC/CMP 2.90 V supply assertion
generates an FCCU event.
0 Disabled. A VD assertion of HV0 on the supply of the DAC/CMP does not
cause an FCCU event.
1 Enabled. A VD assertion of HV0 on the supply of the DAC/CMP causes an
FCCU event.
Supply Gauge Status Register (GR_S)
This status register contains the gauge of the indicated supply. This indicates the present
state of the voltage detect events for each of the supplies. Each of the voltage detect signals
for a given voltage, these signals are combined to form a single bit, refer to Table 155.
382/2075
RM0483 Rev 5
RM0483
Power management controller digital interface (PMC_Dig)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
TEMP_1
TEMP_0
VD3_PLL1
VD3_PLL0
VD3_DD
0
0
0
0
0
VD15_DACCMP
VD15_AS
VD11_OSC
VD11_DACCMP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
VD11_AD
VD11_AS
VD11_IO0
VD11_IO1
VD11_FL
VD11_C
VD7_RC
VD6_C
VD3_RC
0
VD3_FL
VD3_C
R
Access: User read-only
TEMP_2
Offset: 0x0080
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Figure 86. Supply Gauge Status Register (GR_S)
Table 155. GR_S field descriptions
Field
Description
30
TEMP_2
TEMP_2 flag
This bit is the temperature status flag associated with the temperature for the
temperature sensor point (150 °C). It is asserted when the temperature
exceeds its corresponding threshold, and clears when the temperature falls
below its corresponding threshold.
0 Currently no occurrence
1 Temperature occurrence detected
29
TEMP_1
TEMP_1 flag
This bit is the temperature status flag associated with the temperature for the
temperature sensor point (135 °C). It is asserted when the temperature
exceeds its corresponding threshold, and clears when the temperature falls
below its corresponding threshold.
0 Currently no occurrence
1 Temperature occurrence detected
28
TEMP_0
TEMP_0 flag
This bit is the temperature status flag associated with the temperature for the
temperature sensor point (-40 °C). It is asserted when the temperature falls
below its corresponding threshold, and clears when the temperature is above
its corresponding threshold.
0 Currently no occurrence
1 Temperature occurrence detected
RM0483 Rev 5
383/2075
407
Power management controller digital interface (PMC_Dig)
RM0483
Table 155. GR_S field descriptions (continued)
384/2075
Field
Description
27
VD3_PLL1
VD3_PLL1 low-voltage detect flag
This read-only bit is the low-voltage status flag associated with the voltage level
detect LVD119_PLL1 for the low voltage 1.19 V PLL1 supplies. It is asserted
when any of the PLL1 supplies falls below the corresponding LVD threshold,
and clears when all the PLL1 supplies rise above the corresponding LVD
threshold.
0 Currently no occurrence
1 LVD occurrence detected on the low voltage 1.19 V supplies
26
VD3_PLL0
VD3_PLL0 low-voltage detect flag
This read-only bit is the low-voltage status flag associated with the voltage level
detect LVD119_PLL0 for the low voltage 1.19 V PLL0 supplies. It is asserted
when any of the PLL0 supplies falls below the corresponding LVD threshold,
and clears when all the PLL0 supplies rise above the corresponding LVD
threshold.
0 Currently no occurrence
1 LVD occurrence detected on the low voltage 1.19 V supplies
25
VD3_DD
VD3_DD low-voltage detect flag
This read-only bit is the low-voltage status flag associated with the voltage level
detect LVD119_DD for the low voltage 1.19 V DLL supplies. It is asserted when
any of the DLL supplies falls below the corresponding LVD threshold, and
clears when all the DLL supplies rise above the corresponding LVD threshold.
0 Currently no occurrence
1 LVD occurrence detected on the low voltage 1.19 V supplies
19
VD15_DACCMP
VD15_DACCMP high-voltage detect flag
This read-only bit is the high-voltage status flag associated with the voltage
level detect UVD380_DACCMP for the high voltage 3.80 V DAC/CMP supplies.
It is asserted when any of the DAC/CMP supplies rises above the
corresponding UVD threshold, and clears when all the DAC/CMP supplies fall
below the corresponding UVD threshold. All of the 3.80 V UVDs are combined
to form this bit.
0 Currently no occurrence
1 UVD occurrence detected on the high voltage 3.80 V supplies
18
VD15_AS
VD15_AS high-voltage detect flag
This read-only bit is the high-voltage status flag associated with the voltage
level detect UVD380_AS for the high voltage 3.80 V SAR ADC supplies. It is
asserted when any of the SAR ADC supplies rises above the corresponding
UVD threshold, and clears when all the SAR ADC supplies fall below the
corresponding UVD threshold. All of the 3.80 V UVDs are combined to form this
bit.
0 Currently no occurrence
1 UVD occurrence detected on the high voltage 3.80 V supplies
RM0483 Rev 5
RM0483
Power management controller digital interface (PMC_Dig)
Table 155. GR_S field descriptions (continued)
Field
Description
17
VD11_OSC
VD11_OSC high-voltage detect flag
This read-only bit is the high-voltage status flag associated with the voltage
level detect LVD290_OSC for the high voltage 2.90 V OSC supplies. It is
asserted when any of the OSC supplies falls below the corresponding LVD
threshold, and clears when all the OSC supplies rise above the corresponding
LVD threshold. All of the 2.90 V LVDs are combined to form this bit.
0 Currently no occurrence
1 LVD occurrence detected on the high voltage 2.90 V supplies
16
VD11_DACCMP
VD11_DACCMP high-voltage detect flag
This read-only bit is the high-voltage status flag associated with the voltage
level detect LVD290_DACCMP for the high voltage 2.90 V DAC/CMP supplies.
It is asserted when any of the DAC/CMP supplies falls below the corresponding
LVD threshold, and clears when all the DAC/CMP supplies rise above the
corresponding LVD threshold. All of the 2.90 V LVDs are combined to form this
bit.
0 Currently no occurrence
1 LVD occurrence detected on the high voltage 2.90 V supplies
11
VD11_AD
VD11_AD high-voltage detect flag
This read-only bit is the high-voltage status flag associated with the voltage
level detect LVD290_AD for the high voltage 2.90 V Sigma Delta ADC supplies.
It is asserted when any of the ADC supplies falls below the corresponding LVD
threshold, and clears when all the ADC supplies rise above the corresponding
LVD threshold. All of the 2.90 V LVDs are combined to form this bit.
0 Currently no occurrence
1 LVD occurrence detected on the high voltage 2.90 V supplies
10
VD11_AS
VD11_AS high-voltage detect flag
This read-only bit is the high-voltage status flag associated with the voltage
level detect LVD290_AD for the high voltage 2.90 V SAR ADC supplies. It is
asserted when any of the ADC supplies falls below the corresponding LVD
threshold, and clears when all the ADC supplies rise above the corresponding
LVD threshold. All of the 2.90 V LVDs are combined to form this bit.
0 Currently no occurrence
1 LVD occurrence detected on the high voltage 2.90 V supplies
9
VD11_IO0
VD11_IO0 high-voltage detect flag
This read-only bit is the high-voltage status flag associated with the voltage
level detect LVD290_IO0 for the high voltage 2.90 V IO Ring0 supplies. It is
asserted when any of the IO supplies falls below the corresponding LVD
threshold, and clears when all the IO supplies rise above the corresponding
LVD threshold. All of the 2.90 V LVDs are combined to form this bit.
0 Currently no occurrence
1 LVD occurrence detected on the high voltage 2.90 V supplies
RM0483 Rev 5
385/2075
407
Power management controller digital interface (PMC_Dig)
RM0483
Table 155. GR_S field descriptions (continued)
Field
386/2075
Description
8
VD11_IO1
VD11_IO1 high-voltage detect flag
This read-only bit is the high-voltage status flag associated with the voltage
level detect LVD290_IO1 for the high voltage 2.90 V IO Ring1 supplies. It is
asserted when any of the IO supplies falls below the corresponding LVD
threshold, and clears when all the IO supplies rise above the corresponding
LVD threshold. All of the 2.90 V LVDs are combined to form this bit.
0 Currently no occurrence
1 LVD occurrence detected on the high voltage 2.90 V supplies
7
VD11_FL
VD11_FL high-voltage detect flag
This read-only bit is the high-voltage status flag associated with the voltage
level detect LVD290_FL for the high voltage 2.90 V Flash supplies. It is
asserted when any of the Flash supplies falls below the corresponding LVD
threshold, and clears when all the Flash supplies rise above the corresponding
LVD threshold. All of the 2.90 V LVDs are combined to form this bit.
0 Currently no occurrence
1 LVD occurrence detected on the high voltage 2.90 V supplies
6
VD11_C
VD11_C high-voltage detect flag
This read-only bit is the high-voltage status flag associated with the voltage
level detect LVD290_C for the high voltage 2.90 V Core supplies. It is asserted
when any of the Core supplies falls below the corresponding LVD threshold,
and clears when all the Core supplies rise above the corresponding LVD
threshold. All of the 2.90 V LVDs are combined to form this bit.
0 Currently no occurrence
1 LVD occurrence detected on the high voltage 2.90 V supplies
5
VD7_RC
VD7_RC low-voltage detect flag
This read-only bit is the low-voltage status flag associated with the voltage level
detect UVD145_RC for the low voltage 1.45 V RCOSC supplies. It is asserted
when any of the RCOSC supplies rises above the corresponding UVD
threshold, and clears when all the RCOSC supplies fall below the
corresponding UVD threshold. All the 1.45 V UVDs are combined to form this
bit.
0 Currently no occurrence
1 UVD occurrence detected on the low voltage 1.45 V supply
4
VD6_C
VD6_C low-voltage detect flag
This read-only bit is the low-voltage status flag associated with the voltage level
detect HVD140_C for the low voltage 1.40 V Core supplies. It is asserted when
any of the Core supplies rises above the corresponding HVD threshold, and
clears when all the Core supplies fall below the corresponding HVD threshold.
All the 1.40 V HVDs are combined to form this bit.
0 Currently no occurrence
1 HVD occurrence detected on the low voltage 1.40 V supply
RM0483 Rev 5
RM0483
Power management controller digital interface (PMC_Dig)
Table 155. GR_S field descriptions (continued)
14.5.17
Field
Description
3
VD3_RC
VD3_RC low-voltage detect flag
This read-only bit is the low-voltage status flag associated with the voltage level
detect LVD119_RC for the low voltage 1.19 V RCOSC supplies. It is asserted
when any of the RCOSC supplies falls below the corresponding LVD threshold,
and clears when all the RCOSC supplies rise above the corresponding LVD
threshold.
0 Currently no occurrence
1 LVD occurrence detected on the low voltage 1.19 V supplies
1
VD3_FL
VD3_FL low-voltage detect flag
This read-only bit is the low-voltage status flag associated with the voltage level
detect LVD119_FL for the low voltage 1.19 V Flash supplies. It is asserted when
any of the Flash supplies falls below the corresponding LVD threshold, and
clears when all the Flash supplies rise above the corresponding LVD threshold.
0 Currently no occurrence
1 LVD occurrence detected on the low voltage 1.19 V supplies
0
VD3_C
VD3_C low-voltage detect flag
This read-only bit is the low-voltage status flag associated with the voltage level
detect LVD119_C for the low voltage 1.19 V Core supplies. It is asserted when
any of the Core supplies falls below the corresponding LVD threshold, and
clears when all the Core supplies rise above the corresponding LVD threshold.
0 Currently no occurrence
1 LVD occurrence detected on the low voltage 1.19 V supplies
Pending Gauge Status Register (GR_P)
This configuration register contains a mirror of the contents of the Event Pending Registers,
but in a format that includes one bit for each voltage detect signal. These bits indicate the
state of the voltage detect events including whether a voltage level event has occurred at
any time in the past but has not been cleared (via the EPR register). These bits are read
only, and they are cleared by writing a one to the corresponding EPR register.
The Pending registers are only set on an active edge of an event, so a transition must be
seen before they become set.
The raw analog block voltage detect signals are also synchronized to the bus clock before
being used for the pending registers.
RM0483 Rev 5
387/2075
407
Power management controller digital interface (PMC_Dig)
RM0483
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
VD3_PLL1
VD3_PLL0
VD3_DD
0
0
0
0
0
VD15_DACCMP
VD15_AS
VD11_OSC
VD11_DACCMP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
VD11_AS
VD11_IO0
VD11_IO1
VD11_FL
VD11_C
VD7_RC
VD6_C
VD3_RC
0
VD3_FL
VD3_C
0
IRQ_ST
R
Access: User read-only
VD11_AD
Offset: 0x0084
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Figure 87. Pending Gauge Status Register (GR_P)
Table 156. GR_P field descriptions
Field
Description
27
VD3_PLL1
VD3_PLL1 Pending Monitor. Read-only register.
26
VD3_PLL0
VD3_PLL0 Pending Monitor. Read-only register.
25
VD3_DD
VD3_DD Pending Monitor. Read-only register.
19
VD15_DACCMP Pending Monitor. Read-only register.
VD15_DACCMP
18
VD15_AS
VD15_AS Pending Monitor. Read-only register.
17
VD11_OSC
VD11_OSC Pending Monitor. Read-only register.
16
VD11_DACCMP Pending Monitor. Read-only register.
VD11_DACCMP
388/2075
14
VD11_AD
VD11_AD Pending Monitor. Read-only register.
13
VD11_AS
VD11_AS Pending Monitor. Read-only register.
12
VD11_IO0
VD11_IO0 Pending Monitor. Read-only register.
11
VD11_IO1
VD11_IO1 Pending Monitor. Read-only register.
RM0483 Rev 5
RM0483
Power management controller digital interface (PMC_Dig)
Table 156. GR_P field descriptions (continued)
Field
14.5.18
Description
10
VD11_FL
VD11_FL Pending Monitor. Read-only register.
9
VD11_C
VD11_C Pending Monitor. Read-only register.
8
VD7_RC
VD7_RC Pending Monitor. Read-only register.
7
VD6_C
VD6_C Pending Monitor. Read-only register.
6
VD3_RC
VD3_RC Pending Monitor. Read-only register.
4
VD3_FL
VD3_FL Pending Monitor. Read-only register.
3
VD3_C
VD3_C Pending Monitor. Read-only register.
1
IRQ_ST
IRQ_ST user BIST Pending Monitor. Read-only register.
Global Interrupt Enable Register (IE_G)
This configuration register contains a set of Interrupt Enable bits that correspond to each of
the Event Pending Registers (EPR_XX), but in a format similar to the Pending Gauge Status
register (GR_P). These bits indicate whether an interrupt is enabled. A ‘0’ indicates that no
interrupt is enabled, and a ‘1’ indicates that an interrupt is enabled. These bits are enabled
via a write of ‘1’ to the MSB of this register (IE_EN). After this, these bits can be read or
written at any time.
22
21
20
19
18
17
16
0
0
0
0
0
0
5
4
3
0
0
0
15
14
13
12
11
10
9
8
7
6
R
0
VD3IE_RC
0
VD6IE_C
0
VD7IE_RC
0
VD11IE_C
0
VD11IE_FL
0
VD11IE_IO1
0
VD11IE_IO0
0
VD11IE_AS
Reset
VD11IE_AD
W
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
VD11IE_DACCMP
23
0
VD11IE_OSC
24
0
0
0
0
2
1
0
0
0
0
IRQ_EN
25
VD15IE_AS
26
VD15IE_DACCMP
27
VD3IE_DD
0
VVD3IE_PLL0
28
0
VD3IE_PLL1
29
0
IE_EN
30
VD3IE_C
31
R
Access: User read/write, Supervisor read/write, Test read/write
VD3IE_FL
Offset: 0x0088
0
0
0
0
Figure 88. Global Interrupt Enable Register (IE_G)
RM0483 Rev 5
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Power management controller digital interface (PMC_Dig)
RM0483
Table 157. IE_G field descriptions
Field
Description
31
IE_EN
IE_EN. Interrupt Enable. This bit permits Interrupt Enable bit to be written.
0 No interrupt enables can be written.
1 Any interrupt enable can be written.
27
VD3IE_PLL1
VD3IE_PLL1 enable interrupt monitor. Read-only register.
26
VD3IE_PLL0
VD3IE_PLL0 enable interrupt monitor. Read-only register.
25
VD3IE_DD
VD3IE_DD enable interrupt monitor. Read-only register.
19
VD15IE_DACCMP
18
VD15IE_AS
VD15IE_AS enable interrupt monitor. Read-only register.
17
VD11IE_OSC
VD11IE_OSC enable interrupt monitor. Read-only register.
16
VD11IE_DACCMP
390/2075
VD15IE_DACCMP enable interrupt monitor. Read-only register.
VD11IE_DACCMP enable interrupt monitor. Read-only register.
14
VD11IE_AD
VDIE11_AD enable interrupt monitor. Read-only register.
13
VD11IE_AS
VDIE11_AS enable interrupt monitor. Read-only register.
12
VD11IE_IO0
VDIE11_IO0 enable interrupt monitor. Read-only register.
11
VD11IE_IO1
VDIE11_IO1 enable interrupt monitor. Read-only register.
10
VD11IE_FL
VDIE11_FL enable interrupt monitor. Read-only register.
9
VD11IE_C
VDIE11_C enable interrupt monitor. Read-only register.
8
VD7IE_RC
VD7IE_RC enable interrupt monitor. Read-only register.
7
VD6IE_C
VDIE6_C enable interrupt monitor. Read-only register.
6
VD3IE_RC
VD3IE_RC enable interrupt monitor. Read-only register.
4
VD3IE_FL
VDIE3_FL enable interrupt monitor. Read-only register.
RM0483 Rev 5
RM0483
Power management controller digital interface (PMC_Dig)
Table 157. IE_G field descriptions (continued)
Field
14.5.19
Description
3
VD3IE_C
VDIE3_C enable interrupt monitor. Read-only register.
1
IRQ_EN
IRQ_EN user BIST enable interrupt monitor. Read-only register.
HPREG SMPS SELECT STATUS (HPREG_SMPS_SEL_S)
This register shows the status of SMPS.
R
Access: User read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
SMPS_ENB
Offset: 0x0244
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
W
Reset
R
W
Reset
Figure 89. HPREG SMPS SELECT STATUS register (HPREG_SMPS_SEL_S)
Table 158. HPREG_SMPS_SEL_S field descriptions
Field
0
SMPS_ENB
14.5.20
Description
SMPS enable/disable status
0 SMPS enabled
1 SMPS disabled
Event Pending Register (EPR_TD)
This Event Pending Register indicates the present and past state of the temperature sensor
signals. If the temperature event has ever passed the trigger event since the last clearing
event, the flag bit is set. In order to clear the flag, a ‘1’ must be written to the flag bit that
needs to be cleared.
RM0483 Rev 5
391/2075
407
Power management controller digital interface (PMC_Dig)
Offset: 0x0300
R
RM0483
Access: User read/write, Supervisor read/write, Test read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
TEMP_0
R
TEMP_1
Reset
TEMP_2
W
w1c
w1c
w1c
0
0
0
Figure 90. Event Pending Register (EPR_TD)
Table 160. EPR_TD field descriptions
392/2075
Field
Description
2
TEMP_2
TEMP_2 flag. This bit is the temperature status flag associated with the
temperature for the temperature sensor point (150 °C). It is asserted when the
temperature exceeds its corresponding threshold, and clears when the
temperature falls below its corresponding threshold and a ‘1’ is written to this bit
location. If the IETD_2 bit is also asserted, an interrupt is sent to the CPU. If
REE_TD[TEMP_2] is also asserted, a system reset is generated, which clears
IETD_2 and negate the interrupt request. If REE_TD[TEMP_2] is asserted and
a destructive reset is selected (via RES_TD[TEMP_2] being 0), then a
destructive reset is generated. If RES_TD[TEMP_2] is set, then a functional
reset is generated.
0 Currently no occurrence
1 Temperature occurrence detected
1
TEMP_1
TEMP_1 flag. This bit is the temperature status flag associated with the
temperature for the temperature sensor point (135 °C). It is asserted when the
temperature exceeds its corresponding threshold, and clears when the
temperature falls below its corresponding threshold and a ‘1’ is written to this bit
location. If the IETD_1 bit is also asserted, an interrupt is sent to the CPU. If
REE_TD[TEMP_1] is also asserted, a system reset is generated, which clears
IETD_1 and negate the interrupt request. If REE_TD[TEMP_1] is asserted and
a destructive reset is selected (via RES_TD[TEMP_1] being 0), then a
destructive reset is generated. If RES_TD[TEMP_1] is set, then a functional
reset is generated.
0 Currently no occurrence
1 Temperature occurrence detected
RM0483 Rev 5
RM0483
Power management controller digital interface (PMC_Dig)
Table 160. EPR_TD field descriptions (continued)
14.5.21
Field
Description
0
TEMP_0
TEMP_0 flag. This bit is the temperature status flag associated with the
temperature for the cold temperature sensor point. It is asserted when the
temperature exceeds its corresponding threshold, and clears when the
temperature falls below its corresponding threshold and a ‘1’ is written to this bit
location. If the IETD_0 bit is also asserted, an interrupt is sent to the CPU. If
REE_TD[TEMP_0] is also asserted, a system reset is generated, which clears
IETD_0 and negate the interrupt request. If REE_TD[TEMP_0] is asserted and
a destructive reset is selected (via RES_TD[TEMP_0] being 0), then a
destructive reset is generated. If RES_TD[TEMP_0] is set, then a functional
reset is generated.
0 Currently no occurrence
1 Temperature occurrence detected
Reset Event Enable Register (REE_TD)
This Reset Event Enable Register controls whether the temperature detect signal event
causes a reset. If the desired flag bit is enabled, the temperature detect event causes a
reset to be generated when the selected temperature passes the trigger event.
If the Temperature Sensor REE and RES bits are set to cause a destructive reset, then
during that process the TS REE and RES bits also get cleared by the destructive reset.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TEMP_1
TEMP_0
R
Access: User read/write, Supervisor read/write, Test read/write
TEMP_2
Offset: 0x0304
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Figure 91. Reset Event Enable Register (REE_TD)
RM0483 Rev 5
393/2075
407
Power management controller digital interface (PMC_Dig)
RM0483
Table 161. REE_TD field descriptions
14.5.22
Field
Description
2
TEMP_2
TEMP_2 reset enable. This bit defines whether a temperature detect assertion
generates a system reset. The RES_TD[TEMP_2] bit determines whether the
reset is functional or destructive.
0 Disabled. Temperature Sensor detect does not cause system reset.
1 Enabled. Temperature Sensor detect causes system reset.
1
TEMP_1
TEMP_1 reset enable. This bit defines whether a temperature detect assertion
generates a system reset. The RES_TD[TEMP_1] bit determines whether the
reset is functional or destructive.
0 Disabled. Temperature Sensor detect does not cause system reset.
1 Enabled. Temperature Sensor detect causes system reset.
0
TEMP_0
TEMP_0 reset enable. This bit defines whether a temperature detect assertion
generates a system reset. The RES_TD[TEMP_0] bit determines whether the
reset is functional or destructive.
0 Disabled. Temperature Sensor detect does not cause system reset.
1 Enabled. Temperature Sensor detect causes system reset.
Reset Event Select Register (RES_TD)
This Reset Event Select Register controls whether the temperature sensor detect signal
event causes a destructive or functional reset. If the desired flag bit is enabled, the
temperature sensor event causes either a destructive or functional reset to be generated
when the selected temperature passes the trigger event.
If the Temperature Sensor REE and RES bits are set to cause a destructive reset, then
during that process the TS REE and RES bits also get cleared by the destructive reset.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TEMP_1
TEMP_0
R
Access: User read/write, Supervisor read/write, Test read/write
TEMP_2
Offset: 0x0308
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Figure 92. Reset Event Select Register (RES_TD)
394/2075
RM0483 Rev 5
RM0483
Power management controller digital interface (PMC_Dig)
Table 162. RES_TD field descriptions
Field
14.5.23
Description
2
TEMP_2
TEMP_2 reset event select. This bit defines whether a temperature detect
assertion generates a destructive reset or a functional reset. The
REE_TD[TEMP_2] bit determines whether the reset event is enabled.
0 Destructive Reset Generated. Temperature Sensor assertion causes a
destructive system reset.
1 Functional Reset Generated. Temperature Sensor assertion causes a
functional system reset.
1
TEMP_1
TEMP_1 reset event select. This bit defines whether a temperature detect
assertion generates a destructive reset or a functional reset. The
REE_TD[TEMP_1] bit determines whether the reset event is enabled.
0 Destructive Reset Generated. Temperature Sensor assertion causes a
destructive system reset.
1 Functional Reset Generated. Temperature Sensor assertion causes a
functional system reset.
0
TEMP_0
TEMP_0 reset event select. This bit defines whether an temperature detect
assertion generates a destructive reset or a functional reset. The
REE_TD[TEMP_0] bit determines whether the reset event is enabled.
0 Destructive Reset Generated. Temperature Sensor assertion causes a
destructive system reset.
1 Functional Reset Generated. Temperature Sensor assertion causes a
functional system reset.
Temperature Sensor Configuration Register (CTL_TD)
The Temperature Sensor Configuration Registers (CTL_TD) contains two enables that must
both be enabled in order for the Temperature Sensor to be operable. It also includes two 5bit signed trim adjustment register fields that are used to modify both TS trim values (one
bus for over temperature and one bus for under temperature).
18
1
0
0
0
0
5
4
3
2
1
0
ADC_AOUT_EN
31
30
29
28
27
26
25
24
23
22
21
20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
0
0
0
1
W
TS1IE
TS0IE
0
TS2IE
R
Reset
0
0
0
0
TRIM_ADJ_
OVER
Reset
0
0
0
0
7
6
0
0
0
0
TRIM_ADJ_
UNDER
W
17
16
TRIM_ADJ_
OVER1
19
AMUX_CTAT_
TS_CTRL
R
Access: User read/write, Supervisor read/write, Test read/write
PMC_AOUT_EN
Offset: 0x030C
Figure 93. Temperature Sensor Configuration Register (CTL_TD)
RM0483 Rev 5
395/2075
407
Power management controller digital interface (PMC_Dig)
RM0483
Table 163. CTL_TD field descriptions
Field
20
PMC_AOUT_EN
PMC_AOUT_EN. Temperature Sensor Enable for PMU. Refer to the
Temperature Sensor chapter for details.
19:16
TRIM_ADJ_OVER1
TRIM_ADJ_OVER1[3:0]. Customer adjustable over trim register for
PMU. These bits are a signed binary number that is added to the over
temperature trim (NT_TD1) value. The TRIM value is protected from
overflows and underflows due to this addition. Here MSB bit is sign bit
and third bit is tied to zero, the actual trim values are on 2:0 bits. Refer
to the Temperature Sensor chapter for details.
15
TS2IE
TS2IE Temperature Sensor input 2 Interrupt Enable. This bit determines
whether an interrupt is seen by the system when the voltage detect
event occurs. The MSB in IE_G must be set to access this bit.
0 No interrupt occurs
1 An interrupt occurs
14
TS1IE
TS1IE Temperature Sensor input 1 Interrupt Enable. This bit determines
whether an interrupt is seen by the system when the voltage detect
event occurs. The MSB in IE_G must be set to access this bit.
0 No interrupt occurs
1 An interrupt occurs
13
TS0IE
TS0IE Temperature Sensor input 0 Interrupt Enable. This bit determines
whether an interrupt is seen by the system when the voltage detect
event occurs. The MSB in IE_G must be set to access this bit.
0 No interrupt occurs
1 An interrupt occurs
11:8
TRIM_ADJ_OVER
TRIM_ADJ_OVER[3:0]. Customer adjustable over trim register for
ADC. These bits are a signed binary number that is added to the over
temperature trim (NT_TD2) value. The TRIM value is protected from
overflows and underflows due to this addition. Here MSB bit is sign bit
and third bit is tied to zero, the actual trim values are on 2:0 bits. Refer
to the Temperature Sensor chapter for details.
5:2
TRIM_ADJ_UNDER
TRIM_ADJ_UNDER[3:0]. Customer adjustable under trim register.
These bits are a signed binary number that is added to the Under
temperature trim value (NT_TD0). The TRIM value is protected from
overflows and underflows due to this addition. Here MSB bit is sign bit
and third bit is tied to zero, the actual trim values are on 2:0 bits. Refer
to the Temperature Sensor chapter for details.
1
AMUX_CTAT_TS_CTRL
AMUX_CTAT_TS_CTRL. Analog mux enable. Refer to the Temperature
Sensor chapter for details.
0
ADC_AOUT_EN
14.5.24
Description
ADC_AOUT_EN. Temperature Sensor Enable for ADC. Refer to the
Temperature Sensor chapter for details.
Temperature Sensor FCCU Event Enable Register (FEE_TD)
This Temperature Sensor FCCU Event Enable Register controls whether the temperature
sensor detect signal event causes an event signal to be sent to the FCCU (Fault Collection
and Control Unit). If the desired flag bit (EPR_TD) is enabled, the temperature sensor detect
assertion causes an FCCU event to be generated when the selected temperature exceeds
the desired value.
396/2075
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RM0483
Power management controller digital interface (PMC_Dig)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FEE_TS1
FEE_TS0
R
Access: User read/write, Supervisor read/write, Test read/write
FEE_TS2
Offset: 0x0318
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
W
Reset
R
W
Reset
Figure 94. Temperature Sensor FCCU Event Enable Register (FEE_TD)
Table 164. Temperature Sensor FEE_TD field descriptions
Field
14.5.25
Description
2
FEE_TS2
FEE_TS2 Temp Sensor FCCU event enable. This bit defines whether a
temperature detect assertion generates an FCCU event.
0 Disabled. Temp Sensor detect does not cause an FCCU event.
1 Enabled. Temp Sensor detect causes an FCCU event.
1
FEE_TS1
FEE_TS1 Temp Sensor FCCU event enable. This bit defines whether a
temperature detect assertion generates an FCCU event.
0 Disabled. Temp Sensor detect does not cause an FCCU event.
1 Enabled. Temp Sensor detect causes an FCCU event.
0
FEE_TS0
FEE_TS0 Temp Sensor FCCU event enable. This bit defines whether a
temperature detect assertion generates an FCCU event.
0 Disabled. Temp Sensor detect does not cause an FCCU event.
1 Enabled. Temp Sensor detect causes an FCCU event.
BIST Mask Status register (BIST_MASK_STATUS)
This status register contains a monitor of the BIST MASK signal.
Offset: 0x03C8
R
Access: User read-only
31
30
29
28
27
26
0
0
0
0
0
0
25
0
0
0
0
0
0
0
15
14
13
12
11
10
9
24
23
22
21
20
19
18
17
16
BIST_MASK
W
Reset
R
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
BIST_MASK
W
Reset
0
0
0
0
0
0
0
0
0
Figure 95. BIST Mask Status register (BIST_MASK_STATUS)
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RM0483
Table 165. BIST_MASK_STATUS field descriptions
Field
Description
BIST mask status
Bit 25: mvd114b_c_1p2d_mask status
Bit 24: mvd114b_fa_1p2d_mask status
Bit 23: lvd119b_pll0_1p2d_mask status
Bit 22: lvd119b_c_1p2d_mask status
Bit 21: lvd119b_fl_1p2d_mask status
Bit 20: lvd119b_pll1_1p2d_mask status
Bit 19: lvd119b_dd_1p2d_mask status
Bit 18: lvd119b_rc_1p2d_mask status
Bit 17: mvd270b_c_main_1p2d_mask status
Bit 16: mvd270b_fl_1p2d_mask status
Bit 15: lvd290b_c_1p2d_mask status
Bit 14: lvd290b_fl_1p2d_mask status
Bit 13: lvd290b_ad_1p2d_mask status
Bit 12: lvd290b_as_1p2d_mask status
Bit 11: lvd290b_io1_1p2d_mask status
Bit 10: lvd290b_io0_1p2d_mask status
Bit 9: lvd290b_osc_1p2d_mask status
Bit 7: lvd290b_daccmp_1p2d_mask status
Bit 7: hvd140b_c_1p2d_mask status
Bit 6: uvd145b_c_1p2d_mask status
Bit 5: uvd145b_rc_1p2d_mask status
Bit 4: uvd380b_c_1p2d_mask status
Bit 3: uvd380b_fl_1p2d_mask status
Bit 2: uvd380b_as_1p2d_mask status
Bit 1: uvd380b_io0_1p2d_mask status
Bit 0: uvd380b_daccmp_1p2d_mask status
25:0
BIST_MASK
14.5.26
User BIST Flags Phase1 register (BIST_FLAGS_PHASE1)
This configuration register contains a monitor of the flags phase1 coming from the User
BIST sub-block.
Offset: 0x03CC
R
Access: User read-only
31
30
29
28
27
26
0
0
0
0
0
0
25
0
0
0
0
0
0
0
15
14
13
12
11
10
9
24
23
22
21
20
19
18
17
16
FLAGS_P1
W
Reset
R
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
FLAGS_P1
W
Reset
0
0
0
0
0
0
0
0
0
Figure 96. User BIST Flags Phase1 register (BIST_FLAGS_PHASE1)
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Power management controller digital interface (PMC_Dig)
Table 166. BIST_FLAGS_PHASE1 field descriptions
Field
Description
The 26 bits of field FLAGS_P1 are the phase one flags of the User BIST that
indicate the status of monitor when it is tripped:
Bit 25 - UVD380B_DACCMP
Bit 24 - UVD380B_IO0
Bit 23 - UVD380B_AS
Bit 22 - UVD380B_FL
Bit 21 - UVD380B_C
Bit 20 - UVD145B_RC
Bit 19 - UVD145B_C
Bit 18 - HVD140B_C
Bit 17 -LVD290B_DACCMP
Bit 16 - LVD290B_OSC
Bit 15 - LVD290B_IO0
Bit 14 - LVD290B_IO1
Bit 13 - LVD290B_AS
Bit 12 - LVD290B_AD
Bit 11 - LVD290B_FL
Bit 10 - LVD290B_C
Bit 9 - MVD270B_FL
Bit 8 - MVD270B_C_MAIN
Bit 7 - LVD119B_RC
Bit 6 - LVD119B_DD
Bit 5 - LVD119B_PLL1
Bit 4 - LVD119B_FL
Bit 3 - LVD119B_C
Bit 2 - LVD119B_PLL0
Bit 1 - MVD114B_FA
Bit 0 - MVD114B_C
25:0
FLAGS_P1
14.5.27
User BIST Flags Phase2 register (BIST_FLAGS_PHASE2)
This configuration register contains a monitor of the flags phase2 coming from the User
BIST sub-block.
Offset: 0x03D0
R
Access: User read-only
31
30
29
28
27
26
0
0
0
0
0
0
25
0
0
0
0
0
0
0
15
14
13
12
11
10
9
24
23
22
21
20
19
18
17
16
FLAGS_P2
W
Reset
R
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
FLAGS_P2
W
Reset
0
0
0
0
0
0
0
0
0
Figure 97. User BIST Flags Phase2 register (BIST_FLAGS_PHASE2)
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RM0483
Table 167. BIST_FLAGS_PHASE2 field descriptions
Field
Description
25:0
FLAGS_P2
14.5.28
The 26 bits of field FLAGS_P2 are the phase two flags of the User BIST that
indicate the status of monitor when it is lifted:
Bit 25 - UVD380B_DACCMP
Bit 24 - UVD380B_IO0
Bit 23 - UVD380B_AS
Bit 22 - UVD380B_FL
Bit 21 - UVD380B_C
Bit 20 - UVD145B_RC
Bit 19 - UVD145B_C
Bit 18 - HVD140B_C
Bit 17 -LVD290B_DACCMP
Bit 16 - LVD290B_OSC
Bit 15 - LVD290B_IO0
Bit 14 - LVD290B_IO1
Bit 13 - LVD290B_AS
Bit 12 - LVD290B_AD
Bit 11 - LVD290B_FL
Bit 10 - LVD290B_C
Bit 9 - MVD270B_FL
Bit 8 - MVD270B_C_MAIN
Bit 7 - LVD119B_RC
Bit 6 - LVD119B_DD
Bit 5 - LVD119B_PLL1
Bit 4 - LVD119B_FL
Bit 3 - LVD119B_C
Bit 2 - LVD119B_PLL0
Bit 1 - MVD114B_FA
Bit 0 - MVD114B_C
User BIST Control register (BIST_CTRL)
The User BIST Control register (BIST_CTRL) contains both control bits and status bits to
manage the User BIST.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
IRQST
0
0
0
IRQEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
NCFEN
0
0
0
0
START
R
Access: User read/write, Supervisor read/write, Test read/write
NCFST
Offset: 0x03D4
0
0
0
0
0
0
0
0
0
0
Reset
R
W
Reset
0
0
0
STATUS
W
0
0
0
Figure 98. User BIST Control register (BIST_CTRL)
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Power management controller digital interface (PMC_Dig)
Table 168. BIST_CTRL field descriptions
14.5.29
Field
Description
20
IRQST
IRQST is the interrupt request pending status bit to generate a User BIST
Interrupt. It is a R/W0 register. That means Set by HW and Cleared by SW.
The destructive reset resets this bit.
0 No interrupt occurred
1 An interrupt occurred
16
IRQEN
IRQEN is the interrupt request enable bit to permit a User BIST Interrupt. It is
a R/W register. The destructive reset resets this bit.
0 Interrupt is disabled
1 Interrupt enabled
12
NCFST
NCFST is the Not Critical Fault bit. The assertion of this bit generates FCCU
event once user BIST fails. It is set by HW and Cleared by SW. The
destructive reset resets this bit.
0 No User BIST NCF occurred
1 A User BIST NCF occurred
8
NCFEN
NCFEN is the Not Critical Fault enable bit to permit a User BIST Not Critical
Fault and Fault indication is sent to FCCU. It is a R/W register. The
destructive reset resets these bits.
0 No User BIST NCF enabled
1 A User BIST NCF enabled
6:4
STATUS
STATUS register consists of 3 read-only bits, that according to the value has
its own meaning.
000 BIST_IDLE
001 BIST_RUN
010 BIST_PASSED
011 BIST_FAILED
100 BIST_ABORT
101 Reserved
110 Reserved
111 Reserved
0
START
START User BIST bit. If set by SW a 1 is present in the START bit for a
System clock cycle only, then the START bit register is clear by HW. The
destructive reset resets this bit.
0 No start pulse.
1 A start pulse occurs of a 1 System clock cycle duration
User BIST Time1 and Time0 register (BIST_TIME10)
The User BIST Time1 and Time0 Register (BIST_TIME10) contains two time numbers
Time1 and Time0 giving the System clock cycles number required by the User BIST timer1
and timer0 (refer to Section 14.9: Voltage monitor BIST programming for more information
regarding the User BIST timer registers).
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Power management controller digital interface (PMC_Dig)
Offset: 0x03D8
R
Access: User read/write, Supervisor read/write, Test read/write
31
30
29
28
0
0
0
0
27
26
25
24
23
R
0
0
0
0
0
0
1
1
1
1
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
21
20
19
18
17
16
1
0
0
1
1
1
5
4
3
2
1
0
1
0
0
1
1
TIME_0
W
Reset
22
TIME_1
W
Reset
RM0483
0
0
0
1
1
1
1
Figure 99. User BIST Time1 and Time0 register (BIST_TIME10)
Table 169. BIST_TIME10 field descriptions
14.5.30
Field
Description
28:16
TIME_1
TIME_1 is the system clock cycles number required by the TIMER 1 in the User
BIST management. The destructive reset resets these bits.
12:0
TIME_0
TIME_0 is the system clock cycles number required by the TIMER 0 in the User
BIST management. The destructive reset resets these bits.
User BIST Time3 and Time2 register (BIST_TIME32)
The User BIST Time3 and Time2 Register (BIST_TIME32) contains two time numbers
Time3 and Time2 giving the system clock cycles number required by the User BIST timer3
and timer2 (refer to Section 14.9: Voltage monitor BIST programming for more information
regarding the User BIST timer registers).
Offset: 0x03DC
R
Access: User read/write, Supervisor read/write, Test read/write
31
30
29
28
0
0
0
0
27
26
25
24
23
0
0
0
0
0
0
1
1
1
R
15
14
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
21
20
19
18
17
16
TIME_3
W
Reset
22
1
1
0
0
1
1
1
6
5
4
3
2
1
0
0
0
1
1
1
TIME_2
W
Reset
0
0
1
1
1
1
1
Figure 100. User BIST Time3 and Time2 register (BIST_TIME32)
Table 170. BIST_TIME32 field descriptions
402/2075
Field
Description
28:16
TIME_3
TIME_3 is the system clock cycles number required by the TIMER 3 in the
User BIST management. The destructive reset resets these bits.
12:0
TIME_2
TIME_2 is the system clock cycles number required by the TIMER 2 in the
User BIST management. The destructive reset resets these bits.
RM0483 Rev 5
RM0483
Power management controller digital interface (PMC_Dig)
14.5.31
User BIST Time6 and Time5 register (BIST_TIME65)
The User BIST Time6 and Time5 Register (BIST_TIME65) contains two time numbers
Time6 and Time5 giving the system clock cycles number required by the User BIST timer6
and timer5 (refer to Section 14.9: Voltage monitor BIST programming for more information
regarding the User BIST timer registers).
Offset: 0x03E0
R
Access: User read/write, Supervisor read/write, Test read/write
31
30
29
28
0
0
0
0
27
26
25
24
23
0
0
0
0
0
0
0
0
0
0
R
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
20
19
18
17
16
0
0
1
0
0
1
5
4
3
2
1
0
0
1
0
0
1
TIME_5
W
Reset
21
TIME_6
W
Reset
22
0
0
0
0
0
0
0
Figure 101. User BIST Time6 and Time5 register (BIST_TIME65)
Table 171. BIST_TIME65 field descriptions
Field
14.5.32
Description
28:16
TIME_6
TIME_6 is the system clock cycles number required by the TIMER 6 in the
User BIST management. The destructive reset resets these bits.
12:0
TIME_5
TIME_5 is the system clock cycles number required by the TIMER 5 in the
User BIST management. The destructive reset resets these bits.
User BIST VD Under Test Monitor register (BIST_DEBUG)
This VD Under Test Monitor register contains a monitor of the Voltage Detector Under Test
of the USER BIST sub-block.
Note:
The BIST_DEBUG register can only be read while BIST is running. Once BIST is finished
the status can be obtained by checking the BIST_FLAGS_PHASE1 and
BIST_FLAGS_PHASE2 registers.
Offset: 0x03E4
R
Access: User read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
VD_MON
W
Reset
0
0
0
0
Figure 102. User BIST VD Under Test Monitor register (BIST_DEBUG)
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RM0483
Table 172. BIST_DEBUG field description
14.6
Field
Description
5:0
VD_MON
The six read only bits of field VD_MON give the current VD Under Test of the
User BIST unit, among 26 VDs available, according to the following values:
0x1E: MVD114_C
0x1D: MVD114_FA
0x1C: LVD119_PLL0
0x1B: LVD119_C
0x1A: LVD119_FL
0x16: LVD119_DD
0x15: MVD270_C
0x14: MVD270_FL
0x13: LVD290_C
0x12: LVD290_FL
0x11: LVD290_AD
0x10: LVD290_AS
0x0F: LVD290_IO1
0x0E: LVD290_IO0
0x06: UVD145_RC
0x19: HVD140_C
0x18: UVD145_C
0x17: LVD119_PLL1
0x0D: LVD290_OSC
0x0C: LVD290_DACCMP
0x0B: UVD380_DACCMP
0x05: UVD380_C
0x04: UVD380_FL
0x03: UVD380_AS
0x02: UVD380_IO0
0x01: LVD119_RC
0x00: No VD under Test
Temperature Sensor Interface Logic
The Temperature Sensor interface consists of an analog enable, a set of mode registers,
and an overtemp threshold select control.
For more information regarding the Temperature Sensor function, refer to the Chapter 33:
Temperature Sensor.
14.7
Power On Reset (RCC Phase Gates)
The PMU digital logic interfaces to the Reset Generation Module in order to indicate the
type and conditions of the resets from the PMU and Temperature Sensor Analog blocks.
There are two signals for both the PMU and Temp Sensor blocks; one is used to indicate a
destructive reset, and one is used to indicate a functional reset.
The PMU digital logic also indicates when the RCC allows transition to the next POR phase.
The digital PMU also uses signals from the RCC to indicate when some of the reset signals
have to be masked during the POR sequence.
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Power management controller digital interface (PMC_Dig)
During the POR phase 3 exit, the PMU digital logic uses all the enabled Voltage Detects to
determine if it is correct to exit from Phase 3. Once all the enabled LVDs and HVDs have
become deasserted and the time from the LVD circuits to adjust to new trim values has
elapsed, then the signal is sent to the RCC so that the correct voltage levels have been
achieved to exit from Phase 3.
14.8
Flash interface (DCF client usage)
The PMU digital is updated during POR from the Flash block via a DCF client. This load is
used for several pieces of data, but most of the data is trim values being used for analog
modules (PMU, Temperature Sensor, and ADC Bandgap).
These trim bits that are loaded from the Flash are not readable via the IP bus. These trim
values loaded via the DCF client are not compacted (they are written individually, and not
several at a time).
A DCF client is used to interface to the Flash for these early data accesses. This client also
performs triple voting to keep the data safe from stray bit flips.
Another set of data that is loaded during the DCF single read process are updated values
for the REE and RES bits. Refer to:
•
Section 14.5.2: Reset Event Enable Register (REE_LV0),
•
Section 14.5.3: Reset Event Select Register (RES_LV0),
•
Section 14.5.7: Reset Event Enable Register (REE_LV1),
•
Section 14.5.8: Reset Event Select Register (RES_LV1),
•
Section 14.5.12: Reset Event Enable Register (REE_HV0) and
•
Section 14.5.13: Reset Event Select Register (RES_HV0) for more information
regarding the REE/RES bits load from Flash.
If the REE bit is loaded via the DCF as set (enabled), then it is not possible to clear this REE
bit. The reset value of the REE DCF bits are all low (thus to allow the bits to be rewritable)
and the same is the reset value of the REE register.
The monitors for which reactions are enabled are programmed in the corresponding bit flag
of Reset Event Enable (REE_XX) register as “1” (reset enabled) and in the Reset Event
Select (RES_XX) register as “0” (destructive reset selected).
The monitors for which reactions are not enabled are programmed in the corresponding bit
flag of Reset Event Enable (REE_XX) register as “0” (reset disabled) and in the Reset Event
Select (RES_XX) register as “1” (functional reset selected).
The REE DCF bits loaded are compacted into a single DCF write (they do not match the IPS
Bus register bit locations). The REE DCF loaded bits do not have the same limitation that
they can only be written once and any further writes must be to the same value. The REE
DCF bits can be rewritten to a new value during a new reset event.
When the REE DCF bits are updated, the REE and RES register bits are updated at the
same time to the new value.
All of the DCF clients are reset via the POR reset signal.
For more information regarding the DCF records, refer to the DCF Records chapter.
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RM0483
The trim data is read out of the Flash’s differential read space (slower access, but less
issues with voltage variances). Once the differential reads are completed, the Flash
indicates this to the PMU digital via the SSCM module.
Once the PMU trim values have been read, the analog circuit has been given time to update
to the new trim values, and the LVDs have all deasserted, a signal is asserted to the Flash
to indicate that the voltage is high enough for faster single access reads.
All of the LVD signals must indicate that a valid voltage has been reached before the voltage
indication is sent to the Flash.
14.9
Voltage monitor BIST programming
The Built-In Self Test (BIST) is a software initiated testing procedure used to verify all the
voltage monitors.
The application has to program the BIST_TIMExx registers according to the following
timings with respect to the configured PCLK1:
•
BIST_TIME10[Time_0] = 40 µs.
•
BIST_TIME10[Time_1] = 50 µs.
•
BIST_TIME32[Time_2] = 50 µs.
•
BIST_TIME32[Time_3] = 50 µs.
•
BIST_TIME65[Time_5] = 200 ns.
•
BIST_TIME65[Time_6] = 200 ns.
In case the aforementioned timings are not applied, some voltage monitor BIST could
trigger fake faults.
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Power management controller digital interface (PMC_Dig)
The user can run a BIST mode by setting the BIST_CTRL[START] register bit. The following
voltage detectors are then serially tested:
•
MVD114_C
•
MVD114_FA
•
LVD119_PLL0
•
LVD119_C
•
LVD119_FL
•
LVD119_PLL1
•
LVD119_DD
•
LVD119_RC
•
MVD270_C
•
MVD270_FL
•
LVD290_C
•
LVD290_FL
•
LVD290_AD
•
LVD290_AS
•
LVD290_IO1
•
LVD290_IO0
•
LVD290_OSC
•
LVD290_DACCMP
•
HVD140_C
•
UVD145_C
•
UVD145_RC
•
UVD380_C
•
UVD380_FL
•
UVD380_AS
•
UVD380_IO0
•
UVD380_DACCMP
Interrupt can be enabled by programming BIST_CTRL[IRQEN] and interrupt status is
checked with BIST_CTRL[IRQST] on completion of BIST sequence.
FCCU event can be enabled by programming BIST_CTRL[NCFEN]. The
BIST_CTRL[NCFST] status indicates BIST Fail on completion of BIST sequence.
BIST_DEBUG[VD_MON] register bits allow to know which voltage detector is under test.
The overall status of BIST is provided by the BIST_CTRL[STATUS] register bits.
The status of individual monitors is checked in flag registers BIST_FLAGS_PHASE1 (pass
is all zero) and BIST_FLAGS_PHASE2 (pass is all one).
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Platform RAM controller AXI (PRAMC_AXI)
15
Platform RAM controller AXI (PRAMC_AXI)
15.1
Introduction
RM0483
This section provides an overview of the Platform RAM Controller AXI. The module acts as
an interface between the system bus (AMBA AXI4) and the integrated System RAM. It
converts the protocols between the system bus and the dedicated RAM array interface.
Figure 103 below is a simplified block diagram depicting the position of the PRAM controller
AXI within a typical platform architecture:
Figure 103. Platform block diagram
The RAM controller supports one AXI interface configurable to 64-bit/128-bit/256-bit and a
RAM array interface configurable to 64-bit/128-bit/256-bit.
The block consists of two main modules, one of them being the AXI4 read interface and the
other AXI4 write interface. Both the read and write interfaces support all AXI4 burst types
and sizes.
15.2
Features
The following list summarizes the key features of the RAM controller:
•
The RAM controller adheres to the AMBA AXI4 Interface standard.
It includes the following features with few exceptions:
–
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Support for all AXI4 burst types and sizes:
RM0483 Rev 5
RM0483
Platform RAM controller AXI (PRAMC_AXI)
– Handling of FIXED bursts is configurable in the design.
– Support INCR burst sizes up to 256 data transfers and WRAP bursts of 2, 4,
8 and 16 beats.
–
Support for narrow width transactions where data transfers are on different byte
lanes for each beat of the burst.
–
Support for exclusives using the AXI lock attribute.
–
No support for user, prot, and qos AXI attributes.
–
No support for cachability or bufferability.
–
No support for outstanding transactions. It accepts a single address for each of the
read/write channels.
–
No support for reordering. Transactions are executed in order regardless of
transaction ID.
–
It has the attributes listed in the following table:
Table 173. PRAMC_AXI slave attributes
Slave attribute
Description
Value
Write acceptance capability
Max. number of active writes
that a slave can accept
1
Read acceptance capability
Max. number of active reads
that a slave can accept
1
Write interleave depth
No. of active writes for which
slave can receive data
1
Read data reorder depth
No. of active reads for which
slave can transmit data
1
•
The RAM Controller provides a single port memory interface for SRAM/ROM with
configurable RAM data width (64-bit, 128-bit, 256-bit) which is the same as AXI Bus
Width.
•
The RAM Controller provides support for read-modify-write operation to support
memory writes with sparse byte strobes and any access less than ECC granularity.
•
The RAM Controller provides support for Exclusives for multiple processing elements.
•
The RAM Controller assigns priority to the read channel when presented with
simultaneous assertions of read address phase, write address phase and write data
phase.
•
The RAM Controller provides configurability for wait-state on access to RAM array to
target higher memory access times. It is zero or one state programmable.
•
The RAM Controller provides punch-through clock generation capability to enable
memories to run at half the system frequency. This can be configured by adding wait
state on read as well as write.
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Platform RAM controller AXI (PRAMC_AXI)
15.3
RM0483
•
The RAM Controller provides support for Memory Reconstruction to enable
reconstruction of memory image for debug and trace purposes.
•
The RAM Controller provides support for IPS interface which provides a memory
mapped access to RAMC's programming model:
–
Programming model can be referenced only using 32-bit access. Any accesses
using different access sizes to reserve addresses are terminated with an IPS
error.
–
Programming model access is allowed only in supervisor mode.
•
The RAM Controller provides 64-bit ECC granularity. The ECC scheme is aligned to
the Cortex®-M7.
•
The RAM Controller extracts the check-bits from the original check-bits in case of a
read-modify-operation to provide end to end coverage.
•
The RAM Controller performs an EDC check on the data read from memory to report
any memory error to MEMU2.
Memory map and register description
The Platform RAM controller module provides an IPS programming model mapped to a
standard 16 KB on-platform peripheral slot. The programming model can only be referenced
using a 32-bit access. Attempted references using different access sizes or to reserved
addresses generate an IPS error termination. The programming model can only be
accessed in supervisor mode.
Attempted updates to the programming model while the RAM controller module is in the
midst of an operation result in undetermined behavior. The software architecture must avoid
this scenario.
15.3.1
Memory map
Table 174. PRAMC_AXI memory map
Address offset
0x0000
Register
Location
Platform RAM Controller Configuration Register (CR)
0x0004–0x0007
Section 15.3.2.1
Reserved
15.3.2
Register definitions
15.3.2.1
Platform RAM controller Configuration Register (CR)
The platform RAM controller Configuration Register (CR) is used to specify operation of the
RAM Controller.
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Platform RAM controller AXI (PRAMC_AXI)
Offset: 0x0000
R
Access: Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
FIXED_BURST_EN
W
0
RWS_EN
R
MEMACC_WAIT
Reset
WWS_EN
W
0
0
0
0
0
Figure 104. Platform RAM controller Configuration Register (CR)
Table 175. CR field descriptions
Field
Description
4
WWS_EN
Wait State Enable for writes
This bit controls the wait state to be added for all write transactions. The
state of this field effects full width writes as well as narrow width writes.
This field is used to enable the memories to run at half the system
frequency using punch-through clock
0 No extra wait state for Write operations
1 One extra wait state for Write operations
Wait State Enable for ECC for RMW operations
3
MEMACC_WAIT
2
RWS_EN
1
FIXED_BURST_EN
This bit controls the wait state required for ECC calculation on RMW path.
The state of this field has no effect on the response latency of reads.
0 No extra wait state for RMW operations.
1 One extra wait state for RMW operations.
Wait State Enable for high memory access time
This bit controls the wait state to be added to the best case RAM array
access time for read. The state of this field effects read as well as partial
write operations.
0 RAM read takes 1 cycle.
1 RAM read takes 2 cycles.
Fixed Burst Enable
This bit controls burst transaction behavior for a FIXED type burst.
0 Fixed burst not supported. PRAMC signals SLVERR.
1 Fixed burst is supported by PRAMC.
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Platform RAM controller AXI (PRAMC_AXI)
15.4
Functional description
15.4.1
Read/write
RM0483
The RAM controller generates chip-select, write enable, array address, write mask and write
data as inputs to the RAM array. The RAM controller captures read data from the RAM array
and drives it onto the AXI4 System bus. To facilitate operation at higher frequencies, the
RAM controller can optionally incur a single wait state on the AXI system bus.
Table 176. AXI read-write channels stall conditions
Channel
15.4.1.1
Condition
Write address channel
Write address channel is stalled under following conditions:
– Waiting for data for 1st write transfer
– Write address received while ongoing read
– Write address received at same time as read
It is stalled until the last write to the current transaction is initiated to
the memory.
Write data channel
Write data channel is stalled under following conditions:
– Waiting for Write Address to start the write transfer
– Write data received while ongoing read
– Write data received at same time as read
– Every write transfer with access size < ECC granularity
It is stalled until write transaction can make progress after read has
completed.
Write response channel
Write response channel is stalled under the following condition:
– Master is not ready to accept the write response.
Read address channel
Read address channel is stalled until last read for the current
transaction is initiated to the memory.
(NUM_OUTSTANDING_READS =1)
Read data/response channel
Read data channel is stalled until the Master is ready to accept the
read response.
Reads
Read transfers of any size can be configured to complete with either a zero or one additional
wait state response on the AXI system bus.
The read proceeds in a similar way even if a write request arrives at the same time as the
read request.
412/2075
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RM0483
Platform RAM controller AXI (PRAMC_AXI)
Figure 105. Read with CR[RWS_EN]=0
15.4.1.2
Optional read wait state
The RAM controller can be optionally programmed for use when operating with slower
memory access times.
A random initial access takes two clock cycles to complete if CR[RWS_EN]=0 and a
WRAP4 burst have an access time of 2-1-1-1.
A random initial access takes three clock cycles to complete if CR[RWS_EN]=1 and a
WRAP4 burst have an access time of 3-2-2-2.
Figure 106. Read with CR[RWS_EN]=1
15.4.1.3
Writes
15.4.1.3.1 256/218/64-bit writes
Full width writes (256/128/64 bits) are completed in single cycle or in two cycles to maintain
pulse width requirements for memories. The RAM controller can be optionally programmed
for this requirement.
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Platform RAM controller AXI (PRAMC_AXI)
RM0483
Figure 107. Full width write with CR[WWS_EN]=0
15.4.1.3.2 Optional Write Wait State
The RAM controller can be optionally programmed for use to meet pulse width requirements
at higher frequencies.
A write takes one clock cycle to complete if CR[WWS_EN]=0 and a WRAP4 burst complete
in 1-1-1-1.
A write takes two clock cycles to complete if CR[WWS_EN]=1 and a WRAP4 burst complete
in 2-2-2-2.
Figure 108. Full width write with CR[WWS_EN]=1
15.4.1.3.3 Less than 64 bits writes
Writes of size less than 64 bits require a read-modify-write operation as a consequence of
the ECC coding scheme's 64 bits granularity. In case of a read-modify-write operation,
PRAM controller performs SEC/DED on the read data. The write data is merged into the
appropriate byte lanes along with potentially corrected read data. A new codeword is
generated based on the newly formed data. The newly formed data and its associated
checkbits are subsequently written to the RAM.
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Platform RAM controller AXI (PRAMC_AXI)
Valid wait state combinations for RMW operations are:
CR[RWS_EN], CR[WWS_EN], CR[MEMACC_WAIT]=000
or
CR[RWS_EN], CR[WWS_EN], CR[MEMACC_WAIT]=111
Figure 109. Narrow width write with CR[RWS_EN]=0; CR[WWS_EN]=0;
CR[MEMACC_WAIT]=0
Figure 110. Narrow width write with CR[RWS_EN]=1; CR[WWS_EN]=1;
CR[MEMACC_WAIT]=1
15.5
Initialization/application information
It is essential to initialize each memory address to a known value before reading to avoid
generation of spurious ECC errors. Without writing an address to a known value first, a read
from this address most likely generates uncorrectable ECC events.
15.6
Safety considerations
15.6.1
Data Protection
The RAM controller implements single error correction double error detection using 64-bit
ECC scheme used in Cortex®-M7.
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Platform RAM controller AXI (PRAMC_AXI)
15.6.1.1
RM0483
Write
The RAM controller receives data along with checkbits from the NIC.
In case of a full-width write, there is no ECC check and the data is written along with the
checkbits in the RAM memory.
In case of a partial write operation, the RAM controller performs a read-modify-write
operation. The RAM controller reads the data stored in the target location and performs
SECDED on the read data. It then merges it with the data received from master and
generates the new checkbits to be written to the RAM memory. Any single or multi-bit error
detected during the read from memory is reported to the MEMU2. It responds with an error
response on the system bus in case of a multi-bit error.
The datapath for a RMW operation is highlighted below.
Figure 111. PRAM Controller ECC management for read-modify-writes
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The RAM Controller uses the following checkbit manipulation technique to ensure faults in
the PRAM control logic associated with performing the read-modify-write operation are
ultimately detected by e2e ECC:
•
On a partial write request, the write data is presented on AXI system bus in correct byte
lanes with non-pertinent byte lanes zeroed out. The associated check-bit is based on
this “zero-padded” write data.
For example, the case where Master performs a 16-bit write at address 0x0000_0004.
Figure 112. Write data ECC calculation step1
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416/2075
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RAM controller treats that request as a read-modify-write operation and initiates a read
to that address. An ECC check and potential single-bit correction is performed on the
RM0483 Rev 5
RM0483
Platform RAM controller AXI (PRAMC_AXI)
data returned from the RAM. If a non-correctable ECC event is detected, an error is
signaled on the AXI system bus. Additionally, the ECC event is reported to MEMU2.
Figure 113. Write data ECC calculation step2
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RAM Controller isolates the pertinent byte lanes of the read data by zero-padding the
non-pertinent byte lanes and calculating the checkbit contribution associated with the
read data in the byte lanes to be updated as a result of the write request.
Figure 114. Write data ECC calculation step3
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For WR data generation: merge the non-pertinent read data bytes with the write data in
appropriate byte lanes.
For WR ECC generation: take the checkbit value stored in RAM and remove the
checkbit contribution associated with the read data in the byte lanes to be updated.
Then introduce the checkbits associated with the write data. The result is ultimately a
checkbit value associated with 64-bit data to be written to the array.
This is done in two chunks of 64 bits for 128 bits of data.
RM0483 Rev 5
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Platform RAM controller AXI (PRAMC_AXI)
RM0483
Figure 115. Write data ECC calculation step4
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This method calculates the checkbit value on a read-modify-write transaction through a
series of data manipulations, thus taking care to avoid discarding of original checkbits
provided by the requesting master.
Malfunction of ECC logic described above may result in corruption of error event reporting.
Thus, EDC after ECC check is performed on all read-modify-write transactions. If a
mismatch is detected, indicating a failure in the ECC logic, the event is reported to FCCU.
15.6.1.2
Read
The RAM controller performs an EDC check on the data read from the RAM. Any
single/multi-bit error does not gate the read response path while it is reported to the
MEMU2.
15.6.2
MEMU2 interface
There is one channel to the MEMU2 for each 64-bit chunk of data. The same channel is
used to report an error on a read or an RMW operation to MEMU2.
15.6.2.1
Memory Update in case of ECC error
Memory is not updated if an uncorrectable error is detected for a narrow write transfer. The
following table lists the possible scenarios.
Table 177. Memory updates in case of ECC error
418/2075
Error in 4th chunk
(bits [255:192])
Error in 3rd chunk
(bits [191:128])
Error in 2nd chunk
(bits [127:64])
Error in 1st chunk
(bits [63:0])
Memory
updated
Correctable Error
Correctable Error
Correctable Error
Correctable Error
Yes
Uncorrectable Error
X
X
X
No
X
Uncorrectable Error
X
X
No
X
X
Uncorrectable Error
X
No
X
X
Uncorrectable Error
No
RM0483 Rev 5
RM0483
15.6.3
Platform RAM controller AXI (PRAMC_AXI)
Memory feedback monitor
The feedback checker provides functional safety coverage between the PRAM controller
and the RAM array.
The function of the monitor relies on a feedback path between the PRAM controller and the
RAM array. The RAM provides latched address and control feedback outputs as indication
of received inputs when a RAM access is initiated. The feedback monitor uses this feedback
information to verify the expected transaction. A mismatch indicates a failure in the
transmission path between the PRAM controller and the RAM array. The event is forwarded
to the fault collection and control unit.
15.7
Exclusive monitor
The local monitor enables the RAMs to be used for semaphores between processes
running on different masters. The local monitor exclusive granule size is 8 bytes.
A load exclusive transaction on the bus marks a 64-bit memory region as exclusive. A store
exclusive passes the local exclusive monitor check if it accesses the same 64-bit memory
region and returns the exclusive monitor to open access state. If a store exclusive accesses
an address outside the marked 64-bit region, then the store exclusive instruction fails the
exclusive monitor check and the monitor is returned to open access state.
There are multiple exclusive monitors to enable it for multiple masters. The number of
exclusive monitors is controlled by NUM_PROCESSORS.
15.7.1
Support for Exclusive monitor behavior
15.7.1.1
Features
15.7.1.2
•
Support exclusive requests aligned to local monitor concept as specified in
Arm Core
•
Exclusive reservation granularity would be 64 bytes
•
Support one exclusive monitor per processing element
•
Aligned with the implementation as defined in Arm architecture reference manual
ARMv8_A for Exclusive monitor
Functional description
The exclusive monitor supports two states - OPEN and EXCLUSIVE. After Power on Reset,
the state machine remains in OPEN state. Based on the type of operation it transitions to
EXCLUSIVE state. The details of the state machine are shown below.
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Platform RAM controller AXI (PRAMC_AXI)
RM0483
Figure 116. Exclusive monitor state machine
RESET
Locked Read Access to non-marked
Address by same Master
Locked Read Access
(Address is Marked with the ID)
Cond_F
Locked Read Access
Cond_E
OPEN
ACCESS
EXCLUSIVE
ACCESS
Locked Write Access to the
Tagged address
Cond_A
Cond_B
Non-Exclusive Write Access to the
Tagged address by non-tagged
master
Cond_C
Cond_D
Cond_A: Non- Exclusive Write access to tagged address by tagged Master
Cond_B: Non- Exclusive Write access to non-tagged address by tagged Master
Cond_C: Locked Write access to non-tagged address by a non-tagged Master
Cond_D: Locked Read access to non-tagged address by tagged Master
Cond_E: Locked Read access by a non-tagged Master
Cond_F: Non-Exclusive Write access
Some specific points are:
420/2075
•
Any non-exclusive STORE do not generate a no-write condition.
•
WRITE operation is not performed when STREX is not hit in any monitor in the
following cases:
–
Store exclusive to non-tagged address by tagged master when the monitor is in
OPEN state.
–
Store exclusive to non-tagged address by a non-tagged master.
RM0483 Rev 5
RM0483
Non volatile memory platform controller (NVMPC)
16
Non volatile memory platform controller (NVMPC)
16.1
Introduction
16.1.1
Overview
This document describes the features of the embedded non-volatile memory (NVM)
platform controller (NVMPC). The block has these functions:
•
It acts as an interface between the system AXI4 master and the NVM program/erase
controller.
•
It converts the protocols between the system bus and the dedicated NVM array
interface.
The block consists of two modules, implementing an AXI4 read interface and an AXI4 write
interface. The modules can be instantiated independently.
16.1.2
Features
•
•
•
System interface:
–
Support for one 64-bit AXI4 target bus interface for write interface block
–
Support for one 64-bit AXI4 target bus interface for read interface block
–
Support for full burst size/length capability, including support of narrow transfers
for read interface block
–
Support for full burst size/length capability, but narrow transfers for write interface
block are not supported
–
Support for all response type for read channel and write channel
–
Support for separate IPS interface for register programming
NVM interface:
–
Supports configurable size of NVM memory with configurable NVM address bits of
array addresses available
–
Support of programmable access timing (wait-state) allowing use in a wide range
of frequency targets
–
Support of NVM access pipelining (ACP) to improve performance and access
latency reduction
–
Support for NVM array interface of 256-bit read data bus + 64-bit write data bus
Functional safety:
–
Support for protection of address and control signal of AXI4 interface using an e2e
ECC
–
Support for fault detection in address re-encoding check from feedback address
from NVM
–
Support of end-to-end ECC (e2eECC) coverage with the read and write data, the
corresponding ECC code words traverse the entire data path
–
Support for reporting of single, double and multi-bit NVM ECC events on a 64-bit
double word boundary
–
Support for data valid check with the internal counter and input data valid signal
from NVM
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Non volatile memory platform controller (NVMPC)
•
•
RM0483
Security:
–
Support of protection for NVM areas (regions) using PASS_REGIONS set for
NVM read access
–
Support of interrupt flags for the accesses with data collision feature for both nonsecure and secure cores
Selectable features:
–
Support for Configurable (default is 2) Outstanding Address for Read Interface
Block
–
Support of OTA-X1 feature
The NVMPC module supports the following modes of operation:
•
Write transfers, implemented by the AXI4 write interface block
•
Read transfers, implemented by the AXI4 read interface block
Such modes of operation are described in detail in Section 16.8.
The read interface supports single 64-bit AXI4 slave port for Global, Read address and
Read data channels. It has full burst size/length capability, including support of narrow
transfers, and operates as a bridge from the protocol to the custom NVM read protocol
(described in Section 16.8.1.2); the NVM wait state number is configurable and access to
pipelining is supported, with maximum address phase anticipation of one clock cycle
(described in Section 16.6).
One outstanding address is accepted.
The write interface translates 64-bit write accesses from AXI4 master to 64/32bit accesses
to the NVM interface; narrow transfers are not supported by this module and the NVM write
is expected to be performed in a single clock cycle, with no capability of stalling the interface
(described in Section 16.6). Single address is accepted from the master during a burst.
Along with the read and write data, the corresponding ECC codewords traverse the entire
datapath to support end-to-end ECC (e2eECC) coverage (described in Section 16.9).
16.2
Block interface
The block interface is composed by the following protocol interfaces:
•
Memory map and register definitions
•
AXI4 global/read data/read address interface
•
Non-volatile-memory read interface
•
NVMPC interrupt enable
The AXI4 write interface block is composed of the following protocol interfaces:
•
AXI4 write data/write address/write response interface
•
Non-volatile-memory write interface
Global safety features are managed by specific sideband signals, described in Section 16.9.
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Non volatile memory platform controller (NVMPC)
16.3
Memory map and register definitions
16.3.1
Memory map
In the AXI4 read interface an IPS programming model mapped to a standard 16 KB onplatform peripheral slot is implemented. The NVMPC allows access to the programming
model by all system bus masters.
Table 178. NVM controller memory map
Address offset
0x0000
Register
Location
NVM PC configuration register 1 (PFCR1)
0x0004–0x0007
Section 16.3.2.1
Reserved
0x0008
NVM PC configuration register 3 (PFCR3)
Section 16.3.2.2
0x000C
NVM PC Status register (PFSR)
Section 16.3.2.3
0x0010
NVM PC fault latching enable register (FLTENA)
Section 16.3.2.4
0x0014
NVM PC fault forcing register (FLTFRC)
Section 16.3.2.5
0x0018
NVM PC fault status and clear register (FLTSCR)
Section 16.3.2.6
0x001C
NVM PC fault address register (FLTADR)
Section 16.3.2.7
Reserved(1)(2)
0x0020–0x033F
1. Transfer error is not issued at reserved address (such as 0x0300)
2. Additional registers exist to handle the data memory collision avoidance functionality. Refer to the SR5E1x cybersecurity
reference manual.
16.3.2
NVM controller registers
16.3.2.1
NVM PC configuration register 1 (PFCR1)
The configuration register 1 (PFCR1) is used to configure the read operations,
interconnected to the NVM.
Offset 0x0000
R
Access: Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
19
R
APC
W
Reset
0
0
RWSC
0
0
1
0
1
0
17
16
Reserved(1)
W
Reset
18
0
0
0
1
1
0
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
Reserved(1)
0
0
1. Read/write to this field does not return any error.
Figure 117. Platform NVM configuration register 1 (PFCR1)
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RM0483
Table 179. PFCR1 field descriptions
16.3.2.2
Field
Description
15:13
APC
Address Pipeline Control
This field controls the number of cycles that a subsequent NVM read from the
opposite AXI port can be initiated prior to the previous read data being valid.
This field applies to the configuration of Port0 and Port1.
000 Pipelined access to the NVM disabled.
001 A pipelined access can be initiated 1 cycle before the previous data is valid
010 Reserved
011 Reserved
1xx Pipelined access to the NVM is disabled and one wait state is inserted before
a subsequent access can be initiated.
12:8
RWSC
Read Wait State Control
This field controls the number of wait-states to be added to the best-case NVM
array access time for reads. The best-case NVM array access time for reads is
one cycle.
This field must be set to a value corresponding to the operating frequency of the
AXI4 read interface and the actual read access time of the NVM. The required
settings are documented in the device data sheet. Higher operating frequencies
require non-zero settings for this field for proper NVM operation, as computed by
the formula:
NRWSC = floor (Tactime / Taclk)
NVM PC configuration register 3 (PFCR3)
The configuration register 3 (PFCR3) is used to configure the protection, interconnected to
the NVM.
R
Access: Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BAF_DIS
Offset 0x0008
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Figure 118. Platform NVM configuration register 3 (PFCR3)
Table 180. PFCR3 field descriptions
Field
15
BAF_DIS
424/2075
Description
BAF_DIS
This bit is used to prevent the re-execution of the BAF code.
Note: This bit can be written only once and it is cleared after reset.
RM0483 Rev 5
RM0483
Non volatile memory platform controller (NVMPC)
16.3.2.3
NVM PC Status register (PFSR)
The Status Register (PFSR) is used to Sample the status information from NVMC and NVM.
R
Access: Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NVMPCFLHBUSY
Offset 0x000C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Figure 119. NVM PC Status register (PFSR)
Table 181. PFSR field descriptions
Field
0
NVMPCFLHBUSY
16.3.2.4
Description
NVMPCFLHBUSY
This bit reflects the flh busy pin value connected to NVMPC instance.
NVM PC fault latching enable register (FLTENA)
This NVM PC fault enable register (FLTENA) is used to enable or disable the error
forwarding to MEMU or FCCU.
When setting this register, the corresponding bit in the register enables the fault forwarding.
When the bit of the register is cleared, the fault is not forwarded to FCCU or MEMU,
however the FLTSCR latches the fault internally anyway.
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RM0483
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
NVMCDBC
NVMCSBC
NVMDTED
NVMDDBC
NVMDSBC
NVMENCE
NVMCEDC
NVMDEDC
NVMPCENC
NVMPCENSWAP
R
Access: Read/Write
NVMCTED
Offset 0x0010
0
0
0
0
0
1
1
1
0
0
0
1
1
0
1
1
W
Reset
R
W
Reset
Figure 120. Platform NVM fault latching enable register (FLTENA)
Table 182. FLTENA field descriptions
Field
426/2075
Description
10
NVMCTED
NVM Code triple ECC error
9
NVMCDBC
NVM Code double ECC error
8
NVMCSBC
NVM Code single ECC error
7
NVMDTED
NVM Data triple ECC error
Note: DATA fault forwarding is not implemented.
6
NVMDDBC
NVM Data double ECC error
Note: DATA fault forwarding is not implemented.
5
NVMDSBC
NVM Data single ECC error
Note: DATA fault forwarding is not implemented.
4
NVMENCE
NVM Address encoding error
3
NVMCEDC
NVM Code EDC error
2
NVMDEDC
NVM Data EDC error
1
NVMPCENC
NVMPC Address encoding error
0
NVMPCENSWAP
NVMPC SWAP Address error
RM0483 Rev 5
RM0483
Non volatile memory platform controller (NVMPC)
16.3.2.5
NVM PC fault forcing register (FLTFRC)
This NVM PC fault forcing register (FLTFRC) is used to force the error latching in order to
check the error reporting path. When setting this register, the corresponding bit in the
FLTSCR is set and a signal to the fault collector is asserted. The FLTENA masks the error
forced with FLTFRC.
Access: Read/Write(1)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
NVMCDBC
NVMCSBC
NVMDTED
NVMDDBC
NVMDSBC
NVMENCE
NVMCEDC
NVMDEDC
NVMPCENC
NVMPCENSWAP
R
NVMCTED
Offset 0x0014
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
1. Reading back to this register reads 0.
Figure 121. Platform NVM fault forcing register (FLTFRC)
Table 183. FLTFRC field descriptions
Field
Description
10
NVMCTED
NVM Code triple ECC error
9
NVMCDBC
NVM Code double ECC error
8
NVMCSBC
NVM Code single ECC error
7
NVMDTED
NVM Data triple ECC error
6
NVMDDBC
NVM Data double ECC error
5
NVMDSBC
NVM Data single ECC error
4
NVMENCE
NVM Address encoding error
3
NVMCEDC
NVM Code EDC error
2
NVMDEDC
NVM Data EDC error
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Table 183. FLTFRC field descriptions (continued)
Field
16.3.2.6
Description
1
NVMPCENC
NVMPC Address encoding error
0
NVMPCENSWAP
NVMPC SWAP Address error
NVM PC fault status and clear register (FLTSCR)
This NVM PC fault status and clear forcing register (FLTSCR) is used to latch the fault and
error coming from NVM or generated internally by NVMPC. The bit is set when the
corresponding fault is detected or fake fault is injected using FLTFRC register. This latching
is not gated by FLTENA register. The bit can be cleared by write 1 to a bit.
Offset 0x0018
R
Access: Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
NVMCSBC
NVMDTED
NVMDDBC
NVMDSBC
NVMENCE
NVMCEDC
NVMDEDC
NVMPCENC
NVMPCENSWAP
W
Reset
NVMCDBC
R
NVMCTED
W
Reset
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
0
0
0
Figure 122. Platform NVM fault status and clear register (FLTSCR)
Table 184. FLTSCR field descriptions
Field
428/2075
Description
10
NVMCTED
NVM Code triple ECC error
9
NVMCDBC
NVM Code double ECC error
8
NVMCSBC
NVM Code single ECC error
7
NVMDTED
NVM Data triple ECC error
6
NVMDDBC
NVM Data double ECC error
RM0483 Rev 5
RM0483
Non volatile memory platform controller (NVMPC)
Table 184. FLTSCR field descriptions (continued)
Field
16.3.2.7
Description
5
NVMDSBC
NVM Data single ECC error
4
NVMENCE
NVM Address encoding error
3
NVMCEDC
NVM Code EDC error
2
NVMDEDC
NVM Data EDC error
1
NVMPCENC
NVMPC Address encoding error
0
NVMPCENSWAP
NVMPC SWAP Address error
NVM PC fault address register (FLTADR)
This NVM PC fault address register (FLTADR) is used to latch the start address of
transaction where there is fault detected from NVM. Note that this register captures only the
first address of the transaction while the MEMU is notified by the exact address where the
Error is happened in case of multiple errors are detected in a transaction.
Note:
Write to this register does not produce a transfer error.
Offset 0x001C
31
Access: Read-only
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
FADR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
FADR
W
Reset
0
0
0
0
0
0
0
0
0
Figure 123. Platform NVM fault address register (FLTADR)
Table 185. FLTADR field descriptions
Field
31:0
FADR
Description
Fault Address
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16.4
RM0483
AXI4 global/read data/read address interface
On an incoming AXI4 burst request, that is when both ARREADY and ARVALID are high1,
the master request address/controls are latched. During the following clock cycle the read
FSM starts converting the master request into multiple memory read requests; on each
transaction, 64-bit of data are returned to the master on the RDATA[63:0] bus along with
transaction qualifiers.
In order to decouple the memory read flow from the AXI4 master access beats, a FIFO
buffer is implemented in each read interface FSM block. Valid data is notified to the AXI4
master by asserting the RVALID interface signal if FIFO is not empty; the master then
acknowledges data by asserting the RREADY signal, and the FIFO top is sent to the
master.
16.4.1
Operation
16.4.1.1
Read cycles / FIFO hit
A dedicated read FIFO is filled by the data flow from the memory and the burst is stalled
only if the FIFO is full, maximizing the gain given by the access pipelining. On a memory
read, the line is stored in the FIFO. The RVALID signal is high1 when the FIFO is not empty
or when the data is ready from the memory array.
16.4.1.2
Read cycles / hit
Single cycle read responses to the AXI4 are possible with the AXI4 read interface when the
requested read access was previously loaded into one of the page buffers. In these “buffer
hit” cases, read data is returned on the system bus with a zero wait-state response.
16.4.1.3
Read cycles / miss
In the event of a buffer miss, a NVM access is initiated.
On bursts requests issued by the interface allocated master, incoming read data from the
NVM array is stored in the least-recently updated 256-bit page read buffer of the selected
way; concurrently the critical double-word of NVM read data is forwarded onto the system
AXI4 bus.
If the memory access was the direct result of a bus transaction, the corresponding page
buffer is updated and marked as most-recently-used.
If the memory access was the result of a speculative prefetch to the next sequential line, it is
stored into the least-recently-used buffer.
16.5
Non-volatile-memory read interface
The AXI4 read interface read block is tightly interfaced to the embedded non-volatilememory and implements the memory custom protocol.
16.5.1
Operation
A memory read cycle is composed by a single cycle address phase, followed by a data
phase of one or multiple clock cycles. The number of wait states is configurable via the
430/2075
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RM0483
Non volatile memory platform controller (NVMPC)
PFCR1.RWSC register, and it is forwarded to the memory by the ADWS (cfg_adws)
interface bus. Read accesses are terminated under control of the appropriate wait state
settings. Access timing can be varied to account for the operating conditions of the SoC
(frequency, voltage, temperature).
The memory data/errors is registered on the last cycle of the data phase and made available
to the user on the next cycle, while the memory asserts the Data Ready (p0_data_rdy)
signal. A data error is signaled in case of uncorrectable ECC errors by asserting Triple
Error(p0_triple_error). A physical memory address decoding error is signaled by asserting
the Address Encoding Error (p0_aee_error).
When an error response is received, the AXI4 read interface interface returns a slave code
on the RRESP port to the master. A SLVERR code on the RRESP signal is then returned to
the master.
Read cycles from the memory array are initiated by driving a valid access address on Read
Address (p0_addr[23:0]) and asserting Read Strobe Signal (p0_rd_en) for the required
setup (and hold) time before (and after) the rising edge of AXI clock.
The AXI4 read interface then waits for the assertion of the Data Ready from the memory
before sampling the read data on Response Data Bus (p0_rdata[255:0]).
Any error (ECCx, EEE, AEE) signaled by the NVM for a data word, is considered effective at
the time when the AXI4 master consumes the data: during that clock cycle the NVMPC
signals any error, which has been stored in FIFO along with the data.
Data affected by error at source and that never used read by the AXI4 master never triggers
an error by the NVMPC block.
16.5.1.1
Read accesses pipelining
Back-back memory accesses can take advantage of the read access pipelining (APC)
feature, which is implemented to improve the data throughput. Refer to Section 16.8.1.2.1.
16.5.1.2
Read timing coherency
Parallel to the NVM read counter, a read counter is implemented in the AXI4 read interface.
During a read access, the read block counters are used to check the correct assertion of the
data valid signal from the memory, and in case of mismatch an error is reported to the AXI4
master.
If the Data Ready (p0_data_rdy) is not asserted when the internal count ends, the error is
flagged and the SLVERR code is returned by the RRESP bus.
16.5.1.3
Read stall mechanism
The memory protocol supports a stall-while-operation feature.
If required, the memory can operate back-pressure and suspend any read burst in order to
perform a higher priority task. It is in charge of the memory to initiate and release the stall.
The feature is implemented by a handshake, initiated by the assertion of the Read Lock
Request (p0_rlock_req) signal from memory; this signal inhibits any further read to be
issued, while the ongoing access completes. The handshake is completed by the assertion
of the Read Lock Acknowledge (p0_rlock_ack) to the memory. The release of the Read
Lock Request (p0_rlock_req) exits the stall-while-write condition.
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RM0483
In the same clock cycle when the Read Lock Acknowledge (p0_rlock_ack) is asserted, the
Read Penalty (p0_rd_penalty_en) signal is sampled. This allows the NVM memory to
request a read penalty to be added to the programmed RWSC count, in a safe manner that
is without affecting any already initiated read access. If penalty is enabled, the NVMPC
starts adding a latency based the assertion time of Read Penalty (p0_rd_penaly_en) signal
to the ADWS (cfg_adws) information to the NVM.
Penalty is disabled by performing a new handshake, clearing the Read Penalty
(p0_rd_penalty_en) signal.
Figure 124. NVM stall mechanism
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
aclk
FSM
mem_addr_req
g
mem_addr_ack
b
mem_rd_en
arbiter
mem_addr[31:0]
A0
A1
cfg_adws[4:0]
0x02
cfg_apc[2:0]
0x0
rd_counter[4:0]
0x1F
0x02
0x01
0x00
0x1F
0x02
0x01
0x00
0x1F
rd_counter1[4:0]
0x1F
0x02
0x01
0x00
0x1F
0x02
0x01
0x00
0x1F
c
arb_addr_ack
p0_rd_en
memory
p0_addr[31:0]
A1
p0_rdata[255:0]
D0
D1
p0_data_rdy
p0_rlock_req
p0_rlock_ack
16.6
A0
a
e
d
f
AXI4 write data/write address/write response interface
The AXI4 write interface IP implements single AXI4 write interface, for write buffer filling of
the target NVM.
On an incoming AXI4 burst request that is when both AWREADY and AWVALID are high1,
the master request address/controls are latched. The following clock cycle, the write FSM
starts converting the master request into multiple memory write requests; on each
transaction, 64 bits of data are provided by the master on the WDATA[63:0]; the master
asserts WVALID to high1 until data is acknowledged by the slave which asserts WREADY to
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RM0483
Non volatile memory platform controller (NVMPC)
high1. The WSTRB[7:0] signals are used to flag the valid bytes in the data word, one bit per
byte.
16.6.1
Operation
Each AXI4 master write transaction is translated into two successive NVM accesses; the
memory is accessed with no wait states, and no idle cycle is inserted between the write
transactions by the AXI4 write interface.
16.6.1.1
Write cycles
Write cycles to the memory array are initiated by driving a valid access address on Read
Address (p0_addr[23:0]) and asserting Write strobe (p0_wr_en). For write cycles data is
provided on Write Data (p0_wdata[63:0]) and Write Data ECC (p0_wdata_ecc[7:0]). The
size of the write data is indicated by Write 64-bit Strobe; the Write 64-bit Strobe (p0_wr64)
signal is high1 if the WSTRB[7:0] indicates that valid data is present in the low order and
high order 32-bit words in the current Write Data (p0_wdata[63:0] to memory.
Again, the AXI4 write interface drives the address and control information for the required
setup time before the rising edge of AXI Clock (axi_clk), and continues to drive address and
control information on the memory interface bus for the required amount of hold time
beyond the rising edge of AXI Clock (axi_clk).
16.7
Non-volatile-memory write interface
16.7.1
Operation
A single write access to the NVM_P0 interface is always a single cycle operation with no
stall capabilities. The address/data phase is initiated when the Write Strobe (p0_wr_en)
signal is high1, and in the same clock cycle the Address (p0_waddr[23:0]), Write Data
(p0_wdata[63:0]), Write Data Parity (p0_wdata_ecc[7:0]) and Write 64-bits Strobe (p0_wr64)
must be valid.
The NVM write buffer is filled by a sequence of data writes, and it can be accomplished by
transferring data in 64-bit or 32-bit words.
When the Write 64-bit Strobe (p0_wr64) signal is high1, the full Write Data (p0_wdata[63:0])
is accepted by the NVM. When the Write 64-bit Strobe (p0_wr64) signal is low0, only 32 bits
of the full Write Data p0_wdata[63:0]) is accepted by the NVM:
•
The Write Data (p0_wdata[31:0)] if Address (p0_waddr[2]) is low0
•
The Write Data (p0_wdata[63:32]) if Address (p0_waddr[2]) is high1
The Write Data Parity (p0_wdata_ecc[7:0]) is always checked against the full Write Data
(p0_wdata[63:0]), regardless of the Write 64-bit Strobe (p0_wr64) signal level.
16.8
Functional description
The AXI4 read interface block architecture is composed by the following functional subblock:
•
AXI4 read slave controller
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RM0483
The AXI4 write interface block interface is composed by the following functional sub-block:
•
AXI4 write slave controller
Global safety features are managed by specific sideband signals, described in Section 16.9.
16.8.1
AXI4 read slave controller
16.8.1.1
FIFO read buffer operation
The internal FIFO is a three lines by 256-bit buffer; the buffer is capable of stalling the read
FSM on its quasi-full condition, asserted when two lines are filled; on this event, the
remaining line holds the data from the already started memory read.
On any address update by the FSM, the data is searched in the FIFO. In case of FIFO hit,
the memory read is skipped and the address is stepped to the following beat with zero
latency. The FIFO hit condition is computed through combination from the current address
and the most recent memory read address.
The FIFO is filled by any memory read, and the write pointer is incremented by the actual
memory block data size (0x10 or 0x20 bytes).
The FIFO block is in charge of asserting the AXI4 RVALID signal if any valid data is in the
buffer. The assertion of the RREADY signal by the AXI4 master increments the FIFO read
pointer by the actual ARSIZE[2:0] value. When the read pointer equals the write pointer the
RVALID signal is de-asserted.
When the master asserts RREADY to high1, if any FIFO line is valid, the older FIFO line is
returned and discarded, else the memory data line is directly routed to the RDATA[63:0] bus
as soon as it is ready.
In case of incrementing accesses to a code memory area the full Read Data
(p0_rdata[255:0]) is valid; since this information is valid over four successive AXI4 transfers,
the 192 MSb of data is returned from the read FIFO avoiding a new read requests and
minimizing the memory bandwidth usage.
434/2075
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RM0483
Non volatile memory platform controller (NVMPC)
Figure 125. FIFO read buffer operation
0
1
2
3
4
5
6
7
8
9
10
11
12
13
0x18
z
0x20
14
15
aclk
FSM
c_addr[31:0]
A0
c_state[15:0]
A1
A2
A3
sCM1
sBH
sBH
sBH
sSTST
fifo_hit
p
fifo_ready
FIFO
c_fifo_wr_ptr[]
che_addr[31:0]
q
0x00
c_fifo_rd_ptr[]
m
0x20
u
0x00
A0
A1
A2
che_miss_addr[31:0]
w
0x08
y
0x10
A3
A0
arvalid
arready
j
AXI4
rvalid
e
rlast
s
rready
rdata[63:0]
r
D0
t
D0
g
D1
D1
memory
mem_rd_en
mem_addr[31:0]
A0
mem_data_rdy
mem_rdata[255:0]
16.8.1.2
k
D1D0
Memory access arbiter
An arbiter is in charge to serialize the arriving access requests.
The memory acknowledge signal takes into account the actual memory resource availability,
evaluating the internal Address Acknowledge (s_mem_addr_ack) signal as follows (refer to
Section 16.8.1.2.1):
•
If APC is enabled (PFCR1.APC=0x1), memory is available if the Read Counter
(rd_counter) is {0x01,0x00,0x1F}.
•
If APC is disabled and additional wait state is required (PFCR1.APC=0x4), memory is
available if the Read Counter (rd_counter) is {0x1F}.
•
If APC is disabled and no additional wait state is required (PFCR1.APC=0x0), memory
is available if the Read Counter (rd_counter) is {0x00,0x1F}.
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Figure 126. Memory read with pipeline disabled
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
aclk
mem_addr_req
arbiter
mem_addr_ack
cfg_adws[4:0]
0x02
cfg_apc[2:0]
0x0
mem_decode_error
rd_counter[4:0]
0x1F
0x02
0x01
0x00
0x02
0x01
0x00
0x02
0x01
0x00
0x1F
rd_counter1[4:0]
0x1F
0x02
0x01
0x00
0x02
0x01
0x00
0x02
0x01
0x00
0x1F
p0_rd_en
p0_addr[31:0]
A0
p0_data_rdy
p0_rdata[255:0]
A1
A2
k
D0
D1
D2
memory
p0_ecc1_error
p0_ecc2_error
p0_ecc3_error
p0_enc_error
p0_rww_error
p0_rlock_req
p0_rlock_ack
rdtime (analog)
16.8.1.2.1 Read access pipelining
Accesses to the NVM array may be pipelined by driving a subsequent access address and
control signals while waiting for the current access to complete.
NVM access pipelining (ACP) allows for improved performance by reducing the access
latency seen on back-back read cycles targeting the NVM array. This is made possible
because the NVM hard macro internally latches the data after the asynchronous analog
access time Trdtime, and a new read strobe is allowed after this delay; data then passes
through the NVM soft macro multiplexers and ECC decoders, having a combinational delay
of Tdec, and get registered before the Read Data (p0_rdata) pins. The full access time is
such that Trdtime+Tdec<(RWSC+1)Tclk-Tclk,setup. The access pipelining feature triggers a
new read just after Trdtime leveraging the fact that the NVM hard macro internal latches
actually implement a pipeline on data.
Any hit to the read FIFO interrupts the pipelining flow, inserting a non-pipelined read after
the hit.
Address pipelining is enabled by setting the PFCR1.APC register field.
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Non volatile memory platform controller (NVMPC)
Not all combinations of APC (Address Pipeline Control) and RWSC (Read Wait State
Control) settings are recommended or supported. Refer to the device data sheet for
guidance. The integrator is strongly encouraged to verify these settings based on actual
silicon characterization.
Figure 127. Memory read with pipeline enabled
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
aclk
mem_addr_req
arbiter
mem_addr_ack
cfg_adws[4:0]
0x02
cfg_apc[2:0]
0x1
mem_decode_error
rd_counter[4:0]
0x1F 0x02 0x01 0x02 0x01 0x02 0x01
0x1F
rd_counter1[4:0]
p0_rd_en
p0_addr[31:0]
0x1F
0x00 0x1F 0x00 0x1F 0x00
0x1F
h
A0
A1
A2
p0_data_rdy
memory
p0_rdata[255:0]
y
D0
D1
D2
p0_ecc1_error
p0_ecc2_error
p0_ecc3_error
p0_enc_error
p0_rww_error
p0_rlock_req
p0_rlock_ack
rdtime
sout[255:0]
j
t
D0
D1
D2
Tdec
dout[255:0]
k
D0
D1
D2
16.8.1.2.2 AXI4 read interface memory map
The read interface decoding scheme is controlled by a parameter, which selects the NVM
port number. Implemented port numbers are 0 to 5; depending on the physical memory port
to be controlled; each instance of the read NVMPC implements a subset of the full read
address map.
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Any transfer issuing an unmapped address returns dummy data (all bits being ‘0’), along
with a DECERR AXI4 slave response.
The decoder blocks take in input the system address, and return the memory local address
and the Decode Error (mem_decoder_error) signal, asserted if the input address does not
lie inside the controller address space.
For security purposes (refer to Section 16.10), the block has the input
cfg_region_lock[19:0], and operates a comparison of that signal to the region currently
accessed, based on a static hard-coded decoding table. In case of accesses to a protected
region, the Protect Error (mem_protection_error) signal is asserted to the requesting block.
16.8.1.2.3 AXI4 write interface memory map
The write interface implements the full decoding table.
Different AXI4 address maps are allowed for write and read; address ranges mapped to the
‘Kite NVM' read-only interface can require different mapping for write.
16.8.2
AXI4 write slave controller
16.8.2.1
FIFO write buffer operation
The write buffer is a single 128-bit word storage. On an AXI4 write beat, the data is stored
into the buffer, and transferred to the NVM_P0.
16.9
Safety
16.9.1
End2End ECC
Dedicated logic blocks are implemented to protect the data and control path from the AXI4
interface and towards it.
16.9.1.1
NVM data E2E ECC
The AXI4 read interface does not alter the data and parity from the NVM_P0. It only blindly
routes the information from the memory to the AXI4 master.
The NVM must implement the same H-matrix as the AXI4 master.
The NVM uses DECTED and it includes a logic to transform from Kite SECDED to DECTED
and use internally, while before giving back data to NVMC, the NVM transforms from
TEDSEC to Kite SECDED.
No ECC encoder/decoder is implemented by the NVMPC block for the end-to-end data
path. Safety relies on the matching of the NVM and Arm core ECC polynomials. The
NVMPC only routes the ECC parity word along with the data.
16.9.2
Error management
The NVMPC block collects and routes data/address errors which could be internally
detected or signaled by the NVM block.
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Non volatile memory platform controller (NVMPC)
The FLTSCR/FLTADR registers report the error status, and give the capability to clear the
error status. Any error is latched in the FLTSCR and signaled by a level signal on the
NVMPC interface.
Error signaling can be selectively enabled and disabled by the FLTENA register.
Fake errors can be forced by the FLTFRC register.
16.9.2.1
NVMPC address re-encoding error
On every read request to the NVM_P0, the pre-decoding SoC address is compared to the
address computed by applying a dedicated inverse encoding function to the Address
(p0_addr) output.
If these two values do not match an error is reported (high1 active signal) and the error is
latched in the FLTSCR. An OKAY response is sent to the AXI4 master. The actual data
given by NVM is returned to the master, along with OKAY response.
16.9.2.2
NVM data parity errors
The NVMPC collects the error information related to a data word returned by the NVM.
Data parity errors (TED/DEC/SEC) are stored in the FIFO and triggered when the master
actually consumes the data.
SLVERR is generated for uncorrectable ECC Error found in Code region. The Data Region
uncorrectable Error does not translate to SLVERR. The FLTEN only enables/disables the
reporting to MEMU. For uncorrectable data Error, there is fixed Error response
data({0xE7F000F0_0xE7F000F0_0xE7F000F0_0xE7F000F0}) and Response data code of
0x4747 is returned.
The NVMPC, based on its embedded address decoding table, generates dedicated signals
for data/code errors starting from the collective signal returned by the NVM.
•
Single Bit Parity Error (p0_ecc1_error): memu_ecc11_single_error (CODE) and
memu_ecc10_single_error (DATA).
•
Double Bit Parity Error (p0_ecc2_error): memu_ecc11_double_error (CODE) and
memu_ecc10_double_error (DATA).
•
Triple Bit Parity Error (p0_ecc3_error): memu_ecc11_multi_error (CODE) and
memu_ecc10_multi_error (DATA).
The FLT* registers have dedicated bits for NVM data/code parity errors.
16.9.2.3
NVM Read-While-Write error
The NVMPC collects the error information related to a data word returned by the NVM.
Read-While-Write Error (RWE) is stored in the FIFO and triggered when the master actually
consumes the data.
The error is managed by returning a SLVERR to the AXI4 master and the returned data from
NVM is send back to master.
16.9.2.4
NVM address re-encoding
The NVMPC collects the error information related to a data word returned by the NVM.
Address Encoding Error (AEE) is triggered as soon as it is signaled by the NVM.
The FLT* registers have dedicated bits for NVM AEE error.
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In case of address encoding error, the Master is given back OKAY response with the data
from NVM.
16.9.2.4.1 ECC after ECC error
The NVMPC collects the error information related to a data word returned by the NVM.
ECC after ECC Error (EDC) is triggered as soon as it is signaled by the NVM.
All FLT registers have dedicated bits for NVM EDC error. In case of ECC after ECC error,
the Master is given back OKAY response with the data from NVM.
16.9.2.4.2 OTA-X1 SWAP Error
The NVMPC detects the OTA-X1 swapping using two swap signals along with ota_enable. If
there is ota_enabled asserted while the swap bits are not equal, the NVMPC generates the
OTA-X1 SWAP Error to FCCU. There is no specific response to Master for this Error.
The FLT* registers have dedicated bits for OTA-X1 SWAP Error.
Additionally, OTA-X1 SWAP alarm is asserted on access to NVM system address which is
not remapped for OTA (for example, mirrored NVM system address).
16.10
Security
16.10.1
Read NVM access protection
A selective protection on a predefined set of NVM areas (regions) is implemented in the
NVMPC.
The NVM blocks allocation to each of the PASS_REGIONS region is hard-coded and
embedded in the NVMPC design.
During any NVM read, the region number is looked-up, and it is compared to the information
sent by the cfg_region_lock[31:0] interface bus signal.
If the region is protected (cfg_region_lock bit line is high1) the read is not done to the NVM
and ALL0 data is returned to the master, along with SLVERR response.
16.10.2
Data flash management
RWW partition 3 of NVM memory array 0 (as shown in Figure 129) hosts sectors for both
Host EEPROM emulation (Host Data Flash) and HSM EEPROM emulation (HSM Secure
Data Flash).
This setup can lead to potential critical system behavior (RWW exceptions) in the following
cases:
•
Read request on HSM Secure Data Flash while Host Data Flash is under modifications
•
Read request on Host Data Flash while HSM Data Secure Flash is under modifications
In case, Host or HSM application requires to access (read) its own data, while a sector of
the same partition 3 is under modification by the other master, the SW must be written
taking care of avoiding contentions (RWW exceptions) and Host and HSM application SW
cannot be developed in an independent way.
An enhanced HW feature, called “HSM vs Host Data Collision Avoidance”, is available in
order to manage the above access contentions in a transparent way for SW.
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Non volatile memory platform controller (NVMPC)
For details about the way to enable and use this new HW feature, refer to the cybersecurity
reference manual.
16.11
Over The Air (OTA-X1) support
16.11.1
Overview
The OTA feature can be enabled by the customer through a bit of Global System
Configuration DCF.
The OTA feature is implemented for a portion of the non-HSM Code NVM sectors only, no
HSM and NVM Data sectors can be updated via OTA. Refer to the NVM memory map in the
Memory Map chapter for details on the organization of the NVM sectors. The following table
shows the partitions and OTA contexts that can be swapped when OTA feature is enabled.
Table 186. OTA context mapping
Context
RWW
A
1, 2
B
2, 1
The image programming can be done by any core. It is possible to program a new SW
image into the NVM while the application is still running. Once activated, the new SW image
is visible at the same addresses as the old one.
16.11.2
Architecture
The product NVM can be organized in two different ways, depending on bit OTA_EN of the
Global System Configuration DCF. When the OTA functionality is disabled, the NVM
addresses are fixed in HW: no dynamic swap of any NVM region is possible.
When the OTA functionality is enabled, the NVM is divided into 3 regions:
•
A common region, which can be updated only in the garage (that is using some specific
tools).
•
Two OTA contexts, which can be swapped to enable one or the other software images.
The three regions are seen by the MCU masters at different address spaces, as shown in
Figure 128.
Note that whereas the OTA contexts swap for a read operation (that is, the active context is
always seen at address “1”), they do not swap for a write operation, that is, the non-active
context, where the new image is going to be programmed, is seen at address “1” or “2,
depending on which is the active context.
The reason for this is that the NVM identifies the sector during erase with a combination of
bits in a register and write address: because of this it is not possible to erase a sector
belonging to context A passing an address within region “2”.
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Figure 128. OTA regions address space
Address
READ
Swap = 0
Swap = 1
0
Common
Common
1
Context A
Context B
2
Context B
Context A
Address
WRITE
16.11.2.1
Swap = 0
Swap = 1
0
Common
Common
1
Context A
Context A
2
Context B
Context B
Functionality
The OTA feature is split in 3 phases:
1.
Programming the new image
2.
Programming the piece of information that identifies which is the active context
3.
Enabling the swap
The following sections describe each of these phases in detail.
16.11.2.1.1 New image programming
Note:
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The section refers to the case when an update of an existing SW is done. The case of the
very first SW programming at factory is detailed later on.
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Non volatile memory platform controller (NVMPC)
Starting from the situation of an existing SW already programmed in the active OTA context,
the new image is always programmed in the no-active context.
The SW doing this operation knows in which address region is the non-active context
programmed.
In order to pass this piece of information to the SW, a register is implemented in the SSCM:
the SSCM reports into this register the logical address of the non-active context, so that the
SW can use it to program the new image.
16.11.2.1.2 OTA context swap programming
The piece of information that characterizes which is the active context is written in a UTEST
NVM sector.
The information is written in sequential order, in slots of 16 bytes starting from the address
0x1FF8_3800.
The space allocated to store the signature of the active context inside UTEST is 2 Kbyte,
allowing to have 127 updates. The data programmed in each slot is irrelevant and can be
user-defined.
It is mandatory that the last slot of the sector is never programmed.
16.11.2.1.3 OTA context swap enabling
After the new OTA image and the related signature have been programmed, the new image
becomes the active one, where the SW executes the code from. The process of enabling of
the new active OTA context is done only upon a destructive reset. During this phase, as
explained later on, the OTA signature is looked up and the piece of information indicates
which OTA context is active and is latched.
A long functional reset does not change the OTA context, which remains fixed to the value
latched during the last destructive reset. Nevertheless, upon a functional reset the checks of
the signature integrity are still executed.
A short functional reset has no relevance from OTA point of view: nothing is read from the
NVM<var> and the latched outcome (that is which OTA is active) is preserved.
The IP dedicated to decode the OTA signature is the SSCM, which is active during the reset
phase.
The SSCM does the following operations:
1.
Evaluate whether the OTA feature is enabled or not (as reported by a bit of the Global
System Configuration DCF)
2.
If the OTA feature is enabled:
3.
a)
Read UTEST space reserved for signature storage and determine which context
is the active one.
b)
Drive the signals to the SOC indicating which OTA context is the active one.
If the OTA feature is not enabled:
a)
Drive the signals to the SOC indicating the context A as the active one.
16.11.2.1.4 Signature reading and decoding
The signature slot can contain any user-defined data.
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From the SSCM point of view, it is only important to detect that something has been
programmed in a signature slot, in order to distinguish between programmed or notprogrammed.
The “goal” of the SCCM is to determine which is the active context and pass this piece of
information to the SOC.
The information is sent to the SOC in the form of two sideband signals, which are generated
by two set of triple-voted flip-flops, called TVF1 and TVF2.
If the OTA is disabled, no signature is read and the SSCM defaults to the Context A as the
active context.
If OTA is enabled, following a destructive reset, the SSCM linearly scans the signature
portion within the UTEST sector till it finds the latest programmed slot. Note that it is
mandatory that the last slot of the sector is always left non-programmed. A counter, which
starts from 0, increases for every slot recognized as programmed. Once the last
programmed slot is found, the SSCM checks the counter value: if it is an even number, then
context A is selected; if it is an odd number, then context B is selected. If the counter is 0, it
means that no OTA has been done yet and the NVM still contains the original code
programmed by the customers during their production phase. In this case, the context A is
activated. In addition, the SSCM saves:
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•
The address of the last programmed signature slot in Section 19.2.1.5: OTA Signature
Address Location register (OSAL).
•
The identifier of the non active partition in Section 19.2.1.6: Non Active Context Logical
Address register (NACLA).
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Embedded flash memory
17
Embedded flash memory
17.1
Introduction
The flash memory module serves as electrically programmable and erasable nonvolatile
memory, for instructions and data storage.
The flash memory module is a nonvolatile, solid-state silicon memory device consisting of
blocks of single transistor storage elements, an electrical means for selectively adding
(programming) and removing (erasing) charge from these elements, and a means of
selectively sensing (reading) the charge stored in these elements.
The flash memory module has two functional units:
17.1.1
•
The flash core: it is composed of a common high voltage HV block and a flash array
which can contain one or more flash partitions. Each flash partition is composed of
arrayed nonvolatile storage elements, sense amplifiers, row decoders and column
decoders. The arrayed storage elements in the flash partitions are subdivided into
physically separate units referred to as blocks.
•
The memory interface: it contains the registers and logic which control the operation of
the flash core and contains two main ports: the Array Interface and the Registers
Interface. The memory interface is also the interface between the flash memory
module and a Bus Interface Unit (BIU) and contains the ECC and redundancy logic.
Overview
The 2208 KB flash memory module contains four array partitions. Read-While-Write
operations are only possible for separate partitions, meaning fetching/reading from one (or
more) partition(s) while a program/erase operation is active on another partition. Each
module counts as an RWW partition.
EEPROM emulation is managed as 4 × 16 KB blocks in one partitions, referred to as Data
flash.
HSM EEPROM emulation is managed as 2 × 16 KB blocks in one partition, referred to as
HSM Data flash.
The Modify operations are managed by an embedded flash program/erase controller
(FPEC). Commands to the FPEC are delivered through a User Registers interface.
The Read Data bus is 256-wide, while the flash registers are on a separate, 32-bit bus.
The high voltages needed for Program and Erase operations are internally generated and
are common for the four partitions.
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Figure 129. Flash memory module structure
Flash memory module
Flash core
Flash array RWR0:
3 RWW partitions
Code Flash
192 KB
Partition 0
— — — — — — — — — — —
Code Flash
960 KB
Partition 1
HV generator
-
— — — — — — — — — — —
Data Flash
96 KB
Partition 3
— — — — — —
Code Flash
960 KB
Partition 2
— — — — —
-
-
Flash array RWR1:
1 RWW partition(s)
Array
interface
Array
interface
Registers
interface
Flash
Program/Erase
Controller
Flash
registers
Memory interface
Flash
Controller
Flash
Controller
IPS bus
The flash memory module is designed for use in embedded applications which require high
density non-volatile memories with high-speed Read access.
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Embedded flash memory
The flash array is addressable:
•
For programs in data partition: by word (32 bits) or doubleword (64 bits). ECC
granularity is 64 bits.
•
For programs in code partition: by word (32 bits) or doubleword (64 bits). ECC
granularity is 128 bits.
•
For reading code partitions – by page (256 bits).
•
For reading data partitions – by half-page (128 bits).
Multiple-word or doubleword writes to the flash memory may be performed to fill the
program page buffer (256 bits), enabling page programming (256 bits – requiring 4
doubleword writes) and quad-page programming (1024 bits – requiring 16 doubleword
writes). Code flash memory reads always return 256, although Read buffering may be
performed by the Bus Interface Unit (BIU). The address for each word retrieved within a
page differs from the other addresses in the page by address bits (4:2).
Data flash memory reads always return 128 bits, or two consecutive doublewords of
information. The address for each word retrieved within a doubleword differs from the other
addresses by address bits (3:2).
The flash memory module supports fault tolerance through Error Correction Code (ECC)
and error detection. The ECC implemented within the Data flash memory module corrects
up to double bit failures and detects triple bit failures (as uncorrectable).The ECC
implemented within the Code flash memory module corrects single bit failures and detects
double bit failures (as uncorrectable).
The flash memory module uses an embedded hardware algorithm implemented in the flash
program/erase controller to program and erase the flash partitions.
Control logic that works with the software block-enables and software lock mechanisms are
included in the embedded hardware algorithm to guard against accidental program/erase.
The hardware algorithm performs the necessary steps to ensure that the storage elements
are programmed and erased with sufficient margin to guarantee data integrity and reliability.
A programmed bit in the flash array reads as logic level ‘0’ (or low). An erased bit in the flash
array reads as logic level ‘1’ (or high).
Programming and erasing of the flash array requires multiple system clock cycles to
complete.
The program and erase sequences may be suspended or aborted.
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17.1.2
17.1.3
RM0483
Features
•
30 ns code/data array access time
•
Code Partition High Read parallelism: 256 bits
•
Data Partition Read parallelism: 128 bits
•
Error Correction Code (Double Error Correction-Triple Error Detection) to enhance data
integrity
•
Data Partition Doubleword program granularity: 64 bits
•
Erase with fast erase time at factory
•
Blocks one time programmable (OTP) marking
•
Read-While-Modify capability when the accesses are to different partitions
•
Erase/Program Suspend
•
Programming during Erase-Suspend
•
Software programmable program/erase protection to avoid unwanted writings
•
Temperature range (-40 °C to 150 junction)
•
UTEST mode (user-accessible Test modes)
•
Alternate interface provided for program and erase operations to dedicated master as
private access to blocks
•
Independent and Parallel Read access to specific code flash partitions, namely ReadWhile-Read supported.
•
Critical flops, which may affect flash content, are triple-voted for safety application.
Modes of operation
The flash memory module supports the following modes of operation:
•
Reset: the flash memory module initializes when the reset is deasserted.
•
Read mode: the flash memory module accepts Read accesses to the array.
•
Modify mode: it is possible to read and write registers, Interlock Write the memory
array, program the memory array, and erase the memory array. Program and Erase
operations are initiated by performing array and register writes, and controlled by an
internal state machine. Program/Erase operations or User Test modes (Margin Read or
Array Integrity Check) are considered Main Modify modes.
•
Read-While-Write: The flash memory module accepts Read accesses to array
partitions that are not in Modify mode.
•
Read-While-Read: The flash memory module accepts parallel Read accesses in
separate Read-While-Read partitions.
•
Alternate Modify mode: blocks in LOW and MID space could be assigned to Alternate
interface, though which it is possible to read and write registers, Interlock Write the
assigned memory array, program the assigned memory array, and erase the assigned
memory array. Program and Erase operations are initiated by performing array and
alternate register writes, and are controlled by the same internal state machine as in
Main. Alternate Program/Erase operations are considered Alternate Modify modes.
Alternate Modify modes operate concurrently to Main ones and, although functionally
independent, timing can be mutually influenced.
Such modes of operation are described in detail in Section 17.4: Functional description.
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17.2
Embedded flash memory
Flash memory map and description
The flash memory module block subdivision also facilitates independent Erase and Program
protection. A software mechanism is provided to independently lock and unlock each block
in Low, Mid, High and Data address spaces against program and erase.
17.2.1
Flash array memory map
17.2.1.1
Code flash
Partition 0 accounts for 192 KB of the total flash memory and is divided in 5 user blocks for
code storage.
Partition 0 also contains a reserved block named TestFlash in which some One Time
Programmable (OTP) user data is stored.
The sectorization of partition 0 of the flash memory is shown in Table 187.
Table 187. Flash memory partition 0 memory map
Block
Addresses
Size
Address
space
LOCK
SEL
B0F0
0x1800_0000 to 0x1800_7FFF
32 KB
Low
LOWLOCK[7]
LOWSEL[7]
B0F1
0x1800_8000 to 0x1801_7FFF
64 KB
Low
LOWLOCK[8]
LOWSEL[8]
B0F2
0x1801_8000 to 0x1802_7FFF
64 KB
Low
LOWLOCK[9]
LOWSEL[9]
B0F3-UT
0x1FF8_0000 to 0x1FF8_3FFF
16 KB
Low
TSLOCK
—
B0F3-BF
0x1FF0_0000 to 0x1FF0_3FFF
16 KB
Low
LOWLOCK[0]
—
B0F3-TF
—
16 KB
Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
The sectorization of partition 1 of the flash memory is shown in Table 188:
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RM0483
Table 188. flash memory partition 1 memory map
Block
Addresses
Size
Address
space
LOCK
SEL
B1F0
0x0800_0000 to 0x0800_FFFF
64 KB
Low
LOWLOCK[1]
LOWSEL[1]
B1F1
0x0801_0000 to 0x0801_FFFF
64 KB
Low
LOWLOCK[2]
LOWSEL[2]
B1F2
0x0802_0000 to 0x0802_FFFF
64 KB
Low
LOWLOCK[3]
LOWSEL[3]
B1F3
0x0803_0000 to 0x0806_FFFF
256 KB
256K
A256KLOCK[0]
A256KSEL[0]
B1F4
0x0807_0000 to 0x080A_FFFF
256 KB
256K
A256KLOCK[1]
A256KSEL[1]
B1F5
0x080B_0000 to 0x080E_FFFF
256 KB
256K
A256KLOCK[2]
A256KSEL[2]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
The sectorization of partition 2 of the flash memory is listed below.
Table 189. Flash memory partition 2 memory map
Block
Addresses
Size
Address
space
LOCK
SEL
B2F0
0x080F_0000 to 0x080F_FFFF
64 KB
Low
LOWLOCK[4]
LOWSEL[4]
B2F1
0x0810_0000 to 0x0810_FFFF
64 KB
Low
LOWLOCK[5]
LOWSEL[5]
B2F2
0x0811_0000 to 0x0811_FFFF
64 KB
Low
LOWLOCK[6]
LOWSEL[6]
B2F3
0x0812_0000 to 0x0815_FFFF
256 KB
256K
A256KLOCK[3]
A256KSEL[3]
B2F4
0x0816_0000 to 0x0819_FFFF
256 KB
256K
A256KLOCK[4]
A256KSEL[4]
B2F5
0x081A_0000 to 0x081D_FFFF
256 KB
256K
A256KLOCK[5]
A256KSEL[5]
—
—
—
—
—
—
—
—
—
—
—
—
17.2.1.2
Data flash
Data flash is allocated in partition 3 of the flash memory as 4 × 16 KB blocks destined for
data storage.
The data flash sectorization of the flash memory module is listed below.
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Embedded flash memory
Table 190. Flash memory EEPROM data partition 3 memory map
Block
Addresses
Size
Address
space
LOCK
SEL
D0_00
0x08F0_0000 to 0x08F0_3FFF
16 KB
High
HIGHLOCK[0]
HIGHSEL[0]
D0_01
0x08F0_4000 to 0x08F0_7FFF
16 KB
High
HIGHLOCK[1]
HIGHSEL[1]
D0_02
0x08F0_8000 to 0x08F0_BFFF
16 KB
High
HIGHLOCK[2]
HIGHSEL[2]
D0_03
0x08F0_C000 to 0x08F0_FFFF
16 KB
High
HIGHLOCK[3]
HIGHSEL[3]
HSM Data Flash is allocated in partition 3 and is composed by 2 x 16 KB blocks. The HSM
Data Flash sectorization is listed below.
Table 191. Flash memory HSM EEPROM data partition 3 memory map
Block
Addresses
Size
Address
space
LOCK
SEL
D0_04
0x18F0_0000 to 0x18F0_3FFF
16 KB
Mid
MIDLOCK[0]
MIDSEL[0]
D0_05
0x18F0_4000 to 0x18F0_7FFF
16 KB
Mid
MIDLOCK[1]
MIDSEL[1]
17.2.1.3
TestFlash and UTEST block memory map
The TestFlash physical block contains OTP user sections: UTEST (16 KB) and BAF (16 KB)
plus a Manufacturer Reserved Test Flash Area (16 KB) which is referred to as TestFlash
logical block.
The TestFlash logical block exists outside the normal address space. The UTEST block is
programmed and read independently of the other blocks. UTEST is included to support
systems which require nonvolatile memory for security and to store system initialization
information.
The usage of reserved UTEST block is detailed in Table 192.
Table 192. UTEST block memory map
Address Offset
Description
Size
Access
UTEST
0x0000
Reserved
32 bytes
R
0x0020
Factory Erase Diary Location
16 bytes
R/P
0x0030
Test Mode Disable Override Passcode
16 bytes
R/P
0x0040
Test Mode Disable Seal
16 bytes
R/P
0x0050
Test Mode Disable Group A
16 bytes
R/P
0x0060
Test Mode Disable Group B
16 bytes
R/P
0x00A0
Unique chip identifier (UID)
32 bytes
R
0x00C0
Reserved
16 bytes
R
0x00D0
Reserved
48 bytes
R
0x0100
Password to enable the Flash Test Mode when in FA
32 bytes
R
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Table 192. UTEST block memory map (continued)
Address Offset
Description
Size
Access
0x0120
JTAG Password
32 bytes
R/P
0x0140(1)
PASS password - Group 0
32 bytes
R/P
0x0160
PASS password - Group 1
32 bytes
R/P
0x0180
PASS password - Group 2
32 bytes
R/P
0x01A0
PASS password - Group 3
32 bytes
R/P
0x01C0
Reserved
32 bytes
R/P
0x01E0
Life Cycle slot 0 - ST Production
32 bytes
R/P
0x0200
Life Cycle slot 1 - Customer Delivery
32 bytes
R/P
0x0220
Life Cycle slot 2 - OEM Production
32 bytes
R/P
0x0240
Life Cycle slot 3 - In Field
32 bytes
R/P
0x0260
Life Cycle slot 4 - Failure Analysis
32 bytes
R/P
0x0280
Customer Single Bit Correction area
32 bytes
R
0x02A0
Reserved
32 bytes
R
0x02C0
Customer Uncorrectable Bit Detection area
32 bytes
R
0x02E0
Customer Programmable Detection Area
32 bytes
R
0x0300
DCF Start record
8 bytes
R/P
0x0308
Reserved
144 bytes
R/P
0x0398
UTEST DCF Records
3176 bytes
R/P
0x1000
BAF Soft DCF Records
1024 bytes
R/P
0x1400
Customer OTP data
9216 bytes
R/P
0x3800
OTA Signature area
2048 bytes
R/P
1. The offset 0x140 contains the least significant 32-bit of the PASS password - Group 0. The offset 0x15C
contains the most significant 32-bit of the PASS password - Group 0. The same endianess also applies to
the other groups of the PASS password.
UTEST block supports RWW, and is grouped with the Code Flash in partition 0.
Programming of any section of the UTEST block is subject to similar restrictions as the array
in terms of how ECC is calculated. Only one program is allowed per 64-bit ECC segment.
The UTEST nonvolatile memory section is OTP and erase is not allowed. User mode
programming of the UTEST section is enabled only when MCR.PEAS is high. The UTEST
section is divided into a Flexible area where content is managed at System level, and a
Reserved area where addresses are pre-allocated for storing certain content. The UTEST
section may be locked and unlocked against programming via LOCK0.TSLOCK in
conjunction with the relative sideband (System specific). For locking purposes, UTEST is
treated as a stand-alone block even though it resides in the TestFlash block. UTEST access
(both Read and Modify) is disabled in Test mode once the Test Mode Disable Seal
password is written. Test Flash logical block gets also protected by the Test Mode Disable
Seal.
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Embedded flash memory
The UTEST section is also set as OPP once the Test Mode Disable Seal password is
written, thus programming is only allowed on virgin 64-bit locations.
The other area of the TestFlash physical block is BAF and may be used for defined functions
(possibly to store boot code, other configuration words or factory process codes). This
nonvolatile memory area is OTP and cannot be erased once programmed.
Although the BAF (like UTEST) is part of the TestFlash physical block, OPP functionality is
managed through sideband (SoC specific). Program protection is also managed through
sideband (SoC specific), in conjunction with LOCK0.LOWLOCK. For locking and OPP
purposes, BAF is treated as a stand-alone block.
When the UTEST section (via the entire TestFlash block) is protected via Test Mode Disable
Seal, the BAF is also protected from any high voltage operation which may alter the content.
Access to BAF is read only for FPEC in the event that the test interface is open (Failure
Analysis scenario).
Customer Detection and Correction area in UTEST are related to error injection for safety
reaction for Code Memory only.
17.2.1.4
RWR1_UTEST virtual block memory map
RWR1_UTEST virtual block is an area allocated for the purpose of injecting safety relevant
error and to test the reaction path. This task is accomplished in the primary Read-WhileRead partition 0 directly within UTEST memory map. RWR1_UTEST virtual block is
assigned for the second, parallel, Read-While-Read partition 1 (see Section 17.4.2.1: Read
While Read).
Warning:
Customer Programmable Detection Area for RWR1_UTEST
virtual block is qualified by UT0.CPA and UT0.CPE. UT0.CPR
has no effect.
Table 193. RWR1_UTEST virtual block memory map
Address Offset
Description
Size
Access
RWR1_UTEST (Base Address 0x1FFBC000)
17.3
0x0000
Reserved
640 bytes
0x0280
Customer Single Bit Correction area
32 bytes
R
0x02A0
Reserved
32 bytes
R
0x02C0
Customer Uncorrectable Bit Detection area
32 bytes
R
0x02E0
Customer Programmable Detection Area
32 bytes
R
Register memory maps and descriptions
In this section some nonvolatile registers are described as well as the usual volatile
registers. Note that such entities are not Flip-Flops, but Test Flash block locations with a
specific purpose.
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During the flash memory initialization phase, the FPEC reads these nonvolatile registers
and updates their corresponding volatile registers. When the FPEC detects ECC
uncorrectable errors in these special locations, it behaves in the following way:
17.3.1
•
In the case of failing system locations (configurations, redundancy, EmbAlgo firmware),
the initialization phase is interrupted and a Fatal Error is flagged.
•
In the case of failing coherency checks, the volatile registers are filled with ‘1’s and the
Flash Initialization ends setting MCR.RE.
Register memory maps
This section presents the memory mapping of all the flash memory registers.
17.3.1.1
User register memory maps
The Flash User registers represent the communication interface between the host CPU and
the FPEC.
Some register bits (command bits) are Read/Write for the CPU and read only for the FPEC.
Other register bits (status bits) are Read/Write for the FPEC and read only for the CPU.
The Flash User registers mapping is shown in Table 194.
Table 194. Flash user registers memory map
Address offset
Description
Location
0x0000
Module Configuration register (MCR)
Section 17.3.2.1
0x0004
Alternate Module Configuration register (MCRA)
Section 17.3.2.2
0x0008
Extended Module Configuration register (MCRE)
Section 17.3.2.3
0x000C–0x000F
Reserved
0x0010
Locking 0 register (LOCK0)
Section 17.3.2.4
0x0014
Locking 1 register (LOCK1)
Section 17.3.2.5
0x0018
Locking 2 register (LOCK2)
Section 17.3.2.6
0x001C
Locking 3 register (LOCK3)
Section 17.3.2.7
0x0020–0x0027
Reserved
0x0028
Alternate Locking 0 register (LOCK0A)
Section 17.3.2.8
0x002C
Alternate Locking 1 register (LOCK1A)
Section 17.3.2.9
0x0038
Select 0 register (SEL0)
Section 17.3.2.10
0x003C
Select 1 register (SEL1)
Section 17.3.2.11
0x0040
Select 2 register (SEL2)
Section 17.3.2.12
0x0044
Select 3 register (SEL3)
Section 17.3.2.13
0x0048
Module Configuration register 2 (MCR2)
Section 17.3.2.14
0x004C
Program Address register (PAR)
Section 17.3.2.15
0x0050
Address register (ADR)
Section 17.3.2.16
0x0054
User Test register 0 (UT0)
Section 17.3.2.17
0x0058
User Multiple Input Signature register 0 (UM0)
Section 17.3.2.18.1
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Embedded flash memory
Table 194. Flash user registers memory map (continued)
Address offset
Description
Location
0x005C
User Multiple Input Signature register 1 (UM1)
Section 17.3.2.18.2
0x0060
User Multiple Input Signature register 2 (UM2)
Section 17.3.2.18.3
0x0064
User Multiple Input Signature register 3 (UM3)
Section 17.3.2.18.4
0x0068
User Multiple Input Signature register 4 (UM4)
Section 17.3.2.18.5
0x006C
User Multiple Input Signature register 5 (UM5)
Section 17.3.2.18.6
0x0070
User Multiple Input Signature register 6 (UM6)
Section 17.3.2.18.7
0x0074
User Multiple Input Signature register 7 (UM7)
Section 17.3.2.18.8
0x0078
User Multiple Input Signature register 8 (UM8)
Section 17.3.2.18.9
0x007C
User Multiple Input Signature register 9 (UM9)
Section 17.3.2.18.10
0x0080
Over Program Protection 0 (OPP0)
Section 17.3.2.19.1
0x0084
Over Program Protection 1 (OPP1)
Section 17.3.2.19.2
0x0088
Over Program Protection 2 (OPP2)
Section 17.3.2.19.3
0x008C
Over Program Protection 3 (OPP3)
Section 17.3.2.19.4
0x0090
Test Mode Disable Password Check (TMD)
Section 17.3.2.20
0x0094
HSM ALT-SEL 0 register (ALTSEL0)
Section 17.3.2.21.1
0x0098
HSM ALT-SEL 1 register (ALTSEL1)
Section 17.3.2.21.2
0x0100
Erase Lock Protection 0 (ELOCK0)
Section 17.3.2.22.1
0x0104
Erase Lock Protection 1 (ELOCK1)
Section 17.3.2.22.2
0x0108
Erase Lock Protection 2 (ELOCK2)
Section 17.3.2.22.3
0x010C
Erase Lock Protection 3 (ELOCK3)
Section 17.3.2.22.4
0x0110
Program Lock Protection 0 (PLOCK0)
Section 17.3.2.23.1
0x0114
Program Lock Protection 1 (PLOCK1)
Section 17.3.2.23.2
0x0118
Program Lock Protection 2 (PLOCK2)
Section 17.3.2.23.3
0x011C
Program Lock Protection 3 (PLOCK3)
Section 17.3.2.23.4
0x0134
Parallel Address register (ADR2)
Section 17.3.2.24
17.3.2
User register descriptions
This section consists of user register descriptions in address order.
17.3.2.1
Module Configuration register (MCR)
The Module Configuration register is used to enable and monitor all the Modify operations of
the flash memory module and to monitor the Read operations of Read-While-Read Interface
0.
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RM0483
LSW
PEP
PES
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
W w1c w1c
w1c
ESUS
EHV
16
ERS
17
PSUS
0
18
PGM
0
19
FERS
0
20
PECIE
21
PEG
22
DONE
23
PEAS
24
EEE
25
RE
26
AEE
0
27
SBC
28
RRE
29
RWE
30
EER
31
SAK
Access: User Read/Write
SBC1
Address: 0x0000
0
0
1
1
0
0
0
0
0
0
0
0
0
R
W
Reset
R
Reset
0
0
0
DWEE
w1c
Figure 130. Module Configuration register (MCR)
Table 195. MCR field descriptions
456/2075
Field
Description
30
RRE
Read Reference Error
RRE provides information on previous reads monitoring the analog Read references. If
the current and voltage Read references are out of range, this bit is set to signify that
previous reads requested may have been corrupted.
This status flag is cleared to ‘0’ by writing ‘1’ to the register location. A Write of ‘0’ has
no effect.
0 Reads are occurring normally.
1 A Read Reference Error occurred during a previous Read.
29
AEE
Address Encode Error
On every Read request to the flash memory, the incoming address is compared to an
encoded address (row, column, and block) from the memory array using the read data
sense amp timing. If these two values do not match (zero selected, multiple selected,
wrong selected), or the timing is incorrect, an address encode error is recorded.
This status flag is cleared to ‘0’ by writing ‘1’ to the register location. A Write of ‘0’ has
no effect.
0 Reads are occurring normally.
1 An Address Encode Error occurred during a previous Read.
28
EEE
EDC after ECC Error
EEE provides information on previous reads monitoring the EDC after ECC feature.
On every Read request to the flash memory, ECC parity is recomputed (encoding) just
after ECC decoding, and if there is a mismatch between the ECC calculations (taking
into account corrections or detections) a late error is reported.
The EEE flag indicates this event when data is legal or containing up to 3 bit errors.
This status flag is cleared to ‘0’ by writing ‘1’ to the register location. A Write of ‘0’ has
no effect.
0 Reads are occurring normally.
1 A previous Read may have been decoded by an ECC logic corrupted.
RM0483 Rev 5
RM0483
Embedded flash memory
Table 195. MCR field descriptions (continued)
Field
Description
27:24
DWEE
Double Word Uncorrectable ECC Error
DWEE identifies which Double Word is involved in ECC Uncorrectable Error Event.
In Code Flash 4 Double Words are read in parallel and ECC is evaluated on a couple
of Double Words basis. Therefore DWEE value could be:
1111 if an ECC Uncorrectable Error is found in both couples of Double Words
1100 if an ECC Uncorrectable Error is found in the couple of Double Words at high
address
0011 if an ECC Uncorrectable Error is found in the couple of Double Words at low
address
0000 if no ECC Uncorrectable Error is found
In Data Flash 2 Double Words are read in parallel and ECC is evaluated on a single
Double Word basis. Therefore DWEE value could be:
1111 if an ECC Uncorrectable Error is found in both Double Words
1010 if an ECC Uncorrectable Error is found in Double Word at high address
0101 if an ECC Uncorrectable Error is found in Double Word at low address
0000 if no ECC Uncorrectable Error is found
DWEE is a read only. Flags bits get cleared when EER is cleared.
20
SBC1
Single Bit Correction 1
SBC1 provides information on previous reads.
This bit must then be cleared or a reset must occur before this bit returns to a ‘0’ state.
This bit may not be set to ‘1’ by the user.
In the event of an ECC Triple Error detection or ECC Double Error correction, this bit is
not set.
This status flag is cleared to ‘0’ by writing ‘1’ to the register location. A Write of ‘0’ has
no effect.
The function of this bit is SoC dependent and it can be disabled (through UT0.SBCE1).
0 Reads are occurring normally.
1 An ECC Single Error occurred and was corrected during a previous Read.
In Code Flash, with 128b ECC coding, ECC correction is evaluated on couple of
Double word basis.
In Data Flash for EEE, ECC correction is evaluated on each Double word.
19
SAK
Suspend Acknowledge
SAK provides information about the Acknowledge of a suspend request at the setting
of DONE: SAK qualifies if the suspend has been accepted (initiated by PSUS or ESUS
setting) or if the running command has been completed, since very close to natural
end. The aim of this bit is for monitor. The sequence to resume normal functionality
(PSUS or ESUS clearing) is the same both is suspend has been acknowledged or not.
SAK is read Only
0 Operation has been completed prior that Suspend got processed
1 Suspend Acknowledged
18
LSW
Lock-Sel Write Error
LSW provides information about Lock and Sel write denied during the program and
erase sequence. If LSW is asserted, it must be cleared prior to attempting another high
voltage operation. Since this bit is a status flag, it must be cleared to a 0 by writing a 1
to the register location. A write of 0 has no effect.
0 Lock and Sel write successful
1 Lock and Sel write not succeeded
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RM0483
Table 195. MCR field descriptions (continued)
458/2075
Field
Description
17
PEP
Program and Erase Protection Error
PEP provides information about program and erase operations with respect to
protection errors. A protection error occurs if a program is attempted to a Locked block,
or if an erase is selected to a locked block. This is evaluated prior to the operation
beginning, and if an error is detected, high voltage operations are not attempted for this
request. If PEP is asserted, it must be cleared prior to attempting another high voltage
operation. Since this bit is a status flag, it must be cleared to a 0 by writing a 1 to the
register location. A write of 0 has no effect.
0 Program and Erase protection errors do not exist
1 Previous program or erase protection error encountered
16
PES
Program Erase Sequence Error
PES provides information about program and erase operations with respect to
sequence errors. A sequence error occurs when the program or erase sequence is not
followed exactly. If an out-of-order event is detected, PES asserts, and the remainder
of the sequence is not accepted. Sequence errors are checked from the time the PGM
or ERS are set (or remains set from previous operation) until EHV is set. Since this bit
is a status flag, it must be cleared to a 0 by writing a 1 to the register location. A write of
0 has no effect.
0 Program or Erase phase accepted
1 Program or Erase command encountered an error
15
EER
ECC uncorrectable Event Error
EER provides information on previous reads.
This bit must then be cleared or a reset must occur before this bit returns to a ‘0’ state.
EER may not be set to ‘1’ by the user.
EER is not set for a ECC correctable Error detection and related correction event.
This status flag is cleared to ‘0’ by writing ‘1’ to the register location. A Write of ‘0’ has
no effect.
0 Reads are occurring normally.
1 An ECC uncorrectable Error occurred during a previous Read.
In Code Flash, with 128b ECC coding, ECC error is evaluated on couple of Double
word basis.
In Data Flash for EEE, ECC error is evaluated on each Double word.
14
RWE
Read-while-Write event Error
RWE provides information on previous Reads during a Modify operation.
Read-While-Write Error means that a Read access to the Flash Array partition has
occurred while the FPEC was performing a Program or Erase operation or an Array
Integrity Check on the same partition.
This bit must then be cleared or a reset must occur before this bit returns to a ‘0’ state.
This bit may not be set to ‘1’ by the user.
This status flag is cleared to ‘0’ by writing ‘1’ to the register location. A Write of ‘0’ has
no effect.
0 Reads are occurring normally.
1 A RWW Error occurred during a previous Read.
RM0483 Rev 5
RM0483
Embedded flash memory
Table 195. MCR field descriptions (continued)
Field
Description
13
SBC
double Bit Correction
SBC provides information on previous reads.
This bit must then be cleared or a reset must occur before this bit returns to a ‘0’ state.
This bit may not be set to ‘1’ by the user.
In the event of an ECC Triple Error detection, this bit is not set.
This status flag is cleared to ‘0’ by writing ‘1’ to the register location. A Write of ‘0’ has
no effect.
The function of this bit is SoC dependent and it can be disabled (through UT0.SBCE).
0 Reads are occurring normally.
1 An ECC Double Error occurred and was corrected during a previous Read.
In Data Flash for EEE, ECC correction is evaluated on each Double word.
12
RE
Reset Error
This bit provides information on previous resets. Checks are done within the flash
memory, and if a coherency issue or ECC error is detected during the reset reads used
for trimming on the flash memory, this status flag asserts. This bit is status only, and is
not writable.
0 Flash Boot phase has occurred normally.
1 A reset error has been encountered.
11
PEAS
Program/Erase Access Space
PEAS is used to indicate which space is valid for Program and Erase operations: main
array space or UTEST section within Test Flash block.
– PEAS is captured and held with the first Interlock Write done for Modify operations.
– PEAS is retained between sampling events (that is subsequent to first interlock
writes).
– PEAS is changed during erase-suspended program (when program is in UTEST)
and reverts back to its original state (related to erase suspended operation) once the
erase-suspended program is completed (at MCR.PGM 1-0 transition).
0 UTEST address space is disabled for program and main address space enabled.
1 UTEST address space is enabled for program and main address space disabled.
10
DONE
Modify operation DONE
DONE indicates if the flash memory module is performing a high voltage operation.
DONE is set to ‘1’:
– On termination of the flash memory module reset.
– At the end of program and Erase High Voltage sequences.
– After “1-0” transition of EHV, which aborts a high voltage Erase/Program operation
(within a time equal or below to tESUS/t PSUS that are Erase/Program Suspend
Latency).
– After “0-1” transition of ESUS/PSUS which suspends an Erase/Program operation
(within tESUS/t PSUS time equal to the Erase/Program Suspend Latency).
DONE is cleared to ‘0’:
– just after “0-1” transition of EHV, which initiates a high voltage operation, or after
resuming a suspended operation.
0 Flash memory is executing a high-voltage operation.
1 Flash memory is not executing a high-voltage operation.
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RM0483
Table 195. MCR field descriptions (continued)
460/2075
Field
Description
9
PEG
Program/Erase Good
PEG is automatically updated to show the completion status of the last Flash Program
or Erase sequence involving high voltage operations.
PEG is evaluated on the completion status of only the interlocked doubleword during
page program or quad-page programming where some doubleword addresses are not
interlocked (already programmed or intended to remain virgin).
PEG is set to ‘0’ after Aborting a Program/Erase high voltage operation, indicating
sequence failure.
PEG is set to ‘1’ when the flash memory module is reset, unless a Flash Initialization
error has been detected.
Note: PEG is valid only when PGM=1 or ERS=1, or both, and after DONE 0-1
transitions due to an Abort or the completion of a Program/Erase operation.
PEG remains valid until PGM/ERS 1-0 transitions or EHV 0-1 transitions.
PEG is not valid after DONE 0-1 transitions when ESUS/PSUS is set to logic ‘1’.
If Program or Erase is attempted on blocks that are locked, PEG=1 indicating that the
content of the block were properly protected from the Program or Erase operation.
Blocks can be locked through LOCK0/1/2/3 registers OR with flh_plock0/1/2/3
sideband signals.
If a Program operation tries to write ‘1’ to bits that are ‘0’, the program operation is
correctly executed on the new bits to be programmed at ‘0’, but PEG is cleared
indicating that the requested operation has failed.
If Programming during an Erase-Suspend a location that was under suspended erase,
program is not executed and PEG is set to ‘0’.
With end2end ECC scheme, during an Interlock Write also ECC parity bits are input.
After setting EHV, the FPEC checks the integrity of the data received in terms of ECC.
If any doubleword in the doubleword program, in the page program or in the quad-page
program, contains an inconsistency between data and parity, the whole operation is
rejected and a PEG=0 is set.
PEG behavior with blocks marked as OPP (though flh_otpen0/1/2/3 sideband signals)
is the following: PEG=0 if the location to be programmed is not virgin, and thus would
not be over programmed.
In Array Integrity Check or Margin Read PEG is not altered when the operation is
completed, regardless of the occurrence of any error, abort, break point or suspend.
The presence of errors can only be detected by comparing the checksum value stored
in UM0-9 and by checking the MCR flags.
0 Program, Erase operation failed or Program, Erase aborted.
1 Program or Erase operation successful.
8
PECIE
Program/Erase Complete Interrupt Enable
PECIE provides a mechanism to trigger an interrupt request upon the assertion of the
DONE flag.
0 An interrupt request is not generated when the DONE flag is set.
1 An interrupt request is generated when the DONE flag is set.
RM0483 Rev 5
RM0483
Embedded flash memory
Table 195. MCR field descriptions (continued)
Field
Description
7
FERS
Factory Mode
FERS is used for Erase and Program operations to enable a faster operation.
Factory Mode must adhere to Initial maximum (All Temperatures) conditions, with
respect to voltage conditions and Write/Erase cycling. The temperature can range from
-40 °C to 150 °C.
Factory Mode does not support Read and RWW operations.
– FERS may be set to enable a Factory Erase or Program after setting ERS or PGM
but prior to setting EHV.
– FERS can be cleared only when EHV is low and DONE is high.
– FERS is cleared on reset
Note: Factory Mode may be permanently disabled by writing a location in the UTEST
Nonvolatile Memory space. Offset 0x0020 in the UTEST Nonvolatile Memory
space is checked at reset, and if programmed with data that contains at least one
zero, a Factory Mode is not allowed, and FERS is locked. Writes attempted that
violate the above cases result in FERS remaining cleared.
0 Factory Mode is disabled.
1 Factory Mode is enabled.
4
PGM
Program
PGM is used to setup the flash memory module for a Program operation.
– “0-1” transition of PGM initiates a program sequence.
– “1-0” transition of PGM ends the program sequence.
PGM can only be set in the following conditions:
– User Mode Read (ERS is low and UT0.UTE is low);
– Erase Suspend (ERS and ESUS high) with EHV low.
PGM can only be cleared by the user when PSUS and EHV are low and DONE is high.
PGM is cleared on reset.
Note: In an erase-suspended program, programming Flash memory locations in blocks
which were being operated on in the Erase is forbidden. Command is not
accepted and PEG is set to ‘0’
0 The flash memory is not executing a program sequence.
1 The flash memory is executing a program sequence.
RM0483 Rev 5
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Embedded flash memory
RM0483
Table 195. MCR field descriptions (continued)
462/2075
Field
Description
3
PSUS
Program Suspend
PSUS is used to indicate that the flash memory module is in Program Suspend or in
the process of entering a Suspend state. The flash memory module is in Program
Suspend when PSUS=1 and DONE=1.
– PSUS can be set high only when PGM and EHV are high.
– “0-1” transition of PSUS starts the sequence which sets DONE and places the Flash
in Program Suspend. The flash memory module enters Suspend within tPSUS of this
transition.
– PSUS can be cleared only when DONE and EHV are high.
– “1-0” transition of PSUS with EHV=1 starts the sequence which clears DONE and
returns the module to Program.
The flash memory module cannot exit Program Suspend and clear DONE while EHV is
low.
In the case of Program Suspend while in Erase Suspend (PSUS=1, ESUS=1), PSUS
has to be cleared first in order to resume currently higher level suspended operation
that is program.
PSUS is cleared on reset.
0 Program sequence is not suspended.
1 Program sequence is suspended.
2
ERS
Erase
ERS is used to setup the flash memory module for an Erase operation.
– “0-1” transition of ERS initiates an Erase sequence.
– “1-0” transition of ERS ends the Erase sequence.
ERS can be set only under User Mode Read (PGM is low and UT0.UTE is low).
ERS can be cleared by the user only when ESUS and EHV are low and DONE is high.
ERS is cleared on reset.
0 The flash memory is not executing an Erase sequence.
1 The flash memory is executing an Erase sequence.
RM0483 Rev 5
RM0483
Embedded flash memory
Table 195. MCR field descriptions (continued)
Field
Description
1
ESUS
Erase Suspend
ESUS is used to indicate that the flash memory module is in Erase Suspend or in the
process of entering a Suspend state. The flash memory module is in Erase Suspend
when ESUS = 1 and DONE=1.
– ESUS can be set high only when ERS and EHV are high and PGM is low.
– “0-1” transition of ESUS starts the sequence which sets DONE and places the Flash
in Erase Suspend. The flash memory module enters Suspend within tESUS of this
transition.
– ESUS can be cleared only when DONE and EHV are high and PGM is low.
– “1-0” transition of ESUS with EHV=1 starts the sequence which clears DONE and
returns the module to Erase.
The flash memory module cannot exit Erase Suspend and clear DONE while EHV is
low.
In case of Program Suspend while in Erase Suspend (PSUS=1, ESUS=1), ESUS
cannot be cleared first.
ESUS is cleared on reset.
0 Erase sequence is not suspended.
1 Erase sequence is suspended.
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Embedded flash memory
RM0483
Table 195. MCR field descriptions (continued)
Field
Description
0
EHV
Enable High Voltage
The EHV bit enables the flash memory module for a high voltage Program/Erase
operation.
EHV is cleared on reset.
EHV must be set after an Interlock Write to start a Program/Erase sequence.
EHV may be set under one of the following conditions:
– Erase (ERS=1, ESUS=0, UT0.AIE=0)
– Program (ERS=0, ESUS=0, PGM=1, UT0.AIE=0)
– Erase-suspended program (ERS=1, ESUS=1, PGM=1, PSUS=0, UT0.AIE=0).
For a program operation to initiate while an Erase is suspended, EHV must be cleared
while in Erase-Suspend (after DONE transitions to 1) before setting PGM.
In normal operation, a “1-0” transition of EHV with DONE high, PSUS low and ESUS
low terminates the current Program/Erase high voltage operation.
In an erase-suspended program operation, a “1-0” transition of EHV with DONE,
ESUS, PGM and ERS high and PSUS low terminates the program that is the current
high voltage operation.
When an operation is aborted, there is a “1-0” transition of EHV with DONE low and
the eventual Suspend bit for the current program/erase operation low.
An Abort causes the value of PEG to be cleared, indicating failed Program/Erase.
Address locations being operated on by the aborted operation contain indeterminate
data after an Abort. EHV cannot be set to ‘1’ after an Abort request (EHV being
cleared) until the Abort sequence is completed (DONE transitions to 1). Once the Abort
sequence is completed (DONE=1) a new operation of the kind aborted can start
provided that a new interlock is given and then EHV is set to ‘1’ again.
A suspended operation cannot be aborted.
Aborting a high voltage operation leaves the flash memory module addresses in an
indeterminate data state. This may be recovered by executing an Erase on the affected
blocks.
EHV may be written during Suspend. EHV must be high to exit Suspend, resuming
previously suspended command. EHV cannot not be written during transition into
Suspend state (after Suspend bit (ESUS or PSUS) is set high) until DONE transitions
to ‘1’. EHV may not be written after ESUS is set and before DONE transitions high.
EHV may not be cleared after ESUS is cleared and before DONE transitions low.
0 The flash memory is not enabled to perform a high voltage operation.
1 The flash memory is enabled to perform a high voltage operation.
A number of MCR bits are protected against Write when another bit, or set of bits, are in a
specific state. These Write locks are covered on a bit-by-bit basis in the preceding
description, but those locks do not consider the effects of trying to write two or more bits
simultaneously.
The flash memory module does not allow the user to write bits simultaneously (which puts
the device into an illegal state). This is implemented through a priority mechanism among
the bits shown in Table 196.
464/2075
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RM0483
Embedded flash memory
Table 196. MCR Bits Set/Clear Priority Levels
Priority level
MCR bits
1
ERS
2
PGM
3
EHV
4
ESUS, PSUS
If the user attempts to write two or more MCR bits simultaneously then only the bit with the
lowest priority level is written.
17.3.2.2
Alternate Module Configuration register (MCRA)
The Alternate Module Configuration register is used to enable and monitor all the Modify
operations of the flash memory module managed through Alternate interface.
29
28
27
26
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
PGMA
PSUSA
ERSA
ESUSA
EHVA
w1c
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
W
Reset
w1c
PEGA
R
w1c
DONEA
Reset
16
PEASA
W
17
PESA
30
PEPA
31
LSW
A
R
Access: User Read/Write
SAKA
Address: 0x0004
Figure 131. Alternate Module Configuration register (MCRA)
RM0483 Rev 5
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Embedded flash memory
RM0483
Table 197. MCRA field descriptions
466/2075
Field
Description
19
SAKA
Alternate Suspend Acknowledge
SAKA provides information about the Acknowledge of a suspend request at the setting
of DONEa: SAKA qualifies if the suspend has been accepted (initiated by PSUSa or
ESUSa setting) or if the running command has been completed, since very close to
natural end. The aim of this bit is for monitor. The sequence to resume normal
functionality (PSUSa or ESUSa clearing) is the same both is suspend has been
acknowledged or not.
SAKA is read Only
0 Operation has been completed prior that Suspend got processed.
1 Suspend Acknowledged
18
LSWA
Alternate Lock Write Error
LSWA provides information about Lock write denied during the program and erase
sequence. If LSWA is asserted, it must be cleared prior to attempting another high
voltage operation. Since this bit is a status flag, it must be cleared to a 0 by writing a 1
to the register location. A write of 0 has no effect.
0 Lock and Sel write successful.
1 Lock and Sel write not succeeded.
17
PEPA
Alternate Program and Erase Protection Error
PEPA provides information about program and erase operations with respect to
protection errors. A protection error occurs if a program is attempted to a Locked
block, or if an erase is selected to a locked block. This is evaluated prior to the
operation beginning, and if an error is detected, high voltage operations are not
attempted for this request. If PEPA is asserted, it must be cleared prior to attempting
another high voltage operation. Since this bit is a status flag, it must be cleared to a 0
by writing a 1 to the register location. A write of 0 has no effect.
0 Program and Erase protection errors do not exist.
1 Previous program or erase protection error encountered.
16
PESA
Alternate Program Erase Sequence Error
PESA provides information about program and erase operations with respect to
sequence errors. A sequence error occurs when the program or erase sequence is not
followed exactly. If an out-of-order event is detected, PESA asserts, and the remainder
of the sequence is not accepted. Sequence errors are checked from the time the
PGMA or ERSA are set (or remains set from previous operation) until EHVA is set.
Since this bit is a status flag, it must be cleared to a 0 by writing a 1 to the register
location. A write of 0 has no effect.
0 Program or Erase phase accepted
1 Program or Erase command encountered an error
11
PEASA
Program/Erase Access Space
PEASA is used to indicate which space is valid for Program and Erase operations:
main array space or UTEST block. It must be noted that erase is not allowed to the
UTest NVM space, therefore If an interlock write is done to the UTest NVM space with
ERSA set, PEASA remains 0. See PEAS definition in the MCR register for more
information (Table 195).
10
DONEA
Modify operation DONE
DONEA indicates if the embedded flash memory is performing a high-voltage
operation for the Alternate program and erase interface. See DONE definition in the
MCR register for more information (Table 195).
RM0483 Rev 5
RM0483
Embedded flash memory
Table 197. MCRA field descriptions (continued)
Field
Description
9
PEGA
Program/Erase Good
The PEGA bit indicates the completion status of the last Flash memory program or
erase sequence for which high-voltage operations were initiated for the Alternate
program and erase interface. See PEG definition in the MCR register for more
information (Table 195). It must be noted that in the event of a error on the alternate
interface PEGA clears, but the ADR register is not updated with the failing location.
The ADR register is only valid for main interface program or erase fails, and other fails
noted in the ADR register.
4
PGMA
Program
PGMA is used to set up embedded flash memory for a program operation for the
Alternate program and erase interface. See PGM definition in the MCR register for
more information (Table 195).
3
PSUSA
Program Suspend
PSUSA is used to indicate the embedded flash memory is in program suspend or in
the process of entering a suspend state for the Alternate program and erase interface.
See PSUS definition in the MCR register for more information (Table 195).
2
ERSA
Erase
ERSA is used to set up embedded flash memory for an erase operation for the
Alternate program and erase interface. See ERS definition in the MCR register for
more information (Table 195).
1
ESUSA
Erase Suspend
ESUSA is used to indicate that the embedded flash memory is in erase suspend or in
the process of entering a suspend state for the Alternate program and erase interface.
See ESUS definition in the MCR register for more information (Table 195).
0
EHVA
Enable High Voltage
The EHVA bit enables the embedded flash memory for a high-voltage program/erase
operation for the Alternate program and erase interface. See EHV definition in the
MCR register for more information (Table 195).
A number of MCR bits are protected against Write when another bit, or set of bits, are in a
specific state. These Write locks are covered on a bit-by-bit basis in the preceding
description, but those locks do not consider the effects of trying to write two or more bits
simultaneously.
17.3.2.3
Extended Module Configuration register (MCRE)
The Extended Module Configuration register value is based on the size, blocks and address
space configuration of the flash memory module.
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Embedded flash memory
RM0483
Address: 0x0008
31
R
Access: User Read
30
29
28
27
N128KL
26
25
24
23
N256K
22
21
20
N64KH
19
18
N32KH
17
16
N16KH
W
Reset
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
N64KM
N32KM
N16KM
N64KL
N32KL
N16KL
W
Reset
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
Figure 132. Extended Module Configuration register (MCRE)
Table 198. MCRE field descriptions
Field
468/2075
Description
30:29
N128KL
Number of 128 KB blocks in low space.
00 Zero 128 KB block.
01 One 128 KB block.
10 Two 128 KB blocks.
11 Three 128 KB blocks.
28:24
N256K
Number of 128 KB and 256 KB blocks in the 256K space
The value of the N256K field is dependent upon the size of the embedded flash
memory. N256K is read only.
N256K value represents in the number of blocks effectively available.
00000 Zero block.
00001 One block.
00010 Two blocks.
00011 Three blocks.
00100 Four blocks.
00101 Five blocks.
00110 Six blocks.
00111 Seven blocks
01000 Eight blocks.
01001 Nine blocks.
01010 Ten blocks.
…
11111 thirty-one blocks.
23:21
N64KH
Number of 64 KB blocks in high space
N64KH is read only.
000 Zero 64 KB block.
001 Two 64 KB blocks.
010 Four 64 KB blocks.
011 Six 64 KB blocks.
100 Eight 64 KB blocks.
101 Reserved.
110 Reserved.
111 Reserved.
RM0483 Rev 5
1
RM0483
Embedded flash memory
Table 198. MCRE field descriptions (continued)
Field
Description
20:19
N32KH
Number of 32 KB blocks in high space
N32K is read only.
00 Zero 32 KB block.
01 Two 32 KB blocks.
10 Four 32 KB blocks.
11 Reserved.
18:16
N16KH
Number of 16 KB blocks in high space
N16K is read only.
000 Zero 16 KB block.
001 Two 16 KB blocks.
010 Four 16 KB blocks.
011 Six 16 KB blocks.
100 Eight 16 KB blocks.
101 Reserved.
110 Reserved.
111 Reserved.
15:13
N64KM
Number of 64 KB blocks in mid space
N64KM is read only.
000 Zero 64 KB block.
001 Two 64 KB blocks.
010 Four 64 KB blocks.
011 Six 64 KB blocks.
100 Eight 64 KB blocks.
101 Reserved.
110 Reserved.
111 Reserved.
12:11
N32KM
Number of 32 KB blocks in mid space
N32KM is read only.
00 Zero 32 KB block.
01 Two 32 KB blocks.
10 Four 32 KB blocks.
11 Reserved.
10:8
N16KM
Number of 16 KB blocks in mid space
N16KM is read only.
000 Zero 16 KB block.
001 Two 16 KB blocks.
010 Four 16 KB blocks.
011 Six 16 KB blocks.
100 Eight 16 KB blocks.
101 Reserved.
110 Reserved.
111 Reserved.
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Embedded flash memory
RM0483
Table 198. MCRE field descriptions (continued)
Field
17.3.2.4
Description
7:5
N64KL
Number of 64 KB blocks in low space
N64KL is read only.
000 Zero 64 KB block.
001 Two 64 KB blocks.
010 Four 64 KB blocks.
011 Six 64 KB blocks.
100 Eight 64 KB blocks.
101 Three 64 KB blocks + One 96KB block.
110 Reserved.
111 Reserved.
4:3
N32KL
Number of 32 KB blocks in low space
N32KL is read only.
00 Zero 32 KB block.
01 Two 32 KB blocks.
10 One 32 KB block.
11 Three 32 KB blocks.
2:0
N16KL
Number of 16 KB blocks in low space
N16KL is read only.
000 Zero 16 KB block.
001 Two 16 KB blocks.
010 Four 16 KB blocks.
011 Six 16 KB blocks.
100 Eight 16 KB blocks.
101 Three 16 KB blocks.
110 Five 16 KB blocks.
111 Reserved.
Lock 0 register (LOCK0)
The LOCK0 (Low/Mid Address Space Block Locking) register provides a means of
protecting blocks from being modified. LOWLOCK and MIDLOCK bits corresponding to non
existent blocks are read as ‘1’.
To determine the effective status of the Low/Mid Address Space, combine (Or) LOCK0 with
sidebands:
•
flh_plock0 – in order to evaluate protection against programming.
•
flh_elock0 – in order to evaluate protection against erase.
The effect of programming or erasing a block protected with LOCK0 is that no modification
occurs and PEG is set to ‘1’.
470/2075
RM0483 Rev 5
RM0483
Embedded flash memory
Address: 0x0010
W
Reset
31
30
29
28
27
26
25
23
22
21
20
19
18
17
16
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
LOWLOCK
R
MIDLOCK
W
Reset
24
TSLOCK
R
Access: User Read/Write
1
1
1
1
1
1
1
1
1
Figure 133. Lock 0 register (LOCK0)
Table 199. LOCK0 field descriptions
Field
Description
31
TSLOCK
UTEST NVM block lock
This bit is used to lock the UTEST NVM from programming (UTEST NVM is not
erasable).
The LOCK field is not writable:
– Once an Interlock Write is completed until MCR.DONE is set and MCR.EHV gets
cleared.
– If a high voltage operation is suspended.
The default value of the TSLOCK bit is locked.
The effective status of the UTEST protection is done combining (ORed)
LOCK0.TSLOCK with sidebands flh_plock0.31 in order to evaluate protection
against program.
0 Test Address Space Block is unlocked and can be modified.
1 Test Address Space Block is locked and cannot be modified.
RM0483 Rev 5
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Embedded flash memory
RM0483
Table 199. LOCK0 field descriptions (continued)
472/2075
Field
Description
29:16
LOWLOCK
Low address space block lock
These bits are used to lock the existing blocks of Low Address Space from Program
and Erase.
The block numbering for the Low Blocks starts at LOWLOCK[0] with 16 KB block
region (if available), then the 32 KB block region (if available), and lastly the 64 KB
block region (if available). This continues until all blocks are accounted for.
The LOCK field is not writable:
– Once an Interlock Write is completed until MCR.DONE is set and MCR.EHV gets
cleared.
– If a high voltage operation is suspended.
The default value of the LOWLOCK bits is locked.
The reset state of the lock registers is affected by the alternate program and erase
block select information. By default, all blocks are in the main program and erase
space, and the main lock registers have full functionality, and no blocks are in the
alternative program and erase space (and are forced to lock).
Once selected for the alternate interface, the blocks selected in the alternative lock
register are available for locking or unlocking. The corresponding lock register in the
main interface will be forced to locked, and are not writable. This enables blocks to
be present in only one program and erase space (main or alternate).
In the event that blocks are not present (due to configuration or total memory size),
the LOWLOCK bits default to locked and are not writable. The reset value is always
‘1’ and register writes have no effect.
0 Low Address Space Block is unlocked and can be modified.
1 Low Address Space Block is locked and cannot be modified.
15:0
MIDLOCK
Mid address space block lock
These bits are used to lock the blocks of Mid Address Space from Program and
Erase.
The block numbering for the Mid Blocks starts at MIDLOCK[0] with16 KB block
region (if available), then the 32 KB block region (if available), and lastly the 64 KB
block region (if available). This continues until all blocks are accounted for.
The LOCK field is not writable:
– Once an Interlock Write is completed until MCR.DONE is set and MCR.EHV gets
cleared.
– If a high voltage operation is suspended.
The default value of the MIDLOCK bits is locked.
The reset state of the lock registers is affected by the alternate program and erase
block select information. By default, all blocks are in the main program and erase
space, and the main lock registers have full functionality, and no blocks are in the
alternative program and erase space (and are forced to lock).
Once selected for the alternate interface, the blocks selected in the alternative lock
register are available for locking or unlocking. The corresponding lock register in the
main interface will be forced to locked, and are not writable. This enables blocks to
be present in only one program and erase space (main or alternate).
In the event that blocks are not present (due to configuration or total memory size),
the MIDLOCK bits default to locked, and are not writable. The reset value is always
‘1’ and register writes have no effect.
0 Mid Address Space Block is unlocked and can be modified.
1 Mid Address Space Block is locked and cannot be modified.
RM0483 Rev 5
RM0483
Embedded flash memory
17.3.2.5
Lock 1 register (LOCK1)
The LOCK1 (High/Data Address Space Block Locking) register provides a means of
protecting blocks from being modified. HIGHLOCK bits corresponding to nonexistent blocks
are read as ‘1’.
•
To determine the effective status of the High Address Space, combine (Or) LOCK1 with
sidebandsflh_plock1 – in order to evaluate protection against program
•
flh_elock1 – in order to evaluate protection against erase.
The effect of programming/erasing a block protected with LOCK1 is that no modification
occurs and PEG is set to ‘1’.
Address: 0x0014
R
Access: User Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
W
Reset
R
HIGHLOCK
W
Reset
1
1
1
1
1
1
1
1
1
Figure 134. Lock 1 register (LOCK1)
Table 200. LOCK1 field descriptions
Field
Description
15:0
HIGHLOCK
High address space block lock
These bits are used to lock the blocks of High Address Space from Program and
Erase.
The block numbering for the High Blocks starts at HIGHLOCK[0] with16 KB block
region (if available), then the 32 KB block region (if available), and lastly the 64 KB
block region (if available). This continues until all blocks are accounted for.
The LOCK field is not writable:
– Once an Interlock Write is completed until MCR.DONE is set and MCR.EHV gets
cleared.
– If a high voltage operation is suspended.
The default value of the HIGHLOCK bits is locked.
The reset state of the lock registers is affected by the alternate program and erase
block select information. By default, all blocks are in the main program and erase
space, and the main lock registers have full functionality, and no blocks are in the
alternative program and erase space (and are forced to lock).
Once selected for the alternate interface, the blocks selected in the alternative lock
register are available for locking or unlocking. The corresponding lock register in
the main interface will be forced to locked, and are not writable. This enables blocks
to be present in only one program and erase space (main or alternate).
When blocks are not present (due to configuration or total memory size), the
HIGHLOCK bits default to locked, and are not writable. The reset value is always ‘1’
and register writes have no effect.
0 High Address Space Block is unlocked and can be modified.
1 High Address Space Block is locked and cannot be modified.
RM0483 Rev 5
473/2075
532
Embedded flash memory
17.3.2.6
RM0483
Lock 2 register (LOCK2)
The LOCK2 (256K Address Space Block Locking) register provides a means of protecting
blocks from being modified. The A256KLOCK bits corresponding to nonexistent blocks are
read as ‘1’.
To determine the effective status of the A256KLOCK Address Space, combine (Or) LOCK2
with sidebands:
•
flh_plock2 – in order to evaluate protection against program
•
flh_elock2 – in order to evaluate protection against erase
The effect of programming/erasing a block protected with LOCK2 is that no modification
occurs and PEG is set to ‘1’.
Address: 0x0018
31
Access: User Read/Write
30
29
28
27
26
25
R
22
21
20
19
18
17
16
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
R
A256KLOCK
W
Reset
23
A256KLOCK
W
Reset
24
1
1
1
1
1
1
1
1
1
Figure 135. Lock 2 register (LOCK2)
Table 201. LOCK2 field descriptions
17.3.2.7
Field
Description
31:0
A256KLOCK
256K address space block lock A256KLOCK[31:0]
These bits are used to lock the existing blocks of Low Address Space from
Program and Erase.
The block numbering for the 256 KB blocks starts with A256KLOCK[0] and
continues until all blocks are accounted for.
The LOCK field is not writable:
– Once an Interlock Write is completed until MCR.DONE is set and MCR.EHV
gets cleared.
– If a high voltage operation is suspended.
The default value of the A256KLOCK bits is locked.
When blocks are not present (due to configuration or total memory size), the
A256KLOCK bits default to locked and are not writable. The reset value is always
‘1’ and register writes have no effect.
0 A256K Address Space Block is unlocked and can be modified.
1 A256K Address Space Block is locked and cannot be modified.
Lock 3 register (LOCK3)
The LOCK3 (256K Address Space Block Locking) register provides a means of protecting
blocks from being modified. The A256KLOCK bits corresponding to nonexistent blocks are
read as ‘1’.
474/2075
RM0483 Rev 5
RM0483
Embedded flash memory
To determine the effective status of the A256KLOCK Address Space, combine (Or) LOCK3
with sidebands:
•
flh_plock3 – in order to evaluate protection against program
•
flh_elock3 – in order to evaluate protection against erase.
The effect of programming/erasing a block protected with LOCK3 is that no modification
occurs and PEG is set to ‘1’.
Address: 0x001C
31
Access: User Read/Write
30
29
28
27
26
25
R
22
21
20
19
18
17
16
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
R
A256KLOCK
W
Reset
23
A256KLOCK
W
Reset
24
1
1
1
1
1
1
1
1
1
Figure 136. Lock 3 register (LOCK3)
Table 202. LOCK3 field descriptions
17.3.2.8
Field
Description
31:0
A256KLOCK
256K address space block lock A256KLOCK[63:32]
These bits are used to lock the existing blocks of Low Address Space from
Program and Erase.
The block numbering for the 256 KB blocks starts with A256KLOCK[32] and
continues until all blocks are accounted for.
The LOCK field is not writable:
– Once an Interlock Write is completed until MCR.DONE is set and MCR.EHV
gets cleared.
– If a high voltage operation is suspended.
The default value of the A256KLOCK bits is locked.
When blocks are not present (due to configuration or total memory size), the
A256KLOCK bits default to locked and are not writable. The reset value is always
‘1’ and register writes have no effect.
0 A256K Address Space Block is unlocked and can be modified.
1 A256K Address Space Block is locked and cannot be modified.
Alternate Lock 0 register (LOCK0A)
The Alternate LOCK0A (Low/Mid Address Space Block Locking) register provides a means
of protecting blocks from being modified on the alternate program and erase interface.
LOWLOCKA and MIDLOCKA bits corresponding to non existent blocks are read as ‘1’.
The effective status of the Alternate Low Address Space is not affected by sidebands as in
the Main Interface
The effect of programming/erasing a block protected with LOCK1A is that no modification
occurs and PEGA is set to ‘1’.
RM0483 Rev 5
475/2075
532
Embedded flash memory
RM0483
Address: 0x0028
W
Reset
31
30
29
28
27
26
25
23
22
21
20
19
18
17
16
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
LOWLOCKA
R
MIDLOCKA
W
Reset
24
TSLOCKA
R
Access: User Read/Write
1
1
1
1
1
1
1
1
1
Figure 137. Alternate Lock 0 register (LOCK0A)
Table 203. LOCK0A field descriptions
476/2075
Field
Description
31
TSLOCKA
Alternate UTEST NVM block lock
This bit is used to lock the UTEST NVM from programming (UTEST NVM is not
erasable).
The LOCK field is not writable:
– Once an Interlock Write is completed until MCRA.DONEA is set and MCR.EHVA
gets cleared.
– If a high voltage operation is suspended.
The default value of the TSLOCK bit is locked.
The effective status of the UTEST protection is done combining (ORed)
LOCK0A.TSLOCKA with sidebands flh_aplock_utest in order to evaluate protection
against program.
0 The UTEST Block is unlocked and can be modified on the alternate interface.
1 The UTEST Block is locked and cannot be modified on the alternate interface.
RM0483 Rev 5
RM0483
Embedded flash memory
Table 203. LOCK0A field descriptions (continued)
Field
Description
29:16
LOWLOCKA
Alternate Low address space block lock
These bits are used to lock the existing blocks of Low Address Space from Program
and Erase.
The block numbering for the Low Blocks starts at LOWLOCKA[0] with16 KB block
region (if available), then the 32 KB block region (if available), and lastly the 64 KB
block region (if available). This continues until all blocks are accounted for.
The LOCK field is not writable:
– Once an Interlock Write is completed until DONEA is set and MCR.EHVA gets
cleared.
– If a high voltage operation is suspended.
The default value of the LOWLOCKA bits is locked.
By default, all blocks are in the main program and erase space, and the main lock
registers have full functionality, and no blocks are in the alternative program and
erase space (and are forced to lock).
Once selected for the alternate interface, the blocks selected in the alternative lock
register are available for locking or unlocking. The corresponding lock register in the
main interface will be forced to locked, and are not writable. This enables blocks to
be present in only one program and erase space (main or alternate).
In the event that blocks are not present (due to configuration or total memory size),
the LOWLOCKA bits default to locked and are not writable. The reset value is
always ‘1’ and register writes have no effect.
0 Alternate Low Address Space Block is unlocked and can be modified.
1 Alternate Low Address Space Block is locked and cannot be modified.
15:0
MIDLOCKA
Alternate Mid address space block lock
These bits are used to lock the blocks of Mid Address Space from Program and
Erase.
The block numbering for the Mid Blocks starts at MIDLOCKA[0] with16 KB block
region (if available), then the 32 KB block region (if available), and lastly the 64 KB
block region (if available). This continues until all blocks are accounted for.
The LOCK field is not writable:
– Once an Interlock Write is completed until DONEA is set and MCR.EHVA gets
cleared.
– If a high voltage operation is suspended.
The default value of the MIDLOCKA bits is locked.
By default, all blocks are in the main program and erase space, and the main lock
registers have full functionality, and no blocks are in the alternative program and
erase space (and are forced to lock).
Once selected for the alternate interface, the blocks selected in the alternative lock
register are available for locking or unlocking. The corresponding lock register in the
main interface will be forced to locked, and are not writable. This enables blocks to
be present in only one program and erase space (main or alternate).
In the event that blocks are not present (due to configuration or total memory size),
the MIDLOCKA bits default to locked, and are not writable. The reset value is always
‘1’ and register writes have no effect.
0 Alternate Mid Address Space Block is unlocked and can be modified.
1 Alternate Mid Address Space Block is locked and cannot be modified.
RM0483 Rev 5
477/2075
532
Embedded flash memory
17.3.2.9
RM0483
Alternate Lock 1 register (LOCK1A)
The Alternate LOCK1A (Alternate High Address Space Block Locking) register provides a
means of protecting blocks from being modified on the alternate program and erase
interface. HIGHLOCK bits corresponding to nonexistent blocks are read as ‘1’.
The effect of programming/erasing a block protected with LOCK1A is that no modification
occurs and PEGa is set to ‘1’.
Address: 0x002C
Access: User Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
R
W
Reset
R
HIGHLOCKA
W
Reset
1
1
1
1
1
1
1
1
1
Figure 138. Alternate Lock 1 register (LOCK1A)
Table 204. Alternate LOCK1A field descriptions
Field
Description
15:0
HIGHLOCKA
Alternate High address space block lock
These bits are used to lock the blocks of High Address Space from Program and Erase.
The block numbering for the High Blocks starts at HIGHLOCKA[0] with16 KB block region (if
available), then the 32 KB block region (if available), and lastly the 64 KB block region (if
available). This continues until all blocks are accounted for.
The LOCK field is not writable:
– Once an Interlock Write is completed until DONEA is set and MCR.EHVA gets cleared.
– If a high voltage operation is suspended.
The default value of the HIGHLOCKA bits is locked.
By default, all blocks are in the main program and erase space, and the main lock registers
have full functionality, and no blocks are in the alternative program and erase space (and are
forced to lock).
Once selected for the alternate interface, the blocks selected in the alternative lock register are
available for locking or unlocking. The corresponding lock register in the main interface will be
forced to locked, and are not writable. This enables blocks to be present in only one program
and erase space (main or alternate).
When blocks are not present (due to configuration or total memory size), the HIGHLOCK bits
default to locked, and are not writable. The reset value is always ‘1’ and register writes have no
effect.
0 High Address Space Block is unlocked and can be modified.
1 High Address Space Block is locked and cannot be modified.
17.3.2.10 Select 0 register (SEL0)
The SEL0 (Low/Mid Address Space Block Select 0) register provides a means to select
blocks to be operated on during Erase or Array Integrity Check – Margin Read.
478/2075
RM0483 Rev 5
RM0483
Embedded flash memory
Starting an Erase operation, SEL0 bits are latched and become non-alterable from the first
interlock cycle that follows the rising transition of MCR.ERS (see step 4 in Section 17.4.3.2:
Erase) until the completion of the Erase high voltage operation (1–0 transition of MCR.EHV
with MCR.ERS=1 and with MCR.ESUS=0). Reading returns latched data (image of the
SEL0 at the start of the Erase operation) while writing has no effect.
Address: 0x0038
R
Access: User Read/Write
31
30
0
0
29
28
27
26
25
24
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
R
21
20
19
18
17
16
0
0
0
0
0
0
0
6
5
4
3
2
1
0
0
0
0
0
0
0
0
MIDSEL
W
Reset
22
LOWSEL
W
Reset
23
0
0
0
0
0
0
0
0
0
Figure 139. Select 0 register (SEL0)
Table 205. SEL0 field descriptions
Field
Description
29:16
LOWSEL
Low address space block Select
The block numbering for the Low Blocks starts at LOWSEL[0] with16 KB block region
(if available), then the 32 KB block region (if available), and lastly the 64 KB block
region (if available). This continues until all blocks are accounted.
The blocks must be selected (or unselected) before doing an Erase Interlock Write as
part of the Erase sequence.
The select field is not writable:
– once an Interlock Write is completed until DONE is set and MCR.EHV gets cleared.
– a high voltage operation is suspended.
– when UT0.AIE is high.
When blocks are not present (due to configuration or total memory size) the
corresponding LOWSEL bits default to unselected and are not writable. The reset
value is always ‘0’, and register writes have no effect.
0 Low Address Space Block is unselected for Erase.
1 Low Address Space Block is selected for Erase.
RM0483 Rev 5
479/2075
532
Embedded flash memory
RM0483
Table 205. SEL0 field descriptions (continued)
17.3.2.11
Field
Description
15:0
MIDSEL
Mid address space block Select
The block numbering for the Mid Blocks starts at MIDLSEL[0] with16 KB block region
(if available), then the 32 KB block region (if available), and lastly the 64 KB block
region (if available). This continues until all blocks are accounted for.
The blocks must be selected (or unselected) before doing an Erase Interlock Write as
part of the Erase sequence.
The select field is not writable:
– once an Interlock Write is completed until DONE is set and MCR.EHV gets cleared.
– a high voltage operation is suspended.
– when UT0.AIE is high.
When blocks are not present (due to configuration or total memory size), the
corresponding MIDSEL bits default to unselected and are not writable.The reset
value is always ‘0’, and register writes have no effect.
0 Mid Address Space Block is unselected for Erase.
1 Mid Address Space Block is selected for Erase.
Select 1 register (SEL1)
The SEL1 (High Address Space Block Select register 1) provides a means of selecting
blocks to be operated on during Erase or Array Integrity Check – Margin Read.
Starting an Erase operation, SEL1 bits are latched and become non-alterable from the first
interlock cycle that follows the rising transition of MCR.ERS (see step 4 in Section 17.4.3.2:
Erase) until the completion of the Erase high voltage operation (1–0 transition of MCR.EHV
with MCR.ERS=1 and with MCR.ESUS=0). Reading returns latched data (image of the
SEL1 at the start of the Erase operation) while writing has no effect.
Address: 0x003C
R
Access: User Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
W
Reset
R
HIGHSEL
W
Reset
0
0
0
0
0
0
0
0
0
Figure 140. Select 1 register (SEL1)
480/2075
RM0483 Rev 5
RM0483
Embedded flash memory
Table 206. SEL1 field descriptions
Field
Description
15:0
HIGHSEL
High/Data address space block Select 1
The block numbering for the High Blocks starts at HIGHSEL[0] with16 KB block
region (if available), then the 32 KB block region (if available), and lastly the 64 KB
block region (if available). This continues until all blocks are accounted for.
The blocks must be selected (or unselected) before doing an Erase Interlock Write as
part of the Erase sequence.
The select field is not writable:
– once an Interlock Write is completed until DONE is set and MCR.EHV gets cleared.
– a high voltage operation is suspended.
– when UT0.AIE is high.
When blocks are not present (due to configuration or total memory size) the
corresponding HIGHSEL bits default to unselected and are not writable. The reset
value is always ‘0’ and register writes have no effect.
0 High Address Space Block is unselected for Erase.
1 High Address Space Block is selected for Erase.
17.3.2.12 Select 2 register (SEL2)
The SEL2 (256K Address Space Block Select 2) register provides a means of selecting
blocks to be operated on during Erase or Array Integrity Check – Margin Read.
Starting an Erase operation, SEL2 bits are latched and become non-alterable from the first
interlock cycle that follows the rising transition of MCR.ERS (see step 4 in Section 17.4.3.2:
Erase) until the completion of the Erase high voltage operation (1–0 transition of MCR.EHV
with MCR.ERS=1 and with MCR.ESUS=0). Reading returns latched data (image of the
SEL2 at the start of the Erase operation) while writing has no effect.
Address: 0x0040
31
Access: User Read/Write
30
29
28
27
26
25
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
A256KSEL
W
Reset
23
A256KSEL
W
Reset
24
0
0
0
0
0
0
0
0
0
Figure 141. Select 2 register (SEL2)
RM0483 Rev 5
481/2075
532
Embedded flash memory
RM0483
Table 207. SEL2 field descriptions
Field
Description
31:0
A256KSEL
256K address space block select A256KSEL[31:0]
The block numbering for the 256 KB blocks starts with A256KSEL[0] and continues
until all blocks are accounted for.
The blocks must be selected (or unselected) before doing an Erase Interlock Write
as part of the Erase sequence.
The select field is not writable:
– once an Interlock Write is completed until DONE is set and MCR.EHV gets
cleared
– a high voltage operation is suspended.
– when UT0.AIE is high.
When blocks are not present (due to configuration or total memory size) the
corresponding A256KSEL bits default to unselected and are not writable.
The reset value is always ‘0’, and register writes have no effect.
0 A256K Address Space Block is unselected for Erase.
1 A256K Address Space Block is selected for Erase.
17.3.2.13 Select 3 register (SEL3)
The SEL3 (256K Address Space Block Select 3) register provides a means of selecting
blocks to be operated on during Erase or Array Integrity Check – Margin Read.
Starting an Erase operation, SEL3 bits are latched and become non-alterable from the first
interlock cycle that follows the rising transition of MCR.ERS (see step 4 in Section 17.4.3.2:
Erase) until the completion of the Erase high voltage operation (1–0 transition of MCR.EHV
with MCR.ERS=1 and with MCR.ESUS=0). Reading returns latched data (image of the
SEL3 at the start of the Erase operation) while writing has no effect.
Address: 0x0044
31
Access: User Read/Write
30
29
28
27
26
25
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
A256KSEL
W
Reset
23
A256KSEL
W
Reset
24
0
0
0
0
0
0
0
0
0
Figure 142. Select 3 register (SEL3)
482/2075
RM0483 Rev 5
RM0483
Embedded flash memory
Table 208. SEL3 field descriptions
Field
Description
31:0
A256KSEL
256K address space block select A256KSEL[63:32]
The block numbering for the 256 KB blocks starts with A256KSEL[32] and continues
until all blocks are accounted for.
The blocks must be selected (or unselected) before doing an Erase Interlock Write
as part of the Erase sequence.
The select field is not writable:
– once an Interlock Write is completed until DONE is set and MCR.EHV gets
cleared
– a high voltage operation is suspended.
– when UT0.AIE is high.
When blocks are not present (due to configuration or total memory size) the
corresponding A256KSEL bits default to unselected and are not writable.
The reset value is always ‘0’, and register writes have no effect.
0 A256K Address Space Block is unselected for Erase.
1 A256K Address Space Block is selected for Erase.
17.3.2.14 Module Configuration register 2 (MCR2)
The Parallel Module Configuration register is used to monitor all the Read operations of the
flash memory module on Read-While-Read Partition 1.
30
29
28
0
0
25
24
PDWEE
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
w1c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PSBC
w1c
26
PRWE
Reset
w1c
27
PEER
W
PEEE
31
PAEE
R
Access: User Read/Write
PSBC1
Address: 0x0048
0
0
0
0
0
0
0
0
0
0
0
0
0
W w1c w1c
w1c
0
0
1
1
0
0
0
0
0
0
0
0
0
R
Reset
0
0
0
Figure 143. Module Configuration register 2 (MCR2)
RM0483 Rev 5
483/2075
532
Embedded flash memory
RM0483
Table 209. MCR2 field descriptions
484/2075
Field
Description
29
PAEE
Parallel Address Encode Error
On every Read request to the Flash, the incoming address is compared to an
encoded address (row, column, and block) from the memory array using the read
data sense amp timing. If these two values do not match (zero selected, multiple
selected, wrong selected), or the timing is incorrect, an address encode error is
recorded.
This status flag is cleared to ‘0’ by writing ‘1’ to the register location. A Write of ‘0’
has no effect.
0 Reads are occurring normally
1 An Address Encode Error occurred during a previous Read.
28
PEEE
Parallel EDC after ECC Error
PEEE provides information on previous reads monitoring the EDC after ECC
feature.
On every Read request to the Flash, ECC parity is recomputed (encoding) just
after ECC decoding, and if there is a mismatch between the ECC calculations
(taking into account corrections or detections) a late error is reported.
This status flag is cleared to ‘0’ by writing ‘1’ to the register location. A Write of ‘0’
has no effect.
0 Reads are occurring normally
1 A previous Read may have been corrupted.
27:24
PDWEE
Parallel Double Word Uncorrectable ECC Error
PDWEE identifies which Double Word is involved in ECC Uncorrectable Error
Event.
In Code Flash 4 Double Words are read in parallel and ECC is evaluated on a
couple of Double Words basis. Therefore PDWEE value could be:
1111 if an ECC Uncorrectable Error is found in both couples of Double Words
1100 if an ECC Uncorrectable Error is found in the couple of Double Words at
high address
0011 if an ECC Uncorrectable Error is found in the couple of Double Words at low
address
0000 if no ECC Uncorrectable Error is found
PDWEE is a read only. Flags bits get cleared when EER is cleared.
20
PSBC1
Parallel Single Bit Correction 1
PSBC1 provides information on previous reads.
This bit must then be cleared or a reset must occur before this bit returns to a ‘0’
state.
This bit may not be set to ‘1’ by the user.
In the event of an ECC Triple Error detection or ECC Double Error correction, this
bit is not set.
This status flag is cleared to ‘0’ by writing ‘1’ to the register location. A Write of ‘0’
has no effect.
The function of this bit is SoC dependent and it can be disabled (through
UT0.SBCE1).
0 Reads are occurring normally.
1 An ECC Single Error occurred and was corrected during a previous Read.
In Code Flash, with 128b ECC coding, ECC correction is evaluated on couple of
Double word basis.
In Data Flash for EEE, ECC correction is evaluated on each Double word.
RM0483 Rev 5
RM0483
Embedded flash memory
Table 209. MCR2 field descriptions (continued)
Field
Description
15
PEER
Parallel ECC Event Error
PEER provides information on previous reads.
This bit must then be cleared or a reset must occur before this bit returns to a ‘0’
state.
PEER may not be set to ‘1’ by the user.
PEER is not set for a ECC correctable Error detection and related correction
event.
This status flag is cleared to ‘0’ by writing ‘1’ to the register location. A Write of ‘0’
has no effect.
0 Reads are occurring normally.
1 An ECC uncorrectable Error occurred during a previous Read.
In Code Flash, with 128b ECC coding, ECC error is evaluated on couple of
Double word basis.
In Data Flash for EEE, ECC error is evaluated on each Double word.
14
PRWE
Parallel Read-while-Write event Error
PRWE provides information on previous Reads during a Modify operation.
Read-While-Write Error means that a Read access to the Flash Array partition
has occurred while the FPEC was performing a Program or Erase operation or an
Array Integrity Check on the same partition.
This bit must then be cleared or a reset must occur before this bit returns to a ‘0’
state.
This bit may not be set to ‘1’ by the user.
This status flag is cleared to ‘0’ by writing ‘1’ to the register location. A Write of ‘0’
has no effect.
0 Reads are occurring normally.
1 A RWW Error occurred during a previous Read.
13
PSBC
Parallel double Bit Correction
PSBC provides information on previous reads.
This bit must then be cleared or a reset must occur before this bit returns to a ‘0’
state.
This bit may not be set to ‘1’ by the user.
In the event of an ECC Triple Error detection, this bit is not set.
This status flag is cleared to ‘0’ by writing ‘1’ to the register location. A Write of ‘0’
has no effect.
The function of this bit is SoC dependent and it can be disabled (through
UT0.SBCE).
0 Reads are occurring normally.
1 An ECC Double Error occurred and was corrected during a previous Read.
In Data Flash for EEE, ECC correction is evaluated on each Double word.
17.3.2.15 Program Address register (PAR)
The Program Address register provides the last successful address programmed. A
successful program is defined as a program operation of data that is not all 1s, to an
unlocked block and the operation results in MCR.PEG returning a ‘1’. This value is held until
the next successful address program event.
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RM0483
Address: 0x004C
R
Access: User Read
31
30
29
28
27
26
25
24
23
22
21
20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
19
18
17
16
0
0
0
0
3
2
1
0
0
0
0
0
0
0
PAR
W
Reset
PAR
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 144. Program Address register (PAR)
Table 210. PAR field descriptions
Field
Description
23:3
PAR
Address
The Address register provides the last successful address programmed through the
Main Interface.
Address given is in Flash format and has to be intended as in the flash memory Map:
offset respect to absolute address. Mapping can be found in Section 17.3.2.16:
Address register (ADR)
17.3.2.16 Address register (ADR)
The Address register provides the first failing address in the event of module failures (ECC,
RWW or FPEC). ADR captures the first failing address for the modes listed in Table 212
according to the priority rules in Table 213.
In case of Array Integrity Check or Margin Read with Break Point enabled (UT0.AIBPE=1),
the ADR value matches the address where the Break Point was triggered only when the
current run (first start or re-start after a breakpoint (NAIBP cleared)) starts with MCR.ERR
and MCR.SBC flags cleared, otherwise the ADR priority rule overrides Break Point.
Address: 0x0050
Access: User Read
31
30
29
28
27
26
25
24
23
22
21
20
R SAD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
19
18
17
16
0
0
0
0
3
2
1
0
0
0
0
0
0
0
ADDR
W
Reset
R
ADDR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
Figure 145. Address register (ADR)
486/2075
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0
0
RM0483
Embedded flash memory
Table 211. ADR field descriptions
Field
Description
31
SAD
Test Address
When this bit is high, the address indicated by ADDR[23:3] belongs to the Test
Block.
23:3
ADDR
Address
The Address register provides the first failing address in the event of ECC
Uncorrectable error (MCR.EER set) or the first failing address in the event of RWW
error (MCR.RWE set), or the address of a failure that may have occurred in a FPEC
operation (MCR.PEG cleared). The Address register also provides the first address
at which a ECC correction occurs (MCR.SBC or MCR.SBC1, or both are set) if the
SoC is configured to show this feature through UT0.SBCE or UT0.SBCE1, or both.
The ECC uncorrectable error detection takes the highest priority, followed by the
RWW error, the FPEC error and the ECC error corrections. When accessed, ADR
provides the address related to the first event occurred with the highest priority.
In case of a simultaneous ECC Events Detection, bits ADDR[4] and ADDR[3]
output ‘0’.
In User mode the Address register is read only.
In Modify Mode ADDR can be updated on FPEC Error on the whole flash memory
address space.
In User Test Mode ADDR can be updated on Error events on the whole flash
memory address space.
In Read and RWW Modes ADDR can be updated on Error belonging to the address
space of the primary Read-While-Read Partition 0.
Address given is in Flash format and has to be intended as in the flash memory
Map.
Table 212. ADR update mode list
Mode
Update on error
Note
Read
ECC Uncorrectable Error Detection, ECC
Double Error Correction (if UT0.SBCE=1) ECC
Single Error Correction (if UT0.SBCE1=1)
—
Modify
FPEC error
—
RWW
Read-While-Write error
In RWW all Read and Modify
cause of update on error may also
occur
ECC Uncorrectable Error Detection, ECC
Single Error Correction (if UT0.SBCE1=1)
With Break Point enabled
(UT0.AIBPE=1), ADR requires
MCR.ERR and MCR.SBC to be
cleared
User Test
Table 213. ADR content: priority list
Priority level
Error flag
ADR content
1
MCR.EER = 1
Address of first ECC Uncorrectable Error
2
MCR.RWE = 1
Address of first RWW Error
3
MCR.PEG = 0
Address of first FPEC Error
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Table 213. ADR content: priority list (continued)
Priority level
Error flag
ADR content
4
MCR.SBC = 1
Address of first ECC Double Error Correction
5
MCR.SBC1 = 1
Address of first ECC Single Error Correction
Table 214. Flash memory partition 0 address mapping
Block
Flash format addresses
Absolute addresses
B0F0
0x0088_0000 to 0x0088_7FFF
0x1800_0000 to 0x1800_7FFF
B0F1
0x0088_8000 to 0x0089_7FFF
0x1800_8000 to 0x1801_7FFF
B0F2
0x0089_8000 to 0x008A_7FFF
0x1801_8000 to 0x1802_7FFF
B0F3-UT
0x0080_0000 to 0x0080_3FFF
0x1FF8_0000 to 0x1FF8_3FFF
B0F3-BF
0x0080_4000 to 0x0080_7FFF
0x1FF0_0000 to 0x1FF0_3FFF
B0F3-TF
0x0080_8000 to 0x0080_BFFF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table 215. Flash memory partition 1 address mapping
488/2075
Block
Flash format addresses
Absolute addresses
B1F0
0x0000_0000 to 0x0000_FFFF
0x0800_0000 to 0x0800_FFFF
B1F1
0x0001_0000 to 0x0001_FFFF
0x0801_0000 to 0x0801_FFFF
B1F2
0x0002_0000 to 0x0002_FFFF
0x0802_0000 to 0x0802_FFFF
B1F3
0x0003_0000 to 0x0006_FFFF
0x0803_0000 to 0x0806_FFFF
B1F4
0x0007_0000 to 0x000A_FFFF
0x0807_0000 to 0x080A_FFFF
B1F5
0x000B_0000 to 0x000E_FFFF
0x080B_0000 to 0x080E_FFFF
—
—
—
—
—
—
—
—
—
RM0483 Rev 5
RM0483
Embedded flash memory
Table 215. Flash memory partition 1 address mapping (continued)
Block
Flash format addresses
Absolute addresses
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table 216. Flash memory partition 2 address mapping
Block
Flash format addresses
Absolute addresses
B2F0
0x000F_0000 to 0x000F_FFFF
0x080F_0000 to 0x080F_FFFF
B2F1
0x0010_0000 to 0x0010_FFFF
0x0810_0000 to 0x0810_FFFF
B2F2
0x0011_0000 to 0x0011_FFFF
0x0811_0000 to 0x0811_FFFF
B2F3
0x0012_0000 to 0x0015_FFFF
0x0812_0000 to 0x0815_FFFF
B2F4
0x0016_0000 to 0x0016_FFFF
0x0816_0000 to 0x0819_FFFF
B2F5
0x001A_0000 to 0x001D_FFFF
0x081A_0000 to 0x081D_FFFF
—
—
—
—
—
—
Table 217. Flash memory EEPROM data partition 3 address mapping
Block
Flash format addresses
Absolute addresses
D0_00
0x0090_0000 to 0x0090_3FFF
0x08F0_0000 to 0x08F0_3FFF
D0_01
0x0090_4000 to 0x0090_7FFF
0x08F0_4000 to 0x08F0_7FFF
D0_02
0x0090_8000 to 0x0090_BFFF
0x08F0_8000 to 0x08F0_BFFF
D0_03
0x0090_C000 to 0x0090_FFFF
0x08F0_C000 to 0x08F0_FFFF
Table 218. Flash memory HSM EEPROM Data Partition 3 address mapping
Block
Flash format addresses
Absolute addresses
D0_04
0x0098_0000 to 0x0098_3FFF
0x18F0_0000 to 0x18F0_3FFF
D0_05
0x0098_4000 to 0x0098_7FFF
0x18F0_4000 to 0x18F0_7FFF
17.3.2.17 User Test 0 register (UT0)
The User Test 0 register feature gives the user of the flash memory module the ability to
perform test features on the Flash.
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The User Test 0 register allows control of the way the Flash content check is performed. Bits
MRE, MRV and AIS of the User Test 0 register are not accessible when MCR.DONE or
UT0.AID are low. Reading returns indeterminate data while writing has no effect.
27
26
25
24
23
22
21
20
19
18
UTE
0
0
0
0
0
0
0
0
DDEF
CPR CPA CPE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
AISUS
R
28
0
SBCE1
Reset
29
AIBPE
W
30
NAIBP
31
R
Access: User Read/Write
SBCE
Address: 0x0054
AIS
AIE
0
0
0
0
0
0
0
0
0
0
0
W
Reset
VTD
0
MRE MRV
0
0
0
0
17
16
AID
1
Figure 146. User Test 0 register (UT0)
Table 219. UT0 field descriptions
490/2075
Field
Description
31
UTE
User Test Enable
This status bit gives indication when User Test is enabled.
All bits in UT0 and UM0–UM9 are locked when this bit is ‘0’.
This bit is not writable to a ‘1’, but may be cleared. The reset value is ‘0’.
To set UTE, write the password 0xF9F99999 to the UT0 register. The UTE
password is only accepted if PGM=0 and ERS=0 (Program and Erase are not
being requested).
UTE can only be cleared if AID=1, MRE=0 and AIE=0. While clearing UTE, writes
to set AIE or MRE are ignored.
30
SBCE
Double Bit Correction Enable
This bit, when high, enables to flag the information about any eventual ECC Double
Bit Correction in the Flash array (MCR.SBC and ADR). This is true in read mode
and in Array Integrity Check.
SBCE is also used as an Enable for interrupt signals created by the embedded
flash memory. ECC corrections that occur when SBCE is cleared are not logged.
23
SBCE1
Single Bit Correction Enable
This bit, when high, enables to flag the information about any eventual ECC Single
Bit Correction in the Flash array (MCR.SBC1 and ADR). This is true in read mode
and in Array Integrity Check.
SBCE1 is also used as an Enable for interrupt signals created by the embedded
flash memory. ECC corrections that occur when SBCE1 is cleared are not logged.
19
DDEF
Disable Data memory Edc post ecc error reporting to FCCU
This bit is used to disable the EEE error reporting when reading Data Memory.
Code Memory Edc post Ecc error reporting is not affected.
MCR.EEE is generated regarless of DDEF.
0 Data memory EEE error reporting to FCCU is enabled.
1 Data memory EEE error reporting to FCCU is disabled.
RM0483 Rev 5
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Embedded flash memory
Table 219. UT0 field descriptions (continued)
Field
Description
18
CPR
Customer Programmable Read Voltage and Reference Detection
This bit is used to control the error generation for the Customer Programmable
Detection area in the UTEST block when reading Read-While-Read partition 0.
This bit is used to control the error generation for the Customer Programmable
Detection area in the RWR1_UTEST block when reading Read-While-Read
partition 1. If this bit is set and the Customer Programmable Detection location in
UTEST is read, a Read Voltage and Reference Error detection is set.
0 Customer Programmable Read Voltage and Reference Detection Error is not
enabled
1 Customer Programmable Read Voltage and Reference Detection Error is
enabled.
17
CPA
Customer Programmable Address Encode Detection
This bit is used to control the error generation for the Customer Programmable
Detection area in the UTEST block when reading Read-While-Read partition 0.
This bit is used to control the error generation for the Customer Programmable
Detection area in the RWR1_UTEST block when reading Read-While-Read
partition 1. If this bit is set, and the Customer Programmable Detection location in
UTEST is read an Address Encode Error detection is set.
0 Customer Programmable Address Encode Detection Error is not enabled
1 Customer Programmable Address Encode Detection Error is enabled
16
CPE
Customer Programmable EDC after ECC Detection
This bit is used to control the error generation for the Customer Programmable
Detection area in the UTEST block when reading Read-While-Read partition 0.
This bit is used to control the error generation for the Customer Programmable
Detection area in the RWR1_UTEST block when reading Read-While-Read
partition 1. If this bit is set, and the Customer Programmable Detection location in
UTEST is read a EDC after ECC Error detection is set.
0 Customer Programmable EDC after ECC Detection Error is not enabled
1 Customer Programmable EDC after ECC Detection Error is enabled
12
VTD
Vth Distribution
To enable Vth Distribution, VTD may be set. Effective setting of this bit is allowed
when SoC has been brought into Failure Analysis Mode. When Vth Distribution is
enabled, multiple run are needed to assess the Vth status of the cells belonging to
selected blocks. At the end of each run NAIPB has to be checked and if equals to
‘1’ it has to be cleared to start an increased voltage step run. See NAIBP
description for more information.
0 Vth Distribution is not enabled.
1 Vth Distribution is enabled.
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Table 219. UT0 field descriptions (continued)
492/2075
Field
Description
9
NAIBP
Next Array Integrity Break Point
If AIBPE is set, NAIBP is set once a single bit correction (if enabled) or double bit
detection is noted during the Array Integrity test. NAIBP is not writable to ‘1’ but
may be cleared to ‘0’. Clearing NAIBP to ‘0’ enables the Array Integrity operation to
be re-started after a breakpoint is encountered. If the Array Integrity operation
completes without encountering another correction or detection, AID is set with
NAIBP remaining ‘0’.
If VTD is set, NAIBP is set once a voltage step run has been completed during the
voltage sweep in Vth Distribution. NAIBP is not writable to ‘1’ but may be cleared to
‘0’. Clearing NAIBP to ‘0’ enables the Vth Distribution run to be re-started with an
increased voltage step. If the Vth Distribution completes the last voltage step run,
AID is set with NAIBP remaining ‘0’.
0 Array Integrity-Vth Distribution is not currently at a break point.
1 Array Integrity-Vth Distribution is at a break point.
8
AIBPE
Array Integrity Break Point Enable
To enable breakpoints during an Array Integrity test, AIBPE may be set. When
breakpoints are enabled, if the run has been started with MCR.ERR (and
MCR.SBC when UT0.SBCE=1) flag cleared, on the eventual occurrence of a
breakpoint condition, MCR flags and ADR value may be updated. See NAIBP
description for more information about Array Integrity breakpoints.
0 Array Integrity breakpoints are not enabled.
1 Array Integrity breakpoints are enabled during Array Integrity Checks.
6
AISUS
Array Integrity Suspend
AISUS toggles Suspend of an Array Integrity - Margin Read Operation.
AISUS can be written to ‘1’ only when AID is low
AISUS can be written to ‘0’ only when AID is high.
Attempting to Write AISUS and AIE on the same clock cycle results in only AIE
being written.
0 Array Integrity sequence not suspended.
1 Array Integrity sequence is suspended.
5
MRE
Margin Read Enable
MRE enables margin reads to be done.
MRE combined with MRV enables User Margin mode reads to be done.
Margin reads run on a block-by-block basis in linear address sequence selected by
SEL0, SEL1 and SEL2.
This bit is not accessible when MCR.DONE or UT0.AID are low or if AISUS or
NAIBP are high: reading returns indeterminate data while writing has no effect.
0 Margin Read is not enabled.
1 Margin Read is enabled.
4
MRV
Margin Read Value
If MRE is high, MRV selects the margin level that is being checked. Margin can be
checked to an erased level (MRV=1) or to a programmed level (MRV=0).
This bit is not accessible whenever MCR.DONE or UT0.AID are low or if AISUS or
NAIBP are high: reading returns indeterminate data while writing has no effect.
0 Zero’s (programmed) margin reads are requested (if MRE=1).
1 One’s (erased) margin reads are requested (if MRE=1).
RM0483 Rev 5
RM0483
Embedded flash memory
Table 219. UT0 field descriptions (continued)
Field
Description
2
AIS
Array Integrity Sequence
AIS determines the address sequence to be used during Array Integrity checks.
The default AIS=0 checks the read propagation paths along proprietary sequences
followed by user code.
The sequential run sequence time is significantly shorter than the proprietary
sequence.
AIS is not writable if AIE is high.
This bit is not accessible whenever MCR.DONE or UT0.AID are low: reading
returns indeterminate data while writing has no effect.
0 Array Integrity sequence is proprietary sequence.
1 Array Integrity sequence is sequential.
1
AIE
Array Integrity Enable
Setting AIE to ‘1’ starts the Array Integrity Check and the Margin Read on all
selected blocks.
The sequence is selected by AIS and the MISR (UM0–UM9) is checked on
completion to determine if a correct signature is obtained.
AIE can be set only if MCR.ERS, MCR.PGM and MCR.EHV are all low.
AIE is not simultaneously writable to ‘1’ while UTE is being cleared to ‘0’.
Clearing AIE terminates the check when an Array Integrity operation finishes
(AID=1) and aborts the check when and Array Integrity operation is ongoing
(AID=0).
AIE remains ‘1’ when the Array Integrity Check - Margin read are suspended or are
in breakpoint and cannot be cleared. (AIE can be cleared if NAIBP=0 and AISU=0)
0 Array Integrity Check and Margin Read and are not enabled.
1 Array Integrity Check and Margin Read are enabled.
0
AID
Array Integrity Done
AID is set to indicate that the Array Integrity Check - Margin Read is complete and
the MISR (UM0–9) can be checked.
AID may also assert if breakpoints are enabled (AIBPE is set) and the breakpoint
condition is met. AID may also assert if Suspend is set (AISUS 0–1).
AID can not be written, and is status only.
0 Array Integrity Check is on-going.
1 Array Integrity Check is done.
17.3.2.18 User Multiple Input Signature registers
The Multiple Input Signature registers allow evaluation of the Array Integrity or Margin Read
run on a block-by-block basis by accumulating signatures from data bit fields.
These registers are not accessible whenever MCR.DONE or UT0.AID are low. Reading
returns indeterminate data while writing has no effect.
The registers can be written in order to seed signatures before starting an AIC or MR
operation.
Note:
Do not write to the MISR registers during an Array Integrity operation (including Suspend or
Breakpoint) as it may alter the final signature in an unpredictable way.
If reads extend into an invalid address location during address sequencing (that is greater
than the maximum address for a given array size), reads are still executed to the array but
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RM0483
the results are not deterministic: MISR registers are not recalculated and the previous value
is retained.
17.3.2.18.1 User Multiple Input Signature 0 register (UM0)
UM0 represents bits 31–0 of the whole 288-bit word (4 doublewords including ECC).
Address: 0x0058
MISR23
MISR22
MISR21
MISR20
MISR19
MISR18
MISR17
MISR16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MISR7
MISR6
MISR5
MISR4
MISR3
MISR2
MISR1
MISR0
16
MISR24
17
MISR8
18
MISR25
19
MISR9
20
MISR26
21
MISR10
22
MISR27
23
MISR11
24
MISR28
25
MISR12
26
MISR29
Reset
27
MISR13
W
28
MISR30
R
29
MISR14
Reset
30
MISR31
W
31
MISR15
R
Access: User Read/Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 147. User Multiple Input Signature 0 register (UM0)
Table 220. UM0 field descriptions
Field
Description
31:0
MISR[31:0]
Multiple input signature 31–0
MISR registers accumulate a signature from an array integrity event. The MISR
captures all data fields, as well as ECC fields and the ECC error signal. Data (read
and ECC) in the MISR represents corrected data (if required) captured after ECC
logic is applied.
17.3.2.18.2 User Multiple Input Signature 1 register (UM1)
UM1 represents bits 63–32 of the whole 288-bit word (4 doublewords including ECC).
Address: 0x005C
MISR55
MISR54
MISR53
MISR52
MISR51
MISR50
MISR49
MISR48
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MISR39
MISR38
MISR37
MISR36
MISR35
MISR34
MISR33
MISR32
16
MISR56
17
MISR40
18
MISR57
19
MISR41
20
MISR58
21
MISR42
22
MISR59
23
MISR43
24
MISR60
25
MISR44
26
MISR61
Reset
27
MISR45
W
28
MISR62
R
29
MISR46
Reset
30
MISR63
W
31
MISR47
R
Access: User Read/Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 148. User Multiple Input Signature 1 register (UM1)
494/2075
RM0483 Rev 5
RM0483
Embedded flash memory
Table 221. UM1 field descriptions
Field
Description
31:0
MISR[63:32]
Multiple input signature 63–32
MISR registers accumulate a signature from an array integrity event. The MISR
captures all data fields, as well as ECC fields and the ECC error signal. Data (read
and ECC) in the MISR represents corrected data (if required) captured after ECC
logic is applied.
17.3.2.18.3 User Multiple Input Signature 2 register (UM2)
UM2 represents bits 95–64 of the whole 288-bit word (4 doublewords including ECC).
Address: 0x0060
MISR87
MISR86
MISR85
MISR84
MISR83
MISR82
MISR81
MISR80
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MISR71
MISR70
MISR69
MISR68
MISR67
MISR66
MISR65
MISR64
16
MISR88
17
MISR72
18
MISR89
19
MISR73
20
MISR90
21
MISR74
22
MISR91
23
MISR75
24
MISR92
25
MISR76
26
MISR93
Reset
27
MISR77
W
28
MISR94
R
29
MISR78
Reset
30
MISR95
W
31
MISR79
R
Access: User Read/Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 149. User Multiple Input Signature 2 register (UM2)
Table 222. UM2 field descriptions
Field
Description
31:0
MISR[95:64]
Multiple input signature 95–64
MISR registers accumulate a signature from an array integrity event. The MISR
captures all data fields, as well as ECC fields and the ECC error signal. Data (read
and ECC) in the MISR represents corrected data (if required) captured after ECC
logic is applied.
17.3.2.18.4 User Multiple Input Signature 3 register (UM3)
UM3 represents bits 127–96 of the whole 288-bit word (4 doublewords including ECC).
RM0483 Rev 5
495/2075
532
Embedded flash memory
RM0483
Address: 0x0064
MISR119
MISR118
MISR117
MISR116
MISR115
MISR114
MISR113
MISR112
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MISR103
MISR102
MISR101
MISR100
MISR99
MISR98
MISR97
MISR96
16
MISR120
17
MISR104
18
MISR121
19
MISR105
20
MISR122
21
MISR106
22
MISR123
23
MISR107
24
MISR124
25
MISR108
26
MISR125
Reset
27
MISR109
W
28
MISR126
R
29
MISR110
Reset
30
MISR127
W
31
MISR111
R
Access: User Read/Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 150. User Multiple Input Signature 3 register (UM3)
Table 223. UM3 field descriptions
Field
Description
Multiple input signature 127–96
MISR registers accumulate a signature from an array integrity event. The MISR
31:0
captures all data fields, as well as ECC fields and the ECC error signal. Data (read
MISR[127:96]
and ECC) in the MISR represents corrected data (if required) captured after ECC
logic is applied.
17.3.2.18.5 User Multiple Input Signature 4 register (UM4)
UM4 represents bits 159–128 of the whole 288-bit word (4 doublewords including ECC).
Address: 0x0068
MISR151
MISR150
MISR149
MISR148
MISR147
MISR146
MISR145
MISR144
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MISR135
MISR134
MISR133
MISR132
MISR131
MISR130
MISR129
MISR128
16
MISR152
17
MISR136
18
MISR153
19
MISR137
20
MISR154
21
MISR138
22
MISR155
23
MISR139
24
MISR156
25
MISR140
26
MISR157
Reset
27
MISR141
W
28
MISR158
R
29
MISR142
Reset
30
MISR159
W
31
MISR143
R
Access: User Read/Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 151. User Multiple Input Signature 4 register (UM4)
496/2075
RM0483 Rev 5
RM0483
Embedded flash memory
Table 224. UM4 field descriptions
Field
Description
31:0
MISR[159:128]
Multiple input signature 159–128
MISR registers accumulate a signature from an array integrity event. The MISR
captures all data fields, as well as ECC fields and the ECC error signal. Data
(read and ECC) in the MISR represents corrected data (if required) captured after
ECC logic is applied.
17.3.2.18.6 User Multiple Input Signature 5 register (UM5)
UM5 represents bits 191–160 of the whole 288-bit word (4 doublewords including ECC).
Address: 0x006C
MISR183
MISR182
MISR181
MISR180
MISR179
MISR178
MISR177
MISR176
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MISR167
MISR166
MISR165
MISR164
MISR163
MISR162
MISR161
MISR160
16
MISR184
17
MISR168
18
MISR185
19
MISR169
20
MISR186
21
MISR170
22
MISR187
23
MISR171
24
MISR188
25
MISR172
26
MISR189
Reset
27
MISR173
W
28
MISR190
R
29
MISR174
Reset
30
MISR191
W
31
MISR175
R
Access: User Read/Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 152. User Multiple Input Signature 5 register (UM5)
Table 225. UM5 field descriptions
Field
Description
31:0
MISR[191:160]
Multiple input signature 191–160
MISR registers accumulate a signature from an array integrity event. The MISR
captures all data fields, as well as ECC fields and the ECC error signal. Data
(read and ECC) in the MISR represents corrected data (if required) captured
after ECC logic is applied.
17.3.2.18.7 User Multiple Input Signature 6 register (UM6)
UM6 represents bits 223–192 of the whole 288 bits word (4 doublewords including ECC).
RM0483 Rev 5
497/2075
532
Embedded flash memory
RM0483
Address: 0x0070
MISR215
MISR214
MISR213
MISR212
MISR211
MISR210
MISR209
MISR208
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MISR199
MISR198
MISR197
MISR196
MISR195
MISR194
MISR193
MISR192
16
MISR216
17
MISR200
18
MISR217
19
MISR201
20
MISR218
21
MISR202
22
MISR219
23
MISR203
24
MISR220
25
MISR204
26
MISR221
Reset
27
MISR205
W
28
MISR222
R
29
MISR206
Reset
30
MISR223
W
31
MISR207
R
Access: User Read/Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 153. User Multiple Input Signature 6 register (UM6)
Table 226. UM6 field descriptions
Field
Description
31:0
MISR[223:192]
Multiple input signature 223–192
MISR registers accumulate a signature from an array integrity event. The MISR
captures all data fields, as well as ECC fields and the ECC error signal. Data (read
and ECC) in the MISR represents corrected data (if required) captured after ECC
logic is applied.
17.3.2.18.8 User Multiple Input Signature 7 register (UM7)
UM7 represents bits 255–224 of the whole 288 bits word (4 doublewords including ECC).
Address: 0x0074
MISR247
MISR246
MISR245
MISR244
MISR243
MISR242
MISR241
MISR240
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MISR231
MISR230
MISR229
MISR228
MISR227
MISR226
MISR225
MISR224
16
MISR248
17
MISR232
18
MISR249
19
MISR233
20
MISR250
21
MISR234
22
MISR251
23
MISR235
24
MISR252
25
MISR236
26
MISR253
Reset
27
MISR237
W
28
MISR254
R
29
MISR238
Reset
30
MISR255
W
31
MISR239
R
Access: User Read/Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 154. User Multiple Input Signature 7 register (UM7)
498/2075
RM0483 Rev 5
RM0483
Embedded flash memory
Table 227. UM7 field descriptions
Field
Description
31:0
MISR[255:224]
Multiple input signature 255–224
MISR registers accumulate a signature from an array integrity event. The MISR
captures all data fields, as well as ECC fields and the ECC error signal. Data
(read and ECC) in the MISR represents corrected data (if required) captured after
ECC logic is applied.
17.3.2.18.9 User Multiple Input Signature 8 register (UM8)
UM8 represents the ECC parity bits of the whole 288-bits word (8 parity bits for each of the 4
doublewords).
Address: 0x0078
MISR279
MISR278
MISR277
MISR276
MISR275
MISR274
MISR273
MISR272
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MISR263
MISR262
MISR261
MISR260
MISR259
MISR258
MISR257
MISR256
16
MISR280
17
MISR264
18
MISR281
19
MISR265
20
MISR282
21
MISR266
22
MISR283
23
MISR267
24
MISR284
25
MISR268
26
MISR285
Reset
27
MISR269
W
28
MISR286
R
29
MISR270
Reset
30
MISR287
W
31
MISR271
R
Access: User Read/Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 155. User Multiple Input Signature 8 register (UM8)
Table 228. UM8 field descriptions
Field
Description
31:0
MISR[287:256]
Multiple input signature 287–256
MISR registers accumulate a signature from an array integrity event. The MISR
captures all data fields, as well as ECC fields and the ECC error signal. Data (read
and ECC) in the MISR represents corrected data (if required) captured after ECC
logic is applied.
17.3.2.18.10 User Multiple Input Signature 9 register (UM9)
UM9 represents the ERR bits.
RM0483 Rev 5
499/2075
532
Embedded flash memory
RM0483
Address: 0x007C
MISR311
MISR310
MISR309
MISR308
MISR307
MISR306
MISR305
MISR304
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MISR295
MISR294
MISR293
MISR292
MISR291
MISR290
MISR289
MISR288
16
MISR312
17
MISR296
18
MISR313
19
MISR297
20
MISR314
21
MISR298
22
MISR315
23
MISR299
24
MISR316
25
MISR300
26
MISR317
Reset
27
MISR301
W
28
MISR318
R
29
MISR302
Reset
30
MISR319
W
31
MISR303
R
Access: User Read/Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 156. User Multiple Input Signature 9 register (UM9)
Table 229. UM9 field descriptions
Field
Description
31:0
MISR[319:288]
Multiple input signature 319–288
MISR registers accumulate a signature from an array integrity event. The MISR
captures all data fields, as well as ECC fields and the ECC error signal. Data
(read and ECC) in the MISR represents corrected data (if required) captured
after ECC logic is applied.
17.3.2.19 Over-program protection registers
Over-program protection prevents blocks from being over-programmed. These registers
show the over-program protection status. See Section 17.4.3.1.2: Over-programming
protection (OPP) enable.
17.3.2.19.1 Over-program protection 0 register (OPP0)
The Low/Mid Address Space is covered by the Over Program Protection 0 (OPP0) register.
Address: 0x0080
R
Access: User Read
31
30
29
28
27
26
25
24
23
0
0
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
22
21
20
19
18
17
16
—
—
—
—
—
—
—
6
5
4
3
2
1
0
—
—
—
—
—
—
—
LOWOPP
W
Reset(1)
R
MIDOPP
W
Reset(1)
—
—
—
—
—
—
—
—
—
1. A reset value of “—” indicates that the value is set at the factory and can vary among different applications
Figure 157. Over-program protection 0 register (OPP0)
500/2075
RM0483 Rev 5
RM0483
Embedded flash memory
Table 230. OPP0 field descriptions
Field
Description
Low address space Over Program Protection
The block numbering for the Low Blocks starts at LOWOPP[0] with 16 KB block
region (if available), then the 32 KB block region (if available), and lastly the
64 KB block region (if available). This continues until all blocks are accounted for.
29:16
LOWOPP
The LOWOPP field is not writable, and is status only.
The default value of the LOWOPP bits is not over-programming protected. When
blocks are not present (due to configuration or total memory size), the LOWOPP
bits default to not over-programming protected and remain 0.
0 Low Address Space Block is unprotected from over-programming.
1 Low Address Space Block is protected from over-programming.
Mid address space Over Program Protection
The block numbering for the Mid Blocks starts at MIDOPP[0] with 16 KB block
region (if available), then the 32 KB block region (if available), and lastly the
64 KB block region (if available). This continues until all blocks are accounted for.
15:0
MIDOPP
The MIDOPP field is not writable, and is status only.
The default value of the MIDOPP bits is not over-programming protected. When
blocks are not present (due to configuration or total memory size), the MIDOPP
bits default to not over-programming protected, and remain 0.
0 Mid Address Space Block is unprotected from over-programming.
1 Mid Address Space Block is protected from over-programming.
17.3.2.19.2 Over-program protection 1 register (OPP1)
The High Address Space is covered by the Over Program Protection 1 (OPP1) register.
Address: 0x0084
R
Access: User Read
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
W
(1)
Reset
R
HIGHOPP
W
Reset(1)
—
—
—
—
—
—
—
—
—
1. A reset value of “—” indicates that the value is set at the factory and can vary among different applications
Figure 158. Over-program protection 1 register (OPP1)
RM0483 Rev 5
501/2075
532
Embedded flash memory
RM0483
Table 231. OPP1 field descriptions
Field
Description
High address space Over Program Protection
The block numbering for the High Blocks starts at HIGHOPP[0] with 16 KB block
region (if available), then the 32 KB block region (if available), and lastly the
64 KB block region (if available). This continues until all blocks are accounted for.
15:0
HIGHOPP
The HIGHOPP field is not writable, and is status only.
The default value of the HIGHOPP bits is not over-programming protected. When
blocks are not present (due to configuration or total memory size), the HIGHOPP
bits default to not over-programming protected and remain 0.
0 High Address Space Block is unprotected from over-programming.
1 High Address Space Block is protected from over-programming.
17.3.2.19.3 Over-program protection 2 register (OPP2)
The A256K Address Space Block is covered by the Over Program Protection 2 (OPP2)
register.
Address: 0x0088
31
Access: User Read
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
A256KOPP
W
Reset(1)
—
—
—
—
—
—
—
15
14
13
12
11
10
9
R
—
—
—
—
—
—
—
—
—
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
A256KOPP
W
Reset(1)
—
—
—
—
—
—
—
—
—
1. A reset value of “—” indicates that the value is set at the factory and can vary among different applications
Figure 159. Over-program protection 2 register (OPP2)
Table 232. OPP2 field descriptions
502/2075
Field
Description
31:0
A256KOPP
256K Address Space Block Over Program Protection A256KOPP[31:0]
The block numbering for the 256 KB Blocks starts at A256KOPP[0] and continues
until all blocks are accounted for.
The A256KOPP field is not writable, and is status only.
The default value of the A256KOPP bits is not over-programming protected. When
blocks are not present (due to configuration or total memory size), the A256KOPP
bits default to not over-programming protected and remain 0.
0 A256K Address Space Block is unprotected from over-programming.
1 A256K Address Space Block is protected from over-programming.
RM0483 Rev 5
RM0483
Embedded flash memory
17.3.2.19.4 Over-program protection 3 register (OPP3)
The 256K high Address Space is covered by the Over Program Protection 3 (OPP3)
register.
Address: 0x008C
31
Access: User Read
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
A256KOPP
W
Reset(1)
—
—
—
—
—
—
—
15
14
13
12
11
10
9
R
—
—
—
—
—
—
—
—
—
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
A256KOPP
W
Reset(1)
—
—
—
—
—
—
—
—
—
1. A reset value of “—” indicates that the value is set at the factory and can vary among different applications
Figure 160. Over-program protection 3 register (OPP3)
Table 233. OPP3 field descriptions
Field
Description
31:0
A256KOPP
256K Address space Over Program Protection A256KOPP[63:32]
The block numbering for the 256 KB Blocks starts at A256KOPP[32] and
continues until all blocks are accounted for.
The A256KOPP field is not writable, and is status only.
The default value of the A256KOPP bits is not over-programming
protected. When blocks are not present (due to configuration or total
memory size), the A256KOPP bits default to not over-programming
protected and remain 0.
0 A256K Address Space Block is unprotected from over-programming.
1 A256K Address Space Block is protected from over-programming.
17.3.2.20 Test Mode Disable Password Check register (TMD)
The Test Mode Disable Password Check (TMD) register provides a means of entering the
password to be matched with the one stored in UTEST location in order to allow
manufacturer access to protected Test Mode blocks by writing 0x2D3C_4B5A in the Test
Mode Disable Seal location.
RM0483 Rev 5
503/2075
532
Embedded flash memory
RM0483
Address: 0x0090
31
Access: User Write
30
29
28
27
26
25
24
23
R
0
W
PWD
Reset
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
0
W
Reset
22
PWD
0
0
0
0
0
0
0
0
0
Figure 161. Test Mode Disable Password Check register (TMD)
Table 234. TMD field descriptions
Field
Description
31:0
PWD
The Test Mode Disable Check register is used as a location to provide a password
challenge to unlock blocks selected to be sealed as part of the Test Mode Disable
seal mechanism. Please see Section 17.4.6.2: Test Mode Disable for more
information.
Writes to the register have no effect except for a password challenge.
Reads to this register always returns 0.
The register’s reset value is 0.
Note:
17.3.2.21 HSM Alternate selector registers
HSM Alternate selectors assign blocks from default to ALTERNATE Program & Erase
interface. These registers show the HSM Alternate assignment status. See Section 17.4.4:
Alternate program and erase interface.
17.3.2.21.1 HSM ALT-SEL register 0 (ALTSEL0)
The Low/Mid Address Space is assigned between MAIN and ALT Interface. Through the
HSM ALT-SEL register it is possible to read the actual status of the assignment.
Address: 0x0094
R
Access: User Read
31
30
0
0
29
28
27
26
25
24
23
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
22
21
20
19
18
17
16
—
—
—
—
—
—
—
6
5
4
3
2
1
0
—
—
—
—
—
—
—
LOWALTSEL
W
Reset(1)
R
MIDALTSEL
W
Reset(1)
—
—
—
—
—
—
—
—
—
1. A reset value of “—” indicates that the value is set at the factory and can vary among different applications
Figure 162. HSM ALT-SEL register 0 (ALTSEL0)
504/2075
RM0483 Rev 5
RM0483
Embedded flash memory
Table 235. ALTSEL0 field descriptions
Field
Description
29:16
LOWALTSEL
Low address space HSM Alternate Select
The block numbering for the Low Blocks starts at LOWALTSEL[0] with 16 KB
block region (if available), then the 32 KB block region (if available), and lastly
the 64 KB block region (if available). This continues until all blocks are
accounted for.
The LOWALTSEL field is not writable, and is status only.
When blocks are not present (due to configuration or total memory size), the
LOWALTSEL bits remain 0.
0 Low Address Space Block is assigned to Main interface.
1 Low Address Space Block is assigned to Alternate interface.
15:0
MIDALTSEL
Mid address space HSM Alternate Select 0
The block numbering for the Mid Blocks starts at MIDALTSEL[0] with 16 KB
block region (if available), then the 32 KB block region (if available), and lastly
the 64 KB block region (if available). This continues until all blocks are
accounted for.
The MIDALTSEL field is not writable, and is status only.
When blocks are not present (due to configuration or total memory size), the
MIDALTSEL bits remain 0.
0 Mid Address Space Block is assigned to Main interface.
1 Mid Address Space Block is assigned to Alternate interface.
17.3.2.21.2 HSM ALT-SEL register 1 (ALTSEL1)
The High Address Space is assigned between MAIN and ALT Interface. Through the HSM
ALT-SEL register it is possible to read the actual status of the assignment.
Address: 0x0098
R
Access: User Read
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
W
(1)
Reset
R
HIGHALTSEL
W
Reset(1)
—
—
—
—
—
—
—
—
—
1. A reset value of “—” indicates that the value is set at the factory and can vary among different applications
Figure 163. HSM ALT-SEL register 1 (ALTSEL1)
RM0483 Rev 5
505/2075
532
Embedded flash memory
RM0483
Table 236. ALTSEL1 field descriptions
Field
Description
15:0
HIGHALTSEL
High address space HSM Alternate Select
The block numbering for the High Blocks starts at HIGHALTSEL[0] with 16 KB
block region (if available), then the 32 KB block region (if available), and lastly the
64 KB block region (if available). This continues until all blocks are accounted for.
The HIGHALTSEL field is not writable, and is status only.
When blocks are not present (due to configuration or total memory size), the
HIGHALTSEL bits remain 0.
0 High Address Space Block is assigned to Main interface.
1 High Address Space Block is assigned to Alternate interface.
17.3.2.22 Erase Lock protection registers
Erase Lock protection prevents blocks from being erased. These registers show the Erase
Lock protection status. See Section 17.4.6.1: Modify protection.
17.3.2.22.1 Erase Lock Protection 0 register (ELOCK0)
The Low/Mid Address Space is covered by the Erase Lock Protection 0 (ELOCK0) register.
Address: 0x0100
31
Access: User Read
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
LOWELOCK
W
Reset(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
MIDELOCK
W
Reset(1)
—
—
—
—
—
—
—
—
—
1. A reset value of “—” indicates that the value is set at the factory and can vary among different applications
Figure 164. Erase Lock Protection 0 register (ELOCK0)
Table 237. ELOCK0 field descriptions
506/2075
Field
Description
31:16
LOWELOCK
Low address space Erase Lock Protection
The block numbering for the Low Blocks starts at LOWELOCK[0] with 16 KB
block region (if available), then the 32 KB block region (if available), and lastly
the 64 KB block region (if available). This continues until all blocks are
accounted for.
The LOWELOCK field is not writable, and is status only.
When blocks are not present (due to configuration or total memory size), the
LOWELOCK bits default is Erase Lock protected and remain 1.
0 Low Address Space Block is Erase unprotected.
1 Low Address Space Block is Erase protected.
RM0483 Rev 5
RM0483
Embedded flash memory
Table 237. ELOCK0 field descriptions (continued)
Field
Description
15:0
MIDELOCK
Mid address space Erase Lock Protection
The block numbering for the Mid Blocks starts at MIDELOCK[0] with 16 KB
block region (if available), then the 32 KB block region (if available), and lastly
the 64 KB block region (if available). This continues until all blocks are
accounted for.
The MIDELOCK field is not writable, and is status only.
When blocks are not present (due to configuration or total memory size), the
MIDELOCK bits default is Erase Lock protected and remain 1.
0 Mid Address Space Block is Erase unprotected.
1 Mid Address Space Block is Erase protected.
17.3.2.22.2 Erase Lock Protection 1 register (ELOCK1)
The High Address Space is covered by the Erase Lock Protection 1 (ELOCK1) register.
Address: 0x0104
R
Access: User Read
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
W
Reset(1)
R
HIGHELOCK
W
Reset(1)
—
—
—
—
—
—
—
—
—
1. A reset value of “—” indicates that the value is set at the factory and can vary among different applications
Figure 165. Erase Lock Protection 1 register (ELOCK1)
Table 238. ELOCK1 field descriptions
Field
Description
15:0
HIGHELOCK
High address space Erase Lock Protection
The block numbering for the High Blocks starts at HIGHELOCK[0] with 16 KB
block region (if available), then the 32 KB block region (if available), and lastly
the 64 KB block region (if available). This continues until all blocks are
accounted for.
The HIGHELOCK field is not writable, and is status only.
When blocks are not present (due to configuration or total memory size), the
HIGHELOCK bits default is Erase Lock protected and remain 1.
0 High Address Space Block is Erase unprotected.
1 High Address Space Block is Erase protected.
17.3.2.22.3 Erase Lock Protection 2 register (ELOCK2)
The 256K Address Space is covered by the Erase Lock Protection 2 (ELOCK2) register.
RM0483 Rev 5
507/2075
532
Embedded flash memory
RM0483
Address: 0x0108
31
Access: User Read
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
A256KELOCK
W
Reset(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
A256KELOCK
W
Reset(1)
—
—
—
—
—
—
—
—
—
1. A reset value of “—” indicates that the value is set at the factory and can vary among different applications
Figure 166. Erase Lock Protection 2 register (ELOCK2)
Table 239. ELOCK2 field descriptions
Field
Description
31:0
A256KELOCK
256K High address space Erase Lock Protection A256KELOCK[31:0]
The block numbering for the 256 KB Blocks starts at A256KELOCK[0] and
continues until all blocks are accounted for.
The A256KELOCK field is not writable, and is status only.
When blocks are not present (due to configuration or total memory size), the
A256KELOCK bits default is Erase Lock protected and remain 1.
0 A256K Address Space Block is Erase unprotected.
1 A256K Address Space Block is Erase protected.
17.3.2.22.4 Erase Lock protection 3 register (ELOCK3)
The 256K Address Space is covered by the Erase Lock Protection 3 (ELOCK3) register.
Address: 0x010C
31
Access: User Read
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
A256KELOCK
W
Reset(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
A256KELOCK
W
Reset(1)
—
—
—
—
—
—
—
—
—
1. A reset value of “—” indicates that the value is set at the factory and can vary among different applications
Figure 167. Erase Lock protection 3 register (ELOCK3)
508/2075
RM0483 Rev 5
RM0483
Embedded flash memory
Table 240. ELOCK3 field descriptions
Field
Description
31:0
A256KELOCK
256K High address space Erase Lock Protection A256KELOCK[63:32]
The block numbering for the 256 KB Blocks starts at A256KELOCK[32]
and continues until all blocks are accounted for.
The A256KELOCK field is not writable, and is status only.
When blocks are not present (due to configuration or total memory size),
the A256KELOCK bits default is Erase Lock protected and remain 1.
0 A256K Address Space Block is erase unprotected.
1 A256K Address Space Block is Erase protected.
17.3.2.23 Program Lock protection registers
Program Lock protection prevents blocks from being programmed. These registers show
the Program Lock protection status. See Section 17.4.6.1: Modify protection.
17.3.2.23.1 Program Lock Protection 0 register (PLOCK0)
The Low/Mid Address Space is covered by the Program Lock Protection 0 (PLOCK0)
register.
Address: 0x0110
31
Access: User Read
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
LOWPLOCK
W
Reset(1)
—
—
—
—
—
—
—
15
14
13
12
11
10
9
R
—
—
—
—
—
—
—
—
—
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
MIDPLOCK
W
Reset(1)
—
—
—
—
—
—
—
—
—
1. A reset value of “—” indicates that the value is set at the factory and can vary among different applications
Figure 168. Program Lock Protection 0 register (PLOCK0)
Table 241. PLOCK0 field descriptions
Field
Description
31:16
LOWPLOCK
Low address space Erase Lock Protection
The block numbering for the Low Blocks starts at LOWPLOCK[0] with 16 KB block
region (if available), then the 32 KB block region (if available), and lastly the 64 KB
block region (if available). This continues until all blocks are accounted for.
The LOWPLOCK field is not writable, and is status only.
When blocks are not present (due to configuration or total memory size), the
LOWPLOCK bits default is Program Lock protected and remain 1.
0 Low Address Space Block is Program unprotected.
1 Low Address Space Block is Program protected.
RM0483 Rev 5
509/2075
532
Embedded flash memory
RM0483
Table 241. PLOCK0 field descriptions (continued)
Field
Description
15:0
MIDPLOCK
Mid address space Erase Lock Protection
The block numbering for the Mid Blocks starts at MIDPLOCK[0] with 16 KB block
region (if available), then the 32 KB block region (if available), and lastly the 64 KB
block region (if available). This continues until all blocks are accounted for.
The MIDPLOCK field is not writable, and is status only.
When blocks are not present (due to configuration or total memory size), the
MIDPLOCK bits default is Program Lock protected and remain 1.
0 Mid Address Space Block is Program unprotected.
1 Mid Address Space Block is Program protected.
17.3.2.23.2 Program Lock Protection 1 register (PLOCK1)
The High Address Space is covered by the Program Lock Protection 1 (PLOCK1) register.
Address: 0x0114
R
Access: User Read
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
W
Reset(1)
R
HIGHPLOCK
W
Reset(1)
—
—
—
—
—
—
—
—
—
1. A reset value of “—” indicates that the value is set at the factory and can vary among different applications
Figure 169. Erase Lock Protection 1 register (PLOCK1)
Table 242. PLOCK1 field descriptions
Field
Description
15:0
HIGHPLOCK
High address space Program Lock Protection
The block numbering for the High Blocks starts at HIGHPLOCK[0] with 16 KB
block region (if available), then the 32 KB block region (if available), and lastly
the 64 KB block region (if available). This continues until all blocks are
accounted for.
The HIGHPLOCK field is not writable, and is status only.
When blocks are not present (due to configuration or total memory size), the
HIGHPLOCK bits default is Program Lock protected and remain 1.
0 High Address Space Block is Program unprotected.
1 High Address Space Block is Program protected.
17.3.2.23.3 Program Lock Protection 2 register (PLOCK2)
The 256K Address Space is covered by the Program Lock Protection 2 (PLOCK2) register.
510/2075
RM0483 Rev 5
RM0483
Embedded flash memory
Address: 0x0118
Access: User Read
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
A256KPLOCK
W
Reset(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
A256KPLOCK
W
Reset(1)
—
—
—
—
—
—
—
—
—
1. A reset value of “—” indicates that the value is set at the factory and can vary among different applications
Figure 170. Program Lock Protection 2 register (PLOCK2)
Table 243. PLOCK2 field descriptions
Field
Description
31:0
A256KPLOCK
256K High address space Program Lock Protection A256KPLOCK[31:0]
The block numbering for the 256 KB Blocks starts at A256KPLOCK[0] and
continues until all blocks are accounted for.
The A256KPLOCK field is not writable, and is status only.
When blocks are not present (due to configuration or total memory size), the
A256KPLOCK bits default is Program Lock protected and remain 1.
0 A256K Address Space Block is Program unprotected.
1 A256K Address Space Block is Program protected.
17.3.2.23.4 Program Lock protection 3 register (PLOCK3)
The 256K Address Space is covered by the Program Lock Protection 3 (PLOCK3) register.
Address: 0x011C
31
Access: User Read
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
A256KPLOCK
W
Reset(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
A256KPLOCK
W
Reset(1)
—
—
—
—
—
—
—
—
—
1. A reset value of “—” indicates that the value is set at the factory and can vary among different applications
Figure 171. Program Lock protection 3 register (PLOCK3)
RM0483 Rev 5
511/2075
532
Embedded flash memory
RM0483
Table 244. PLOCK3 field descriptions
Field
Description
31:0
A256KPLOCK
256K High address space Program Lock Protection A256KPLOCK[63:32]
The block numbering for the 256 KB Blocks starts at A256KPLOCK[32] and
continues until all blocks are accounted for.
The A256KPLOCK field is not writable, and is status only.
When blocks are not present (due to configuration or total memory size), the
A256KPLOCK bits default is Program Lock protected and remain 1.
0 A256K Address Space Block is Program unprotected.
1 A256K Address Space Block is Program protected.
17.3.2.24 Parallel Address register (ADR2)
The Parallel Address register provides the first failing address in the event of module
failures (ECC) or the first address at which ECC single error correction occurs, when Reads
are performed from Read While Read 1 interface. ADR2 captures the first failing address for
the modes listed in Table 246 according to the priority rules in Table 247.
Address: 0x0134
R
Access: User Read
31
30
29
28
27
26
25
24
23
22
21
20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
19
18
17
16
0
0
0
0
3
2
1
0
0
0
0
0
0
0
PADR
W
Reset
R
PADR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 172. Parallel Address register (ADR2)
Table 245. ADR2 field descriptions
512/2075
Field
Description
23:3
PADR
Parallel Address
The Address register provides the first failing address in the event of ECC
Uncorrectable error (MCR2.PEER set) or the first failing address in the event of
RWW error (MCR2.PRWE set). The Address register also provides the first
address at which a ECC correction occurs (MCR2.PSBC or MCR2.PSBC1, or
both are set) if the SoC is configured to show this feature through UT0.SBCE or
UT0.SBCE1, or both.
The ECC uncorrectable error detection takes the highest priority, followed by the
RWW error, and the ECC error corrections. When accessed, PADR provides the
address related to the first event occurred with the highest priority.
In case of a simultaneous ECC Events Detection, bits PADR[4] and PADR[3]
output ‘0’.
In Read and RWW Modes PADR can be updated on Error belonging to the
address space of the primary Read-While-Read Partition 1.
Address given is in Flash format and has to be intended as in the flash memory
Map.
RM0483 Rev 5
RM0483
Embedded flash memory
Table 246. ADR2 update mode list
Mode
Update on error
Note
Read
ECC Uncorrectable Error Detection, ECC Single
Error Correction (if UT0.SBCE1=1)
—
RWW
Read-While-Write error
User Test
In RWW all Read and Modify
cause of update on error may also
occur
With Break Point enabled
ECC Uncorrectable Error Detection, ECC Single (UT0.AIBPE=1), ADR requires
Error Correction (if UT0.SBCE1=1)
MCR.ERR and MCR.SBC to be
cleared
Table 247. ADR2 content: priority list
Priority level
Error flag
ADR2 content
1
MCR2.PEER = 1
Address of first ECC Uncorrectable Error
2
MCR2.PRWE = 1
Address of first RWW Error
3
MCR2.PSBC1 = 1
Address of first ECC Single Error Correction
For the address mapping, refer to Section 17.3.2.16: Address register (ADR) description.
17.4
Functional description
This chapter describes the details of all the modes of operation available to the flash
memory module.
17.4.1
Reset
A reset is the highest priority operation for the flash memory module and terminates all other
operations.
The flash memory module uses reset to initialize register and status bits to their default reset
values. If the flash memory module is executing a Program or Erase operation
(MCR.PGM=1 or MCR.ERS=1) and a reset is issued, the operation is immediately
terminated and the module disables the high voltage circuits.Reset terminates all operations
and forces the flash memory module into Read mode ready to receive Read/Write
accesses.
Warning:
Reset and Power-Off must not be used as a systematic way
to terminate a Program or Erase operation.
After reset is negated Read register access may be performed, although registers that
require updating from shadow information or other inputs may not read updated values until
MCR.DONE transforms. MCR.DONE may be polled to determine if the flash memory
module has transitioned out of reset. Note that the registers cannot be written until
MCR.DONE is high.
RM0483 Rev 5
513/2075
532
Embedded flash memory
17.4.2
RM0483
Read mode
Read mode is the active mode of operation of the flash memory module in which the Flash
array can be read or ‘written’ (the so-called Interlock Write), or the Flash registers can be
read or written.
The flash memory module enters Read mode when exiting from reset. The default state of
the flash memory module is Read mode.
The main spaces (Low, Mid, High, and 256K) and UTEST address space of Flash array can
only be read in Read mode.
Flash memory module is in Read mode, granting the same access time, under the following
conditions:
17.4.2.1
•
The Read state is active when the module is enabled (User Mode Read)
•
The Read state is active when MCR.ERS and MCR.ESUS are high and MCR.PGM is
low (Erase Suspend)
•
The Read state is active when MCR.PGM and MCR.PSUS are high (Program
Suspend)
•
The Read state is active when MCR.PGM or MCR.ERS are high and High Voltage
operation is ongoing on one partition, thus MCR.EHV is high (condition referred to as
Read-While-Write). In this case reads done on the other partitions are allowed, while
reads done to the partition being operated on (either Erase or Program) result in an
error with MCR.RWE set and the data read back possibly being random including the
possibility of ECC errors.
•
The Read state is active when MCRA.ERSA and MCRA.ESUSA are high and
MCRA.PGMA is low (Alternate Erase Suspend)
•
The Read state is active when MCRA.PGMA and MCRA.PSUSA are high (Alternate
Program Suspend)
•
The Read state is active when MCRA.PGMA or MCRA.ERSA are high and High
Voltage operation is ongoing on one partition, thus MCRA.EHVa is high (condition
referred to as Alternate Read-While-Write). In this case reads done on the other
partitions are allowed, while reads done to the partition being operated on (either
Alternate Erase or Alternate Program) result in an error with MCRA.RWEA set and the
data read back possibly being random including the possibility of ECC errors.
Read While Read
Flash memory module is organized in Two independent Read interfaces. Each Read
interface is associated exclusively to a specific group of Read While Write Partitions. Flash
memory module supports independent and Parallel Read access through the Two
interfaces, namely Read-While-Read. Read interface assignment to Read While Write
Partition is described in the following table:
Table 248. Read interface assignment
514/2075
Read-While-Read Interface 0
Read-While Read Interface 1
RWW P0
—
RWW P1
—
—
RWW P2
RWW P3
—
RM0483 Rev 5
RM0483
Embedded flash memory
Code Flash partitions reads return 256 bits (1 page = 4 doublewords). Data Flash partition
reads return 128 bits. Register reads return 32 bits (1 word).
Flash array reads are performed through the Bus Interface Unit. In many cases the BIU
applies “Read Page Buffering” to allow sequential reads to be executed with higher
performance. This can provide data coherency issues that must be handled by software.
Data coherency may be an issue after a program or an Erase operation, as well as Test
block operations.
Flash array reads to invalid locations result in indeterminate data. Invalid locations occur
when addressing points to blocks that are not included in the flash memory map of any
partition. Interlock writes to invalid locations result in an interlock occurring, but attempts to
program these blocks do not eventuate since they are forced into a locked state. Erase
occurs to selected and unlocked blocks even if the Interlock Write is to an invalid location.
Register reads to unmapped register address spaces return all 0’s. Registers writes to
unmapped register address spaces have no effect.
Simultaneous Read cycles on the Flash array and Read/Write cycles on the registers are
possible, but not simultaneous register Read/Write accesses with Flash Array Interlock
Writes are forbidden.
17.4.2.2
Error correction code
The flash memory module implements a strategy for improving the reliability of the data
stored in Flash via the use of Error Correction Code.
In Code Memory the ECC size is 128 bits with 9 ECC bits associated. In Data Memory the
ECC size is 64 bits with 15 ECC bits associated.
ECC function is implemented in such a way to guarantee Double Error Correction and Triple
Error Detection (DEC-TED) in Data Memory.
ECC function is implemented in such a way to guarantee Single Error Correction and
Double Error Detection (SEC-DED) in Code Memory.
ECC coding has all 0’s (intended as data and parity) as an invalid word and all 1’s as a valid
word.
In addition to providing the requested Read data, the Flash also provides output sidebands
reflecting the status of the single and double error corrections and triple error detections
performed at the end of each Read.
For functional safety coverage, Flash performs an EDC post ECC operation at every Read
to detect mismatches in the ECC logic detection and correction. The result is output as
sideband. Also active is a monitor circuit that checks the reference current in the sense
amplifiers, including control of the internally regulated Read voltage, to prevent anomalous
Read operation.
ECC circuitry provides single-bit fault correction used to achieve automotive reliability
targets. Some units experience single-bit corrections throughout the life of the product with
no impact on product reliability.
17.4.2.2.1 Multi-bits error management (more errors than uncorrectable detection
capability)
In this case, behavior cannot be predicted without knowing the original data and the position
of the bit flips. The hardware can react in multiple ways:
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1.
do nothing (that is, not signaling of any flag)
2.
assert either SBC, SBC1, or EER without EEE
3.
assert either SBC, SBC1, or EER with EEE
4.
assert EEE only.
SBC and SBC1 reporting have to be activated in UT0.
It is worth highlighting that by design the purpose of the ECC logic is not to detect multi-bit
errors but cope with errors in the data and parity containing maximum number of bit flip till
uncorrectable detection capability. In this condition, the EDC after ECC monitors the
integrity of the ECC logic.
Other mechanisms must detect multi-bit errors or avoid their occurrence.
For example running the Array Integrity Check once after the boot before the safety
application starts to protect the Data with an application level checksum.
An example of a mechanism that decreases the possibility of multi-bit errors in the array is
the multiplexing. The bits of the same word are not one next to each other, but they are
spaced of a fixed number of bits.
17.4.2.2.2 EEPROM emulation
The chosen ECC allows some bit manipulation so that a doubleword can be re-written
several times without needing an erase of the block. This allows the use of a doubleword to
store flags useful for the EEPROM emulation.
The sequence provided in Table 249: Bits Manipulation: doublewords preserving ECC
integrity is related to Data Memory (therefore would not apply on Code Memory). The ECC
coding allows, starting from an all 1’s doubleword value, to rewrite subsequent predefined
code values changing only 1s into 0s and preserving the ECC integrity.
Caution:
Predefined code values have to be applied following the exact Byte order, as reported in the
table.
Table 249. Bits Manipulation: doublewords preserving ECC integrity
Doubleword
ECC parity bits
Sequence
0xFFFF_FFFF_FFFF_FFFF
0x7FFF
erase
0xFFFF_FFFF_FFFF_FFFE
0x3C88
write1
0xFFFF_FFFF_FEFE_FC80
0x3C88
write2
0xFFFF_FFFC_FEFC_FC80
0x1880
write3
0xFCFC_FFFC_FCFC_F880
0x1880
write4
0xFCF8_F8F0_FCE0_E080
0x1800
write5
0xF8F8_E080_F0E0_E000
0x1000
write6
0xE0E0_E080_E0E0_C000
0x1000
write7
0xE000_8000_00C0_0000
0x1000
write8
B7-B6-B5-B4-B3-B2_B1-B0
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17.4.2.3
Embedded flash memory
Flash address generation check
For functional safety coverage, Flash provides output sidebands reflecting the re-encoded
address used to perform the actual Read operation. In the re-encoding process both word
line and column within the selected block are evaluated. For the completion of the reencoding operation, the addresses related to block selections are also computed. Reencoding circuitry is able to detect both no-selection as well as multi-selection. Flash
provides a self-check of address consistency comparing at each Read the sampling of the
current Read address with the re-encoded one, and in case of mismatch an error sideband
is set.
17.4.3
Modify mode
All the Modify operations of the flash memory module are managed through the Flash User
registers interface. This interface is referred as MAIN.
When a Modify operation is active on some blocks, no Read access is possible on any other
block of the same Flash Partition. The Read-While-Modify is supported only among different
Flash partitions.
During a Flash Modify operation any attempt to read any Flash location in the same Flash
partition outputs invalid data and MCR.RWE is automatically set.
If a reset occurs during a Modify operation, the operation is immediately terminated and the
module is reset to Read mode. The data integrity of the Flash section where the Modify
operation was terminated is not guaranteed: the interrupted Flash Modify operation must be
repeated.
In general each Modify operation is started through a sequence of 3 steps:
1.
The first instruction is used to select the desired operation by setting its corresponding
selection bit in MCR.PGM or MCR.ERS or UT0.MRE.
2.
The second step is the definition of the operands: the address and the data for
Programming, or the blocks for Array Integrity Check or Margin Read.
3.
The third instruction is used to start the Modify operation by setting MCR.EHV or
UT0.AIE.
Once selected, but not yet initiated, one operation can be canceled by resetting the
operation selection bit.
A summary of the available Flash Modify operations is shown in Table 250.
Table 250. Flash Modify operations
Operation
Select bit
Operands
Start bit
Doubleword Program
MCR.PGM
Address and Data by Interlock Writes
MCR.EHV
Block Erase
MCR.ERS
SEL0, SEL1, SEL2 and SEL3
MCR.EHV
Array Integrity Check
None
SEL0, SEL1, SEL2 and SEL3
UT0.AIE
Margin Read
UT0.MRE
UT0.MRV + SEL0, SEL1, SEL2 and SEL3
UT0.AIE
Once MCR.EHV (or UT0.AIE) is set, all the operands can no longer be modified until
MCR.DONE (or UT0.AID) is high.
In general each Modify operation is completed through a sequence of 4 steps:
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1.
Wait for operation completion: wait for MCR.DONE (or UT0.AID) to go high.
2.
Check operation result: check bit MCR.PEG (or compare UM0–UM9 with expected
value).
3.
Switch-Off FPEC by resetting MCR.EHV (or UT0.AIE).
4.
Deselect current operation by clearing MCR.PGM/ERS (or UT0.MRE).
Do not initiate a Modify operation on a flash memory module while another Modify operation
is in progress on a separate module.
In the following sections, all the possible Modify operations are described with
accompanying examples of the sequences needed to activate them.
17.4.3.1
Program
A Flash Program sequence operates on any doubleword within the Flash core. Up to two
words within the doubleword may be altered in a single doubleword program operation. A
single program operation can also alter one page (4 doublewords, 32 bytes), or 4 pages
max (128 bytes in total). It is possible to program only certain doublewords in the page or
the quad-page, leaving the others with their original content. Whenever the array is
programmed, the ECC bits are also programmed.
ECC is handled on a 64-bit boundary in Data Flash and 128b boundary in Code Flash.
Whenever you program, ECC bits are also programmed. Thus, if only one word in any given
ECC segment is programmed, the adjoining word/s (in that segment) must not be
programmed later on, since ECC calculation has already completed for that segment.
Attempts to program the adjoining word probably result in an operation failure. All
programming operations must be from 64 bits to 1024 bits, must be 64-bit aligned for Data
Flash and 128-bit aligned for Code Flash. The programming operation must completely fill
selected ECC segments.
Due to the fact that Flash functions in a System with an end2end ECC scheme, ECC parity
bits are also input during an Interlock Write. After setting MCR.EHV, the FPEC checks the
integrity of the data received in terms of ECC. If any doubleword in the doubleword program,
the page program or the quad-page program contains an inconsistency between data and
parity, the whole operation is rejected and a MCR.PEG=0 is set. The doublewords without
data and with parity inconsistency are thus not programmed.
Programming changes the value stored in an array bit from logic ‘1’ to logic ‘0’ only.
Programming cannot change a stored logic ‘0’ to a logic ‘1’. If a logic ‘0’ is attempted to be
over programmed by a logic ‘1’, the resulting operation fails (MCR.PEG=0), and the 0s that
are interlocked are merged (ORed) with 0s that are already present in the 64-bit ECC
segment. Extreme care has to be taken when doing such an operation due to the high risk
of producing ECC errors.
Addresses in locked blocks cannot be programmed. Register locked blocks cannot be
programmed. Hardware locking is also available which only affects the program operation.
Hardware locking is enabled by sideband signals, and if enabled, programs are prevented
from accessing hardware locked blocks in the same way as program software locking.
The user may program the values in any or all the eight words in a page with a single
program sequence. Page-bound words have addresses which differ only in address bits
[4:2]. Up to four pages can be programmed at once on a quad-page boundary, which differ
only in address bits [6:5]. Only certain doublewords may be programmed within the page or
the quad-page, without altering the content of the ones unselected via interlock.
The Program operation consists of the following sequence of events:
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1.
Change the value of MCR.PGM from ‘0’ to ‘1’.
2.
Ensure the block that contains the address to be programmed is unlocked. Write the
first address to be programmed with the program data. The flash memory module
latches address bits (23:7) at this time, as well as written data. This Write is referred to
as a Program Data Interlock Write. An Interlock Write may be as large as 64 bits, and
as small as 32 bits (depending on the CPU bus).
3.
If more than 1 word is to be programmed, write the additional address in the
doubleword with data to be programmed. This is referred to as a Program Data Write.
The flash memory modules ignore address bits (23:7) for program data writes. The
eventual unwritten data word defaults to 0xFFFFFFFF.
4.
Write a logic ‘1’ to the MCR.EHV to start the internal program sequence or terminate
via step 9.
5.
Wait until the MCR.DONE goes high.
6.
Confirm MCR.PEG=1.
7.
Write a logic ‘0’ to the MCR.EHV.
8.
If more addresses are to be programmed, return to step 2.
9.
Write a logic ‘0’ to the MCR.PGM to terminate the program operation.
Programs may be initiated with the 0–1 transition of MCR.PGM or by clearing MCR.EHV at
the end of a previous program. The first Write after a program is initiated determines the
page address to be programmed. This first Write is referred to as an Interlock Write. The
Interlock Write determines if the UTEST or normal array space is programmed via
MCR.PEAS.
In the case of an erase-suspended program, the values in MCR.PEAS may be modified via
the Program Interlock Write, enabling erase-suspended programs to UTEST Nonvolatile
Memory space and revert back to their original state (related to erase-suspended operation)
once the erase-suspended program is completed.
An Interlock Write must be performed before setting MCR.EHV. An Interlock Write
performed after setting MCR.EHV is forbidden and data and address passed through
interlock is lost.The user may terminate a program sequence by clearing MCR.PGM prior to
setting MCR.EHV.
After the Interlock Write, additional writes affect the data to be programmed at the word
location determined by address bits [4:2], as well as the page location within a 1024-bit
segment (determined by address bits [6:5]). Unwritten locations default to a data value of
0xFFFF_FFFF. If multiple writes are performed on the same location, the data for the last
Write is used in programming.
While MCR.DONE is low and MCR.EHV is high, the user may clear EHV, resulting in a
Program Abort.
A Program Abort forces the module to step 8 of the program sequence.
An aborted program results in MCR.PEG being set low, indicating a failed operation.
MCR.DONE must be checked to know when the aborting command has completed.
The data space being operated on before the Abort contains indeterminate data. This may
be recovered by repeating the same program instruction or executing an Erase of the
affected blocks.
The user may not abort a program sequence while in Program Suspend.
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Figure 173. Doubleword program of data 0x55AA_55AA at address 0x00_AAA8 and
data 0xAA55_AA55 at address 0x00_AAAC
MCR = 0x0000_0010;
/* Set PGM in MCR: Select Operation */
(0x00_AAA8) = 0x55AA_55AA;
/* Latch Address and 32 LSB data */
(0x00_AAAC) = 0xAA55_AA55;
/* Latch 32 MSB data */
MCR = 0x0000_0011;
/* Set EHV in MCR: Operation Start */
do
/* Loop to wait for DONE=1 */
{ tmp = MCR;
/* Read MCR */
} while ( !(tmp & 0x0000_0400) );
status = MCR & 0x0000_0200;
/* Check PEG flag */
MCR = 0x0000_0010;
/* Reset EHV in MCR: Operation End */
MCR = 0x0000_0000;
/* Reset PGM: Deselect Operation */
17.4.3.1.1 Program Suspend/Resume
The program sequence may be suspended to allow Read access to the Flash array. It is not
possible to program or to erase during a Program Suspend. Read-While-Write operations
may also be used to read the array during a program sequence providing the Read is to a
different partition.
During Program Suspend, all reads to the doubleword targeted for program return
indeterminate data.
A Program Suspend can be initiated by changing the value of MCR.PSUS from ‘0’ to ‘1’.
MCR.PSUS can be set to ‘1’ at any time when MCR.PGM and MCR.EHV are high and
MCR.ERS is low. 0–1 transition of MCR.PSUS causes the module to start the sequence
which places it in Program Suspend.
It is possible to suspend a program performed during an Erase Suspend. The user must
wait until MCR.DONE=1 before the module is suspended and further actions are attempted.
MCR.DONE takes no more time than tPSUS to go high after MCR.PSUS is set to ‘1’.
Once suspended, the array may be read. Flash memory reads while MCR.PSUS=1 from the
doubleword being programmed return indeterminate data.
Figure 174. Doubleword Program Suspend
MCR = 0x0000_0019; /* Set PSUS in MCR: Program Suspend */
do
/* Loop to wait for DONE=1 */
{ tmp = MCR;
/* Read MCR */
} while ( !(tmp & 0x0000_0400) );
Note that there is no need to clear MCR.EHV and MCR.PGM in order to perform reads
during program suspend.
The Program sequence is resumed by writing a logic ‘0’ to MCR.PSUS.
MCR.EHV must be set to ‘1’ before MCR.PSUS can be cleared to resume the operation.
The module continues the program sequence from one of a set of predefined points. This
may extend the time required for the program operation.
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Figure 175. Doubleword Program Resume
MCR = 0x0000_0011;/* Reset PSUS in MCR: Program Resume */
Repeated suspends at a high frequency may result in the operation timing out, and the
embedded flash memory responds by completing the operation with a fail code
(MCR.PEG=0). The minimum time between Program Suspends to ensure this does not
occur is tPSRT.
17.4.3.1.2 Over-programming protection (OPP) enable
Over Programming Protection can be enabled on a block-by-block basis. In an OPP
enabled block of code Flash, any quad-word which has already been programmed cannot
be programmed again. The OPP enable does not affect the Erase operation. It is possible to
independently set OPP and (hardware) erase protection in order to avoid any kind of
overwrite. Using these protection mechanisms in conjunction with the Test mode disable
feature gives even greater overwrite protection. Attempts to over-program result in
MCR.PEG being cleared.
OPP can be enabled for 16 KB, 32 KB, 64 KB and 256 KB blocks.
OPP is enabled by sideband signals and, if enabled, the program operation is modified to
check for programmed bits prior to undertaking a high voltage program event.
17.4.3.1.3 Successful program address
To enable the System to create logic to authenticate operations with a program (like in a
diary operation), the flash memory module provides the last successful address
programmed as a sideband signal. This value is held until the next successful program. A
successful program is defined as a program operation of data that is not all 1s, to an
unlocked block and the operation results in MCR.PEG returning a ‘1’. An all 1’s value is the
default (and invalid) address after reset.
In case of page programming, the last successful address returned is the beginning of the
page itself regardless of whether that specific address has not been passed through
interlock. In case of quad-page programming, the last successful address returned is the
beginning of the quad-page itself regardless of whether that specific address has not been
passed through interlock.
17.4.3.2
Erase
Erase changes the value stored in all bits of the selected block(s) to logic ‘1’. An Erase
sequence operates on any combination of blocks in the low, mid, high or 256K address
space. The Test block cannot be erased.
The Erase sequence is fully automated within the Flash. The user only needs to select the
blocks to be erased and initiate the Erase sequence.
Register locked blocks cannot be erased. Hardware locking, which only affects the Erase
operation is also available. Hardware locking is enabled by sideband signals and, if
enabled, erases are prohibited on hardware locked blocks in the same way as erase
software locking. If multiple blocks are selected for erase during an Erase sequence, no
specific operation order can be assumed.
The Erase operation consists of the following sequence of events:
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1.
Change the value in the MCR.ERS bit from ‘0’ to ‘1’.
2.
Select the block(s) to be erased by writing 1’s to the appropriate register(s) in SEL0,
SEL1, SEL2 and SEL3 registers. Note that Lock and Select are independent. If a block
is selected and locked, no erase occurs.
3.
Write to any address in Flash. This is referred to as an Erase Interlock Write.
4.
Write a logic ‘1’ to MCR.EHV to start the internal Erase sequence or skip to step 9 to
terminate.
5.
Wait until MCR.DONE goes high.
6.
Confirm MCR.PEG=1.
7.
Write a logic ‘0’ to MCR.EHV.
8.
If more blocks are to be erased, return to step 2.
9.
Write a logic ‘0’ to the MCR.ERS bit to terminate the Erase operation.
After setting MCR.ERS, one Write (referred to as an Interlock Write) must be performed
before MCR.EHV can be set to ‘1’.
Data words written during Erase sequence Interlock Writes are ignored. As Flash functions
in a System with an end2end ECC scheme, ECC parity bits are also input during an
Interlock Write. After setting MCR.EHV, the FPEC checks the integrity of the data received
in terms of ECC even if the value of the data is not meaningful for the Erase operation. If an
inconsistency between data and parity is found, the whole operation is rejected and
MCR.PEG=0 is set.
The user may terminate the Erase sequence by clearing ERS before setting EHV.
An Erase operation may be aborted by clearing MCR.EHV assuming MCR.DONE is low,
MCR.EHV is high and MCR.ESUS is low. An Erase Abort forces the module to step 8 of the
Erase sequence. An aborted Erase results in MCR.PEG being set low, indicating a failed
operation. MCR.DONE must be checked to know when the aborting command has
completed.
The block(s) being operated on before the Abort contain indeterminate data. This may be
recovered by executing an Erase on the affected blocks. The user may not abort an Erase
sequence while in Erase-Suspend.
Figure 176. Erase of blocks (example)
MCR = 0x0000_0004;
/* Set ERS in MCR: Select Operation */
SEL0 = 0x0006_0000;
Blocks */
/* Set the corresponding bit in SEL0: Select
(0x00_0000) = 0xFFFF_FFFF;
/* Latch a Flash Address */
MCR = 0x0000_0005;
/* Set EHV in MCR: Operation Start */
do
/* Loop to wait for DONE=1 */
{ tmp = MCR;
/* Read MCR */
} while ( !(tmp & 0x0000_0400) );
status = MCR & 0x0000_0200;
/* Check PEG flag */
MCR = 0x0000_0004;
/* Reset EHV in MCR: Operation End */
17.4.3.2.1 Erase Suspend/Resume
The Erase sequence may be suspended to allow Read access to the Flash array. It is
possible to program another block in any flash memory module during Erase-Suspend.
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Programming a location subject to suspended Erase results in the program not being
executed and PEG being set to 0.
It is not possible to erase any block during an Erase-Suspend.
During Erase-Suspend, all reads to blocks targeted for Erase return indeterminate data.
An Erase-Suspend can be initiated by changing the value of MCR.ESUS from ‘0’ to ‘1’.
MCR.ESUS can be set to 1 at any time when MCR.ERS and MCR.EHV are high and
MCR.PGM is low. A 0–1 transition of MCR.ESUS causes the module to start the sequence
which places it in Erase-Suspend. The User must wait until MCR.DONE=1 before the
module is suspended and further actions are attempted.
MCR.DONE takes no longer than tESUS to go high after MCR.ESUS is set to ‘1’.
Once suspended, it is not possible to alter the content of SEL0, SEL1, SEL2 and SEL3
registers. Once suspended, the array may be read. Flash memory reads while
MCR.ESUS=1 from the block(s) being erased return indeterminate data.
Figure 177. Block Erase Suspend
MCR = 0x0000_0007; /* Set ESUS in MCR: Erase Suspend */
do
/* Loop to wait for DONE=1 */
{ tmp = MCR;
/* Read MCR */
} while ( !(tmp & 0x0000_0400) );
Note that there is no need to clear MCR.EHV and MCR.ERS in order to perform reads
during Erase-Suspend.
The Erase sequence is resumed by writing a logic ‘0’ to MCR.ESUS.
MCR.EHV must be set to ‘1’ before MCR.ESUS can be cleared to resume the operation.
The module continues the Erase sequence from one of a set of predefined points and this
may extend the time required for the Erase operation.
Figure 178. Block Erase Resume
MCR= 0x0000_0005;/* Reset ESUS in MCR: Erase Resume */
Repeated suspends at a high frequency may result in the operation timing out and the
embedded flash memory responds by completing the operation with a fail code
(MCR.PEG=0). The minimum time between Erase suspends to ensure this does not occur
is tESRT.
17.4.3.3
Factory Mode
The Factory Mode feature can be used to improve Program and Erase Times and it is
managed through a diary location mechanism. If location UTEST at offset +0x0020 is found
virgin at the moment of the reset, MCR.FERS can be set, after rising MCR.ERS and before
MCR.EHV. After setting MCR.EHV the FPEC recognizes the value of FERS and allows a
fast Program and Erase Operation. Under those conditions a factory Mode can start and no
Read-While-Write is allowed (all the flh_busy sideband signals are set high). If the diary
location has been programmed by the user (having changed from being virgin at reset), the
Factory Mode gets permanently disabled.
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17.4.4
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Alternate program and erase interface
A second Modify interface is provided on the Flash for program and erase operations. The
intent is that a dedicated master can have private access to blocks through this interface.
The alternate interface includes an alternate MCR register and alternate lock registers. Any
block in low, mid, or high address space may be accessible through the alternate interface.
The UTest NVM Block is also accessible for program through the alternate interface. Blocks
in 256K Address Space are not accessible through this interface.
The alternate interface supports programming of data sizes from one doubleword (64 bits)
to four doublewords within a single page (256 bits). Within a page, up to eight words may be
altered in a single program operation. It is recommended that programming operations
through the alternate interface be from 64 bits to 256 bits, and be 64-bit aligned.
Programming has the same constraints as for the Main interface concerning ECC
boundaries: 64b for Data Flash and 128b for Code Flash.
The alternate interface supports erasing a single block at a time with each erase operation.
Like with the main interface, erase suspend, program suspend, and erase-suspended
programs are supported.
Program and Erase times for the alternate interface are the same as the main interface
when programs and erases are done in isolation. If the main interface and alternate
interface are being utilized simultaneously, bandwidth sharing is utilized.
Note:
It is possible for the UTest NVM block to exist in both the main program interface and
alternate program interface. In the event of a conflict the first interface to do the program to
an address gets priority, and all other attempts after this result in an OTP over-program
failure (MCR[PEG] or MCRA[PEGa] being set to 0).
17.4.4.1
Alternate program interface
The programming procedure follows exactly the same flow as the main interface, except
that only page programming is allowed.
The alternate interface program is done at lower priority compared to the main interface.
Based on the size of programming allowed, the main interface has a 4:1 ratio advantage
over the alternate interface. Program operations are allowed to finish on the active interface
prior to allowing the inactive interface to execute its operation. Suspends done on the active
interface enable the inactive interface to begin its operation.
For alternate program while erase, there could be a latency of up to 5 ms in the program
operation.
For more information on interaction between the alternate program interface and the main
interface, see Section 17.4.4.3: Alternate interface performance.
If the alternate interface is the only interface active, then normal program times may be
expected.
17.4.4.2
Alternate erase interface
For erases done through the alternate interface, the single block to be erased is selected
based on the address that is received during the erase interlock write. Thus the Select
registers are not valid for the alternate interface (step 2 of the erase flow in Section 17.4.3.2:
Erase), and the interlock write address is used (step 3 of the erase flow in Section 17.4.3.2:
Erase). All other features of the main interface apply to the alternate erase interface. The
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erase procedure is exactly the same as for the main interface. See Section 17.4.3.2: Erase
for more information on erase.
The alternate interface erase is done at lower priority compared to the main interface. The
time-slice ratio between the two interfaces is 10:1, with 50 ms of time given to the main
erase for every 5 ms of alternate interface. Suspends done on the active interface enable
the inactive interface to begin its operation.
For alternate erase while program, there can be a latency of up to 5 ms in the main program
time. Once the alternate erase is interrupted, it remains interrupted for main programs for a
fixed time of 50 ms, at which time the alternate erase restarts. It must be noted that multiple
interruptions of the alternate erase significantly increase the total erase time.
For alternate erase while erase, the main erase has priority and receives 50 ms of erase for
every 5 ms of alternate erase. This may result in a significant increase in the erase time for
the alternate interface, and a minor increase in erase time for the main interface.
For more information on interaction between the alternate erase interface and the main
interface, see Section 17.4.4.3: Alternate interface performance.
If the alternate interface is the only interface active, then normal erase times may be
expected.
17.4.4.3
Alternate interface performance
Table 251 highlights the interactions between the alternate interface and the main interface
for program, erase, suspend, and idle conditions.
Table 251. Alternate Program and Erase Characteristics
Alt PGM/ERS
interface
request
Main
PGM/ERS
interface
request
Alt interface result on
memory array
Main interface result on
memory array
Idle
Idle
Idle
Idle
Idle/SUSP
PGM/ERS
Idle/SUSP
PGM/ERS
PGM/ERS
Idle/SUSP
PGM/ERS
Idle/SUSP
PGM
PGM
PGM
Priority PGM (4:1 ratio)
PGM
ERS
PGM with 5ms latency
ERS
(possible minimal increase to
total ERS time)
PGM
ERS
(significant increase in total ERS
time expected)
Priority PGM
(possible latency of 5 ms)
Once PGM is granted, 50 ms
time slice
available for more programs
ERS
Priority ERS (10:1 ratio)
ERS
(possible minimal increase to
total ERS time)
(significant increase in total ERS
time expected)
50 ms Main ERS for every 5 ms
alternate ERS
ERS
ERS
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Embedded flash memory
17.4.5
RM0483
User Test mode
Customers can put the flash memory module in User Test mode to perform specific tests for
the integrity of the Flash array.
Three kinds of test can be performed:
•
Array Integrity Self Check
•
Margin Read
•
Vth Distribution
User Test mode is an exclusive operation—it cannot be run in conjunction with any other
Flash mode (Read and Write), and Read-While-Write functionality is inapplicable. Read
accesses attempted by the user during User Test mode generates a Read-While-Write Error
(RWE of MCR set). Vth Distribution mode is conditioned by SoC Life Status (mode allowed
only as Failure analysis)
It is not permitted to perform User Test operations on the Test blocks (including the UTEST
section).
17.4.5.1
Array Integrity Self Check
Array integrity is checked using a predefined address sequence (proprietary), and this
operation is executed on selected (SEL0, SEL1, SEL2 and SEL3) blocks. Blocks marked by
TMDBS are automatically excluded from MISR signature computation. Any random or nonrandom code is valid. Once the operation is completed, the results of the reads can be
checked by reading the MISR value (stored in UM0–UM9), to determine if an incorrect
Read, or ECC detection was noted. Array integrity requires that the Read Wait States and
Address Pipelined control registers in the BIU be set to match the frequency being used.
The internal MISR calculator is a 64 + 8 + 1-bit register.
The 256 data, the respective ECC parity data, and the uncorrectable ECC (ERR) errors of
the four doublewords are therefore captured by the MISR through 4 different Read
accesses at the same location.
The whole check is done through 4 complete scans of the memory address space:
1.
The first pass scans only bits 63-0 + 8 ecc + ERR of each doubleword.
2.
The second pass scans only bits 128-64 + 8 ecc + ERR of each doubleword.
3.
The third pass scans only bits 191-129 + 8 ecc + ERR of each doubleword.
4.
The fourth pass scans only bits 255-192 + 8 ecc + ERR of each doubleword.
The 256-bit data and the respective ECC parity data are sampled after any singlebit/double-bit ECC correction and/or the uncorrectable error flag is set after any ECC
detection. Single-bit corrections are always active and logging may be enabled (by
UT0.SBCE1), resulting in the MCR.SBC1 flags and related address to be captured in ADR
register, but this does not change the final signature in the UM0–UM9.
Only data from existing locations are captured by the MISR. The MISR can be seeded to
any value by writing the UM0–UM9 registers.
The Array Integrity Self Check consists of the following sequence of events:
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1.
Set UTE in UT0 by writing the respective password in UT0.
2.
Select the block(s) to be checked by writing 1’s to the appropriate field(s) in SEL0,
SEL1, SEL2 and SEL3 registers. Blocks selected for Array Integrity Check do not need
RM0483 Rev 5
RM0483
Embedded flash memory
to be unlocked. It is not possible to perform Array Integrity operations on the UTEST
Nonvolatile Memory block.
3.
If desired, UT0.AIS can be set for sequential addressing only.
4.
Seed the MISR UM0–UM9 with desired values.
5.
If breakpoints are desired, set UT0.AIBPE to ‘1’, and ensure that MCR.EER and
MCR.SBC1 are cleared. If breaking on single-bit correction is required, ensure that
UT0.SBCE1 is set.
6.
Write a logic ‘1’ to UT0.AIE to start the Array Integrity Check. Array integrity operations
may be aborted prior to UT0.AID going high. This may be done by clearing UT0.AIE. It
must be noted that in the event of an aborted Array Integrity check, the MISR registers
contain a signature for the portion of the operation that was completed prior to the
Abort, and is not definitive. Prior to performing further Array Integrity operations, the
UM0–UM9 registers may require initialization to the desired seed value by performing
register writes. Array Integrity operations may be suspended while UT0.AID is low.
UT0.AISUS may be set to request an Array Integrity Suspend. Once UT0.AID has been
set high, UT0.AISUS may be cleared to resume the Array Integrity sequence.
7.
Wait until UT0.AID goes high.
8.
Check that UT0.NAIBP is set to ‘1’ if breakpoints were previously enabled so that the
MCR.EER, MCR.SBC1 and ADR registers may be checked to determine the cause
and address of the break. Prior to resuming the operation, it is necessary to clear
MCR.SBC1 or MCR.EER in order to preserve coherency of the flags and ADR updates
with respect to any subsequent breakpoints. Operation may then be resumed by
clearing UT0.NAIBP. Continue waiting until the UT0.AID bit goes high. If breakpoints
were not enabled, or if UT0.NAIBP is low when UT0.AID goes high, then the operation
is complete.
9.
Compare UM0–UM9 content with the expected result.
10. Write a logic ‘0’ to the UT0.AIE bit.
Use sequential addressing for normal integrity checks of the flash memory. If a more
detailed check of the Read path is required (in diagnostic mode), leave UT0.AIS at ‘0’ and
use the proprietary address sequence that checks the Read path more completely, however
this sequence takes more time.
Caution:
Do not modify the content of Block Select (SEL0, SEL1, SEL2 and SEL3) and Lock
(LOCK0, LOCK1, LOCK2 and LOCK3) registers during the execution of the Array Integrity
Check operation or the MISR value may vary unpredictably.
User mode array reads requested during the Array Integrity test are ignored to ensure that
the Array Integrity operation is not corrupted. The memory array does not respond to array
Read requests during this time. User mode array reads may be executed if suspended or at
a breakpoint.
While UT0.AID is low and UT0.AIE is high, the user may clear AIE, resulting in an Array
Integrity Check Abort. UT0.AID must be checked to know when the aborting command has
completed.
Array Integrity Check can be suspended by setting UT0.AISUS while Array Integrity Check
is running (UT0.AID=0). Once suspended (UT0.AID=1) Array Integrity Check cannot be
aborted and clearing UT0.AISUS starts the Resume.
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Figure 179. Array Integrity Check of blocks (example)
UM0/9 = 0x0000_0000; /* Reset UM0/9 content */
UT0 = 0xF9F9_9999;
/* Set UTE in UT0: Enable User Test */
SEL0 = 0x0006_0000;
*/
/* Set the corresponding bit in SEL0: Select Blocks
SEL2 = 0x0000_0006;
*/
/* Set the corresponding bit in SEL2: Select Blocks
UT0 = 0x8000_0002;
/* Set AIE in UT0: Operation Start */
do
/* Loop to wait for AID=1 */
{ tmp = UT0;
/* Read UT0 */
} while ( !(tmp & 0x0000_0001) );
17.4.5.2
Margin Read
User Margin Read may be achieved using the Array Integrity interface and has all the
associated features of the Array Integrity interface (MISR calculation, suspend capability
and Breakpoints).
Margin Read procedure (either Margin 0 or Margin 1) can be run on selected blocks in order
to unbalance the Sense Amplifiers with respect to standard Read conditions, so that all the
Read accesses reduce the margin vs ‘0’ (UT0.MRV=0) or vs ‘1’ (UT0.MRV=1).
User Margin Read is a self timed event and is independent of system clocks or wait states
selected. Margin Read can be run on selected (SEL0, SEL1, SEL2 and SEL3) blocks,
generating checksum calculations on MISR and ECC flagging. Blocks marked by TMDBS
are automatically excluded from MISR signature computation. Once the operations are
completed, the results of the Margin Reads can be checked, comparing checksum values in
UM0–UM9 and reading MCR.EER and MCR.SBC to determine if zero, one or two bits are
being detected by the Margin Read.
The MISR can be seeded to any value by writing the UM0–UM9 registers.
As with Array Integrity Check, the internal MISR calculator is a 64 + 8 + 1-bit register. The
256-bit data, the corresponding ECC parity data and the uncorrectable ECC (ERR) errors of
the four doublewords are therefore captured by the MISR through 4 different Read
accesses at the same location. The whole check is accomplished through 4 complete scans
of the memory address space:
1.
The first pass scans only bits 63-0 + 8 ecc + ERR of each doubleword.
2.
The second pass scans only bits 128-64 + 8 ecc + ERR of each doubleword.
3.
The third pass scans only bits 191-129 + 8 ecc + ERR of each doubleword.
4.
The fourth pass scans only bits 255-192 + 8 ecc + ERR of each doubleword.
The 256-bit data and the respective ECC parity data are sampled after any single-bit ECC
correction, and the double error flags are set after any ECC detection. Single-bit corrections
are always active and logging may be enabled (by UT0.SBCE1), resulting in the MCR.SBC1
flags and related address to be captured in ADR register, but this does not change the final
signature in the UM0–UM9.
In any case, the charge losses detected through the Margin Read cannot be considered
device failures and no Failure Analysis is initiated on them.
The Margin Read Setup operation consists of the following sequence of events:
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Embedded flash memory
1.
Set UTE in UT0 by writing the respective password in UT0.
2.
Select the block(s) to be checked by writing 1’s to the appropriate register(s) in SEL0,
SEL1, SEL2 and SEL3 registers. Blocks selected for Margin Read do not need to be
unlocked. It is not possible to do Margin Read operations on the UTEST Nonvolatile
Memory block.
3.
Seed the MISR UM0–UM9 with desired values.
4.
Ensure that MCR.EER and MCR.SBC1 are cleared.
5.
Set UT0.SBCE1 to ‘1’ to detect single bits during Margin Read.
6.
Change the value of UT0.MRE from ‘0’ to ‘1’.
7.
Select the Margin level: UT0.MRV=0 for 0’s margin, UT0.MRV=1 for 1’s margin.
8.
Write a logic ‘1’ to UT0.AIE to start the Margin Read.
9.
Wait until UT0.AID goes high.
10. Check that UT0.NAIBP is set to ‘1’ if breakpoints were previously enabled so that
MCR.EER, MCR.SBC and ADR.ADDR may be checked to determine the cause and
address of the break. Prior to resuming operation, clear MCR.SBC1 or MCR.EER.
Operation may then be resumed by clearing UT0.NAIBP. Continue to wait until
UT0.AID goes high. If breakpoints were not enabled, or if UT0.NAIBP is low when
UT0.AID goes high, then the operation is complete.
11. Compare UM0–UM9 content with the expected results.
12. Check MCR.EER and MCR.SBC1.
13. Write a logic ‘0’ to UT0.AIE, UT0.MRE and UT0.MRV.
14. If more blocks are to be checked, return to step 2.
The linear address sequence is used regardless of the value of UT0.AIS.
Caution:
Do not modify the content of Block Select (SEL0, SEL1, SEL2 and SEL3) and Lock
(LOCK0, LOCK1, LOCK2 and LOCK3) registers during execution of the Margin Read
operation, otherwise the MISR value may vary unpredictably.
User mode array reads requested during the Margin Read are ignored to ensure that the
Margin Read operation is not corrupted. The memory array does not respond to array Read
requests during this time. User mode array reads may be executed if suspended or at a
breakpoint.
While UT0.AID is low and UT0.AIE is high, the user may abort Margin Read by clearing AIE.
UT0.AID must be checked to know when the aborting command has completed. Margin
Read can be suspended by setting UT0.AISUS while Margin Read is running (UT0.AID=0).
Once suspended (UT0.AID=1), Margin Read cannot be aborted and clearing UT0.AISUS
starts the Resume.
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Figure 180. Margin Read Check versus 1’s
UM0/9 = 0x0000_0000; /* Reset UM0/9 content */
UT0 = 0xF9F9_9999;
/* Set UTE in UT0: Enable User Test */
SEL0 = 0x0006_0000;
/* Set LSL2-1 in SEL0: Select Blocks */
UT0 = 0x8000_0020;
/* Set MRE in UT0: Select Operation */
UT0 = 0x8000_0030;
/* Set MRV: Select Margin versus 1’s */
UT0 = 0x8000_0032;
/* Set AIE in UT0: Operation Start */
do
/* Loop to wait for AID=1 */
{ tmp = UT0;
/* Read UT0 */
} while ( !(tmp & 0x0000_0001) );
data0/9 = UM0/9;
/* Read UM0/9 content*/
UT0 = 0x8000_0030;
/* Reset AIE in UT0: Operation End */
UT0 = 0x0000_0000;
/* Reset UTE, MRE, MRV, AIS in UT0:
Deselect Operation */
17.4.5.3
Vth Distribution
Vth Distribution functionality can be used in case of Failure Analysis for quick assessment of
cells status in terms of Vth. The functionality has bit register UTO.VTD as initiator. Writing of
this bit is enabled by the Life Cycle state of the device. Life Cycles has to be in Failure
Analysis (FA) condition to allow Vth Distribution mode.
Vth Distribution functionality works on selected blocks on the base of multi internal runs.
Each run corresponds to an internal voltage step, where cells read as '1' (Vth lower than
internal voltage level) are counted: the completion of each run provides on UMISR0 the
count of these cells. Clearing UTO.NAIBP starts next voltage step run, till completion of the
intended voltage range. Number of internal voltage step is fixed. Aim of the test is to sweep
the range from the erased cells with the highest Vth to the programmed cells with the lowest
Vth, therefore to provide an assessment of the effective distribution of the cells in the
selected blocks.
Once all the cell counts, one per run, have been collected, distribution can be obtained as
difference between counts collected through subsequent steps.
In every run, all the cells, including the ECC parity ones, are counted for the block selected.
Vth Distribution results are expected to be collected at room temperature (25C).
Vth Distribution Setup operation consists of the following sequence of events:
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1.
Set UTE in UT0 by writing the respective password in UT0.
2.
Select the block(s) to be checked by writing 1’s to the appropriate register(s) in SEL0,
SEL1, SEL2 and SEL3 registers.
3.
Unlock blocks to be checked by writing 0’s to the appropriate register(s) in LOCK0,
LOCK1, LOCK2 and LOCK3 registers. Blocks selected for Vth Distribution need to be
RM0483 Rev 5
RM0483
Embedded flash memory
unlocked. It is not possible to do Vth Distribution operations on the UTEST Nonvolatile
Memory block, neither on blocks protected through TMD SEAL Block Select.
4.
Set UT0.VTD to ‘1’ to select Vth Distribution mode.
5.
Write a logic ‘1’ to UT0.AIE to start the first internal run.
6.
Wait until UT0.AID goes high.
7.
Check that UT0.NAIBP is set to ‘1’. If NAIBP is at ‘1’ it means current internal run has
been completed and device is ready to increase voltage step. If NAIBP is at ‘0’ the
overall sweep has been completed.
8.
Collect UM0 content for the current voltage step (run).
9.
Clear UT0.NAIBP to increase voltage step and return to 6)
Caution:
Voltage levels used during Vth distribution sweep may alter the intended reliability of the
Cells as data retention. For this reason Vth distribution can be used no more than 10 times.
17.4.6
Protection strategy
Two kinds of protection are available: Modify Protection to avoid unwanted program/erase in
Flash blocks and Test Mode Disable to avoid piracy.
17.4.6.1
Modify protection
The Flash Modify Protection information is stored in nonvolatile Flash cells located in the
UTEST region. This information is read once during the Flash Initialization phase following
exit from reset and is stored in volatile registers that act as actuators at SoC level. The
information is passed to the flash memory module through erase_lock and program_lock
sidebands, and allows independent protection of each block of Low, Mid, High and 256K
Address Space Block.
There are also Address Space Block Locking registers provided to independently
lock/unlock each block of Low, Mid, High and 256K Address Space Block against program
and erase. Locking is done through the LOCK0, LOCK1, LOCK2 and LOCK3 registers.
These registers do not have a nonvolatile image stored in the UTEST area of TestFlash, so
the locking information is kept on reset: volatile content is all 1’s, meaning all blocks are
locked.
All the volatile registers can be written to ‘0’ or ‘1’ at any time, therefore the user application
can lock and unlock blocks when desired. Note, however, that overall protection is achieved
by the combination of sidebands with Low, Mid, High and 256K Address Space Block
Locking registers in such a way that a block can be programmed/erased only if both
(sidebands and Locking registers) indicate an unlocked state. Sidebands independently
control program protection, erase protection and over-programming protection (OPP) on a
block-by-block basis.
As UTEST and BAF (each one with its own lock bit, LOCK0.TSLOCK and
LOCK0.LOWLOCK respectively) are two sections of the same physical block (TestFlash),
effective locking is achieved via the ‘AND’ operand of the lock bits. For effective locking,
overall protection is obtained in conjunction with sidebands: UTEST and BAF may have
dedicated program protection sidebands (System specific).
17.4.6.2
Test Mode Disable
In the TestFlash area a mechanism is also available to disable entry into Test mode.
Extreme care must be taken when using this feature, as blocks that are selected for
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RM0483
protection in this way cannot be analyzed for possible failures by manufacture failure
analysts.
Protection of this sort prevents all high voltage operations to the Flash executed by the
internal FPEC as well as reads from FPEC, including Array Integrity Check or Margin Read,
when using Test mode interfaces. Protection through other interfaces is managed through
normal User mode protection mechanisms, that are System specific.
To disable manufacturer entry into Test mode, first program the Test Mode Disable Seal
location to 0x2D3C_4B5A and once the next reset is asserted, Test mode is disabled.
It is possible to create a password to enable manufacturer entry into Test mode. This can be
programmed into the Test Mode Disable Override Passcode. It is safest to do this prior to
censoring the part to avoid unintended lockout. The passcode may not be 0x0000_0000,
0xFFFF_FFFF, or 0x5555_5555. These are all invalid passcodes and are not accepted for
override. If the customer desires that override never be possible, one of the three invalid
passcodes must be put into this location. Passcodes may be entered to authenticate entry
(if enabled) by performing a register Write to offset address 0x90.
Only blocks selected in the Test Mode Disable Block Select field are controlled by the Test
Mode Disable feature. Thus it is possible for customers to select blocks for this type of
protection, and render them ineligible for manufacturer failure analysis. Bits programmed to
‘0’ in the Test Mode Disable Block Select field designate blocks that are controlled by Test
Mode Disable feature. The TestFlash block, and thus the UTEST and BAF sections, is
always protected once the Test Mode Disable Seal password is written. In order to permit
two opportunities to select blocks for Test Mode disable, two regions are available, both in
UTEST: one at offset 0x50, and the other at offset 0x60; both are 128-bit sized (only some
may be effective, depending on actual sectorization). The bits of these two regions are
logically ANDed in order to define which blocks are effectively selected for the Test Mode
Disable feature.
The bit Block Select field is organized as follows, and aligned in the way blocks are defined
in the LOCKx/SELx registers:
Table 252. Test Mode Disable block select
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Block
Block selection bits
Blocks in Mid space
Data[15:0]
Blocks in Low space
Data[29:16]
Blocks in High space
Data[47:32]
Blocks in 256K space
Data[127:64]
RM0483 Rev 5
RM0483
Boot assist flash (BAF)
18
Boot assist flash (BAF)
18.1
Introduction
The BAF code is programmed by ST. The two main tasks of BAF are to provide a serial
bootloader feature and to search for the application entry point.
For details regarding how the BAF code execution is triggered, refer to Clock reset and boot
chapter.
The BAF is executed via the IRCOSC as clock source.
The MCU is booted through a collaboration of several blocks, hardware and firmware. The
first boot phases are performed by a state machine inside the System Status and
Configuration Module (SSCM). Once completed, the SSCM sends a reset vector to the HW
boot core of the device pointing into the Boot Assist Flash (BAF).
The BAF reads on special RCC registers to know: if a boot address has been updated, if the
core2 is in lockstep and if the core2 boot address has been updated, it enables the core2 if
needed, and it boots the application code in internal Flash.
If no Core1 User Application Address DCF record is found in internal flash memory and
lifecycle is < “IN_FIELD”, BAF downloads application code serially using the UART module
or the M_CAN module.
18.2
Memory map
For the BAF location in flash, refer to the Embedded memories chapter. The BAF block
base address is 0x1FF0_0000. It is one time programmable (OTP) and is programmed
during factory test. The address space and memory used by the BAF code are shown in
Table 253.
Note:
The BAF Flash block is assigned as OTP and it is protected from programming by a bit in
the PASS LOCK0 registers; but the BAF Flash block can further be protected from
programming by an external hardware pin. If the Hardware Interlock feature is enabled,
while this pin is logic ‘0’ the BAF Flash block cannot be programmed.
Table 253. BAF memory organization
BAF component
Address
BAF image header
0x1FF0_0000
BAF code entry point
0x1FF0_0100
BAF data area and stack
18.2.1
0x5C00_0000–0x5C00_0603
BAF image header
BAF image contains a 256-byte header starting from address 0x1FF0_0000. The BAF
header is explained in Table 254.
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Table 254. BAF image header
Address offset
Size (bits)
0x0000
32
0x0004–0x000F
BAF version number
Reserved
0x0010
32
0x0014–0x00FF
18.2.1.1
Field description
Clock Jitter Activation Constant
Reserved
BAF image version
The BAF version is a 32-bit field in the image header starting at address 0x1FF0_0000. The
32-bit field is explained in Table 255.
Table 255. BAF image version
18.2.1.2
Field
Description
31:24
Major Number: This field contains the major version number for the BAF image
23:16
Minor Number: This field contains the minor version number for the BAF image
15:0
Reserved
Clock Jitter Activation constant
The Clock Jitter Activation constant is a 32-bit flag, but the smallest element in flash that can
be programmed is 64 bits, so the first 32 bits are reserved to allow programming of this
constant. This 32-bit flag can be programmed by the customer and is used to activate the
Clock Jitter feature that adds clock edge jitter to the baud rate clocks of several
communications modules.As part of the BAF startup procedure, BAF copies this constant
from flash to the PASS Clock Jitter Enable Register.
Table 256. BAF Clock Jitter Activation Constant
Field
0:31
18.3
Description
Clock Jitter Activation Constant. The initial state of production disable flag is
erased - 0xFFFF_FFFF.
This equates to NO clock jitter.
Functional description
A functional description of the BAF modes is contained in the following sections.
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18.3.1
Boot assist flash (BAF)
Boot modes
Depending on the state and the content of its flash memory, the device can enter one of
these different boot modes.
•
Application code execution
If the internal flash contains application code with a valid Core1 User Application
Address DCF record, the application is executed.
•
Serial boot
If no valid Core1 User Application Address DCF record is found and the current
life cycle phase of the device is less than Infield, an attempt is made to download
the application by a serial protocol using the UART module or M_CAN module.
The downloaded code is then executed by the boot CPU.
•
Static mode
The device enters power safe mode and waits for an external reset.
18.3.2
Device initialization
The BAF performs a minimal initialization of core registers and clocks required to enter the
above described boot modes, then attempts to interact with the Hardware Security Module
(HSM) in the following way:
•
•
•
•
18.3.3
HSM: if the HSM is enabled and the “wait for HSM” flag is present, then the boot core
waits for the HSM to become ready.
BAF sets up the exception vector table to catch machine check exceptions, which may
occur if there are any uncorrectable ECC errors. In the event of an uncorrectable ECC
error, the BAF issues a destructive reset from the machine check exception handler if
the exception is due to the reading of instructions from the BAF region. If an ECC error
occurs during reading of D-MEM, the BAF still issues a destructive reset. BAF
programs the Reset and Clock Control module to issue a destructive reset.
BAF uses DMEM memory area of the boot CPU as in Table 253: BAF memory
organization for its stack, data and any code that executes from volatile memory.
During the BAF start-up procedure, it initializes this section of memory so that there is
no ECC error when BAF accesses this memory area.
The memory area of the BAF is protected from execution for functional safety
considerations. This is achieved by disabling BAF execution in PFLASH control
register3 (PFLASHC_PFCR3[BAF_DIS]). At this point the BAF has finished its
operation.
Flow of control
The figure below shows the overall flow of control in the BAF. The individual steps are
explained in the following sections.
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Figure 181. Flow of control
reset vector
n
ifecycle = Failure analysis?
lifecycle = Failure analysis?
y
BAF = Execution in Failure
Analysis?
n
Service Watchdog
y
HSM enabled & wait?
n
y
wait for HSM
clock jitter
activation?
TDM
Program DCF Clients/ secure
watchdog
Core1User Application
Address DCF valid?
n
lifecycle is < “IN_FIELD”?
y
disable BAF execution access
y
n
Destructive Reset
18.3.4
Serial boot
Jump to the application entry code
Optionally wait for HSM
If the HSM is enabled (SSCM_UOPS[HSE] = 1), the boot core waits for the HSM to become
ready (SSCM_UOPS[HSB = 1]). The core then polls the HSM until a ready flag is set. Both
SSCM registers can be set by a DCF record. The boot core polls the HSM to HOST
STATUS register (HSM_HSM2HTS) until its least significant bit is set. The boot core also
services the watchdog while polling the HSM_HSM2HTS register. This is just in case the
HSM is not ready in 16 ms, servicing the watchdog prevents the system from going to reset.
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Boot assist flash (BAF)
18.3.5
Initialization of BAF DCF clients
18.3.5.1
‘Soft’ DCF clients
DCF clients are 32-bit hardware registers that are written by the SSCM during reset with
data that is stored in DCF record format in UTEST region of flash memory. These DCF
records are used to configure module registers, and select device operating modes.
The BAF extends the DCF record concept by implementing soft DCF clients. The 64-bit
DCF records include:
•
32 bits of data
•
15-bit chip select field (selects the module which implements the DCF clients)
•
15-bit address field (selects a specific DCF client within the selected module)
•
Parity bit (not used with UTEST DCF records)
•
Stop bit (to indicate the end of DCF record has been reached)
As part of its execution flow, BAF searches through the list of DCF records in UTEST flash
to determine if any of the records are to be processed by BAF.
The search starts at one of two addresses: either the start address of DCF records in
UTEST (DCF Start Record), or the address specified in UTEST (Soft DCF Record Start
Address). If either of the two least significant bits of the 32-bit address stored at the Soft
DCF Record Start Address is set, the default start address at the DCF Start Record is used.
If the two least significant bits are clear, this 32-bit value is assumed to be the start address
of the search.
The default setting of the two least significant bits is 11b (erased value of flash memory is
0xFFFF_FFFF). A user may intentionally program a dummy address with the least two
significant bits set in order to disable the search for an alternate address (as the UTEST
block is OTP). Valid search start address must start on a 4-byte boundary.
The DCF record search finishes when a DCF record is read with a STOP bit set. The STOP
bit may be set because that memory location is not programmed yet (so the list can be
added to) or it can be intentionally programmed STOP record to indicate that no more
records are added to the list. BAF does not execute the DCF record with STOP bit set. BAF
parses the STOP bit before parsing the rest of the records.
BAF uses Chip Select 14 (CS14) for BAF DCF clients. For records with CS14 asserted, the
BAF uses the address field (address[14:0]) in DCF records to determine how to process the
32-bit of data. The soft DCF clients programmed by BAF is listed in Table 257.
A group of four Soft DCF clients is used to provide a mechanism to write configuration
information to address locations. The first DCF client receive 32-bit address information.
The next three DCF Clients receive the data that is to be written to the address contained in
the first client. The three data clients allow 32-, 16- and 8-bit data to be written to the
address in the first client. These four clients can be accessed repeatedly to write the whole
string of data to memory.
Another soft DCF client as stated in Table 257 provides a simple callback feature. The soft
DCF record data contains the start address of a subroutine that the BAF calls before it starts
checking for a valid User Application Address and exits to customer application code. The
callback routine can reside within the BAF or UTEST blocks only. The callback DCF client
can be accessed repeatedly in order to execute a callback sequence.
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The serial boot DCF client provides a mechanism whose application can inform BAF to
perform serial boot or boot from internal flash. Details can be viewed in Section 18.3.5.5:
SER_BOOT_CBACK – BAF serial boot DCF client.
Table 257. BAF DCF client list
Address (hex)
Name
Label
0x0000–0x01FF
Description
Reserved
0x0200
Address
ADDR
The address to which DATAX is written
0x0201
32-bit Data
DATA32
The 32-bit data that is written to ADDR
0x0202
16-bit Data
DATA16
The 16-bit data that is written to ADDR
0x0203
8-bit Data
DATA8
The 8-bit data that is written to ADDR
0x0204–0x020F
Reserved
0x0210
Callback Address
CALLBACK
0x0211
Serial boot Callback
Address
The address of a callback function
SER_BOOT_CBACK The address of serial boot callback function
0x0212–0x0213
Reserved
Reserved for future use.
0x0214
Reserved
Reserved for future use.
0x0215–0x7FFF
Reserved
Reserved for future use.
Note:
BAF boots with a watchdog timeout window set to 16ms. Parsing more and more DCF
Records may increase boot time. But it must be taken care that number of DCF records
must not be very high as it can cause watchdog window timeout.
18.3.5.2
BAF DCF client - Address
BAF parses the DCF records. If BAF finds a DCF record with CS14 set and Address field as
0x0200 while parsing, BAF programs this DCF client. This client is written with a 32-bit
address from the Data section of DCF record. This 32-bit address is used in conjunction
with any one of the DATA32, DATA16 or DATA8 DCF Data clients. BAF does not
immediately use the ADDRESS information, but it is stored and used later in conjunction
with a DATAX DCF client (DATA32, DATA16 or DATA8). Then BAF writes the data to the
address in memory specified by this ADDRESS DCF client.
The user can create a series of data writes to memory by programming a series of DCF
records consisting of pairs of records. The first DCF record of the pair writes to ADDR to
provide the address. The second DCF record of the pair writes to the DATA client (DATAX)
to provide the data. Subsequent pairs of DCF records can be programmed to write to more
memory locations. The number of pairs of DCF records that can be programmed is only
limited by the amount UTEST space set aside for DCF records.
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DCF Client Address 0x0200
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5
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0
ADDR
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14
13
12
11
10
9
8
7
ADDR
Figure 182. BAF DCF ADDR client configuration
Table 258. BAF DCF ADDR client description
Field
Description
31:0
ADDR
32-Bit Address DCF client
This ADDRESS value is used in conjunction with a DATAX value. The BAF writes
DATAX value to ADDRESS value in the memory space of the MCU.
18.3.5.3
BAF DCF client - DATAX
Caution:
While using DATAX DCF records, it must be taken in account that BAF does not take care of
ECC scheme and can generate ECC, if write is performed in memory locations which are
protected by ECC and are not pre-initialized as required.
18.3.5.3.1 DATA32 – 32-bit data DCF client
BAF parses the DCF records. If BAF finds a record with CS14 set and address field set as
0x0201 while parsing, BAF programs this 32-bit DCF client. BAF takes the memory address
provided by the ADDR client, masks the least significant 2 bits to ‘0’ (Only 32-bit aligned
writes are supported) and writes this 32-bit data to the address.
DCF Client Address 0x0201
31
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26
25
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23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
DATA
15
14
13
12
11
10
9
8
7
DATA
Figure 183. DATA32 DCF client configuration
Table 259. DATA32 DCF client configuration
Field
31:0
DATA
Description
32-Bit DCF data
18.3.5.3.2 DATA16 – 16-bit data DCF client
BAF parses the DCF records. If BAF finds a record with CS14 set and address field set as
0x0202 while parsing, BAF programs this 16-bit DCF client. BAF takes the memory address
provided by the ADDR client, masks the least significant bits to ‘0’ (Only 16-bit aligned
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writes are supported) and writes the least significant 16-bit data to the address. Data in the
16 most significant bits are ignored.
DCF Client Address 0x0202
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25
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19
18
17
16
6
5
4
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2
1
0
Reserved
15
14
13
12
11
10
9
8
7
DATA
Figure 184. DATA16 DCF Client Configuration
Table 260. DATA16 DCF client configuration
Field
Description
15:0
DATA
16-Bit DCF data
18.3.5.3.3 DATA8 – 8-bit DCF client
BAF parses the DCF records. If BAF finds a record with CS14 set and address field set as
0x0203 while parsing, BAF programs this 8-bit DCF client. BAF takes the memory address
provided by the ADDR client, and writes the least significant 8-bit data to the address. Data
in the 24 most significant bits are ignored.
DCF Client Address 0x0203
31
30
29
28
27
26
25
24
23
22
21
20
6
5
4
19
18
17
16
3
2
1
0
RESERVED
15
14
13
12
11
10
9
8
7
RESERVED
DATA
Figure 185. DATA8 DCF Client Configuration
Table 261. DATA8 DCF client configuration
Field
7:0
DATA
18.3.5.4
Description
8-bit DCF data
CALLBACK – BAF callback DCF client
BAF parses the DCF records. If BAF finds a record with CS14 set and address field as
0x0210 while parsing, BAF programs this callback DCF client. This client is written with a
32-bit start address of a function which is invoked by BAF. The BAF code checks the start
address is within the UTEST or within the BAF flash memory blocks, and then passes
program flow to this address. If the address is found to be outside the UTEST and BAF flash
memory blocks, no function call is executed. The callback is aborted and BAF moves on to
the next DCF records. The function that is called is expected to comply with Embedded
Application Binary Interface (EABI) for Arm® found in Arm® Architecture web site and to
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terminate in an orderly manner. An incorrectly written function causes unpredictable
operations in BAF. No parameters are passed to this function and no return value is
expected.
Caution:
Excessively long callback functions could cause the watchdog timer to time-out and cause a
reset.
BAF executes the callback function as the DCF records are parsed. Therefore, several
callback functions can be executed by writing several DCF records that write to the callback
DCF clients. The callback functions are executed in the same order as the DCF records.
18.3.5.5
SER_BOOT_CBACK – BAF serial boot DCF client
BAF parses the DCF records. If BAF finds a record with CS14 set and address field as
0x0211 while parsing, BAF programs this serial boot DCF client. This DCF client is written
with a 32 bit start address of function which is invoked by BAF. The BAF code checks the
start address is within UTEST or within the BAF flash memory block, and then passes
program flow to this address. If the address is found to be outside the UTEST and BAF flash
memory block, no function call is executed. The DCF client execution is aborted and BAF
moves on to the next DCF record. The function that is called is expected to comply with
Embedded Application Binary Interface (EABI) for Arm® found in over Architecture web site
and to terminate in orderly manner. An incorrectly written function causes unpredictable
operations in BAF. No parameters are passed to this function.
Warning:
No parameters are passed to the function invoked by the
BAF. Excessively long callback functions could cause the
watchdog timer to time-out and cause a reset.
The serial boot callback function returns a char value. The returned value informs BAF if
serial boot or normal internal flash boot must be executed (refer to Table 262 for details
regarding return value).
Table 262. Serial boot callback function return value definition
Return values
18.3.6
Description
0x00
Boot from internal flash using standard search for boot record.
0x01
Serial boot using both M_CAN and UART (in UART mode).
Note: Serial boot is conditioned by life cycle as described in Figure 181.
Production disable activation protocol and implementation
Module failure analysis is a standard requirement. But some OEMs have an additional
requirement that upon entering failure analysis mode, the MCU operation is modified in
such a way that the MCU can never be used in production ECU. The chosen operational
modification for production disable is to apply clock jitters to can modules so that it prevents
active communications with another can device on a can network. For detail regarding
Production Disable refer to the Security manual.
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The BAF maintains a 64-bit flag in BAF code flash region as explained in Section 18.2.1.2:
Clock Jitter Activation constant. On every POR BAF copies the clock jitter activation
constant from this flag to clock jitter enable register in PASS module to enable jitters on can
baud clock. Default value of this flag is shown in Section 18.2.1.2: Clock Jitter Activation
constant. Hence, jitter on the MCAN baud clock is disabled if the default value is used. To
enable jitter on MCAN baud clock, the value of this flag must be modified to 0xFFFF_FFFE.
The BAF flash memory is write protected and locked.
18.3.7
TDM diary operation
On every reset, BAF copies the first four bytes of last record of every Tamper Detect Region
to the corresponding Software Tamper Override Key Region Registers in TDM. BAF reads
the base address of TDM Diary from DBA register in TDM. For more details on TDM refer to
the device Security Manual. This is done as a part of TDM Diary Override enhancement.
18.3.8
Optionally perform a serial boot
If no Core1 User Application Address DCF record is found in one of the locations mentioned
above, then BAF determines the Life Cycle status of the device. If the Life Cycle is lower
than In Field, it attempts a serial boot. Otherwise, the boot has failed and the BAF issues a
destructive reset.
If the customer selects serial boot using serial boot using serial boot DCF client, then BAF
determines the Life Cycle status of the device. If the Life Cycle is lower than Failure
Analysis, it attempts a serial boot.
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Figure 186. Flow of control during serial boot
Serial boot
Set clock sources
Initialize MCAN and UART
(UART Mode)
Poll UART and MCAN for
password
Password Valid?
n
y
receive START address
receive DOWNLOAD size
receive Code
Error?
y
n
Jump to downloaded code
Static mode
The clock source in the RCC is configured (with IRCOSC for UART and with XOSC for
CAN) and the PADs are set up for UART and M_CAN signals, then the code is downloaded
using UART or M_CAN in Serial Boot mode. In the absence of errors causing the device to
be placed in Static mode, the device state is restored to resemble the out-of-reset state and
the downloaded code is executed.
Serial boot allows the download of application to internal SRAM via UART or M_CAN
interface. After downloading the application image to SRAM, the BAF jumps to the start
address provided as part of download protocol mentioned below and executes the
downloaded application.
At the start of the process both UART and M_CAN are configured in passive listening mode.
As soon as either interface receives a valid message, the receiving interface is configured in
full Tx and Rx mode. The non receiving interface is switched back to reset state and does
not participate further in serial boot.
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If a CAN message of 8 bytes with ID 0x11 is received on the M_CAN controller first, the BAF
program:
•
Disables UART.
•
Configures UART RXD input mux back to reset state.
•
Transitions to CAN serial download protocol routine.
If a CAN message not containing 8 bytes or NOT with ID 0x11 is received by M_CAN
controller or a M_CAN controller generates a CAN error, it is probable that the tool is
sending a UART frame. Under such circumstances BAF program:
•
Ignores the CAN message, if a message arrived.
•
Clears any pending CAN error.
•
Continues monitoring for valid CAN messages.
If any byte from UART is received first, the BAF program:
18.3.8.1
•
Checks if the first byte is 0xFE of the password. If not it continues polling. The data may
be a valid CAN message.
•
If it is first byte of the password (0xFE), then it disables the M_CAN controller and
restores to its reset state.
•
Configures the M_CAN pads to their reset state.
•
Transitions to UART serial boot (UART mode).
Serial boot mode protocol
From a high-level perspective, the download protocol over M_CAN and LIN interfaces
follows the steps below:
1.
Host transmits the 64-bit password to MCU.
2.
Host transmits start address, size of downloaded code in bytes, NO_ECHO bit to MCU.
NO_ECHO bit signifies if actual download data to be echoed or not. If NO_ECHO bit is
set, then data is not echoed otherwise if NO_ECHO bit is clear, then data is echoed.
3.
Host transmits a sequence of data bytes that are to be executed.
4.
The boot CPU executes code from start address provided in step 2.
Each step must be completed before the next step starts.
The exact protocol between UART and M_CAN is slightly different.
18.3.8.2
UART download protocol
The communication is performed in half-duplex mode, any transmission from the host is
followed by the MCU transmission.
1.
The host sends data to the MCU and starts waiting.
2.
The MCU echoes the received 8-byte of password, 4-byte of load address and 4-byte
of NO_ECHO bit and 31-bit of download size to the host. The MCU echoes actual
download data depending upon NO_ECHO bit.
3.
The host verifies whether the echo is correct.
–
If the data is correct, the host can send the next byte of data.
–
If data is not correct, it is assumed the MCU has not correctly received the data
and the only practical option is for the Host to reset the MCU and start again.
A more detailed description of these steps follows.
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All multi-byte data structures are sent with MSB first.
The tool sends data in the following order:
18.3.8.3
1.
8 bytes that represent the password.
2.
4 bytes that represent the start address where the code is to be downloaded.
3.
4 bytes that represent the number of bytes to be downloaded, NO_ECHO bit.
4.
x bytes of code that is downloaded to SRAM and executed (x must match the value
specified in step 3.).
M_CAN download protocol
The M_CAN download protocol uses very similar structure to the UART protocol, but it
makes use of the message ID’s provided by M_CAN.
The tool sends data packed into standard CAN message in the following manner:
18.3.8.4
1.
A message with 0x11 as the ID and an 8-byte length to send the password. The MCU
transmits the same message, but with an ID of 0x1.
2.
A message with 0x12 as the ID and 8-byte length to send the start address, size of the
code.The MCU transmits back the same data but with an ID of 0x2.
3.
A message with 0x13 as the ID is used to send data that is to be downloaded to SRAM.
The MCU transmits the same data with an ID of 0x3.
Download 64-bit password and password check
The first 64 bits received represent the password. The MCU only supports public
passwords. The received password is always compared with the public password
0xFEED_FACE_CAFE_BEEF.
18.3.8.5
•
If the correct password is received, BAF continues its task.
•
If an incorrect password is supplied, BAF puts the device into static mode (low power
safe mode).
•
If 64 bits of password data is not received after approximately 30s, BAF causes a
destructive reset of the MCU.
Download start address, NO_ECHO bit and code size
After the password, the next 8 bytes received by the MCU contains a 32-bit start address,
NO_ECHO bit and 31-bit code length as shown in Figure 187 and Figure 188.
The NO_ECHO bit is used to indicate if download data must be echoed by the MCU. If the
NO_ECHO bit is set (for example, NO_ECHO = 1), then only 8 bytes of password, 4 bytes
of download address, and 4 bytes of download size are echoed, but download data is not
echoed. If the NO_ECHO bit is clear, then every byte sent to the MCU must be echoed.
The start address defines where the received data is stored and where the MCU branches
after the download is finished. The three LSB bits of the start address are ignored by BAF,
such that the load address is 64-bit double-word aligned.
The length determines how many data bytes have to be loaded.
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0
START_ADDRESS
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14
13
12
11
10
9
8
7
START_ADDRESS
Figure 187. Start address
Bytes 4:7
30
29
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27
26
25
24
NO_ECHO
31
15
23
22
CODE_LENGTH
14
13
12
11
10
9
8
7
6
CODE_LENGTH
Figure 188. NO_ECHO bit and code size
18.3.8.6
Download data
Each byte of data received is downloaded into device SRAM starting from the address
specified in the previous protocol step. It is not verified whether the provided address is a
valid address in SRAM or is writable.
The address increments until a number of bytes of data received matches the code length
specified in the previous protocol step.
Since the SRAM is protected by 64-bit wide Error Correction Code (ECC), BAF always
writes to SRAM grouped in 64-bit double-words. If the last byte does not fall into a 64-Bit
bounder, the BAF fills it with zero’s and renders the data aligned on a 64-bit bounder. After
the last data is written to SRAM, the BAF writes a dummy double-word
(0x0000_0000_0000_0000) to the next address location. This is written to avoid possible
ECC error during core prefetch.
18.3.8.7
Execute code
The BAF program waits for the last echo message transmission to be completed. Then it
restores the initial MCU configuration and jumps to the loaded code at Start Address which
was received in step 2 of the protocol. At this point the BAF has finished its tasks and the
MCU is controlled by new code executing from SRAM.
18.3.9
Serial boot configuration
18.3.9.1
UART configuration
Boot using UART protocol is implemented by UART module.
Note:
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Refer to the pin configuration table in Chapter 5: Device configuration for pins used by the
UART module.
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When Serial Boot mode is started the UART_Rx is configured as an input and multiplexed to
the UART module. The UART_Tx remains in a passive input state until the first byte of
protocol is received. It is then configured as an output and multiplexed to UART module.
The application may not be using the Serial Boot Mode function, and may be using the pin
used by UART_Tx as an input, which may have some external hardware driving the pin.
Inadvertently driving this pin as an output would cause contention and possible damage.
The UART module operates in half-duplex mode. The interfac">