ST Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 Reference Manual

PDF

مستند

RM0471

Reference manual

Multiprotocol wireless 32-bit MCU Arm

-based Cortex

-M4

with FPU, Bluetooth

Low Energy or 802.15.4 radio solution

Introduction

This reference manual is addressed to application developers. It provides complete information on how to use the STM32WB50CG/30CE microcontroller memory and peripherals.

These multi-protocol wireless and ultra-low-power devices embed a powerful and ultra-low-power radio compliant with the Bluetooth ® Low Energy SIG specification 5.2 and with IEEE 802.15.4-2011. They contain a dedicated Arm ® Cortex ® -M0+ for performing the real-time low layer operation.

The STM32WB50CG provide value line microcontrollers with 1 Mbyte Flash memory and

128 Kbytes SRAM.

The STM32WB30CE provide value line microcontrollers with 512 Kbyte Flash memory and

96 Kbytes SRAM.

List of tables

List of tables

STM32WB50CG/30CE memory map and peripheral register boundary addresses. . . . . . 57

Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Flash memory - Single bank organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Number of wait states vs, Flash memory clock (HCLK4) frequency. . . . . . . . . . . . . . . . . . 66

Page erase overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Mass erase overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Errors in page-based row programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Option bytes format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 9.

Option bytes organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 10.

Option loading control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 11.

UID64 organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 12.

Flash memory read protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 13.

RDP regression from Level 1 to Level 0 and memory erase . . . . . . . . . . . . . . . . . . . . . . . 90

Table 14.

Access status vs. protection level and execution modes . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 17.

Flash memory interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 18.

Flash interface register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 19.

CRC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 20.

CRC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 21.

Sub-system low power wakeup sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 22.

Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 23.

Functionalities depending on system operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 24.

Low-power run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 25.

CPU CSTOP wakeup vs. system operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 26.

Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 27.

Low-power sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 28.

Stop0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 29.

Stop1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 30.

Stop2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 31.

Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 32.

Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 33.

PWR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 34.

Maximum clock source frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 35.

Peripheral clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Table 36.

Single core Low power debug configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 37.

RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Table 38.

Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Table 39.

GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Table 40.

SYSCFG register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

Table 41.

Peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

Table 42.

DMA1 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Table 43.

DMA internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

Table 44.

Programmable data width and endian behavior (when PINC = MINC = 1) . . . . . . . . . . . 297

Table 45.

DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Table 46.

DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

Table 47.

DMAMUX instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

Table 48.

DMAMUX: assignment of multiplexer inputs to resources . . . . . . . . . . . . . . . . . . . . . . . . 312

Table 49.

DMAMUX: assignment of trigger inputs to resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

Table 50.

DMAMUX: assignment of synchronization inputs to resources . . . . . . . . . . . . . . . . . . . . 313

RM0471 Rev 5 37/1202

List of tables RM0471

Table 51.

DMAMUX signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

Table 52.

DMAMUX interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

Table 53.

DMAMUX register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

Table 54.

CPU1 vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

Table 55.

CPU2 vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

Table 56.

Wakeup interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

Table 57.

EXTI pin overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

Table 58.

EVG pin overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

Table 59.

EXTI event input configurations and register control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

Table 60.

Masking functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

Table 61.

EXTI register map sections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

Table 62.

EXTI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

Table 63.

ADC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

Table 64.

ADC input/output pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

Table 65.

Configuring the trigger polarity for regular external triggers . . . . . . . . . . . . . . . . . . . . . . . 372

Table 66.

Configuring the trigger polarity for injected external triggers . . . . . . . . . . . . . . . . . . . . . . 372

Table 67.

ADC1 - External triggers for regular channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373

Table 68.

ADC1 - External trigger for injected channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373

Table 69.

TSAR timings depending on resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

Table 70.

Offset computation versus data resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

Table 71.

Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398

Table 72.

Analog watchdog 1 comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

Table 73.

Analog watchdog 2 and 3 comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

Table 74.

Maximum output results versus N and M (gray cells indicate truncation). . . . . . . . . . . . . 403

Table 75.

ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

Table 76.

ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

Table 77.

ADC register map and reset values (master and slave ADC common registers) offset = 0x300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

Table 78.

RNG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445

Table 79.

RNG interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452

Table 80.

RNG register map and reset map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

Table 81.

AES internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

Table 82.

CTR mode initialization vector definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

Table 83.

GCM last block definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

Table 84.

Initialization of SAES_IVRx registers in GCM mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

Table 85.

Initialization of AES_IVRx registers in CCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

Table 86.

Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . . . . . . . . . . . 490

Table 87.

AES interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

Table 88.

Processing latency for ECB, CBC and CTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

Table 89.

Processing latency for GCM and CCM (in clock cycles). . . . . . . . . . . . . . . . . . . . . . . . . . 494

Table 90.

AES register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

Table 91.

Internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

Table 92.

PKA integer arithmetic functions list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

Table 93.

PKA prime field (Fp) elliptic curve functions list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

Table 94.

Montgomery parameter computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513

Table 95.

Modular addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

Table 96.

Modular subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

Table 97.

Montgomery multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515

Table 98.

Modular exponentiation (normal mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

Table 99.

Modular exponentiation (fast mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

Table 100. Modular inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

Table 101. Modular reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

38/1202 RM0471 Rev 5

RM0471 List of tables

Table 102. Arithmetic addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

Table 103. Arithmetic subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

Table 104. Arithmetic multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

Table 105. Arithmetic comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

Table 106. CRT exponentiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

Table 107. Point on elliptic curve Fp check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520

Table 108. ECC Fp scalar multiplication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520

Table 109. ECC Fp scalar multiplication (Fast Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521

Table 110. ECDSA sign - Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

Table 111. ECDSA sign - Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

Table 112. Extended ECDSA sign (extra outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

Table 113. ECDSA verification (inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

Table 114. ECDSA verification (outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

Table 115. Family of supported curves for ECC operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524

Table 116. Modular exponentiation computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526

Table 117. ECC scalar multiplication computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526

Table 118. ECDSA signature average computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526

Table 119. ECDSA verification average computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527

Table 120. Point on elliptic curve Fp check average computation times . . . . . . . . . . . . . . . . . . . . . . 527

Table 121. Montgomery parameters average computation times. . . . . . . . . . . . . . . . . . . . . . . . . . . . 527

Table 122. PKA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527

Table 123. PKA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

Table 124. Behavior of timer outputs versus BRK/BRK2 inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574

Table 125. Break protection disarming conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

Table 126. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582

Table 127. TIM1 internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599

Table 128. Output control bits for complementary OCx and OCxN channels with break feature . . . . 613

Table 129. TIM1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629

Table 130. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665

Table 131. TIM2 internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682

Table 132. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693

Table 133. TIM2 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

Table 134. Break protection disarming conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725

Table 135. Output control bits for complementary OCx and OCxN channels with break feature

(TIM16/17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742

Table 136. TIM16/TIM17 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752

Table 137. LPTIM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755

Table 138. LPTIM input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756

Table 139. LPTIM internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756

Table 140. LPTIM1 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756

Table 141. LPTIM2 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756

Table 142. Prescaler division ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758

Table 143. Encoder counting scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765

Table 144. Effect of low-power modes on the LPTIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766

Table 145. Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767

Table 146. LPTIM register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777

Table 147. Effect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794

Table 148. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794

Table 149. RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818

Table 150. IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828

Table 151. WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834

Table 152. STM32WB50CG/30CE I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836

RM0471 Rev 5 39/1202

List of tables RM0471

Table 153. I2C input/output pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838

Table 154. I2C internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838

Table 155. Comparison of analog vs. digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840

Table 156. I2C-SMBus specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843

Table 157. I2C configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847

Table 158. I2C-SMBus specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858

Table 159. Examples of timing settings for fI2CCLK = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868

Table 160. Examples of timings settings for fI2CCLK = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868

Table 161. SMBus timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870

Table 162. SMBus with PEC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873

Table 163. Examples of TIMEOUTA settings for various I2CCLK frequencies

(max t

TIMEOUT

= 25 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874

Table 164. Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . . . . . . . . . . . . . . 874

Table 165. Examples of TIMEOUTA settings for various I2CCLK frequencies

(max t

IDLE

= 50 µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874

Table 166. Effect of low-power modes on the I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885

Table 167. I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886

Table 168. I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901

Table 169. USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905

Table 170. Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920

Table 171. Tolerance of the USART receiver when BRR [3:0] = 0000. . . . . . . . . . . . . . . . . . . . . . . . 923

Table 172. Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . . . . . . . . . . 924

Table 173. USART frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929

Table 174. Effect of low-power modes on the USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952

Table 175. USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953

Table 176. USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988

Table 177. SPI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991

Table 178. SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015

Table 179. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024

Table 180. IPCC interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026

Table 181. Bits used for the communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027

Table 182. IPCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1038

Table 183. HSEM internal input/output signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040

Table 184. Authorized AHB bus master IDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045

Table 185. HSEM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051

Table 186. JTAG/Serial-wire debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055

Table 187. Single Wire Trace port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055

Table 188. JTAG-DP data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059

Table 189. Packet request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060

Table 190. ACK response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061

Table 191. Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061

Table 192. Debug port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069

Table 193. Access port register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076

Table 194. CPU2 CTI inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077

Table 195. CPU2 CTI outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078

Table 196. CPU1 CTI inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078

Table 197. CPU1 CTI outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078

Table 198. CTI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094

Table 199. DBGMCU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1103

Table 200. CPU2 processor ROM table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105

Table 201. CPU2 ROM table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105

Table 202. CPU2 processor ROM table register map and reset values . . . . . . . . . . . . . . . . . . . . . . 1112

40/1202 RM0471 Rev 5

RM0471 List of tables

Table 203. CPU2 ROM table register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1118

Table 204. CPU2 DWT register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130

Table 205. CPU2 BPU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1139

Table 206. CPU1 ROM table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140

Table 207. CPU1 ROM table register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147

Table 208. CPU1 DWT register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1159

Table 209. CPU1 ITM register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168

Table 210. CPU1 FPB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175

Table 211. CPU1 TPIU register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186

Table 212. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192

RM0471 Rev 5 41/1202

List of figures

List of figures

RM0471

Figure 1.

System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 2.

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 3.

Sequential 16-bit instructions execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 4.

Changing the Read protection (RDP) level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 5.

Radio system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 6.

CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 7.

Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 8.

Brown-out reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 9.

PVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 10.

CPU2 boot options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 11.

Low-power modes possible transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 12.

Real time radio activity flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 13.

Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 14.

Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 15.

HSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 16.

LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Figure 17.

Frequency measurement with TIM16 in capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Figure 18.

Frequency measurement with TIM17 in capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Figure 19.

Three-volt or Five-volt tolerant GPIO structure (TT or FT) . . . . . . . . . . . . . . . . . . . . . . . . 248

Figure 20.

Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

Figure 21.

Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

Figure 22.

Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Figure 23.

High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Figure 24.

DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Figure 25.

DMAMUX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

Figure 26.

Synchronization mode of the DMAMUX request line multiplexer channel . . . . . . . . . . . . 317

Figure 27.

Event generation of the DMA request line multiplexer channel . . . . . . . . . . . . . . . . . . . . 317

Figure 28.

Interrupt block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

Figure 29.

EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

Figure 30.

Configurable event trigger logic CPU wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

Figure 31.

Direct event trigger logic CPU wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

Figure 32.

ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

Figure 33.

ADC clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

Figure 34.

ADC1 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

Figure 35.

ADC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

Figure 36.

Updating the ADC calibration factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

Figure 37.

Mixing single-ended and differential channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

Figure 38.

Enabling / disabling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

Figure 39.

Analog to digital conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

Figure 40.

Stopping ongoing regular conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371

Figure 41.

Stopping ongoing regular and injected conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371

Figure 42.

Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375

Figure 43.

Example of JSQR queue of context (sequence change) . . . . . . . . . . . . . . . . . . . . . . . . . 378

Figure 44.

Example of JSQR queue of context (trigger change) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

Figure 45.

Example of JSQR queue of context with overflow before conversion . . . . . . . . . . . . . . . 379

Figure 46.

Example of JSQR queue of context with overflow during conversion . . . . . . . . . . . . . . . 379

Figure 47.

Example of JSQR queue of context with empty queue (case JQM=0). . . . . . . . . . . . . . . 380

Figure 48.

Example of JSQR queue of context with empty queue (case JQM=1). . . . . . . . . . . . . . . 381

42/1202 RM0471 Rev 5

RM0471 List of figures

Figure 49.

Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).

Case when JADSTP occurs during an ongoing conversion. . . . . . . . . . . . . . . . . . . . . . . 381

Figure 50.

Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).

Case when JADSTP occurs during an ongoing conversion and a new trigger occurs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

Figure 51.

Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).

Case when JADSTP occurs outside an ongoing conversion . . . . . . . . . . . . . . . . . . . . . . 382

Figure 52.

Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) . . . . . . . . . . . . . . . . . . 383

Figure 53.

Flushing JSQR queue of context by setting ADDIS=1 (JQM=0). . . . . . . . . . . . . . . . . . . . 383

Figure 54.

Flushing JSQR queue of context by setting ADDIS=1 (JQM=1). . . . . . . . . . . . . . . . . . . . 384

Figure 55.

Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

Figure 56.

Continuous conversion of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . 386

Figure 57.

Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387

Figure 58.

Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . 387

Figure 59.

Right alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389

Figure 60.

Right alignment (offset enabled, signed value). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

Figure 61.

Left alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

Figure 62.

Left alignment (offset enabled, signed value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

Figure 63.

Example of overrun (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

Figure 64.

AUTODLY=1, regular conversion in continuous mode, software trigger . . . . . . . . . . . . . 395

Figure 65.

AUTODLY=1, regular HW conversions interrupted by injected conversions

(DISCEN=0; JDISCEN=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

Figure 66.

AUTODLY=1, regular HW conversions interrupted by injected conversions . . . . . . . . . . . . .

(DISCEN=1, JDISCEN=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

Figure 67.

AUTODLY=1, regular continuous conversions interrupted by injected conversions . . . . 397

Figure 68.

AUTODLY=1 in auto- injected mode (JAUTO=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

Figure 69.

Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398

Figure 70.

ADCy_AWDx_OUT signal generation (on all regular channels). . . . . . . . . . . . . . . . . . . . 400

Figure 71.

ADCy_AWDx_OUT signal generation (AWDx flag not cleared by software) . . . . . . . . . . 401

Figure 72.

ADCy_AWDx_OUT signal generation (on a single regular channel) . . . . . . . . . . . . . . . . 401

Figure 73.

ADCy_AWDx_OUT signal generation (on all injected channels) . . . . . . . . . . . . . . . . . . . 401

Figure 74.

20-bit to 16-bit result truncation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402

Figure 75.

Numerical example with 5-bit shift and rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402

Figure 76.

Triggered regular oversampling mode (TROVS bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 404

Figure 77.

Regular oversampling modes (4x ratio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

Figure 78.

Regular and injected oversampling modes used simultaneously . . . . . . . . . . . . . . . . . . . 406

Figure 79.

Triggered regular oversampling with injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

Figure 80.

Oversampling in auto-injected mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

Figure 81.

Temperature sensor channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408

Figure 82.

VBAT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409

Figure 83.

VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410

Figure 84.

RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445

Figure 85.

Entropy source model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446

Figure 86.

RNG initialization overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

Figure 87.

AES block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

Figure 88.

ECB encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

Figure 89.

CBC encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

Figure 90.

CTR encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462

Figure 91.

GCM encryption and authentication principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463

Figure 92.

GMAC authentication principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463

Figure 93.

CCM encryption and authentication principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464

Figure 94.

Encryption key derivation for ECB/CBC decryption (Mode 2). . . . . . . . . . . . . . . . . . . . . . 467

RM0471 Rev 5 43/1202

List of figures RM0471

Figure 95.

Example of suspend mode management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

Figure 96.

ECB encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469

Figure 97.

ECB decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469

Figure 98.

CBC encryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470

Figure 99.

CBC decryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470

Figure 100. ECB/CBC encryption (Mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

Figure 101. ECB/CBC decryption (Mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

Figure 102. Message construction in CTR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

Figure 103. CTR encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

Figure 104. CTR decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

Figure 105. Message construction in GCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

Figure 106. GCM authenticated encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

Figure 107. Message construction in GMAC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

Figure 108. GMAC authentication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

Figure 109. Message construction in CCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

Figure 110. CCM mode authenticated encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

Figure 111. 128-bit block construction with respect to data swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

Figure 112. DMA transfer of a 128-bit data block during input phase . . . . . . . . . . . . . . . . . . . . . . . . . 491

Figure 113. DMA transfer of a 128-bit data block during output phase . . . . . . . . . . . . . . . . . . . . . . . . 492

Figure 114. PKA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

Figure 115. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

Figure 116. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 536

Figure 117. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 536

Figure 118. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

Figure 119. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

Figure 120. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

Figure 121. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

Figure 122. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 540

Figure 123. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . . 540

Figure 124. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

Figure 125. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

Figure 126. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

Figure 127. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

Figure 128. Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . . 544

Figure 129. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 545

Figure 130. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546

Figure 131. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 546

Figure 132. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547

Figure 133. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 547

Figure 134. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 548

Figure 135. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 549

Figure 136. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550

Figure 137. TIM1 ETR input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550

Figure 138. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 551

Figure 139. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

Figure 140. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553

Figure 141. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553

Figure 142. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

Figure 143. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 555

Figure 144. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555

Figure 145. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . . . . . . . . . 556

Figure 146. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 556

44/1202 RM0471 Rev 5

RM0471 List of figures

Figure 147. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . . . . . . . . . . . . . . 557

Figure 148. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559

Figure 149. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

Figure 150. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562

Figure 151. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

Figure 152. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . . 565

Figure 153. Combined PWM mode on channel 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566

Figure 154. 3-phase combined PWM signals with multiple trigger pulses per period . . . . . . . . . . . . . 567

Figure 155. Complementary output with dead-time insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568

Figure 156. Dead-time waveforms with delay greater than the negative pulse . . . . . . . . . . . . . . . . . . 568

Figure 157. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 569

Figure 158. Break and Break2 circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

Figure 159. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . . . . . . . . 573

Figure 160. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . . . . . . . . . . . . 574

Figure 161. PWM output state following BRK assertion (OSSI=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

Figure 162. Output redirection (BRK2 request not represented) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

Figure 163. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577

Figure 164. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578

Figure 165. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579

Figure 166. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581

Figure 167. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 582

Figure 168. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 583

Figure 169. Measuring time interval between edges on 3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584

Figure 170. Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586

Figure 171. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

Figure 172. Control circuit in Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

Figure 173. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589

Figure 174. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 590

Figure 175. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633

Figure 176. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 635

Figure 177. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 635

Figure 178. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636

Figure 179. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

Figure 180. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

Figure 181. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638

Figure 182. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 638

Figure 183. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 639

Figure 184. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640

Figure 185. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640

Figure 186. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641

Figure 187. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641

Figure 188. Counter timing diagram, Update event when repetition counter is not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642

Figure 189. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 643

Figure 190. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644

Figure 191. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 644

Figure 192. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645

Figure 193. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 645

Figure 194. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 646

Figure 195. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 647

Figure 196. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

Figure 197. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648

RM0471 Rev 5 45/1202

List of figures RM0471

Figure 198. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649

Figure 199. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650

Figure 200. Capture/Compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 650

Figure 201. Capture/Compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651

Figure 202. Output stage of Capture/Compare channel (channel 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 651

Figure 203. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653

Figure 204. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655

Figure 205. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656

Figure 206. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658

Figure 207. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . . 659

Figure 208. Combined PWM mode on channels 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660

Figure 209. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661

Figure 210. Example of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662

Figure 211. Retriggerable one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664

Figure 212. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 665

Figure 213. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 666

Figure 214. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667

Figure 215. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668

Figure 216. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

Figure 217. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 670

Figure 218. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670

Figure 219. Master/slave connection example with 1 channel only timers . . . . . . . . . . . . . . . . . . . . . 671

Figure 220. Gating TIM2 with OC1REF of TIM1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672

Figure 221. Gating TIM2 with Enable of TIM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

Figure 222. Triggering TIM2 with update of TIM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

Figure 223. Triggering TIM2 with Enable of TIM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674

Figure 224. TIM16/TIM17 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704

Figure 225. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 706

Figure 226. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 706

Figure 227. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708

Figure 228. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708

Figure 229. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709

Figure 230. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709

Figure 231. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710

Figure 232. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710

Figure 233. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 712

Figure 234. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 713

Figure 235. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713

Figure 236. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714

Figure 237. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 715

Figure 238. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715

Figure 239. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 716

Figure 240. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719

Figure 241. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720

Figure 242. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721

Figure 243. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 721

Figure 244. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 722

Figure 245. Output behavior in response to a break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724

Figure 246. Output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726

Figure 247. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727

46/1202 RM0471 Rev 5

RM0471 List of figures

Figure 248. Example of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729

Figure 249. Low-power timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755

Figure 250. Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758

Figure 251. LPTIM output waveform, single counting mode configuration . . . . . . . . . . . . . . . . . . . . . 759

Figure 252. LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760

Figure 253. LPTIM output waveform, Continuous counting mode configuration . . . . . . . . . . . . . . . . . 760

Figure 254. Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762

Figure 255. Encoder mode counting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766

Figure 256. IRTIM internal hardware connections with TIM16 and TIM17 . . . . . . . . . . . . . . . . . . . 778

Figure 257. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781

Figure 258. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820

Figure 259. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830

Figure 260. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831

Figure 261. I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837

Figure 262. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839

Figure 263. Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841

Figure 264. I2C initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844

Figure 265. Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845

Figure 266. Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846

Figure 267. Slave initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849

Figure 268. Transfer sequence flowchart for I2C slave transmitter,

NOSTRETCH= 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851

Figure 269. Transfer sequence flowchart for I2C slave transmitter,

NOSTRETCH= 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852

Figure 270. Transfer bus diagrams for I2C slave transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853

Figure 271. Transfer sequence flowchart for slave receiver with NOSTRETCH=0 . . . . . . . . . . . . . . 854

Figure 272. Transfer sequence flowchart for slave receiver with NOSTRETCH=1 . . . . . . . . . . . . . . 855

Figure 273. Transfer bus diagrams for I2C slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855

Figure 274. Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857

Figure 275. Master initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859

Figure 276. 10-bit address read access with HEAD10R=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859

Figure 277. 10-bit address read access with HEAD10R=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860

Figure 278. Transfer sequence flowchart for I2C master transmitter for N ≤ 255 bytes . . . . . . . . . . . . 861

Figure 279. Transfer sequence flowchart for I2C master transmitter for N>255 bytes . . . . . . . . . . . . 862

Figure 280. Transfer bus diagrams for I2C master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863

Figure 281. Transfer sequence flowchart for I2C master receiver for N ≤ 255 bytes . . . . . . . . . . . . . . 865

Figure 282. Transfer sequence flowchart for I2C master receiver for N >255 bytes . . . . . . . . . . . . . . 866

Figure 283. Transfer bus diagrams for I2C master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867

Figure 284. Timeout intervals for t

LOW:SEXT

, t

LOW:MEXT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871

Figure 285. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . . 875

Figure 286. Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . . . . . . . . . . . . . . . . . . 875

Figure 287. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC . . . . . . . . . . . . . 877

Figure 288. Bus transfer diagrams for SMBus slave receiver (SBC=1). . . . . . . . . . . . . . . . . . . . . . . . 878

Figure 289. Bus transfer diagrams for SMBus master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879

Figure 290. Bus transfer diagrams for SMBus master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881

Figure 291. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906

Figure 292. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909

Figure 293. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911

Figure 294. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914

Figure 295. Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915

Figure 296. usart_ker_ck clock divider block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918

RM0471 Rev 5 47/1202

List of figures RM0471

Figure 297. Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919

Figure 298. Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920

Figure 299. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927

Figure 300. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928

Figure 301. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . . 931

Figure 302. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 932

Figure 303. USART example of synchronous master transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . 933

Figure 304. USART data clock timing diagram in synchronous master mode

(M bits = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933

Figure 305. USART data clock timing diagram in synchronous master mode

(M bits = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934

Figure 306. USART data clock timing diagram in synchronous slave mode

(M bits = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935

Figure 307. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937

Figure 308. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939

Figure 309. IrDA SIR ENDEC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943

Figure 310. IrDA data modulation (3/16) - Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943

Figure 311. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945

Figure 312. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946

Figure 313. Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946

Figure 314. RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947

Figure 315. RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948

Figure 316. Wakeup event verified (wakeup event = address match, FIFO disabled) . . . . . . . . . . . . 951

Figure 317. Wakeup event not verified (wakeup event = address match,

FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951

Figure 318. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991

Figure 319. Full-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992

Figure 320. Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993

Figure 321. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994

Figure 322. Master and three independent slaves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995

Figure 323. Multi-master application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996

Figure 324. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997

Figure 325. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998

Figure 326. Data alignment when data length is not equal to 8-bit or 16-bit . . . . . . . . . . . . . . . . . . . . 999

Figure 327. Packing data in FIFO for transmission and reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003

Figure 328. Master full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006

Figure 329. Slave full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007

Figure 330. Master full-duplex communication with CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008

Figure 331. Master full-duplex communication in packed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009

Figure 332. NSSP pulse generation in Motorola SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . 1012

Figure 333. TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013

Figure 334. IPCC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026

Figure 335. IPCC Simplex channel mode transfer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027

Figure 336. IPCC Simplex - Send procedure state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028

Figure 337. IPCC Simplex - Receive procedure state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029

Figure 338. IPCC Half-duplex channel mode transfer timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030

Figure 339. IPCC Half-duplex - Send procedure state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030

Figure 340. IPCC Half-duplex - Receive procedure state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 1031

Figure 341. HSEM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040

Figure 342. Procedure state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041

Figure 343. Interrupt state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044

48/1202 RM0471 Rev 5

RM0471 List of figures

Figure 344. Block diagram of debug support infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055

Figure 345. JTAG TAP state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058

Figure 346. Debug and access port connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070

Figure 347. Embedded cross trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077

Figure 348. Mapping trigger inputs to outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079

Figure 349. Cross trigger configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080

Figure 350. CPU2 CoreSight™ topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1106

Figure 351. CPU1 CoreSight™ topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1141

Figure 352. Trace port interface unit (TPIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1176

RM0471 Rev 5 49/1202

Documentation conventions

The STM32WB50CG/30CE devices embed an Arm

® (a)

CPU1 Cortex

-M4 core.

RM0471

1.2 List of abbreviations for registers

The following abbreviations

(b)

are used in register descriptions: read-only (r) write-only (w) read/write (rw) read/clear write0 (rc_w0) read/clear write1 (rc_w1) read/clear write (rc_w) read/clear by read (rc_r) read/set by read (rs_r)

Software can read and write to this bit.

Software can only read this bit.

Software can only write to this bit. Reading this bit returns the reset value.

Software can read as well as clear this bit by writing 0. Writing 1 has no effect on the bit value.

Software can read as well as clear this bit by writing 1. Writing 0 has no effect on the bit value.

Software can read as well as clear this bit by writing to the register. The value written to this bit is not important.

Software can read this bit. Reading this bit automatically clears it to 0.

Writing this bit has no effect on the bit value.

Software can read this bit. Reading this bit automatically sets it to 1.

Writing this bit has no effect on the bit value.

read/set (rs) read/write once (rwo)

Software can read as well as set this bit. Writing 0 has no effect on the bit value.

Software can only write once to this bit and can also read it at any time.

Only a reset can return the bit to its reset value.

The software can toggle this bit by writing 1. Writing 0 has no effect.

toggle (t) read-only write trigger (rt_w1) Software can read this bit. Writing 1 triggers an event but has no effect on the bit value.

Reserved (Res.) Reserved bit, must be kept at reset value.

50/1202 a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

b. This is an exhaustive list of all abbreviations applicable to STMicroelectronics microcontrollers, some of them may not be used in the current document.

RM0471 Rev 5

RM0471 Documentation conventions

1.3 Glossary

This section gives a brief definition of acronyms and abbreviations used in this document:

 Word : data of 32-bit length.

 Half-word : data of 16-bit length.

 Byte : data of 8-bit length.

 AHB : advanced high-performance bus.

For availability of peripherals and their number across all sales types, refer to the particular device datasheet.

RM0471 Rev 5 51/1202

System and memory overview

2 System and memory overview

RM0471

The main system consists of 32-bit multilayer AHB bus matrix that interconnects:

 Seven masters:

– CPU1 (CPU1 Cortex

-M4 with FPU) core I-bus

– CPU1 (CPU1 Cortex ® -M4 with FPU) core D-bus

– CPU1 (CPU1 Cortex

-M4 with FPU) core S-bus

– CPU2 (Cortex ® -M0+) core S-bus

– DMA1

– Radio system

 Ten slaves:

– Internal Flash memory on the CPU1 (CPU1 Cortex ® -M4) ICode bus

– Internal Flash memory on CPU1 (CPU1 Cortex

-M4) DCode bus

– Internal Flash memory on CPU2 (Cortex ® -M0+) S bus

– Internal SRAM1 (64 KB for the STM32WB50CG, 32 KB for the STM32WB30CE)

– Internal SRAM2a (32 KB) + SRAM2b (32 KB)

– AHB1 peripherals including AHB to APB bridges and APB peripherals (connected to APB1 and APB2)

– AHB2 peripherals

– AHB4 shared peripheral

– AHB5 including AHB to APB bridge and Radio peripherals (connected to APB3)

The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even when several high-speed peripherals work simultaneously. This architecture is shown in

Figure 1 .

52/1202 RM0471 Rev 5

RM0471

CPU1

Arm

Cortex

-M4

Figure 1. System architecture

CPU2

Arm

Cortex

-M0+

DMA1

Radio system

System and memory overview

S0 S1 S2 S3 S4 S6

CFI arbiter

Flash memory

SRAM1

SRAM2

AHB1

AHB2

2.1.1

2.1.2

2.1.3

AHB4

AHB5

BusMatrix when remapped

MS52642V1

S0: CPU1 (CPU1 Cortex

-M4) I-bus

This bus connects the instruction bus of the CPU1 core to the BusMatrix. This bus is used by the core to fetch instructions. The targets of this bus are the internal Flash memory,

SRAM1, SRAM2a (backup) and SRAM2b (non backup).

S1: CPU1 (CPU1 Cortex

-M4) D-bus

This bus connects the data bus of the CPU1 core to the BusMatrix. This bus is used by the core for literal load and debug access. The targets of this bus are the internal Flash memory,

SRAM1, SRAM2a (backup) and SRAM2b (non backup).

S2: CPU1 (CPU1 Cortex

-M4) S-bus

This bus connects the system bus of the CPU1 core to the BusMatrix. This bus is used by the core to access data located in a peripheral or SRAM area. The targets of this bus are

SRAM1, SRAM2a (backup), SRAM2b (non backup), the AHB1 peripherals including the

APB1 and APB2 peripherals, the AHB2 peripherals and the AHB4 peripherals.

RM0471 Rev 5 53/1202

System and memory overview

2.1.4

RM0471

S3: CPU2 (Cortex

-M0+) S-bus

This bus connects the system bus of the CPU2 core to the BusMatrix. This bus is used by the core to fetch instructions, for literal load and debug access, and access data located in a peripheral or SRAM area. The targets of this bus are the internal Flash memory, SRAM1,

SRAM2a (backup), SRAM2b (non backup), the AHB1 peripherals including the APB1 and

APB2 peripherals, the AHB2 peripherals, and the AHB4 peripherals and the AHB5 peripherals including the APB3 peripherals.

2.1.6

This bus connects the AHB master interface of the DMA to the BusMatrix.The targets of this bus are the SRAM1, SRAM2a (backup), SRAM2b (non backup), the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals and the AHB4 peripherals.

S6: Radio system-bus

This bus connects the AHB master interface of the Radio system to the BusMatrix.The targets of this bus are the SRAM2a (backup) and SRAM2b (non backup).

2.1.7 BusMatrix

The BusMatrix manages the access arbitration between masters. The arbitration uses a

Round Robin algorithm. The BusMatrix is composed by six masters (CPU1: system bus,

DCode bus, ICode bus, CPU2: system bus, DMA1-bus and Radio system-bus) and nine slaves (3 x Flash memory, SRAM1, SRAM2a (backup), SRAM2b (non backup), AHB1

(including APB1 and APB2), AHB2, AHB4, and AHB5).

Note:

AHB/APB bridges

The two bridges AHB to APB1 and AHB to ABP2 provide full synchronous connections between the AHB and the two APB buses, allowing flexible selection of the peripheral frequency.

The bridges AHB to APB3 provide an a-synchronous connections between the AHB and the

APB bus, allowing flexible selection of the frequency between the AHB and peripheral.

Refer to Section 2.2: Memory organization for the address mapping of the peripherals

connected to this bridge.

After each device reset, all peripheral clocks are disabled (except for the SRAM1/2 and

Flash memory interface). Before using a peripheral you have to enable its clock in the

RCC_AHBxENR and the RCC_APBxENR registers.

When a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

54/1202 RM0471 Rev 5

RM0471

2.2.1 Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear

4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.

The addressable memory space is divided into eight main blocks, of 512 Mbytes each.

RM0471 Rev 5 55/1202

RM0471

2.2.2 Memory map and register boundary addresses

Figure 2. Memory map

0xFFFF FFFF

0xE000 0000

0x6000 0000

0x5800 0000

0x4800 0000

0x4000 0000

0x2004 0000

Cortex

M4 and M0+

Internal

APB3 RF

(2)

AHB Shared

AHB2

AHB1

CFI

PKA RAM

PKA

AES

HSEM

TRNG

IPCC

EXTI

PWR

RCC

Legend

Securable IP

(1) Only accessible by CPU1

(2) Only accessible by CPU2

(3) At this address range only accessible by CPU1

(4) CPU2 execution from

SRAM can be disabled by

SYSCFG sticky register bit

C2RFD

Reserved

0x2003 8000

SRAM2b

(4)

SRAM2a

(4)

0x2003 0000

0x2001 0000

0x2000 0000

0x1FFF 8000

0x1FFF 7400

0x1FFF 7000

0x1FFF 0000

0x1001 0000

SRAM1

(4)

Option bytes

Enginering bytes

OTP Area

System Flash

ADC

GPIOH

GPIOE

GPIOC

GPIOB

GPIOA

TIM17

TIM16

USART1

SPI1

TIM1

SYSCFG

SRAM2b

(3)(4)

SRAM2a

(3)(4)

0x1000 0000

0x0810 0000 CRC

0x0800 0000

0x0010 0000

Flash

Cortex

M4 and M0+ internal code space

TSC

DMAMUX

DMA

APB2

APB1

LPTIM2

LPTIM1

I2C1

IWDG

WWDG

RTC and TAMP

TIM2

0x0000 0000

MS52643V1

All the memory areas not allocated to on-chip memories and peripherals are considered

“Reserved”. For the detailed mapping of available memory and register areas, refer to the following table, which gives the boundary addresses of the available peripherals.

56/1202 RM0471 Rev 5

RM0471

Table 1. STM32WB50CG/30CE memory map and peripheral register boundary addresses

Bus Boundary address Size (bytes) Peripheral Peripheral register map

APB3

0x6000 2000 - 0xDFFF FFFF

0x6000 1000 - 0x6000 1FFF

0x6000 0800 - 0x6000 0FFF

0x6000 0400 - 0x6000 07FF

0x6000 0000 - 0x6000 03FF

0x5800 4400 - 0x5FFF FFFF

0x5800 4000 - 0x5800 43FF

4 K

2 K

1 K

Reserved

802.15.4 CTRL

Reserved

Radio CTRL

BLE CTRL

Reserved

FLASH

Section 3.10.20: FLASH register map on page 115

0x5800 3400 - 0x5800 3FFF

0x5800 2400 - 0x5800 33FF

0x5800 2000 - 0x5800 23FF

0x5800 1C00 - 0x5800 1FFF

5 K

1 K

Reserved

PKA RAM

PKA

Reserved

Section 18.7.5: PKA register map on page 531

AHB4

AHB2

0x5800 1800 - 0x5800 1BFF

0x5800 1400 - 0x5800 17FF

0x5800 1000 - 0x5800 13FF

0x5800 0C00 - 0x5800 0FFF

0x5800 0800 - 0x5800 0BFF

0x5800 0400 - 0x5800 07FF

0x5800 0000 - 0x5800 03FF

0x5004 0400 - 0x57FF FFFF

0x5004 0000 - 0x5004 03FF

0x4800 1C00 - 0x4800 1FFF

1 K

1 KB

AES2

HSEM

True RNG

IPCC

EXTI

PWR

RCC

Reserved

ADC

GPIOH

Section 17.7.18: AES register map on page 504

Section 31.4.9: HSEM register map on page 1051

Section 16.7.4: RNG register map on page 456

Section 30.4.9: IPCC register map on page 1038

Section 14.5.17: EXTI register map on page 351

Section 6.6.21: PWR register map and reset value table on page 168

Section 7.4.47: RCC register map on page 241

Section 15.7: ADC register map on page 441

Section 8.4.12: GPIO register map on page 265

0x4800 1400 - 0x4800 1BFF

0x4800 1000 - 0x4800 13FF

0x4800 0C00 - 0x4800 0FFF

0x4800 0800 - 0x4800 0BFF

0x4800 0400 - 0x4800 07FF

0x4800 0000 - 0x4800 03FF

3 K

1 K

Reserved

GPIOE

Reserved

GPIOC

GPIOB

GPIOA

Section 8.4.12: GPIO register map on page 265

RM0471 Rev 5 57/1202

RM0471

Table 1. STM32WB50CG/30CE memory map and peripheral register boundary addresses

Bus Boundary address Size (bytes) Peripheral Peripheral register map

0x4002 3400 - 0x47FF FFFF Reserved

AHB1

APB2

0x4002 3000 - 0x4002 33FF

0x4002 0C00 - 0x4002 2FFF

0x4002 0800 - 0x4002 0BFF

0x4002 0400 - 0x4002 07FF

0x4002 0000 - 0x4002 03FF

0x4001 4C00 - 0x4001 FFFF

0x4001 4800 - 4001 4BFF

0x4001 4400 - 4001 47FF

0x4001 3C00 - 4001 43FF

0x4001 3800 - 4001 3BFF

0x4001 3400 - 4001 37FF

0x4001 3000 - 4001 33FF

0x4001 2C00 - 4001 2FFF

0x4001 0400 - 4001 2BFF

0x4001 0200 - 4001 03FF

0x4001 0100 - 4001 01FF

0x4001 0030 - 4001 00FF

0x4001 0000 - 4001 002F

1 K

9 K

1 K

45 K

1 K

2 K

1 K

10 K

1 K

CRC

Reserved

DMAMUX

Reserved

DMA1

Reserved

TIM17

TIM16

Reserved

USART1

Reserved

SPI1

TIM1

Reserved

SYSCFG

Reserved

SYSCFG

Section 5.4.6: CRC register map on page 125

Section 12.6.7: DMAMUX register map on page 324

Section 11.6.7: DMA register map on page 307

Section 21.4.23: TIM16/TIM17 register map on page 752

Section 28.8.15: USART register map on page 988

Section 29.6.8: SPI register map on page 1024

Section 19.4.30: TIM1 register map on page 629

Section 9.2.17: SYSCFG register map on page 283

58/1202 RM0471 Rev 5

RM0471

Table 1. STM32WB50CG/30CE memory map and peripheral register boundary addresses

Bus Boundary address Size (bytes) Peripheral Peripheral register map

0x4000 9800 - 4000 FFFF 26 K

APB1

AHB4

AHB1

AHB4

0x4000 9400 - 04000 97FF

0x4000 8000 - 04000 93FF

0x4000 7C00 - 04000 7FFF

0x4000 5800 - 04000 7BFF

0x4000 5400 - 04000 57FF

0x4000 3400 - 04000 53FF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 0400 - 0x4000 27FF

0x4000 0000 - 0x4000 03FF

0x2003 8000 - 0x2003 FFFF

0x2003 0000 - 0x2003 7FFF

0x2001 0000 - 0x2002 FFFF

0x2000 0000 - 0x2000 FFFF

0x1FFF 8000 - 0x1FFF 807F

0x1FFF 7000 - 0x1FFF 73FF

0x1FFF 0000 - 0x1FFF 6FFF

0x1000 0000 - 0x1000 FFFF

0x0800 0000 - 0x080 FFFF

1 K

5 K

1 K

9 K

1 K

8 K

1 K

9 K

1 K

32 K

64 K

128

1 K

28 K

64 K

1 M

(2)

(3)

0x0000 0000 - 0x000 FFFF 1 M

(2)

1. 64 KB for STM32WB50CG, 32 KB for STM32WB30CE.

2. 1 MB for STM32WB50CG, 512 KB for STM32WB30CE.

3. Bus depends upon selected CPUn Boot area.

Reserved

LPTIM2

Reserved

LPTIM1

Reserved

I2C1

Reserved

IWDG

WWDG

RTC and TAMP

Reserved

TIM2

SRAM2b

SRAM2a

Reserved

SRAM1

(1)

Flash memory options

Flash memory

OTP

Flash memory

Boot loader

SRAM2a/b

CPU1 mirror

User Flash memory

CPUn Boot area

Section 22.7.9: LPTIM register map on page 777

Section 27.7.12: I2C register map on page 901

Section 25.4.6: IWDG register map on page 828

Section 26.5.4: WWDG register map on page 834

Section 24.6.21: RTC register map on page 818

Section 20.4.25: TIMx register map on page 700

Section 3.10.20: FLASH register map on page 115

RM0471 Rev 5 59/1202

RM0471

The CPU1 map includes two bit-band regions. These regions map each word in an alias region of memory to a bit in a bit-band region of memory. writing to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region.

The AHB1, APB1, APB2 peripheral registers and the SRAM1, SRAM2a and SRAM2b are mapped to a bit-band region, hence single bit-band write and read operations are allowed.

The operations are only available for CPU1 accesses, and not form other bus masters (e.g.

DMA)

The peripheral bit-band alias is located from address 0x4200 0000 to 0x42FF FFFF

The SRAM bit-band alias is located from address 0x2200 0000 to 0x227F FFFF

A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region. The mapping formula is: bit_word_addr = bit_band_base + (byte_offset * 32) + (bit_number * 4) where:

– bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit.

– bit_band_base is the starting address of the alias region

– byte_offset is the number of the byte in the bit_band region that contains the targeted bit

– bit_number is the bit position (0-7) of the targeted bit

Example

The following example shows how to map bit [2] of the byte located at SRAM1 address

0x2000 0300 to the alias region.

0x2200 6008 = 0x2200 0000 + 0x0300 * 32 + 2 * 4

Writing to address 0x2200 6008 has the same effect as a read-modify-write operation on bit

[2] of the byte at SRAM1 address 0x2000 0300.

Reading address 0x2200 6008 returns the value 0x01 or 0x00 of bit [2] of the byte at

SRAM1 address 0x2000 0300.

For more information on bit-band, refer to the Cortex

-M4 programming manual.

Three different CPU1 boot modes can be selected through the BOOT0 pin and nBOOT1 bit in the User options, as shown in

Table 2

nBOOT1

FLASH_OPTR[23] nBOOT0

FLASH_OPTR[27] x x x x

Table 2. Boot modes

BOOT0 pin PH3 nSWBOOT0

FLASH_OPTR[26]

Main Flash empty

(1)

Boot memory space alias

Main Flash memory is selected as boot area

System memory is selected as boot area

60/1202 RM0471 Rev 5

RM0471 nBOOT1

FLASH_OPTR[23]

Table 2. Boot modes (continued) nBOOT0

FLASH_OPTR[27]

BOOT0 pin PH3 nSWBOOT0

FLASH_OPTR[26]

Main Flash empty

(1)

Boot memory space alias x 1 x 0 x

Main Flash memory is selected as boot area

1 x

0 x

1 x

0 x x x x

Embedded SRAM1 is selected as boot area

System memory is selected as boot area

1. A Flash empty check mechanism is implemented to force the boot from system Flash if the first Flash memory location is not programmed (0xFFFF FFFF) and if the boot selection was configured to boot from the main Flash.

The values on both BOOT0 and BOOT1 are latched after a reset. It is up to the user to provide the correct value for the required boot mode.

The BOOT0 and BOOT1 are also re-sampled when exiting Standby mode. Consequently they must be kept in the required boot mode. After the startup delay, the CPU1 fetches the top-of-stack from address 0x0000 0000, then starts code execution from the boot memory at

0x0000 0004.

Depending on the selected boot mode, main Flash, system Flash, or SRAM1 memories are accessible as follows:

 Boot from main Flash memory: the main Flash memory is aliased in the CPU1 boot memory space at address 0x0000 0000, and is also still accessible from its physical address 0x0800 0000. In other words, the Flash memory contents can be accessed starting from address 0x0000 0000 or 0x0800 0000.

 Boot from System Flash memory: the system Flash memory is aliased in the CPU1 boot memory space at address 0x0000 0000, and is also still accessible from its physical address 0x1FFF 0000.

 Boot from SRAM memory: the SRAM is aliased in the CPU1 boot memory space at address 0x0000 0000, and is also still accessible from its physical address 0x2000

0000.

CPU1 physical remap

Following CPU1 boot the application software can modify the memory map at address

0x0000 0000. This modification is performed by programming the SYSCFG memory remap register (SYSCFG_MEMRMP)

in the SYSCFG controller.

The following memories can be remapped:

 Main Flash memory

 System Flash memory

 SRAM

RM0471 Rev 5 61/1202

RM0471

Embedded boot loader

The embedded boot loader is located in the system Flash memory, programmed by ST during production. It is used to program the Flash memory using one of the following device interfaces:

 USART1 on pins PA9 and PA10

 I2C1 on pins PB6 and PB7.

 SPI1 on pins PA4, PA5, PA6 and PA7

2.5

Following a device reset the CPU2 will only boot after CPU1 has set the C2BOOT bit in the

PWR control register 4 (PWR_CR4)

. The C2BOOT value is retained in Standby mode and the CPU2 will boot accordingly when exit from Standby.

The CPU2 will boot from it boot reset vector as defined by the Flash user Option C2OPT and SBRV.

The CPU2 may boot from anywhere in User Flash or SRAM1/SRAM2a/SRAM2b.

CPU2 safe boot

When, after a reset, the User options are not valid and the BOOT0 and BOOT1 select CPU1 to boot from main Flash memory, the CPU2 will boot instead from a safe boot vector in main

Flash memory at address 0x080F F000.

The safe boot can be used to restore the last known user options from an copied image.

CPU2 SRAM fetch disable

CPU2 execution from SRAM can be disabled by the C2RFD bit in SYSCFG register.

Disabling CPU2 execution from SRAM improves robustness of the CPU2 software.

62/1202 RM0471 Rev 5

RM0471

3

Embedded Flash memory (FLASH)

Embedded Flash memory (FLASH)

3.1 Introduction

The Flash memory interface manages CPU1 (CPU1 Cortex

-M4) AHB ICode and DCode accesses and the CPU2 (Cortex

-M0+) AHB to the Flash memory. It implements the access arbitration between the two CPUs, the erase and program Flash memory operations, the read and write protection, and the security mechanisms.

The Flash memory interface accelerates code execution with a system of instruction prefetch and cache lines.

3.2 FLASH main features

 Up to 1 Mbyte of Flash memory single bank architecture

 Memory organization: 1 bank

– main memory: up to 1 Mbyte

– page size: 4 Kbytes

 72-bit wide data read (64 bits plus 8 ECC bits)

 72-bit wide data write (64 bits plus 8 ECC bits)

 Page erase (4 Kbytes), and mass erase

Flash memory interface features:

 Flash memory read operations

 Flash memory program/erase operations

 Read protection activated by option (RDP)

 Two write protection areas selected by option (WRP)

 Two proprietary code read protection area selected by option (PCROP)

 CPU2 Security area

 Flash empty check

 Program and Erase suspension feature

 Prefetch on CPU1 ICODE and CPU2 S-bus

 CPU1 instruction cache: 32 cache lines of 4 x 64 bits on ICode (1 Kbyte RAM)

 CPU1 data cache: eight cache lines of 4 x 64 bits on DCode (256 bytes RAM)

 CPU2 instruction cache: four cache lines of 1 x 64 bits on S-bus (32 bytes RAM)

 Error code correction (ECC): eight bits for 64-bit

 Option byte loader

3.3 FLASH functional description

The Flash memory is organized as 72-bit wide memory cells (64 bits, plus 8 ECC bits) that can be used for storing both code and data constants.

RM0471 Rev 5 63/1202

116

Embedded Flash memory (FLASH) RM0471

The Flash memory is organized as follows:

 a main memory block containing up to 256 pages for STM32WB50CG, up to 128 pages for STM32WB30CE of 4 Kbytes, each page with eight rows of 512 bytes.

 an information block containing:

– System memory from which the CPU1 boots in System memory boot mode. The area is reserved and contains the boot loader used to reprogram the Flash memory through one of the following interfaces: USART1, I2C1 SPI1. It is programmed by STMicroelectronics when the device is manufactured, and protected against spurious write/erase operations. For further details, refer to the

AN2606 available from www.st.com

– 1 Kbyte (128 double words) OTP (one-time programmable) for user data. The

OTP data cannot be erased and can be written only once. If only one bit is at 0, the entire double word (64 bits) cannot be written anymore, even with the value

0x0000 0000 0000 0000.

The OTP area cannot be read when RDP level is 1 and boot source is not Flash memory user area.

– Option bytes for user configuration.

The memory organization is based on a main area and an information block as shown in

Table 3 .

Area

Table 3. Flash memory - Single bank organization

Addresses Size (bytes)

Main memory

(1)

Information block

0x0800 0000 - 0x0800 0FFF

0x0800 1000 - 0x0800 1FFF

0x0800 2000 - 0x0800 2FFF

0x0807 E000 - 0x0807 EFFF

0x0807 F000 - 0x0807 FFFF

0x0808 0000 - 0x0808 0FFF

0x080F E000 - 0x080F EFFF

0x080F F000 - 0x080F FFFF

0x1FFF 0000 - 0x1FFF 6FFF

0x1FFF 7000 - 0x1FFF 73FF

0x1FFF 8000 - 0x1FFF 807F

1. Pages 128 to 255 available on STM32WB50CG only.

4 K

28 K

1 K

128

Name

Page 0

Page 1

Page 2

Page 126

Page 127

Page 128

Page 254

Page 255

System memory

OTP area

Option bytes

64/1202 RM0471 Rev 5

RM0471 Embedded Flash memory (FLASH)

3.3.3

Note:

During the OBL phase, after loading all options, the Flash memory interface checks whether the first location of the main memory is programmed. The result of this check in conjunction with the boot0 and boot1 information is used to determine where the system has to boot from. It prevents the system to boot from Flash main memory area when, for instance, no user code has been programmed.

The Flash main memory empty check status can be read from the EMPTY bit in Flash memory access control register (FLASH_ACR) . Software can modify the Flash main

memory empty status by writing to the EMPTY bit.

Error code correction (ECC)

Data in Flash memory words are 72-bit wide: eight bits are added per each double word

(64 bits). The ECC mechanism supports:

 One error detection and correction

 Two errors detection

When one error is detected and corrected, the flag ECCC (ECC correction) is set in

Flash memory ECC register (FLASH_ECCR)

. If ECCCIE is set, an interrupt is generated.

When two errors are detected, a flag ECCD (ECC detection) is set in

Flash memory ECC register (FLASH_ECCR)

. In this case, a NMI is generated.

When an ECC error is detected, the address of the failing double word is saved in

ADDR_ECC[16:0] in the FLASH_ECCR register. ADDR_ECC[2:0] are always cleared. The bus-ID of the CPU accessing the address is saved in CPUID[2:0].

While ECCC or ECCD is set, FLASH_ECCR is not updated if a new ECC error occurs.

FLASH_ECCR is updated only when ECC flags are cleared.

For a virgin data (0xFF FFFF FFFF FFFF FFFF), one error is detected and corrected, but two errors detection is not supported.

When an ECC error is reported, a new read at the failing address may not generate an ECC error if the data is still present in the current buffer, even if ECCC and ECCD are cleared. If this is not the desired behavior, the user must reset the cache.

To correctly read data from Flash memory, the number of wait states (LATENCY) must be correctly programmed in the

Flash memory access control register (FLASH_ACR)

according to the frequency of the Flash memory (HCLK4) clock.

RM0471 Rev 5 65/1202

116

Embedded Flash memory (FLASH) RM0471

Table 4 shows the correspondence between wait states and Flash clock frequency.

Table 4. Number of wait states vs, Flash memory clock (HCLK4) frequency

Wait states (WS) (LATENCY) HCLK4 (MHz)

0 WS (1 HCLK cycles)

1 WS (2 HCLK cycles)

2 WS (3 HCLK cycles)

3 WS (4 HCLK cycles)

≤ 18

≤ 36

≤ 54

≤ 64

After POR on reset, the HCLK4 clock frequency is 4 MHz and 0 wait state (WS) is configured in the FLASH_ACR register.

When woken-up from Standby, the HCLK4 clock frequency is 16 MHz and 0 wait state (WS) is configured in the FLASH_ACR register.

When changing the Flash memory clock frequency, the software sequences described below must be applied in order to tune the number of wait states needed to access the

Flash memory.

Increasing the CPU frequency

Program the new number of wait states to the LATENCY bits in the

Flash memory access control register (FLASH_ACR)

2. Check that the new number of wait states is taken into account to access the Flash

memory by reading back the LATENCY from the Flash memory access control register

(FLASH_ACR)

, and wait until the programmed new number is read.

3. Modify the System cock source by writing the SW bits in the RCC_CFGR register.

4. If needed, modify the CPU clock prescaler by writing the SHDHPRE bits in

RCC_EXTCFGR.

5. Optionally, check that the new System clock source or/and the new Flash memory clock prescaler value is/are taken into account by reading the clock source status

(SWS bits) in the RCC_CFGR register, or/and the AHB prescaler value (SHDHPREF bit), in the RCC_EXTCFGR register.

Decreasing the CPU frequency

Modify the System clock source by writing the SW bits in the RCC_CFGR register.

2. If needed, modify the Flash memory clock prescaler by writing the SHDHPRE bits in

RCC_EXTCFGR.

3. Check that the new System clock source or/and the new Flash memory clock prescaler value is/are taken into account by reading the clock source status (SWS bits) in the

RCC_CFGR register, or/and the AHB prescaler value (SHDHPREF bit), in the

RCC_EXTCFGR register, and wait until the programmed new system clock source or/and new Flash memory clock prescaler value is/are read.

4. Program the new number of wait states to the LATENCY bits in

Flash memory access control register (FLASH_ACR)

5. Optionally, check that the new number of wait states is used to access the Flash

memory by reading back the LATENCY from the Flash memory access control register

(FLASH_ACR)

66/1202 RM0471 Rev 5

RM0471 Embedded Flash memory (FLASH)

The proprietary Adaptive real-time (ART) memory accelerator is optimized for STM32 industry-standard Arm

Cortex

-M4 with FPU processors. It balances the inherent performance advantage of the Arm

Cortex

-M4 with FPU over Flash memory technologies, which normally require the processor to wait for the Flash memory at higher operating frequencies.

To release the processor full performance, the accelerator implements an instruction prefetch queue and branch cache that increases program execution speed from the 64-bit

Flash memory. Based on CoreMark

benchmark, the performance achieved thanks to the

ART Accelerator

™

is equivalent to 0 wait state program execution from Flash memory at a

CPU frequency up to 64 MHz.

Instruction prefetch

The CPU1 fetches the instruction over the ICode bus and the literal pool (constant/data) over the DCode bus. The prefetch block aims at increasing the efficiency of ICode bus accesses.

The CPU2 fetches the instruction and the literal pool (constant/data) over the S-bus. The prefetch block aims at increasing the efficiency of S-bus accesses.

Each Flash memory read operation provides 64 bits from either two instructions of 32 bits or four instructions of 16 bits according to the program launched. This 64-bits current instruction line is saved in a current buffer. So, in case of sequential code, at least two CPU cycles are needed to execute the previous read instruction line. Prefetch on the CPU1

ICode bus or CPU2 S-bus can be used to read the next sequential instruction line from the

Flash memory while the current instruction line is being requested by the CPU.

Prefetch is enabled by setting the PRFTEN bit in the

Flash memory access control register

(FLASH_ACR)

for the CPU1 or

Flash memory CPU2 access control register

(FLASH_C2ACR)

for the CPU2. This feature is useful if at least one wait state is needed to access the Flash memory.

Figure 3 shows the execution of sequential 16-bit instructions with and without prefetch

when three WS are needed to access the Flash memory.

RM0471 Rev 5 67/1202

116

Embedded Flash memory (FLASH)

WAIT

Figure 3. Sequential 16-bit instructions execution

WAIT

WITHOUT PREFETCH

8 ins 1 fetch ins 2 fetch ins 3 fetch ins 4 fetch ins 5 fetch ins 6 fetch ins 7 fetch ins 8 fetch

RM0471

Read ins 1, 2, 3, 4 Gives ins 1, 2, 3, 4 Read ins 5, 6, 7, 8 Gives ins 5, 6, 7, 8

68/1202

WAIT

WITH PREFETCH

Cortex-M4 pipeline

6 ins 1 fetch ins 2 fetch ins 3 fetch ins 4 fetch ins 5 fetch ins 6 fetch ins 7 fetch ins 8 fetch

Read ins 1, 2, 3, 4 Gives ins 1, 2, 3, 4 Gives ins 5, 6, 7, 8

AHB protocol

@: address requested

F: Fetch stage

D: Decode stage

E: Execute stage

Read ins 5, 6, 7, 8 Read ins 9, 10, ...

MS33467V1

When the code is not sequential (branch), the instruction may not be present in the currently used instruction line or in the prefetched instruction line. In this case (miss), the penalty in terms of number of cycles is at least equal to the number of wait states.

RM0471 Rev 5

RM0471

Note:

Embedded Flash memory (FLASH)

If a loop is present in the current buffer, no new access is performed.

CPU1 Instruction cache memory (I-Cache)

To limit the CPU1 time lost due to jumps, it is possible to retain 32 lines of 4*64 bits (1 Kbyte) in an instruction cache memory.This feature can be enabled for the CPU1 by setting the instruction cache enable (ICEN) bit in the

Flash memory access control register

(FLASH_ACR)

Once all the instruction cache memory lines have been filled, the LRU (least recently used) policy is used to determine the line to replace in the instruction memory cache. This feature is particularly useful in case of code containing loops.

The Instruction cache memory is enable after system reset.

CPU1 Data cache memory (D-Cache)

CPU1 literal pools are fetched from Flash memory through the DCode bus during the execution stage of the CPU pipeline. Each CPU1 DCode bus read access fetches 64 bits that are saved in a current buffer. The CPU pipeline is consequently stalled until the requested literal pool is provided. To limit the time lost due to literal pools, accesses through the AHB databus DCode have priority over accesses through the AHB instruction bus

ICode.

If some literal pools are frequently used, the CPU1 data cache memory can be enabled by

setting the data cache enable (DCEN) bit in the Flash memory access control register

(FLASH_ACR)

. This feature works like the instruction cache memory, but the retained data size is limited to 8 lines of 4*64 bits (256 bytes).

The Data cache memory is enabled after system reset.

The D-Cache is active only when data is requested by the CPU (not by DMAs).

Data in option bytes block are not cacheable.

CPU2 cache memory (S-bus)

To limit the CPU2 time lost due to jumps, it is possible to retain four lines of 1*64 bits (32 bytes) in an instruction cache memory.This feature can be enabled for the CPU2 by setting the instruction cache enable (ICEN) bit in the

Flash memory CPU2 access control register

(FLASH_C2ACR)

. Each time a miss occurs (requested data not present in the currently used instruction line, in the prefetched instruction line or in the instruction cache memory), the line read is copied into the instruction cache memory. If some data contained in the instruction cache memory are requested by the CPU, they are provided without inserting any delay. Once all the instruction cache memory lines have been filled, the LRU (least recently used) policy is used to determine the line to replace in the instruction memory cache. This feature is particularly useful in case of code containing loops.

The Instruction cache memory is enable after system reset.

CPU2 literal pools are fetched from Flash memory through the S-bus during the execution stage of the CPU pipeline. Each CPU2 S-bus read access fetches 64 bits that are saved in a current buffer. The CPU pipeline is consequently stalled until the requested literal pool is provided.

No Data cache is available on Cortex ® -M0+.

RM0471 Rev 5 69/1202

116

Embedded Flash memory (FLASH)

3.3.6

Note:

Flash memory program and erase operations

RM0471

The embedded Flash memory can be programmed using in-circuit or in-application programming.

The in-circuit programming (ICP) method is used to update the entire contents of the

Flash memory, using the JTAG, SWD protocol or the supported interfaces by the System boot loader, to load the user application for both the CPU1 and CPU2, into the microcontroller. ICP offers quick and efficient design iterations and eliminates unnecessary package handling or socketing of devices.

In contrast to the ICP method, in-application programming (IAP) can use any communication interface supported by the microcontroller (e.g. I/Os, UART, I

C, SPI) to download programming data into memory. IAP allows the user to re-program the Flash memory while the application is running. Nevertheless, part of the application has to have been previously programmed in the Flash memory using ICP.

The contents of the Flash memory are not guaranteed if a device reset occurs during a

Flash memory operation.

During a program/erase operation to the Flash memory, any attempt to read the Flash memory stalls the bus. The read operation proceeds correctly once the program/erase operation is completed.

In a multi-CPU system it is good practice to use semaphores to manage Flash memory program and erase operations, and prevent simultaneous operations by the CPUs.

Secure system Flash memory programming

The secure CPU2 application can only be programmed by in-application programming

(IAP) running on the secure CPU2 . Only the secure CPU2 is able to download programming data into secure part of the memory. Secure IAP allows the user to re-program the Flash memory while the application is running. Nevertheless, part of the application has to have been previously programmed in the Flash memory using ICP.

The in-circuit programming (ICP) System boot loader is able to communicate with the secure CPU2 IAP, to download programming data into secure memory.

Unlocking the Flash memory

After reset, write is not allowed in the

Flash memory control register (FLASH_CR) or

Flash memory CPU2 control register (FLASH_C2CR)

to protect the Flash memory against possible unwanted operations due, for example, to electric disturbances. The following sequence is used to unlock these registers:

Write KEY1 = 0x4567 0123 in the

Flash memory key register (FLASH_KEYR)

2. Write KEY2 = 0xCDEF 89AB in the

Flash memory key register (FLASH_KEYR) .

Any wrong sequence locks up the FLASH_CR registers until the next system reset. In the case of a wrong key sequence, a bus error is detected and a hard fault interrupt is generated.

The FLASH_CR registers can be locked again by software by setting the LOCK bit in one of these registers.

The FLASH_CR register cannot be written when the BSY bit in the

Flash memory status register (FLASH_SR)

or Flash memory CPU2 status register (FLASH_C2SR) is set. Any

70/1202 RM0471 Rev 5

RM0471 Embedded Flash memory (FLASH) attempt to write to these registers with the BSY bit set causes the AHB bus to stall until the

BSY bit is cleared.

3.3.7 Flash main memory erase sequences

The Flash memory erase operation can be performed at page level (page erase), or on the whole memory (mass erase). Mass erase does not affect the Information block (system

Flash, OTP and option bytes).

Flash memory page erase

The CPU1 is only able to page erase the non-secure part of the user Flash.

The secure CPU2 is able to page erase both the secure and non-secure parts of the user

Flash memory.

A page erase starts only when allowed by the PESD bit in the Flash memory status register

(FLASH_SR)

and in the

Flash memory CPU2 status register (FLASH_C2SR) .

When a page is protected by PCROP or WRP it is not erased.

Table 5. Page erase overview

Page PCROP WRP PCROP_RDP Comment WRPERR

CPU1 bus error

CPU2 bus error

Non secure

Yes

Page is erased

Page erase aborted (no page erase started)

Yes

No No

No x

Requested by CPU2, secure page is erased

Requested by CPU1, secure page erase is aborted (no secure page erase started)

N/A No

N/A

Secure

Yes

Page erase aborted (no page erase started)

Yes

(1)

Yes

1. WRPERR is generated only when PER is requested by CPU2 (Cortex-M0+). There is no WRPERR when PER is requested by CPU1.

To erase a page (4 Kbytes), follow the procedure below:

Check that no Flash memory operation is ongoing by checking the BSY bit in the Flash memory status register (FLASH_SR) or

Flash memory CPU2 status register

(FLASH_C2SR)

Check that Flash memory program and erase operations are allowed by checking the

PESD bit in the

Flash memory status register (FLASH_SR)

or Flash memory CPU2 status register (FLASH_C2SR) (these checks are recommended even if status may

RM0471 Rev 5 71/1202

116

Embedded Flash memory (FLASH) RM0471

Note: change due to Flash memory operation requests by the other CPU, to limit the risk of receiving a bus error when starting page erase).

2. Check and clear all error programming flags due to a previous programming. If not,

PGSERR is set.

3. Set the PER bit and select the page to erase (PNB) in the

Flash memory control register (FLASH_CR)

Flash memory CPU2 control register (FLASH_C2CR)

4. Set the STRT bit in the FLASH_xxCR register.

5. Wait for the BSY bit to be cleared in the FLASH_xxSR register.

The internal oscillator HSI16 (16 MHz) is enabled automatically when STRT bit is set, and disabled automatically when STRT bit is cleared, except if the HSI16 is previously enabled with HSION in RCC_CR register.

Flash memory mass erase

A Flash memory mass erase by the CPU1 is ignored and a bus error is generated.

When PCROP or WRP is enabled any Flash memory mass erase is aborted and no erase started.

PCROP WRP PCROP_RDP

Table 6. Mass erase overview

Comment WRPERR

CPU1 bus error

CPU2 bus error

Requested by secure CPU2,

Flash memory is mass erased

No No

Yes

Yes x

Yes

Yes x x

Requested by secure CPU2, mass erase aborted (no erase started)

Requested by CPU1, mass erase aborted (no erase started)

Yes

N/A

Yes

N/A

Note:

To perform a mass erase, follow the procedure below:

Check that no Flash memory operation is ongoing by checking the BSY bit in the Flash memory status register (FLASH_SR) or

Flash memory CPU2 status register

(FLASH_C2SR)

2. Check and clear all error programming flags due to a previous programming. If not,

PGSERR is set.

3. Set the MER bit in the

Flash memory control register (FLASH_CR) or

Flash memory

CPU2 control register (FLASH_C2CR) .

4. Set the STRT bit in the FLASH_xxCR register.

5. Wait for the BSY bit to be cleared in the FLASH_xxSR.

72/1202 RM0471 Rev 5

RM0471

3.3.8

Note:

Embedded Flash memory (FLASH)

Flash main memory programming sequences

The Flash memory is programmed 72 bits (a double word, 64 bits plus ECC, 8 bits) at a time.

Programming in a previously programmed double word is only allowed when programming an all 0 value. It is not allowed to program any other value in a previously programmed

double word, any attempt sets PROGERR flag in the Flash memory status register

(FLASH_SR)

Flash memory CPU2 status register (FLASH_C2SR)

, except when programming an already programmed double word with an all 0 value .

It is only possible to program a double word (2 x 32-bit data).

 Any attempt to write byte (8 bits) or half-word (16 bits) sets SIZERR flag in the

FLASH_xxSR register .

 Any attempt to write a double word that is not aligned with a double word address sets

PGAERR flag in the FLASH_xxSR register .

Only the secure CPU2 is able to download programming data into the secure part of the memory. A Flash memory programming by the CPU1 in the secure Flash memory area is ignored and a bus error is generated.

Standard programming

The Flash memory programming sequence in standard mode is as follows:

Check that no Flash main memory operation is ongoing by checking the BSY bit in the

Flash memory status register (FLASH_SR)

or Flash memory CPU2 status register

(FLASH_C2SR)

Check that Flash memory program and erase operations are allowed by checking the

PESD bit in the

Flash memory status register (FLASH_SR)

or Flash memory CPU2 status register (FLASH_C2SR) (these checks are recommended even if status may

change due to Flash memory operation requests by the other CPU, to limit the risk of receiving a bus error when starting programming).

2. Check and clear all error programming flags due to a previous programming. If not,

PGSERR is set.

3. Set the PG bit in the Flash memory control register (FLASH_CR) or

Flash memory

CPU2 control register (FLASH_C2CR) .

4. Perform the data write operation at the desired memory address, inside main memory block or OTP area. Only double word (64 bits) can be programmed.

a) Write a first word in an address aligned with double word b) Write the second word.

5. Wait until the BSY bit is cleared in the FLASH_xxSR register.

6. Check that EOP flag is set in the FLASH_xxSR register (meaning that the programming operation has succeed), and clear it by software.

7. Clear the PG bit in the FLASH_xxSR register if there no more programming request anymore.

When the Flash memory interface has received a good sequence (a double word), programming is automatically launched and BSY bit is set. The internal oscillator HSI16

RM0471 Rev 5 73/1202

116

Embedded Flash memory (FLASH)

Note:

RM0471

(16 MHz) is enabled automatically when PG bit is set, and disabled automatically when PG bit is cleared, except if the HSI16 is previously enabled with HSION in RCC_CR register.

If the user needs to program only one word, double word must be completed with the erase value 0xFFFF FFFF to launch automatically the programming.

ECC is calculated from the double word to program.

Fast programming

This mode allows to program a row, 64 double words (512 bytes) and to reduce the page programming time by eliminating the need for verifying the Flash memory locations before they are programmed and to avoid rising and falling time of high voltage for each double word. During fast programming, the Flash memory clock frequency (HCLK4) must be at least 8 MHz.

Only the main memory can be programmed in Fast programming mode.

Fast row programming must be performed by executing software from SRAM and disabling interrupts when not relocating the CPU interrupt vector table. A read access from the CPU requesting row programming causes a bus error. A read from any other source (the other

CPU or DMA) is stalled until the row programming finishes (standard double word programming does not cause a bus error to the requesting CPU, but stalls any read until standard programming finishes).

The Flash main memory programming sequence in standard mode is described below:

Perform a mass erase. If not, PGSERR is set.

2. Check that no Flash main memory operation is ongoing by checking the BSY bit in the

Flash memory status register (FLASH_SR)

or Flash memory CPU2 status register

(FLASH_C2SR)

Check that Flash memory program and erase operation is allowed by checking the

PESD bit in the

Flash memory status register (FLASH_SR)

or Flash memory CPU2 status register (FLASH_C2SR)

(these checks are recommended even if status may change due to Flash memory operation requests by the other CPU, to limit the risk of receiving a bus error when starting programming).

3. Check and clear all error programming flag due to a previous programming.

4. Set the FSTPG bit in

Flash memory control register (FLASH_CR)

or Flash memory

CPU2 control register (FLASH_C2CR) .

5. Write the 64 double words to program a row (512 bytes).

6. Wait until the BSY bit is cleared in the FLASH_xxSR register.

7. Check that EOP flag is set in the FLASH_xxSR register (meaning that the programming operation has succeed), and clear it by software.

8. Clear the FSTPG bit in the FLASH_xxSR register if there are no more programming requests anymore.

When attempting to write in Fast programming mode while a read operation is on going, the programming is aborted without any system notification (no error flag is set).

When the Flash memory interface has received the first double word, programming is automatically launched. The BSY bit is set when the high voltage is applied for the first double word, and it is cleared when the last double word has been programmed or in case of error. The internal oscillator HSI16 (16 MHz) is enabled automatically when FSTPG bit is

74/1202 RM0471 Rev 5

RM0471 Embedded Flash memory (FLASH) set, and disabled automatically when FSTPG bit is cleared, except if the HSI16 is previously enabled with HSION in RCC_CR register.

The 64 double word must be written successively. The high voltage is kept on the Flash memory for all the programming. Maximum time between two double words write requests is the time programming (around 20 µs). If a second double word arrives after this time programming, fast programming is interrupted and MISSERR is set.

High voltage must not exceed 8 ms for a full row between two erases. This is guaranteed by the sequence of 64 double words successively written with a clock system greater or equal to 8 MHz. An internal time-out counter counts 7 ms when Fast programming is set and stops the programming when time-out is over. In this case the FASTERR bit is set.

If an error occurs, high voltage is stopped and next double word to programmed is not programmed. Anyway, all previous double words have been properly programmed.

Programming errors signaled by flags

Several kind of errors can be detected. In case of error, the Flash memory operation

(programming or erasing) is aborted.

 PROGERR : Programming error

In standard programming: PROGERR is set if the word to write with values different from all 0 has not been previously erased, except if the value to program is all 0. If any other error (SIZERR, PAGERR, PGSERR, WRPERR) occurs the PROGRERR may not be set even if there is a word re-programming without erase error.

 SIZERR : Size programming error

In standard programming or in fast programming: only double word can be programmed, and only 32-bit data can be written. SIZERR is set if a byte or an half-word is written.

 PGAERR : Alignment programming error

PGAERR is set if one of the following conditions occurs:

– Alignment programming errors are individually checked per CPU. No checks are available for simultaneous multi-CPU programming. HSEM or other software mechanisms shall be used to prevent simultaneous multi CPU programming.

– In standard programming: the first word to be programmed is not aligned with a double word address, or the second word does not belong to the same double word address.

– In fast programming: the data to program does not belong to the same row than the previous programmed double words, or the address to program is not greater than the previous one.

 PGSERR : Programming sequence error

PGSERR is set if one of the following conditions occurs:

– In the standard programming sequence or the fast programming sequence: data is written when PG and FSTPG are cleared.

– In the standard programming sequence or the fast programming sequence: MER and PER are not cleared when PG or FSTPG is set.

– In the fast programming sequence: the Mass erase is not performed before setting the FSTPG bit.

– In the mass erase sequence: PG, FSTPG, and PER are not cleared when MER is set.

RM0471 Rev 5 75/1202

116

Embedded Flash memory (FLASH)

Note:

RM0471

– In the page erase sequence: PG, FSTPG and MER are not cleared when PER is set.

– PGSERR is set also if PROGERR, SIZERR, PGAERR, WRPERR, MISSERR,

FASTERR or PGSERR is set due to a previous programming error.

– In the fast programming sequence: if the row to be programmed is on a page different from the one previously erased. If a mass erase has been done it is allowed to program rows on higher order pages, but not on lower order.

 WRPERR : Write protection error

WRPERR is set if one of the following conditions occurs:

– Attempt to program or erase in a write protected area (WRP) or in a PCROP area.

– Attempt to perform a mass erase when one page or more is protected by WRP or

PCROP.

– The debug features are connected or the boot is executed from SRAM or from

System Flash when the read protection (RDP) is set to Level 1.

– Attempt to modify the option bytes when the read protection (RDP) is set to

Level 2, except when requested by the secure CPU2.

 MISSERR : Fast programming data miss error

In fast programming: all the data must be written successively. MISSERR is set if the previous data programmation is finished and the next data to program is not written yet.

 FASTERR : Fast programming error

In fast programming: FASTERR is set if one of the following conditions occurs:

– When FSTPG bit is set for more than 7 µs, which generates a time-out detection.

– When the row fast programming has been interrupted by a MISSERR, PGAERR,

WRPERR or SIZERR.

If an error occurs during a program or erase operation, one of the following error flags is set in the

Flash memory status register (FLASH_SR)

or Flash memory CPU2 status register

(FLASH_C2SR) :

 PROGERR, SIZERR, PGAERR, PGSERR, MISSERR (program error flags)

 WRPERR (protection error flag)

In this case, if the error interrupt enable bit ERRIE is set in the

Flash memory control register (FLASH_CR)

or in the

Flash memory CPU2 control register (FLASH_C2CR) , an

interrupt is generated and the operation error flag OPERR is set in the FLASH_xxSR register.

If several successive errors are detected (for example, in case of DMA transfer to the Flash memory), the error flags cannot be cleared until the end of the successive write request.

76/1202 RM0471 Rev 5

RM0471

Note:

Embedded Flash memory (FLASH)

Programming errors causing a bus error

Some error conditions, listed below, do not generate an error flag but a bus error instead.

 AHB write to any page when RDP level 1 and boot is performed from system Flash memory or SRAM1

 AHB write when Flash memory is powered down

 Read or write from Flash memory through the debugger

 Reading from Flash memory when fast row programming is ongoing, from the source which requested the fast row programming.

 Requesting a new programming request, when the previous one has not finished.

 FLASH_CR register write between the two accesses of a double word programming.

 FLASH_CR register write when PESDx is active (set).

 Writing a wrong key in FLASH_KEYR or FLASH_OPTKEYR register

 Any subsequent write to FLASH_KEYR or FLASH_OPTKEYR after unlocking the respective feature

PGSERR and PGAERR in a page-based row programming

When performing a fast programming Table 7 describes how PGSERR and PGAERR are

handled.

Last page / row page [x] / row [y] page [x] / row [y] page [x] / row [y]

Table 7. Errors in page-based row programming

Current page / row MER active PER active page [x] / row [y-n] PGAERR PGAERR page [x-n] / row [any] PGAERR and PGSERR PGAERR and PGSERR page [x+n] / row [any] No error PGAERR

When after a system reset neither MER nor PER is performed, any programming attempt causes PGAERR and PGSERR errors.

Programming and caches

If a Flash memory write access impacts data in the data cache, the Flash memory write access modifies the data in the memory and the data in the cache.

If an erase operation in Flash memory also concerns data in the data or instruction cache, the user has to ensure that these data are rewritten before they are accessed during code execution. Upon an erase operation the cache content is invalidated.

The I/D cache must be flushed only when it is disabled (I/DCEN = 0).

RM0471 Rev 5 77/1202

116

Embedded Flash memory (FLASH) RM0471

3.4 FLASH option bytes

3.4.1 Option bytes description

The option bytes are configured by the end user depending on the application requirements.

As a configuration example, the watchdog may be selected in hardware or software mode

(refer to

Section 3.4.2: Option bytes programming

A double word is split up in option bytes as indicated in

Table 8

63-56 55-48

Table 8. Option bytes format

47-40 39-32

Complemented option byte 3

Complemented option byte 2

Complemented option byte 1

Complemented option byte 0

31-24

Option byte 3

23-16

Option byte 2

15 -8

Option byte 1

7-0

Option byte 0

Address

(1)

The organization of these bytes in the information block is shown in

Table 9 . The option bytes can be read from the memory locations listed in Table 9 or from the Option byte

registers:



Flash memory option register (FLASH_OPTR)



Flash memory PCROP zone A start address register (FLASH_PCROP1ASR)



Flash memory PCROP zone A end address register (FLASH_PCROP1AER)



Flash memory PCROP zone B start address register (FLASH_PCROP1BSR)



Flash memory PCROP zone B end address register (FLASH_PCROP1BER)



Flash memory WRP area A address register (FLASH_WRP1AR)



Flash memory WRP area B address register (FLASH_WRP1BR)



Flash memory IPCC mailbox data buffer address register (FLASH_IPCCBR)



Secure Flash memory start address register (FLASH_SFR)



Flash memory secure SRAM2 start address and CPU2 reset vector register

(FLASH_SRRVR)

Table 9. Option bytes organization

1FFF8000

1FFF8008

1FFF8010

1FFF8018

1FFF8020

Unused

WRP1A_END

WRP1B_END

Unused

RDP

PCROP1A_STRT

PCROP1A_END

WRP1A_STRT

WRP1B_STRT

78/1202 RM0471 Rev 5

RM0471 Embedded Flash memory (FLASH)

Table 9. Option bytes organization (continued)

Address (1)

1FFF8028

1FFF8030

1FFF8038 to

1FFF8060

1FFF8068

1FFF8070

Unused

PCROP1B_STRT

PCROP1B_END

Unused

IPCCDBA

SFSA

1FFF8078 SNBRSA SBRSA SBRV

1FFF8FF8 OPVAL

1. The upper 32-bits of the double-word address contain the inverted data from the lower 32 bits.

User and read protection option bytes

Flash memory address: 0x1FFF 8000

ST production value: 0x3FFF F1AA

31 30

AGC_TRIM[2:0]

29 r

Res.

14 nRST

_SHDW r r

13 nRST

_STDBY r

Res.

12 nRST

_STOP r

27 n

BOOT0 r

26 25 24 nSW

BOOT0 r

SRAM2

_RST r

SRAM2

_PE r

10 9 8

23 n

BOOT1 r

7 r

BOR_LEV[2:0] r r

ESE r r

Res.

6 r

Res.

WWDG

_SW r

18 17

IWGD

_STDBY r

IWDG

_STOP r

2 1

IWDG

_SW r

RDP[7:0] r r r r r r

Bits 31:29 AGC_TRIM : Automatic gain control trimming.

Default value 0b001.

Bit 28 Not used

Bit 27 nBOOT0: nBOOT0 option bit

0: nBOOT0 = 0

1: nBOOT0 = 1

Bit 26 nSWBOOT0: Software BOOT0

0: BOOT0 taken from the option bit nBOOT0

1: BOOT0 taken from PH3/BOOT0 pin

Bit 25 SRAM2_RST: SRAM2 and PKA RAM erase when system reset

0: SRAM2 and PKA RAM erased when a system reset occurs

1: SRAM2 and non-secure PKA RAM not erased when a system reset occurs

Bit 24 SRAM2_PE: SRAM2 parity check enable

0: SRAM2 parity check enable

1: SRAM2 parity check disable

RM0471 Rev 5 79/1202

116

Embedded Flash memory (FLASH) RM0471

Bit 23 nBOOT1: Boot configuration

Together with the BOOT0 pin or option bit nBOOT0 (depending on nSWBOOT0 option bit configuration), this bit selects boot mode from the Flash main memory, SRAM1 or the

System memory. Refer to Section 2.3: Boot configuration .

Bits 22:20 Not used

Bit 19 WWDG_SW: Window watchdog selection

0: Hardware window watchdog

1: Software window watchdog

Bit 18 IWDG_STDBY: Independent watchdog counter freeze in Standby mode

0: Independent watchdog counter is frozen in Standby mode

1: Independent watchdog counter is running in Standby mode

Bit 17 IWDG_STOP: Independent watchdog counter freeze in Stop mode

0: Independent watchdog counter is frozen in Stop mode

1: Independent watchdog counter is running in Stop mode

Bit 16 IDWG_SW: Independent watchdog selection

0: Hardware independent watchdog

1: Software independent watchdog

Bit 15 Not used

Bit 14 nRST_SHDW

0: Reset generated when entering the Shutdown mode

1: No reset generated when entering the Shutdown mode

Bit 13 nRST_STDBY

0: Reset generated when entering the Standby mode

1: No reset generate when entering the Standby mode

Bit 12 nRST_STOP

0: Reset generated when entering the Stop mode

1: No reset generated when entering the Stop mode

Bits 11:9 BOR_LEV: BOR reset Level

These bits contain the VDD supply level threshold that activates/releases the reset.

000: BOR Level 0. Reset level threshold is ~ 1.7 V

001: BOR Level 1. Reset level threshold is ~ 2.0 V

010: BOR Level 2. Reset level threshold is ~ 2.2 V

011: BOR Level 3. Reset level threshold is ~ 2.5 V

100: BOR Level 4. Reset level threshold is ~ 2.8 V

Bit 8 ESE: System security enabled flag.

0: Security disabled

1: Security enabled

Bits 7:0 RDP: Read protection level

0xAA: Level 0, read protection not active

0xCC: Level 2, chip read protection active

Others: Level 1, memories read protection active

PCROP1A start address option bytes

Flash memory address: 0x1FFF 8008

ST production value: 0xFFFF FFFF

80/1202 RM0471 Rev 5

RM0471 Embedded Flash memory (FLASH)

Res.

8 r

7 r

6 r

5 4 3

PCROP1A_STRT[8:0] r r r

2 r

1 r

0 r

Bits 31:9 Not used

Bits 8:0 PCROP1A_STRT: PCROP1A area start offset

PCROP1A_STRT contains the first 2 Kbytes page of the PCROP1A area. Note that bit 8 is reserved on STM32WB30CE devices.

PCROP1A end address option bytes

Flash memory address: 0x1FFF 8010

ST production value: 0x0000 0000

31 30

PCROP_RDP Res.

Res.

8 7 r r

Res.

6 r

5 r

PCROP1A_END[8:0] r

3 r

2 r

1 r

Res.

0 r

Res.

Bit 31 PCROP_RDP: PCROP area preserved when RDP level is decreased

This bit is set only. It is reset after a full mass erase due to a change of RDP from Level 1 to

Level 0.

0: PCROP area is not erased when the RDP level is decreased from Level 1 to Level 0.

1: PCROP area is erased when the RDP level is decreased from Level 1 to Level 0 (full mass erase).

Bits 30:9 Not used

Bits 8:0 PCROP1A_END: PCROP1A area end offset

PCROP1A_END contains the last 2 Kbytes page of the PCROP1A area. Note that bit 8 is reserved on STM32WB30CE devices.

WRP Area A address option bytes

Flash memory address: 0x1FFF 8018

ST production value: 0x0000 00FF

Res.

23 22 17 16

Res.

7 r r

6 r r

21 r

20 19

WRP1A_END[7:0] r

4 r

WRP1A_STRT[7:0] r r

18 r r

2 r

1 r r

0 r

RM0471 Rev 5 81/1202

116

Embedded Flash memory (FLASH) RM0471

Res.

Bits 31:24 Not used

Bits 23:16 WRP1A_END: WRP area “A” end offset

WRPA1_END contains the last 4 Kbytes page of the WRP area “A”. Note that bit 23 is reserved on STM32WB30CE devices.

Bits 15:8 Not used

Bits 7:0 WRP1A_STRT: WRP area “A” start offset

WRPA1_STRT contains the first 4 Kbytes page of the WRP area “A”. Note that bit 7 is reserved on STM32WB30CE devices.

WRP Area B address option bytes

Flash memory address: 0x1FFF 8020

ST production value: 0x0000 00FF

Res.

23 r

22 r

6 r

21 r

20 19

WRP1B_END[7:0] r r

4 3

WRP1B_STRT[7:0] r r

18 r r

17 r

1 r r r

Bits 31:24 Not used

Bits 23:16 WRP1B_END: WRP area “B” end offset

WRPB1_END contains the last 4 Kbytes page of the WRP area “B”. Note that bit 23 is reserved on STM32WB30CE devices.

Bits 15:8 Not used

Bits 7:0 WRP1B_STRT: WRP area “B” start offset

WRPB1_STRT contains the first 4 Kbytes page of the WRP area “B”. Note that bit 7 is reserved on STM32WB30CE devices.

16 r

0 r

PCROP1B start address option bytes

Flash memory address: 0x1FFF 8028

ST production value: 0xFFFF FFFF

Res.

8 r

7 r

6 r

5 4 3

PCROP1B_STRT[8:0] r r r

2 r

1 r

0 r

Bits 31:9 Not used

Bits 8:0 PCROP1B_STRT: PCROP1B area start offset

PCROP1B_STRT contains the first 2 Kbytes page of the PCROP1B area. Note that bit 8 is reserved on STM32WB30CE devices.

82/1202 RM0471 Rev 5

RM0471 Embedded Flash memory (FLASH)

Res.

PCROP1B end address option bytes

Flash memory address: 0x1FFF 8030

ST production value: 0x0000 0000

Res.

8 r

7 r

6 r

5 4 3

PCROP1B_END[8:0] r r r

2 r

1 r

0 r

Bits 31:9 Not used

Bits 8:0 PCROP1B_END: PCROP1B area end offset

PCROP1B_END contains the last 2 Kbytes page of the PCROP1B area. Note that bit 8 is reserved on STM32WB30CE devices.

IPCC mailbox data buffer address option bytes

Flash memory address: 0x1FFF 8068

ST production value: 0x0000 0000

Res.

13 r

12 r

11 r

10 r

9 r

8 r

7 6

IPCCDBA[13:0] r r

5 r

4 r

3 r

2 r

1 r

0 r

Res.

Bits 31:14 Not used

Bits 13:0 IPCCDBA: IPCC mailbox data buffer base address offset

IPCCDBA contains the first double-word offset of the IPCC mailbox data buffer area in

SRAM2.

Secure Flash memory start address option bytes

Flash memory address: 0x1FFF 8070

ST production value: 0xFFFF FEXX

Res.

DDS r

Res.

FSD r

7 r

6 r

5 r

4 3

SFSA[7:0] r r

2 r

1 r

0 r

RM0471 Rev 5 83/1202

116

Embedded Flash memory (FLASH) RM0471

30 31

C2OPT .

NBRSD r

15 r

14 r

Bits 31:13 Not used

Bits 12 DDS: Disable CPU2 debug access

0: CPU2 debug access enabled.

1: CPU2 debug access disabled.

Bits 11:9 Not used

Bit 8 FSD: Flash security disable

FSD = 1: System and Flash non-secure

FSD = 0: System and Flash secure. SFSA[7:0] contains the start address of the first

4 Kbytes page of the secure Flash area.

Bits 7:0 SFSA: Secure Flash start address

System and Flash secure. SFSA[7:0] contains the start address of the first 4 Kbytes page of the secure Flash area.

Secure SRAM2 start address and CPU2 reset vector option bytes

Flash memory address: 0x1FFF 8078

ST production value: 0xXXXX XXXX

29 r

13 r

28 27

SNBRSA[4:0]

26 r

12 r

11 r

10 r r r

25 r

9 r

Res.

BRSD r

7 8

SBRV[15:0] r r

22 r

6 r r

21 20

SBRSA[4:0]

19 r

4 r

3 r r r

18 r

2 r r

17 16

SBRV[17:16] r

0 r r

Bit 31 C2OPT: CPU2 boot reset vector memory selection.

0: SBRV offset addresses SRAM1 or SRAM2, from start address 0x2000 0000 (SBRV value must be kept within the SRAM area).

1: SBRV offset addresses Flash memory, from start address 0x0800 0000.

Bit 30 NBRSD: Non-backup SRAM2b security disable

NBRSD = 1: SRAM2b is non-secure

NBRSD = 0: SRAM2b is secure. SNBRSA[4:0] contains the start address of the first

1 Kbyte page of the secure non-backup SRAM2b area.

Bits 29:25 SNBRSA: Secure non-backup SRAM2b start address

NBRSD = 0: SRAM2b is secure. SNBRSA[4:0] contains the start address of the first

1 Kbyte page of the secure non-backup SRAM2b area.

Bit 24 Not used

Bits 23 BRSD: Backup SRAM2a security disable

BRSD = 1: SRAM2a is non-secure

BRSD = 0: SRAM2a is secure. SBRSA[4:0] contains the start address of the first 1 Kbyte page of the secure backup SRAM2a area.

Bits 22:18 SBRSA: Secure backup SRAM2a start address

BRSD = 0: SRAM2a is secure. SBRSA[4:0] contains the start address of the first 1 Kbyte page of the secure backup SRAM2a area.

Bits 17:0 SBRV: CPU2 boot reset vector

Contains the word aligned CPU2 boot reset start address offset within the selected memory area by C2OPT.

84/1202 RM0471 Rev 5

RM0471

3.4.2

Note:

Embedded Flash memory (FLASH)

Option bytes programming

After reset, the options related bits in the Flash memory control register (FLASH_CR)

and

Flash memory CPU2 control register (FLASH_C2CR)

are write-protected. To run any operation on the option bytes page, the option lock bit OPTLOCK in the

Flash memory control register (FLASH_CR) must be cleared. The following sequence is used to unlock

this register:

Unlock the FLASH_CR with the LOCK clearing sequence (refer to Unlocking the Flash memory )

2. Write OPTKEY1= 0x08192A3B in the

Flash memory option key register

(FLASH_OPTKEYR)

3. Write OPTKEY2 = 0x4C5D6E7F in the Flash memory option key register

(FLASH_OPTKEYR)

Any wrong sequence locks up the Flash memory option registers until the next system reset. In the case of a wrong key sequence, a bus error is detected and a hard fault interrupt is generated.

The User options can be protected against unwanted erase/program operations by setting the OPTLOCK bit by software.

If LOCK is set by software, OPTLOCK is automatically set as well.

In a multi-CPU system it is good practice to use semaphores to manage option programming, and prevent simultaneous option programming by the CPUs.

Modifying User options

The option bytes are programmed differently from a main memory user address.

To modify the value of User options follow the procedure below:

Clear OPTLOCK option lock bit with the clearing sequence described above

2. Write the desired options value in the options registers.

3. Check that no Flash memory operation is on going by checking the BSY bit in the

Flash memory status register (FLASH_SR) or

Flash memory CPU2 status register

(FLASH_C2SR)

Check that Flash program and erase operation is allowed by checking the PESD bit in the

Flash memory status register (FLASH_SR)

or Flash memory CPU2 status register

(FLASH_C2SR)

(these checks are recommended even if status may change due to

Flash operation requests by the other CPU, to limit the risk of receiving a bus error when modifying User options).

4. Set the Options start bit OPTSTRT in the Flash memory control register (FLASH_CR) .

5. Wait for the BSY bit to be cleared.

Any modification of the value of one option is automatically performed by erasing User option bytes pages first, and then programming all the option bytes with the values contained in the Flash memory option registers.

Secure User options

The secure option bytes Secure Flash memory start address register (FLASH_SFR) and

Flash memory secure SRAM2 start address and CPU2 reset vector register

(FLASH_SRRVR) can only be written by the secure CPU2.

RM0471 Rev 5 85/1202

116

Embedded Flash memory (FLASH) RM0471

Option byte loading

After the BSY bit is cleared, all new options are updated into the Flash memory, but not applied to the system. A read from the option registers returns the last loaded option byte values, the new options have effect on the system only after they are loaded.

Option bytes loading is performed in two cases:

– when OBL_LAUNCH bit is set in the

Flash memory control register (FLASH_CR)

– after a power reset (BOR reset or exit from Standby/Shutdown modes)

Option byte loader performs a read of the options block and stores the data into internal option registers. These internal registers configure the system and can be read by software.

Setting OBL_LAUNCH generates a reset so the option byte loading is performed under system reset.

Each option bit has also its complement in the same double word. During option loading, a verification of the option bit and its complement allows to check the loading has correctly taken place.

During option byte loading, the options are read by double word. ECC on option words is not taken into account during OBL, but only during direct SW read of option area.

If the word and its complement are matching, the option word/byte is copied into the option register.

If the comparison between the word and its complement fails, a status bit OPTVERR is set.

Mismatch values are forced into the option registers:

– for USR OPT option, the value of mismatch is all options at ‘1’, except for

BOR_LEV that is “000” (lowest threshold)

– for WRP option, the value of mismatch is the default value “No protection”

– for RDP option, the value of mismatch is the default value “Level 1”

– for PCROP, the value of mismatch is “all memory protected”

– for FSD and SFSA option, the value of mismatch is “all memories (Flash, SRAM2a and SRAM2b) secured”

– for BRSD, SBRSA, NBRSD and SNBRASA options, the value of mismatch is

“SRAM2 memory part secured”

– for DDS option, the value of mismatch is “CPU2 debug disabled”

– for C2OPT and SBRV options, the value of mismatch is “CPU2 boot from start address of last Flash page (safe boot)”

– for OPTVAL option, the value of mismatch is “not valid”.

If the OPTVAL option indicates “not valid” all memories (Flash, SRAM2a and SRAM2b) are secure.

OPTVERR

OPTNV

Table 10. Option loading control

Description

Options correctly loaded and OPTVAL is “valid”.

– Security applied according to options.

Does not occur

86/1202 RM0471 Rev 5

RM0471 Embedded Flash memory (FLASH)

OPTVERR

OPTNV

Table 10. Option loading control (continued)

Description

OPTVAL option correctly loaded as “valid”, but some or all other option and engineering bits corrupted, mismatch values loaded.

– When secure option is loaded correctly, security is applied according to the loaded secure option values.

– When secure option is corrupted, security is applied on the full memory as indicated by the loaded mismatch value.

Some or all option and engineering bits corrupted, mismatch values loaded. OPTVAL correctly loaded as “not valid”. Security applied on full memories irrespective of the loaded secure option values.

On system reset rising, internal option registers are copied into option registers that can be read and written by software:

 FLASH_OPTR

 FLASH_PCROPxySR (x = 1 and y = A or B)

 FLASH_PCROPxyER (x = 1 and y = A or B)

 FLASH_WRPxyR (x = 1 and y = A or B)

 FLASH_IPCCDBA

 FLASH_SFR

 FLASH_SRRVA

These registers are also used to modify options. If these registers are not modified by user, they reflect the options states of the system. See Modifying User options for more details.

Address

0x1FFF 7580

0x1FFF 7584

A 64-bit unique device identification (UID64) is stored in the Flash memory, and can be accessed by the CPUs.

Table 11. UID64 organization

Unique device number

ST company ID Device ID

The UID64 is programed at device production, and provides a unique code for each device

 the 24-bit ST company ID returns 0x00 80 E1

 the 8-bit device ID returns 0x26 for STM32WB50CG revision Y and STM32WB30CE revision A, 0x27 for STM32WB50CG/STM32WB30CE revision B, as indicated in

DBGMCU_IDCODE

 the 32-bit unique device number is a sequential number, different for each individual device.

The 64-bit UID64 may be used by firmware to derive BLE 48-bit device address EUI-48 or

802.15.4 64-bit device address EUI-64.

RM0471 Rev 5 87/1202

116

Embedded Flash memory (FLASH)

3.6 Flash memory protection

RM0471

The Flash main memory can be protected against external accesses with the Read protection (RDP). The pages can also be protected against unwanted write (WRP) due to loss of program counter context. The write-protection WRP granularity is 4 Kbytes. Apart from the RDP and WRP, Flash memory can also be protected against read and write from third parties (PCROP). The PCROP granularity is 2 Kbyte s .

Part of the Flash main memory can be secured. It grants exclusive access to this part of the memory to the CPU2.

Note:

The read protection is activated by setting the RDP option byte and then, by applying a system reset to reload the new RDP option byte. The read protection protects the Flash main memory, the option bytes, the backup registers (RTC_BKPxR in the RTC) and the

SRAM2.

If the read protection is set while the debugger is still connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset.

There are three levels of read protection from no protection (Level 0) to maximum protection or no debug (Level 2).

The Flash memory is protected when the RDP option byte and its complement contain the pair of values shown in

Table 12 .

Table 12. Flash memory read protection status

RDP byte value RDP complement value Read protection level

Level 0 0xAA

Any value except 0xAA or 0xCC

0xCC

0x55

Any value (not necessarily complementary), except 0x55 and 0x33

0x33

Level 1 (default)

Level 2

The System memory area is read accessible whatever the protection level. It is never accessible for program/erase operation.

Level 0: No protection

Read, program and erase operations into the Flash main memory area are possible. The option bytes, the SRAM2 and the backup registers are also accessible by all operations.

88/1202 RM0471 Rev 5

RM0471 Embedded Flash memory (FLASH)

Level 1: Read protection

This is the default protection level when RDP option byte is erased. It is defined as well when RDP value is at any value different from 0xAA and 0xCC, or even if the complement is not correct.

 User mode: Code executing in user mode ( Boot Flash ) can access Flash main memory, option bytes, SRAM2 and backup registers with all operations.

 Debug, boot RAM and boot loader modes: In debug mode or when code is running from boot RAM or boot loader, the Flash main memory, the backup registers

(RTC_BKPxR in the RTC) and the SRAM2 are totally inaccessible. In these modes, a read or write access to the Flash memory generates a bus error and a hard fault interrupt.

Caution: In case the Level 1 is configured and no PCROP areas are defined, it is mandatory to set

PCROP_RDP bit to 1 (full mass erase when the RDP level is decreased from Level 1 to

Level 0). In case the Level 1 is configured and a PCROP area is defined, if user code needs to be protected by RDP but not by PCROP, it must not be placed in a page containing a

PCROP area.

Note:

Level 2: No debug

In this level, the protection Level 1 is guaranteed. In addition, the CPU1 and CPU2 debug port, the boot from RAM (boot RAM mode) and the boot from System memory (boot loader mode) are no more available. In user execution mode (boot FLASH mode), all operations are allowed on the Flash Main memory. On the contrary, only read and secure write operations can be performed on the option bytes. Option bytes, can only be programmed and erased by a secure CPU2.

The Level 2 cannot be removed from the non-secure application side: it is an irreversible operation. When attempting to modify the options bytes, the protection error flag WRPERR is set in the FLASH_xxxSR register and an interrupt can be generated.

The debug feature is also disabled under reset.

STMicroelectronics is not able to perform analysis on defective parts on which the Level 2 protection has been set.

Changing the Read protection level

It is easy to move from Level 0 to Level 1 by changing the value of the RDP byte to any value (except 0xCC). By programming the 0xCC value in the RDP byte, it is possible to go to level 2 either directly from Level 0 or from Level 1. Once in Level 2 it is no more possible to modify the Read protection level.

When the RDP is reprogrammed to the value 0xAA to move from Level 1 to Level 0, a mass

erase of the Flash main memory is performed if PCROP_RDP is set in the Flash memory

PCROP zone A end address register (FLASH_PCROP1AER) . The backup registers

(RTC_BKPxR in the RTC), the SRAM2 and the PKA SRAM are also erased. The User options (except PCROP protection) are set to their previous values copied from

FLASH_OPTR, FLASH_WRPxyR (x = 1 and y = A or B). PCROP is disabled. The OTP area is not affected by mass erase and remains unchanged.

If the bit PCROP_RDP is cleared in the FLASH_PCROP1AER, the full mass erase is replaced by a partial mass erase that is successive page erases, except for the pages protected by PCROP. This is done in order to keep the PCROP code. Only when the Flash

RM0471 Rev 5 89/1202

116

Embedded Flash memory (FLASH) RM0471

SFSA

Partial

Complete

Flash memory memory is erased, options are re-programmed with their previous values. This is also true for FLASH_PCROPxySR and FLASH_PCROPxyER registers (x = 1 and y = A or B).

A requested mass erase performs a partial mass erase (a sequence of page erases), except for the pages protected by CPU2 security (SFSA). This is done to keep the CPU2 secure code.

Table 13. RDP regression from Level 1 to Level 0 and memory erase

PCROP PCROP_RDP Comment

None x

Flash memory multiple page erase of all non-secure pages, SRAM2 and

PKA RAM and backup registers erase. (secure Flash pages conserved).

Partial

Complete non-secure

Flash memory multiple page erase of all non-PCROP pages and non-secure pages, SRAM2 and PKA RAM and backup registers erase

(PCROP Flash memory pages and secure Flash memory pages conserved).

Flash memory, SRAM2 and PKA RAM and backup registers are conserved.

x x

Flash memory, SRAM2 and PKA RAM and backup registers are conserved.

Note: Partial mass erase is performed only when Level 1 is active and Level 0 requested. When the protection level is increased (0 → 1, 1 → 2, 0 → 2) there is no mass erase.

To validate the protection level change, the option bytes must be reloaded through the

OBL_LAUNCH bit in Flash memory control register.

90/1202 RM0471 Rev 5

RM0471 Embedded Flash memory (FLASH)

Figure 4. Changing the Read protection (RDP) level

RDP ≠ 0xAA and RDP ≠ 0xCC

Other options modified

Write options including

RDP = 0xCC

Level 2

RDP = 0xCC

Level 1

RDP ≠ 0xAA

RDP ≠ 0xCC default

Write options including

RDP ≠ 0xCC and RDP ≠ 0xAA

Write options including

RDP = 0xAA

Write options including

RDP = 0xCC

Level 0

RDP = 0xAA

Options write (RDP level increase) includes:

- Options page erase

- New options program

Options write (RDP level decrease) includes

- Full Mass erase or Partial Mass erase to not

erase PCROP pages if PCROP_RDP is cleared

- Backup registers and CCM SRAM erase

- Options page erase

- New options program

RDP = 0xAA

Other option(s) modified

Options write (RDP level identical) includes

- Options page erase

- New options program

MS33468V1

Area

Flash main memory

System memory

(2)

Table 14. Access status vs. protection level and execution modes

Protection level

User execution (BootFromFlash memory)

Debug / BootFromRam /

BootFromLoader

Read

Yes

Write

Yes

(3)

Erase

Yes

Read

N/A

(1)

Yes

N/A

(1)

Yes

Write

N/A

(1)

Erase

N/A

(4)

(1)

No No

N/A

(1)

N/A

(1)

Yes

(3)

Yes

Option bytes

Backup registers

SRAM2

Yes

CPU1 and CPU2 none secure - No

CPU2 secure - Yes CPU2 secure - Yes

Yes N/A

Yes

N/A

(1)

N/A

(1)

N/A

(1)

N/A

(1)

N/A

(1)

N/A

(1)

N/A

(1)

(4)

N/A

(1)

(5)

N/A

(1)

1. When the protection Level 2 is active, the Debug port, the boot from RAM and the boot from system memory are disabled.

2. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.

RM0471 Rev 5 91/1202

116

Embedded Flash memory (FLASH) RM0471

3. The Flash non secure main memory is erased when the RDP option byte is programmed with all level of protections disabled (0xAA). The Flash secure main memory is also erased when the SFSA option byte is programmed to be non-secure and at the same time the RDP option byte is programmed with all level protections disabled (0xAA).

4. The backup registers are erased when RDP changes from Level 1 to Level 0.

5. The SRAM2 is erased when RDP changes from Level 1 to Level 0.

3.6.2 Proprietary code readout protection (PCROP)

Two parts of the Flash memory can be protected against read and write from third parties.

The protected area is execute-only: it can only be reached by the STM32 CPUs, with an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. The PCROP areas have a 2 Kbytes granularity. An additional option bit (PCROP_RDP) makes it possible to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0 (refer to Changing the Read protection level ).

Each PCROP area is defined by a start page offset and an end page offset into the Flash

memory. These offsets are defined in the PCROP address registers Flash memory PCROP zone A start address register (FLASH_PCROP1ASR) ,

Flash memory PCROP zone A end address register (FLASH_PCROP1AER) ,

Flash memory PCROP zone B start address register (FLASH_PCROP1BSR)

and

Flash memory PCROP zone B end address register

(FLASH_PCROP1BER)

A PCROP area is defined from the address Flash memory Base address +

[PCROPxy_STRT x 0x800] (included) to the address: Flash memory Base address +

[(PCROPxy_END+1) x 0x800] (excluded). The minimum PCROP area size is two PCROP pages (4 Kbytes) PCROPxy_END = PCROPxy_STRT + 1 .

When PCROPxy_END = PCROPxy_STRT the full Flash memory is PCROP protected.

For example, to protect by PCROP from the address 0x0806 2F80 (included) to the address

0x0807 0004 (included):

 if boot in Flash memory is selected, one of the FLASH_PCROPxySR and

FLASH_PCROPxyER registers (x = 1 and y = A or B) must be programmed with:

– PCROPxy_STRT = 0xC5 (PCROP area first address 0x0806 2800)

– PCROPxy_END = 0xE0 (PCROP area last address 0x0807 07FF)

Any data read access performed through a PCROP protected area triggers the RDERR flag error.

Any PCROP protected address is also write protected and any write access to one of these addresses triggers WRPERR.

Any PCROP area is also erase protected. Consequently, any erase to a page in this zone is impossible (including the page containing the start address and the end address of this zone). Moreover, a software mass erase cannot be performed if one zone is PCROP protected.

In the previous example, due to erase by page, all pages from page 0xC5 to 0xE0 are protected in case of page erase, all addresses from 0x0806 2800 to 0x0807 07FF cannot be erased.

Deactivation of PCROP can only occur when the RDP is changing from Level 1 to Level 0. If the User options modification tries to clear PCROP or to decrease the PCROP areas, the

92/1202 RM0471 Rev 5

RM0471 Embedded Flash memory (FLASH) options programming is launched but PCROP areas stays unchanged. On the contrary, it is possible to increase the PCROP areas.

When option bit PCROP_RDP is cleared, and when the RDP is changing from Level 1 to

Level 0, Full mass erase is replaced by Partial mass erase to preserve the PCROP area

(refer to Changing the Read protection level ). In this case, PCROPxy_STRT and

PCROPxy_END (x = 1 and y = A or B) are not erased.

Table 15: PCROP protection

PCROP registers values (x = 1 and y = A or B) PCROP protection area

PCROPxy_STRT = PCROPxy_END

PCROPxy_STRT > PCROPxy_END

PCROPxy_STRT < PCROPxy_END

The full Flash memory is PCROP protected

No PCROPxy, unprotected

Pages from PCROPxy_STRT to PCROPxy_END are protected

Note:

3.6.3

It is recommended to align PCROP areas with page granularity when using PCROP_RDP, or to leave free the rest of the page where PCROP zones start or end.

Write protection (WRP)

The user area in Flash memory can be protected against unwanted write operations. Two write-protected (WRP) areas can be defined, with page (4 Kbytes) granularity. Each area is defined by a start page offset and an end page offset related to the physical Flash memory base address. These offsets are defined in the WRP address registers

Flash memory WRP area A address register (FLASH_WRP1AR) and

Flash memory WRP area B address register (FLASH_WRP1BR) .

The WRP “y” area (y = A, B) is defined from the address Flash memory Base address +

[WRP1y_STRT x 0x1000] (included) to the address Flash memory Base address +

[(WRP1y_END+1) x 0x1000] (excluded). The minimum WRP area size is one WRP page

(4 Kbytes), WRP1y_END = WRP1y_STRT .

For example, to protect by WRP from the address 0x0806 2000 (included) to the address

0x0807 1FFF (included):

 If boot in Flash memory is selected, FLASH_WRP1AR register must be programmed with:

– WRP1A_STRT = 0x62.

– WRP1A_END = 0x71.

WRP1B_STRT and WRP1B_END in FLASH_WRP1BR can be used instead (area “B” in Flash memory).

When WRP is active, it cannot be erased or programmed. Consequently, a software mass erase cannot be performed if one area is write-protected.

If an erase/program operation to a write-protected part of the Flash memory is attempted, the write protection error flag (WRPERR) is set in the FLASH_SR register. This flag is also set for any write access to:

– OTP area

– part of the Flash memory that can never be written like the ICP

– PCROP area.

RM0471 Rev 5 93/1202

116

Embedded Flash memory (FLASH) RM0471

Note: When the Flash memory read protection level is selected (RDP level = 1), it is not possible to program or erase the memory if the CPU debug features are connected (JTAG or single wire) or boot code is being executed from RAM or System Flash memory, even if WRP is not activated. Any attempt generates an hard fault (BusFault).

Table 16: WRP protection

WRP registers values (x = 1 and y = A or B) WRP protection area

WRPxy_STRT = WRPxy_END

WRPxy_STRT > WRPxy_END

WRPxy_STRT < WRPxy_END

Page WRPxy is protected

No WRP, unprotected

Pages from WRPxy_STRT to WRPxy_END are protected

Note: To validate the WRP options, the option bytes must be reloaded through the OBL_LAUNCH bit in Flash memory control register.

94/1202

All or a part of the Flash memory and the SRAM2a and SRAM2b can be made secure, exclusively accessible by the CPU2, protected against execution, read and write from third parties. Only the CPU2 can execute, read and write in these areas. It can only be reached by the CPU2, while all other accesses (CPU1 and DMA) are strictly prohibited.

Changing the CPU2 security mode

CPU2 security start address can be modified by the secure CPU2 by loading a new User option SFSA.

CPU2 secure Flash memory area

The CPU2 secure Flash memory area has sector (4 Kbytes) granularity and is defined by the secure Flash memory start page offset User option (SFSA) into the Flash memory. This offset is controlled from the SFSA field in the

Secure Flash memory start address register

(FLASH_SFR) .

The CPU2 secure Flash memory area is defined as follows: Flash memory Base address +

[SFSA x 0x1000] (included) to the last Flash memory address: When CPU2 security is enabled, the minimum CPU2 secure area size is one sector (4 Kbytes).

For example, a CPU2 secure area from the address 0x080E 7000 (included) to the address

0x080F FFFF (included):

 FLASH_SFR registers must be programmed with:

– SFSA= 0x0E7.

A flag (ESE) is available from the Flash memory option register (FLASH_OPTR) informing

that CPU2 security is enabled.

Any CPU1 access to a CPU2 security area triggers RDERR or WRPERR flag error.

CPU2 secure SRAM2 areas

The CPU2 secure SRAM2a and SRAM2b areas have a 1 Kbyte granularity and are defined by the secure backup RAM (SRAM2a) start address User options (BRSD and SBRSA) and the secure non-backup RAM (SRAM2b) start address User options (NBRSD and SNBRSA) into the Flash memory. These offset are controlled by the SBRSA and SNBRSA fields in the

RM0471 Rev 5

RM0471 Embedded Flash memory (FLASH)

Flash memory secure SRAM2 start address and CPU2 reset vector register

(FLASH_SRRVR) .

The CPU2 secure SRAM2a area is defined as Backup SRAM2a Base address + [SBRSA x

0x0400] (included) to the last SRAM2a address.

As an example, for a CPU2 secure SRAM2a area from the address 0x2003 5000 (included) to the address 0x2003 7FFF (included) FLASH_SRRVR registers must be programmed with

SBRSA = 0x14.

Any CPU1 read access returns no data, and a write access to a CPU2 security SRAM2a area is discarded and triggers a bus error.

When BRSD is set to 1 the SRAM2a is non-secure.

The CPU2 secure non-backup SRAM2b area is defined as Non-backup SRAM2b base address + [SNBRSA x 0x0400] (included) to the last SRAM2b address.

As an example, for a CPU2 secure SRAM2b area from the address 0x2003 EC00 (included) to the address 0x2003 FFFF (included) FLASH_SRRVR registers must be programmed with SNBRSA = 0x1B.

Any CPU1 read access returns no data, and a write access to a CPU2 security SRAM2b area is discarded and triggers a bus error.

When NBRSD is set to 1 the SRAM2b is non-secure.

CPU2 debug access

Debug access to the CPU2 is disabled, as indicated by the DDS filed in the

Secure Flash memory start address register (FLASH_SFR) . The debugger has no access to the CPU2

and the secure peripherals and memory areas.

3.7 FLASH program/erase suspension

Flash memory program and erase operations can be suspended by setting the PES bit in the

Flash memory access control register (FLASH_ACR)

or Flash memory CPU2 access control register (FLASH_C2ACR) . This feature is useful when executing time critical

sections by a CPU. It makes it possible to suspend any new program or erase operation from being started, preventing CPU instruction and data fetches from being blocked.

When at least one PES bit is set:

 Any ongoing program or erase operation is completed.

– The maximum latency for a Flash memory program erase suspension is the maximum time for one program or erase operation to complete (see the device datasheet for more information on the program and erase timing).

 All new requested program and erase operations are not started, but suspended.

– PESD bits in the

Flash memory status register (FLASH_SR)

and Flash memory

CPU2 status register (FLASH_C2SR) are set as soon as any PES is set, no

matter if a program/erase is currently suspended. This allows a CPU to test PESD prior to requesting a program or an erase operation.

RM0471 Rev 5 95/1202

116

Embedded Flash memory (FLASH) RM0471

When all PES bits are reset to 0:

 A suspended program or erase operation is started.

–

The PESD bit in both the Flash memory status register (FLASH_SR) and in the

Flash memory CPU2 status register (FLASH_C2SR) are cleared.

Interrupt event

Table 17. Flash memory interrupt requests

Event flag

Event flag/interrupt clearing method

End of operation

Operation error

Read protection error

EOP

(1)

OPERR

(2)

RDERR

Write EOP = 1

Write OPERR = 1

Write RDERR = 1

Write protection error

Size error

Programming sequential error

Programming alignment error

Programming sequence error

Data miss during fast programming error

Fast programming error

ECC error correction

ECC double error (NMI)

WRPERR

SIZERR

PROGERR

PGAERR

PGSERR

MISSERR

FASTERR

ECCC

ECCD

Write WRPERR = 1

Write SIZERR = 1

Write PROGERR = 1

Write PGAERR = 1

Write PGSERR = 1

Write MISSERR = 1

Write FASTERR = 1

Write ECCC = 1

Write ECCD = 1

1. EOP is set only if EOPIE is set.

2. OPERR is set only if ERRIE is set.

Note:

Interrupt enable control bit

EOPIE

ERRIE

RDERRIE

N/A

ECCCIE

N/A

The Flash interface provides only a single interrupt line to both CPUs. It is good practice to manage Flash operations between the CPUs using a semaphore. To avoid receiving unwanted Flash operation interrupts, the CPU must mask the Flash interrupt in the NVIC or

SYSCFG pre-mask.

3.9 Register access protection

The User options registers can be protected by security.

The FLASH secure registers (FSD, SFSA, BRSD, SBRSA, NBRSD, SNBRSA, SBRV,

C2OPT, and DDS) are secure and can be written only by the secure CPU2 and read by any

CPU, secure and non-secure. When the CPU1 tries to write, the write is discarded.

96/1202 RM0471 Rev 5

RM0471 Embedded Flash memory (FLASH)

3.10.1 Flash memory access control register (FLASH_ACR)

Address offset: 0x000

Reset value: 0x0000 0600

Res.

PES rw

Res.

13 12 11 10 9 8 7

Res.

DCRST ICRST DCEN ICEN PRFTEN Res.

rw rw rw rw rw

Res.

17 16

Res.

EMPTY

1 rw

0 2 rw

LATENCY[2:0] rw rw

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 EMPTY : Flash memory user area empty.

When read indicates whether the first location of the User Flash memory is erased or has a programmed value.

0: Read: User Flash memory programmed

1: Read: User Flash memory empty

When written this bit is overwritten with the written value.

Bit 15 PES : CPU1 program / erase suspend request

0: Flash memory program and erase operations granted.

1: Any new Flash memory program and erase operation is suspended until this bit and the

same bit in Flash memory CPU2 access control register (FLASH_C2ACR) are cleared. The

PESD bit in both the

Flash memory status register (FLASH_SR) and

Flash memory CPU2 status register (FLASH_C2SR) is set when at least one PES bit in FLASH_ACR or

FLASH_C2ACR is set.

Bits 14:13 Reserved, must be kept at reset value.

Bit 12 DCRST : CPU1 Data cache reset

0: CPU1 Data cache is not reset

1: CPU1 Data cache is reset

This bit can be written only when the data cache is disabled.

Bit 11 ICRST : CPU1 Instruction cache reset

0: CPU1 Instruction cache is not reset

1: CPU1 Instruction cache is reset

This bit can be written only when the instruction cache is disabled.

Bit 10 DCEN : CPU1 Data cache enable

0: CPU1 Data cache is disabled

1: CPU1 Data cache is enabled

Bit 9 ICEN : CPU1 Instruction cache enable

0: CPU1 Instruction cache is disabled

1: CPU1 Instruction cache is enabled

Bit 8 PRFTEN: CPU1 Prefetch enable

0: CPU1 Prefetch disabled

1: CPU1 Prefetch enabled

RM0471 Rev 5 97/1202

116

Embedded Flash memory (FLASH) RM0471

Bits 7:3 Reserved, must be kept at reset value.

Bits 2:0 LATENCY[2:0] : Latency

These bits represent the ratio of the Flash memory HCLK clock period to the Flash memory access time.

000: Zero wait states

001: One wait state

010: Two wait states

011: Three wait states

Others: Reserved

31 w

15 w

Address offset: 0x008

Reset value: 0x0000 0000

29 w

14 w

28 w

27 w

26 w

25 w

24 23

KEY[31:16] w w

8 7

KEY[15:0] w w

22 w

21 w

20 w

19 w

18 w

17 w

1 w w w w w w w w w w w w

Bits 31:0 KEY : Flash memory key

The following values must be written consecutively to unlock the

Flash memory control register (FLASH_CR) and

Flash memory CPU2 control register (FLASH_C2CR)

, thus enabling programming/erasing operations:

KEY1: 0x4567 0123

KEY2: 0xCDEF 89AB

16 w w

3.10.3 Flash memory option key register (FLASH_OPTKEYR)

Address offset: 0x00C

Reset value: 0x0000 0000

31 w

15 w

29 w

14 w

28 w

27 w

26 w

25 w

24 23

OPTKEY[31:16] w

8 w

OPTKEY[15:0] w w

22 w

21 w

20 w

19 w

18 w

17 w

1 w w w w w w w w w w w w

Bits 31:0 OPTKEYR : Option byte key

The following values must be written consecutively to unlock the Flash memory option registers, enabling option byte programming/erasing operations:

KEY1: 0x0819 2A3B

KEY2: 0x4C5D 6E7F

16 w w

98/1202 RM0471 Rev 5

RM0471 Embedded Flash memory (FLASH)

Address offset: 0x010

Reset value: 0x000X 0000

Res.

15 14

OPTV

ERR

ERR rc_w1 rc_w1

13 r

OPTNV Res.

Res.

19 18 17

PESD CFGBSY .

Res r

3 r

2 1 9 8 7 6 5 4

FAST

ERR

MISS

ERR

PGS

ERR

SIZ

ERR

PGA

ERR

WRP

ERR

PROG

ERR rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Res.

ERR

BSY r

EOP rc_w1 rc_w1

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 PESD : Programming / erase operation suspended.

This bit is set and reset by hardware.

Set when at least one PES bit in either Flash memory access control register (FLASH_ACR)

or Flash memory CPU2 access control register (FLASH_C2ACR) is set.

Cleared when both PES bits in FLASH_ACR and FLASH_C2ACR are cleared.

When set, new program or erase operations are not started.

Bit 18 CFGBSY : Programming or erase configuration busy.

This bit is set and reset by hardware. (set when first word is sent and reset when program operation completes or is interrupted by an error.)

When set to ‘1’ the programming and erase settings in FLASH_PG and FLASH_PNB

requested by Flash memory control register (FLASH_CR) ) are used (busy), and cannot be

changed (a programming or erase operation is ongoing).

When reset to ‘0’ programming and erase settings in FLASH_PG and FLASH_PNB in Flash memory control register (FLASH_CR)

) can be modified.

Bit 17 Reserved, must be kept at reset value.

Bit 16 BSY : Busy

Indicates that a Flash memory operation requested by

Flash memory control register

(FLASH_CR)

is in progress. This bit is set at the beginning of a Flash memory operation, and reset when the operation finishes or when an error occurs.

Bit 15 OPTVERR : Option and Engineering bits loading validity error

Set by hardware when the options and engineering bits read may not be the one configured by the user or production. If options and engineering bits have not been properly loaded,

OPTVERR is set again after each system reset. Option bytes that fail loading are forced to a

safe value, see Section 3.4.2: Option bytes programming

Cleared by writing 1.

Bit 14 RDERR : PCROP read error

Set by hardware when an address to be read through the D-bus belongs to a read protected area of the Flash memory (PCROP protection). An interrupt is generated if RDERRIE is set in FLASH_CR.

Cleared by writing 1.

Bit 13 OPTNV : User option OPTVAL indication.

This bit is set and reset by hardware.

0: the OBL User option OPTVAL indicates “valid”.

1: the OBL User option OPTVAL indicates “not valid”.

Bits 12:10 Reserved, must be kept at reset value.

RM0471 Rev 5 99/1202

116

Embedded Flash memory (FLASH) RM0471

Bit 9 FASTERR : Fast programming error

Set by hardware when a fast programming sequence (activated by FSTPG) is interrupted due to an error (alignment, size, write protection or data miss). The corresponding status bit

(PGAERR, SIZERR, WRPERR or MISSERR) is set at the same time.

Cleared by writing 1.

Bit 8 MISERR : Fast programming data miss error

In Fast programming mode, 64 double words (512 bytes) must be sent to Flash memory successively, and the new data must be sent to the logic control before the current data is fully programmed. MISSERR is set by hardware when the new data is not present in time.

Cleared by writing 1.

Bit 7 PGSERR : Programming sequence error

Set by hardware when a write access to the Flash memory is performed by the code while

PG or FSTPG have not been set previously. Set also by hardware when PROGERR,

SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a previous programming error.

Cleared by writing 1.

Bit 6 SIZERR : Size error

Set by hardware when the size of the access is a byte or half-word during a program or a fast program sequence. Only double word programming is allowed (consequently: word access).

Cleared by writing 1.

Bit 5 PGAERR : Programming alignment error

Set by hardware when the data to program cannot be contained in the same double word

(64-bit) Flash memory in case of standard programming, or if there is a change of page during fast programming.

Cleared by writing 1.

Bit 4 WRPERR : Write protection error

Set by hardware when an address to be erased/programmed belongs to a write-protected part (by WRP, PCROP or RDP Level 1) of the Flash memory.

Cleared by writing 1.

Bit 3 PROGERR : Programming error

Set by hardware when a double-word address to be programmed contains a value different from 0xFFFF FFFF FFFF FFFF before programming, except if the data to write is

0x0000 0000 0000 0000.

Cleared by writing 1.

Bit 2 Reserved, must be kept at reset value.

Bit 1 OPERR : Operation error

Set by hardware when a Flash memory operation (program / erase) completes unsuccessfully.

This bit is set only if error interrupts are enabled (ERRIE = 1).

Cleared by writing ‘1’.

Bit 0 EOP : End of operation

Set by hardware when one or more Flash memory operation (programming / erase) has been completed successfully.

This bit is set only if the end of operation interrupts are enabled (EOPIE = 1).

Cleared by writing 1.

Address offset: 0x014

100/1202 RM0471 Rev 5

RM0471 Embedded Flash memory (FLASH)

LOCK rs

Res.

OPT

LOCK rs

Res.

Reset value: 0xC000 0000

Access: no wait state when no Flash memory operation is on going, word, half-word and byte access.

This register cannot be modified when CFGBSY in

Flash memory status register

(FLASH_SR)

is set.

–

When the PESD bit in Flash memory status register (FLASH_SR) is cleared, the

–

When the PESD bit in Flash memory status register (FLASH_SR) is set and a

program or an erase operation is ongoing, the register write access causes a bus error.

– When the PESD bit in

Flash memory status register (FLASH_SR)

is set, but there is no ongoing programming or erase operation, the register write access is completed. The requested program or erase operation is suspended, the

BSY/CFGBSY asserted and remains 1, until suspend is deactivated.

Consequently, PESD bit goes back to 0 and the suspended operation completes.

Res.

OBL_

LAUNCH rc_w1

Res.

ERRIE rw

10 rw

25 24 23

ERRIE EOPIE Res.

9 rw rw

8 rw

Res.

PNB[7:0] rw rw

21 20 19 18

Res.

FSTPG

5 rw

4 rw

3 rw rw

MER rw

OPT

STRT rs

PER rw

STRT rs

PG rw

Bit 31 LOCK: FLASH_CR lock

This bit is set only. When set, the FLASH_CR register is locked. It is cleared by hardware after detecting the unlock sequence.

In case of an unsuccessful unlock operation, this bit remains set until the next system reset.

Bit 30 OPTLOCK: Options lock

This bit is set only. When set, all bits concerning in FLASH_CR register and so option page are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit must be cleared before doing the unlock sequence for OPTLOCK bit.

In case of an unsuccessful unlock operation, this bit remains set until the next reset.

Bits 29:28 Reserved, must be kept at reset value.

Bit 27 OBL_LAUNCH : Forces the option byte loading

When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. It cannot be written if OPTLOCK is set.

0: Option byte loading complete

1: Option byte loading requested

Bit 26 RDERRIE : PCROP read error interrupt enable

This bit enables the interrupt generation when the RDERR bit in the FLASH_SR is set to 1.

0: PCROP read error interrupt disabled

1: PCROP read error interrupt enabled

Bit 25 ERRIE : Error interrupt enable

This bit enables the interrupt generation when the OPERR bit in the FLASH_SR is set to 1.

0: OPERR error interrupt disabled

1: OPERR error interrupt enabled

RM0471 Rev 5 101/1202

116

Embedded Flash memory (FLASH) RM0471

Bit 24 EOPIE : End of operation interrupt enable

This bit enables the interrupt generation when the EOP bit in the FLASH_SR is set to 1.

0: EOP Interrupt disabled

1: EOP Interrupt enabled

Bits 23:19 Reserved, must be kept at reset value.

Bit 18 FSTPG : Fast programming

0: Fast programming disabled

1: Fast programming enabled

Bit 17 OPTSTRT : Options modification start

This bit triggers an options operation when set.

This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_SR.

Bit 16 STRT : Start

This bit triggers an erase operation when set. If MER and PER bits are reset and the STRT bit is set, an unpredictable behavior may occur without generating any error flag. This condition must be forbidden.

This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_SR.

Starting operations by the CPU1, involving secure Flash memory pages are rejected and a bus error is generated.

Bits 15:11 Reserved, must be kept at reset value.

Bits 10:3 PNB[7:0] : Page number selection

These bits select the page to erase:

0x00:

0x01: page 0 page 1

...

0x7F: page 127

... (STM32WB50CG only)

0xFF: page 255 (STM32WB50CG only)

Bit 2 MER : Mass erase

This bit triggers the mass erase (all user pages) when set.

Bit 1 PER : Page erase

0: page erase disabled

1: page erase enabled

Bit 0 PG : Programming

0: Flash memory programming disabled

1: Flash memory programming enabled

Address offset: 0x018

Reset value: 0x0000 0000

Access: no wait state when no Flash memory operation is on going, word, half-word and byte access.

102/1202 RM0471 Rev 5

RM0471 Embedded Flash memory (FLASH)

31 30 29

ECCD ECCC Res.

rc_w1 rc_w1

15 14 13 r

28 27 26 r

CPUID[2:0] r

11 r

25 24 23 22

Res.

ECCCIE Res.

9 r rw

8 7

ADDR_ECC[15:0] r r

Res.

6 r

Res.

SYSF

_ECC r

Res.

3 r r r

Res.

ADDR

_ECC[16] r

0 r r r r r r r r

Bit 31 ECCD : ECC detection

Set by hardware when two ECC errors have been detected. When this bit is set, an NMI is generated.

Cleared by writing 1.

Bit 30 ECCC : ECC correction

Set by hardware when one ECC error has been detected and corrected. An interrupt is generated if ECCIE is set.

Cleared by writing 1.

Bit 29 Reserved, must be kept at reset value.

Bits 28:26 CPUID : CPU identification

Set by hardware, indicates the Bus-ID of the CPU access causing the ECC failure.

0x0: value for CPUID for CPU1 bus-ID

0x1: value for CPUID for CPU2 bus-ID

Bit 25 Reserved, must be kept at reset value.

Bit 24 ECCIE : ECC correction interrupt enable

0: ECCC interrupt disabled

1: ECCC interrupt enabled

Bits 23:21 Reserved, must be kept at reset value.

Bit 20 SYSF_ECC : System Flash memory ECC fail

This bit indicates that the ECC error correction or double ECC error detection is located in the System Flash memory.

Bits 19:17 Reserved, must be kept at reset value.

Bits 16:0 ADDR_ECC : ECC fail double-word address

These bits indicate that double word address is concerned by the ECC error correction or causes the double ECC error detection.

Address offset: 0x020

Reset value: ‘bXXX1 XXXX X111 XXXX 1XXX XXX1 XXXX XXXX. The option bits are loaded with values from Flash memory at reset release.

Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access.

RM0471 Rev 5 103/1202

116

Embedded Flash memory (FLASH) RM0471

31 30

AGC_TRIM[2:0]

29 rw

Res.

rw rw

14 nRST

_SHDW

13 nRST

_STDBY rw rw

Res.

12 nRST

_STOP rw

27 n

BOOT0 rw

26 25 24 nSW

BOOT0 rw

SRAM2

_RST rw

SRAM2

_PE rw

10 9 8

23 n

BOOT1 rw

7 rw

BOR_LEV[2:0] rw rw

ESE r rw

Res.

6 rw

Res.

WWDG

_SW rw

IWGD

_STDBY rw

IWDG

_STOP rw

IWDG

_SW rw

RDP[7:0] rw rw rw rw rw rw

Bits 31:29 AGC_TRIM : Radio automatic gain control trimming

Default value 0b001

Bit 28 Reserved, must be kept at reset value.

Bit 27 nBOOT0: nBOOT0 option bit

If nSWBOOT0 bit configuration select BOOT0 is taken from bit nBOOT0, together with bit nBOOT1, selects boot from the User Flash memory, SRAM1, or System Flash memory. Refer to

Section 2.3: Boot configuration .

0: nBOOT0 = 0

1: nBOOT0 = 1

Bit 26 nSWBOOT0: Software BOOT0 selection

0: BOOT0 taken from the option bit nBOOT0

1: BOOT0 taken from PH3/BOOT0 pin

Bit 25 SRAM2_RST: SRAM2 and PKA RAM Erase when system reset

0: SRAM2 and PKA RAM erased when a system reset occurs

1: SRAM2 and non-secure PKA RAM not erased when a system reset occurs

Bit 24 SRAM2_PE: SRAM2 parity check enable

0: SRAM2 parity check enabled

1: SRAM2 parity check disabled

Bit 23 nBOOT1: Boot configuration

Together with the BOOT0 pin or option bit nBOOT0 (depending on nSWBOOT0 option bit configuration), this bit selects boot mode from the User Flash memory, SRAM1 or the

System memory. Refer to Section 2.3: Boot configuration .

Bits 22:20 Reserved, must be kept at reset value.

Bit 19 WWDG_SW: Window watchdog selection

0: Hardware window watchdog

1: Software window watchdog

Bit 18 IWDG_STDBY: Independent watchdog counter freeze in Standby mode

0: Independent watchdog counter is frozen in Standby mode

1: Independent watchdog counter is running in Standby mode

Bit 17 IWDG_STOP: Independent watchdog counter freeze in Stop mode

0: Independent watchdog counter is frozen in Stop mode

1: Independent watchdog counter is running in Stop mode

Bit 16 IDWG_SW: Independent watchdog selection

0: Hardware independent watchdog

1: Software independent watchdog

Bit 15 Reserved, must be kept at reset value.

104/1202 RM0471 Rev 5

RM0471 Embedded Flash memory (FLASH)

Bit 14 nRST_SHDW

0: Reset generated when entering the Shutdown mode

1: No reset generated when entering the Shutdown mode

Bit 13 nRST_STDBY

0: Reset generated when entering the Standby mode

1: No reset generated when entering the Standby mode

Bit 12 nRST_STOP

0: Reset generated when entering the Stop mode

1: No reset generated when entering the Stop mode

Bits11:9 BOR_LEV: BOR reset level

These bits contain the V

supply level threshold that activates/releases the reset.

000: BOR Level 0. Reset level threshold is ~ 1.7 V

001: BOR Level 1. Reset level threshold is ~ 2.0 V

010: BOR Level 2. Reset level threshold is ~ 2.2 V

011: BOR Level 3. Reset level threshold is ~ 2.5 V

100: BOR Level 4. Reset level threshold is ~ 2.8 V

Bit 8 ESE: System security enabled flag.

Indicates whether the system security is enabled User Flash memory FSD = 0.

0: Security disabled

1: Security enabled

Bits 7:0 RDP: Read protection level

0xAA: Level 0, read protection not active

0xCC: Level 2, chip read protection active

Others: Level 1, memories read protection active

Note: Take care about PCROP_RDP configuration in Level 1. Refer to Level 1: Read protection for more details.

3.10.8 Flash memory PCROP zone A start address register

(FLASH_PCROP1ASR)

Address offset: 0x024

Reset value: ‘b1111 1111 1111 1111 1111 111X XXXX XXXX

Access: no wait state when no Flash memory operation is on going, word, half-word access

Res.

8 rw

7 rw

6 rw

5 4 3

PCROP1A_STRT[8:0] rw rw rw

2 rw

1 rw

0 rw

Bits 31:9 Reserved, must be kept at reset value.

Bits 8:0 PCROP1A_STRT: PCROP1A area start offset

PCROP1A_STRT contains the first 2 Kbytes page of the PCROP1A area. Note that bit 8 is reserved on STM32WB30CE.

RM0471 Rev 5 105/1202

116

Embedded Flash memory (FLASH) RM0471

31 30

PCROP_RDP Res.

Res.

(FLASH_PCROP1AER)

Address offset: 0x028

Reset value: ‘bX111 1111 1111 1111 1111 1111 XXXX XXXX

Access: no wait state when no Flash memory operation is on going, word, half-word access.

PCROP_RDP bit can be accessed with byte access

Res.

8 rw

7 rw

Res.

6 rw

Res.

5 4 3

PCROP1A_END[8:0] rw rw rw

Res.

2 rw

Res.

1 rw

Res.

0 rw

Bit 31 PCROP_RDP: PCROP area preserved when RDP level decreased

This bit is set only. It is reset after a full mass erase due to a change of RDP from Level 1 to

Level 0.

0: PCROP area is not erased when the RDP level is decreased from Level 1 to Level 0.

1: PCROP area is erased when the RDP level is decreased from Level 1 to Level 0 (full mass erase).

Bits 30:9 Reserved, must be kept at reset value.

Bits 8:0 PCROP1A_END: PCROP1A area end offset

PCROP1A_END contains the last 2 Kbytes page of the PCROP1A area. Note that bit 8 is reserved on STM32WB30CE devices.

3.10.10 Flash memory WRP area A address register (FLASH_WRP1AR)

Address offset: 0x02C

Reset value: 0xFFXX FFXX

Access: no wait state when no Flash memory operation is on going, word, half-word and byte access.

Res.

23 rw

22 rw

21 rw

5 rw

20 19

WRP1A_END[7:0] rw rw

4 3

WRP1A_STRT[7:0] rw rw

18 rw

2 rw

17 rw

1 rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 WRP1A_END: WRP first area “A” end offset

Contains the last 4 Kbytes page of the WRP first area. Note that bit 23 is reserved on

STM32WB30CE devices.

Bits 15:8 Reserved, must be kept at reset value.

16 rw

0 rw

106/1202 RM0471 Rev 5

RM0471 Embedded Flash memory (FLASH)

Bits 7:0 WRP1A_STRT: WRP first area “A” start offset

Contains the first 4 Kbytes page of the WRP first area. Note that bit 7 is reserved on

STM32WB30CE devices.

3.10.11 Flash memory WRP area B address register (FLASH_WRP1BR)

Address offset: 0x030

Reset value: 0xFFXX FFXX

Access: no wait state when no Flash memory operation is on going, word, half-word and byte access.

Res.

23 22 17 16

Res.

7 rw rw

6 rw

21 rw

5 rw

20 19

WRP1B_END[7:0] rw rw

4 3

WRP1B_STRT[7:0] rw rw

18 rw

2 rw rw

1 rw rw

0 rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 WRP1B_END: WRP second area “B” end offset

WRPB1_END contains the last 4 Kbytes page of the WRP second area. Note that bit 23 is reserved on STM32WB30CE devices.

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:0 WRP1B_STRT: WRP second area “B” start offset

WRPB1_END contains the first 4 Kbytes page of the WRP second area. Note that bit 7 is reserved on STM32WB30CE devices.

3.10.12 Flash memory PCROP zone B start address register

(FLASH_PCROP1BSR)

Address offset: 0x034

Reset value: ‘b1111 1111 1111 1111 1111 111X XXXX XXXX

Access: no wait state when no Flash memory operation is on going, word, half-word access.

Res.

8 rw

7 rw

6 rw

5 4 3

PCROP1B_STRT[8:0] rw rw rw

2 rw

1 rw

Bits 31:9 Reserved, must be kept at reset value.

Bits 8:0 PCROP1B_STRT: PCROP1B area start offset

Contains the first 2 Kbytes page of the PCROP1B area. Note that bit 8 is reserved on

STM32WB30CE devices.

0 rw

RM0471 Rev 5 107/1202

116

Embedded Flash memory (FLASH) RM0471

Res.

(FLASH_PCROP1BER)

Address offset: 0x038

Reset value: ‘b1111 1111 1111 1111 1111 111X XXXX XXXX

Access: no wait state when no Flash memory operation is on going, word, half-word access.

Res.

8 rw

7 rw

6 rw

5 4 3

PCROP1B_END[8:0] rw rw rw

2 rw

1 rw

0 rw

Bits 31:9 Reserved, must be kept at reset value.

Bits 8:0 PCROP1B_END: PCROP1B area end offset

Contains the last 2 Kbytes page of the PCROP1B area. Note that bit 8 is reserved on

STM32WB30CE devices.

3.10.14 Flash memory IPCC mailbox data buffer address register

(FLASH_IPCCBR)

Address offset: 0x03C

Reset value: ‘b1111 1111 1111 1111 11XX XXXX XXXX XXXX

Res.

13 12 11 10 9 8 rw

7 6

IPCCDBA[13:0] rw rw

5 rw

4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:0 IPCCDBA: IPCC mailbox data buffer base address offset

Contains the first double-word offset of the IPCC mailbox data buffer area in SRAM2.

3.10.15 Flash memory CPU2 access control register (FLASH_C2ACR)

Address offset: 0x05C

Reset value: 0x0000 0600

Res.

PES rw

Res.

12 11 10

Res.

ICRST Res.

9 8 7

ICEN PRFTEN Res.

rw rw

Res.

108/1202 RM0471 Rev 5

RM0471 Embedded Flash memory (FLASH)

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 PES : CPU2 program / erase suspend request

0: Flash memory program and erase operations granted.

1: Any new Flash memory program and erase operation is suspended until this bit and the

same bit in Flash memory access control register (FLASH_ACR) are cleared. The PESD bit

in both the Flash memory status register (FLASH_SR) and

Flash memory CPU2 status register (FLASH_C2SR)

is set when at least one PES bit in FLASH_ACR or

FLASH_C2ACR is set.

Bits 14:12 Reserved, must be kept at reset value.

Bit 11 ICRST : CPU2 Instruction cache reset

0: CPU2 Instruction cache is not reset

1: CPU2 Instruction cache is reset

This bit can be written only when the instruction cache is disabled.

Bit 10 Reserved, must be kept at reset value.

Bit 9 ICEN : CPU2 Instruction cache enable

0: CPU2 Instruction cache is disabled

1: CPU2 Instruction cache is enabled

Bit 8 PRFEN: CPU2 Prefetch enable.

0: CPU2 prefetch is disabled

1: CPU2 prefetch is enabled

Bits 7:0 Reserved, must be kept at reset value.

3.10.16 Flash memory CPU2 status register (FLASH_C2SR)

Address offset: 0x060

Reset value: 0x000X 0000

Access: no wait state, word, half-word and byte access.

Res.

ERR rc_w1

Res.

20 19 18 17

Res.

PESD .

CFGBSY .

Res

4 r

3 r

2 1 9 8 7 6 5

FAST

ERR

MISS

ERR

PGS

ERR

SIZ

ERR

PGA

ERR

WRP

ERR

PROG

ERR rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Res.

ERR

BSY r

EOP rc_w1 rc_w1

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 PESD : Programming / erase operation suspended.

This bit is set and reset by hardware.

Set when at least one PES bit in either Flash memory access control register (FLASH_ACR)

or Flash memory CPU2 access control register (FLASH_C2ACR) is set.

Cleared when both PES bits in FLASH_ACR and FLASH_C2ACR are cleared.

When set new program or erase operations are not started.

RM0471 Rev 5 109/1202

116

Embedded Flash memory (FLASH) RM0471

Bit 18 CFGBSY : Programming or erase configuration busy.

This bit is set and reset by hardware. (set when first word is sent and reset when program operation completes or is interrupt by an error.)

When set to ‘1’ the programming and erase settings in (FLASH_PG, and FLASH_PNB in

Flash memory CPU2 control register (FLASH_C2CR)

) are used (busy) and may not be changed. A Flash programming or erase operation is ongoing.

When reset to ‘0’ programming and erase settings in (FLASH_PG and FLASH_PNB in

Flash memory CPU2 control register (FLASH_C2CR)

) may be modified.

Bit 17 Reserved, must be kept at reset value.

Bit 16 BSY : Busy

This bit indicates that a Flash memory operation requested by Flash memory CPU2 control register (FLASH_C2CR)

is in progress. This is set on the beginning of a Flash memory operation and reset when the operation finishes or when an error occurs.

Bit 15 Reserved, must be kept at reset value.

Bit 14 RDERR : PCROP read error

Set by hardware when an address to be read through the D-bus belongs to a read protected area of the Flash memory (PCROP protection). An interrupt is generated if RDERRIE is set in FLASH_CR.

Cleared by writing 1.

Bits 13:10 Reserved, must be kept at reset value.

Bit 9 FASTERR : Fast programming error

Set by hardware when a fast programming sequence (activated by FSTPG) is interrupted due to an error (alignment, size, write protection or data miss). The corresponding status bit

(PGAERR, SIZERR, WRPERR or MISSERR) is set at the same time.

Cleared by writing 1.

Bit 8 MISERR : Fast programming data miss error

In Fast programming mode, 64 double words (512 bytes) must be sent to the Flash memory successively, and the new data must be sent to the Flash memory logic control before the current data is fully programmed. MISSERR is set by hardware when the new data is not present in time.

Cleared by writing 1.

Bit 7 PGSERR : Programming sequence error

Set by hardware when a write access to the Flash memory is performed by the code while

PG or FSTPG have not been set previously. Set also by hardware when PROGERR,

SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a previous programming error.

Cleared by writing 1.

Bit 6 SIZERR : Size error

Set by hardware when the size of the access is a byte or half-word during a program or a fast program sequence. Only double word programming is allowed (consequently: word access).

Cleared by writing 1.

Bit 5 PGAERR : Programming alignment error

Set by hardware when the data to program cannot be contained in the same double word

(64-bit) Flash memory in case of standard programming, or if there is a change of page during fast programming.

Cleared by writing 1.

110/1202 RM0471 Rev 5

RM0471 Embedded Flash memory (FLASH)

Bit 4 WRPERR : Write protection error

Set by hardware when an address to be erased/programmed belongs to a write-protected part (by WRP, PCROP or RDP Level 1) of the Flash memory.

Cleared by writing 1.

Bit 3 PROGERR : Programming error

Set by hardware when a double-word address to be programmed contains a value different from 0xFFFF FFFF before programming, except if the data to write is

0x0000 0000 0000 0000.

Cleared by writing 1.

Bit 2 Reserved, must be kept at reset value.

Bit 1 OPERR : Operation error

Set by hardware when a Flash memory operation (program / erase) completes unsuccessfully.

This bit is set only if error interrupts are enabled (ERRIE = 1).

Cleared by writing ‘1’.

Bit 0 EOP : End of operation

Set by hardware when one or more Flash memory operation (programming / erase) completes successfully.

This bit is set only if the end of operation interrupts are enabled (EOPIE = 1).

Cleared by writing 1.

3.10.17 Flash memory CPU2 control register (FLASH_C2CR)

Address offset: 0x064

Reset value: 0xC000 0000

Access: no wait state when no Flash memory operation is on going, word, half-word and byte access

This register cannot be modified when CFGBSY in

Flash memory CPU2 status register

(FLASH_C2SR) is set.

 When the PESD bit in

Flash memory CPU2 status register (FLASH_C2SR)

is cleared, the register write access is stalled until the CFGBSY bit is cleared (by the other CPU).

 When the PESD bit in

Flash memory CPU2 status register (FLASH_C2SR)

is set, the register write access causes a bus error.

 When the PESD bit in

Flash memory CPU2 status register (FLASH_C2SR)

is set, but there is no ongoing programming or erase operation, the register write access is completed. The requested program or erase operation is suspended, the

BSY/CFGBSY asserted and remains 1 until suspend has been deactivated.

Consequently, PESD bit goes back to 0 and the suspended operation completes.

Res.

ERRIE rw

ERR

IE rw

9 rw rw

EOP

IE rw

8 rw

Res.

PNB[7:0]

6 rw rw

21 20 19 18 17

Res.

FSTPG Res.

5 rw

4 rw

3 rw rw

MER rw

PER rw

STRT rs

PG rw

RM0471 Rev 5 111/1202

116

Embedded Flash memory (FLASH) RM0471

Bits 31:27 Reserved, must be kept at reset value.

Bit 26 RDERRIE : PCROP read error interrupt enable

This bit enables the interrupt generation when the RDERR bit in the FLASH_SR is set to 1.

0: PCROP read error interrupt disabled

1: PCROP read error interrupt enabled

Bit 25 ERRIE : Error interrupt enable

This bit enables the interrupt generation when the OPERR bit in the FLASH_SR is set to 1.

0: OPERR error interrupt disabled

1: OPERR error interrupt enabled

Bit 24 EOPIE : End of operation interrupt enable

This bit enables the interrupt generation when the EOP bit in the FLASH_SR is set to 1.

0: EOP Interrupt disabled

1: EOP Interrupt enabled

Bits 23:19 Reserved, must be kept at reset value

Bit 18 FSTPG : Fast programming

0: Fast programming disabled

1: Fast programming enabled

Bit 17 Reserved, must be kept at reset value.

Bit 16 STRT : Start

This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_SR.

Starting operations by the CPU1, involving secure Flash memory pages is rejected and a bus error generated.

Bits 15:11 Reserved, must be kept at reset value.

Bits 10:3 PNB[7:0] : Page number selection

These bits select the page to erase:

0x00:

0x01:

...

page 0 page 1

... (STM32WB50CG only)

0xFF: page 255 (STM32WB50CG only)

Bit 2 MER : Mass erase

This bit triggers the mass erase (all user pages) when set.

Bit 1 PER : Page erase

0: page erase disabled

1: page erase enabled

Bit 0 PG : Programming

0: Flash programming disabled

1: Flash programming enabled

3.10.18 Secure Flash memory start address register (FLASH_SFR)

Address offset: 0x080

112/1202 RM0471 Rev 5

RM0471 Embedded Flash memory (FLASH)

Res.

Reset value: ‘b1111 1111 1111 1111 1111 1110 XXXX XXXX

This register provides write access security and can only be written by the CPU2. A write access from the CPU1 is ignored and a bus error generated. On any read access the register value is returned.

Written values are only taken into account after OBL.

Res.

DDS rw

Res.

FSD rw

7 rw

6 rw

5 rw

4 3

SFSA[7:0] rw rw

2 rw

1 rw

0 rw

Bits 31:13 Reserved, must be kept at reset value.

Bits 12 DDS: Disable CPU2 debug access

0: CPU2 debug access enabled

1: CPU2 debug access disabled

Bits 11:9 Reserved, must be kept at reset value.

Bits 8 FSD: Flash memory security disabled.

1: System and Flash memory non-secure

0: System and Flash memory secure (the secure area of the Flash memory is given by

SFSA)

Bits 7:0 SFSA: Secure Flash memory start address

SFSA[7:0] contain the start address of the first 4 Kbytes page of the secure Flash memory area.

3.10.19 Flash memory secure SRAM2 start address and CPU2 reset vector register (FLASH_SRRVR)

Address offset: 0x084

Reset value: ‘bXXXX XXX1 XXXX XXXX XXXX XXXX XXXX XXXX

This register provides write access security and can only be written by the CPU2. A write access from the CPU1 is ignored and a bus error generated. On any read access the register value is returned.

Written values are only taken into account after OBL.

31 30

C2OPT .

NBRSD rw

15 rw

14 rw rw

29 rw

13 rw

28 27

SNBRSA[4:0]

26 rw

12 rw

11 rw

10 rw rw rw

25 rw

9 rw

Res.

BRSD rw

7 8

SBRV[15:0] rw rw

22 rw

6 rw

21 20

SBRSA[4:0]

19 rw

5 rw

4 rw

3 rw rw rw

18 rw

2 rw

17 16

SBRV[17:16] rw

1 rw

0 rw rw

RM0471 Rev 5 113/1202

116

Embedded Flash memory (FLASH) RM0471

Bit 31 C2OPT: CPU2 boot reset vector memory selection.

0: SBRV offset addresses SRAM1 or SRAM2, from start address 0x2000 0000. SBRV value must be kept within the SRAM area.

1: SBRV offset addresses Flash memory, from start address 0x0800 0000.

Bits 30 NBRSD: Non-backup SRAM2b security disable.

NBRSD = 1: SRAM2b is non-secure

NBRSD = 0: SRAM2b is secure. SNBRSA[4:0] contains the start address of the first

1 Kbyte page of the secure non-backup SRAM2b area.

Bits 29:25 SNBRSA: Secure non-backup SRAM2b start address

NBRSD = 0: SRAM2b is secure. SNBRSA[4:0] contains the start address of the first

1 Kbyte page of the secure non-backup SRAM2b area.

Bit 24 Reserved, must be kept at reset value.

Bit 23 BRSD: Backup SRAM2a security disable.

BRSD = 1: SRAM2a is non-secure

BRSD = 0: SRAM2a is secure. SBRSA[4:0] contains the start address of the first 1 Kbyte page of the secure backup SRAM2a area.

Bits 22:18 SBRSA: Secure backup SRAM2a start address

BRSD = 0: SRAM2a is secure. SBRSA[4:0] contains the start address of the first 1 Kbyte page of the secure backup SRAM2a area.

Bits 17:0 SBRV: CPU2 boot reset vector

Contains the word aligned CPU2 boot reset start address offset within the selected memory area by C2OPT.

114/1202 RM0471 Rev 5

RM0471

Table 18. Flash interface register map and reset values

Offset Register

0x000

0x004

0x008

0x00C

FLASH_ACR

LATENCY

[2:0]

Reset value

Reserved

Reset value

FLASH_KEYR

Reset value

FLASH_OPT

KEYR

Reset value

0 0

OPTKEYR[31:0]

0 0 1 1 0 0 0 0

KEYR[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x010

FLASH_SR

Reset value 0 0 0 X 0 X 0 0 0 0 0 0 0 0 0

0x014

FLASH_CR

Reset value 1 1

0x018

FLASH_ECCR

Reset value 0 0

0 0 0 0

CPUID

[2:0]

0 0 0 0

0 0 0 0 0 0

PNB[7:0]

0 0

ADDR_ECC[16:0]

0 0 0 0 0 0

0x020

FLASH_OPTR

0x024

Reset value

FLASH_

PCROP1ASR

Reset value

X X X X X X X X

0x028

FLASH_

PCROP1AER

0x02C

Reset value

FLASH_

WRP1AR

Reset value x

X X X X

WRP1A_END[7:0]

X X X X X X X X

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BOR_LEV

[2:0]

RDP[7:0]

X X X X X X 1 X X X X X X X X

PCROP1A_STRT[8:0]

X X X X X X X X X

PCROP1A_END[8:0]

X X X X X X X X X

WRP1A_STRT[7:0]

X X X X X X X X

RM0471 Rev 5

Embedded Flash memory (FLASH)

115/1202

116

Embedded Flash memory (FLASH)

Table 18. Flash interface register map and reset values (continued)

Offset Register

RM0471

0x030

0x034

0x038

0x03C

FLASH_

WRP1BR

Reset value

FLASH_

PCROP1BSR

Reset value

FLASH_

PCROP1BER

Reset value

FLASH_

IPCCBR

Reset value

0x05C

FLASH_C2ACR

Reset value

WRP1B_END[7:0]

X X X X X X X X

WRP1B_STRT[7:0]

X X X X X X X X

PCROP1B_STRT[8:0]

X X X X X X X X X

PCROP1B_END[8:0]

X X X X X X X X X

IPCCDBA[13:0]

X X X X X X X X X X X X X X

0 1 0

0x060

FLASH_C2SR

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0

0x064

FLASH_C2CR

0x080

Reset value

FLASH_SFR

Reset value

0 0

0x084

FLASH_SRRVR

Reset value

SNBRSA[4:0]

X X X X X X X

SBRSA[4:0]

0 0

PNB[7:0]

0 0 0 0 0 0 0 0 0 0 0

SFSA[7:0]

0 X X X X X X X X

SBRV[17:0]

X X X X X X X X X X X X X X X X X X X X X X X X

Refer to Section 2.2 on page 55 for the register boundary addresses.

116/1202 RM0471 Rev 5

RM0471 Radio system

4.1 Introduction

The system is ultra low power compliant with the Bluetooth

core specification BLE5.2 and

IEEE 802.15.4 standard.

The radio system consists of a 2.4 GHz RF front end and a Bluetooth

Low Energy (BLE) and IEEE 802.15.4 physical layer controller. The system is controlled from the CPU2 that contains the radio lower protocol software layers. Interface to the application running on the

CPU2 is provided via mailbox message system.

 2.4 GHz RF transceiver supporting:

– Bluetooth

BLE5.2 standard support

– IEEE 802.15.4-2011 standard support

 Programmable output power

 RSSI

 Integrated balun

 Bluetooth ® BLE5.2 features:

– GAP: central, peripheral, observer and broadcaster roles

– Simultaneous multiple role support

– Master / slave support

– ATT / GATT: client and server

RM0471 Rev 5 117/1202

118

Radio system RM0471

The block diagram of the Radio system is shown in Figure 5

Figure 5. Radio system block diagram

Timer and Power control

AGC

Interrupt

Wakeup

AHB

APB

Interrupt

Wakeup

RF control

BLE modulator

BLE controller

BLE demodulator

802.15.4 modulator

802.15.4

MAC

802.15.4 demodulator PLL

BP filter

LNA

RF1

See note

Adjust

HSE

Adjust

LDO LDO LDO

Max PA level

Trimmed bias

V

DDRF

OSC_IN OSC_OUT

32 MHz

Note: on QFN packages V

through exposed pad, and V

SSRF

pin must be connected to ground plane

MS52602V2

118/1202 RM0471 Rev 5

RM0471

5

Cyclic redundancy check calculation unit (CRC)

Cyclic redundancy check calculation unit (CRC)

5.1 Introduction

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16- or 32-bit data word and a generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the functional safety standards, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link time and stored at a given memory location.

5.2 CRC main features

 Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7

+ X

+ X +1

 Alternatively, uses fully programmable polynomial with programmable size (7, 8, 16, 32 bits)

 Handles 8-,16-, 32-bit data size

 Programmable CRC initial value

 Single input/output 32-bit data register

 Input buffer to avoid bus stall during calculation

 CRC computation done in 4 AHB clock cycles (HCLK) for the 32-bit data size

 General-purpose 8-bit register (can be used for temporary storage)

 Reversibility option on I/O data

 Accessed through AHB slave peripheral by 32-bit words only, with the exception of

CRC_DR register that can be accessed by words, right-aligned half-words and rightaligned bytes

RM0471 Rev 5 119/1202

125

Cyclic redundancy check calculation unit (CRC)

5.3 CRC functional description

crc_hclk

Figure 6. CRC calculation unit block diagram read access

32-bit AHB bus write access 32-bit accesses

Data register

(output)

Data register

(input)

CRC computation

CRC_INIT

CRC_CR

CRC_POL

CRC_IDR

RM0471

MS19882V3

Signal name crc_hclk

Table 19. CRC internal input/output signals

Signal type Description

Digital input AHB clock

The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to input new data (write access), and holds the result of the previous CRC calculation (read access).

Each write operation to the data register creates a combination of the previous CRC value

(stored in CRC_DR) and the new one. CRC computation is done on the whole 32-bit data word or byte by byte depending on the format of the data being written.

The CRC_DR register can be accessed by word, right-aligned half-word and right-aligned byte. For the other registers only 32-bit access is allowed.

The duration of the computation depends on data width:

 4 AHB clock cycles for 32 bits

 2 AHB clock cycles for 16 bits

 1 AHB clock cycles for 8 bits

An input buffer allows a second data to be immediately written without waiting for any wait states due to the previous CRC calculation.

120/1202 RM0471 Rev 5

RM0471

Note:

Cyclic redundancy check calculation unit (CRC)

The data size can be dynamically adjusted to minimize the number of write accesses for a given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write followed by a byte write.

The input data can be reversed, to manage the various endianness schemes. The reversing operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits in the CRC_CR register.

For example: input data 0x1A2B3C4D is used for CRC calculation as:

 0x58D43CB2 with bit-reversal done by byte

 0xD458B23C with bit-reversal done by half-word

 0xB23CD458 with bit-reversal done on the full word

The output data can also be reversed by setting the REV_OUT bit in the CRC_CR register.

The operation is done at bit level: for example, output data 0x11223344 is converted into

0x22CC4488.

The CRC calculator can be initialized to a programmable value using the RESET control bit in the CRC_CR register (the default value is 0xFFFFFFFF).

The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR register is automatically initialized upon CRC_INIT register write access.

The CRC_IDR register can be used to hold a temporary value related to CRC calculation. It is not affected by the RESET bit in the CRC_CR register.

Polynomial programmability

The polynomial coefficients are fully programmable through the CRC_POL register, and the polynomial size can be configured to be 7, 8, 16 or 32 bits by programming the

POLYSIZE[1:0] bits in the CRC_CR register. Even polynomials are not supported.

The type of an even polynomial is X+X

+..+X n

, while the type of an odd polynomial is

1+X+X

+..+X n

If the CRC data is less than 32-bit, its value can be read from the least significant bits of the

CRC_DR register.

To obtain a reliable CRC calculation, the change on-fly of the polynomial value or size can not be performed during a CRC calculation. As a result, if a CRC calculation is ongoing, the application must either reset it or perform a CRC_DR read before changing the polynomial.

The default polynomial value is the CRC-32 (Ethernet) polynomial: 0x4C11DB7.

RM0471 Rev 5 121/1202

125

Cyclic redundancy check calculation unit (CRC) RM0471

The CRC_DR register can be accessed by words, right-aligned half-words and right-aligned bytes. For the other registers only 32-bit accesses are allowed.

5.4.1

31 rw

15 rw

CRC data register (CRC_DR)

Address offset: 0x00

Reset value: 0xFFFF FFFF

30 29 rw

14 rw

28 rw

27 rw

26 rw

25 rw

24 23

DR[31:16] rw

8 rw

DR[15:0] rw rw

22 rw

21 rw

20 rw

19 rw

18 rw

17 rw

16 rw

0 rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 DR[31:0]: Data register bits

This register is used to write new data to the CRC calculator.

It holds the previous CRC calculation result when it is read.

If the data size is less than 32 bits, the least significant bits are used to write/read the correct value.

5.4.2

31 rw

15 rw

CRC independent data register (CRC_IDR)

Address offset: 0x04

Reset value: 0x0000 0000

30 29 rw

14 rw

28 rw

27 rw

26 rw

25 rw

24 23

IDR[31:16] rw

8 rw

IDR[15:0] rw rw

22 rw

21 rw

20 rw

19 rw

18 rw

17 rw

16 rw

0 rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 IDR[31:0] : General-purpose 32-bit data register bits

These bits can be used as a temporary storage location for four bytes.

This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register rw

122/1202 RM0471 Rev 5

RM0471 Cyclic redundancy check calculation unit (CRC)

5.4.3

Res.

CRC control register (CRC_CR)

Address offset: 0x08

Reset value: 0x0000 0000

Res.

REV_

OUT rw

6 5

REV_IN[1:0] rw rw

4 3

POLYSIZE[1:0] rw rw

Res.

1 0

Res.

RESET rs

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 REV_OUT : Reverse output data

This bit controls the reversal of the bit order of the output data.

0: Bit order not affected

1: Bit-reversed output format

Bits 6:5 REV_IN[1:0] : Reverse input data

These bits control the reversal of the bit order of the input data

00: Bit order not affected

01: Bit reversal done by byte

10: Bit reversal done by half-word

11: Bit reversal done by word

Bits 4:3 POLYSIZE[1:0] : Polynomial size

These bits control the size of the polynomial.

00: 32 bit polynomial

01: 16 bit polynomial

10: 8 bit polynomial

11: 7 bit polynomial

Bits 2:1 Reserved, must be kept at reset value.

Bit 0 RESET : RESET bit

This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware

RM0471 Rev 5 123/1202

125

Cyclic redundancy check calculation unit (CRC) RM0471

5.4.4

31 rw

15 rw

CRC initial value (CRC_INIT)

Address offset: 0x10

Reset value: 0xFFFF FFFF

30 29 rw

14 rw

28 rw

27 rw

26 rw

25 rw

24 23

CRC_INIT[31:16] rw

8 rw

CRC_INIT[15:0] rw rw

22 rw

6 rw rw rw rw rw rw rw

Bits 31:0 CRC_INIT[31:0] : Programmable initial CRC value

This register is used to write the CRC initial value.

21 rw

5 rw

20 rw

4 rw

19 rw

3 rw

18 rw

2 rw

17 rw

1 rw

16 rw

0 rw

5.4.5

31 rw

15 rw

CRC polynomial (CRC_POL)

Address offset: 0x14

Reset value: 0x04C1 1DB7

30 29 rw

14 rw

28 rw

27 rw

26 rw

25 rw

24 23

POL[31:16] rw

8 rw

POL[15:0] rw rw

22 rw

21 rw

20 rw

19 rw

18 rw

17 rw

16 rw

0 rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 POL[31:0] : Programmable polynomial

This register is used to write the coefficients of the polynomial to be used for CRC calculation.

If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value.

124/1202 RM0471 Rev 5

RM0471 Cyclic redundancy check calculation unit (CRC)

5.4.6

Offset

0x00

0x04

CRC register map

Table 20. CRC register map and reset values

Register name

CRC_DR

Reset value

CRC_IDR

DR[31:0]

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

IDR[31:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CRC_CR

0x08

0x10

0x14

Reset value

CRC_INIT

Reset value

CRC_POL

Reset value

0 0 0 0 0 0

CRC_INIT[31:0]

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

POL[31:0]

0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1

Refer to Section 2.2 on page 55 for the register boundary addresses.

RM0471 Rev 5 125/1202

125

Power control (PWR)

6 Power control (PWR)

RM0471

The devices require a V

DD operating voltage supply between 2.00 V and 3.6 V. Several independent supplies (V

DDA

, V

DDRF

) can be provided for specific peripherals:

 V

= 2.00 V to 3.6 V

DD is the external power supply for the I/Os, the system analog blocks such as reset, power management, internal clocks and low power regulator. It is provided externally through VDD pins.

 V

DDA

= 2.00 V to 3.6 V

DDA is the external analog power supply for A/D converters. The V

DDA voltage level is independent from the V

DD voltage and must preferably be connected to V

DD these peripherals are not used.

when

 V

DDRF

= 2.00 V to 3.6 V

DDRF is the external power supply for the Radio. It is provided externally through the

VDDRF pin, and must be connected to the same supply as V

 V

BAT

= 1.55 V to 3.6 V

BAT

is the power supply for RTC, external clock 32 kHz oscillator and backup registers

(through power switch) when V

DD is not present.

During power up and power down, the following power sequence is required:

 When V

< 1 V the other power supplies (V

During the power down V

DDA

) must remain below V

+ 0.3 V.

can temporarily become lower than the other supplies only if the energy provided to the MCU remains below 1 mJ. This allows the external decoupling capacitors to discharge with different time constants.

 When V

≥ 1 V all power supplies become independent.

An embedded linear voltage regulator is used to supply the internal digital power V

CORE

CORE is supplied by V

CORE

and V

. is the power supply for digital peripherals, SRAM1 and SRAM2. The Flash memory

126/1202 RM0471 Rev 5

RM0471

Figure 7. Power supply overview

V

Power control (PWR)

V

BAT

V

LP REG

V

RFLDO

V

BKP

MLDO

V

MAIN

> 1.4V

6.1.1 V

DDO

V

DDI

MS52634V1

Independent analog peripherals supply

To improve ADC conversion accuracy and to extend the supply flexibility, the analog peripherals have an independent power supply that can be separately filtered and shielded from noise on the PCB.

 The analog peripherals voltage supply input is available on a separate V

DDA

pin.

 An isolated supply ground connection is provided on V

SSA pin.

The V

DDA

supply voltage can be different from V

. The presence of V

DDA before enabling any of the analog peripherals supplied by V comparators, voltage reference buffer).

DDA

must be checked

(A/D converter,

When a single supply is used, V

DDA

can be externally connected to V

DD external filtering circuit in order to ensure a noise-free V

DDA

through the

reference voltage.

ADC reference voltage

DDA

is also the reference voltage for the ADC.

To retain the content of the Backup registers and supply the RTC function when V

DD turned off, the V

BAT battery or by another source.

is pin can be connected to an optional backup voltage supplied by a

The V

BAT

pin powers the RTC unit, the LSE oscillator and the PC14 to PC15 I/Os, allowing the RTC to operate even when the main power supply is turned off. The switch to the V

BAT supply is controlled by the power-down reset embedded in the Reset block.

RM0471 Rev 5 127/1202

169

Power control (PWR) RM0471

Note:

Warning: During t

RSTTEMPO

(temporization at V remains connected to V

BAT

During the startup phase, if V

startup) or after a PDR has been detected, the power switch between V

BAT

(refer to the datasheet for its value) and and V

is established in less than t

RSTTEMPO

> V

BAT

+ 0.6 V, a current may be injected into V

BAT through an internal diode connected between V

DD power switch (V

BAT

and the

If the power supply / battery connected to the V

BAT

pin cannot support this current injection, it is recommended to connect an external low-drop diode between this power supply and the V

BAT

pin.

If no external battery is used in the application, it is recommended to connect V

BAT externally to V

with a 100 nF external ceramic decoupling capacitor.

When the backup domain is supplied by V

DD following pins are available:

(analog switch connected to V

), the

 PC14 and PC15, which can be used as GPIO pins

 PC14 and PC15, which can be configured by RTC or LSE (refer to

Section 24.3: RTC functional description )

 PA0/RTC_TAMP2 when configured by the RTC as tamper pin

As the analog switch can transfer only a limited amount of current (3 mA), the use of GPIO

PC14 to PC15 in output mode is restricted: the speed must be limited to 2 MHz with a maximum load of 30 pF, and these I/Os cannot be used as current sources (e.g. to drive a

LED).

When the backup domain is supplied by V

BAT

(analog switch connected to V

is not present), the following functions are available:

BAT

because

 PC14 and PC15 can be controlled only by LSE (refer to

Section 24.3: RTC functional description

)

 PA0/RTC_TAMP2 when configured by the RTC as tamper pin

Backup domain access

After a system reset, the backup domain (RTC registers and backup registers) is protected against possible unwanted write accesses. To enable access to the backup domain, proceed as follows:

Set the DBP bit in the PWR control register 1 (PWR_CR1)

to enable access to the backup domain.

VBAT battery charging

When V

is present, it is possible to charge the external battery on VBAT through an internal resistance.

The VBAT charging is done either through a 5 k Ω resistor or through a 1.5 k Ω resistor, depending on the VBRS bit value in the

PWR control register 4 (PWR_CR4)

128/1202 RM0471 Rev 5

RM0471 Power control (PWR)

The battery charging is enabled by setting VBE bit in the PWR control register 4

(PWR_CR4)

, and automatically disabled in VBAT mode.

Two embedded linear voltage regulators supply all the digital circuitries, except for the

Standby circuitry and the backup domain.

The voltage regulators are always enabled after a reset. Depending on the application modes, the V

CORE regulator (LPR).

supply is provided either by the main regulator (MR) or by the low-power

 In Run, Sleep and Stop0 modes, both regulators are enabled and the main regulator

(MR) supplies full power to the V

CORE domain (core, memories and digital peripherals).

 In low-power run and low-power sleep modes, the main regulator is off and the low-power regulator (LPR) supplies low power to the V

CORE contents of the registers and internal SRAM1 and SRAM2.

domain, preserving the

 In Stop1 and Stop2 modes the main regulator is off and the low-power regulator (LPR) supplies low power to the V

CORE of internal SRAM1 and SRAM2.

domain, preserving the contents of the registers and



In Standby mode with SRAM2a content preserved (RRS bit is set in the PWR control register 3 (PWR_CR3) ), the main regulator (MR) is off and the low-power regulator

(LPR) provides the supply to SRAM2a only. The core and digital peripherals (except

Standby circuitry and backup domain), SRAM1 and SRAM2b are powered off.

 In Standby mode, both regulators are powered off. The contents of the registers and of

SRAM1 and SRAM2 is lost except for the Standby circuitry and the backup domain.

 In Shutdown mode, both regulators are powered off. When exiting from Shutdown mode, a power-on reset is generated. Consequently, the contents of the registers and of both SRAM1 and SRAM2 is lost, except for the backup domain.

6.2.1 Power-on reset (POR) / power-down reset (PDR) / brown-out reset

(BOR)

The device has an integrated power-on reset / power-down reset, coupled with a brown-out reset circuitry.

Five BOR thresholds can be selected through option bytes.

The BOR is active in all power modes except Shutdown mode, and cannot be disabled. The

BOR mechanism needs to be enabled, and can be disabled at any time if needed.

Reset mode

During power-on, the BOR keeps the device under reset until the supply voltage V

DD reaches the specified V

BORx

threshold. When V

DD drops below the selected threshold, a device reset is generated. When V

DD released and the system can start.

is above the V

BORx upper limit, the device reset is

For more details on the brown-out reset thresholds refer to the electrical characteristics section in the datasheet.

RM0471 Rev 5 129/1202

169

Power control (PWR)

V

Figure 8. Brown-out reset waveform

BORH

rise hysteresis

BORH

fall

RM0471

t

6.2.2 nPwr

MS44480V1

1. The reset temporization t

RSTTEMPO

is present only for the BOR lowest threshold (V

BOR0

Programmable voltage detector (PVD)

The PVD can be used to monitor the V

power supply by comparing it to a threshold selected by the PLS[2:0] bits in the

PWR control register 2 (PWR_CR2)

The PVD can also be used to monitor a voltage level on the PVD_IN pin. In this case the voltage level on PVD_IN is compared to the internal VREFINT level.

The PVD is enabled by setting the PVDE bit.

A PVDO flag is available, in the

PWR status register 2 (PWR_SR2)

, to indicate if V

or the voltage level on PVD_IN is higher or lower than the PVD threshold. This event is internally connected to the EXTI Line16 and can generate an interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated when V

DD drops below the PVD threshold and/or when V

or voltage level on PVD_IN

or voltage level on PVD_IN rises above the PVD threshold depending on EXTI Line16 rising/falling edge configuration. As an example, the service routine can perform emergency shutdown tasks.

130/1202 RM0471 Rev 5

RM0471 Power control (PWR)

V

, or

PVD_IN

PVD

rise

Figure 9. PVD thresholds hysteresis

PVD

fall

t

PVDO

PVDE

SW enable PDR reset

MS44481V1

Booting of the CPU2 is controlled by the C2BOOT bit in

PWR control register 4 (PWR_CR4)

Low-power mode, before booting the CPU2.

 Following reset the CPU2 is prevented from booting by the C2BOOT bit. The CPU2 boots only once the CPU1 has set the C2BOOT bit.

 When exiting from system low power modes STOP0, STOP1 or STANDBY the

C2BOOT bit controls the CPU2 booting.

– When C2BOOT = 1, after a system low power mode the CPU2 boots when it is woken up via a wakeup source.

– When C2BOOT = 0, after a system low power mode the CPU2 is prevented from booting. Instead on a CPU2 wakeup source the CPU1 is woken up via a C2HF. It is up to the CPU1 to boot the CPU2 by setting the C2BOOT bit.

RM0471 Rev 5 131/1202

169

Power control (PWR)

Figure 10. CPU2 boot options

Reset

CPU1 CRUN, CSLEEP,

CPU2 CSTOP (BOOT HOLD)

C2BOOT = 1

CPU1 CRUN or CSLEEP

CPU2 CRUN or CSLEEP

RM0471

RUN

LP-RUN

CPU1 CRUN or CSLEEP

CPU2 CSTOP

CPU1 CSTOP

CPU2 CRUN or CSLEEP

CPU1 CRUN or CSLEEP

CPU2 CSTOP (BOOT HOLD)

CPU1 CSTOP

STANDBY

CPU1 CSTOP

CPU2 CSTOP

STOP0

STOP1

STOP2

LP_STOP

Enter STANDBY

STANDBY

Wakeup CPU2 & C2BOOT = 1

MS44482V1

When the CPU2 is prevented from booting, the wakeup from Low-power mode boot procedure is the following:

 Before the CPU1 enters CSTOP mode it clears the C2BOOT bit.

 When CPU1 exits CSTOP:

– When the system remains in Run mode, it sets the C2BOOT bit, and subsequently processes the wakeup event.

– When the system exits from a low power mode from a CPU1 wakeup source, it initialize the system and sets the C2BOOT bit, and subsequently processes the wakeup event.

– When the system exits from a low power mode from the C2HF wakeup source, it initializes the system and set the C2BOOT bit, and subsequently goes back to

CSTOP.

132/1202 RM0471 Rev 5

RM0471 Power control (PWR)

 There is no special wakeup procedure for the CPU2. When the CPU2 wakes up, the system has been initialized by the CPU1. So the CPU2 can directly process the wakeup event.

When the system remains in Run mode (due to the Radio system) the CPU2 wakes up from

CSTOP mode independently from the C2BOOT setting.

By default, the microcontroller is in Run mode after a system or a power Reset and at least one CPU is in CRun mode executing code. Low-power modes are available to save power when the CPU does not need to be kept running, for example when it is waiting for an external event. The user has to select the mode that gives the best compromise between consumption, startup time and available wakeup sources.

The individual CPUs feature two low power modes, entered by the CPU when executing

WFI, WFE or on return from an exception handler when SLEEPONEXIT is enabled.

 CSleep mode: when the CPU enters low power mode and SLEEPDEEP is disabled,

Arm ® “sleep mode”.

 CStop mode: when the CPU enters low power mode and SLEEPDEEP is enabled,

Arm

“sleepdeep mode”.

The device features several low-power modes:



Sleep mode : CPU clock off, all peripherals including CPU core peripherals (among

them NVIC, SysTick) can run and wake up the CPU when an interrupt or an event occurs.



Low-power run mode (LP run)

: This mode is achieved when the system clock frequency is reduced below 2 MHz. The code is executed from the SRAM or from the

Flash memory. The regulator is in low-power mode to minimize the operating current.



Low-power sleep mode (LP sleep)

: This mode is entered from the Low-power run mode: CPU is off.



Stop0 mode ,

Stop1 mode

and Stop2 mode

: the content of SRAM1, SRAM2 and of all registers is retained. All clocks in the V

CORE

domain are stopped, the PLL, the MSI, the

HSI16 and the HSE are disabled. The LSI and the LSE can be kept running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with the wakeup capability can enable the HSI16 RC during the Stop mode to detect their wakeup condition.

In Stop2 mode, most of the V

CORE

domain is put in a lower leakage mode. Stop1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption compared with Stop2. In Stop0 mode, the main regulator remains ON, resulting in the fastest wakeup time but with much higher consumption.

The active peripherals and wakeup sources are the same as in Stop1 mode.

The system clock, when exiting from Stop0, Stop1 or Stop2 mode, can be either MSI up to 48 MHz or HSI16, depending on the software configuration.



Standby mode : V

CORE

SRAM2a contents: domain is powered off. However, it is possible to preserve the

– Standby mode with SRAM2a retention when bit RRS is set in the

PWR control register 3 (PWR_CR3) . In this case, SRAM2a is supplied by the low-power

regulator.

– Standby mode when bit RRS is cleared in the

PWR control register 3 (PWR_CR3)

RM0471 Rev 5 133/1202

169

Power control (PWR) RM0471

Note:

In this case the main regulator and the low-power regulator are powered off.

All clocks in the V

CORE

domain are stopped, the PLL, the MSI, the HSI16 and the HSE are disabled. The LSI and the LSE can be kept running.

The RTC can remain active (Standby mode with RTC, Standby mode without RTC).

The system clock, when exiting Standby modes, is HSI16.



Shutdown mode

: V

CORE domain is powered off. All clocks in the V

CORE

domain are stopped, the PLL, the MSI, the HSI16, the LSI and the HSE are disabled. The LSE can be kept running. The system clock, when exiting the Shutdown mode, is MSI at 4 MHz.

In this mode, the supply voltage monitoring is disabled and the product behavior is not guaranteed in case of a power voltage drop.

Stop, Standby, and Shutdown modes are only entered when both CPUs are in CStop mode.

In addition, the power consumption in Run mode can be reduced by slowing down the system clocks, and/or by gating the clocks to the APB and AHB peripherals when they are unused.

The system operation mode depend on the CPU1, the CPU2 and the Radio sub-system operating mode. The system enters a low power mode only when all three sub-systems allow it to do so.

After a system reset the CPU1 is in CRUN mode. The CPU2 boots only if enabled by the

CPU1 via the C2BOOT register bit. As long as the CPU1 does not boot the CPU2, the device operates as a single CPU system. The CPU1 can enter and wakeup from system low power modes on its own.

When CPU2 has boot, the CPU1, CPU2 and Radio sub-systems can enter and wakeup from system low power modes on their own. The different wakeup sources for the different sub-systems are detailed in

Table 21 .

Table 21. Sub-system low power wakeup sources

Wakeup source

EXTI

RTC

WKUP

RADIO

RFWAKEUP

CPU1 CPU2 Radio

From Stop modes From Stop modes

From Stop and Standby modes From Stop and Standby modes

Not available

From Stop and Standby modes From Stop and Standby modes

From Stop From Stop

Not available

From Stop and Standby modes From Stop and Standby modes

The system low power mode to enter depends on the allowed mode selected by both CPUs in the LPMS bits of

PWR control register 1 (PWR_CR1)

and

PWR CPU2 control register 1

(PWR_C2CR1)

. This is also valid when CPU2 is kept in hold by C2BOOT.

Figure 11

shows the operating modes state diagram. The CPU1, CPU2 and Radio sub-systems operate interdependently according to their own sub-system states. Each sub-system has its own wakeup sources, which allow it to wakeup from Stop and Standby modes. For the device to be in Stop, Standby or Shutdown mode, all three sub-systems need to be in CStop. When one sub-system enters CRun mode the device enters Run mode.

134/1202 RM0471 Rev 5

RM0471 Power control (PWR)

Figure 11. Low-power modes possible transitions

Sub-system modes Bus modes System modes

RUN

LP-RUN

Wakeup from STOP with CPU HOLD

CPU2 sub-system having allocated peripheral in the

HCLK1 domain

CPU1 CRUN or CSLEEP

CPU2 CRUN or CSLEEP

Radio CRUN or CSTOP

C2_wakeup

C1_wakeup

C1STOP

HCLK1 RUN

HCLK4 RUN

HCLK1 peripheral allocation

CPU1 CSTOP

CPU2 CRUN or CSLEEP

Radio CRUN or CSTOP reset

C2STOP

CPU1 CRUN or CSLEEP

CPU2 CSTOP

Radio CSTOP

HCLK1 RUN

HCLK4 RUN

C1_wakeup

C2STOP

CPU1 CRUN or CSLEEP

CPU2 CSTOP

Radio CRUN

HCLK1 RUN

HCLK4 RUN

C1_wakeup

C1STOP

CPU1 CSTOP

CPU2 CRUN or CSLEEP

Radio CRUN or CSTOP

HCLK1 STOP

C2_wakeup

HCLK4 RUN

C2_wakeup

HCLK1 peripheral delocation

C1STOP

CPU1 CSTOP

CPU2 CSTOP

Radio CRUN

HCLK1 STOP

HCLK4 RUN

Radio_wakeup

C2STOP

STOP0

STOP1

STOP2

LP-STOP

C1STOP Radio STOP

CPU1 CSTOP

CPU2 CSTOP

Radio CSTOP

HCLK1 STOP

HCLK4 STOP

C2STOP

Wakeup CPU1 from STM32-WKUP

STANDBY

Enter STANDBY

STANDBY

Wakeup from BLE-WKUP

Wakeup CPU2 from STM32-WKUP

Wakeup

SHUTDOWN

Enter SHUTDOWN

SHUTDOWN

MS44483V2

RM0471 Rev 5 135/1202

169

Power control (PWR) RM0471

Table 22. Low-power mode summary

Mode name Entry

Wakeup source

(1)

Wakeup system clock

Effect on clocks

Voltage regulator

MR LPR

Sleep

(Sleep-now or

Sleep-on-exit)

WFI or Return from ISR

WFE

Low-power run

Set LPR bit

Low-power sleep

Set LPR bit +

WFI or Return from ISR

Set LPR bit +

WFE

Stop0

Stop1

Stop2

Standby with

SRAM2a

Standby

Shutdown

Any interrupt

Wakeup event

Clear LPR bit

Any interrupt

Wakeup event

Same as before entering Sleep mode

Same as Low-power run clock

Same as before entering Low-power sleep mode

LPMS=”000” +

SLEEPDEEP bit

+ WFI or Return from ISR or WFE

LPMS=”001” +

SLEEPDEEP bit

+ WFI or Return from ISR or WFE

LPMS=”010” +

SLEEPDEEP bit

+ WFI or Return from ISR or WFE

Any EXTI line

(configured in the

EXTI registers).

Specific peripherals events

HSI16 when

STOPWUCK=1 in

RCC_CFGR.

MSI with the frequency before entering the Stop mode when

STOPWUCK=0.

LPMS=”011”+

Set RRS bit +

SLEEPDEEP bit

+ WFI or Return from ISR or WFE

WKUP pin edge,

RTC event,

LSECSS, external reset in

NRST pin,

IWDG reset

HSI16

LPMS=”011” +

Clear RRS bit +

SLEEPDEEP bit

+ WFI or Return from ISR or WFE

WKUP pin edge,

RTC event,

LSECSS, external reset in

NRST pin,

IWDG reset

LPMS=”1--” +

SLEEPDEEP bit

+ WFI or Return from ISR or WFE

WKUP pin edge,

RTC event, external reset in

NRST pin

MSI 4 MHz

CPU clock OFF

No effect on other clocks or analog clock sources

None

CPU clock OFF

No effect on other clocks or analog clock sources

All clocks OFF except LSI and LSE

All clocks OFF except LSE

OFF

OFF OFF

1. Refer to Table 23 .

136/1202 RM0471 Rev 5

RM0471 Power control (PWR)

Table 23. Functionalities depending on system operating mode (1)

Stop0 Stop1 Stop2 Standby Shutdow

Peripheral

CPU1

CPU2

Radio-system (BLE, 802)

Flash memory

SRAM1

SRAM2a

SRAM2b

Backup registers

Brown-out reset (BOR)

Programmable voltage detector (PVD)

DMA

High speed internal (HSI16)

Oscillator HSI48

High speed external (HSE)

Low speed internal (LSI)

Low speed external (LSE)

Multi-speed internal (MSI)

Y O

(4)

Y O

(4)

Y O

(4)

Y O

(4)

O O O O

O O O O O

O -

Y Y O O R

(5)

O O O O -

O O O O O

Y Y Y

(5)

Y Y

(3)

(2)

R -

Clock security system (CSS) O O O O -

Clock security system on LSE O O O O O O O O O O O O

RTC / Auto wakeup

Number of RTC tamper pins

USART1

I2C1

O O O O O O O O O O O O O O O

1 1 1 1 1

O O O O O

(6)

O O O O O

(7)

(6)

(7)

(6)

(7)

(6)

(7)

O 1

SPIx (x=1)

ADC1

Temperature sensor

Timers (TIMx)

Low-power timer 1 (LPTIM1)

Low-power timer 2 (LPTIM2)

RM0471 Rev 5 137/1202

169

Power control (PWR) RM0471

Table 23. Functionalities depending on system operating mode (1) (continued)

Stop0 Stop1 Stop2 Standby Shutdow

Peripheral

Independent watchdog (IWDG) O O O O O O O O O O O O

Window watchdog (WWDG) O O O O -

O O O O SysTick timer

True random number generator (RNG)

AES hardware accelerator

O -

CRC calculation unit

IPCC

HSEM

PKA

GPIOs

O -

O O O O

(8)

2 pins

(9)

(10)

pins

(9)

1. Legend: Y = Yes (enabled). O = Optional (disabled by default, can be enabled by software). R = Data retained.

- = Not available. Gray cells indicate Wakeup capability.

2. SRAM2a content needs to be retained via the PWR_CR3.RRS bit.

3. The SRAM2a content can optionally be retained when the PWR_CR3.RRS bit is set,

4. The SRAM clock can be gated on or off.

5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral that requested it. HSI16 is automatically put off when the peripheral does not need it anymore.

6. UART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.

7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

8. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.

9. The I/Os with wakeup from Standby/Shutdown capability are PA0 and PA2.

10. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

Debug mode

By default, the debug connection is lost if the application puts the MCU in Stop0, Stop1,

Stop2, Standby or Shutdown mode while the debug features are used. This is because the

CPU1 core is no longer clocked.

However, by setting some configuration bits in the DBGMCU_CR register, the software can be debugged even when using the low-power modes extensively. For more details refer to

Section 32.3.5: Debug and low power modes

138/1202 RM0471 Rev 5

RM0471 Power control (PWR)

Slowing down system clocks

In Run mode, the speed of the system clocks (SYSCLK, HCLK, PCLK) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down the peripherals before entering the Sleep mode.

For more details, refer to Section 7.4.3: RCC clock configuration register (RCC_CFGR)

Peripheral clock gating

In Run mode, the HCLK and PCLK for individual peripherals and memories can be stopped at any time to reduce the power consumption.

To further reduce the power consumption in Sleep mode, the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.

The peripheral clock gating is controlled by the RCC_AHBxENR and RCC_APBxENR registers.

Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting the corresponding bit in the RCC_AHBxSMENR and RCC_APBxSMENR registers.

To further reduce the consumption when the system is in Run mode, the regulator can be configured in low-power mode. In this mode, the system frequency must not exceed 2 MHz.

The Radio sub-system cannot be used in low-power Run mode.

Refer to the product datasheet for more details on voltage regulator and peripherals operating conditions.

I/O states in Low-power run mode

In Low-power run mode, all I/O pins keep the same state as in Run mode.

Entering the Low-power run mode

To enter the Low-power run mode, proceed as follows:

Optional: Jump into the SRAM and power-down the Flash memory by setting the FPDR bit in

PWR control register 1 (PWR_CR1)

and PWR CPU2 control register 1

(PWR_C2CR1)

2. Decrease the system clock frequency below 2 MHz.

3. Force the regulator in low-power mode by setting the LPR bit in the PWR control register 1 (PWR_CR1) .

Refer to Table 24

on how to enter the Low-power run mode.

Exiting the Low-power run mode

To exit the Low-power run mode, proceed as follows (refer to

Table 24 ):

Force the regulator in main mode by clearing the LPR bit in the PWR control register 1

(PWR_CR1)

2. Wait until REGLPF bit is cleared in the PWR status register 2 (PWR_SR2) .

3. Increase the system clock frequency.

RM0471 Rev 5 139/1202

169

Power control (PWR)

Low-power run mode

Mode entry

Mode exit

Wakeup latency

Table 24. Low-power run

Description

Decrease the system clock frequency below 2 MHz

LPR = 1

LPR = 0

Wait until REGLPF = 0

Increase the system clock frequency

Regulator wakeup time from low-power mode

RM0471

Low power modes are entered by the MCU by executing the WFI (Wait for Interrupt), or

WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in the CPU1 System control register is set on Return from ISR.

Entering Low-power mode through WFI or WFE is executed only if no interrupt is pending or no event is pending.

140/1202

From Sleep modes, and Stop modes the MCU exit Low-power mode depending on the way the mode was entered:

 If the WFI instruction or Return from ISR was used to enter the Low-power mode, any peripheral interrupt acknowledged by the NVIC can wake up the device.

 If the WFE instruction is used to enter the Low-power mode, the MCU exits the

Low-power mode as soon as an event occurs. The wakeup event can be generated either by an NVIC IRQ interrupt, or by an event.

– In the first case, when SEVONPEND = 0 in the CPU System control register, enabling an interrupt in the peripheral control register and in the NVIC. When the

MCU resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. Only NVIC interrupts with sufficient priority wakeup and interrupt the MCU.

When SEVONPEND = 1 in the CPU System control register, enabling an interrupt in the peripheral control register and optionally in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and when enabled the

NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. All NVIC interrupts wake up the MCU, even the disabled ones. Only enabled NVIC interrupts with sufficient priority wake up and interrupt the MCU.

– In the second case, configuring an EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bits corresponding to the event line is not set. It may be necessary to clear the interrupt flag in the peripheral.

From Standby and Shutdown modes the MCU exits Low-power mode through an external reset (NRST pin), an IWDG reset, a rising edge on one of the enabled WKUPx pins, or an

RTC event (see

Section 24: Real-time clock (RTC)

), or a Radio event (for Standby only).

RM0471 Rev 5

RM0471 Power control (PWR)

System mode

After waking up from Standby or Shutdown mode, program execution restarts in the same way as after a Reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.).

The system mode when the CPU wakes up from CStop mode can be determined from the

CnSTOPF and CnSBF in PWR extended status and status clear register (PWR_EXTSCR) .

CPU1

Table 25. CPU CSTOP wakeup vs. system operating mode

CPU2

CPU1 wakeup CPU2 wakeup

Run

Stop

Standby

N.A.

0 0 0

1 0 0

0 0 1

1 1 0

0 0 1

0 1 0

1 1 0

0 1 1

Others

0 Wakeup from Run

Wakeup from STOP, but system is already in Run due to CPU2

Wakeup from Run

Wakeup from STANDBY, but system is already in Run due to CPU2

Wakeup from Run

Wakeup from STANDBY, but system is already in Run due to CPU1

Wakeup from STANDBY followed by

STOP, but system is already in Run due to CPU2

Wakeup from Run

Wakeup from STOP (CPU2 still in

CSTOP)

Wakeup from STOP after the system has been in STANDBY (CPU2 still in

CSTOP)

Wakeup from STOP, but system is already in Run due to CPU1

Wakeup from STANDBY followed by

STOP, but system is already in Run due to CPU1

Wakeup from STOP (CPU1 still in

CSTOP)

Wakeup from STOP (CPU1 still in

CSTOP)

Wakeup from STOP (CPU2 is still in

CSTOP)

Wakeup from STOP after the system having been in STANDBY (CPU1 still in

CSTOP)

Wakeup from STANDBY (CPU2 still in

CSTOP)

Wakeup from STANDBY (CPU1 still in

CSTOP)

Not valid, does not occur

I/O states in Sleep mode

In Sleep mode, all I/O pins keep the same state as in Run mode.

Entering the Sleep mode

The Sleep mode is entered according to

Entering Low-power mode

, when the SLEEPDEEP

RM0471 Rev 5 141/1202

169

Power control (PWR)

6.4.6

RM0471 bit in the CPU System control register is cleared (see

Table 26).

Exiting the Sleep mode

The MCU exits from the Sleep mode (see

Table 26)

as indicated in

Exiting Low-power mode

Sleep-now mode

Mode entry

Mode exit

Wakeup latency

Table 26. Sleep mode

Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP = 0

– No interrupt (for WFI) or event (for WFE) is pending

Refer to the Cortex

System control register.

On return from ISR while:

– SLEEPDEEP = 0 and

– SLEEPONEXIT = 1

– No interrupt is pending

Refer to the Cortex

System control register.

If WFI or return from ISR was used for entry:

Interrupt: refer to Table 54: CPU1 vector table

and Table 55: CPU2 vector table

If WFE was used for entry and SEVONPEND = 0:

Wakeup event: refer to Section 13.5: Interrupt list

If WFE was used for entry and SEVONPEND = 1:

Interrupt even when disabled in NVIC: refer to Table 54: CPU1 vector table

and Table 55: CPU2 vector table

or Wakeup event: refer to Section 13.5:

Interrupt list

None

Low-power sleep mode (LP sleep)

Refer to the product datasheet for more details on voltage regulator and peripherals operating conditions.

I/O states in Low-power sleep mode

In Low-power sleep mode, all I/O pins keep the same state as in Run mode.

Entering the Low-power sleep mode

The Low-power sleep mode is entered from Low-power run mode as described in

Section 6.4.3

, when the SLEEPDEEP bit in the Cortex

System control register is cleared.

Refer to Table 27

for details on how to enter the Low-power sleep mode.

Exiting the Low-power sleep mode

The low-power Sleep mode is exited as described in

Section 6.4.4

. When exiting the

Low-power sleep mode by issuing an interrupt or an event, the MCU is in Low-power run mode.

Refer to Table 27

for details on how to exit the Low-power sleep mode.

142/1202 RM0471 Rev 5

RM0471 Power control (PWR)

Low-power sleep-now mode

Mode entry

Mode exit

Wakeup latency

Table 27. Low-power sleep

Description

Low-power sleep mode is entered from the Low-power run mode.

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP = 0

– No interrupt (for WFI) or event (for WFE) is pending

Refer to the Cortex ® System control register.

Low-power sleep mode is entered from the Low-power run mode.

On return from ISR while:

– SLEEPDEEP = 0 and

– SLEEPONEXIT = 1

– No interrupt is pending

Refer to the Cortex

System control register.

If WFI or Return from ISR was used for entry:

Interrupt: refer to

Table 54: CPU1 vector table and

Table 55: CPU2 vector table

If WFE was used for entry and SEVONPEND = 0:

Wakeup event: refer to Section 13.5: Interrupt list

If WFE was used for entry and SEVONPEND = 1:

Interrupt even when disabled in NVIC: refer to

Table 54: CPU1 vector table

and

Table 55: CPU2 vector table

Wakeup event: refer to Section 13.5: Interrupt list

After exiting the Low-power sleep mode, the MCU is in Low-power run mode.

None

The Stop0 mode is based on the CPU deep sleep mode combined with the peripheral clock gating. The voltage regulator is configured in main regulator mode. In Stop0 mode, all clocks in the V

CORE

domain are stopped; the PLL, the MSI, the HSI16 and the HSE oscillators are disabled. Some peripherals with wakeup capability (I2Cx (x=1), and USART1) can switch on the HSI16 to receive a frame, and switch off the HSI16 after receiving the frame if it is not a wakeup frame. In this case, the HSI16 clock is propagated only to the peripheral requesting it.

SRAM1, SRAM2 and register contents are preserved.

The BOR is always available in Stop0 mode. The consumption increases when thresholds higher than V

BOR0

are used.

I/O states in Stop0 mode

In the Stop0 mode, all I/O pins keep the same state as in the Run mode.

Entering the Stop0 mode

The Stop0 mode is entered according Section 6.4.3

, when the SLEEPDEEP bit in the

Cortex System control register is set (see Table 28

RM0471 Rev 5 143/1202

169

Power control (PWR) RM0471

If Flash memory programming is ongoing, the Stop0 mode entry is delayed until the operation is completed.

If an access to the APB domain is ongoing, The Stop0 mode entry is delayed until the APB access is finished.

In Stop0 mode, the following features can be selected by programming individual control bits:

 Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started, it cannot be stopped except by a reset. See

Section 25.3: IWDG functional description

 Real-time clock (RTC): this is configured by the RTCEN bit in the

RCC backup domain control register (RCC_BDCR)



Internal RC oscillator (LSI): this is configured by the LSIxON bit in the RCC control/status register (RCC_CSR) .



External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RCC backup domain control register (RCC_BDCR)

Some peripherals can be used in Stop0 mode and add consumption if they are enabled and clocked by LSI or LSE, or when they request the HSI16 clock, namely LPTIM1, LPTIM2,

I2Cx (x=1), USART1.

The PVD can be used in Stop0 mode. If not needed, it must be disabled by software to reduce power consumption.

The ADC and the temperature sensor can consume power during the Stop0 mode, unless they are disabled before entering this mode.

Exiting the Stop0 mode

The Stop0 mode is exit according to what indicated in Section 6.4.4

Refer to Table 28

for details on how to exit Stop0 mode.

When exiting Stop0 mode by issuing an interrupt or a wakeup event, the HSI16 oscillator is

selected as system clock if the bit STOPWUCK is set in RCC clock configuration register

(RCC_CFGR)

. The MSI oscillator is selected as system clock if the bit STOPWUCK is cleared. The wakeup time is shorter when HSI16 is selected as wakeup system clock. The

MSI selection enables wakeup at higher frequency, up to 48 MHz.

When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Stop0 mode with HSI16. By keeping the internal regulator ON during Stop0 mode, the consumption is higher but the startup time is reduced.

When exiting the Stop0 mode, the MCU is either in Run mode or in Low-power run mode if the bit LPR is set in the same register.

144/1202 RM0471 Rev 5

RM0471 Power control (PWR)

Stop0 mode

Mode entry

Mode exit

Wakeup latency

Table 28. Stop0 mode

Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP bit is set in Cortex System control register

– No interrupt (for WFI) or event (for WFE) is pending

– LPMS = “000” in PWR_CR1 and/or PWR_C2CR1 or higher

On Return from ISR while:

– SLEEPDEEP bit is set in Cortex System control register

– SLEEPONEXIT = 1

– No interrupt is pending

– LPMS = “000” in PWR_CR1 and/or PWR_C2CR1 or higher

Note: To enter Stop0 mode, all EXTI line pending bits (in

EXTI pending register

(EXTI_PR1)

, and EXTI pending register (EXTI_PR2)

), and the peripheral flags generating wakeup interrupts must be cleared. Otherwise, the Stop0 mode entry procedure is ignored and program execution continues.

If WFI or Return from ISR was used for entry:

Any EXTI line configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). The interrupt source can be external

interrupts or peripherals with wakeup capability. Refer to Table 54: CPU1 vector table

and Table 55: CPU2 vector table .

If WFE was used for entry and SEVONPEND = 0:

Any EXTI line configured in event mode. Refer to Section 13.5: Interrupt list .

If WFE was used for entry and SEVONPEND = 1:

Any EXTI line configured in Interrupt mode (even if the corresponding EXTI

Interrupt vector is disabled in the NVIC). The interrupt source can be external

interrupts or peripherals with wakeup capability. Refer to Table 54: CPU1 vector table

and Table 55: CPU2 vector table .

Wakeup event: refer to Section 13.5: Interrupt list

Longest wakeup time between: MSI or HSI16 wakeup time and Flash memory wakeup time from Stop0 mode.

The Stop1 mode is the same as Stop0 mode except that the main regulator is OFF, and only the low-power regulator is ON. Stop1 mode can be entered from Run mode and from

Low-power run mode.

Refer to Table 29

for details on how to enter and exit Stop1 mode.

RM0471 Rev 5 145/1202

169

Power control (PWR) RM0471

Stop1 mode

Mode entry

Mode exit

Wakeup latency

Table 29. Stop1 mode

Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP bit is set in Cortex System control register

– No interrupt (for WFI) or event (for WFE) is pending

– LPMS = “001” in PWR_CR1 and/or PWR_C2CR1 or higher

On Return from ISR while:

– SLEEPDEEP bit is set in Cortex System control register

– SLEEPONEXIT = 1

– No interrupt is pending

– LPMS = “001” in PWR_CR1 and/or PWR_C2CR1 or higher

Note: To enter Stop1 mode, all EXTI line pending bits (in EXTI pending register

(EXTI_PR1)

, and EXTI pending register (EXTI_PR2) ), and the peripheral

flags generating wakeup interrupts must be cleared. Otherwise, the Stop1 mode entry procedure is ignored and program execution continues.

If WFI or Return from ISR was used for entry:

Any EXTI line configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). The interrupt source can be external

interrupts or peripherals with wakeup capability. Refer to Table 54: CPU1 vector table

and Table 55: CPU2 vector table

If WFE was used for entry and SEVONPEND = 0:

Any EXTI line configured in event mode. Refer to Section 13.5: Interrupt list .

If WFE was used for entry and SEVONPEND = 1:

Any EXTI line configured in Interrupt mode (even if the corresponding EXTI

Interrupt vector is disabled in the NVIC). The interrupt source can be external

interrupts or peripherals with wakeup capability. Refer to Table 54: CPU1 vector table

and Table 55: CPU2 vector table

Wakeup event: refer to Section 13.5: Interrupt list .

Longest wakeup time between: MSI or HSI16 wakeup time and regulator wakeup time from Low-power mode + Flash memory wakeup time from Stop1 mode.

Note:

The Stop2 mode is based on the CPU deepsleep mode combined with peripheral clock gating. In Stop2 mode, all clocks in the V

CORE

HSI16 and the HSE oscillators are disabled.

domain are stopped, the PLL, the MSI, the

SRAM1, SRAM2 and register contents are preserved.

The BOR is always available in Stop2 mode. The consumption is increased when thresholds higher than V

BOR0

are used.

The comparators, LPUART and LPTIM1 outputs are forced to low speed (OSPEEDy = 00) during the Stop2 mode.

I/O states in Stop2 mode

In the Stop2 mode, all I/O pins keep the same state as in the Run mode.

146/1202 RM0471 Rev 5

RM0471 Power control (PWR)

Entering Stop2 mode

The Stop2 mode is entered as described in

Section 6.4.3

, when the SLEEPDEEP bit in the

Cortex System control register is set (see Table 30

Stop2 mode can only be entered from Run mode. It is not possible to enter Stop2 mode from the Low-power run mode.

If Flash memory programming is ongoing, the Stop2 mode entry is delayed until the memory access is finished.

If an access to the APB domain is ongoing, The Stop2 mode entry is delayed until the APB access is finished.

In Stop2 mode, the following features can be selected by programming individual control bits:

 Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. See

Section 25.3: IWDG functional description

 real-time clock (RTC): this is configured by the RTCEN bit in the

RCC backup domain control register (RCC_BDCR)



Internal RC oscillator (LSI): this is configured by the LSIxON bit in the RCC control/status register (RCC_CSR) .



External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RCC backup domain control register (RCC_BDCR)

Some peripherals can be used in Stop2 mode and add consumption if they are enabled and clocked by LSI or LSE, or when they request the HSI16 clock, namely LPTIM1.

The PVD can be used in Stop2 mode. If not needed, it must be disabled by software to reduce power consumption.

The ADC and the temperature sensor can consume power during Stop2 mode, unless they are disabled before entering this mode.

All the peripherals that cannot be enabled in Stop2 mode must be either disabled by clearing the Enable bit in the peripheral itself, or put under reset state by setting the corresponding bit in the



RCC AHB1 peripheral reset register (RCC_AHB1RSTR)



RCC AHB2 peripheral reset register (RCC_AHB2RSTR)



RCC AHB3 and AHB4 peripheral reset register (RCC_AHB3RSTR)



RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1)



RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2)



RCC APB2 peripheral reset register (RCC_APB2RSTR)



RCC APB3 peripheral reset register (RCC_APB3RSTR)

Exiting Stop2 mode

The Stop2 mode is exit according

Section 6.4.4

(see

Table 30 ).

When exiting Stop2 mode by issuing an interrupt or a wakeup event, the HSI16 oscillator is

selected as system clock if the bit STOPWUCK is set in RCC clock configuration register

(RCC_CFGR)

. The MSI oscillator is selected as system clock if the bit STOPWUCK is cleared. The wakeup time is shorter when HSI16 is selected as wakeup system clock. The

MSI selection allows wakeup at higher frequency, up to 48 MHz.

RM0471 Rev 5 147/1202

169

Power control (PWR) RM0471

When exiting the Stop2 mode, the MCU is in Run mode (Range 1 or Range 2 depending on

VOS bit in PWR_CR1).

Stop2 mode

Table 30. Stop2 mode

Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP bit is set in Cortex System control register

– No interrupt (for WFI) or event (for WFE) is pending

– LPMS = “010” in PWR_CR1 and/or PWR_C2CR1 or higher

Mode entry

Mode exit

Wakeup latency

On return from ISR while:

– SLEEPDEEP bit is set in Cortex System control register

– SLEEPONEXIT = 1

– No interrupt is pending

– LPMS = “010” in PWR_CR1 and/or PWR_C2CR1 or higher

Note: To enter Stop2 mode, all EXTI line pending bits in

EXTI pending register

(EXTI_PR1)

, and

EXTI pending register (EXTI_PR2) ), and the peripheral

flags generating wakeup interrupts must be cleared. Otherwise, the Stop mode entry procedure is ignored and program execution continues.

If WFI or Return from ISR was used for entry:

Any EXTI line configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). The interrupt source can be external

interrupts or peripherals with wakeup capability. Refer to Table 54: CPU1 vector table and

Table 55: CPU2 vector table .

If WFE was used for entry and SEVONPEND = 0:

Any EXTI line configured in event mode. Refer to Section 13.5: Interrupt list .

If WFE was used for entry and SEVONPEND = 1:

Any EXTI line configured in Interrupt mode (even if the corresponding EXTI

Interrupt vector is disabled in the NVIC). The interrupt source can be external

interrupts or peripherals with wakeup capability. Refer to Table 54: CPU1 vector table and

Table 55: CPU2 vector table .

Any EXTI line configured in event mode. Refer to Section 13.5: Interrupt list .

Longest wakeup time between: MSI or HSI16 wakeup time and regulator wakeup time from Low-power mode + Flash wakeup time from Stop2 mode.

The Standby mode makes possible to achieve the lowest power consumption with BOR. It is based on the CPU deepsleep mode, with the voltage regulators disabled (except when

SRAM2 content is preserved). The PLL, the HSI16, the MSI and the HSE oscillators are also switched off.

SRAM1 and register contents are lost except for registers in the Backup domain and

Standby circuitry (see Figure 7

). SRAM2 content can be preserved if the bit RRS is set in the

PWR control register 3 (PWR_CR3)

. In this case the Low-power regulator is ON and provides the supply to SRAM2 only.

The BOR is always available in Standby mode. The consumption is increased when thresholds higher than V

BOR0 are used.

148/1202 RM0471 Rev 5

RM0471 Power control (PWR)

I/O states in Standby mode

In the Standby mode, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx registers (x=A,B,C,E,H)), or with a pull-down (refer to PWR_PDCRx registers

(x=A,B,C,E,H)), or can be kept in analog state.

The RTC outputs on PC14 and PC15 used for LSE are functional. Two wakeup pins

(WKUPx, x=1,4) and the RTC tamper are available.

Entering Standby mode

The Standby mode is entered according

Section 6.4.3

, when the SLEEPDEEP bit in the

Cortex System control register is set.

Refer to Table 31

for details on how to enter Standby mode.

In Standby mode, the following features can be selected by programming individual control bits:

 Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a reset. See

Section 25.3: IWDG functional description

 Real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR).

 Internal RC oscillator (LSI): this is configured by the LSIxON bit in the Control/status register (RCC_CSR).

 External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR)

Exiting Standby mode

The Standby mode is exit according Section 6.4.4

. The SBF status flag in the

PWR control register 3 (PWR_CR3)

indicates that the MCU was in Standby mode. All registers are reset

after wakeup from Standby except for PWR control register 3 (PWR_CR3) .

Refer to Table 31

for more details on how to exit Standby mode.

Standby mode

Mode entry

Table 31. Standby mode

Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP bit is set in Cortex System control register

– No interrupt (for WFI) or event (for WFE) is pending

– LPMS = “011” in PWR_CR1 and/or PWR_C2CR1 or higher

– WUFx bits are cleared in power status register 1 (PWR_SR1)

On return from ISR while:

– SLEEPDEEP bit is set in Cortex System control register

– SLEEPONEXIT = 1

– No interrupt is pending

– LPMS = “011” in PWR_CR1 and/or PWR_C2CR1 or higher

– WUFx bits are cleared in power status register 1 (PWR_SR1)

The RTC flag corresponding to the chosen wakeup source (RTC Alarm A, RTC

Alarm B, RTC wakeup, tamper or timestamp flags) is cleared.

RM0471 Rev 5 149/1202

169

Power control (PWR) RM0471

Standby mode

Table 31. Standby mode (continued)

Description

Mode exit

WKUPx pin edge, RTC event, external Reset in NRST pin, IWDG Reset, BOR reset

Wakeup latency Reset phase

The Shutdown mode allows to achieve the lowest power consumption. It is based on the deepsleep mode, with the voltage regulator disabled. The V

CORE

domain is consequently powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off.

SRAM1, SRAM2 and register contents are lost except for registers in the Backup domain.

The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported.

I/O states in Shutdown mode

In the Shutdown mode, the I/Os can be configured either with a pull-up (refer to

PWR_PUCRx registers (x=A,B,C,E,H)), or with a pull-down (refer to PWR_PDCRx registers

(x=A,B,C,E,H)), or can be kept in analog state.

However this configuration is lost when exiting the Shutdown mode due to the power-on reset.

PC14 and PC15 used for LSE are also functional. Two wakeup pins (WKUPx, x=1,4) and the RTC tamper are available.

Entering Shutdown mode

The Shutdown mode is entered according

Entering Low-power mode , when the

SLEEPDEEP bit in the Cortex System control register is set.

Refer to Table 32

for details on how to enter Shutdown mode.

In Shutdown mode, the following features can be selected by programming individual control bits:

 Real-time clock (RTC): this is configured by the RTCEN bit in the

RCC backup domain control register (RCC_BDCR) . Caution: in case of V

DD lost.

power-down the RTC content is



External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RCC backup domain control register (RCC_BDCR)

Exiting Shutdown mode

The Shutdown mode is exit according

Exiting Low-power mode

. A power-on reset occurs when exiting from Shutdown mode. All registers (except for the ones in the Backup domain) are reset after wakeup from Shutdown.

Refer to Table 32

for more details on how to exit Shutdown mode.

150/1202 RM0471 Rev 5

RM0471 Power control (PWR)

Shutdown mode

Mode entry

Mode exit

Wakeup latency

Table 32. Shutdown mode

Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP bit is set in Cortex System control register

– No interrupt (for WFI) or event (for WFE) is pending

– LPMS = “1XX” in PWR_CR1 and PWR_C2CR1

– WUFx bits are cleared in power status register 1 (PWR_SR1)

On return from ISR while:

– SLEEPDEEP bit is set in Cortex System control register

– SLEEPONEXT = 1

– No interrupt is pending

– LPMS = “1XX” in PWR_CR1 and PWR_C2CR1

– WUFx bits are cleared in power status register 1 (PWR_SR1)

The RTC flag corresponding to the chosen wakeup source (RTC Alarm A,

RTC Alarm B, RTC wakeup, tamper or timestamp flags) is cleared.

WKUPx pin edge, RTC event, external Reset in NRST pin

Reset phase

6.4.12 Auto wakeup from Low-power mode

The RTC can be used to wakeup the MCU from Low-power mode without depending on an external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for waking up from Stop (0, 1 or 2) or Standby mode at regular intervals. For this purpose, two of the three alternative RTC clock sources can be selected by programming the

RTCSEL[1:0] bits in the

RCC backup domain control register (RCC_BDCR) :

 Low-power 32.768 kHz external crystal oscillator (LSE OSC)

This clock source provides a precise time base with very low-power consumption.

 Low-power internal RC oscillator (LSI)

This oscillator is designed to add minimum power consumption.

To wakeup from Stop mode with an RTC alarm event, it is necessary to:

 Configure the EXTI Line 18 to be sensitive to rising edge

 Configure the RTC to generate the RTC alarm

To wakeup from Standby mode, there is no need to configure the EXTI Line 18.

To wakeup from Stop mode with an RTC wakeup event, it is necessary to:

 Configure the EXTI Line 20 to be sensitive to rising edge

 Configure the RTC to generate the RTC alarm

To wakeup from Standby mode, there is no need to configure the EXTI Line 20.

RM0471 Rev 5 151/1202

169

Power control (PWR)

6.5 Real time radio information

The PWR provides flags indicating the real time operation on the radio:

 IEEE802.15.4 radio activity end interrupt flag

 BLE radio activity end interrupt flag

 Critical radio phase flag

 Critical radio phase end interrupt flag

These flags may be used by the CPU1 to determine the radio activity.

The basic timing relation for the different flags is shown in

Figure 11 .

Figure 12. Real time radio activity flags

802AF

C802AF

BLEAF

CBLEAF

CRPEF

CCRPEF

CRPF

Cortex

-M0+ CCRPF

Radio stop Radio activity

RM0471

Radio stop

MS44484V1

When enabled, the radio activity end interrupt flag 802AF indicates the end of an

IEEE802.15.4 radio activity period, and is generated when the radio enters Cstop mode.

When enabled, the radio activity end interrupt flag BLEAF indicates the end of a BLE radio activity period, and is generated when the radio enters Cstop mode.

The critical radio phase flag indicates the critical real time phase of the radio, where access to the Flash memory must not be blocked by erase or program operations (all erase and program operations are suspended by the CPU2 in the Flash memory interface). The end of the critical radio phase may be triggered by the CPU2 clearing the critical radio phase flag

CRPF, and is eventually cleared at the end of the IEEE802.15.4 or BLE radio activity.

When enabled, the critical radio phase end interrupt flag CRPEF indicates the end of a radio critical phase, and is generated when the radio critical phase ends.

152/1202 RM0471 Rev 5

RM0471 Power control (PWR)

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

6.6.1

Res.

PWR control register 1 (PWR_CR1)

Address offset: 0x000

Reset value: 0x0000 0200. This register is reset after wakeup from Standby mode, except for bits [2:0].

Res.

LPR rw

Res.

DBP rw

Res.

5 4

FPDS FPDR rw rw

Res.

2 rw

LPMS[2:0] rw

0 rw

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 LPR : Low-power run

When this bit is set, the regulator is switched from main mode (MR) to low-power mode

(LPR).

Note: Stop2 mode cannot be entered when LPR bit is set. Stop1 is entered instead.

Bits 13:9 Reserved, must be kept at reset value.

Bit 8 DBP : Disable backup domain write protection

In reset state, the RTC and backup registers are protected against parasitic write access.

This bit must be set to enable write access to these registers.

0: Access to RTC and Backup registers disabled

1: Access to RTC and Backup registers enabled

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 FPDS : Flash memory power down mode during LPSleep for CPU1

This bit selects whether the Flash memory is in power down mode or idle mode when both

CPUs are in Sleep mode. Flash memory is set in power down mode only when the system is in LPSleep mode and the PWR_C2CR1.FPDS bit from CPU2 also allows this.

0: Flash memory in Idle mode when system is in LPSleep mode

1: Flash memory in power down mode when system is in LPSleep mode

Bit 4 FPDR : Flash memory power down mode during LPRun for CPU1

This bit can only be written to 1 after unlocking this register bit, by first writing (code 0xC1B0) into this register (when writing the code, the register bits are not updated). Selects whether the Flash memory is in power down mode or idle mode when in LPRun mode. (Flash memory can only be in power down mode when code is executed from SRAM). Flash memory is set in power down mode only when the system is in LPRun mode, and the

PWR_C2CR1.FPDR bit from CPU2 too allows so.

0: Flash memory in Idle mode when system is in LPRun mode

1: Flash memory in power down mode when system is in LPRun mode

Bit 3 Reserved, must be kept at reset value.

RM0471 Rev 5 153/1202

169

Power control (PWR) RM0471

Bits 2:0 LPMS[2:0] : Low-power mode selection for CPU1

These bits are not reset when exiting Standby mode.

These bits select the low-power mode allowed when CPU1 enters the deepsleep mode. The entered system low-power mode depends also upon the PWR_C2CR1.LPMS allowed low-power mode from CPU2.

000: Stop0 mode

001: Stop1 mode

010: Stop2 mode

011: Standby mode

1xx: Shutdown mode

Note: If LPR bit is set, Stop2 mode cannot be selected and Stop1 mode must be entered instead of Stop2.

In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR_CR3.

6.6.2

Res.

PWR control register 2 (PWR_CR2)

Address offset: 0x004

Reset value: 0x0000 0000. This register is reset when exiting the Standby mode.

Res.

Res

Res.

3 rw

PLS[2:0] rw

1 rw

PVDE rw

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:1 PLS[2:0] : Programmable voltage detector level selection.

These bits select the voltage threshold detected by the Programmable voltage detector:

000: V

PVD0

~ 2.0 V

001: V

PVD1

~ 2.2 V

010: V

PVD2

~ 2.4 V

011: V

PVD3

~ 2.5 V

100: V

PVD4

~ 2.6 V

101: V

PVD5

~ 2.8 V

110: V

PVD6

~ 2.9 V

111: External input analog voltage PVD_IN (compared internally to V

DDA

PVD_IN input must be configured in analog mode in the GPIO register.

). The I/O used as

Note: These bits are write-protected when the bit PVDL (PVD lock) is set in the

SYSCFG_CBR register, they are reset only by a system reset.

Bit 0 PVDE : Programmable voltage detector enable

0: Programmable voltage detector disabled

1: Programmable voltage detector enabled

Note: This bit is write-protected when bit PVDL (PVD lock) is set in the SYSCFG_CBR register. This bit is reset only by a system reset.

154/1202 RM0471 Rev 5

RM0471 Power control (PWR)

6.6.3

Res.

PWR control register 3 (PWR_CR3)

Address offset: 0x008

Reset value: 0x0000 8000. This register is not reset when exiting Standby modes.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Res.

26 25

Res.

23 22 21

Res.

EIWUL EC2H E802A EBLEA ECRPE APC RRS rw

14 rw

13 rw

12 rw

11 rw

10 rw

9 rw

EBORH

SMPSFB rw

7 6 5

Res.

4 3 2

Res.

EWUP4 Res.

1 0

Res.

EWUP1 rw

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 EIWUL : Enable internal wakeup line for CPU1

0: Internal wakeup line interrupt to CPU1 disabled

1: Internal wakeup line interrupt to CPU1 enabled

Bit 14 EC2H : Enable CPU2 Hold interrupt for CPU1

Enable CPU2 kept in hold, due to C2BOOT, interrupt to CPU1.

0: Interrupt to CPU1 disabled

1: interrupt to CPU1 enabled

Bit 13 E802A : Enable 802.15.4 end of activity interrupt for CPU1

0: Interrupt to CPU1 disabled

1: interrupt to CPU1 enabled

Bit 12 EBLEA : Enable BLE end of activity interrupt for CPU1

0: Interrupt to CPU1 disabled

1: interrupt to CPU1 enabled

Bit 11 ECRPE : Enable critical radio phase end of activity interrupt for CPU1

0: Interrupt to CPU1 disabled

1: interrupt to CPU1 enabled

Bit 10 APC : Apply pull-up and pull-down configuration from CPU1

When this bit for CPU1 or the PWR_C2CR3.APC bit for CPU2 is set, the I/O pull-up and pulldown configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied.

When both bits are cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os.

Bit 9 RRS : SRAM2a retention in Standby mode

0: SRAM2a powered off in Standby mode (content is lost).

1: SRAM2a powered by the low-power regulator in Standby mode (content is kept).

Bit 8 EBORHSMPSFB : Enable BORH interrupts for CPU1

0: Interrupts BORHF to CPU1 disabled

1: interrupts BORHF to CPU1 enabled

Bits 7:4 Reserved, must be kept at reset value.

RM0471 Rev 5 155/1202

169

Power control (PWR) RM0471

Bit 3 EWUP4 : Enable Wakeup pin WKUP4 for CPU1

When this bit is set, the external wakeup pin WKUP4 is enabled and triggers an interrupt and wakeup from Stop, Standby or Shutdown event when a rising or a falling edge occurs to

CPU1. The active edge is configured via the WP4 bit in the

PWR control register 4

(PWR_CR4)

Bits 2:1 Reserved, must be kept at reset value.

Bit 0 EWUP1 : Enable Wakeup pin WKUP1 for CPU1

When this bit is set, the external wakeup pin WKUP1 is enabled and triggers an interrupt and wakeup from Stop, Standby or Shutdown event when a rising or a falling edge occurs to

CPU1. The active edge is configured via the WP1 bit in the

PWR control register 4

(PWR_CR4)

6.6.4

Res.

PWR control register 4 (PWR_CR4)

Address offset: 0x00C

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Res.

15 14

C2BOOT Res.

Res.

VBRS rw

VBE rw

Res.

WP4 rw

Res.

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 C2BOOT : Boot CPU2 after reset or wakeup from Stop or Standby modes.

0: CPU2 does not boot after reset or wakeup from Stop or Standby modes.

1: CPU2 boots after wakeup from Stop or Standby modes.

Bits 14:10 Reserved, must be kept at reset value.

Bit 9 VBRS : V

BAT

battery charging resistor selection

0: Charge V

BAT

through a 5 k Ω resistor

1: Charge V

BAT

through a 1.5 k Ω resistor

Bit 8 VBE : V

BAT

battery charging enable

0: V

BAT

battery charging disabled

1: V

BAT

battery charging enabled

Bits 7:4 Reserved, must be kept at reset value.

Bit 3 WP4 : Wakeup pin WKUP4 polarity

This bit defines the polarity used for an event detection on external wake-up pin, WKUP4

0: Detection on high level (rising edge)

1: Detection on low level (falling edge)

Bits 2:1 Reserved, must be kept at reset value.

WP1 rw

156/1202 RM0471 Rev 5

RM0471 Power control (PWR)

Bit 0 WP1 : Wakeup pin WKUP1 polarity

This bit defines the polarity used for an event detection on external wake-up pin, WKUP1

0: Detection on high level (rising edge)

1: Detection on low level (falling edge)

6.6.5

Res.

PWR status register 1 (

PWR_SR1

)

Address offset: 0x010

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes.

Access: Two additional APB cycles are needed to read this register vs. a standard APB read.

Res.

15 14 13

WUFI C2HF 802AF r r

BLE

AF r

CRPEF r

10 9

BLE

WUF r

8 r

BORHF Res.

Res.

4 3 2

Res.

WUF4 Res.

1 0

Res.

WUF1 r r

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 WUFI : Internal wakeup interrupt flag

This bit is set when a wakeup is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared.

Bit 14 C2HF : CPU2 Hold interrupt flag

This bit is set when a CPU2 wakeup is detected when C2BOOT = 0. It is cleared by

PWR_SCR.CC2HF.

Bit 13 802AF : 802.15.4 end of activity interrupt flag

This bit is set when a 802.15.4 activity ends. It is cleared by PWR_SCR.C802AF.

Bit 12 BLEAF : BLE end of activity interrupt flag

This bit is set when a BLE activity ends. It is cleared by PWR_SCR.CBLEAF.

Bit 11 CRPEF : Enable critical radio phase end of activity interrupt flag

This bit is set when Radio phase activity ends. It is cleared by PWR_SCR.CCRPEF.

Bit 10 802WUF 802.15.4 wakeup interrupt flag

This bit is set when a wakeup is detected on the 802.15.4 line. It is cleared by

PWR_SCR.C802WUF.

Bit 9 BLEWUF BLE wakeup interrupt flag

This bit is set when a wakeup is detected on the BLE line. It is cleared by

PWR_SCR.CBLEWUF.

Bit 8 BORHF : BORH interrupt flag

This bit is set when the V

PWR_SCR.CBORHF.

rises above the BORH threshold. It is cleared by

Bits 7:4 Reserved, must be kept at reset value.

RM0471 Rev 5 157/1202

169

Power control (PWR) RM0471

Bit 3 WUF4 : Wakeup flag 4

This bit is set when a wakeup event is detected on wakeup pin,WKUP4. It is cleared by writing ‘1’ in the CWUF4 bit of the

PWR status clear register (PWR_SCR) .

Bits 2:1 Reserved, must be kept at reset value.

Bit 0 WUF1 : Wakeup flag 1

This bit is set when a wakeup event is detected on wakeup pin, WKUP1. It is cleared by writing ‘1’ in the CWUF1 bit of the

PWR status clear register (PWR_SCR) .

6.6.6

Res.

PWR status register 2 (PWR_SR2)

Address offset: 0x014

Reset value: 0x0000 0002. This register is partially reset when exiting Standby/Shutdown modes.

Res.

23 22 21

Res.

20 19 18

Res.

11 10 9 8 7 6 5

PVDO Res.

REGLPF REGLPS Res.

Res.

r r r

4 3 2

Res.

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 PVDO : Programmable voltage detector output

0: V

1: V

or voltage level on PVD_IN is above the selected PVD threshold

or voltage level on PVD_IN is below the selected PVD threshold

Bit 10 Reserved, must be kept at reset value.

Bit 9 REGLPF : Low-power regulator flag

This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits from the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode.

A polling on this bit must be done before increasing the product frequency.

This bit is cleared by hardware when the regulator is ready.

0: The regulator is ready in main mode (MR)

1: The regulator is in low-power mode (LPR)

Bit 8 REGLPS : Low-power regulator started

This bit provides the information whether the low-power regulator is ready after a power-on reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wakeup from Standby mode time may be increased.

0: The low-power regulator is not ready

1: The low-power regulator is ready

Bits 7:0 Reserved, must be kept at reset value.

6.6.7 PWR status clear register (PWR_SCR)

Address offset: 0x018

Reset value: 0x0000 0000

158/1202 RM0471 Rev 5

RM0471 Power control (PWR)

Res.

Access: Three additional APB cycles are needed to write this register vs. a standard APB write.

Res.

15 14

Res.

CC2HF w

C802

AF w

CFBLE

AF w

CCRP

EF w

C802

WUF w

CBLE

WUF w

CBORH

F w

Res.

4 3 2

Res.

CWUF4 Res.

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 CC2HF : Clear CPU2 Hold interrupt flag

Setting this bit clears the C2HF flag in the PWR_SR1. This bit is always read 0.

Bit 13 C802AF : Clear 802.15.4 end of activity interrupt flag

Setting this bit clears the 802AF flag in the PWR_SR1. This bit is always read 0.

Bit 12 CBLEAF : Clear BLE end of activity interrupt flag

Setting this bit clears the BLEAF flag in the PWR_SR1. This bit is always read 0.

Bit 11 CCRPEF : Clear critical radio phase end of activity interrupt flag

Setting this bit clears the CRPEF flag in the PWR_SR1. This bit is always read 0.

Bit 10 C802WUF Clear 802.15.4 wakeup interrupt flag

Setting this bit clears the 802WUF flag in the PWR_SR1. This bit is always read 0.

Bit 9 CBLEWUF Clear BLE wakeup interrupt flag

Setting this bit clears the BLEWUF flag in the PWR_SR1. This bit is always read 0.

Bit 8 CBORHF : Clear BORH interrupt flag

Setting this bit clears the SBORHF flag in the PWR_SR1. This bit is always read 0.

Bits 7:4 Reserved, must be kept at reset value.

Bit 3 CWUF4 : Clear wakeup flag 4

Setting this bit clears the WUF4 flag in the PWR_SR1 register.

Bits 2:1 Reserved, must be kept at reset value.

Bit 0 CWUF1 : Clear wakeup flag 1

Setting this bit clears the WUF1 flag in the PWR_SR1 register.

1 0

Res.

CWUF1 w

6.6.8 PWR Port A pull-up control register (PWR_PUCRA)

Address offset: 0x020

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

RM0471 Rev 5 159/1202

169

Power control (PWR) RM0471

Res.

15 14 13 12 11 10

PU15 PU14 PU13 PU12 PU11 PU10 rw rw rw rw rw rw

PU9 rw

PU8 rw

PU7 rw

PU6 rw

PU5 rw

PU4 rw

PU3 rw

PU2 rw

PU1 rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy : Port A pull-up bit y (y=0...15)

When set, this bit activates the pull-up on Px[y] when one of the APC bits is set in PWR control register 3 (PWR_CR3)

and in PWR CPU2 control register 3 (PWR_C2CR3) . The

pull-up is not activated if the corresponding PDy bit is also set.

PU0 rw

6.6.9

Res.

PWR Port A pull-down control register (PWR_PDCRA)

Address offset: 0x024

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Res.

15 14 13 12 11 10

PD15 PD14 PD13 PD12 PD11 PD10 rw rw rw rw rw rw

PD9 rw

PD8 rw

PD7 rw

PD6 rw

PD5 rw

PD4 rw

PD3 rw

PD2 rw

PD1 rw

PD0 rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy : Port A pull-down bit y (y=0...15)

When set, this bit activates the pull-down on PA[y] when one of the APC bits is set in

PWR control register 3 (PWR_CR3)

and in PWR CPU2 control register 3 (PWR_C2CR3) .

6.6.10 PWR Port B pull-up control register (PWR_PUCRB)

Address offset: 0x028

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Res.

PU9 rw

PU8 rw

PU7 rw

PU6 rw

PU5 rw

PU4 rw

PU3 rw

PU2 rw

PU1 rw

PU0 rw

160/1202 RM0471 Rev 5

RM0471 Power control (PWR)

Bits 31:10 Reserved, must be kept at reset value.

Bits 9:0 PUy : Port B pull-up bit y (y=0...9)

When set, this bit activates the pull-up on Px[y] when one of the APC bits is set in PWR control register 3 (PWR_CR3)

and in PWR CPU2 control register 3 (PWR_C2CR3) . The

pull-up is not activated if the corresponding PDy bit is also set.

6.6.11 PWR Port B pull-down control register (PWR_PDCRB)

Address offset: 0x02C

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Res.

PD9 rw

PD8 rw

PD7 rw

PD6 rw

PD5 rw

PD4 rw

PD3 rw

PD2 rw

PD1 rw

PD0 rw

Bits 31:10 Reserved, must be kept at reset value.

Bits 9:0 PDy : Port B pull-down bit y (y=0...9)

When set, this bit activates the pull-down on PB[y] when one of the APC bits is set in

PWR control register 3 (PWR_CR3)

and in PWR CPU2 control register 3 (PWR_C2CR3) .

6.6.12 PWR Port C pull-up control register (PWR_PUCRC)

Address offset: 0x030

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Res.

15 14

PU15 PU14 rw rw

Res.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:14 PUy : Port C pull-up bit y (y=14,15)

When set, this bit activates the pull-up on Px[y] when one of the APC bits is set in PWR control register 3 (PWR_CR3)

and in PWR CPU2 control register 3 (PWR_C2CR3) . The

pull-up is not activated if the corresponding PDy bit is also set.

Bits 13:0 Reserved, must be kept at reset value.

RM0471 Rev 5 161/1202

169

Power control (PWR) RM0471

6.6.13 PWR Port C pull-down control register (PWR_PDCRC)

Address offset: 0x034

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Res.

15 14

PD15 PD14 rw rw

Res.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:14 PDy : Port C pull-down bit y (y=14,15)

When set, this bit activates the pull-down on PC[y] when one of the APC bits is set in PWR control register 3 (PWR_CR3)

and in PWR CPU2 control register 3 (PWR_C2CR3) .

Bits 13:0 Reserved, must be kept at reset value.

6.6.14 PWR Port E pull-up control register (PWR_PUCRE)

Address offset: 0x040

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Res.

PU4 rw

Res.

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 PU4 : Port E pull-up bit 4

When set, this bit activates the pull-up on Px[y] when one of the APC bits is set in PWR control register 3 (PWR_CR3)

and in PWR CPU2 control register 3 (PWR_C2CR3) . The

pull-up is not activated if the corresponding PD4 bit is also set.

Bits 3:0 Reserved, must be kept at reset value.

6.6.15 PWR Port E pull-down control register (PWR_PDCRE)

Address offset: 0x044

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes.

162/1202 RM0471 Rev 5

RM0471 Power control (PWR)

Res.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Res.

PD4 rw

Res.

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 PD4 : Port E pull-down bit 4

When set, this bit activates the pull-down on PE4 when one of the APC bits is set in

PWR control register 3 (PWR_CR3)

and in PWR CPU2 control register 3 (PWR_C2CR3) .

Bits 3:0 Reserved, must be kept at reset value.

6.6.16 PWR Port H pull-up control register (PWR_PUCRH)

Address offset: 0x058

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with

PWRRST bit in the RCC_APB1RSTR1 register.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Res.

PU3 rw

Res.

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 PU3: Port H pull-up bit 3

When set, this bit activates the pull-up on PH[y] when one of the APC bits is set in

PWR control register 3 (PWR_CR3)

and in PWR CPU2 control register 3 (PWR_C2CR3) .

The pull-up is not activated if the corresponding PDy bit is also set.

Bits 2:0 Reserved, must be kept at reset value.

Res.

6.6.17 PWR Port H pull-down control register (PWR_PDCRH)

Address offset: 0x05C

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with

PWRRST bit in the RCC_APB1RSTR1 register.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

RM0471 Rev 5 163/1202

169

Power control (PWR) RM0471

Res.

PD3 rw

Res.

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 PD3: Port H pull-down bit 3

When set, this bit activates the pull-down on PH[y] when one of the APC bits is set in PWR control register 3 (PWR_CR3)

and in PWR CPU2 control register 3 (PWR_C2CR3) .

Bits 2:0 Reserved, must be kept at reset value.

Res.

Address offset: 0x080

Reset value: 0x0000 0000. This register is reset after wakeup from Standby mode, except for bits [2:0].

Res.

802

EWKUP rw

BLE

EWKUP rw

Res.

FPDS rw

FPDR rw

Res.

2 1 0 rw

LPMS[2:0] rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 802EWKUP : 802.15.4 external wakeup signal

When set this bit forces a wakeup of the 802.15.4 controller. It is automatically reset when

802.15.4 controller exits its sleep mode.

0: No action.

1: Wakeup 802.15.4 controller form its sleep mode.

Bit 14 BLEEWKUP : BLE external wakeup

When set this bit forces a wakeup of the BLE controller. It is automatically reset when BLE controller exits its sleep mode.

0: No action

1: Wakeup BLE controller from its sleep mode

Bits 13:6 Reserved, must be kept at reset value.

Bit 5 FPDS : Flash memory power down mode during LPSleep for CPU2

This bit selects whether the Flash memory is in power down mode or idle mode when both

CPUs are in Sleep mode. Flash memory is set in power down mode only when the system is in LPSleep mode and the PWR_CR1.FPDS bit from CPU1 also allows so.

0: Flash memory in Idle mode when system is in LPSleep mode

1: Flash memory in power down mode when system is in LPSleep mode

164/1202 RM0471 Rev 5

RM0471 Power control (PWR)

Bit 4 FPDR : Flash memory power down mode during LPRun for CPU2

This bit can only be written to 1 after unlocking this register bit, by first writing (code 0xC1B0) into this register (when writing the code register bits are not updated). Selects whether the

Flash memory is in power down mode or idle mode when in LPRun mode. (Flash memory can only be in power down mode when code is executed from SRAM). Flash memory is set in power down mode only when the system is in LPRun mode, and the PWR_CR1.FPDR bit from CPU1 also allows so.

0: Flash memory in Idle mode when system is in LPRun mode

1: Flash memory in power down mode when system is in LPRun mode

Bit 3 Reserved, must be kept at reset value.

Bits 2:0 LPMS[2:0] : Low-power mode selection for CPU2

These bits are not reset when exiting Standby mode.

These bits select the low-power mode entered when CPU2 enters the deepsleep mode. The system low-power mode entered depend also on the PWR_CR1.LPMS allowed low-power mode from CPU1.

000: Stop0 mode

001: Stop1 mode

010: Stop2 mode

011: Standby mode

1xx: Shutdown mode

Note: If LPR bit is set, Stop2 mode cannot be selected and Stop1 mode must be entered instead of Stop2.

In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration

in PWR control register 3 (PWR_CR3) .

Res.

Address offset: 0x084

Reset value: 0x0000 8000. This register is not reset when exiting Standby modes.

Access: Additional APB cycles are needed to access this register vs. those needed for a standard APB access (three for a write and two for a read).

Res.

WUL rw

Res.

APC rw

Res.

E802

WUP rw

EBLE

WUP rw

Res.

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 EIWUL : Enable internal wakeup line for CPU2

0: Internal wakeup line to CPU2 disabled

1: Internal wakeup line to CPU2 enabled

Bits 14:13 Reserved, must be kept at reset value.

Res.

4 3 2

Res.

EWUP4 Res.

1 0

Res.

EWUP1 rw

RM0471 Rev 5 165/1202

169

Power control (PWR) RM0471

Bit 12 APC : Apply pull-up and pull-down configuration for CPU2

When this bit for CPU2 or the PWR_CR3.APC bit for CPU1 is set, the I/O pull-up and pulldown configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied.

When both bits are cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os.

Bit 11 Reserved, must be kept at reset value.

Bit 10 E802WUP Enable 802.15.4 host wakeup interrupt for CPU2

0: Interrupt to CPU2 disabled

1: interrupt to CPU2 enabled

Bit 9 EBLEWUP Enable BLE host wakeup interrupt for CPU2

0: Interrupt to CPU2 disabled

1: interrupt to CPU2 enabled

Bits 8:4 Reserved, must be kept at reset value.

Bit 3 EWUP4 : Enable Wakeup pin WKUP4 for CPU2

When this bit is set, the external wakeup pin WKUP4 is enabled and triggers an interrupt and wakeup from Stop, Standby or Shutdown event when a rising or a falling edge occurs to

CPU2. The active edge is configured via the WP4 bit in the

PWR control register 4

(PWR_CR4)

Bits 2:1 Reserved, must be kept at reset value.

Bit 0 EWUP1 : Enable Wakeup pin WKUP1 for CPU2

When this bit is set, the external wakeup pin WKUP1 is enabled and triggers an interrupt and wakeup from Stop, Standby or Shutdown event when a rising or a falling edge occurs to

CPU2. The active edge is configured via the WP1 bit in the

PWR control register 4

(PWR_CR4)

6.6.20 PWR extended status and status clear register (PWR_EXTSCR)

Address offset: 0x088

Reset value: 0x0000 0000

Access: Three additional APB cycles are needed to write this register vs. a standard APB write.

Res.

23 22 21 20 19

Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

C2DS C1DS CRPF Res.

C2STOPF C2SBF C1STOPF C1SBF Res.

Res.

CCRPF C2CSSF C1CSSF r r r r r r r w w w

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 C2DS : CPU2 deepsleep mode

This bit is set by hardware when CPU2 enters deepsleep mode or is hold by C2BOOT.

0: CPU2 is running or in sleep

1: CPU2 is in deepsleep or hold by C2BOOT

166/1202 RM0471 Rev 5

RM0471 Power control (PWR)

Bit 14 C1DS : CPU1 deepsleep mode

This bit is set by hardware when CPU1 enters deepsleep mode.

0: CPU1 is running or in sleep

1: CPU1 is in deepsleep

Bit 13 CRPF : Critical Radio system phase

This bit is set by hardware when the Radio system wakes up. It is reset either by hardware when the Radio system enters Low-power mode or by software when writing CCRPF.

0: Not a critical Radio system phase

1: Critical Radio system phase ongoing

Bit 12 Reserved, must be kept at reset value.

Bit 11 C2STOPF : System Stop flag for CPU2.

This bit is set by hardware and cleared only by any reset or by setting C2CSSF bit.

0: System has not been in Stop mode

1: System has been in Stop mode

Bit 10 C2SBF : System Standby flag for CPU2.

This bit is set by hardware and cleared only by a POR reset or by setting C2CSSF bit.

0: System has not been in Standby mode

1: System has been in Standby mode

Bit 9 C1STOPF : System Stop flag for CPU1.

This bit is set by hardware and cleared only by any reset or by setting C1CSSF bit.

0: System has not been in Stop mode

1: System has been in Stop mode

Bit 8 C1SBF : System Standby flag for CPU1.

This bit is set by hardware and cleared only by a POR reset or by setting C1CSSF bit.

0: System has not been in Standby mode

1: System has been in Standby mode

Bits 7:3 Reserved, must be kept at reset value.

Bit 2 CCRPF : Clear critical Radio system phase

Setting this bit clears the CRPF bit.

Bit 1 C2CSSF : Clear CPU2 Stop Standby flags

Setting this bit clears the C2STOPF and C2SBF bits.

Bit 0 C1CSSF : Clear CPU1 Stop Standby flags

Setting this bit clears the C1STOPF and C1SBF bits.

RM0471 Rev 5 167/1202

169

Power control (PWR) RM0471

Offset Register

0x000

0x004

0x008

0x00C

0x010

0x014

PWR_SCR

0x018

0x01C

0x020

0x024

0x028

0x02C

0x030

0x034

0x038

0x03C

0x040

Reset value

Reserved

PWR_PUCRA

Reset value

PWR_PDCRA

Reset value

PWR_PUCRB

Reset value

PWR_PDCRB

Reset value

PWR_PUCRC

Reset value

PWR_PDCRC

Reset value

Reserved

PWR_PUCRE

Reset value

PWR_CR1

Reset value

PWR_CR2

Reset value

PWR_CR3

Reset value

PWR_CR4

Reset value

PWR_SR1

Reset value

PWR_SR2

Reset value

168/1202

Table 33. PWR register map and reset values

1 0 0 0 0 0 0

0 0 0

LPMS

[2:0]

0 0 0

PLS [2:0]

0 0 0 0

0 0

0 0 0 0 0

RM0471 Rev 5

0 0 0 0 0 0 0 0

0 0 0

0 0 0 0 0 0 0

0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0

0 0

RM0471 Power control (PWR)

Offset

0x044

0x058

0x05C

Register

PWR_PDCRE

Reset value

PWR_PUCRH

Reset value

PWR_PDCRH

Reset value

Table 33. PWR register map and reset values (continued)

0x080

PWR_C2CR1

Reset value 0 0

PWR_C2CR3

0x084

Reset value 1 0 0 0

0x088

PWR_EXTSCR

Reset value 0 0 0 0 0 0 0

Refer to Section 2.2 on page 55 for the register boundary addresses.

0 0

LPMS

[2:0]

0 0 0

0 0

0 0 0

RM0471 Rev 5 169/1202

169

Reset and clock control (RCC)

7 Reset and clock control (RCC)

7.1 Reset

There are three types of reset, namely:

a system reset

2. a power reset

3. a backup domain reset

RM0471

A power reset is generated when one of the following events occurs:

a brown-out reset (BOR)

2. when exiting from Standby mode

3. when exiting from Shutdown mode

A brown-out reset, including power-on or power-down reset (POR/PDR), sets all registers to their reset values except the Backup domain.

When exiting Standby mode, all registers in the V

CORE

Registers outside the V

CORE control) are not impacted.

domain are set to their reset value.

domain (RTC, WKUP, IWDG, and Standby/Shutdown modes

When exiting Shutdown mode, a Brown-out reset is generated, resetting all registers except those in the Backup domain.

A system reset sets all registers to their reset values except register (RCC_CSR) and the registers in the Backup domain.

A system reset is generated when one of the following events occurs:

A low level on the NRST pin (external reset)

2. Window watchdog event (WWDG reset)

3. Independent watchdog event (IWDG reset)

4. A software (SW) reset (see Software reset )

5. Low-power mode security reset (see

Low-power mode security reset )

6. Option byte loader reset (see Option byte loader reset

)

7. A brown-out reset

The reset source can be identified by checking the reset flags in the RCC control/status register (RCC_CSR) .

These sources act on the NRST pin, always kept low during the delay phase. The CPU1

RESET service routine vector is selected via the BOOT0 and BOOT1.

The system reset signal provided to the device is output on the NRST pin. The pulse generator guarantees a minimum reset pulse duration of 20 µs for each internal reset source. In case of an external reset, the reset pulse is generated while the NRST pin is asserted low.

170/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

In case of an internal reset, the internal pull-up R

PU consumption through the pull-up resistor.

is deactivated to reduce power

Figure 13. Simplified diagram of the reset circuit

System reset

External reset

NRST

Filter

Pulse generator

(min 20 μs)

WWDG reset

IWDG reset

Software reset

Low-power manager reset

Option byte loader reset

BOR reset

MS45403V1

Software reset

The SYSRESETREQ bit in CPU1 application interrupt and reset control register may be set to force a software reset on the device (refer to PM0214 “ STM32 Cortex

-M4 MCUs and

MPUs programming manual “, available on www.st.com

The SYSRESETREQ bit in CPU2 application interrupt and reset control register may be set to force a software reset on the device.

Low-power mode security reset

To prevent that critical applications enter a low-power mode by mistake, two low-power mode security resets are available. If enabled in option bytes, the resets are generated in the following conditions:

When entering Standby mode: reset is enabled by resetting nRST_STDBY bit in User option Bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode.

2. When entering Stop mode: reset is enabled by resetting nRST_STOP bit in User option bytes. In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering Stop mode.

3. When entering Shutdown mode: reset is enabled by resetting nRST_SHDW bit in User option bytes. In this case, whenever a Shutdown mode entry sequence is successfully executed, the device is reset instead of entering Shutdown mode.

For further information on the User option bytes refer to

Section 3.4.1: Option bytes description

Option byte loader reset

The option byte loader reset is generated when the OBL_LAUNCH bit is set in the

FLASH_CR register. This bit is used to launch the option byte loading by software.

RM0471 Rev 5 171/1202

246

Reset and clock control (RCC) RM0471

The backup domain has two specific resets.

A backup domain reset is generated when one of the following events occurs:

Software reset, triggered by setting the BDRST bit in the RCC backup domain control register (RCC_BDCR)

2. V

or V

BAT

power on, if both supplies have previously been powered off.

A backup domain reset only affects the LSE oscillator, the RTC, the Backup registers and the RCC Backup domain control register.

7.2 Clocks

Four different clock sources can be used to drive the system clock (SYSCLK):

 HSI16 (high speed internal)16 MHz RC oscillator clock

 MSI (multispeed internal) RC oscillator clock from 100 kHz to 48 MHz.

 HSE 32 MHz oscillator clock

 PLL clock

The MSI is used as system clock source after startup from Reset, configured at 4 MHz.

The devices have the following additional clock sources:

 LSI1: 32 kHz low speed internal RC which may drive the independent watchdog and optionally the RTC used for Auto-wakeup from Stop and Standby modes (shall not be used for RF system Auto-wakeup).

 LSI2: 32 kHz low speed low drift internal RC which may drive the independent watchdog and optionally the RTC used for Auto-wakeup from Stop and Standby modes.

 LSE: 32.768 kHz low speed external crystal which optionally drives the RTC used for

Auto-wakeup or the RF system Auto-wakeup from Stop and Standby modes, or the real-time clock (RTCCLK).

 HSI48: RC 48 MHz internal clock sources to potentially drive the True RNG.

Each clock source can be switched on or off independently when it is not used, to optimize power consumption.

Several prescalers can be used to configure the AHB frequencies (HCLK1, HCLK2 and

HCLK4) the high speed APB (PCLK2) and the low speed APB (PCLK1) domains. The maximum frequency of the AHB (HCLK1 and HCLK4), and of the PCLK1 and PCLK2 domains is 64 MHz. The maximum frequency of the AHB (HCLK2) domain is 32 MHz.

172/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Most peripheral clocks are derived from their bus clock (HCLK, PCLK) except:

 The 48 MHz clock, used for True RNG. This clock is derived (selected by software) from one of the following sources:

– PLL VCO (PLLQCLK only available in Run mode)

– MSI clock (only available in Run mode)

– HSI48 internal oscillator (only available in Run mode)

 The ADCs clock, which is derived (selected by software) from one of the three following sources:

– system clock (SYSCLK only available in Run mode)

– PLL VCO (PLLAPCLK only available in Run mode)

 The U(S)ARTs clocks, which are derived (selected by software) from one of the four following sources:

– system clock (SYSCLK only available in Run mode)

– HSI16 clock (only available in Run and Stop modes)

– LSE clock ( only available in Run and Stop modes)

– APB clock (PCLK depending on which APB is mapped the U(S)ART only available in CRun when enabled in U(S)ARTxEN and CSleep when also enabled in

U(S)ARTxSMEN)

The wakeup from Stop mode is supported only when the clock is HSI16 or LSE.

 The I 2 Cs clocks, derived (selected by software) from one of the three following sources:

– system clock (SYSCLK only available in Run mode)

– HSI16 clock (only available in Run and Stop modes)

– APB clock (PCLK depending on which APB is mapped the I

C only available in

CRun when enabled in I2CxEN and CSleep when also enabled in I2CxSMEN)

The wakeup from Stop mode is supported only when the clock is HSI.

 The low-power timer (LPTIMx) clocks, which are derived (selected by software) from one of the five following sources:

– LSI clock (LSI1 or LSI2 only available in Run and Stop modes)

– LSE clock (only available in Run and Stop modes)

– HSI16 clock (only available in Run mode)

– APB clock (PCLK depending on which APB is mapped the LPTIMx only available in CRun when enabled in LPTIMxEN and CSleep when also enabled in

LPTIMxSMEN)

– External clock mapped on LPTIMx_IN1 (only available in Run and Stop modes)

The functionality in Stop mode (including wakeup) is supported only when the clock is

LSI or LSE, or in external clock mode.

 The RTC clock, which is derived (selected by software) from one of the three following sources:

– LSE clock

– LSI clock (LSI1 or LSI2)

– HSE clock divided by 32

The functionality in Stop mode (including wakeup) is supported only when the clock is

LSI or LSE.

RM0471 Rev 5 173/1202

246

Reset and clock control (RCC) RM0471

 The IWDG clock, which is always the LSI clock (LSI1 or LSI2).

 The RF system wakeup clock, which is derived (selected by software) from one of the two following sources:

– LSE clock

– HSE clock divided by 1024

The functionality in Stop mode (including wakeup) is supported only when the clock is

LSE. When HSE/1024 is selected as RF system wakeup source HSEON bit must be set by the application.

 The RF system clock is derived (selected by hardware) from one of the two following sources:

– HSI16 clock

– HSE clock

The functionality in Stop mode is supported only when the clock is HSI16 is selected as wakeup clock by STOPWUCK.

The RCC feeds the CPU1 system timer (SysTick) external clock with the AHB clock

(HCLK1) divided by 8. The SysTick can work either with this clock or directly with the CPU1 clock (HCLK1), configurable in the SysTick Control and status register.

FCLK1 acts as CPU1 free-running clock. For more details refer to PM0214.

The RCC feeds the CPU2 system timer (SysTick) external clock with the AHB clock

(HCLK2) divided by 8. The SysTick can work either with this clock or directly with the CPU2 clock (HCLK2), configurable in the SysTick Control and status Register.

FCLK2 acts as CPU2 free-running clock.

The clock tree is detailed in

Figure 14

174/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Figure 14. Clock tree

LSI1 RC 32 kHz

LSI2 RC 32 kHz

LSI to IWDG

LSCO

OSC32_OUT

OSC32_IN

LSE OSC

32.768 kHz

LSE CSS

MCO

/1 - 16

OSC_OUT

OSC_IN

HSE OSC

32 MHz

HSE CSS

HSI16 RC

16 MHz

MSI RC

100 kHz - 48 MHz

HSI48 RC

48 MHz

LSI1

LSI2

LSE

HSE

SYSCLK

PLLRCLK

HSI16

MSI

RC48

MSI

HSI16

LSI

LSE to RTC to BLE wakeup

LSE to 802.15.4 wakeup

/32

CPU1

HPRE

/1,2,...,512

HCLK1 to CPU1, AHB1, AHB2, AHB3, and SRAM1 to CPU1 FCLK to CPU1 system timer

SYS clock source control

PLLRCLK

HSI16

HSE

HSEPRE/1,2

MSI

SYSCLK

CPU2

C2HPRE

1,2,...,512

HCLK2

AHB4

SHDHPRE

/1,2,...,512

HSI16

HSE

HCLK4

HCLK5

APB1

PPRE1

/1,2,4,8,16

PCLK1 to APB1 x1 or x2 to APB1 TIMx

APB2

PPRE2

/1,2,4,8,16

PCLK2 to APB2 x1 or x2 to APB2 TIMx to CPU2 to CPU2 FCLK to CPU2 system timer

/8 to AHB4, Flash memory, SRAM2 to APB3 to AHB5 to RF xN

PLL

PLLPCLK

PLLQCLK

PLLRCLK

MSI

HSI48 CLK48SE

LSI

LSE to RNG PCLKn

SYSCLK

HSI16

LSE to USART1

SYSCLK to ADC

PCLKn

SYSCLK

HSI16 to I2Cx

PCLKn

HSI16

LSI

LSE to LPTIMx

MSv63019V3

2. For full details about the internal and external clock source characteristics refer to the “Electrical characteristics” section in the device datasheet.

3. The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4).

When the programmable factor is ‘1’, the AHB prescaler must be equal to ‘1’.

The high speed external clock signal (HSE) can be generated from two possible clock sources (see

Figure 15

 HSE external crystal

 HSE user external clock

RM0471 Rev 5 175/1202

246

Reset and clock control (RCC) RM0471

The crystal has to be placed as close as possible to the oscillator pins to minimize output distortion and startup stabilization time. The loading capacitance are integrated and can be adjusted according to

Frequency tuning

Clock source

Figure 15. HSE clock sources

Hardware configuration

OSC_IN OSC_OUT

External clock

External source

OSC_IN OSC_OUT

Crystal

Note:

External crystal (HSE crystal)

The 32 MHz external oscillator has the advantage of producing a very accurate rate on the main clock, and is mandatory for any Radio operation.

The associated hardware configuration is shown in

Figure 15

. Refer to the electrical characteristics section of the datasheet for more details.

The HSERDY flag in the

RCC clock control register (RCC_CR)

indicates if the HSE oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware.

An interrupt can be generated if enabled in the

RCC clock interrupt enable register

(RCC_CIER) .

The HSE Crystal can be switched on and off using the HSEON bit in the RCC clock control register (RCC_CR) .

External source

In this mode, selectable by setting the HSEON

bit in the RCC clock control register

(RCC_CR)

, an external clock source must be provided, with a frequency of 32 MHz. The external clock signal (sinus) with ~45 to 55 % duty cycle (refer to the datasheet) has to drive the OSC_IN pin, while the OSC_OUT pin must be left not connected (see

Figure 15 ).

For details on pin availability, refer to the pinout section in the corresponding device datasheet.

Frequency tuning

The HSE oscillator frequency can vary from one chip to another due to manufacturing process variations and used crystal. User can tune the HSE frequency in the application by

176/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC) writing the HSETUNE bits in

RCC clock HSE register (RCC_HSECR) . The HSE frequency

can be measured by outputting the HSE clock on the MCO.

HSE oscillator gain and sense can be controlled by HSEGMC and HSES bits in

RCC clock

HSE register (RCC_HSECR)

. Refer to AN5042 for the HSE trimming procedure.

The HSI16 clock signal is generated from an internal 16 MHz oscillator.

The HSI16 oscillator has the advantage of providing a clock source at low cost. It also has a faster startup time than the HSE crystal oscillator however, even with calibration the frequency is less accurate than an external crystal oscillator or ceramic resonator.

The HSI16 clock can be selected as system clock after wakeup from Stop modes (Stop0,

Stop1 or Stop2), see

Section 7.3: Low-power modes

. It can also be used as a backup clock

source (auxiliary clock) if the HSE crystal oscillator fails, see Section 7.2.11

When the RF system is enabled the HSI16 must be selected as system clock after wakeup from Stop modes.

The HSI16 clock is used as system clock after restart wakeup from Standby.

Calibration

RC oscillator frequencies can vary from one chip to another because of manufacturing process variations, this is why each device is factory calibrated by ST for 1 % accuracy at T

= 25 °C.

After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the RCC internal clock sources calibration register (RCC_ICSCR) .

The RC oscillator speed can be affected by voltage or temperature variations, the user can

trim the HSI16 frequency in the application using the HSITRIM bits in the RCC internal clock sources calibration register (RCC_ICSCR) .

For more details on how to measure the HSI16 frequency variation, refer to

Section 7.2.20

The HSIRDY flag in the

RCC clock control register (RCC_CR)

indicates if the HSI16 RC is stable or not. At startup, the HSI16 RC output clock is not released until this bit is set by hardware.

The HSI16 RC can be switched on and off using the HSION bit in the RCC clock control register (RCC_CR) .

The HSI16 signal can also be used as a backup source (auxiliary clock) if the HSE crystal oscillator fails. Refer to

Section 7.2.11

The MSI clock signal is generated from an internal RC oscillator. Its frequency range can be

adjusted by software by using the MSIRANGE[3:0] bits in the RCC clock control register

(RCC_CR)

. Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz,

1 MHz, 2 MHz, 4 MHz (default value), 8 MHz, 16 MHz, 24 MHz, 32 MHz and 48 MHz.

The MSI clock is used as system clock after restart from Reset, wakeup from Shutdown lowpower modes. After restart from Reset, the MSI frequency is set to its default value 4 MHz.

Refer to Section 7.3: Low-power modes

RM0471 Rev 5 177/1202

246

Reset and clock control (RCC) RM0471

The MSI clock can be selected as system clock after a wakeup from Stop mode (Stop 0,

Stop 1 or Stop 2). Refer to Section 7.3: Low-power modes . It can also be used as a backup

clock source (auxiliary clock) if the HSE crystal oscillator fails. Refer to

Section 7.2.11

In addition, when used in PLL-mode with the LSE, it provides a very accurate clock source which can be used by the PLL to run the system at the maximum speed 64 MHz.

The MSIRDY flag in the RCC clock control register (RCC_CR)

indicates if the MSI RC is stable or not. At startup, the MSI RC output clock is not released until this bit is set by hardware. The MSI RC can be switched on and off by using the MSION bit in the

RCC clock control register (RCC_CR) .

Hardware auto calibration with LSE (PLL-mode)

When a 32.768 kHz external oscillator is present in the application, it is possible to configure the MSI in a PLL-mode by setting the MSIPLLEN bit in the

RCC clock control register

(RCC_CR)

. When configured in PLL-mode, the MSI automatically calibrates itself thanks to the LSE. This mode is available for all MSI frequency ranges.

Software calibration

The MSI RC oscillator frequency can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1 % accuracy at

25 °C ambient temperature (T

). After reset, the factory calibration value is loaded in the

MSICAL[7:0] bits in the RCC internal clock sources calibration register (RCC_ICSCR) . If the

application is subject to voltage or temperature variations, this may affect the RC oscillator speed. The MSI frequency in the application can be trimmed by using the MSITRIM[7:0] bits in the RCC_ICSCR register. For more details on how to measure the MSI frequency

variation refer to Section 7.2.20

The HSI48 clock signal is generated from an internal 48 MHz RC oscillator and can be used for the random number generator (True RNG).

The HSI48RDY flag in the Clock recovery register (RCC_CRRCR) indicates whether the

HSI48 RC oscillator is stable or not. At startup, the HSI48 RC oscillator output clock is not released until this bit is set by hardware.

The HSI48 can be switched on and off using the HSI48ON bit in the Clock recovery register

(RCC_CRRCR).

7.2.5 PLL

The device embeds a PLL providing three independent outputs. The internal PLL can be used to multiply the HSI, HSE or MSI output clock frequency. The PLL input frequency must be between 2.66 and 16 MHz. The selected clock source is divided by a programmable factor PLLM from 1 to 8 to provide a clock frequency in the requested input range. Refer to

Figure 14: Clock tree

and RCC PLL configuration register (RCC_PLLCFGR) .

The PLL configuration (selection of the input clock and multiplication factor) must be done before enabling the PLL. Once the PLL is enabled, these parameters cannot be changed.

To modify the PLL configuration, proceed as follows:

178/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Disable the PLL by setting PLLON to 0 in RCC clock control register (RCC_CR)

2. Wait until PLLRDY is cleared. The PLL is now fully stopped.

3. Change the desired parameter.

4. Enable the PLL again by setting PLLON to 1.

5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, PLLREN in

RCC

PLL configuration register (RCC_PLLCFGR) .

An interrupt can be generated when the PLL is ready, if enabled in the RCC clock interrupt enable register (RCC_CIER) .

The PLL output frequency must not exceed 64 MHz.

The enable bit of the PLL output clock (PLLPEN, PLLQEN, PLLREN) can be modified at any time without stopping the corresponding PLL. PLLREN cannot be cleared if PLLRCLK is used as system clock.

The LSE crystal is a 32.768 kHz low-speed external crystal or ceramic resonator. It has the advantage of providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions.

The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

Clock source

Figure 16. LSE clock sources

Hardware configuration

External clock

OSC32_IN OSC32_OUT

GPIO

External source

OSC32_IN OSC32_OUT

Crystal / ceramic resonators

Load capacitors

The LSE crystal is switched on and off using the LSEON bit in

RCC backup domain control register (RCC_BDCR)

. The crystal oscillator driving strength can be changed at runtime

using the LSEDRV[1:0] bits in the RCC backup domain control register (RCC_BDCR)

to obtain the best compromise between robustness and short start-up time on one side and

RM0471 Rev 5 179/1202

246

Reset and clock control (RCC) RM0471 low-power-consumption on the other side. The LSE drive can be decreased to the lower drive capability (LSEDRV = 00) when the LSE is ON. However, once LSEDRV is selected, the drive capability cannot be increased if LSEON = 1.

The LSERDY flag in the

RCC backup domain control register (RCC_BDCR)

indicates whether the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the

RCC clock interrupt enable register (RCC_CIER)

External source (LSE bypass)

In this mode, selectable by setting the LSEBYP and LSEON bits in the

RCC AHB1 peripheral clocks enable in Sleep modes register (RCC_AHB1SMENR) an external clock

source must be provided, with a frequency of up to 1 MHz. The external clock signal

(square, sinus or triangle) with ~50 % duty cycle has to drive the OSC32_IN pin while the

OSC32_OUT pin can be used as GPIO, see Figure 16

The LSI1 RC acts as a low-power clock source that can be kept running in Stop and

Standby mode for the independent watchdog (IWDG), RTC and RF wakeup. The clock frequency is 32 kHz. For more details refer to the electrical characteristics section of the datasheet.

The LSI1 RC can be switched on and off using the LSI1ON bit in the RCC control/status register (RCC_CSR) .

The LSI1RDY flag in the

RCC control/status register (RCC_CSR)

indicates if the LSI1 oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware.

An interrupt can be generated if enabled in the

RCC clock interrupt enable register

(RCC_CIER) .

The LSI2 RC acts as a low drift low-power clock source that can be kept running in Stop and

Standby mode for the independent watchdog (IWDG), RTC wakeup. The clock frequency is

~ 32 kHz. For more details refer to the electrical characteristics section of the datasheet.

The LSI2 RC can be switched on and off using the LSI2ON bit in the RCC control/status register (RCC_CSR) .

The LSI2RDY flag in the

RCC control/status register (RCC_CSR)

indicates if the LSI2 oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware.

An interrupt can be generated if enabled in the

RCC clock interrupt enable register

(RCC_CIER) .

After any system reset NRST and before using the LSI2, its oscillator must get the trimming information. Firmware must copy the LSI2 trimming information from the ST production trimmed Flash memory location to the LSI2TRIM location in register RCC_SCR.

180/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

7.2.9 System clock (SYSCLK) selection

Four different clock sources can be used to drive the system clock (SYSCLK):

 MSI oscillator

 HSI16 oscillator

 HSE oscillator

 PLLRCLK

The system clock maximum frequency is 64 MHz. After a system reset, the MSI oscillator, at

4 MHz, is selected as system clock. When a clock source is used directly or through the PLL as a system clock, it is not possible to stop it.

A switch from one clock source to another occurs only if the target clock source is ready

(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source becomes ready. Status bits in the

RCC internal clock sources calibration register (RCC_ICSCR)

indicate which clock(s) is (are) ready and which clock is currently used as a system clock.

When waking up from Standby mode the HSI16 is selected as system clock.

7.2.10 Clock source frequency

Table 34 gives the different clock source frequencies.

MSI

48 MHz

Table 34. Maximum clock source frequency

HSI HSE

16 MHz 32 MHz

PLL

64 MHz

(VCO max = 344 MHz)

Note:

The clock security system can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.

If a failure is detected on the HSE clock, the HSE oscillator is automatically disabled, a clock failure event is sent to the break input of the advanced-control timers (TIM1 and TIM16/17) and an interrupt is generated to inform the software about the failure (clock security system interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the

CPU1 and CPU2 NMI (non-maskable interrupt) exception vector.

Once the HSE CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and a

NMI is automatically generated. The NMI is executed indefinitely unless the CSS interrupt pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt by setting the CSSC bit in the

RCC clock interrupt clear register (RCC_CICR)

If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is used as PLL input clock, and the PLL clock is used as system clock), a detected failure causes a switch of the system clock to the MSI or the HSI16 oscillator depending on the

STOPWUCK configuration in the RCC clock configuration register (RCC_CFGR) , and the

disabling of the HSE oscillator. If the HSE clock (divided or not) is the clock entry of the PLL used as system clock when the failure occurs, the PLL is disabled too.

RM0471 Rev 5 181/1202

246

Reset and clock control (RCC) RM0471

The clock security system on LSE can be activated by software writing the LSECSSON bit in the

RCC control/status register (RCC_CSR) . This bit can be disabled only by a hardware

reset or RTC software reset, or after a failure detection on LSE. LSECSSON must be written after LSE and LSI are enabled (LSEON and LSI1ON enabled) and ready (LSERDY and

LSIRDY set by hardware), and after the RTC clock has been selected by RTCSEL.

The CSS on LSE is working in all modes except VBAT. It is working also under system reset

(excluding power on reset). If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied to the RTC but no hardware action is made to the registers. If the

MSI was in PLL-mode, this mode is disabled.

In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup

the software (see RCC clock interrupt enable register (RCC_CIER)

, RCC clock interrupt flag register (RCC_CIFR) ,

RCC clock interrupt clear register (RCC_CICR) ).

The software MUST then disable the LSECSSON bit, stop the defective 32 kHz oscillator

(disabling LSEON), and change the RTC clock source (no clock or LSI or HSE, with

RTCSEL), or take any required action to secure the application.

7.2.13 LSI source selection

The LSI used in the system can be selected to come either from LSI1 or LSI2. Whenever

LSI2 is turned on by LSI2ON register bit, the LSI2 (when ready) is selected as LSI source.

To switch from LSI2 to LSI1 without interrupting the LSI clock, the LSI1 must first be switched on by LSI1ON register bit. The FW must verify that the LSI1 is ready by LSI1RDY register bit before disabling LSI2 in LSI2ON register bit.

The ADC clock is derived from the system clock, or from the PLL output. It can reach

64 MHz and can be divided by the prescaler values 1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128 or

256 by configuring the ADC1_CCR register. It is asynchronous to the AHB clock.

Alternatively, the ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). This programmable factor is configured using the CKMODE bit fields in the ADC1_CCR.

If the programmed factor is ‘1’, the AHB prescaler must be set to ‘1’.

The RTCCLK clock source can be either the HSE/32, LSE or LSI clock. It is selected by programming the RTCSEL[1:0] bits in the

RCC backup domain control register

(RCC_BDCR)

. This selection cannot be modified without resetting the Backup domain. The system must always be configured so as to get a PCLK frequency greater then or equal to the RTCCLK frequency for a proper operation of the RTC.

182/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not.

Consequently:

 If LSE is selected as RTC clock the RTC continues to work even if the V

DD switched off, provided the V

BAT

supply is maintained.

supply is

 If LSI is selected as the RTC clock the RTC state is not guaranteed if the V

DD powered off.

supply is

 If the HSE clock divided by a prescaler is used as the RTC clock the RTC state is not guaranteed if the V

supply is powered off or if the internal voltage regulator is powered off (removing power from the V

CORE

domain).

When the RTC clock is LSE or LSI, the RTC remains clocked and functional under system reset.

The timer clock frequencies are automatically defined by hardware. There are two cases:

If the APB prescaler equals 1, the timer clock frequencies are set to the same frequency as that of the APB domain.

2. Otherwise, they are set to twice (×2) the frequency of the APB domain.

If the Independent watchdog (IWDG) is started by either hardware option or software access, the LSI clock is forced on.

When neither the LSI1 oscillator nor the LSI2 oscillator is enabled when starting the IWDG, the LSI1 oscillator is forced on. After the LSI1 oscillator temporization, the clock is provided to the IWDG.

When LSI2 is switched on with the LSI2ON bit, the LSI clock is switched from LSI1 to LSI2.

When LSI2 is disabled by LSI2ON (when the IWDG is running), the LSI1 oscillator is forced on. The LSI clock is switched to LSI1 when ready, and only then LSI2 is stopped.

RM0471 Rev 5 183/1202

246

Reset and clock control (RCC) RM0471

The true random number generator (RNG) seed clock is derived from the MSI, HSI48, PLL

LSI or LSE clock.

 MCO

The microcontroller clock output (MCO) capability enables the clock to be output on the external MCO pin. One of the following clock signals can be selected as MCO clock:

– LSI1 (available in Run and Stop modes)

– LSI2 (available in Run and Stop modes)

– LSE (available in Run and Stop modes)

– MSI (available in Run mode)

– HSI (available in Run mode, when enabled by HSION)

– HSI48 (available in Run mode)

– HSE (available in Run mode)

– PLLRCLK (available in Run mode)

– SYSCLK (available in Run mode)

The selection is controlled by the MCOSEL[3:0] bits of the RCC clock configuration register (RCC_CFGR)

. The selected clock can be divided with the MCOPRE[2:0] field of the

RCC clock configuration register (RCC_CFGR) .

The clock on MCO is only available in Run and Stop modes and in not available in

Standby and Shutdown modes.

 LSCO

The LSCO output enables a low speed clock to be output on the external LSCO pin:

– LSI (LSI1 or LSI2)

– LSE

The selection is controlled by the LSCOSEL, and enabled with the LSCOEN in the

RCC backup domain control register (RCC_BDCR) .

The clock on LSCO is available in Run, Stop, and on one GPIO in Standby and

Shutdown modes.

The configuration registers of the corresponding GPIO port must be programmed in alternate function mode.

It is possible to indirectly measure the frequency of all on-board clock sources by mean of the TIM16 or TIM17 channel 1 input capture, as shown on

Figure 17 and Figure 18 .

184/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Figure 17. Frequency measurement with TIM16 in capture mode

TIM16

TI1_RMP[1:0]

GPIO

LSI

LSE

RTC wakeup interrupt

TI1

MS33434V1

The input capture channel of TIM16 can be a GPIO line or an internal clock of the MCU.

This selection is performed through the TI1_RMP[1:0] bits in the TIM16_OR register. The possibilities are the following ones:

 TIM16 Channel1 is connected to the GPIO. Refer to the alternate function mapping in the device datasheets.

 TIM16 Channel1 is connected to the LSI clock.

 TIM16 Channel1 is connected to the LSE clock.

 TIM16 Channel1 is connected to the RTC wakeup interrupt signal. In this case the RTC interrupt should be enabled.

Figure 18. Frequency measurement with TIM17 in capture mode

TIM17

TI1_RMP[1:0]

GPIO

MSI

HSE/32

MCO

TI1

MS33435V1

The input capture channel of the Timer 17 can be a GPIO line or an internal clock of the

MCU. This selection is performed through the TI1_RMP[1:0] bits in the TIM17_OR register.

The possibilities are the following ones:

 TIM17 Channel1 is connected to the GPIO. Refer to the alternate function mapping in the device datasheet.

 TIM17 Channel1 is connected to the MSI clock.

 TIM17 Channel1 is connected to the HSE/32 clock.

 TIM17 Channel1 is connected to the microcontroller clock output (MCO), this selection is controlled by the MCOSEL[3:0] bits of the Clock configuration register (RCC_CFGR).

Calibration of the HSI16 and the MSI

For TIM16, the primary purpose of connecting the LSE to the channel 1 input capture is to be able to precisely measure the HSI16 and MSI system clocks (for this, either the HSI16 or

RM0471 Rev 5 185/1202

246

Reset and clock control (RCC) RM0471

MSI should be used as the system clock source). The number of HSI16 (MSI, respectively) clock counts between consecutive edges of the LSE signal provides a measure of the internal clock period. Taking advantage of the high precision of LSE crystals (typically a few ppm tens), it is possible to determine the internal clock frequency with the same resolution, and trim the source to compensate for manufacturing-process- and/or temperature- and voltage-related frequency deviations.

Both the MSI and HSI16 oscillators have dedicated user-accessible calibration bits for this purpose.

The basic concept consists in providing a relative measurement (e.g. the HSI/LSE ratio): the precision is therefore closely related to the ratio between the two clock sources (the higher the ratio, the better the measurement).

If LSE is not available, HSE32 is the better option to reach the most precise possible calibration.

It is however impossible to have a good enough resolution when the MSI clock is low

(typically below 1 MHz). In this case, it is advised to:

 accumulate the results of several captures in a row

 use the timer input capture prescaler (up to one capture every eight periods)

 use the RTC wakeup interrupt signal (when the RTC is clocked by the LSE) as the input for the channel1 input capture. This improves the measurement precision. For this purpose the RTC wakeup interrupt must be enable.

Calibration of the LSI

The calibration of the LSI will follow the same pattern that for the HSI, but changing the reference clock. It is necessary to connect LSI clock to the channel 1 input capture of the

TIM16. Then define the HSE as system clock source, the number of his clock counts between consecutive edges of the LSI signal provides a measure of the internal low speed clock period.

The basic concept consists in providing a relative measurement (e.g. the HSE/LSI ratio).

The precision is therefore closely related to the ratio between the two clock sources, higher ratios result in more accurate measurements.

7.2.21 Peripheral clocks enable

Most peripheral bus and kernel clocks can individually be enabled per CPU. The

RCC_AHBxENR, and RCC_APBxENRy enable peripheral clocks for CPU1 and

RCC_C2_AHBxENR, and RCC_C2_APBxENR for CPU2. The peripheral clocks will follow

the CPU(s) state for which they are enabled, see Table 35

Peripheral bus clock activity during the CPU Sleep mode is controlled by the peripheral clock CPU sleep mode enable bit of the RCC_AHBxSMENR, and RCC_APBxSMENRy for

CPU1 and RCC_C2_AHBxSMENR, and RCC_C2_APBxSMENRy for CPU2 registers.The peripheral bus clock during Sleep mode will follow the CPU(s) state for which is it enabled,

see Table 35

186/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Table 35. Peripheral clock enable

Peripheral xxxEN xxxSMEN

1 x

CPU mode

Any

CRun

CSleep and CStop

CSleep

CStop

System mode

Any

Run

Stop

Standby or Shutdown

Bus clock

Stopped

Clocked

Stopped

Clocked

Stopped

1. Only the peripherals I2C, LPTIM, USART, True RNG and ADC have a kernel clock.

Kernel clock

(1)

Stopped

Clocked

Clocked when selected from

– HSI16

– LSI

– LSE.

Stopped when selected from

– bus clock

– SYSCLK

– PLL clocks

– MSI

– HSI48

Stopped

When the peripheral bus clock is not active, the peripheral registers read or write accesses are not supported.

When the peripheral bus clock is active the peripheral can be accessed by both CPUs regardless of which CPU has enabled the peripheral bus clock in its CPU xxxEN bit.

However, when the peripheral bus clock is enabled by only one CPU, and this CPU enters low power mode, the peripheral bus clock is stopped (also depending on this CPUs xxxSMEN setting) and peripheral access for the other CPU is no longer supported. It is therefor good practice to enable the peripheral bus clock with the CPU dedicated clock enable.

When the peripheral kernel clock is not active, the peripheral functionality is stopped.

The enable bit has a synchronization mechanism to create a glitch free clock for the peripheral. After the enable bit is set, there is a two clock cycles delay before the clock becomes active.

Caution: Just after enabling the clock for a peripheral, software must wait for a delay before accessing the peripheral registers.

Note: The BLE-IP when active, will activate the BLE bus and SRAM2 bus interface clocks.

RM0471 Rev 5 187/1202

246

Reset and clock control (RCC) RM0471

188/1202

 AHB and APB peripheral clocks, including DMA clock, can be disabled by software.

 Sleep and Low-power sleep modes stop the CPU clock. The memory interface clocks

(Flash and SRAM1 and SRAM2 interfaces) can be stopped by software during Sleep mode. The AHB to APB bridge clocks are disabled by hardware during Sleep mode when all the clocks of the peripherals connected to them are disabled.

 Stop modes (Stop 0, Stop 1 and Stop 2) stops most clocks in the V

CORE

domain and disables the PLL, the MSI and the HSE oscillators. The HSI16 may be kept running when requested by the IPs (USART1, I2C1) that make it possible to wakeup from Stop modes.

All U(S)ARTs and I 2 Cs have the capability to enable the HSI16 oscillator even when the

MCU is in Stop mode (if HSI16 is selected as the clock source for that peripheral).

All U(S)ARTs and LPTIMs can also be driven by the LSE oscillator when the system is in Stop mode (if LSE is selected as clock source for that peripheral) and the LSE oscillator is enabled (LSEON). In that case the LSE remains always ON in Stop mode

(they do not have the capability to turn on the LSE oscillator).

The LPTIMs can also be driven by the LSI oscillator when the system is in Stop mode

(if LSI is selected as clock source for that peripheral) and the LSI oscillator is enabled

(LSI1ON or LSI2ON).

 Standby and Shutdown modes stops all the clocks in the V

CORE the PLL, the HSI, the MSI and the HSE oscillators.

domain and disables

The low power modes mode can be overridden for debugging by setting the DBG_SLEEP,

DBG_STOP or DBG_STANDBY bits in the DBGMCU_CR register. In addition the EXTI

CDBGPWRUPREQ events can be used to allow debugging in Stop modes (see Table 36

Table 36. Single core Low power debug configurations

(1)

CDBGPWRUPREQ DBGMCU Debug

Mode

Sleep

Stop0 and

Stop1

Stop0, Stop1 and Stop2

CPU1

Disabled

Enabled

DBG_STANDBY DBG_STOP DBG_SLEEP

X X X

Disabled

Enabled

CPU1

Enabled

Disabled

Enabled

Standby X

Disabled

Enabled

Disabled

Enabled

1. X = Do not use.

When leaving the Stop modes (Stop0, Stop1 or Stop2), the system clock is either MSI or

HSI, depending on the software configuration of the STOPWUCK bit in the RCC_CFGR register. When the RF system is enabled the HSI16 shall be selected as in STOPWUCK.

When STOPWUCK select the HSI16 clock when leaving Stop mode, the C2HPRE is reset. to select divide by 1. The frequency (range and user trim) of the MSI oscillator is the one configured before entering Stop mode. The user trim of HSI16 is kept. If the MSI was in PLLmode before entering Stop mode, the PLL-mode stabilization time must be waited for after wakeup even if the LSE was kept ON during the Stop mode.

RM0471 Rev 5

RM0471 Reset and clock control (RCC)

When leaving the Standby mode, the system clock is HSI.

When leaving the Shutdown modes, the system clock is MSI. The MSI frequency at wakeup from Shutdown mode is 4 MHz. The user trim is lost.

If a Flash memory programming operation is on going, Stop, Standby and Shutdown modes entry is delayed until the Flash memory interface access is finished. If an access to the APB domain is ongoing, Stop, Standby and Shutdown modes entry is delayed until the APB access is finished.

RM0471 Rev 5 189/1202

246

Reset and clock control (RCC) RM0471

Address offset: 0x000

Reset value: 0x0000 0061 (after POR reset), 0x0000 0160 (after wakeup from Standby reset).

Access: No wait state, word, half-word and byte access

31 30 29

Res.

15 14 13

Res.

HSIKE

RDY r

Res.

HSI

ASFS rw

Res.

HSI

RDY r

PLL

RDY r

HSIKER

ON rw

PLL

ON rw

HSI

ON rw

Res.

HSEP

RE rw

4 rw

MSIRANGE[3:0] rw rw rw

CSS

ON rs

Res.

MSI

PLLEN rw

HSE

RDY r

MSI

RDY r

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 PLLRDY: System PLL clock ready flag

Set by hardware to indicate that the system PLL is locked.

0: PLL unlocked

1: PLL locked

Bit 24 PLLON: System PLL enable

Set and cleared by software to enable the PLL.

Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL clock is used as the system clock.

0: PLL OFF

1: PLL ON

Bits 23:21 Reserved, must be kept at reset value.

Bit 20 HSEPRE: HSE system clock and PLL M divider prescaler

Set and cleared by software to control the division factor of the system clock and PLL M divider input when selecting HSE clock.

0: SYSCLK and PLL M divider input clocks are not divided (HSE)

1: SYSCLK and PLL M divider input clocks are divided by 2 (HSE/2)

Bit 19 CSSON: HSE clock security system enable

Set by software to enable the clock security system. When CSSON is set, the HSE lock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset.

0: HSE clock security system OFF (clock detector OFF)

1: HSE clock security system ON (clock detector ON if the HSE oscillator is stable, OFF if not).

Bit 18 Reserved, must be kept at reset value.

HSE

ON rw

MSI

ON rw

190/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Bit 17 HSERDY: HSE clock ready flag

Set by hardware to indicate that the HSE oscillator is stable.

0: HSE oscillator not ready

1: HSE oscillator ready

Note: Once the HSEON bit is cleared, HSERDY goes low after six HSE clock cycles.

Regardless of the value of the HSEON bit, the HSE oscillator starts on RF demand when needed. It is possible to have HSEON = 0 and HSERDY = 1.

Bit 16 HSEON: HSE clock enable

Set and cleared by software.

Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.

0: HSE oscillator OFF

1: HSE oscillator ON

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 HSIKERDY : HSI16 kernel clock ready flag for peripherals requests.

Set by hardware to indicate that HSI16 oscillator is stable when enabled by HSIKERON or a peripheral kernel clock request. Not set when HSI16 is enabled by software by setting

HSION, or by wakeup from Standby.

0: HSI16 oscillator not ready

1: HSI16 oscillator ready

Bit 11 HSIASFS: HSI16 automatic start from Stop

Set and cleared by software. When the system wakeup clock is MSI, this bit is used to wakeup the HSI16 is parallel of the system wakeup.

0: HSI16 oscillator is not enabled by hardware when exiting Stop mode with MSI as wakeup clock.

1: HSI16 oscillator is enabled by hardware when exiting Stop mode with MSI as wakeup clock.

Bit 10 HSIRDY: HSI16 clock ready flag. (After wakeup from Standby this bit is read ‘b1 once the

HSI16 is ready)

Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION, or by wakeup from Standby. Not set when HSI16 is enabled by HSIKERON or by IP request.

0: HSI16 oscillator not ready

1: HSI16 oscillator ready

Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI16 clock cycles.

Bit 9 HSIKERON: HSI16 always enable for peripheral kernel clocks.

Set and cleared by software to force HSI16 ON even in Stop modes. The HSI16 enabled by

HSIKERON can only feed USARTs and I

Cs peripherals configured with HSI16 as kernel clock. Keeping the HSI16 ON in Stop mode avoids slowing down the communication speed because of the HSI16 startup time. This bit has no effect on HSION value.

0: No effect on HSI16 oscillator.

1: HSI16 oscillator is forced ON even in Stop mode.

RM0471 Rev 5 191/1202

246

Reset and clock control (RCC) RM0471

Bit 8 HSION: HSI16 clock enable

Set and cleared by software.

Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby or Shutdown mode.

Set by hardware to force the HSI16 oscillator ON when STOPWUCK = 1 or HSIASFS = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator.

This bit is set by hardware if the HSI16 is used directly or indirectly as system clock.

0: HSI16 oscillator OFF

1: HSI16 oscillator ON

Bits 7:4 MSIRANGE[3:0]: MSI clock ranges

These bits are configured by software to choose the frequency range of MSI when

MSIRANGE is set.Twelve frequency ranges are available:

0000: range 0, ~100 kHz

0001: range 1, ~200 kHz

0010: range 2, ~400 kHz

0011: range 3, ~800 kHz

0100: range 4, ~1M Hz

0101: range 5, ~2 MHz

0110: range 6, ~4 MHz (reset value)

0111: range 7, ~8 MHz

1000: range 8, ~16 MHz

1001: range 9, ~24 MHz

1010: range 10, ~32 MHz

1011: range 11, ~48 MHz others: not allowed (hardware write protection)

Note: Warning: MSIRANGE can be modified when MSI is OFF (MSION = 0) or when MSI is ready (MSIRDY = 1). MSIRANGE must NOT be modified when MSI is ON and NOT ready (MSION = 1 and MSIRDY = 0).

Bit 3 Reserved, must be kept at reset value.

Bit 2 MSIPLLEN: MSI clock PLL enable

Set and cleared by software to enable/ disable the PLL part of the MSI clock source.

MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware).There is a hardware protection to avoid enabling MSIPLLEN if LSE is not ready.

This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the clock security system on LSE detects a LSE failure (refer to RCC_CSR register).

0: MSI PLL OFF

1: MSI PLL ON

Bit 1 MSIRDY: MSI clock ready flag (After reset this bit is read ‘b1 once the MSI is ready)

This bit is set by hardware to indicate that the MSI oscillator is stable.

0: MSI oscillator not ready

1: MSI oscillator ready

Note: Once the MSION bit is cleared, MSIRDY goes low after 6 MSI clock cycles.

192/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Bit 0 MSION: MSI clock enable

This bit is set and cleared by software.

Cleared by hardware to stop the MSI oscillator when entering Stop, Standby or Shutdown mode.

Set by hardware to force the MSI oscillator ON when exiting Standby or Shutdown mode.

Set by hardware to force the MSI oscillator ON when STOPWUCK = 0 when exiting from

Stop modes, or in case of a failure of the HSE oscillator

Set by hardware when used directly or indirectly as system clock.

0: MSI oscillator OFF

1: MSI oscillator ON

7.4.2

Res.

15 rw

RCC internal clock sources calibration register (RCC_ICSCR)

Address offset: 0x004

Reset value: 0x40XX 00XX (X is factory-programmed)

Access: No wait state, word, half-word and byte access

30 29 rw

14 rw rw

13 rw

28 27

HSITRIM[6:0]

26 rw

12 rw

MSITRIM[7:0] rw rw rw

10 rw

25 rw

9 rw

24 rw

8 rw

23 r

7 r

22 r

6 r

21 r

5 r r

20 19

HSICAL[7:0] r

MSICAL[7:0] r r

18 r

2 r

17 r

1 r

16 r

0 r

Bit 31 Reserved, must be kept at reset value.

Bits 30:24 HSITRIM[6:0]: HSI16 clock trimming

These bits provide an additional user-programmable trimming value that is added to the

HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI16.

The default value is 64, which, when added to the HSICAL value, should trim the HSI16 to

16 MHz ± 1 %.

Bits 23:16 HSICAL[7:0]: HSI16 clock calibration

These bits are initialized at startup with the factory-programmed HSI16 calibration trim value.

When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value.

Bits 15:8 MSITRIM[7:0]: MSI clock trimming

These bits provide an additional user-programmable trimming value that is added to the

MSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the MSI.

The default value is 0, which, when added to the MSICAL value, should trim the MSI to its mid frequency.

Bits 7:0 MSICAL[7:0]: MSI clock calibration

These bits are initialized at startup with the factory-programmed MSI calibration trim value.

When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim value.

RM0471 Rev 5 193/1202

246

Reset and clock control (RCC) RM0471

Address offset: 0x008

Reset value: 0x0007 0000 (after POR reset), 0x0007 0001 (after wakeup from Standby).

Access: 0  wait state  2, word, half-word and byte access

One or two wait states inserted only if the access occurs during clock source switch.

From 0 to 15 wait states inserted if the access occurs when the APB or AHB prescalers values update is on going.

Res.

STOP

WUCK rw

30 29 28 rw

MCOPRE[2:0] rw rw

14 13 12

Res.

PPRE2[2:0]

27 rw

11 rw rw rw

26 25

MCOSEL[3:0] rw rw

10 9

PPRE1[2:0]

24 rw

8 rw rw rw

Res.

6 5

HPRE[3:0] rw rw

Res.

19 18 17 16

Res.

PPRE2F PPRE1F HPREF r r r

3 2 1 0

SWS[1:0] SW[1:0] r r rw rw rw rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:28 MCOPRE[2:0]: Microcontroller clock output prescaler

These bits are set and cleared by software.

It is highly recommended to change this prescaler before MCO output is enabled.

000: MCO is divided by 1

001: MCO is divided by 2

010: MCO is divided by 4

011: MCO is divided by 8

100: MCO is divided by 16

Others: not allowed

Bits 27:24 MCOSEL[3:0]: Microcontroller clock output

Set and cleared by software.

0000: MCO output disabled, no clock on MCO

0001: SYSCLK system clock selected

0010: MSI clock selected.

0011: HSI16 clock selected.

0100: HSE clock selected (after stabilization, after HSERDY = 1)

0101: Main PLLRCLK clock selected

0110: LSI1 clock selected

0111: LSI2 clock selected

1000: LSE clock selected

1001: Internal HSI48 clock selected

1100: HSE clock selected (before stabilization, after HSEON = 1)

Others: Reserved

Note: This clock output may have some truncated cycles at startup or during MCO clock source switching.

Bits 23:19 Reserved, must be kept at reset value.

194/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Bit 18 PPRE2F: PCLK2 prescaler flag (APB2)

Set and reset by hardware to acknowledge PCLK2 prescaler programming

Reset when a new prescaler value is programmed in PPRE2. set when the programmed value is actually applied.

0: PCLK2 prescaler value not yet applied

1: PCLK2 prescaler value applied

Bit 17 PPRE1F: PCLK1 prescaler flag (APB1)

Set and reset by hardware to acknowledge PCLK1 prescaler programming

Reset when a new prescaler value is programmed in PPRE1. set when the programmed value is actually applied.

0: PCLK1 prescaler value not yet applied

1: PCLK1 prescaler value applied

Bit 16 HPREF: HCLK1 prescaler flag (CPU1, AHB1, AHB2, AHB3 and SRAM1)

Set and reset by hardware to acknowledge HCLK1 prescaler programming

Reset when a new prescaler value is programmed in HPRE. set when the programmed value is actually applied.

0: HCLK1 prescaler value not yet applied

1: HCLK1 prescaler value applied

Bit 15 STOPWUCK: Wakeup from Stop and CSS backup clock selection

Set and cleared by software to select the system clock used when exiting Stop mode.

The selected clock is also used as emergency clock for the clock security system on HSE.

Warning: STOPWUCK must not be modified when the HSE clock security system is enabled by CSSON in

RCC clock control register (RCC_CR)

(SWS = 10) or a switch on HSE is requested (SW= 10).

0: MSI oscillator selected as wakeup from stop clock and CSS backup clock.

1: HSI16 oscillator selected as wakeup from stop clock and CSS backup clock

Bit 14 Reserved, must be kept at reset value

Bits 13:11 PPRE2[2:0]: PCLK2 high-speed prescaler (APB2)

Set and cleared by software to control the division factor of the PCLK2 clock (APB2).

The PPRE2F flag can be checked to know if the programmed PPRE2 prescaler value is applied.

0xx: HCLK1 not divided

100: HCLK1 divided by 2

101: HCLK1 divided by 4

110: HCLK1 divided by 8

111: HCLK1 divided by 16

Bits 10:8 PPRE1[2:0]: PCLK1 low-speed prescaler (APB1)

Set and cleared by software to control the division factor of the PCLK1 clock (APB1).

The PPRE1F flag can be checked to know if the programmed PPRE1 prescaler value is applied.

0xx: HCLK1 not divided

100: HCLK1 divided by 2

101: HCLK1 divided by 4

110: HCLK1 divided by 8

111: HCLK1 divided by 16

RM0471 Rev 5 195/1202

246

Reset and clock control (RCC) RM0471

Note:

Bits 7:4 HPRE[3:0]: HCLK1 prescaler (CPU1, AHB1, AHB2, AHB3 and SRAM1.)

Set and cleared by software to control the division factor of the HCLK1 clock (CPU1, AHB1,

AHB2, AHB3 and SRAM1).

The HPREF flag can be checked to know if the programmed HPRE prescaler value is applied.

Caution: The software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details refer to

Section 7.2.10: Clock source frequency ). After a write operation to these bits the

0001: SYSCLK divided by 3

0010: SYSCLK divided by 5

0101: SYSCLK divided by 6

0110: SYSCLK divided by 10

0111: SYSCLK divided by 32

1000: SYSCLK divided by 2

1001: SYSCLK divided by 4

1010: SYSCLK divided by 8

1011: SYSCLK divided by 16

1100: SYSCLK divided by 64

1101: SYSCLK divided by 128

1110: SYSCLK divided by 256

1111: SYSCLK divided by 512

Others: SYSCLK not divided

Bits 3:2 SWS[1:0]: System clock switch status

Set and cleared by hardware to indicate which clock source is used as system clock.

00: MSI oscillator used as system clock

01: HSI16 oscillator used as system clock

10: HSE used as system clock

11: PLL used as system clock

Bits 1:0 SW[1:0]: System clock switch

Set and cleared by software to select system clock source (SYSCLK).

Configured by HW to force MSI oscillator selection when exiting Shutdown mode.

Configured by HW to force HSI16 oscillator selection when exiting Standby mode.

Configured by HW to force MSI or HSI16 oscillator selection when exiting Stop mode or in case of failure of the HSE oscillator, depending on STOPWUCK value.

00: MSI selected as system clock

01: HSI16 selected as system clock

10: HSE selected as system clock

11: PLL selected as system clock

The latency when changing SW and SWS bits is set according to the new configuration when switching the SYSCLK clock source, in a maximum of three cycles of the previous clock.

7.4.4 RCC configuration register (RCC_PLLCFGR)

Address offset: 0x00C

Reset value: 0x2204 0100

Access: No wait state, word, half-word and byte access

196/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

This register is used to configure the PLL clock outputs according to the following formulas:

 f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)

 f(PLL_P) = f(VCO clock) / PLLP

 f(PLL_Q) = f(VCO clock) / PLLQ

 f(PLL_R) = f(VCO clock) / PLLR

31 rw

Res.

PLLR[2:0] rw

29 rw

13 rw rw

PLLREN rw

27 rw

PLLN[6:0]

PLLQ[2:0] rw

10 rw rw rw

25 rw

9 rw

PLLQEN Res.

Res.

21 20

6 rw rw

PLLM[2:0] rw rw

4 rw

PLLP[4:0] rw

Res.

18 rw

Res.

17 16

PLLPEN rw rw

1 0

PLLSRC[1:0] rw rw

Bits 31:29 PLLR[2:0]: Main PLL division factor for PLLRCLK

Set and cleared by software to control the frequency of the main PLL output clock PLLRCLK.

This output can be selected as system clock. These bits can be written only if the PLL is disabled.

PLLRCLK output clock frequency = VCO frequency / PLLR with PLLR = 2, 3, 4,... or 8

[VCO frequency / (N + 1)]

000: reserved

001: PLLR = 2

010: PLLR = 3

011: PLLR = 4

100: PLLR = 5

101: PLLR = 6

110: PLLR = 7

111: PLLR = 8

The software has to set these bits so that 64 MHz is not exceeded on this domain.

Bit 28 PLLREN: Main PLL PLLRCLK output enable

Set and reset by software to enable the PLLRCLK output of the main PLL (used as system clock).

This bit cannot be written when PLLRCLK output of the PLL is used as System clock.

To save power, when the PLLRCLK output of the PLL is not used, the value of PLLREN should be 0.

0: PLLRCLK output disabled

1: PLLRCLK output enabled

RM0471 Rev 5 197/1202

246

Reset and clock control (RCC) RM0471

Bits 27:25 PLLQ[2:0]: Main PLL division factor for PLLQCLK

Set and cleared by software to control the frequency of the main PLL output clock

PLLQCLK. This output can be selected for True RNG clock. These bits can be written only if

PLL is disabled.

PLLQCLK output clock frequency = VCO frequency / PLLQ with PLLQ = 2, 3, 4,... or 8 [VCO frequency / (N + 1)]

000: reserved

001: PLLQ = 2

010: PLLQ = 3

011: PLLQ = 4

100: PLLQ = 5

101: PLLQ = 6

110: PLLQ = 7

111: PLLQ = 8

The software has to set these bits so that 64 MHz is not exceeded on this domain.

Bit 24 PLLQEN: Main PLL PLLQCLK output enable

Set and reset by software to enable the PLLQCLK output of the main PLL (used as system clock).

In order to save power, when the PLLQCLK output of the PLL is not used, the value of

PLLQEN should be 0.

0: PLLQCLK output disable

1: PLLQCLK output enable

Bits 23:22 Reserved, must be kept at reset value.

Bits 21:17 PLLP[4:0]: Main PLL division factor for PLLPCLK.

Set and cleared by software to control the frequency of the main PLL output clock PLLPCLK.

This output can be selected for ADC. These bits can be written only if PLL is disabled.

PLLPCLK output clock frequency = VCO frequency / PLLP with PLLP = 2, 3, 4,... or 32 [VCO frequency / (N + 1)]

0000: reserved

00001: PLLP = 2

00010: PLLP = 3

00011: PLLP = 4

00100: PLLP = 5

...

11111: PLLP = 32

The software has to set these bits so that 64 MHz is not exceeded on this domain.

Bit 16 PLLPEN: Main PLL PLLPCLK output enable

Set and reset by software to enable the PLLPCLK output of the main PLL.

In order to save power, when the PLLPCLK output of the PLL is not used, the value of

PLLPEN should be 0.

0: PLLPCLK output disable

1: PLLPCLK output enable

Bit 15 Reserved, must be kept at reset value.

198/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

7.4.5

Bits 14:8 PLLN[6:0]: Main PLL multiplication factor for VCO

Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled.

VCO output frequency = VCO input frequency x PLLN with 6 ≤ PLLN ≤ 127

0000000: PLLN = 0 reserved (must not be used)

0000001: PLLN = 1 reserved (must not be used)

...

0000101: PLLN = 5 reserved (must not be used)

0000110: PLLN = 6

1111111: PLLN = 127

The software has to set these bits to ensure that the VCO output frequency is between 96 and

344 MHz.

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 PLLM: Division factor for the main PLL

Set and cleared by software to divide the PLL input clock before the VCO. These bits can be written only when the PLLis disabled.

VCO input frequency = PLL input clock frequency / PLLM with 1 ≤ PLLM ≤ 8

000: PLLM = 1

001: PLLM = 2

010: PLLM = 3

011: PLLM = 4

100: PLLM = 5

101: PLLM = 6

110: PLLM = 7

111: PLLM = 8

The software has to set these bits to ensure that the VCO input frequency ranges from 2.66 to

16 MHz.

Bits 3:2 Reserved, must be kept at reset value.

Bits 1:0 PLLSRC: Main PLL entry clock source

Set and cleared by software to select PLL clock source. These bits can be written only when

PLLis disabled.

In order to save power, when no PLL is used, the value of PLLSRC should be 00.

00: No clock sent to PLL

01: MSI clock selected as PLL clock entry

10: HSI16 clock selected as PLL clock entry

11: HSE clock selected as PLL clock entry

RCC clock interrupt enable register (RCC_CIER)

Address offset: 0x018

Reset value: 0x0000 0000

Access: No wait state, word, half-word and byte access

RM0471 Rev 5 199/1202

246

Reset and clock control (RCC) RM0471

Res.

LSI2

RDYIE rw

HSI48

RDYIE rw

LSE

CSSIE rw

Res.

PLL

RDYIE rw

HSE

RDYIE rw

HSI

RDYIE rw

MSI

RDYIE rw

LSE

RDYIE rw

LSI1

RDYIE rw

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 LSI2RDYIE: LSI2 ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the LSI2 oscillator stabilization.

0: LSI2 ready interrupt disabled

1: LSI2 ready interrupt enabled

Bit 10 HSI48RDYIE: HSI48 ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the internal HSI48 oscillator.

0: HSI48 ready interrupt disabled

1: HSI48 ready interrupt enabled

Bit 9 LSECSSIE: LSE clock security system interrupt enable

Set and cleared by software to enable/disable interrupt caused by the clock security system on LSE.

0: Clock security interrupt caused by LSE clock failure disabled

1: Clock security interrupt caused by LSE clock failure enabled

Bits 8:6 Reserved, must be kept at reset value.

Bit 5 PLLRDYIE: PLL ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by PLL lock.

0: PLL lock interrupt disabled

1: PLL lock interrupt enabled

Bit 4 HSERDYIE: HSE ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization.

0: HSE ready interrupt disabled

1: HSE ready interrupt enabled

Bit 3 HSIRDYIE: HSI16 ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization.

0: HSI16 ready interrupt disabled

1: HSI16 ready interrupt enabled

Bit 2 MSIRDYIE: MSI ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the MSI oscillator stabilization.

0: MSI ready interrupt disabled

1: MSI ready interrupt enabled

200/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Bit 1 LSERDYIE: LSE ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization.

0: LSE ready interrupt disabled

1: LSE ready interrupt enabled

Bit 0 LSI1RDYIE: LSI1 ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the LSI1 oscillator stabilization.

0: LSI1 ready interrupt disabled

1: LSI1 ready interrupt enabled

Address offset: 0x01C

Reset value: 0x0000 0000

Access: No wait state, word, half-word and byte access

Res.

LSI2

RDYF r

HSI48R

DYF r

LSE

CSSF r

Res.

PLL

RDYF r

HSE

RDYF r

HSI

RDYF r

MSI

RDYF r

LSE

RDYF r

LSI1

RDYF r

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 LSI2RDYF: LSI2 ready interrupt flag

Set by hardware when the LSI2 clock becomes stable and LSI2RDYDIE is set.

Cleared by software setting the LSI2RDYC bit.

0: No clock ready interrupt caused by the LSI2 oscillator

1: Clock ready interrupt caused by the LSI2 oscillator

Bit 10 HSI48RDYF: HSI48 ready interrupt flag

Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set in a

response to setting the HSI48ON (refer to RCC clock recovery RC register (RCC_CRRCR)

Cleared by software setting the HSI48RDYC bit.

0: No clock ready interrupt caused by the HSI48 oscillator

1: Clock ready interrupt caused by the HSI48 oscillator

Bit 9 LSECSSF: LSE clock security system interrupt flag

Set by hardware when a failure is detected in the LSE oscillator.

Cleared by software setting the LSECSSC bit.

0: No clock security interrupt caused by LSE clock failure

1: Clock security interrupt caused by LSE clock failure

Bit 8 CSSF: HSE clock security system interrupt flag

Set by hardware when a failure is detected in the HSE oscillator.

Cleared by software setting the CSSC bit.

0: No clock security interrupt caused by HSE clock failure

1: Clock security interrupt caused by HSE clock failure

RM0471 Rev 5 201/1202

246

Reset and clock control (RCC) RM0471

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 PLLRDYF: PLL ready interrupt flag

Set by hardware when the PLL locks and PLLRDYDIE is set.

Cleared by software setting the PLLRDYC bit.

0: No clock ready interrupt caused by PLL lock

1: Clock ready interrupt caused by PLL lock

Bit 4 HSERDYF: HSE ready interrupt flag

Set by hardware when the HSE clock becomes stable and HSERDYDIE is set.

Cleared by software setting the HSERDYC bit.

0: No clock ready interrupt caused by the HSE oscillator

1: Clock ready interrupt caused by the HSE oscillator

Bit 3 HSIRDYF: HSI16 ready interrupt flag

Set by hardware when the HSI16 clock becomes stable and HSIRDYDIE is set in a

response to setting the HSION (refer to RCC clock control register (RCC_CR) ). When

HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.

Cleared by software setting the HSIRDYC bit.

0: No clock ready interrupt caused by the HSI16 oscillator

1: Clock ready interrupt caused by the HSI16 oscillator

Bit 2 MSIRDYF: MSI ready interrupt flag

Set by hardware when the MSI clock becomes stable and MSIRDYDIE is set.

Cleared by software setting the MSIRDYC bit.

0: No clock ready interrupt caused by the MSI oscillator

1: Clock ready interrupt caused by the MSI oscillator

Bit 1 LSERDYF: LSE ready interrupt flag

Set by hardware when the LSE clock becomes stable and LSERDYDIE is set.

Cleared by software setting the LSERDYC bit.

0: No clock ready interrupt caused by the LSE oscillator

1: Clock ready interrupt caused by the LSE oscillator

Bit 0 LSI1RDYF: LSI1 ready interrupt flag

Set by hardware when the LSI1 clock becomes stable and LSI1RDYDIE is set.

Cleared by software setting the LSI1RDYC bit.

0: No clock ready interrupt caused by the LSI1 oscillator

1: Clock ready interrupt caused by the LSI1 oscillator

Address offset: 0x020

Reset value: 0x0000 0000

Access: No wait state, word, half-word and byte access

202/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Res.

LSI2

RDYC w

HSI48

RDYC w

LSE

CSSC w

8 7

CSSC Res.

Res.

PLL

RDYC w

HSE

RDYC w

HSI

RDYC w

MSI

RDYC w

LSE

RDYC w

LSI1

RDYC w

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 LSI2RDYC: LSI2 ready interrupt clear

This bit is set by software to clear the LSI2RDYF flag.

0: No effect

1: LSI2RDYF cleared

Bit 10 HSI48RDYC: HSI48 oscillator ready interrupt clear

This bit is set by software to clear the HSI48RDYF flag.

0: No effect

1: Clear the HSI48RDYC flag

Bit 9 LSECSSC: LSE clock security system interrupt clear

This bit is set by software to clear the LSECSSF flag.

0: No effect

1: Clear LSECSSF flag

Bit 8 CSSC: HSE clock security system interrupt clear

This bit is set by software to clear the HSE CSSF flag.

0: No effect

1: Clear HSE CSSF flag

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 PLLRDYC: PLL ready interrupt clear

This bit is set by software to clear the PLLRDYF flag.

0: No effect

1: Clear PLLRDYF flag

Bit 4 HSERDYC: HSE ready interrupt clear

This bit is set by software to clear the HSERDYF flag.

0: No effect

1: Clear HSERDYF flag

Bit 3 HSIRDYC: HSI16 ready interrupt clear

This bit is set software to clear the HSIRDYF flag.

0: No effect

1: Clear HSIRDYF flag

Bit 2 MSIRDYC: MSI ready interrupt clear

This bit is set by software to clear the MSIRDYF flag.

0: No effect

1: MSIRDYF cleared

Bit 1 LSERDYC: LSE ready interrupt clear

This bit is set by software to clear the LSERDYF flag.

0: No effect

1: LSERDYF cleared

RM0471 Rev 5 203/1202

246

Reset and clock control (RCC)

Bit 0 LSI1RDYC: LSI1 ready interrupt clear

This bit is set by software to clear the LSI1RDYF flag.

0: No effect

1: LSI1RDYF cleared

RM0471

Res.

Address offset: 0x028

Reset value: 0x00000 0000

Access: No wait state, word, half-word and byte access

Res.

CRC

RST rw

Res.

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 CRCRST: CRC reset

Set and cleared by software.

0: No effect

1: Reset CRC

Bits 11:3 Reserved, must be kept at reset value.

Bit 2 DMAMUX1RST: DMAMUX reset

Set and cleared by software.

0: No effect

1: Reset DMAMUX1

Bit 1 Reserved, must be kept at reset value.

Bit 0 DMA1RST: DMA1 reset

Set and cleared by software.

0: No effect

1: Reset DMA1

Res.

DMAMUX1

RST rw

Res.

DMA1

RST rw

Address offset: 0x02C

Reset value: 0x00000 0000

Access: No wait state, word, half-word and byte access

204/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Res.

ADC

RST rw

Res.

GPIOH

RST rw

Res.

Bits 31:148 Reserved, must be kept at reset value.

Bit 13 ADCRST: ADC reset

Set and cleared by software.

0: No effect

1: Reset ADC interface

Bits 12:8 Reserved, must be kept at reset value.

Bit 7 GPIOHRST: IO port H reset

Set and cleared by software.

0: No effect

1: Reset IO port H

Bits 6:5 Reserved, must be kept at reset value.

Bit 4 GPIOERST: IO port E reset

Set and cleared by software.

0: No effect

1: Reset IO port E

Bit 3 Reserved, must be kept at reset value.

Bit 2 GPIOCRST: IO port C reset

Set and cleared by software.

0: No effect

1: Reset IO port C

Bit 1 GPIOBRST: IO port B reset

Set and cleared by software.

0: No effect

1: Reset IO port B

Bit 0 GPIOARST: IO port A reset

Set and cleared by software.

0: No effect

1: Reset IO port A

Res.

GPIOE

RST rw

Res.

GPIOC

RST rw

GPIOB

RST

GPIOA

RST rw rw

7.4.10 RCC AHB3 and AHB4 peripheral reset register (RCC_AHB3RSTR)

Address offset: 0x030

Reset value: 0x00000 0000

Access: No wait state, word, half-word and byte access

RM0471 Rev 5 205/1202

246

Reset and clock control (RCC) RM0471

Res.

FLASH

RST rw

Res.

IPCC

RST rw

Res.

HSEM

RST rw

Res.

RNG

RST rw

Res.

AES2

RST rw

Res.

PKA

RST rw

Res.

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 FLASHRST: Flash interface reset

This bit can only be set when the Flash memory is in power-down. Set and cleared by software.

0: No effect

1: Reset Flash interface.

Bits 24:21 Reserved, must be kept at reset value.

Bit 20 IPCCRST: IPCC interface reset

Set and cleared by software.

0: No effect

1: Reset IPCC

Bit 19 HSEMRST: HSEM reset

Set and cleared by software.

0: No effect

1: Reset HSEM

Bit 18 RNGRST: True RNG reset

Set and cleared by software.

0: No effect

1: Reset True RNG

Bit 17 AES2RST: AES2 hardware accelerator reset

Set and cleared by software.

0: No effect

1: Reset AES2

Bit 16 PKARST: PKA hardware accelerator reset

Set and cleared by software.

0: No effect

1: Reset PKA

Bits 15:0 Reserved, must be kept at reset value.

7.4.11 RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1)

Address offset: 0x038

Reset value: 0x0000 0000

Access: No wait state, word, half-word and byte access

206/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

LPTIM1

RST rw

Res.

I2C1

RST rw

Res.

Bit 31 LPTIM1RST: Low power timer 1 reset

Set and cleared by software.

0: No effect

1: Reset LPTIM1

Bits 30:22 Reserved, must be kept at reset value.

Bit 21 I2C1RST: I2C1 reset

Set and cleared by software.

0: No effect

1: Reset I2C1

Bits 20:1 Reserved, must be kept at reset value.

Bit 0 TIM2RST: TIM2 timer reset

Set and cleared by software.

0: No effect

1: Reset TIM2

7.4.12 RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2)

Address offset: 0x03C

Reset value: 0x00000 0000

Access: No wait state, word, half-word and byte access

Res.

TIM2

RST rw

Res.

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 LPTIM2RST: Low-power timer 2 reset

Set and cleared by software.

0: No effect

1: Reset LPTIM2

Bits 4:0 Reserved, must be kept at reset value.

Res.

LPTIM2

RST rw

Res.

7.4.13 RCC APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x040

Res.

RM0471 Rev 5 207/1202

246

Reset and clock control (RCC) RM0471

Res.

Reset value: 0x00000 0000

Access: No wait state, word, half-word and byte access

Res.

TIM17

RST rw

Res.

TIM16

RST rw

Res.

USART1

RST rw

Res.

SPI1

RST rw

TIM1

RST rw

Res.

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 TIM17RST: TIM17 timer reset

Set and cleared by software.

0: No effect

1: Reset TIM17 timer

Bit 17 TIM16RST: TIM16 timer reset

Set and cleared by software.

0: No effect

1: Reset TIM16 timer

Bits 16:15 Reserved, must be kept at reset value.

Bit 14 USART1RST: USART1 reset

Set and cleared by software.

0: No effect

1: Reset USART1

Bit 13 Reserved, must be kept at reset value.

Bit 12 SPI1RST: SPI1 reset

Set and cleared by software.

0: No effect

1: Reset SPI1

Bit 11 TIM1RST: TIM1 timer reset

Set and cleared by software.

0: No effect

1: Reset TIM1 timer

Bits 10:0 Reserved, must be kept at reset value.

Res.

7.4.14 RCC APB3 peripheral reset register (RCC_APB3RSTR)

Address offset: 0x044

Reset value: 0x00000 0000

Access: No wait state, word, half-word and byte access

208/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Res.

1 0

Res.

RFRST rw

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 RFRST: Radio system BLE and 802.15.4 reset.

Set and cleared by software.

0: No effect

1: Reset radio system BLE and 802.15.4. The reset status of the radio system can be obtained from RFRSTS in

RCC control/status register (RCC_CSR) .

7.4.15 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)

Note:

Address offset: 0x048

Reset value: 0x0000 0000

Access: No wait state, word, half-word and byte access

When the peripheral clock is not active, the peripheral registers read or write access from

CPU1 is not supported.

31 30 29

Res.

27 26 25 24

Res.

23 22 21 20 19

Res.

15 14 13 12 11 10 9 8

Res.

CRCEN Res.

Res.

7 6 5 4 3 2

Res.

DMAMUX1EN rw

Res.

DMA1EN rw

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 CRCEN: CPU1 CRC clock enable

Set and cleared by software.

0: CRC clock disable for CPU1

1: CRC clock enable for CPU1

Bits 11:3 Reserved, must be kept at reset value.

Bit 2 DMAMUX1: CPU1 DMAMUX1 clock enable

Set and cleared by software.

0: DMAMUX1 clock disable for CPU1

1: DMAMUX1 clock enable for CPU1

Bit 1 Reserved, must be kept at reset value.

Bit 0 DMA1EN: CPU1 DMA1 clock enable

Set and cleared by software.

0: DMA1 clock disable for CPU1

1: DMA1 clock enable for CPU1

RM0471 Rev 5 209/1202

246

Reset and clock control (RCC) RM0471

7.4.16 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)

Note:

Address offset: 0x04C

Reset value: 0x0000 0000

Access: No wait state, word, half-word and byte access

When the peripheral clock is not active, the peripheral registers read or write access from

CPU1 is not supported.

Res.

ADC

EN rw

Res.

GPIOH

EN rw

Res.

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 ADCEN: CPU1 ADC clocks enable

Set and cleared by software.

0: ADC bus and kernel clocks disabled for CPU1

1: ADC bus and kernel clocks enabled for CPU1

Bits 12:8 Reserved, must be kept at reset value.

Bit 7 GPIOHEN: CPU1 IO port H clock enable

Set and cleared by software.

0: IO port H clock disabled for CPU1

1: IO port H clock enabled for CPU1

Bits 6:5 Reserved, must be kept at reset value.

Bit 4 GPIOEEN: CPU1 IO port E clock enable

Set and cleared by software.

0: IO port E clock disabled for CPU1

1: IO port E clock enabled for CPU1

Bit 3 Reserved, must be kept at reset value.

Bit 2 GPIOCEN: CPU1 IO port C clock enable

Set and cleared by software.

0: IO port C clock disabled for CPU1

1: IO port C clock enabled for CPU1

Bit 1 GPIOBEN: CPU1 IO port B clock enable

Set and cleared by software.

0: IO port B clock disabled for CPU1

1: IO port B clock enabled for CPU1

Bit 0 GPIOAEN: CPU1 IO port A clock enable

Set and cleared by software.

0: IO port A clock disabled for CPU1

1: IO port A clock enabled for CPU1

Res.

GPIOE

EN rw

Res.

GPIOC

EN rw

GPIOB

EN rw

GPIOA

EN rw

210/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

7.4.17 RCC AHB3 and AHB4 peripheral clock enable register

(RCC_AHB3ENR)

Note:

Address offset: 0x050

Reset value: 0x0208 0000

Access: No wait state, word, half-word and byte access

When the peripheral clock is not active, the peripheral registers read or write access from

CPU1 is not supported.

Res.

FLASH

EN rw

Res.

IPCC

EN rw

Res.

HSEM

EN rw

Res.

RNG

EN rw

Res.

AES2

EN rw

Res.

PKA

EN rw

Res.

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 FLASHEN CPU1 Flash memory interface clock enable

This bit can only be cleared when the Flash memory is in Power down. Set and cleared by software.

0: Flash interface clock disable for CPU1

1: Flash interface clock enable for CPU1

Bits 24:21 Reserved, must be kept at reset value.

Bit 20 IPCCEN CPU1 IPCC interface clock enable

Set and cleared by software.

0: IPCC clock disable for CPU1

1: IPCC clock enable for CPU1

Bit 19 HSEMEN CPU1 HSEM clock enable

Set and cleared by software.

0: HSEM clock disable for CPU1

1: HSEM clock enable for CPU1

Bit 18 RNGEN CPU1 True RNG clocks enable

Set and cleared by software.

0: True RNG bus and kernel clocks disable for CPU1

1: True RNG bus and kernel clocks enable for CPU1

Bit 17 AES2EN CPU1 AES2 accelerator clock enable

Set and cleared by software.

0: AES2 clock disable for CPU1

1: AES2 clock enable for CPU1

Bit 16 PKAEN CPU1 PKA accelerator clock enable

Set and cleared by software.

0: PKA clock disable for CPU1

1: PKA clock enable for CPU1

Bits 15:0 Reserved, must be kept at reset value.

RM0471 Rev 5 211/1202

246

Reset and clock control (RCC) RM0471

7.4.18 RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1)

Note:

Address: 0x058

Reset value: 0x0000 0400

Access: No wait state, word, half-word and byte access

When the peripheral clock is not active, the peripheral registers read or write access from

CPU1 is not supported.

LPTIM1

EN rw

Res.

WWDG

EN rs

RTCAPB

EN rw

Res.

I2C1

EN rw

Res.

TIM2

EN rw

Bit 31 LPTIM1EN: CPU1 Low power timer 1 clocks enable

Set and cleared by software.

0: LPTIM1 bus and kernel clocks disabled for CPU1

1: LPTIM1 bus and kernel clocks enabled for CPU1

Bits 30:22 Reserved, must be kept at reset value.

Bit 21 I2C1EN: CPU1 I2C1 clocks enable

Set and cleared by software.

0: I2C1 bus and kernel clocks disabled for CPU1

1: I2C1 bus and kernel clocks enabled for CPU1

Bits 20:12 Reserved, must be kept at reset value.

Bit 11 WWDGEN: CPU1 Window watchdog clock enable

Set by software to enable the window watchdog clock. Reset by hardware system reset.

This bit can also be set by hardware if the WWDG_SW option bit is reset.

0: Window watchdog clock disabled for CPU1

1: Window watchdog clock enabled for CPU1

Bit 10 RTCAPBEN: CPU1 RTC APB clock enable

Set and cleared by software

0: RTC APB clock disabled for CPU1

1: RTC APB clock enabled for CPU1

Bits 9:1 Reserved, must be kept at reset value.

Bit 0 TIM2EN: CPU1 TIM2 timer clock enable

Set and cleared by software.

0: TIM2 clock disabled for CPU1

1: TIM2 clock enabled for CPU1

7.4.19 RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2)

Address offset: 0x05C

Reset value: 0x00000 0000

Access: No wait state, word, half-word and byte access

212/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Note:

Res.

When the peripheral clock is not active, the peripheral registers read or write access from

CPU1 is not supported.

Res.

LPTIM2

EN rw

Res.

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 LPTIM2EN CPU1 Low power timer 2 clocks enable

Set and cleared by software.

0: LPTIM2 bus and kernel clocks disabled for CPU1

1: LPTIM2 bus and kernel clocks enabled for CPU1

Bits 4:0 Reserved, must be kept at reset value.

Res.

7.4.20 RCC APB2 peripheral clock enable register (RCC_APB2ENR)

Note:

Address: 0x060

Reset value: 0x0000 0000

Access: word, half-word and byte access

When the peripheral clock is not active, the peripheral registers read or write access from

CPU1 is not supported.

Res.

USART1

EN rw

Res.

SPI1

EN rw

Res.

TIM1

EN rw

Res.

TIM17

EN rw

TIM16

EN rw

Res.

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 TIM17EN: CPU1 TIM17 timer clock enable

Set and cleared by software.

0: TIM17 timer clock disabled for CPU1

1: TIM17 timer clock enabled for CPU1

Bit 17 TIM16EN: CPU1 TIM16 timer clock enable

Set and cleared by software.

0: TIM16 timer clock disabled for CPU1

1: TIM16 timer clock enabled for CPU1

Bits 16:15 Reserved, must be kept at reset value.

RM0471 Rev 5 213/1202

246

Reset and clock control (RCC) RM0471

Bit 14 USART1EN: CPU1 USART1 clocks enable

Set and cleared by software.

0: USART1 bus and kernel clocks disabled for CPU1

1: USART1 bus and kernel clocks enabled for CPU1

Bit 13 Reserved, must be kept at reset value.

Bit 12 SPI1EN: CPU1 SPI1 clock enable

Set and cleared by software.

0: SPI1 clock disabled for CPU1

1: SPI1 clock enabled for CPU1

Bit 11 TIM1EN: CPU1 TIM1 timer clock enable

Set and cleared by software.

0: TIM1 timer clock disabled for CPU1

1: TIM1P timer clock enabled for CPU1

Bits 10:0 Reserved, must be kept at reset value.

7.4.21 RCC AHB1 peripheral clocks enable in Sleep modes register

(RCC_AHB1SMENR)

Address offset: 0x068

Reset value: 0x0001 1207

Access: No wait state, word, half-word and byte access

Res.

CRC

SMEN rw

Res.

SRAM1

SMEN rw

Res.

DMAMUX1

SMEN rw

Res.

DMA1

SMEN rw

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 CRCSMEN: CRC clock enable during CPU1 CSleep mode

Set and cleared by software.

0: CRC clock disabled by the clock gating during CPU1 Csleep and CStop modes

1: CRC clock enabled by the clock gating during CPU1 CSleep mode, disabled during CPU1

CStop mode

Bits 11:10 Reserved, must be kept at reset value.

Bit 9 SRAM1SMEN: SRAM1 interface clock enable during CPU1 CSleep mode

Set and cleared by software.

0: SRAM1 interface clock disabled by the clock gating during CPU1 Csleep and CStop modes

1: SRAM1 interface clock enabled by the clock gating during CPU1 CSleep mode, disabled during CPU1 CStop mode

Bits 8:3 Reserved, must be kept at reset value.

214/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Bit 2 DMAMUX1SMEN: DMAMUX1 clock enable during CPU1 CSleep mode

Set and cleared by software during Sleep mode.

0: DMAMUX1 clock disabled by the clock gating during CPU1 Csleep and CStop modes

1: DMAMUX1 clock enabled by the clock gating during CPU1 CSleep mode, disabled during

CPU1 CStop mode

Bit 1 Reserved, must be kept at reset value.

Bit 0 DMA1SMEN: DMA1 clock enable during CPU1 CSleep mode

Set and cleared by software.

0: DMA1 clock disabled by the clock gating during CPU1 Csleep and CStop modes

1: DMA1 clock enabled by the clock gating during CPU1 CSleep mode, disabled during

CPU1 CStop mode.

7.4.22 RCC AHB2 peripheral clocks enable in Sleep modes register

(RCC_AHB2SMENR)

Address offset: 0x06C

Reset value: 0x0001 209F

Access: No wait state, word, half-word and byte access

Res.

ADC

SMEN rw

Res.

GPIOH

SMEN rw

Res.

GPIOE

SMEN rw

Res.

GPIOC

SMEN rw

GPIOB

SMEN rw

GPIOA

SMEN rw

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 ADCSMEN: ADC clock enable during CPU1 Csleep and CStop modes

Set and cleared by software.

0: ADC bus clock disabled by the clock gating during CPU1 Csleep and CStop modes.

1: ADC bus clock enabled by the clock gating during CPU1 CSleep mode, disabled during

CPU1 CStop mode.

Bits 12:8 Reserved, must be kept at reset value.

Bit 7 GPIOHSMEN: IO port H clock enable during CPU1 CSleep mode

Set and cleared by software.

0: IO port H clock disabled by the clock gating during CPU1 Csleep and CStop modes

1: IO port H clock enabled by the clock gating during CPU1 CSleep mode, disabled during

CPU1 CStop mode.

Bits 6:5 Reserved, must be kept at reset value.

Bit 4 GPIOESMEN: IO port E clock enable during CPU1 CSleep mode

Set and cleared by software.

0: IO port E clock disabled by the clock gating during CPU1 Csleep and CStop modes

1: IO port E clock enabled by the clock gating during CPU1 CSleep mode, disabled during

CPU1 CStop mode

Bit 3 Reserved, must be kept at reset value.

RM0471 Rev 5 215/1202

246

Reset and clock control (RCC) RM0471

Bit 2 GPIOCSMEN: IO port C clock enable during CPU1 CSleep mode

Set and cleared by software.

0: IO port C clock disabled by the clock gating during CPU1 Csleep and CStop modes

1: IO port C clock enabled by the clock gating during CPU1 CSleep mode, disabled during

CPU1 CStop mode

Bit 1 GPIOBSMEN: IO port B clock enable during CPU1 CSleep mode

Set and cleared by software.

0: IO port B clock disabled by the clock gating during CPU1 Csleep and CStop modes

1: IO port B clock enabled by the clock gating during CPU1 CSleep mode, disabled during

CPU1 CStop mode

Bit 0 GPIOASMEN: IO port A clock enable during CPU1 CSleep mode

Set and cleared by software.

0: IO port A clock disabled by the clock gating during CPU1 Csleep and CStop modes

1: IO port A clock enabled by the clock gating during CPU1 CSleep mode, disabled during

CPU1 CStop mode.

7.4.23 RCC AHB3 and AHB4 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB3SMENR)

Address offset: 0x070

Reset value: 0x0307 0100

Access: No wait state, word, half-word and byte access

Res.

FLASH

SMEN rw

Res.

SRAM2S

MEN rw

Res.

RNG

SMEN rw

Res.

AES2

SMEN rw

Res.

PKA

SMEN rw

Res.

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 FLASHSMEN: Flash memory interface clock enable during CPU1 CSleep mode

Set and cleared by software.

0: Flash interface clock disabled by the clock gating during CPU1 Csleep and CStop modes

1: Flash interface clock enabled by the clock gating during CPU1 CSleep mode, disabled during CPU1 CStop mode.

Bit 24 SRAM2SMEN: SRAM2a and SRAM2b memory interface clock enable during CPU1 CSleep mode

Set and cleared by software.

0: SRAM2 clock disabled by the clock gating during CPU1 Csleep and CStop modes

1: SRAM2 clock enabled by the clock gating during CPU1 CSleep mode, disabled during

CPU1 CStop mode.

Bits 23:19 Reserved, must be kept at reset value.

216/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Bit 18 RNGSMEN: True RNG clock enable during CPU1 Csleep and CStop modes

Set and cleared by software.

0: True RNG bus clock disabled by the clock gating during CPU1 Csleep and CStop modes

1: True RNG bus clock enabled by the clock gating during CPU1 CSleep mode, disabled during CPU1 CStop mode.

Bit 17 AES2MEN: AES2 accelerator clock enable during CPU1 CSleep mode

Set and cleared by software.

0: AES2 clock disabled by the clock gating during CPU1 Csleep and CStop modes

1: AES2 clock enabled by the clock gating during CPU1 CSleep mode, .disabled during

CPU1 CStop mode

Bit 16 PKASMEN: PKA accelerator clock enable during CPU1 CSleep mode

Set and cleared by software.

0: PKA clock disabled by the clock gating during CPU1 Csleep and CStop modes

1: PKA clock enabled by the clock gating during CPU1 CSleep mode, disabled during CPU1

CStop mode.

Bits 15:0 Reserved, must be kept at reset value.

7.4.24 RCC APB1 peripheral clocks enable in Sleep mode register 1

(RCC_APB1SMENR1)

Address: 0x078

Reset value: 0x85A0 4E01

Access: No wait state, word, half-word and byte access

LPTIM1

SMEN rw

Res.

WWDG

SMEN rw

RTCAPB

SMEN rw

Res.

I2C1

SMEN rw

Res.

TIM2

SMEN rw

Bit 31 LPTIM1SMEN: Low power timer 1 clock enable during CPU1 Csleep and CStop mode

Set and cleared by software.

0: LPTIM1 bus clock disabled by the clock gating during CPU1 Csleep and CStop modes

1: LPTIM1 bus clock enabled by the clock gating during CPU1 CSleep mode, disabled during CPU1 CStop mode.

Bits 30:22 Reserved, must be kept at reset value.

Bit 21 I2C1SMEN: I2C1 clock enable during CPU1 Csleep and CStop modes

Set and cleared by software.

0: I2C1 bus clock disabled by the clock gating during CPU1 Csleep and CStop modes

1: I2C1 bus clock enabled by the clock gating during CPU1 CSleep mode, disabled during

CPU1 CStop mode.

Bits 20:12 Reserved, must be kept at reset value.

RM0471 Rev 5 217/1202

246

Reset and clock control (RCC) RM0471

Bit 11 WWDGSMEN: Window watchdog clocks enable during CPU1 CSleep mode

Set and cleared by software. This bit is forced to ‘1’ by hardware when the hardware

WWDG_SW option is reset.

0: Window watchdog clock disabled by the clock gating during CPU1 Csleep and CStop modes

1: Window watchdog clocks enabled by the clock gating during CPU1 CSleep mode, disabled during CPU1 CStop mode.

Bit 10 RTCAPBSMEN: RTC bus clock enable during CPU1 CSleep mode

Set and cleared by software

0: RTC bus clock disabled during by the clock gating during CPU1 Csleep and CStop modes.

1: RTC bus clock enabled during by the clock gating during CPU1 CSleep mode, disabled during CPU1 CStop mode.

Bits 9:1 Reserved, must be kept at reset value.

Bit 0 TIM2SMEN: TIM2 timer clock enable during CPU1 CSleep mode

Set and cleared by software.

0: TIM2 clock disabled by the clock gating during CPU1 Csleep and CStop modes

1: TIM2 clock enabled by the clock gating during CPU1 CSleep mode, disabled during CPU1

CStop mode.

7.4.25 RCC APB1 peripheral clocks enable in Sleep mode register 2

(RCC_APB1SMENR2)

Address offset: 0x07C

Reset value: 0x0000 0021

Access: No wait state, word, half-word and byte access

Res.

LPTIM2

SMEN rw

Res.

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 LPTIM2SMEN Low power timer 2 clock enable during CPU1 Csleep and CStop modes

Set and cleared by software.

0: LPTIM2 bus clock disabled by the clock gating during CPU1 Csleep and CStop modes.

1: LPTIM2 bus clock enabled by the clock gating during CPU1 CSleep mode, disabled during CPU1 CStop mode.

Bits 4:0 Reserved, must be kept at reset value.

7.4.26 RCC APB2 peripheral clocks enable in Sleep mode register

(RCC_APB2SMENR)

Address: 0x080

Reset value: 0x0026 5800

218/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Access: word, half-word and byte access

Res.

USART1

SMEN rw

Res.

SPI1

SMEN rw

TIM1

SMEN rw

Res.

TIM17

SMEN rw

Res.

TIM16

SMEN rw

Res.

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 TIM17SMEN: TIM17 timer clock enable during CPU1 CSleep mode

Set and cleared by software.

0: TIM17 timer clock disabled by the clock gating during CPU1 Csleep and CStop mode

1: TIM17 timer clocks enabled by the clock gating during CPU1 CSleep mode, disabled during CPU1 CStop mode.

Bit 17 TIM16SMEN: TIM16 timer clock enable during CPU1 CSleep mode

Set and cleared by software.

0: TIM16 timer clock disabled by the clock gating during CPU1 Csleep and CStop mode

1: TIM16 timer clock enabled by the clock gating during CPU1 CSleep mode, disabled during

CPU1 CStop mode

Bits 16:15 Reserved, must be kept at reset value.

Bit 14 USART1SMEN: USART1 clock enable during CPU1 Csleep and CStop modes.

Set and cleared by software.

0: USART1 bus clock disabled by the clock gating during CPU1 Csleep and CStop mode

1: USART1 bus clock enabled by the clock gating during CPU1 CSleep mode, disabled during CPU1 CStop mode.

Bit 13 Reserved, must be kept at reset value.

Bit 12 SPI1SMEN: SPI1 clock enable during CPU1 CSleep mode

Set and cleared by software.

0: SPI1 clock disabled by the clock gating during CPU1 Csleep and CStop mode

1: SPI1 clock enabled by the clock gating during CPU1 CSleep mode, disabled during CPU1

CStop mode.

Bit 11 TIM1SMEN: TIM1 timer clock enable during CPU1 CSleep mode

Set and cleared by software.

0: TIM1 timer clock disabled by the clock gating during CPU1 Csleep and CStop mode

1: TIM1 timer clock enabled by the clock gating during CPU1 CSleep mode, disabled during

CPU1 CStop mode.

Bits 10:0 Reserved, must be kept at reset value.

(RCC_CCIPR)

Address: 0x088

Reset value: 0x0000 0000

Access: no wait states, word, half-word and byte access

RM0471 Rev 5 219/1202

246

Reset and clock control (RCC) RM0471

31 30

RNGSEL[1:0] rw rw

Res.

29 28

ADCSEL[1:0] rw rw

13 12

I2C1SEL[1:0] rw rw

27 26

CLK48SEL[1:0] rw rw

Res.

22 21 20 19 18 17

Res.

LPTIM2SEL[1:0] LPTIM1SEL[1:0] Res.

rw rw rw rw

Res.

USART1SEL[1:0] rw

0 rw

Bits 31:30 RNGSEL[1:0]: RNG clock source selection

These bits are set and cleared by software to select the clock source used by the True RNG.

00: Use clock as selected by CLK48SEL

01: Select LSI clock

10: Select LSE clock

11: Reserved

Bits 29:28 ADCSEL[1:0]: ADC clock source selection

These bits are set and cleared by software to select the clock source used by the ADC interface.

00: No clock selected

01: Reserved

10: PLL “P” clock (PLLPCLK) selected as ADC clock

11: System clock (SYSCLK) selected as ADC clock

Bits 27:26 CLK48SEL[1:0]: 48 MHz clock source selection

These bits are set and cleared by software to select the 48 MHz clock source used by True

RNG. The True RNG clock source selection is furthermore selected by RNGSEL.

00: HSI48 clock selected as 48 MHz clock

01: Reserved

10: PLL “Q” clock (PLLQCLK) selected as 48 MHz clock

11: MSI clock selected as 48 MHz clock

Bits 25:22 Reserved, must be kept at reset value.

Bits 21:20 LPTIM2SEL[1:0]: Low power timer 2 clock source selection

These bits are set and cleared by software to select the LPTIM2 clock source.

00: PCLK selected as LPTIM2 clock

01: LSI clock selected as LPTIM2 clock

10: HSI16 clock selected as LPTIM2 clock

11: LSE clock selected as LPTIM2 clock

Bits 19:18 LPTIM1SEL[1:0]: Low power timer 1 clock source selection

These bits are set and cleared by software to select the LPTIM1 clock source.

00: PCLK selected as LPTIM1 clock

01: LSI clock selected as LPTIM1 clock

10: HSI16 clock selected as LPTIM1 clock

11: LSE clock selected as LPTIM1 clock

Bits 17:14 Reserved, must be kept at reset value.

Bits 13:12 I2C1SEL[1:0]: I2C1 clock source selection

These bits are set and cleared by software to select the I2C1 clock source.

00: PCLK selected as I2C1 clock

01: System clock (SYSCLK) selected as I2C1 clock

10: HSI16 clock selected as I2C1 clock

11: reserved

220/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Bits 11:2 Reserved, must be kept at reset value.

Bits 1:0 USART1SEL[1:0]: USART1 clock source selection

This bit is set and cleared by software to select the USART1 clock source.

00: PCLK selected as USART1 clock

01: System clock (SYSCLK) selected as USART1 clock

10: HSI16 clock selected as USART1 clock

11: LSE clock selected as USART1 clock

7.4.28 RCC backup domain control register (RCC_BDCR)

Note:

Address offset: 0x090

Reset value: 0x0000 0000, (reset by Backup domain Reset, except LSCOSEL, LSCOEN and BDRST which are reset only by Backup domain power-on reset, not reset by wakeup from Standby and NRST pad.)

Access: 0  wait state  3, word, half-word and byte access

Wait states are inserted in case of successive accesses to this register.

The bits of the

RCC backup domain control register (RCC_BDCR) are outside of the V

CORE domain. As a result, after Reset, these bits are write-protected and the DBP bit in the

PWR control register 1 (PWR_CR1)

has to be set before these can be modified. Refer to

Section 6.1.2: Battery backup domain

for further information. These bits (except LSCOSEL,

LSCOEN and BDRST) are only reset after a

Backup domain reset

. Any internal or external

Reset will not have any effect on these bits.

Res.

15 14

RTCEN Res.

Res.

LSCO

SEL rw

RTCSEL[1:0]

LSCO

EN rw

8 rw rw

Res.

LSE

CSSD r

LSE

CSSON rw

4 3

LSEDRV[1:0] rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 LSCOSEL: Low speed clock output selection

Set and cleared by software.

0: LSI clock selected

1: LSE clock selected

Bit 24 LSCOEN: Low speed clock output enable

Set and cleared by software.

0: Low speed clock output (LSCO) disable

1: Low speed clock output (LSCO) enable

Bits 23:17 Reserved, must be kept at reset value.

Bit 16 BDRST: Backup domain software reset

Set and cleared by software.

0: Reset not activated

1: Resets the entire Backup domain

Res.

LSE

BYP rw

17 16

Res.

BDRST

LSE

RDY r rw

LSEON rw

RM0471 Rev 5 221/1202

246

Reset and clock control (RCC) RM0471

Bit 15 RTCEN: RTC clock enable

Set and cleared by software.

0: RTC clock disabled

1: RTC clock enabled

Bits 14:10 Reserved, must be kept at reset value.

Bits 9:8 RTCSEL[1:0]: RTC clock source selection

Set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them.

00: No clock

01: LSE oscillator clock used as RTC clock

10: LSI oscillator clock used as RTC clock

11: HSE oscillator clock divided by 32 used as RTC clock

Bit 7 Reserved, must be kept at reset value.

Bit 6 LSECSSD CSS on LSE failure detection

Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator (LSE).

0: No failure detected on LSE (32 kHz oscillator)

1: Failure detected on LSE (32 kHz oscillator)

Bit 5 LSECSSON CSS on LSE enable

Set by software to enable the clock security system on LSE (32 kHz oscillator).

LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected.

Once enabled this bit cannot be disabled, except after a LSE failure detection

(LSECSSD = 1). In that case the software MUST disable the LSECSSON bit.

0: CSS on LSE (32 kHz external oscillator) OFF

1: CSS on LSE (32 kHz external oscillator) ON

Bits 4:3 LSEDRV[1:0] LSE oscillator drive capability

Set by software to modulate the LSE oscillator drive capability.

00: ‘Xtal mode’ lower driving capability

01: ‘Xtal mode’ medium low driving capability

10: ‘Xtal mode’ medium high driving capability

11: ‘Xtal mode’ higher driving capability

The oscillator is in Xtal mode when it is not in bypass mode.

Bit 2 LSEBYP: LSE oscillator bypass

Set and cleared by software to bypass oscillator. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0).

0: LSE oscillator not bypassed

1: LSE oscillator bypassed

Bit 1 LSERDY: LSE oscillator ready

Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles.

0: LSE oscillator not ready

1: LSE oscillator ready

222/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Bit 0 LSEON: LSE oscillator enable

Set and cleared by software.

0: LSE oscillator OFF

1: LSE oscillator ON

Address: 0x094

Reset value: 0x0C00 0000. Reset by NRST pad, except reset flags by POR only, not reset by wakeup from Standby.

Access: 0  wait state  3, word, half-word and byte access

Wait states are inserted in case of successive accesses to this register.

LPWR

RSTF r

WWDG

RSTF

IWWG

RSTF r

14 r

SFT

RSTF r

RFWKPSEL[1:0] Res.

rw rw

Res.

BOR

RSTF r

11 rw

RSTF r

OB L

RSTF r

LSI2TRIM[3:0] rw rw

24 23 22

Res.

RMVF Res.

8 rw

7 6

Res.

LSI2

RDY r

Res.

LSI2

ON rw

Res.

LSI1

RDY r

RSTS r

LSI1

ON rw

Bit 31 LPWRRSTF: Low-power reset flag

Set by hardware when a reset occurs due to illegal Stop, Standby or Shutdown mode entry.

Cleared by writing to the RMVF bit.

0: No illegal mode reset occurred

1: Illegal mode reset occurred

Bit 30 WWDGRSTF: Window watchdog reset flag

Set by hardware when a window watchdog reset occurs.

Cleared by writing to the RMVF bit.

0: No window watchdog reset occurred

1: Window watchdog reset occurred

Bit 29 IWDGRSTF : Independent window watchdog reset flag

Set by hardware when an independent watchdog reset domain occurs.

Cleared by writing to the RMVF bit.

0: No independent watchdog reset occurred

1: Independent watchdog reset occurred

Bit 28 SFTRSTF: Software reset flag

Set by hardware when a software reset occurs.

Cleared by writing to the RMVF bit.

0: No software reset occurred

1: Software reset occurred

Bit 27 BORRSTF: BOR flag

Set by hardware when a BOR occurs.

Cleared by writing to the RMVF bit.

0: No BOR occurred

1: BOR occurred

RM0471 Rev 5 223/1202

246

Reset and clock control (RCC) RM0471

Bit 26 PINRSTF: Pin reset flag

Set by hardware when a reset from the NRST pin occurs.

Cleared by writing to the RMVF bit.

0: No reset from NRST pin occurred

1: Reset from NRST pin occurred

Bit 25 OBLRSTF: Option byte loader reset flag

Set by hardware when a reset from the Option Byte loading occurs.

Cleared by writing to the RMVF bit.

0: No reset from Option Byte loading occurred

1: Reset from Option Byte loading occurred

Bit 24 Reserved, must be kept at reset value.

Bit 23 RMVF: Remove reset flag

Set by software to clear the reset flags.

0: No effect

1: Clear the reset flags

Bits 22:17 Reserved, must be kept at reset value.

Bit 16 RFRSTS: Radio system BLE and 802.15.4 reset status

Set and cleared by hardware

0: Radio system BLE and 802.15.4 not in reset, radio system can be accessed

1: Radio system BLE and 802.15.4 under reset, radio system cannot be accessed

Bits 15:14 RFWKPSEL[1:0] : RF system wakeup clock source selection

Set by software to select the clock source for RF system wakeup logic.

00: No clock

01: LSE oscillator clock used as RF system wakeup clock

10: Reserved

11: HSE oscillator clock divided by 1024 used as RF system wakeup clock

Bits 13:12 Reserved, must be kept at reset value.

Bits 11:8 LSI2TRIM[3:0] : LSI2 oscillator trim.

Note: LSI2TRIM must be changed only when LSI2 is disabled (LSI2ON = 0).

Bits 7:4 Reserved, must be kept at reset value.

Bit 3 LSI2RDY: LSI2 oscillator ready

Set and cleared by hardware to indicate when the LSI2 oscillator is stable. After the LSI2ON bit is cleared, LSI2RDY goes low after three LSI2 oscillator clock cycles.

0: LSI2 oscillator not ready

1: LSI2 oscillator ready

Bit 2 LSI2ON: LSI2 oscillator enable and selection

Set and cleared by software.

0: LSI2 oscillator OFF (LSI1 selected on LSI)

1: LSI2 oscillator ON(LSI2 when ready selected on LSI)

224/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Bit 1 LSI1RDY: LSI1 oscillator ready

Set and cleared by hardware to indicate when the LSI1 oscillator is stable. After the LSI1ON bit is cleared, LSI1RDY goes low after three LSI1 oscillator clock cycles. This bit can be set even if LSI1ON = 0 if the LSI1 is requested by the clock security system on LSE, by the

Independent watchdog or by the RTC.

0: LSI1 oscillator not ready

1: LSI1 oscillator ready

Bit 0 LSI1ON: LSI1 oscillator enable

Set and cleared by software.

0: LSI1 oscillator OFF

1: LSI1 oscillator ON

Res.

Address: 0x098

Reset value: 0x0000 XXX0 where X is factory-programmed.

Access: No wait state, word, half-word and byte access

Res.

15 r

14 13 12 11

HSI48CAL[8:0]

10 r r r

9 8 7 6

Res.

HSI48

RDY r

HSI48

ON rw r r r r r

Bits 31:16 Reserved, must be kept at reset value

Bits 15:7 HSI48CAL[8:0]: HSI48 clock calibration

These bits are initialized at startup with the factory-programmed HSI48 calibration trim value.

They are ready only.

Bits 6:2 Reserved, must be kept at reset value

Bit 1 HSI48RDY: HSI48 clock ready flag

Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON.

0: HSI48 oscillator not ready

1: HSI48 oscillator ready

Bit 0 HSI48ON: HSI48 clock enable

Set and cleared by software.

Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes.

0: HSI48 oscillator OFF

1: HSI48 oscillator ON

Address: 0x09C

Reset value: 0x0000 0030 (reset by NRST pad, not reset by wakeup from Standby)

RM0471 Rev 5 225/1202

246

Reset and clock control (RCC) RM0471

Res.

Access: Write access is protected and software must write a KEY (0xCAFE CAFE) as a word access in this register to unlock the register. Once unlocked t a single write access

(word, half-word or byte) can be performed to the register. It is then locked again. No wait states.

Res.

13 r

12 r

11 10

HSETUNE[5:0] r r

9 r

8 r

Res.

6 5

HSEGMC[2:0]

4 rw rw rw

3 2

HSES Res.

1 0

Res.

UNLOCKED r

Bits 31:14 Reserved, must be kept at reset value

Bits 13:8 HSETUNE[5:0]: HSE capacitor tuning

Can be changed by software. Not to be changed when HSE is on.

0x00: minimum load capacitance

0x3F maximum load capacitance

Bits 7 Reserved, must be kept at reset value

Bits 6:4 HSEGMC[2:0]: HSE current control

Can be changed by software. Not to be changed when HSE is on.

000: current max limit 0.18 mA/V

001: current max limit 0.57 mA/V

010: current max limit 0.78 mA/V

011: current max limit 1.13 mA/V

100: current max limit 0.61 mA/V

101: current max limit 1.65 mA/V

110: current max limit 2.12 mA/V

111: current max limit 2.84 mA/V

Bit 3 HSES: HSE Sense amplifier threshold

Can be changed by software. Not to be changed when HSE is on.

0: HSE bias current factor 1/2

1: HSE bias current factor 3/4

Bits 2:1 Reserved, must be kept at reset value

Bit 0 UNLOCKED: HSE clock control register unlocked

Set and cleared by hardware.

0: register locked, the key has not been programmed, or a write access has been performed to the register

1: Register unlocked. Key 0xCAFE CAFE has been written to unlock this register, enabling a single data write

7.4.32 RCC extended clock recovery register (RCC_EXTCFGR)

Address: 0x108

Reset value: 0x0003 0000.

Access: No wait state, word, half-word and byte access

226/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Res.

30 29

Res.

14 13

Res.

10 9

Res.

23 22

C2HPRE[3:0]

20 19

Res.

RFCSS Res.

7 4 3 rw rw rw rw rw

Res.

SHDHPRE[3:0]

C2HPREF SHDHPREF r r

0 rw rw rw

Bits 31:21 Reserved, must be kept at reset value

Bit 20 RFCSS: Radio system HCLK5 and APB3 selected clock source indication

Set and reset by hardware to indicate which clock source is selected for the Radio system

HCLK5 and APB3 clock.

0: HSI16 used for Radio system HCLK5 and APB3 clock

1: HSE divided by 2 used for Radio system HCLK5 and APB3 clock

Bits 19:18 Reserved, must be kept at reset value

Bit 17 C2HPREF: HCLK2 prescaler flag (CPU2)

Set and reset by hardware to acknowledge HCLK2 prescaler programming

Reset when a new prescaler value is programmed in C2HPRE. set when the programmed value is actually applied.

0: HCLK2 prescaler value not yet applied

1: HCLK2 prescaler value applied

Bit 16 SHDHPREF: HCLK4 shared prescaler flag (AHB4, Flash memory and SRAM2)

Set and reset by hardware to acknowledge Shared HCLK4 prescaler programming

Reset when a new prescaler value is programmed in SHDHPRE. set when the programmed value is actually applied.

0: HCLK4 prescaler value not yet applied

1: HCLK4 prescaler value applied

Bits 15:8 Reserved, must be kept at reset value

RM0471 Rev 5 227/1202

246

Reset and clock control (RCC) RM0471

Bits 7:4 C2HPRE[3:0]: HCLK2 prescaler (CPU2)

Set and cleared by software to control the division factor of the HCLK2 clock (CPU2).

The C2HPREF flag can be checked to know if the programmed C2HPRE prescaler value is applied.

Caution: The software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details refer to

Section 7.2.10: Clock source frequency ). After a write operation to these bits the

0001: SYSCLK divided by 3

0010: SYSCLK divided by 5

0101: SYSCLK divided by 6

0110: SYSCLK divided by 10

0111: SYSCLK divided by 32

1000: SYSCLK divided by 2

1001: SYSCLK divided by 4

1010: SYSCLK divided by 8

1011: SYSCLK divided by 16

1100: SYSCLK divided by 64

1101: SYSCLK divided by 128

1110: SYSCLK divided by 256

1111: SYSCLK divided by 512

Others: SYSCLK not divided

Bit 3:0 SHDHPRE[3:0]: HCLK4 shared prescaler (AHB4, Flash memory and SRAM2)

Set and cleared by software to control the division factor of the Shared HCLK4 clock (AHB4,

Flash memory and SRAM2).

The SHDHPREF flag can be checked to know if the programmed SHDHPRE prescaler value is applied.

Caution: The software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details refer to

Section 7.2.10: Clock source frequency ). After a write operation to these bits the

0001: SYSCLK divided by 3

0010: SYSCLK divided by 5

0101: SYSCLK divided by 6

0110: SYSCLK divided by 10

0111: SYSCLK divided by 32

1000: SYSCLK divided by 2

1001: SYSCLK divided by 4

1010: SYSCLK divided by 8

1011: SYSCLK divided by 16

1100: SYSCLK divided by 64

1101: SYSCLK divided by 128

1110: SYSCLK divided by 256

1111: SYSCLK divided by 512

Others: SYSCLK not divided

228/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

7.4.33 RCC CPU2 AHB1 peripheral clock enable register

(RCC_C2AHB1ENR)

Note:

Address offset: 0x148

Reset value: 0x0000 0000

Access: No wait state, word, half-word and byte access

When the peripheral clock is not active, the peripheral registers read or write access from

CPU2 is not supported.

31 30 29

Res.

27 26

Res.

24 23 22 21 20 19

Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2

Res.

CRCEN Res.

Res.

SRAM1EN Res.

Res.

DMAMUX1EN rw rw rw

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 CRCEN: CPU2 CRC clock enable

Set and cleared by software.

0: CRC clock disable for CPU2

1: CRC clock enable for CPU2

Bits 11:10 Reserved, must be kept at reset value.

Bit 9 SRAM1EN: CPU2 SRAM1 clock enable

Set and cleared by software.

0: SRAM1 clock disabled for CPU2

1: SRAM1 clock enabled for CPU2

Bits 8:3 Reserved, must be kept at reset value.

Bit 2 DMAMUX1: CPU2 DMAMUX1 clock enable

Set and cleared by software.

0: DMAMUX1 clock disable for CPU2

1: DMAMUX1 clock enable for CPU2

Bit 1 Reserved, must be kept at reset value.

Bit 0 DMA1EN: CPU2 DMA1 clock enable

Set and cleared by software.

0: DMA1 clock disable for CPU2

1: DMA1 clock enable for CPU2

Res.

DMA1EN rw

7.4.34 RCC CPU2 AHB2 peripheral clock enable register

(RCC_C2AHB2ENR)

Note:

Address offset: 0x14C

Reset value: 0x0000 0000

Access: No wait state, word, half-word and byte access

When the peripheral clock is not active, the peripheral registers read or write access from

CPU2 is not supported.

RM0471 Rev 5 229/1202

246

Reset and clock control (RCC) RM0471

Res.

ADC

EN rw

Res.

GPIOH

EN rw

Res.

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 ADCEN: ADC clocks enable

Set and cleared by software.

0: ADC bus and kernel clocks disabled for CPU2

1: ADC bus and kernel clocks enabled for CPU2

Bits 12:8 Reserved, must be kept at reset value.

Bit 7 GPIOHEN: CPU2 IO port H clock enable

Set and cleared by software.

0: IO port H clock disabled for CPU2

1: IO port H clock enabled for CPU2

Bits 6:5 Reserved, must be kept at reset value.

Bit 4 GPIOEEN: CPU2 IO port E clock enable

Set and cleared by software.

0: IO port E clock disabled for CPU2

1: IO port E clock enabled for CPU2

Bit 3 Reserved, must be kept at reset value.

Bit 2 GPIOCEN: CPU2 IO port C clock enable

Set and cleared by software.

0: IO port C clock disabled for CPU2

1: IO port C clock enabled for CPU2

Bit 1 GPIOBEN: CPU2 IO port B clock enable

Set and cleared by software.

0: IO port B clock disabled for CPU2

1: IO port B clock enabled for CPU2

Bit 0 GPIOAEN: CPU2 IO port A clock enable

Set and cleared by software.

0: IO port A clock disabled for CPU2

1: IO port A clock enabled for CPU2

Res.

GPIOE

EN rw

Res.

GPIOC

EN rw

GPIOB

EN rw

GPIOA

EN rw

7.4.35 RCC CPU2 AHB3 and AHB4 peripheral clock enable register

(RCC_C2AHB3ENR)

Note:

Address offset: 0x150

Reset value: 0x0208 0000

Access: No wait state, word, half-word and byte access

When the peripheral clock is not active, the peripheral registers read or write access from

CPU2 is not supported.

230/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Res.

FLASH

EN rw

Res.

IPCC

EN rw

Res.

HSEM

EN rw

Res.

RNG

EN rw

Res.

AES2

EN rw

Res.

PKA

EN rw

Res.

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 FLASHEN CPU2 Flash interface clock enable

This bit can only be cleared when the Flash is in Power down. Set and cleared by software.

0: Flash interface clock disable for CPU2

1: Flash interface clock enable for CPU2

Bits 24:21 Reserved, must be kept at reset value.

Bit 20 IPCCEN CPU2 IPCC interface clock enable

Set and cleared by software.

0: IPCC clock disable for CPU2

1: IPCC clock enable for CPU2

Bit 19 HSEMEN CPU2 HSEM clock enable

Set and cleared by software.

0: HSEM clock disable for CPU2

1: HSEM clock enable for CPU2

Bit 18 RNGEN CPU2 True RNG clocks enable

Set and cleared by software.

0: True RNG bus and kernel clocks disable for CPU2

1: True RNG bus and kernel clocks enable for CPU2

Bit 17 AES2EN CPU2 AES2 accelerator clock enable

Set and cleared by software.

0: AES2 clock disable for CPU2

1: AES2 clock enable for CPU2

Bit 16 PKAEN CPU2 PKA accelerator clock enable

Set and cleared by software.

0: PKA clock disable for CPU2

1: PKA clock enable for CPU2

Bits 15:0 Reserved, must be kept at reset value.

7.4.36 RCC CPU2 APB1 peripheral clock enable register 1

(RCC_C2APB1ENR1)

Note:

Address: 0x158

Reset value: 0x0000 0400

Access: No wait state, word, half-word and byte access

When the peripheral clock is not active, the peripheral registers read or write access from

CPU2 is not supported.

RM0471 Rev 5 231/1202

246

Reset and clock control (RCC) RM0471

LPTIM1

EN rw

Res.

RTCAPB

EN rw

Res.

Bit 31 LPTIM1EN: CPU2 Low power timer 1 clocks enable

Set and cleared by software.

0: LPTIM1 bus and kernel clocks disabled for CPU2

1: LPTIM1 bus and kernel clocks enabled for CPU2

Bits 30:22 Reserved, must be kept at reset value.

Bit 21 I2C1EN: CPU2 I2C1 clocks enable

Set and cleared by software.

0: I2C1 bus and kernel clocks disabled for CPU2

1: I2C1 bus and kernel clocks enabled for CPU2

Bits 20:11 Reserved, must be kept at reset value.

Bit 10 RTCAPBEN: CPU2 RTC APB clock enable

Set and cleared by software

0: RTC APB clock disabled for CPU2

1: RTC APB clock enabled for CPU2

Bits 9:1 Reserved, must be kept at reset value.

Bit 0 TIM2EN: CPU2 TIM2 timer clock enable

Set and cleared by software.

0: TIM2 clock disabled for CPU2

1: TIM2 clock enabled for CPU2

I2C1

EN rw

Res.

TIM2

EN rw

7.4.37 RCC CPU2 APB1 peripheral clock enable register 2

(RCC_C2APB1ENR2)

Note:

Address offset: 0x15C

Reset value: 0x00000 0000

Access: No wait state, word, half-word and byte access

When the peripheral clock is not active, the peripheral registers read or write access from

CPU2 is not supported.

Res.

26 25

Res.

10 9

Res.

6 5 4

Res.

LPTIM2EN Res.

Res.

232/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 LPTIM2EN CPU2 Low power timer 2 clocks enable

Set and cleared by software.

0: LPTIM2 bus and kernel clocks disable for CPU2

1: LPTIM2 bus and kernel clocks enable for CPU2

Bits 4:0 Reserved, must be kept at reset value.

7.4.38 RCC CPU2 APB2 peripheral clock enable register

(RCC_C2APB2ENR)

Note:

Address: 0x160

Reset value: 0x0000 0000

Access: word, half-word and byte access

When the peripheral clock is not active the peripheral registers read or write access from

CPU2 is not supported.

Res.

TIM17

EN rw

Res.

TIM16

EN rw

Res.

USART1

EN rw

Res.

SPI1

EN rw

TIM1

EN rw

Res.

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 TIM17EN: CPU2 TIM17 timer clock enable

Set and cleared by software.

0: TIM17 timer clock disabled for CPU2

1: TIM17 timer clock enabled for CPU2

Bit 17 TIM16EN: CPU2 TIM16 timer clock enable

Set and cleared by software.

0: TIM16 timer clock disabled for CPU2

1: TIM16 timer clock enabled for CPU2

Bits 16:15 Reserved, must be kept at reset value.

Bit 14 USART1EN: CPU2 UFSART1 clock enable

Set and cleared by software.

0: USART1 bus and kernel clocks disabled for CPU2

1: USART1 bus and kernel clocks enabled for CPU2

Bit 13 Reserved, must be kept at reset value.

Bit 12 SPI1EN: CPU2 SPI1 clock enable

Set and cleared by software.

0: SPI1 clock disabled for CPU2

1: SPI1 clock enabled for CPU2

Res.

RM0471 Rev 5 233/1202

246

Reset and clock control (RCC) RM0471

Bit 11 TIM1EN: CPU2 TIM1 timer clock enable

Set and cleared by software.

0: TIM1 timer clock disabled for CPU2

1: TIM1P timer clock enabled for CPU2

Bits 10:0 Reserved, must be kept at reset value.

7.4.39 RCC CPU2 APB3 peripheral clock enable register

(RCC_C2APB3ENR)

Note:

Address offset: 0x164

Reset value: 0x00000 0000

Access: No wait state, word, half-word and byte access

When the peripheral clock is not active, the peripheral registers read or write access from

CPU2 is not supported.

Res.

2 1 0

Res.

802EN BLEEN rw rw

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 802EN: CPU2 802.15.4 interface clock enable

Set and cleared by software.

0: 802.15.4 clock disable for CPU2

1: 802.15.4 clock enable for CPU2

Bit 0 BLEEN: CPU2 BLE interface clock enable

Set and cleared by software.

0: BLE clock disable for CPU2

1: BLE clock enable for CPU2

7.4.40 RCC CPU2 AHB1 peripheral clocks enable in Sleep modes register

(RCC_C2AHB1SMENR)

Address offset: 0x168

Reset value: 0x0001 1007

Access: No wait state, word, half-word and byte access

Res.

CRC

SMEN rw

Res.

SRAM1

SMEN rw

Res.

DMAMUX1

SMEN rw

Res.

DMA1

SMEN rw

234/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 CRCSMEN: CRC clock enable during CPU2 CSleep mode

Set and cleared by software.

0: CRC clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: CRC clock enabled by the clock gating during CPU2 CSleep mode, disabled during CPU2

CStop mode

Bits 11:10 Reserved, must be kept at reset value.

Bit 9 SRAM1SMEN : SRAM1 interface clock enabled during CPU2 CSleep mode

Set and cleared by software

0: SRAM1 interface clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: SRAM1 interface clock enabled by the clock gating during CPU2 CSleep mode, disabled during CStop mode

Bits 8:3 Reserved, must be kept at reset value.

Bit 2 DMAMUX1SMEN: DMAMUX1 clock enable during CPU2 CSleep mode

Set and cleared by software during Sleep mode.

0: DMAMUX1 clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: DMAMUX1 clock enabled by the clock gating during CPU2 CSleep mode, disabled during

CPU2 CStop mode

Bit 1 Reserved, must be kept at reset value.

Bit 0 DMA1SMEN: DMA1 clock enable during CPU2 CSleep mode

Set and cleared by software.

0: DMA1 clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: DMA1 clock enabled by the clock gating during CPU2 CSleep mode, disabled during

CPU2 CStop mode

7.4.41 RCC CPU2 AHB2 peripheral clocks enable in Sleep modes register

(RCC_C2AHB2SMENR)

Address offset: 0x16C

Reset value: 0x0001 209F

Access: No wait state, word, half-word and byte access

Res.

ADC

SMEN rw

Res.

GPIOH

SMEN rw

Res.

GPIOE

SMEN rw

Res.

GPIOC

SMEN rw

GPIOB

SMEN rw

GPIOA

SMEN rw

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 ADCSMEN: ADC clock enable during CPU2 CSleep and CStop modes

Set and cleared by software.

0: ADC bus clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: ADC bus clock enabled by the clock gating during CPU2 CSleep mode, disabled during

CPU2 CStop mode

RM0471 Rev 5 235/1202

246

Reset and clock control (RCC) RM0471

Bits 12:8 Reserved, must be kept at reset value.

Bit 7 GPIOHSMEN: IO port H clock enable during CPU2 CSleep mode

Set and cleared by software.

0: IO port H clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: IO port H clock enabled by the clock gating during CPU2 CSleep mode, disabled during

CPU2 CStop mode

Bits 6:5 Reserved, must be kept at reset value.

Bit 4 GPIOESMEN: IO port E clock enable during CPU2 CSleep mode

Set and cleared by software.

0: IO port E clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: IO port E clock enabled by the clock gating during CPU2 CSleep mode, disabled during

CPU2 CStop mode

Bit 3 Reserved, must be kept at reset value.

Bit 2 GPIOCSMEN: IO port C clock enable during CPU2 CSleep mode

Set and cleared by software.

0: IO port C clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: IO port C clock enabled by the clock gating during CPU2 CSleep mode, disabled during

CPU2 CStop mode

Bit 1 GPIOBSMEN: IO port B clock enable during CPU2 CSleep mode

Set and cleared by software.

0: IO port B clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: IO port B clock enabled by the clock gating during CPU2 CSleep mode, disabled during

CPU2 CStop mode

Bit 0 GPIOASMEN: IO port A clock enable during CPU2 CSleep mode

Set and cleared by software.

0: IO port A clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: IO port A clock enabled by the clock gating during CPU2 CSleep mode, disabled during

CPU2 CStop mode

7.4.42 RCC CPU2 AHB3 and AHB4 peripheral clocks enable in Sleep mode register (RCC_C2AHB3SMENR)

Address offset: 0x170

Reset value: 0x0307 0000

Access: No wait state, word, half-word and byte access

Res.

FLASH

SMEN rw

Res.

SRAM2

SMEN rw

Res.

RNG

SMEN rw

Res.

AES2

SMEN rw

Res.

PKA

SMEN rw

Res.

Bits 31:26 Reserved, must be kept at reset value.

236/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Bit 25 FLASHSMEN Flash memory interface clock enable during CPU2 CSleep mode

Set and cleared by software.

0: Flash memory interface clock disabled by the clock gating during CPU2 CSleep and

CStop modes.

1: Flash memory interface clock enabled by the clock gating during CPU2 CSleep mode, disabled during CPU2 CStop mode.

Bit 24 SRAM2SMEN: SRAM2a and SRAM2b interface clock enable during CPU2 CSleep mode

Set and cleared by software.

0: SRAM2 clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: SRAM2 clock enabled by the clock gating during CPU2 CSleep mode, disabled during

CPU2 CStop mode

Bits 23:19 Reserved, must be kept at reset value.

Bit 18 RNGSMEN True RNG clock enable during CPU2 CSleep and CStop mode

Set and cleared by software.

0: True RNG bus clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: True RNG bus clock enabled by the clock gating during CPU2 CSleep mode, disabled during CPU2 CStop mode

Bit 17 AES2SMEN AES2 accelerator clock enable during CPU2 CSleep mode

Set and cleared by software.

0: AES2 clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: AES2 clock enabled by the clock gating during CPU2 CSleep mode, disabled during

CPU2 CStop mode

Bit 16 PKASMEN: PKA accelerator clock enable during CPU2 CSleep mode

Set and cleared by software.

0: PKA clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: PKA clock enabled by the clock gating during CPU2 CSleep mode, disabled during CPU2

CStop mode

Bits 15:0 Reserved, must be kept at reset value.

7.4.43 RCC CPU2 APB1 peripheral clocks enable in Sleep mode register 1

(RCC_C2APB1SMENR1)

Address: 0x178

Reset value: 0x85A0 4601

Access: No wait state, word, half-word and byte access

LPTIM1

SMEN rw

Res.

RTCAPB

SMEN rw

Res.

I2C1

SMEN rw

Res.

TIM2

SMEN rw

RM0471 Rev 5 237/1202

246

Reset and clock control (RCC) RM0471

Bit 31 LPTIM1SMEN: Low power timer 1 clock enable during CPU2 CSleep and CStop mode

Set and cleared by software.

0: LPTIM1 bus clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: LPTIM1 bus clock enabled by the clock gating during CPU2 CSleep mode, disabled during CPU2 CStop mode

Bits 30:22 Reserved, must be kept at reset value.

Bit 21 I2C1SMEN: I2C1 clock enable during CPU2 CSleep and CStop modes

Set and cleared by software.

0: I2C1 bus clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: I2C1 bus clock enabled by the clock gating during CPU2 CSleep modes disabled during

CPU2 CStop mode

Bits 20:11 Reserved, must be kept at reset value.

Bit 10 RTCAPBSMEN: RTC bus clock enable during CPU2 CSleep mode

Set and cleared by software

0: RTC bus clock disabled during by the clock gating during CPU2 CSleep and CStop modes

1: RTC bus clock enabled during by the clock gating during CPU2 CSleep mode, disabled during CPU2 CStop mode

Bits 9:1 Reserved, must be kept at reset value.

Bit 0 TIM2SMEN: TIM2 timer clock enable during CPU2 CSleep mode

Set and cleared by software.

0: TIM2 clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: TIM2 clock enabled by the clock gating during CPU2 CSleep mode, disabled during CPU2

CStop mode

7.4.44 RCC CPU2 APB1 peripheral clocks enable in Sleep mode register 2

(RCC_C2APB1SMENR2)

Address offset: 0x17C

Reset value: 0x0000 0021

Access: No wait state, word, half-word and byte access

Res.

LPTIM2

SMEN rw

Res.

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 LPTIM2SMEN Low power timer 2 clock enable during CPU2 CSleep and CStop modes.

Set and cleared by software.

0: LPTIM2 bus clock disabled by the clock gating during CPU2 CSleep and CStop modes.

1: LPTIM2 bus clock enabled by the clock gating during CPU2 CSleep mode, disabled during CPU2 CStop mode.

Bits 4:0 Reserved, must be kept at reset value.

238/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

7.4.45 RCC CPU2 APB2 peripheral clocks enable in Sleep mode register

(RCC_C2APB2SMENR)

Address: 0x180

Reset value: 0x0026 5800

Access: word, half-word and byte access

Res.

USART1

SMEN rw

Res.

SPI1

SMEN rw

TIM1SM

EN rw

Res.

TIM17

SMEN rw

TIM16

SMEN rw

Res.

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 TIM17SMEN: TIM17 timer clock enable during CPU2 CSleep mode

Set and cleared by software.

0: TIM17 timer clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: TIM17 timer clock enabled by the clock gating during CPU2 CSleep mode, disabled during

CPU2 CStop mode

Bit 17 TIM16SMEN: TIM16 timer clock enable during CPU2 CSleep mode

Set and cleared by software.

0: TIM16 timer clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: TIM16 timer clock enabled by the clock gating during CPU2 CSleep mode, disabled during

CPU2 CStop mode

Bits 16:15 Reserved, must be kept at reset value.

Bit 14 USART1SMEN: USART1 clock enable during CPU2 CSleep and CStop mode

Set and cleared by software.

0: USART1 bus clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: USART1 bus clock enabled by the clock gating during CPU2 CSleep mode, disabled during CPU2 CStop mode

Bit 13 Reserved, must be kept at reset value.

Bit 12 SPI1SMEN: SPI1 clock enable during CPU2 CSleep mode

Set and cleared by software.

0: SPI1 clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: SPI1 clock enabled by the clock gating during CPU2 CSleep mode, disabled during CPU2

CStop mode

Bit 11 TIM1SMEN: TIM1 timer clock enable during CPU2 CSleep mode

Set and cleared by software.

0: TIM1 timer clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: TIM1 timer clock enabled by the clock gating during CPU2 CSleep mode, disabled during

CPU2 CStop mode

Bits 10:0 Reserved, must be kept at reset value.

RM0471 Rev 5 239/1202

246

Reset and clock control (RCC) RM0471

7.4.46 RCC CPU2 APB3 peripheral clock enable in Sleep mode register

(RCC_C2APB3SMENR)

Address offset: 0x184

Reset value: 0x00000 0003

Access: word, half-word and byte access

Res.

2 1 0

Res.

802SMEN BLESMEN rw rw

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 802SMEN: 802.15.4 interface bus clock enable during CPU2 CSleep mode

Set and cleared by software.

0: 802.15.4 bus clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: 802.15.4 bus clock enabled by the clock gating during CPU2 CSleep mode, disabled during CPU2 CStop mode

Bit 0 BLESMEN: BLE interface bus clock enable during CPU2 CSleep mode

Set and cleared by software.

0: BLE bus clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: BLE bus clock enabled by the clock gating during CPU2 CSleep mode, disabled during

CPU2 CStop mode

Note: The BLE interface bus clock is also enabled by the BLE IP itself.

240/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

7.4.47 RCC register map

The following table gives the RCC register map and the reset values.

Table 37. RCC register map and reset values

Offset Register

RCC_CR

0x000

0x004

Reset value

RCC_ICSCR

Reset value

HSITRIM[6:0]

1 0 0 0 0

RCC_CFGR

MCOPRE

[2:0]

MCOSEL[3:0]

0x008

Reset value 0 0 0 0 0 0 0

RCC_PLLCFGR PLLR[2:0]

0x00C

Reset value

0x010 Reserved

PLLQ[2:0]

0 0 1 0 0 0 1 0 x x

HSICAL[7:0] x

0 x

0 x x

0 0 x x 0 0 0 0 0 0 0 0

1 1 1 0

PLLP[4:0]

0 0 0 1 0 0

MSIRANGE

[3:0]

0 0 0 0 0 0 1 1 0

MSITRIM[7:0]

PPRE2

[2:0]

PPRE1

[2:0] x x

0 0 1

MSICAL[7:0] x

HPRE[3:0] x x x

SWS

[1:0] x

0 0 0 0 0 0 0 0 0 0 0 0 0 0

PLLN[6:0]

0 0 0 0 0 0 1

PLLM[2:0]

0 0 0 0 0

0x018

RCC_CIER

Reset value

0x01C

RCC_CIFR

Reset value

RCC_CICR

0x020

0x024

Reset value

Reserved

0 0 0

0 0 0 0

0 0 0 0 0 0

0x028

RCC_AHB1RSTR

Reset value

0x02C

RCC_AHB2RSTR

Reset value 0

0 0

0 0 0 0

RM0471 Rev 5 241/1202

246

Reset and clock control (RCC)

Table 37. RCC register map and reset values (continued)

Offset Register

0x030

RCC_AHB3RSTR

Reset value

0x034 Reserved

0x038

RCC_

APB1RSTR1

Reset value 0

0x03C

RCC_

APB1RSTR2

Reset value

RCC_

APB2RSTR

0x040

Reset value

0x044

RCC_APB3RSTR

Reset value

0x048

RCC_AHB1ENR

Reset value

0x04C

RCC_AHB2ENR

Reset value

0x050

RCC_AHB3ENR

Reset value

0x054 Reserved

0x058

RCC_APB1ENR1

Reset value 0

0x05C

RCC_APB1ENR2

Reset value

0 0 0 0 0

0 0

0 1 0 0 0

0 0 0

0 1

RM0471

0 0

0 0 0 0

242/1202 RM0471 Rev 5

RM0471 Reset and clock control (RCC)

Table 37. RCC register map and reset values (continued)

Offset Register

0x060

RCC_APB2ENR

Reset value

0x064 Reserved

0x068

RCC_

AHB1SMENR

Reset value

0x06C

RCC_

AHB2SMENR

Reset value

0x070

RCC

_AHB3SMENR

Reset value

0x074 Reserved

0x078

RCC

_APB1SMENR1

Reset value 1

0x07C

RCC

_APB1SMENR2

Reset value

0x080

RCC_

APB2SMENR

Reset value

0x084 Reserved

0x088

RCC_CCIPR

Reset value

0x08C Reserved

0 0 0 0 0 0

1 1

0 0

1 1 1

1 1

0 0 0 0

0 0 0

1 1 1

0 0

1 1

1 1 1 1

0 0

RM0471 Rev 5 243/1202

246

Reset and clock control (RCC)

Table 37. RCC register map and reset values (continued)

Offset Register

RM0471

0x090

RCC_BDCR

Reset value 0 0

0x094

RCC_CSR

Reset value 0 0 0 0 1 1 0

0x098

RCC_CRRCR

Reset value

0x09C

RCC_HSECR

Reset value

0x0A0 to

0x104

Reserved

0x108

RCC_EXTCFGR

Reset value

0x10C to

0x144

Reserved

0x148

RCC

_C2AHB1ENR

Reset value

0x14C

RCC

_C2AHB2ENR

Reset value

RCC

_C2AHB3ENR

0x150

Reset value

0x154 Reserved

0x158

RCC

_C2APB1ENR1

Reset value 0

0 1 1

0 1 0 0 0

0 0

0 0 0

0 0

LSI2TRIM

[3:0]

0 0 0 0

0 0 0 0 0 0 0

0 0 0 0

HSI48CAL[8:0] x x x x x x x x x 0 0

HSETUNE[5:0]

HSEGMC

[2:0]

0 0 0 0 0 0 0 0 1 1 0 0 0 0

C2HPRE[3:0]

0 0 0 0 0 0 0 0

0 0

SHDHPRE

[3:0]

0 0

0 0 0

244/1202 RM0471 Rev 5

RM0471

Offset Register

0x15C

RCC

_C2APB1ENR2

Reset value

0x160

RCC

_C2APB2ENR

0x164

Reset value

RCC

_C2APB3ENR

Reset value

0x168

RCC

_C2AHB1SMENR

Reset value

0x16C

RCC

_C2AHB2SMENR

Reset value

0x170

RCC

_C2AHB33MENR

Reset value

0x174 Reserved

0x178

RCC_C2

APB1SMENR1

Reset value 1

0x17C

RCC_C2

APB1SMENR2

Reset value

0x180

RCC_C2

APB2SMENR

Reset value

Reset and clock control (RCC)

Table 37. RCC register map and reset values (continued)

1 1

0 0

1 1 1

1 1

0 0 0

1 1 1

0 0

1 1

1 1 1 1

RM0471 Rev 5 245/1202

246

Reset and clock control (RCC)

Table 37. RCC register map and reset values (continued)

Offset Register

0x184

RCC_C2

APB3SMENR

0x188 to 03FC

Reset value

Reserved

Refer to Section 2.2 on page 55 for the register boundary addresses.

RM0471

1 1

246/1202 RM0471 Rev 5

RM0471

8 General-purpose I/Os (GPIO)

General-purpose I/Os (GPIO)

8.1 Introduction

Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER,

GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers

(GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). In addition all GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL).

8.2 GPIO main features

 Output states: push-pull or open drain + pull-up/down

 Output data from output data register (GPIOx_ODR) or peripheral (alternate function output)

 Speed selection for each I/O

 Input states: floating, pull-up/down, analog

 Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)

 Bit set and reset register (GPIOx_ BSRR) for bitwise write access to GPIOx_ODR

 Locking mechanism (GPIOx_LCKR) provided to freeze the I/O port configurations

 Analog function

 Alternate function selection registers

 Fast toggle capable of changing every two clock cycles

 Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several peripheral functions

8.3 GPIO functional description

Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in several modes:

 Input floating

 Input pull-up

 Input-pull-down

 Analog

 Output open-drain with pull-up or pull-down capability

 Output push-pull with pull-up or pull-down capability

 Alternate function push-pull with pull-up or pull-down capability

 Alternate function open-drain with pull-up or pull-down capability

Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR register is to allow atomic read/modify accesses to any of the GPIOx_ODR registers. In this way, there is no risk of an IRQ occurring between the read and the modify access.

RM0471 Rev 5 247/1202

268

General-purpose I/Os (GPIO) RM0471

Analog

Figure 19

shows the basic structure of a Three-volt tolerant (TT) and Five-volt tolerant (FT)

I/O port bit.

Figure 19. Three-volt or Five-volt tolerant GPIO structure (TT or FT)

Parasitic diode and resistor

DDA

Analog option

Analog IP

Analog switch

Alternate function input

Input data register on/off

I/O pin

Input buffer

Digital

Note:

Output data register

Alternate function output

Output control

PMOS on/off

ESD protection

NMOS

Ouput buffer V

MSv46873V1

The parasitic diode in the analog domain is connected to V

DDA protection diode.

and cannot be used as a

The voltage level called V

DD_FT

ESD protection block.

in some datasheets and reference manuals is within the

When the analog option is selected, the FT I/O is not five-volt tolerant anymore since the pin is supplied with V

DDA

A TT or FT GPIO pin has no internal protection diode connected to supply (V

). There is no physical limitation against over-voltage. Therefore, for applications requiring a limited voltage threshold, it is recommended to connect an external diode to V

Table 38 gives the possible port bit configurations.

248/1202 RM0471 Rev 5

RM0471 General-purpose I/Os (GPIO)

MODE(i)

[1:0]

Table 38. Port bit configuration table (1)

OTYPER(i)

OSPEED(i)

[1:0]

PUPD(i)

[1:0]

I/O configuration

11 x x x x x

1 x x x

0 x x x x x x x x

SPEED

[1:0]

SPEED

[1:0] x x x x x x x x

GP output

Reserved

GP output

Reserved

PP + PU

PP + PD

OD + PU

OD + PD

Reserved (GP output OD)

AF PP

AF PP + PU

PP + PD AF

Reserved

AF OD

OD + PU

OD + PD

Input

Floating

Reserved (input floating)

Input/output Analog

Reserved

1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate function.

RM0471 Rev 5 249/1202

268

General-purpose I/Os (GPIO) RM0471

8.3.2

During and just after reset, the alternate functions are not active and most of the I/O ports are configured in analog mode.

The debug pins are in AF pull-up/pull-down after reset:

 PA15: JTDI in input mode with pull-up

 PA14: JTCK/SWCLK in input mode with pull-down

 PA13: JTMS/SWDAT in input mode with pull-up

 PB4: NJTRST in input mode with pull-up

 PB3: JTDO in Hi-Z mode no pulls

PH3/BOOT0 is in input mode during the reset until at least the end of the option byte loading phase. See

Section 8.3.15: Using PH3 as GPIO

When the pin is configured as output, the value written to the output data register

(GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull mode or open-drain mode (only the low level is driven, high level is HI-Z).

The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB clock cycle.

All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not depending on the value in the GPIOx_PUPDR register.

I/O pin alternate function multiplexer and mapping

The device I/O pins are connected to on-board peripherals/modules through a multiplexer that allows only one peripheral alternate function (AF) connected to an I/O pin at a time. In this way, there can be no conflict between peripherals available on the same I/O pin.

Each I/O pin has a multiplexer with up to sixteen alternate function inputs (AF0 to AF15) that can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to

15) registers:

 After reset the multiplexer selection is alternate function 0 (AF0). The I/Os are configured in alternate function mode through GPIOx_MODER register.

 The specific alternate function assignments for each pin are detailed in the device datasheet.

In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped onto different I/O pins to optimize the number of peripherals available in smaller packages.

To use an I/O in a given configuration, the user has to proceed as follows:

 Debug function: after each device reset these pins are assigned as alternate function pins immediately usable by the debugger host

 GPIO: configure the desired I/O as output, input or analog in the GPIOx_MODER register.

 Peripheral alternate function:

– Connect the I/O to the desired AFx in one of the GPIOx_AFRL or GPIOx_AFRH register.

– Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,

GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively.

250/1202 RM0471 Rev 5

RM0471

8.3.3

8.3.4

8.3.5

General-purpose I/Os (GPIO)

– Configure the desired I/O as an alternate function in the GPIOx_MODER register.

 Additional functions:

– For the ADC and PVD, configure the desired I/O in analog mode in the

GPIOx_MODER register and configure the required function in the ADC and

COMP registers.

– For the additional functions like RTC, WKUPx and oscillators, configure the required function in the related RTC, PWR and RCC registers. These functions have priority over the configuration in the standard GPIO registers.

Refer to the “Alternate function mapping” table in the device datasheet for the detailed mapping of the alternate function I/O pins.

I/O port control registers

Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER,

GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The

GPIOx_MODER register is used to select the I/O mode (input, output, AF, analog). The

GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (pushpull or open-drain) and speed. The GPIOx_PUPDR register is used to select the pullup/pull-down whatever the I/O direction.

I/O port data registers

Each GPIO has two 16-bit memory-mapped data registers: input and output data registers

(GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write accessible. The data input through the I/O are stored into the input data register

(GPIOx_IDR), a read-only register.

See Section 8.4.5: GPIO port input data register (GPIOx_IDR) (x = A to C and E and H)

and

Section 8.4.6: GPIO port output data register (GPIOx_ODR) (x = A to C and E and H) for the

I/O data bitwise handling

The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset register has twice the size of GPIOx_ODR.

To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BS(i) and BR(i).

When written to 1, bit BS(i) sets the corresponding ODR(i) bit. When written to 1, bit BR(i) resets the ODR(i) corresponding bit.

Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in

GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set action takes priority.

Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a

“one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always be accessed directly. The GPIOx_BSRR register provides a way of performing atomic bitwise handling.

There is no need for the software to disable interrupts when programming the GPIOx_ODR at bit level: it is possible to modify one or more bits in a single atomic AHB write access.

RM0471 Rev 5 251/1202

268

General-purpose I/Os (GPIO) RM0471

It is possible to freeze the GPIO control registers by applying a specific write sequence to the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER,

GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.

To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must be the same). When the LOCK sequence has been applied to a port bit, the value of the port bit can no longer be modified until the next MCU reset or peripheral reset. Each

GPIOx_LCKR bit freezes the corresponding bit in the control registers (GPIOx_MODER,

GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.

The LOCK sequence (refer to

Section 8.4.8: GPIO port configuration lock register

(GPIOx_LCKR) (x = A to C and E and H)

) can only be performed using a word (32-bit long) access to the GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same time as the [15:0] bits.

For more details refer to LCKR register description in Section 8.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A to C and E and H)

8.3.8

Two registers are provided to select one of the alternate function inputs/outputs available for each I/O. With these registers, the user can connect an alternate function to some other pin as required by the application.

This means that a number of possible peripheral functions are multiplexed on each GPIO using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can thus select any one of the possible functions for each I/O. The AF selection signal being common to the alternate function input and alternate function output, a single channel is selected for the alternate function input/output of a given I/O.

To know which functions are multiplexed on each GPIO pin refer to the device datasheet.

External interrupt/wakeup lines

All ports have external interrupt capability. To use external interrupt lines, the port must be configured in input mode.

Refer to Section 14: Extended interrupt and event controller (EXTI)

and to Section 14.3:

EXTI functional description.

252/1202

When the I/O port is programmed as input:

 The output buffer is disabled

 The Schmitt trigger input is activated

 The pull-up and pull-down resistors are activated depending on the value in the

GPIOx_PUPDR register

 The data present on the I/O pin are sampled into the input data register every AHB clock cycle

 A read access to the input data register provides the I/O state

RM0471 Rev 5

RM0471 General-purpose I/Os (GPIO)

Figure 20

shows the input configuration of the I/O port bit.

Figure 20. Input floating/pull up/pull down configurations on

Read

Write

TTL Schmitt trigger

Input driver

Output driver on/off on/off

DDIOx

Pull up

I/O pin

Pull down

ESD protection

Protection diode

Read/write

MSv63602V1

When the I/O port is programmed as output:

 The output buffer is enabled:

– Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated)

– Push-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register activates the P-MOS

 The Schmitt trigger input is activated

 The pull-up and pull-down resistors are activated depending on the value in the

GPIOx_PUPDR register

 The data present on the I/O pin are sampled into the input data register every AHB clock cycle

 A read access to the input data register gets the I/O state

 A read access to the output data register gets the last written value

Figure 21

shows the output configuration of the I/O port bit.

Figure 21. Output configuration

Read

Write

Read/write on

Input driver

Output driver

TTL Schmitt trigger

Output control

DDIOx

P- MO S on/off on/off

DDIOx

Pull up

I/O pin

Pull ESD down protection

Protection diode

N- MO S

Push-pull or

open-drain

MSv63641V1

RM0471 Rev 5 253/1202

268

General-purpose I/Os (GPIO) RM0471

8.3.11 Alternate function configuration

When the I/O port is programmed as alternate function:

 The output buffer can be configured in open-drain or push-pull mode

 The output buffer is driven by the signals coming from the peripheral (transmitter enable and data)

 The Schmitt trigger input is activated

 The weak pull-up and pull-down resistors are activated or not depending on the value in the GPIOx_PUPDR register

 The data present on the I/O pin are sampled into the input data register every AHB clock cycle

 A read access to the input data register gets the I/O state

Figure 22

shows the alternate function configuration of the I/O port bit.

To on-chip peripheral

Figure 22. Alternate function configuration

Alternate function input on

Read

DDIOx

TTL Schmitt trigger

Write

From on-chip peripheral

Read/write

Input driver

Output driver

Output control

DDIOx

P-MOS on/off on/off

N-MOS

Push-pull or

open-drain

Pull up

I/O pin

Pull ESD down protection

Protection diode

Alternate function output

MSv63642V1

When the I/O port is programmed as analog configuration:

 The output buffer is disabled

 The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).

 The weak pull-up and pull-down resistors are disabled by hardware

 Read access to the input data register gets the value “0”

254/1202 RM0471 Rev 5

RM0471 General-purpose I/Os (GPIO)

Figure 23

shows the high-impedance, analog-input configuration of the I/O port bits.

Figure 23. High impedance-analog configuration

To on-chip peripheral

Read

Analog off

TTL Schmitt trigger

Write Input driver

Output driver

ESD protection

I/O pin

Protection diode

From on-chip peripheral

Read/write

Analog

MSv63643V1

8.3.13 Using the LSE oscillator pins as GPIOs

Note:

When the LSE oscillator is switched OFF (default state after reset), the related oscillator pins can be used as normal GPIOs.

When the LSE oscillator is switched ON (by setting the LSEON bit in the RCC_CSR register) the oscillator takes control of its associated pins and the GPIO configuration of these pins has no effect.

When the oscillator is configured in a user external clock mode, only the OSC32_IN pin is reserved for clock input and the OSC32_OUT pin can still be used as normal GPIO.

The HSE OSC_IN and OSC_OUT pins are dedicated oscillator pins and cannot be used as

GPIO.

8.3.14 Using the GPIO pins in the RTC supply domain

The PC14/PC15 GPIO functionality is lost when the core supply domain is powered off

(when the device enters Standby mode). In this case, if their GPIO configuration is not bypassed by the RTC configuration, these pins are set in an analog input mode.

For details about I/O control by the RTC, refer to

Section 24.3: RTC functional description .

8.3.15 Using PH3 as GPIO

PH3 may be used as boot pin (BOOT0) or as a GPIO. Depending on the nSWBOOT0 bit in the user option byte, it switches from the input mode to the analog input mode:

 After the option byte loading phase if nSWBOOT0 = 1.

 After reset if nSWBOOT0 = 0.

RM0471 Rev 5 255/1202

268

General-purpose I/Os (GPIO) RM0471

For a summary of register bits, register address offsets and reset values, refer to Table 39

The peripheral registers can be written in word, half word or byte mode.

8.4.1 GPIO port mode register (GPIOx_MODER)

(x = A to C and E and H)

Address offset:0x00

Reset value: 0xABFF FFFF (for port A)

Reset value: 0xFFFF FEBF (for port B)

Reset value: 0xFFFF FFFF for port C, D

Reset value: 0x0000 03FF for port E

Reset value: 0x0000 00CF for port H

Port B[31:20] are reserved

Port C[27:0] are reserved

Port E[31:10, 7:0] are reserved

Port H[31:8, 5:0] are reserved

31 30

MODE15[1:0]

29 28

MODE14[1:0] rw

15 rw

MODE7[1:0] rw rw rw

13 rw

MODE6[1:0] rw rw

27 26

MODE13[1:0] rw

11 rw

MODE5[1:0] rw rw

25 24

MODE12[1:0] rw

9 rw

MODE4[1:0] rw rw

23 22

MODE11[1:0] rw

7 rw

MODE3[1:0] rw rw

21 20

MODE10[1:0] rw

5 rw

MODE2[1:0] rw rw

Bits 31:0 MODE[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O mode.

00: Input mode

01: General purpose output mode

10: Alternate function mode

11: Analog mode (reset state)

19 18

MODE9[1:0] rw

3 rw

MODE1[1:0] rw rw

17 16

MODE8[1:0] rw

1 rw

MODE0[1:0] rw rw

256/1202 RM0471 Rev 5

RM0471 General-purpose I/Os (GPIO)

8.4.2

Res.

GPIO port output type register (GPIOx_OTYPER)

(x = A to C and E and H)

Address offset: 0x04

Reset value: 0x0000 0000

Port B[31:10] are reserved

Port C[31:16, 13:0] are reserved

Port E[31:5, 3:0] are reserved

Port H[31:4, 2:0] are reserved

Res.

15 14 13 12 11 10

OT15 OT14 OT13 OT12 OT11 OT10 rw rw rw rw rw rw

OT9 rw

OT8 rw

OT7 rw

OT6 rw

OT5 rw

OT4 rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OT[15:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O output type.

0: Output push-pull (reset state)

1: Output open-drain

OT3 rw

OT2 rw

8.4.3 GPIO port output speed register (GPIOx_OSPEEDR)

(x = A to C and E and H)

Address offset: 0x08

Reset value: 0x0C00 0000 (for port A)

Reset value: 0x0000 00C0 (for port B)

Reset value: 0x0000 0000 (for other ports)

Port B[31:20] are reserved

Port C[27:0] are reserved

Port E[31:10, 7:0] are reserved

Port H[31:8, 5:0] are reserved

31 30

OSPEED15

[1:0] rw

15 rw

OSPEED7

[1:0] rw rw

29 28

OSPEED14

[1:0] rw

13 rw

OSPEED6

[1:0] rw rw

27 26

OSPEED13

[1:0] rw

11 rw

OSPEED5

[1:0] rw rw

25 24

OSPEED12

[1:0] rw

9 rw

OSPEED4

[1:0] rw rw

23 22

OSPEED11

[1:0] rw

7 rw

OSPEED3

[1:0] rw rw

21 20

OSPEED10

[1:0] rw

5 rw

OSPEED2

[1:0] rw rw

19 18

OSPEED9

[1:0] rw

3 rw

OSPEED1

[1:0] rw rw

OT1 rw

OT0 rw

17 16

OSPEED8

[1:0] rw

1 rw

OSPEED0

[1:0] rw rw

RM0471 Rev 5 257/1202

268

General-purpose I/Os (GPIO) RM0471

Bits 31:0 OSPEED[15:0][1:0] : Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O output speed.

00: Low speed

01: Medium speed

10: Fast speed

11: High speed

Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed..

8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR)

(x = A to C and E and H)

Address offset: 0x0C

Reset value: 0x6400 0000 (for port A)

Reset value: 0x0000 0100 (for port B)

Reset value: 0x0000 0000 (for other ports)

Port B[31:20] are reserved

Port C[27:0] are reserved

Port E[31:10, 7:0] are reserved

Port H[31:8, 5:0] are reserved

31 30

PUPD15[1:0] rw rw

15 14

PUPD7[1:0] rw rw

29 28

PUPD14[1:0] rw rw

13 12

PUPD6[1:0] rw rw

27 26

PUPD13[1:0] rw rw

11 10

PUPD5[1:0] rw rw

25 24

PUPD12[1:0] rw rw

9 8

PUPD4[1:0] rw rw

23 22

PUPD11[1:0] rw rw

7 6

PUPD3[1:0] rw rw

21 20

PUPD10[1:0] rw rw

5 4

PUPD2[1:0] rw rw

19 18

PUPD9[1:0] rw rw

3 2

PUPD1[1:0] rw rw

Bits 31:0 PUPD[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O pull-up or pull-down

00: No pull-up, pull-down

01: Pull-up

10: Pull-down

11: Reserved

17 16

PUPD8[1:0] rw rw

1 0

PUPD0[1:0] rw rw

258/1202 RM0471 Rev 5

RM0471 General-purpose I/Os (GPIO)

8.4.5 GPIO input data register (GPIOx_IDR)

(x = A to C and E and H)

Address offset: 0x10

Reset value: 0x0000 XXXX

Port B[31:10] are reserved

Port C[31:16, 13:0] are reserved

Port E[31:5, 3:0] are reserved

Port H[31:4, 2:0] are reserved

Res.

ID15 r

ID14 r

ID13 r

ID12 r

ID11 r

ID10 r

ID9 r

ID8 r

ID7 r

ID6 r

ID5 r

ID4 r

ID3 r

ID2 r

ID1 r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 ID[15:0]: Port x input data I/O pin y (y = 15 to 0)

These bits are read-only. They contain the input value of the corresponding I/O port.

ID0 r

8.4.6

Res.

GPIO port output data register (GPIOx_ODR)

(x = A to C and E and H)

Address offset: 0x14

Reset value: 0x0000 0000

Port B[31:10] are reserved

Port C[31:16, 13:0] are reserved

Port E[31:5, 3:0] are reserved

Port H[31:4, 2:0] are reserved

Res.

15 14 13 12

OD15 OD14 OD13 OD12 rw rw rw rw

11 10

OD11 OD10 rw rw

OD9 rw

OD8 rw

OD7 rw

OD6 rw

OD5 rw

OD4 rw

OD3 rw

OD2 rw

OD1 rw

OD0 rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OD[15:0]: Port output data I/O pin y (y = 15 to 0)

These bits can be read and written by software.

Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the

GPIOx_BSRR register (x = A..F).

RM0471 Rev 5 259/1202

268

General-purpose I/Os (GPIO) RM0471

8.4.7 GPIO port bit set/reset register (GPIOx_BSRR)

(x = A to C and E and H)

Address offset: 0x18

Reset value: 0x0000 0000

Port B[31:26, 15:10] are reserved

Port C[29:16, 13:0] are reserved

Port E[31:21, 19:5, 3:0] are reserved

Port H[31:20, 18:4, 2:0] are reserved

BR15 w

BS15 w

BR14 w

BS14 w

BR13 w

BS13 w

BR12 w

BS12 w

BR11 w

BS11 w

BR10 w

BS10 w

BR9 w

BS9 w

BR8 w

BS8 w

BR7 w

BS7 w

BR6 w

BS6 w

BR5 w

BS5 w

BR4 w

BS4 w

Bits 31:16 BR[15:0]: Port x reset I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns the value 0x0000.

0: No action on the corresponding ODx bit

1: Resets the corresponding ODx bit

Note: If both BSx and BRx are set, BSx has priority.

Bits 15:0 BS[15:0]: Port x set I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns the value 0x0000.

0: No action on the corresponding ODx bit

1: Sets the corresponding ODx bit

BR3 w

BS3 w

BR2 w

BS2 w

8.4.8

BR1 w

BS1 w

GPIO port configuration lock register (GPIOx_LCKR)

(x = A to C and E and H)

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the

GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the

BR0 w

BS0 w

260/1202 RM0471 Rev 5

RM0471 General-purpose I/Os (GPIO)

Note:

LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.

A specific write sequence is used to write to the GPIOx_LCKR register. Only word access

(32-bit long) is allowed during this locking sequence.

Each lock bit freezes a specific configuration register (control and alternate function registers).

Address offset: 0x1C

Reset value: 0x0000 0000

Port B[31:17, 15:10] are reserved

Port C[31:17, 13:0] are reserved

Port E[31:17, 15:5, 3:0] are reserved

Port H[31:17, 15:4, 2:0] are reserved

Res.

LCKK rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 LCKK: Lock key

This bit can be read any time. It can only be modified using the lock key write sequence.

0: Port configuration lock key not active

1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset.

LOCK key write sequence:

WR LCKR[16] = 1 + LCKR[15:0]

WR LCKR[16] = 0 + LCKR[15:0]

WR LCKR[16] = 1 + LCKR[15:0]

RD LCKR

RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active)

Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.

Any error in the lock sequence aborts the lock.

After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset.

Bits 15:0 LCK[15:0]: Port x lock I/O pin y (y = 15 to 0)

These bits are read/write but can only be written when the LCKK bit is 0.

0: Port configuration not locked

1: Port configuration locked

RM0471 Rev 5 261/1202

268

General-purpose I/Os (GPIO) RM0471

31 rw

15 rw

(x = A to C and E and H)

Address offset: 0x20

Reset value: 0x0000 0000

Port C[31:0] are reserved

Port E[31:20, 15:0] are reserved

Port H[31:16, 11:0] are reserved

30 29

AFSEL7[3:0] rw

14 rw

AFSEL3[3:0] rw rw

28 rw

27 rw

26 25

AFSEL6[3:0] rw

10 rw

AFSEL2[3:0] rw rw

24 rw

23 rw

22 21

AFSEL5[3:0] rw

6 rw

AFSEL1[3:0] rw rw

20 rw

19 rw

3 rw rw rw rw rw rw

Bits 31:0 AFSEL[7:0][3:0]: Alternate function selection for port x I/O pin y (y = 7 to 0)

These bits are written by software to configure alternate function I/Os.

0000: AF0

0001: AF1

0010: AF2

0011: AF3

0100: AF4

0101: AF5

0110: AF6

0111: AF7

1000: AF8

1001: AF9

1010: AF10

1011: AF11

1100: AF12

1101: AF13

1110: AF14

1111: AF15

18 17

AFSEL4[3:0] rw

2 rw

AFSEL0[3:0] rw rw

16 rw

0 rw

262/1202 RM0471 Rev 5

RM0471 General-purpose I/Os (GPIO)

31 rw

15 rw

(x = A to C and E and H)

Address offset: 0x24

Reset value: 0x0000 0000

Port B[31:8] are reserved

Port C[23:0] are reserved

Port E[31:0] are reserved

Port H[31:0] are reserved

30 29

AFSEL15[3:0] rw

14 rw

AFSEL11[3:0] rw rw

28 rw

27 rw

26 25

AFSEL14[3:0] rw

10 rw

AFSEL10[3:0] rw rw

24 rw

23 rw

22 21

AFSEL13[3:0] rw

6 rw

AFSEL9[3:0] rw rw

20 rw

19 rw

3 rw rw rw rw rw rw

Bits 31:0 AFSEL[15:8][3:0]: Alternate function selection for port x I/O pin y (y = 15 to 8)

These bits are written by software to configure alternate function I/Os.

0000: AF0

0001: AF1

0010: AF2

0011: AF3

0100: AF4

0101: AF5

0110: AF6

0111: AF7

1000: AF8

1001: AF9

1010: AF10

1011: AF11

1100: AF12

1101: AF13

1110: AF14

1111: AF15

18 17

AFSEL12[3:0] rw

2 rw

AFSEL8[3:0] rw rw

16 rw

0 rw

RM0471 Rev 5 263/1202

268

General-purpose I/Os (GPIO) RM0471

8.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to C and E and H)

Address offset: 0x28

Reset value: 0x0000 0000

Port B[31:10] are reserved

Port C[31:16, 13:0] are reserved

Port E[31:5, 3:0] are reserved

Port H[31:4, 2:0] are reserved

Res.

BR15 w

BR14 w

BR13 w

BR12 w

BR11 w

BR10 w

BR9 w

BR8 w

BR7 w

BR6 w

BR5 w

BR4 w

BR3 w

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 BR[15:0]: Port x reset IO pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns the value 0x0000.

0: No action on the corresponding ODx bit

1: Reset the corresponding ODx bit

BR2 w

BR1 w

BR0 w

264/1202 RM0471 Rev 5

RM0471 General-purpose I/Os (GPIO)

8.4.12 GPIO register map

The following table gives the GPIO register map and reset values.

Table 39. GPIO register map and reset values

Offset Register name

0x00

GPIOA_MODER

Reset value 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0x00

GPIOB_MODER

Reset value - - - - - - - - - - - 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1

0x00

GPIOC_MODER

Reset value 1 1 1 1

- - - - - - - - - - - - - - - - - - - - - - - - - - - -

0x00

GPIOE_MODER

Reset value

- - - - - - - - - - - - - - - - - - - - - -

1 1

- - - - - - - -

GPIOH_MODER

0x00

0x04

Reset value

GPIOA_OTYPER

- - - - - - - - - - - - - - - - - - - - - - - -

1 1

- - - - - -

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value

GPIOB_OTYPER

Reset value

GPIOC_OTYPER

0 0 0 0 0 0 0 0 0 0

Reset value

GPIOE_OTYPER

Reset value

0 0

Reset value

GPIOH_OTYPER

- - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - -

RM0471 Rev 5 265/1202

268

General-purpose I/Os (GPIO)

Offset Register name

Table 39. GPIO register map and reset values (continued)

RM0471

0x08

GPIOA_OSPEEDR

Reset value 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x08

GPIOB_OSPEEDR

Reset value - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0

0x08

GPIOC_OSPEEDR

Reset value 0 0 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - -

0x08

GPIOE_OSPEEDR

Reset value - - - - - - - - - - - - - - - - - - - - - 0 0 - - - - - - - -

0x08

GPIOH_OSPEEDR

Reset value - - - - - - - - - - - - - - - - - - - - - - - 0 0 - - - - - -

0x0C

GPIOA_PUPDR

Reset value 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0C

GPIOB_PUPDR

0x0C

Reset value

GPIOx_PUPDR

(where x = C, D

Reset value

- - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

0 0 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - -

0x0C

GPIOE_PUPDR

Reset value - - - - - - - - - - - - - - - - - - - - - 0 0 - - - - - - - -

0x0C

GPIOH_PUPDR

Reset value - - - - - - - - - - - - - - - - - - - - - - - 0 0 - - - - - -

266/1202 RM0471 Rev 5

RM0471 General-purpose I/Os (GPIO)

Offset Register name

Table 39. GPIO register map and reset values (continued)

0x10

0x14

0x18

0x1C

Reset value

GPIOB_ODR

Reset value

GPIOC_ODR

Reset value

GPIOE_ODR

Reset value

GPIOH_ODR

Reset value

GPIOA_BSRR

Reset value

GPIOB_BSRR

Reset value

GPIOA_IDR

Reset value

GPIOB_IDR

Reset value

GPIOC_IDR

Reset value

GPIOE_IDR

Reset value

GPIOH_IDR

Reset value

GPIOA_ODR

GPIOC_BSRR

Reset value

GPIOE_BSRR

Reset value

GPIOH_BSRR

Reset value

GPIOA_LCKR

Reset value

GPIOB_LCKR

Reset value

- - - - - - - - - - - - - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - -

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - -

0 0

0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - 0 0 - - - - - - - - - - - - - -

- - - - - - - - - - -

- - - - - - - - - - - -

- - - - - - - - - - - - - - -

- - - - - x

0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - -

- - - x

- - - -

- - -

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0

0 0 0 0 0 0 0 0 0 0

RM0471 Rev 5 267/1202

268

General-purpose I/Os (GPIO) RM0471

Offset Register name

Table 39. GPIO register map and reset values (continued)

0x1C

0x20

0x24

0x28

GPIOC_LCKR

Reset value

GPIOE_LCKR

Reset value

GPIOH_LCKR

Reset value

GPIOx_AFRL

(where x = A,B )

Reset value

GPIOE_AFRL

Reset value

GPIOH_AFRL

Reset value

GPIOA_AFRH

Reset value

GPIOB_AFRH

Reset value

GPIOC_AFRH

Reset value

GPIOA_BRR

Reset value

GPIOB_BRR

Reset value

GPIOC_BRR

Reset value

GPIOE_BRR

Reset value

GPIOH_BRR

Reset value

- - - - - - - - - - - - - - -

0 0 0

0 - - - - - - - - - - -

- - - - - - - - - - - - - - 0 - - - - - - - - - - - 0 - - -

AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0] AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AFSEL4

[3:0]

- - - - - - - - - - - 0 0 0 0 - - - - - - - - - - - - - - - -

AFSEL3

[3:0]

- - - - - - - - - - - - - - - -

0 0 0 0

- - - - - - - - - - - -

AFSEL15

[3:0]

AFSEL14

[3:0]

AFSEL13

[3:0]

AFSEL12

[3:0]

AFSEL11

[3:0]

AFSEL10

[3:0]

AFSEL9

[3:0]

AFSEL8

[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AFSEL9

[3:0]

AFSEL8

[3:0]

0 0 0 0 0 0 0 0

AFSEL15

[3:0]

AFSEL14

[3:0]

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0

0 0 0 0 0 0 0 0 0 0

- - - -

Refer to Section 2.2 on page 55 for the register boundary addresses.

268/1202 RM0471 Rev 5

RM0471

9

System configuration controller (SYSCFG)

System configuration controller (SYSCFG)

9.1 SYSCFG main features

The devices feature a set of configuration registers. The main purposes of the system configuration controller are the following:

 Remapping memory areas

 Managing the external interrupt line connection to the GPIOs

 Managing robustness feature

 Setting SRAM2 and PKA RAM write protection and software erase

 Configuring FPU interrupts

 Enabling /disabling I

C Fast-mode Plus driving capability on some I/Os and voltage booster for I/Os analog switches

 Interrupt pre-masking

9.2.1

Res.

SYSCFG memory remap register (SYSCFG_MEMRMP)

This register is used for specific configurations on memory remap.

Address offset: 0x000

Reset value: 0x0000 000X (X is the memory mode selected by the BOOT0 pin and BOOT1 option bit)

Res.

2 1 0 rw

MEM_MODE[2:0] rw rw

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 MEM_MODE[2:0]: Memory mapping selection

These bits control the memory internal mapping at address 0x0000 0000. These bits are used to select the physical remap by software and so, bypass the BOOT mode setting. After reset these bits take the value selected by BOOT0 (pin or option bit depending on nSWBOOT0 option bit) and BOOT1 option bit.

000: Main Flash memory mapped at CPU1 0x00000000

001: System Flash memory mapped at CPU1 0x00000000

010: Reserved

011: SRAM1 mapped at CPU1 0x00000000

100: Reserved

101: Reserved

110: Reserved

111: Reserved

RM0471 Rev 5 269/1202

284

System configuration controller (SYSCFG) RM0471

31 rw

Res.

Address offset: 0x004

Reset value: 0x7C00 0001

30 29 28

FPU_IE[5:0] rw

Res.

27 rw

Res.

26 rw

Res.

BOOST

EN rw

Res.

I2C1_

FMP rw

Res.

I2C_

PB9_

FMP rw

Res.

I2C_

PB8_

FMP rw

Res.

I2C_

PB7_

FMP rw

Res.

I2C_

PB6_

FMP rw

Res.

Bits 31:26 FPU_IE[5:0] : CPU1 FPU interrupts enable bits

FPU_IE[5]: Inexact interrupt enable

FPU_IE[4]: Input denormal interrupt enable

FPU_IE[3]: Overflow interrupt enable

FPU_IE[2]: underflow interrupt enable

FPU_IE[1]: Divide-by-zero interrupt enable

FPU_IE[0]: Invalid operation interrupt enable

Bits 25:21 Reserved, must be kept at reset value.

Bit 20 I2C1_FMP: I2C1 Fast-mode Plus driving capability activation

This bit enables the Fm+ driving mode on I2C1 pins selected through AF selection bits.

0: Fm+ mode is not enabled on I2C1 pins selected through AF selection bits

1: Fm+ mode is enabled on I2C1 pins selected through AF selection bits.

Bit 19 I2C_PB9_FMP : Fast-mode Plus (Fm+) driving capability activation on PB9

This bit enables the Fm+ driving mode for PB9.

0: PB9 pin operates in standard mode.

1: Fm+ mode enabled on PB9 pin, and the Speed control is bypassed.

Bit 18 I2C_PB8_FMP : Fast-mode Plus (Fm+) driving capability activation on PB8

This bit enables the Fm+ driving mode for PB8.

0: PB8 pin operates in standard mode.

1: Fm+ mode enabled on PB8 pin, and the Speed control is bypassed.

Bit 17 I2C_PB7_FMP : Fast-mode Plus (Fm+) driving capability activation on PB7

This bit enables the Fm+ driving mode for PB7.

0: PB7 pin operates in standard mode.

1: Fm+ mode enabled on PB7 pin, and the Speed control is bypassed.

Bit 16 I2C_PB6_FMP : Fast-mode Plus (Fm+) driving capability activation on PB6

This bit enables the Fm+ driving mode for PB6.

0: PB6 pin operates in standard mode.

1: Fm+ mode enabled on PB6 pin, and the Speed control is bypassed.

Bits 15:9 Reserved, must be kept at reset value.

270/1202 RM0471 Rev 5

RM0471 System configuration controller (SYSCFG)

Bit 8 BOOSTEN: I/O analog switch voltage booster enable

0: I/O analog switches are supplied by V

DDA when using the ADC in high V

DDA

voltage. This is the recommended configuration

voltage operation.

1: I/O analog switches are supplied by a dedicated voltage booster (supplied by V

DD the recommended configuration when using the ADC in low V

DDA

). This is

voltage operation.

Bits 7:0 Reserved, must be kept at reset value.

9.2.3

Res.

SYSCFG external interrupt configuration register 1

(SYSCFG_EXTICR1)

Address offset: 0x008

Reset value: 0x0000 0000

Res.

14 rw

EXTI3[2:0] rw

12 rw

Res.

10 rw

EXTI2[2:0] rw

8 rw

Res.

6 rw

EXTI1[2:0] rw

4 rw

Res.

2 rw

EXTI0[2:0] rw

0 rw

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:12 EXTI3[2:0] : EXTI 3 configuration bits

These bits are written by software to select the source input for the EXTI3 external interrupt.

000: PA[3] pin

001: PB[3] pin

010: Reserved

011: Reserved

100: Reserved

101: Reserved

110: Reserved

111: PH[3] pin

Bit 11 Reserved, must be kept at reset value.

Bits 10:8 EXTI2[2:0] : EXTI 2 configuration bits

These bits are written by software to select the source input for the EXTI2 external interrupt.

000: PA[2] pin

001: PB[2] pin

010: Reserved

011: Reserved

100: Reserved

101: Reserved

110: Reserved

111: Reserved

Bit 7 Reserved, must be kept at reset value.

RM0471 Rev 5 271/1202

284

System configuration controller (SYSCFG) RM0471

Note:

Bits 6:4 EXTI1[2:0] : EXTI 1 configuration bits

These bits are written by software to select the source input for the EXTI1 external interrupt.

000: PA[1] pin

001: PB[1] pin

010: Reserved

011: Reserved

100: Reserved

101: Reserved

110: Reserved

111: Reserved

Bit 3 Reserved, must be kept at reset value.

Bits 2:0 EXTI0[2:0] : EXTI 0 configuration bits

These bits are written by software to select the source input for the EXTI0 external interrupt.

000: PA[0] pin

001: PB[0] pin

010: Reserved

011: Reserved

100: Reserved

101: Reserved

110: Reserved

111: Reserved

Some of the I/O pins mentioned in this register may be not available on small packages.

9.2.4

Res.

SYSCFG external interrupt configuration register 2

(SYSCFG_EXTICR2)

Address offset: 0x00C

Reset value: 0x0000 0000

Res.

14 rw

EXTI7[2:0] rw

12 rw

Res.

10 rw

EXTI6[2:0] rw

8 rw

Res.

6 rw

EXTI5[2:0] rw

4 rw

Res.

2 rw

EXTI4[2:0] rw

0 rw

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:12 EXTI7[2:0] : EXTI 7 configuration bits

These bits are written by software to select the source input for the EXTI7 external interrupt.

000: PA[7] pin

001: PB[7] pin

010: Reserved

011: Reserved

100: Reserved

101: Reserved

110: Reserved

111: Reserved

272/1202 RM0471 Rev 5

RM0471

Note:

9.2.5

System configuration controller (SYSCFG)

Bit 11 Reserved, must be kept at reset value.

Bits 10:8 EXTI6[2:0] : EXTI 6 configuration bits

These bits are written by software to select the source input for the EXTI6 external interrupt.

000: PA[6] pin

001: PB[6] pin

010: Reserved

011: Reserved

100: Reserved

101: Reserved

110: Reserved

111: Reserved

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 EXTI5[2:0] : EXTI 5 configuration bits

These bits are written by software to select the source input for the EXTI5 external interrupt.

000: PA[5] pin

001: PB[5] pin

010: Reserved

011: Reserved

100: Reserved

101: Reserved

110: Reserved

111: Reserved

Bit 3 Reserved, must be kept at reset value.

Bits 2:0 EXTI4[2:0] : EXTI 4 configuration bits

These bits are written by software to select the source input for the EXTI4 external interrupt.

000: PA[4] pin

001: PB[4] pin

010: Reserved

011: Reserved

100: PE[4] pin

101: Reserved

110: Reserved

111: Reserved

Some of the I/O pins mentioned in this register may be not available on small packages.

SYSCFG external interrupt configuration register 3

(SYSCFG_EXTICR3)

Address offset: 0x010

Reset value: 0x0000 0000

RM0471 Rev 5 273/1202

284

System configuration controller (SYSCFG) RM0471

Res.

14 rw

EXTI11[2:0] rw

12 rw

Res.

10 rw

EXTI10[2:0] rw

8 rw

Res.

6 rw

EXTI9[2:0] rw

4 rw

Res.

2 rw

EXTI8[2:0] rw

0 rw

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:12 EXTI11[2:0] : EXTI 11 configuration bits

These bits are written by software to select the source input for the EXTI11 external interrupt.

000: PA[11] pin

001: Reserved

010: Reserved

011: Reserved

100: Reserved

101: Reserved

110: Reserved

111: Reserved

Bit 11 Reserved, must be kept at reset value.

Bits 10:8 EXTI10[2:0] : EXTI 10 configuration bits

These bits are written by software to select the source input for the EXTI10 external interrupt.

000: PA[10] pin

001: Reserved

010: Reserved

011: Reserved

100: Reserved

101: Reserved

110: Reserved

111: Reserved

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 EXTI9[2:0] : EXTI 9 configuration bits

These bits are written by software to select the source input for the EXTI9 external interrupt.

000: PA[9] pin

001: PB[9] pin

010: Reserved

011: Reserved

100: Reserved

101: Reserved

110: Reserved

111: Reserved

Bit 3 Reserved, must be kept at reset value.

274/1202 RM0471 Rev 5

RM0471 System configuration controller (SYSCFG)

Note:

Bits 2:0 EXTI8[2:0] : EXTI 8 configuration bits

These bits are written by software to select the source input for the EXTI8 external interrupt.

000: PA[8] pin

001: PB[8] pin

010: Reserved

011: Reserved

100: Reserved

101: Reserved

110: Reserved

111: Reserved

Some of the I/O pins mentioned in this register may be not available on small packages.

9.2.6

Res.

SYSCFG external interrupt configuration register 4

(SYSCFG_EXTICR4)

Address offset: 0x014

Reset value: 0x0000 0000

Res.

14 rw

EXTI15[2:0] rw

12 rw

Res.

10 rw

EXTI14[2:0] rw

8 rw

Res.

6 rw

EXTI13[2:0] rw

4 rw

Res.

2 rw

EXTI12[2:0] rw

0 rw

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:12 EXTI15[2:0] : EXTI15 configuration bits

These bits are written by software to select the source input for the EXTI15 external interrupt.

000: PA[15] pin

001: Reserved

010: PC[15] pin

011: Reserved

100: Reserved

101: Reserved

110: Reserved

111: Reserved

Bit 11 Reserved, must be kept at reset value.

Bits 10:8 EXTI14[2:0] : EXTI14 configuration bits

These bits are written by software to select the source input for the EXTI14 external interrupt.

000: PA[14] pin

001: Reserved

010: PC[14] pin

011: Reserved

100: Reserved

101: Reserved

110: Reserved

111: Reserved

RM0471 Rev 5 275/1202

284

System configuration controller (SYSCFG) RM0471

Note:

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 EXTI13[2:0] : EXTI13 configuration bits

These bits are written by software to select the source input for the EXTI13 external interrupt.

000: PA[13] pin

001: Reserved

010: Reserved

011: Reserved

100: Reserved

101: Reserved

110: Reserved

111: Reserved

Bit 3 Reserved, must be kept at reset value.

Bits 2:0 EXTI12[2:0] : EXTI12 configuration bits

These bits are written by software to select the source input for the EXTI12 external interrupt.

000: PA[12] pin

001: Reserved

010: Reserved

011: Reserved

100: Reserved

101: Reserved

110: Reserved

111: Reserved

Some of the I/O pins mentioned in this register may be not available on small packages.

9.2.7 SYSCFG SRAM2 control and status register (SYSCFG_SCSR)

Address offset: 0x18

System reset value: 0x0000 0000

31 30

C2RFD Res.

15 14

Res.

1 0

SRAM2

BSY r

SRAM2

ER rw

Bit 31 C2RFD : CPU2 SRAM fetch (execution) disable.

This bit can be set by software and be reset by a hardware reset, including a reset after Standby. Software writing 'b0 has no effect.

0: CPU2 fetch from SRAM1, SRAM2a and SRAM2b enabled, allows CPU2 to fetch and execute code from SRAMs

1: CPU2 fetch from SRAM1, SRAM2a and SRAM2b disabled, Any CPU2 fetch from SRAMs generates a bus error.

Bits 30:2 Reserved, must be kept at reset value.

276/1202 RM0471 Rev 5

RM0471 System configuration controller (SYSCFG)

Bit 1 SRAM2BSY: SRAM2 and PKA RAM busy by erase operation

0: Nor SRAM2 neither PKA RAM erase operation is on going.

1: SRAM2 and/or PKA RAM erase operation is on going.

Bit 0 SRAM2ER: SRAM2 and PKA RAM Erase

Setting this bit starts a hardware SRAM2 and PKA RAM erase operation. This bit is automatically cleared at the end of the SRAM2 and PKA RAM erase operation.

Note: This bit is write-protected: setting this bit is possible only after the correct key sequence is written in the SYSCFG_SKR register.

Res.

Address offset: 0x01C

System reset value: 0x0000 0000

Res.

SPF rc_w1

Res.

3 2

ECCL PVDL rs rs

SPL rs

CLL rs

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 SPF : SRAM2 parity error flag

This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software by writing ‘1’.

0: No SRAM2 parity error detected

1: SRAM2 parity error detected

Bits 7:4 Reserved, must be kept at reset value.

Bit 3 ECCL : ECC Lock

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the Flash ECC error connection to TIM1/16/17 Break input.

0: ECC error disconnected from TIM1/16/17 Break input.

1: ECC error connected to TIM1/16/17 Break input.

Bit 2 PVDL : PVD lock enable bit

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection to TIM1/16/17 Break input, as well as the

PVDE and PLS[2:0] in the PWR_CR2 register.

0: PVD interrupt disconnected from TIM1/16/17 Break input. PVDE and PLS[2:0] bits can be programmed by the application.

1: PVD interrupt connected to TIM1/16/17 Break input, PVDE and PLS[2:0] bits are read only.

Bit 1 SPL : SRAM2 parity lock bit

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/16/17 Break inputs.

0: SRAM2 parity error signal disconnected from TIM1/16/17 Break inputs

1: SRAM2 parity error signal connected to TIM1/16/17 Break inputs

RM0471 Rev 5 277/1202

284

System configuration controller (SYSCFG) RM0471

Bit 0 CLL: CPU1 LOCKUP (Hardfault) output enable bit

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the connection of CPU1 LOCKUP (Hardfault) output to

TIM1/16/17 Break input

0: CPU1 LOCKUP output disconnected from TIM1/16/17 Break inputs

1: CPU1 LOCKUP output connected to TIM1/16/17 Break inputs

Address offset: 0x020

System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

P31WP P30WP P29WP P28WP P27WP P26WP P25WP P24WP P23WP P22WP P21WP P20WP P19WP P18WP P17WP P16WP rs

15 rs

14 rs

13 rs

12 rs

11 rs

10 rs

9 rs

8 rs

7 rs

6 rs

5 rs

4 rs

3 rs

2 rs

1 rs

P15WP P14WP P13WP P12WP P11WP P10WP P9WP P8WP P7WP P6WP P5WP P4WP P3WP P2WP P1WP P0WP rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs

Bits 31:0 PxWP (x= 0 to 31): SRAM2 1Kbyte page x write protection

These bits are set by software and cleared only by a system reset.

0: Write protection of SRAM2 1Kbyte page x is disabled.

1: Write protection of SRAM2 1Kbyte page x is enabled.

Res.

Address offset: 0x024

System reset value: 0x0000 0000

Res.

7 w

6 w

5 w

4 3

KEY[7:0] w w

2 w

1 w

0 w

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 KEY[7:0] : SRAM2 write protection key for software erase

The following steps are required to unlock the write protection of the SRAM2ER bit in the SYSCFG_CFGR2 register.

1. Write 0xCA into Key[7:0]

2. Write 0x53 into Key[7:0]

Writing a wrong key reactivates the write protection.

278/1202

Address offset: 0x028

System reset value: 0x0000 0000

RM0471 Rev 5

RM0471 System configuration controller (SYSCFG)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

P63WP P62WP P61WP P60WP P59WP P58WP P57WP P56WP P55WP P54WP P53WP P52WP P51WP P50WP P49WP P48WP rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

P47WP P46WP P45WP P44WP P43WP P42WP P41WP P40WP P39WP P38WP P37WP P36WP P35WP P34WP P33WP P32WP rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs

Bits 31:0 PxWP (x= 32 to 63): SRAM2 1 Kbyte page x write protection

These bits are set by software and cleared only by a system reset.

0: Write protection of SRAM2 1 Kbyte page x is disabled.

1: Write protection of SRAM2 1 Kbyte page x is enabled.

9.2.12 SYSCFG CPU1 interrupt mask register 1 (SYSCFG_IMR1)

Address offset: 0x100

System reset value: 0x0000 0000

EXTI15

IM rw

EXTI14

IM rw

EXTI13

IM rw

TIM17

IM rw

TIM16

IM rw

TIM1

IM rw

28 27 26

EXTI12

IM rw

EXTI11I

M rw

EXTI10

IM rw

12 11 10

Res.

EXTI9

IM rw

Res.

EXTI8

IM rw

Res.

EXTI7

IM rw

Res.

EXTI6

IM rw

Res.

EXTI5

IM rw

Res.

Bits 31:21 xxxIM : Peripheral xxx interrupt mask to CPU1

0: Peripheral xxx interrupt forwarded to CPU1

1. Peripheral xxx interrupt to CPU1 masked.

Bits 20:16 Reserved, must be kept at reset value.

Bits 15:13 xxxIM : Peripheral xxx interrupt mask to CPU1

0: Peripheral xxx interrupt forwarded to CPU1

1. Peripheral xxx interrupt to CPU1 masked.

Bits 12:0 Reserved, must be kept at reset value.

Res.

9.2.13 SYSCFG CPU1 interrupt mask register 2 (SYSCFG_IMR2)

Address offset: 0x104

System reset value: 0x0000 0000

Res.

21 20

Res.

PVDIM

Res.

RM0471 Rev 5 279/1202

284

System configuration controller (SYSCFG) RM0471

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 xxxIM : Peripheral xxx interrupt mask to CPU1

0: Peripheral xxx interrupt forwarded to CPU1

1. Peripheral xxx interrupt to CPU1 masked.

Bits 19:18 Reserved, must be kept at reset value.

Bits 17:0 Reserved, must be kept at reset value.

9.2.14 SYSCFG CPU2 interrupt mask register 1 (SYSCFG_C2IMR1)

Address offset: 0x108

System reset value: 0x0000 0000

EXTI15

IM rw

EXTI14

IM rw

EXTI13

IM rw

EXTI12

IM rw

EXTI11

IM rw

EXTI10

IM rw

EXTI9

IM rw

Res.

ADC

IM rw

Res.

RNG

IM rw

EXTI8

IM rw

EXTI7

IM rw

PKA

IM rw

Res.

EXTI6

IM rw

FLASH

IM rw

EXTI5

IM rw

EXTI4

IM rw

EXTI3

IM rw

RCC

RTC

ALARM

RTC

WKUP

IM rw rw rw

EXTI2

IM rw

EXTI1

IM rw

Res.

EXTI0

IM rw

RTC

STAMP

TAMP

LSECSS

IM rw

Bits 31:16 xxxIM : Peripheral xxx interrupt mask to CPU2

0: Peripheral xxx interrupt forwarded to CPU2

1. Peripheral xxx interrupt to CPU2 masked.

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 xxxIM : Peripheral xxx interrupt mask to CPU2

0: Peripheral xxx interrupt forwarded to CPU2

1. Peripheral xxx interrupt to CPU2 masked.

Bits 11:10 Reserved, must be kept at reset value.

Bits 9:8 xxxIM : Peripheral xxx interrupt mask to CPU2

0: Peripheral xxx interrupt forwarded to CPU2

1. Peripheral xxx interrupt to CPU2 masked.

Bit 7 Reserved, must be kept at reset value.

Bits 6:3 xxxIM : Peripheral xxx interrupt mask to CPU2

0: Peripheral xxx interrupt forwarded to CPU2

1. Peripheral xxx interrupt to CPU2 masked.

Bits 2:1 Reserved, must be kept at reset value.

Bit 0 xxxIM : Peripheral xxx interrupt mask to CPU2

0: Peripheral xxx interrupt forwarded to CPU2

1. Peripheral xxx interrupt to CPU2 masked.

9.2.15 SYSCFG CPU2 interrupt mask register 2 (SYSCFG_C2IMR2)

Address offset: 0x10C

280/1202 RM0471 Rev 5

RM0471 System configuration controller (SYSCFG)

Res.

System reset value: 0x0000 0000

Res.

DMA

MUX1

IM rw

Res.

DMA1

CH7

IM rw

DMA1

CH6

IM rw

PVD

IM rw

DMA1

CH5

IM rw

Res.

DMA1

CH4

IM rw

DMA1

CH3

IM rw

Res.

DMA1

CH2

IM rw

DMA1

CH1

IM rw

Bits 31:21 Reserved, must be kept at reset value.

Bit:20 xxxIM : Peripheral xxx interrupt mask to CPU2

0: Peripheral xxx interrupt forwarded to CPU2

1. Peripheral xxx interrupt to CPU2 masked.

Bits 19:16 Reserved, must be kept at reset value.

Bit15 xxxIM : Peripheral xxx interrupt mask to CPU2

0: Peripheral xxx interrupt forwarded to CPU2

1. Peripheral xxx interrupt to CPU2 masked.

Bits 14:7 Reserved, must be kept at reset value.

Bits 6:0 xxxIM : Peripheral xxx interrupt mask to CPU2

0: Peripheral xxx interrupt forwarded to CPU2

1. Peripheral xxx interrupt to CPU2 masked.

9.2.16 SYSCFG secure IP control register (SYSCFG_SIPCR)

Address offset: 0x110

System reset value: 0x0000 0000

This register provides write access security and can only be written by the CPU2. A write access from the CPU1 is ignored and a bus error is generated. On any read access the register value is returned.

Res.

4 3 2 1 0

Res.

SRNG SPKA SAES2 Res.

rw rw rw

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 SRNG : Enable True RNG security

0: True RNG security disabled. (RNG registers can be accessed by both CPU1 and CPU2)

1: True RNG security enabled. (RNG registers can only be accessed by the

CPU2. Write accesses by the CPU1 generate a bus error, read access return 0 value).

RM0471 Rev 5 281/1202

284

System configuration controller (SYSCFG) RM0471

Bit 2 SPKA : Enable PKA security

0: PKA security disabled (PKA registers can be accessed by both CPU1 and

CPU2)

1: PKA security enabled. PKA registers can only be accessed by the CPU2.

Write accesses by the CPU1 generate a bus error, read access return 0 value.

When this bis is set and a system reset occurs (including a reset due to wakeup from Standby) the PKA RAM is erased.

Bit 1 SAES2 : Enable AES2 security

0: AES2 security disabled (AES2 registers can be accessed by both CPU1 and

CPU2)

1: AES2 security enabled. (AES2 registers can only be accessed by the CPU2.

Write accesses by the CPU1 generate a bus error, read access return 0 value).

Bit 0 Reserved, must be kept at reset value.

282/1202 RM0471 Rev 5

RM0471 System configuration controller (SYSCFG)

9.2.17 SYSCFG register map

The following table summarizes the SYSCFG register map and the reset values.

Table 40. SYSCFG register map and reset values

Offset Register

0x000

SYSCFG_

MEMRMP

Reset value x x x

0x004

SYSCFG_CFGR1 FPU_IE[5..0]

0x008

0x00C

0x010

0x014

Reset value

SYSCFG_EXTICR1

0 1 1 1 1 1

Reset value

SYSCFG_EXTICR2

Reset value

SYSCFG_EXTICR3

Reset value

SYSCFG_EXTICR4

Reset value

0 0 0 0 0

EXTI3

[2:0]

0 0 0

EXTI7

[2:0]

0 0 0

EXTI11

[2:0]

0 0 0

EXTI15

[2:0]

0 0 0

EXTI2

[2:0]

0 0 0

EXTI6

[2:0]

0 0 0

EXTI10

[2:0]

0 0 0

EXTI14

[2:0]

0 0 0

EXTI1

[2:0]

0 0 0

EXTI5

[2:0]

0 0 0

EXTI9

[2:0]

0 0 0

EXTI13

[2:0]

0 0 0

SYSCFG_SCSR

0x018

0x01C

Reset value

SYSCFG_CFGR2

Reset value

SYSCFG_SWPR

0x020

0x024

Reset value

SYSCFG_SKR

Reset value

0 0

0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

KEY

0 0 0 0 0 0 0 0

0x028

SYSCFG_SWPR2

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI0

[2:0]

0 0 0

EXTI4

[2:0]

0 0 0

EXTI8

[2:0]

0 0 0

EXTI12

[2:0]

0 0 0

RM0471 Rev 5 283/1202

284

System configuration controller (SYSCFG)

Table 40. SYSCFG register map and reset values (continued)

Offset Register

0x100

SYSCFG_IMR1

0x104

Reset value

SYSCFG_IMR2

Reset value

0 0 0 0 0 0 0 0 0 0 0

0 0 0

RM0471

0x108

SYSCFG_C2IMR1

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x10C

SYSCFG_C2IMR2

0x110

Reset value

SYSCFG_SIPCR

Reset value

0 0

Refer to Section 2.2 on page 55 for the register boundary addresses.

0 0 0

0 0 0 0 0 0 0

284/1202 RM0471 Rev 5

RM0471

10 Peripherals interconnect matrix

Peripherals interconnect matrix

10.1 Introduction

Several peripherals have direct connections, enabling autonomous communication and/or synchronization between them. This saves CPU resources and, consequently, reduces power consumption. In addition, these hardware connections remove software latency and result in more predictable system design.

Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes.

Source

TIM1

Table 41. Peripherals interconnect matrix

(1) (2)

Destination

TIM2 TIM16 TIM17 LPTIM1 LPTIM2 ADC1

TIM1

TIM2

TIM16

TIM17

LPTIM1

LPTIM2

ADC1

Temp. sensor

VBAT

VREFINT

HSE

LSE

MSI

LSI

MCO

EXTI

RTC

SYST ERR

1. Numbers in table are links to corresponding subsections of

Section 10.3: Interconnection details

2. The “-” symbol in grayed cells means no interconnect.

IRTIM

RM0471 Rev 5 285/1202

289

Peripherals interconnect matrix RM0471

10.3.1 From timer (TIM1/TIM2/TIM17) to timer (TIM1/TIM2)

Purpose

Some of the timers are linked together internally for synchronization or chaining.

When one timer is configured in Master Mode, it can reset, start, stop or clock the counter of another timer configured in Slave Mode. A description of the feature is provided in

Section 19.3.26: Timer synchronization .

The modes of synchronization are detailed in:



Section 19.3.26: Timer synchronization for advanced-control timers (TIM1)



Section 20.3.18: Timers and external trigger synchronization for general-purpose

timers (TIM2)

Triggering signals

The output (from Master) is on signal TIMx_TRGO (and TIMx_TRGO2 for TIM1) following a configurable timer event. The input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3.

The input and output signals for TIM1 are shown in Figure 115: Advanced-control timer block diagram

The possible master/slave connections are given in:



Table 127: TIM1 internal trigger connection



Table 131: TIM2 internal trigger connection

Active power mode(s)

Run, Sleep, Low-power run, Low-power sleep.

10.3.2 From timer (TIM1/TIM2) and EXTI to ADC (ADC1)

Purpose

General-purpose timer TIM2, advanced-control timer TIM1 and EXTI can be used to generate an ADC triggering event.

TIMx synchronization is described in

Section 19.3.27: ADC synchronization .

ADC synchronization is described in Section 15.5: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) .

Triggering signals

The output (from timer) is on signal TIMx_TRGO, TIMx_TRGO2 or TIMx_CCx event.

The input (to ADC) is on signals EXT[15:0] and JEXT[15:0].

The connection between timers and ADC is provided in:



Table 67: ADC1 - External triggers for regular channels



Table 68: ADC1 - External trigger for injected channels

286/1202 RM0471 Rev 5

RM0471 Peripherals interconnect matrix

Active power mode(s)

Run, Sleep, Low-power run, Low-power sleep.

10.3.3 From ADC (ADC1) to timer (TIM1)

Purpose

ADC1 can provide trigger event through watchdog signals to advanced-control timers

(TIM1).

A description of the ADC analog watchdog setting is provided in

Section 15.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH,

AWD_HTx, AWD_LTx, AWDx)

Trigger settings on the timer are provided in

Section 19.3.4: External trigger input

Triggering signals

The output (from ADC) is on signals ADC_AWDx_OUT n = 1, 2, 3 (for ADC1) x = 1, 2, 3

(three watchdogs on ADC) and the input (to timer) on signal TIMx_ETR (external trigger).

Active power mode(s)

Run, Sleep, Low-power run, Low-power sleep.

10.3.4 From HSE, LSE, LSI, MSI, MCO, RTC to timers

(TIM2/TIM16/TIM17)

Purpose

External clocks (HSE, LSE), internal clocks (LSI, MSI), microcontroller output clock (MCO),

GPIO and RTC wakeup interrupt can be used as input to general-purpose timers (TIM16/17) channel 1.

This makes possible calibration of the HSI16/MSI system clocks (with TIM16 and LSE) or of the LSI (with TIM16 and HSE). This is also used to precisely measure LSI (with TIM16 and

HSI16) or MSI (with TIM17 and HSI16) oscillator frequency.

When Low Speed External (LSE) oscillator is used, no additional hardware connections are required.

This feature is described in Section 7.2.20: Internal/external clock measurement with

TIM16/TIM17

External clock LSE can be used as input to general-purpose timer (TIM2) on TIM2_ETR pin,

see Section 7.2.20: Internal/external clock measurement with TIM16/TIM17

Active power mode(s)

Run, Sleep, Low-power run, Low-power sleep.

RM0471 Rev 5 287/1202

289

Peripherals interconnect matrix RM0471

10.3.5 From RTC to low-power timers (LPTIM1/LPTIM2)

Purpose

RTC alarm A/B, RTC_TAMP2 input detection can be used as trigger to start LPTIM counters

(LPTIM1/2).

Triggering signals

This trigger feature is described in

Section 22.4.7: Trigger multiplexer

(and following sections).

The input selection is described in

Table 140: LPTIM1 external trigger connection and

Table 141: LPTIM2 external trigger connection .

Active power mode(s)

Run, Sleep, Low-power run, Low-power sleep, Stop 0, Stop 1, Stop 2 (LPTIM1 only).

10.3.6 From internal analog to ADC1

Purpose

Internal temperature sensor (VTS), internal reference voltage (VREFINT) and VBAT monitoring channel are connected to ADC1 input channel.

This is according to:

 Section 15.2: ADC main features

 Section 15.4.8: Channel selection (CHSEL, SCANDIR, CHSELRMOD)

 Section 15.10: Temperature sensor and internal reference voltage

 Section 15.11: ADC interrupts

Active power mode(s)

Run, Sleep, low-power run, Low-power sleep.

10.3.7 From system errors to timers (TIM1/TIM16/TIM17)

Purpose

CSS, CPU hard fault, RAM parity error, FLASH ECC double error detection, PVD can generate system errors in the form of timer break toward timers TIM1/TIM16/TIM17.

The purpose of the break function is to protect power switches driven by PWM signals generated by the timers.

List(s) of possible break source(s) are described in:



Section 19.3.16: Using the break function

(TIM1)



Section 21.3.11: Using the break function (TIM16/TIM17)



Figure 224: TIM16/TIM17 block diagram

Active power mode(s)

Run, Sleep, Low-power run, Low-power sleep.

288/1202 RM0471 Rev 5

RM0471 Peripherals interconnect matrix

10.3.8 From timers (TIM16/TIM17) to IRTIM

Purpose

General-purpose timer (TIM16/TIM17) output channel TIMx_OC1 are used to generate the waveform of infrared signal output.

The functionality is described in Section 23: Infrared interface (IRTIM)

Active power mode(s)

Run, Sleep, Low-power run, Low-power sleep.

RM0471 Rev 5 289/1202

289

Direct memory access controller (DMA)

11 Direct memory access controller (DMA)

RM0471

11.1 Introduction

The direct memory access (DMA) controller is a bus master and system peripheral.

The DMA is used to perform programmable data transfers between memory-mapped peripherals and/or memories, upon the control of an off-loaded CPU.

The DMA controller features a single AHB master architecture.

There is one instance of DMA with 7 channels.

Each channel is dedicated to managing memory access requests from one or more peripherals. The DMA includes an arbiter for handling the priority between DMA requests.

11.2 DMA main features

 Single AHB master

 Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-toperipheral data transfers

 Access, as source and destination, to on-chip memory-mapped devices such as Flash memory, SRAM, and AHB and APB peripherals

 All DMA channels independently configurable:

– Each channel is associated either with a DMA request signal coming from a peripheral, or with a software trigger in memory-to-memory transfers. This configuration is done by software.

– Priority between the requests is programmable by software (4 levels per channel: very high, high, medium, low) and by hardware in case of equality (such as request to channel 1 has priority over request to channel 2).

– Transfer size of source and destination are independent (byte, half-word, word), emulating packing and unpacking. Source and destination addresses must be aligned on the data size.

– Support of transfers from/to peripherals to/from memory with circular buffer management

– Programmable number of data to be transferred: 0 to 2 16 - 1

 Generation of an interrupt request per channel. Each interrupt request is caused from any of the three DMA events: transfer complete, half transfer, or transfer error.

290/1202 RM0471 Rev 5

RM0471 Direct memory access controller (DMA)

11.3.1 DMA1

DMA1 is implemented with the hardware configuration parameters shown in the table below.

Table 42. DMA1 implementation

Number of channels

Feature DMA1

The DMA controller is connected to DMA requests from the AHB/APB peripherals through the DMAMUX peripheral.

For the mapping of the different requests, refer to the DMAMUX section.

11.4 DMA functional description

The DMA block diagram is shown in the figure below.

Figure 24. DMA block diagram

DMA

Ch 1

Ch 2

AHB master interface

Ch 7 dma_req [1..7] dma_ack [1..7]

Arbiter

Interrupt interface

AHB slave interface dma_it[1..7]

MSv48187V1

RM0471 Rev 5 291/1202

309

Direct memory access controller (DMA) RM0471

The DMA controller performs direct memory transfer by sharing the AHB system bus with other system masters. The bus matrix implements round-robin scheduling. DMA requests may stop the CPU access to the system bus for a number of bus cycles, when CPU and

DMA target the same destination (memory or peripheral).

According to its configuration through the AHB slave interface, the DMA controller arbitrates between the DMA channels and their associated received requests. The DMA controller also schedules the DMA data transfers over the single AHB port master.

The DMA controller generates an interrupt per channel to the interrupt controller.

11.4.2 DMA pins and internal signals

Signal name

Table 43. DMA internal input/output signals

Signal type Description dma_req[x] dma_ack[x] dma_it[x]

Input

Output

DMA channel x request

DMA channel x acknowledge

DMA channel x interrupt

292/1202

The software configures the DMA controller at channel level, in order to perform a block transfer, composed of a sequence of AHB bus transfers.

A DMA block transfer may be requested from a peripheral, or triggered by the software in case of memory-to-memory transfer.

After an event, the following steps of a single DMA transfer occur:

The peripheral sends a single DMA request signal to the DMA controller.

2. The DMA controller serves the request, depending on the priority of the channel associated to this peripheral request.

3. As soon as the DMA controller grants the peripheral, an acknowledge is sent to the peripheral by the DMA controller.

4. The peripheral releases its request as soon as it gets the acknowledge from the DMA controller.

5. Once the request is de-asserted by the peripheral, the DMA controller releases the acknowledge.

The peripheral may order a further single request and initiate another single DMA transfer.

The request/acknowledge protocol is used when a peripheral is either the source or the destination of the transfer. For example, in case of memory-to-peripheral transfer, the peripheral initiates the transfer by driving its single request signal to the DMA controller. The

DMA controller reads then a single data in the memory and writes this data to the peripheral.

For a given channel x, a DMA block transfer consists of a repeated sequence of:

 a single DMA transfer, encapsulating two AHB transfers of a single data, over the DMA

AHB bus master:

– a single data read (byte, half-word or word) from the peripheral data register or a location in the memory, addressed through an internal current peripheral/memory address register.

RM0471 Rev 5

RM0471

Note:

Direct memory access controller (DMA)

The start address used for the first single transfer is the base address of the peripheral or memory, and is programmed in the DMA_CPARx or DMA_CMARx register.

– a single data write (byte, half-word or word) to the peripheral data register or a location in the memory, addressed through an internal current peripheral/memory address register.

The start address used for the first transfer is the base address of the peripheral or memory, and is programmed in the DMA_CPARx or DMA_CMARx register.

 post-decrementing of the programmed DMA_CNDTRx register

This register contains the remaining number of data items to transfer (number of AHB

‘read followed by write’ transfers).

This sequence is repeated until DMA_CNDTRx is null.

The AHB master bus source/destination address must be aligned with the programmed size of the transferred single data to the source/destination.

The DMA arbiter manages the priority between the different channels.

When an active channel x is granted by the arbiter (hardware requested or software triggered), a single DMA transfer is issued (such as a AHB ‘read followed by write’ transfer of a single data). Then, the arbiter considers again the set of active channels and selects the one with the highest priority.

The priorities are managed in two stages:

 software: priority of each channel is configured in the DMA_CCRx register, to one of the four different levels:

– very high

– high

– medium

– low

 hardware: if two requests have the same software priority level, the channel with the lowest index gets priority. For example, channel 2 gets priority over channel 4.

When a channel x is programmed for a block transfer in memory-to-memory mode, re arbitration is considered between each single DMA transfer of this channel x. Whenever there is another concurrent active requested channel, the DMA arbiter automatically alternates and grants the other highest-priority requested channel, which may be of lower priority than the memory-to-memory channel.

Each channel may handle a DMA transfer between a peripheral register located at a fixed address, and a memory address. The amount of data items to transfer is programmable.

The register that contains the amount of data items to transfer is decremented after each transfer.

A DMA channel is programmed at block transfer level.

RM0471 Rev 5 293/1202

309

Direct memory access controller (DMA)

Note:

RM0471

Programmable data sizes

The transfer sizes of a single data (byte, half-word, or word) to the peripheral and memory are programmable through, respectively, the PSIZE[1:0] and MSIZE[1:0] fields of the

DMA_CCRx register.

Pointer incrementation

The peripheral and memory pointers may be automatically incremented after each transfer, depending on the PINC and MINC bits of the DMA_CCRx register.

If the incremented mode is enabled (PINC or MINC set to 1), the address of the next transfer is the address of the previous one incremented by 1, 2 or 4, depending on the data size defined in PSIZE[1:0] or MSIZE[1:0]. The first transfer address is the one programmed in the DMA_CPARx or DMA_CMARx register. During transfers, these registers keep the initially programmed value. The current transfer addresses (in the current internal peripheral/memory address register) are not accessible by software.

If the channel x is configured in non-circular mode , no DMA request is served after the last data transfer (once the number of single data to transfer reaches zero). The DMA channel must be disabled in order to reload a new number of data items into the DMA_CNDTRx register.

If the channel x is disabled, the DMA registers are not reset. The DMA channel registers

(DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during the channel configuration phase.

In circular mode , after the last data transfer, the DMA_CNDTRx register is automatically reloaded with the initially programmed value. The current internal address registers are reloaded with the base address values from the DMA_CPARx and DMA_CMARx registers.

Channel configuration procedure

The following sequence is needed to configure a DMA channel x:

Set the peripheral register address in the DMA_CPARx register.

The data is moved from/to this address to/from the memory after the peripheral event, or after the channel is enabled in memory-to-memory mode.

2. Set the memory address in the DMA_CMARx register.

The data is written to/read from the memory after the peripheral event or after the channel is enabled in memory-to-memory mode.

3. Configure the total number of data to transfer in the DMA_CNDTRx register.

After each data transfer, this value is decremented.

4. Configure the parameters listed below in the DMA_CCRx register:

– the channel priority

– the data transfer direction

– the circular mode

– the peripheral and memory incremented mode

– the peripheral and memory data size

– the interrupt enable at half and/or full transfer and/or transfer error

5. Activate the channel by setting the EN bit in the DMA_CCRx register.

A channel, as soon as enabled, may serve any DMA request from the peripheral connected to this channel, or may start a memory-to-memory block transfer.

294/1202 RM0471 Rev 5

RM0471

Note:

Direct memory access controller (DMA)

The two last steps of the channel configuration procedure may be merged into a single access to the DMA_CCRx register, to configure and enable the channel.

Channel state and disabling a channel

A channel x in active state is an enabled channel (read DMA_CCRx.EN = 1). An active channel x is a channel that must have been enabled by the software (DMA_CCRx.EN set to 1) and afterwards with no occurred transfer error (DMA_ISR.TEIFx = 0). In case there is a transfer error, the channel is automatically disabled by hardware (DMA_CCRx.EN = 0).

The three following use cases may happen:

 Suspend and resume a channel

This corresponds to the two following actions:

– An active channel is disabled by software (writing DMA_CCRx.EN = 0 whereas

DMA_CCRx.EN = 1).

– The software enables the channel again (DMA_CCRx.EN set to 1) without reconfiguring the other channel registers (such as DMA_CNDTRx, DMA_CPARx and DMA_CMARx).

This case is not supported by the DMA hardware, that does not guarantee that the remaining data transfers are performed correctly.

 Stop and abort a channel

If the application does not need any more the channel, this active channel can be disabled by software. The channel is stopped and aborted but the DMA_CNDTRx register content may not correctly reflect the remaining data transfers versus the aborted source and destination buffer/register.

 Abort and restart a channel

This corresponds to the software sequence: disable an active channel, then reconfigure the channel and enable it again.

This is supported by the hardware if the following conditions are met:

– The application guarantees that, when the software is disabling the channel, a

DMA data transfer is not occurring at the same time over its master port. For example, the application can first disable the peripheral in DMA mode, in order to ensure that there is no pending hardware DMA request from this peripheral.

– The software must operate separated write accesses to the same DMA_CCRx register: First disable the channel. Second reconfigure the channel for a next block transfer including the DMA_CCRx if a configuration change is needed. There are read-only DMA_CCRx register fields when DMA_CCRx.EN=1. Finally enable again the channel.

When a channel transfer error occurs, the EN bit of the DMA_CCRx register is cleared by hardware. This EN bit can not be set again by software to re-activate the channel x, until the

TEIFx bit of the DMA_ISR register is set.

Circular mode (in memory-to-peripheral/peripheral-to-memory transfers)

The circular mode is available to handle circular buffers and continuous data flows (such as

ADC scan mode). This feature is enabled using the CIRC bit in the DMA_CCRx register.

The circular mode must not be used in memory-to-memory mode. Before enabling a channel in circular mode (CIRC = 1), the software must clear the MEM2MEM bit of the

DMA_CCRx register. When the circular mode is activated, the amount of data to transfer is

RM0471 Rev 5 295/1202

309

Direct memory access controller (DMA)

Note:

RM0471 automatically reloaded with the initial value programmed during the channel configuration phase, and the DMA requests continue to be served.

In order to stop a circular transfer, the software needs to stop the peripheral from generating

DMA requests (such as quit the ADC scan mode), before disabling the DMA channel.

The software must explicitly program the DMA_CNDTRx value before starting/enabling a transfer, and after having stopped a circular transfer.

Memory-to-memory mode

The DMA channels may operate without being triggered by a request from a peripheral. This mode is called memory-to-memory mode, and is initiated by software.

If the MEM2MEM bit in the DMA_CCRx register is set, the channel, if enabled, initiates transfers. The transfer stops once the DMA_CNDTRx register reaches zero.

The memory-to-memory mode must not be used in circular mode. Before enabling a channel in memory-to-memory mode (MEM2MEM = 1), the software must clear the CIRC bit of the DMA_CCRx register.

Peripheral-to-peripheral mode

Any DMA channel can operate in peripheral-to-peripheral mode:

 when the hardware request from a peripheral is selected to trigger the DMA channel

This peripheral is the DMA initiator and paces the data transfer from/to this peripheral to/from a register belonging to another memory-mapped peripheral (this one being not configured in DMA mode).

 when no peripheral request is selected and connected to the DMA channel

The software configures a register-to-register transfer by setting the MEM2MEM bit of the DMA_CCRx register.

Programming transfer direction, assigning source/destination

The value of the DIR bit of the DMA_CCRx register sets the direction of the transfer, and consequently, it identifies the source and the destination, regardless the source/destination type (peripheral or memory):

 DIR = 1 defines typically a memory-to-peripheral transfer. More generally, if DIR = 1:

– The source attributes are defined by the DMA_MARx register, the MSIZE[1:0] field and MINC bit of the DMA_CCRx register.

Regardless of their usual naming, these ‘memory’ register, field and bit are used to define the source peripheral in peripheral-to-peripheral mode.

– The destination attributes are defined by the DMA_PARx register, the PSIZE[1:0] field and PINC bit of the DMA_CCRx register.

Regardless of their usual naming, these ‘peripheral’ register, field and bit are used to define the destination memory in memory-to-memory mode.

 DIR = 0 defines typically a peripheral-to-memory transfer. More generally, if DIR = 0:

– The source attributes are defined by the DMA_PARx register, the PSIZE[1:0] field and PINC bit of the DMA_CCRx register.

Regardless of their usual naming, these ‘peripheral’ register, field and bit are used to define the source memory in memory-to-memory mode

– The destination attributes are defined by the DMA_MARx register, the

MSIZE[1:0] field and MINC bit of the DMA_CCRx register.

296/1202 RM0471 Rev 5

RM0471 Direct memory access controller (DMA)

Regardless of their usual naming, these ‘memory’ register, field and bit are used to define the destination peripheral in peripheral-to-peripheral mode.

When PSIZE[1:0] and MSIZE[1:0] are not equal, the DMA controller performs some data alignments as described in the table below.

Table 44. Programmable data width and endian behavior (when PINC = MINC = 1)

Source port width

(MSIZE if

DIR = 1, else

PSIZE)

Destinat ion port width

(PSIZE if

DIR = 1, else

MSIZE)

Number of data items to transfer

(NDT)

Source content: address / data

(DMA_CMARx if

DIR = 1, else

DMA_CPARx)

DMA transfers

Destination content: address / data

(DMA_CPARx if

DIR = 1, else

DMA_CMARx)

@0x0 / B0

@0x1 / B1

@0x2 / B2

@0x3 / B3

@0x0 / B0

@0x1 / B1

@0x2 / B2

@0x3 / B3

@0x0 / B0

@0x1 / B1

@0x2 / B2

@0x3 / B3

@0x0 / B1B0

@0x2 / B3B2

@0x4 / B5B4

@0x6 / B7B6

1: read B0[7:0] @0x0 then write B0[7:0] @0x0

2: read B1[7:0] @0x1 then write B1[7:0] @0x1

3: read B2[7:0] @0x2 then write B2[7:0] @0x2

4: read B3[7:0] @0x3 then write B3[7:0] @0x3

1: read B0[7:0] @0x0 then write 00B0[15:0] @0x0

2: read B1[7:0] @0x1 then write 00B1[15:0] @0x2

3: read B2[7:0] @0x2 then write 00B2[15:0] @0x4

4: read B3[7:0] @0x3 then write 00B3[15:0] @0x6

1: read B0[7:0] @0x0 then write 000000B0[31:0] @0x0

2: read B1[7:0] @0x1 then write 000000B1[31:0] @0x4

3: read B2[7:0] @0x2 then write 000000B2[31:0] @0x8

4: read B3[7:0] @0x3 then write 000000B3[31:0] @0xC

1: read B1B0[15:0] @0x0 then write B0[7:0] @0x0

2: read B3B2[15:0] @0x2 then write B2[7:0] @0x1

3: read B5B4[15:0] @0x4 then write B4[7:0] @0x2

4: read B7B6[15:0] @0x6 then write B6[7:0] @0x3

@0x0 / B0

@0x1 / B1

@0x2 / B2

@0x3 / B3

@0x0 / 00B0

@0x2 / 00B1

@0x4 / 00B2

@0x6 / 00B3

@0x0 / 000000B0

@0x4 / 000000B1

@0x8 / 000000B2

@0xC / 000000B3

@0x0 / B0

@0x1 / B2

@0x2 / B4

@0x3 / B6

@0x0 / B1B0

@0x2 / B3B2

@0x4 / B5B4

@0x6 / B7B6

@0x0 / B1B0

@0x2 / B3B2

@0x4 / B5B4

@0x6 / B7B6

@0x0 / B3B2B1B0

@0x4 / B7B6B5B4

@0x8 / BBBAB9B8

@0xC / BFBEBDBC

@0x0 / B3B2B1B0

@0x4 / B7B6B5B4

@0x8 / BBBAB9B8

@0xC / BFBEBDBC

1: read B1B0[15:0] @0x0 then write B1B0[15:0] @0x0

2: read B3B2[15:0] @0x2 then write B3B2[15:0] @0x2

3: read B5B4[15:0] @0x4 then write B5B4[15:0] @0x4

4: read B7B6[15:0] @0x6 then write B7B6[15:0] @0x6

1: read B1B0[15:0] @0x0 then write 0000B1B0[31:0] @0x0

2: read B3B2[15:0] @0x2 then write 0000B3B2[31:0] @0x4

3: read B5B4[15:0] @0x4 then write 0000B5B4[31:0] @0x8

4: read B7B6[15:0] @0x6 then write 0000B7B6[31:0] @0xC

1: read B3B2B1B0[31:0] @0x0 then write B0[7:0] @0x0

2: read B7B6B5B4[31:0] @0x4 then write B4[7:0] @0x1

3: read BBBAB9B8[31:0] @0x8 then write B8[7:0] @0x2

4: read BFBEBDBC[31:0] @0xC then write BC[7:0] @0x3

1: read B3B2B1B0[31:0] @0x0 then write B1B0[15:0] @0x0

2: read B7B6B5B4[31:0] @0x4 then write B5B4[15:0] @0x2

3: read BBBAB9B8[31:0] @0x8 then write B9B8[15:0] @0x4

4: read BFBEBDBC[31:0] @0xC then write BDBC[15:0] @0x6

@0x0 / B1B0

@0x2 / B3B2

@0x4 / B5B4

@0x6 / B7B6

@0x0 / 0000B1B0

@0x4 / 0000B3B2

@0x8 / 0000B5B4

@0xC / 0000B7B6

@0x0 / B0

@0x1 / B4

@0x2 / B8

@0x3 / BC

@0x0 / B1B0

@0x2 / B5B4

@0x4 / B9B8

@0x6 / BDBC

@0x0 / B3B2B1B0

@0x4 / B7B6B5B4

@0x8 / BBBAB9B8

@0xC / BFBEBDBC

1: read B3B2B1B0[31:0] @0x0 then write B3B2B1B0[31:0] @0x0

2: read B7B6B5B4[31:0] @0x4 then write B7B6B5B4[31:0] @0x4

3: read BBBAB9B8[31:0] @0x8 then write BBBAB9B8[31:0] @0x8

4: read BFBEBDBC[31:0] @0xC then write BFBEBDBC[31:0] @0xC

@0x0 / B3B2B1B0

@0x4 / B7B6B5B4

@0x8 / BBBAB9B8

@0xC / BFBEBDBC

RM0471 Rev 5 297/1202

309

Direct memory access controller (DMA) RM0471

Addressing AHB peripherals not supporting byte/half-word write transfers

When the DMA controller initiates an AHB byte or half-word write transfer, the data are duplicated on the unused lanes of the AHB master 32-bit data bus (HWDATA[31:0]).

When the AHB slave peripheral does not support byte or half-word write transfers and does not generate any error, the DMA controller writes the 32 HWDATA bits as shown in the two examples below:

 To write the half-word 0xABCD, the DMA controller sets the HWDATA bus to

0xABCDABCD with a half-word data size (HSIZE = HalfWord in AHB master bus).

 To write the byte 0xAB, the DMA controller sets the HWDATA bus to 0xABABABAB with a byte data size (HSIZE = Byte in the AHB master bus).

Assuming the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take into account the HSIZE data, any AHB byte or half-word transfer is changed into a 32-bit APB transfer as described below:

 An AHB byte write transfer of 0xB0 to one of the 0x0, 0x1, 0x2 or 0x3 addresses, is converted to an APB word write transfer of 0xB0B0B0B0 to the 0x0 address.

 An AHB half-word write transfer of 0xB1B0 to the 0x0 or 0x2 addresses, is converted to an APB word write transfer of 0xB1B0B1B0 to the 0x0 address.

11.4.7 DMA error management

A DMA transfer error is generated when reading from or writing to a reserved address space. When a DMA transfer error occurs during a DMA read or write access, the faulty channel x is automatically disabled through a hardware clear of its EN bit in the corresponding DMA_CCRx register.

The TEIFx bit of the DMA_ISR register is set. An interrupt is then generated if the TEIE bit of the DMA_CCRx register is set.

The EN bit of the DMA_CCRx register can not be set again by software (channel x reactivated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register).

When the software is notified with a transfer error over a channel which involves a peripheral, the software has first to stop this peripheral in DMA mode, in order to disable any pending or future DMA request. Then software may normally reconfigure both DMA and the peripheral in DMA mode for a new transfer.

298/1202 RM0471 Rev 5

RM0471 Direct memory access controller (DMA)

An interrupt can be generated on a half transfer, transfer complete or transfer error for each

DMA channel x. Separate interrupt enable bits are available for flexibility.

Interrupt request

Table 45. DMA interrupt requests

Interrupt event Event flag

Channel x interrupt

Half transfer on channel x

Transfer complete on channel x

Transfer error on channel x

Half transfer or transfer complete or transfer error on channel x

HTIFx

TCIFx

TEIFx

GIFx

Interrupt enable bit

HTIEx

TCIEx

TEIEx

Refer to Section 1.2

for a list of abbreviations used in register descriptions.

The DMA registers have to be accessed by words (32-bit).

11.6.1 DMA interrupt status register (DMA_ISR)

Address offset: 0x00

Reset value: 0x0000 0000

Every status bit is cleared by hardware when the software sets the corresponding clear bit or the corresponding global clear bit CGIFx, in the DMA_IFCR register.

Res.

28 27 26 25

Res.

TEIF7 HTIF7 TCIF7 r r r

15 14 13 12 11 10 9

TEIF4 HTIF4 TCIF4 GIF4 TEIF3 HTIF3 TCIF3 r r r r r r r

GIF7 r

GIF3 r

23 22 21

TEIF6 HTIF6 TCIF6 r r r

7 6 5

TEIF2 HTIF2 TCIF2 r r r

GIF6 r

GIF2 r

19 18 17

TEIF5 HTIF5 TCIF5 r r r

3 2 1

TEIF1 HTIF1 TCIF1 r r r

GIF5 r

GIF1 r

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 TEIF7 : transfer error (TE) flag for channel 7

0: no TE event

1: a TE event occurred

Bit 26 HTIF7 : half transfer (HT) flag for channel 7

0: no HT event

1: a HT event occurred

Bit 25 TCIF7 : transfer complete (TC) flag for channel 7

0: no TC event

1: a TC event occurred

Bit 24 GIF7 : global interrupt flag for channel 7

0: no TE, HT or TC event

1: a TE, HT or TC event occurred

RM0471 Rev 5 299/1202

309

Direct memory access controller (DMA)

300/1202

Bit 23 TEIF6 : transfer error (TE) flag for channel 6

0: no TE event

1: a TE event occurred

Bit 22 HTIF6 : half transfer (HT) flag for channel 6

0: no HT event

1: a HT event occurred

Bit 21 TCIF6 : transfer complete (TC) flag for channel 6

0: no TC event

1: a TC event occurred

Bit 20 GIF6 : global interrupt flag for channel 6

0: no TE, HT or TC event

1: a TE, HT or TC event occurred

Bit 19 TEIF5 : transfer error (TE) flag for channel 5

0: no TE event

1: a TE event occurred

Bit 18 HTIF5 : half transfer (HT) flag for channel 5

0: no HT event

1: a HT event occurred

Bit 17 TCIF5 : transfer complete (TC) flag for channel 5

0: no TC event

1: a TC event occurred

Bit 16 GIF5 : global interrupt flag for channel 5

0: no TE, HT or TC event

1: a TE, HT or TC event occurred

Bit 15 TEIF4 : transfer error (TE) flag for channel 4

0: no TE event

1: a TE event occurred

Bit 14 HTIF4 : half transfer (HT) flag for channel 4

0: no HT event

1: a HT event occurred

Bit 13 TCIF4 : transfer complete (TC) flag for channel 4

0: no TC event

1: a TC event occurred

Bit 12 GIF4 : global interrupt flag for channel 4

0: no TE, HT or TC event

1: a TE, HT or TC event occurred

Bit 11 TEIF3 : transfer error (TE) flag for channel 3

0: no TE event

1: a TE event occurred

Bit 10 HTIF3 : half transfer (HT) flag for channel 3

0: no HT event

1: a HT event occurred

Bit 9 TCIF3 : transfer complete (TC) flag for channel 3

0: no TC event

1: a TC event occurred

RM0471 Rev 5

RM0471

Bit 8 GIF3 : global interrupt flag for channel 3

0: no TE, HT or TC event

1: a TE, HT or TC event occurred

Bit 7 TEIF2 : transfer error (TE) flag for channel 2

0: no TE event

1: a TE event occurred

Bit 6 HTIF2 : half transfer (HT) flag for channel 2

0: no HT event

1: a HT event occurred

Bit 5 TCIF2 : transfer complete (TC) flag for channel 2

0: no TC event

1: a TC event occurred

Bit 4 GIF2 : global interrupt flag for channel 2

0: no TE, HT or TC event

1: a TE, HT or TC event occurred

Bit 3 TEIF1 : transfer error (TE) flag for channel 1

0: no TE event

1: a TE event occurred

Bit 2 HTIF1 : half transfer (HT) flag for channel 1

0: no HT event

1: a HT event occurred

Bit 1 TCIF1 : transfer complete (TC) flag for channel 1

0: no TC event

1: a TC event occurred

Bit 0 GIF1 : global interrupt flag for channel 1

0: no TE, HT or TC event

1: a TE, HT or TC event occurred

Direct memory access controller (DMA)

RM0471 Rev 5 301/1202

309

Direct memory access controller (DMA) RM0471

11.6.2 DMA interrupt flag clear register (DMA_IFCR)

Address offset: 0x04

Reset value: 0x0000 0000

Setting the global clear bit CGIFx of the channel x in this DMA_IFCR register, causes the

DMA hardware to clear the corresponding GIFx bit and any individual flag among TEIFx,

HTIFx, TCIFx, in the DMA_ISR register.

Setting any individual clear bit among CTEIFx, CHTIFx, CTCIFx in this DMA_IFCR register, causes the DMA hardware to clear the corresponding individual flag and the global flag

GIFx in the DMA_ISR register, provided that none of the two other individual flags is set.

Writing 0 into any flag clear bit has no effect.

Res.

30 29

Res.

27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 w

11 w

10 w

9 w

8 w

7 w

6 w

5 w

4 w

3 w

2 w

1 w

0 w w w w w w w w w w

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 CTEIF7 : transfer error flag clear for channel 7

Bit 26 CHTIF7 : half transfer flag clear for channel 7

Bit 25 CTCIF7 : transfer complete flag clear for channel 7

Bit 24 CGIF7 : global interrupt flag clear for channel 7

Bit 23 CTEIF6 : transfer error flag clear for channel 6

Bit 22 CHTIF6 : half transfer flag clear for channel 6

Bit 21 CTCIF6 : transfer complete flag clear for channel 6

Bit 20 CGIF6 : global interrupt flag clear for channel 6

Bit 19 CTEIF5 : transfer error flag clear for channel 5

Bit 18 CHTIF5 : half transfer flag clear for channel 5

Bit 17 CTCIF5 : transfer complete flag clear for channel 5

Bit 16 CGIF5 : global interrupt flag clear for channel 5

Bit 15 CTEIF4 : transfer error flag clear for channel 4

Bit 14 CHTIF4 : half transfer flag clear for channel 4

Bit 13 CTCIF4 : transfer complete flag clear for channel 4

Bit 12 CGIF4 : global interrupt flag clear for channel 4

Bit 11 CTEIF3 : transfer error flag clear for channel 3

Bit 10 CHTIF3 : half transfer flag clear for channel 3

Bit 9 CTCIF3 : transfer complete flag clear for channel 3 w w w w w w

302/1202 RM0471 Rev 5

RM0471 Direct memory access controller (DMA)

Bit 8 CGIF3 : global interrupt flag clear for channel 3

Bit 7 CTEIF2 : transfer error flag clear for channel 2

Bit 6 CHTIF2 : half transfer flag clear for channel 2

Bit 5 CTCIF2 : transfer complete flag clear for channel 2

Bit 4 CGIF2 : global interrupt flag clear for channel 2

Bit 3 CTEIF1 : transfer error flag clear for channel 1

Bit 2 CHTIF1 : half transfer flag clear for channel 1

Bit 1 CTCIF1 : transfer complete flag clear for channel 1

Bit 0 CGIF1 : global interrupt flag clear for channel 1

11.6.3 DMA channel x configuration register (DMA_CCRx)

Address offset: 0x08 + 0x14 * (x - 1), (x = 1 to 7)

Reset value: 0x0000 0000

The register fields/bits MEM2MEM, PL[1:0], MSIZE[1:0], PSIZE[1:0], MINC, PINC, and DIR are read-only when EN = 1.

The states of MEM2MEM and CIRC bits must not be both high at the same time.

Res.

MEM2

MEM rw

PL[1:0]

12 rw rw

11 10

MSIZE[1:0] rw rw

9 8

PSIZE[1:0] rw rw

MINC rw

PINC rw

CIRC rw

DIR rw

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 MEM2MEM : memory-to-memory mode

0: disabled

1: enabled

Note: this bit is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is read-only when the channel is enabled (EN = 1).

Bits 13:12 PL[1:0] : priority level

00: low

01: medium

10: high

11: very high

Note: this field is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is read-only when the channel is enabled (EN = 1).

TEIE rw

HTIE rw

TCIE rw

EN rw

RM0471 Rev 5 303/1202

309

Direct memory access controller (DMA) RM0471

Bits 11:10 MSIZE[1:0] : memory size

Defines the data size of each DMA transfer to the identified memory.

In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0.

In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0.

00: 8 bits

01: 16 bits

10: 32 bits

11: reserved

Note: this field is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is read-only when the channel is enabled (EN = 1).

Bits 9:8 PSIZE[1:0] : peripheral size

Defines the data size of each DMA transfer to the identified peripheral.

In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0.

In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0.

00: 8 bits

01: 16 bits

10: 32 bits

11: reserved

Note: this field is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is read-only when the channel is enabled (EN = 1).

Bit 7 MINC : memory increment mode

Defines the increment mode for each DMA transfer to the identified memory.

In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0.

In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0.

0: disabled

1: enabled

Note: this bit is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is read-only when the channel is enabled (EN = 1).

Bit 6 PINC : peripheral increment mode

Defines the increment mode for each DMA transfer to the identified peripheral.

n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0.

In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0.

0: disabled

1: enabled

Note: this bit is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is read-only when the channel is enabled (EN = 1).

304/1202 RM0471 Rev 5

RM0471 Direct memory access controller (DMA)

Bit 5 CIRC : circular mode

0: disabled

1: enabled

Note: this bit is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is not read-only when the channel is enabled (EN = 1).

Bit 4 DIR : data transfer direction

This bit must be set only in memory-to-peripheral and peripheral-to-memory modes.

0: read from peripheral

– Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register.

This is still valid in a memory-to-memory mode.

– Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode.

1: read from memory

– Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode.

– Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register.

This is still valid in a peripheral-to-peripheral mode.

Note: this bit is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is read-only when the channel is enabled (EN = 1).

Bit 3 TEIE : transfer error interrupt enable

0: disabled

1: enabled

Note: this bit is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is not read-only when the channel is enabled (EN = 1).

Bit 2 HTIE : half transfer interrupt enable

0: disabled

1: enabled

Note: this bit is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is not read-only when the channel is enabled (EN = 1).

Bit 1 TCIE : transfer complete interrupt enable

0: disabled

1: enabled

Note: this bit is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is not read-only when the channel is enabled (EN = 1).

Bit 0 EN : channel enable

When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register).

0: disabled

1: enabled

Note: this bit is set and cleared by software.

RM0471 Rev 5 305/1202

309

Direct memory access controller (DMA) RM0471

11.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx)

Address offset: 0x0C + 0x14 * (x - 1), (x = 1 to 7)

Reset value: 0x0000 0000

Res.

15 rw

14 13 12 11 10 9 8 7 rw

NDT[15:0] rw

6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 NDT[15:0] : number of data to transfer (0 to 2

- 1)

This field is updated by hardware when the channel is enabled:

– It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer.

– It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register).

– It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1).

If this field is zero, no transfer can be served whatever the channel status (enabled or not).

Note: this field is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is read-only when the channel is enabled (EN = 1).

11.6.5 DMA channel x peripheral address register (DMA_CPARx)

Address offset: 0x10 + 0x14 * (x - 1), (x = 1 to 7)

Reset value: 0x0000 0000

31 30 29 28 27 26 25 22 21 20 19 rw

15 rw rw

14 rw rw

13 rw rw

12 rw rw

11 rw rw

10 rw rw

9 rw

24 23 rw

PA[31:16] rw

8 7

PA[15:0] rw rw rw

6 rw rw

5 rw rw

4 rw rw

3 rw

18 rw

2 rw

17 rw

1 rw

16 rw

0 rw

306/1202 RM0471 Rev 5

RM0471 Direct memory access controller (DMA)

Bits 31:0 PA[31:0] : peripheral address

It contains the base address of the peripheral data register from/to which the data will be read/written.

When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address.

When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address.

In memory-to-memory mode, this register identifies the memory destination address if

DIR = 1 and the memory source address if DIR = 0.

In peripheral-to-peripheral mode, this register identifies the peripheral destination address

DIR = 1 and the peripheral source address if DIR = 0.

Note: this register is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is not read-only when the channel is enabled (EN = 1).

11.6.6 DMA channel x memory address register (DMA_CMARx)

Address offset: 0x14 + 0x14 * (x - 1), (x = 1 to 7)

Reset value: 0x0000 0000

31 rw

15 rw

30 29 rw

14 rw

28 rw

27 rw

26 rw

25 rw

24 23

MA[31:16] rw

8 rw

7 rw

MA[15:0] rw

22 rw

21 rw

20 rw

19 rw

18 rw

17 rw

16 rw

0 rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MA[31:0] : peripheral address

It contains the base address of the memory from/to which the data will be read/written.

When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address.

When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address.

In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0.

In peripheral-to-peripheral mode, this register identifies the peripheral source address

DIR = 1 and the peripheral destination address if DIR = 0.

Note: this register is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is not read-only when the channel is enabled (EN = 1).

Offset

0x000

The table below gives the DMA register map and reset values.

Table 46. DMA register map and reset values

Register

DMA_ISR

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RM0471 Rev 5 307/1202

309

Direct memory access controller (DMA) RM0471

Table 46. DMA register map and reset values (continued)

Offset Register

0x004

DMA_IFCR

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x008

DMA_CCR1

0x00C

0x010

0x014

0x018

Reset value

DMA_CNDTR1

Reset value

DMA_CPAR1

Reset value

DMA_CMAR1

Reset value

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NDTR[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved.

0x01C

DMA_CCR2

0x020

0x024

0x028

0x02C

Reset value

DMA_CNDTR2

Reset value

DMA_CPAR2

Reset value

DMA_CMAR2

Reset value

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NDTR[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved.

0x030

DMA_CCR3

0x034

0x038

0x03C

0x040

Reset value

DMA_CNDTR3

Reset value

DMA_CPAR3

Reset value

DMA_CMAR3

Reset value

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NDTR[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved.

DMA_CCR4

0x044

0x048

0x04C

0x050

0x054

Reset value

DMA_CNDTR4

Reset value

DMA_CPAR4

Reset value

DMA_CMAR4

Reset value

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NDTR[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved.

308/1202 RM0471 Rev 5

RM0471 Direct memory access controller (DMA)

Table 46. DMA register map and reset values (continued)

Offset Register

0x058

DMA_CCR5

0x05C

0x060

0x064

0x068

Reset value

DMA_CNDTR5

Reset value

DMA_CPAR5

Reset value

DMA_CMAR5

Reset value

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NDTR[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved.

0x06C

DMA_CCR6

0x070

0x074

0x078

0x07C

Reset value

DMA_CNDTR6

Reset value

DMA_CPAR6

Reset value

DMA_CMAR6

Reset value

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NDTR[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved.

0x080

DMA_CCR7

0x084

0x088

0x08C

Reset value

DMA_CNDTR7

Reset value

DMA_CPAR7

Reset value

DMA_CMAR7

Reset value

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NDTR[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2

for the register boundary addresses.

RM0471 Rev 5 309/1202

309

DMA request multiplexer (DMAMUX)

12 DMA request multiplexer (DMAMUX)

RM0471

12.1 Introduction

A peripheral indicates a request for DMA transfer by setting its DMA request signal. The

DMA request is pending until it is served by the DMA controller that generates a DMA acknowledge signal, and the corresponding DMA request signal is deasserted.

In this document, the set of control signals required for the DMA request/acknowledge protocol is not explicitly shown or described, and it is referred to as DMA request line.

The DMAMUX request multiplexer enables routing a DMA request line between the peripherals and the DMA controller of the product. The routing function is ensured by a programmable multi-channel DMA request line multiplexer. Each channel selects a unique

DMA request line, unconditionally or synchronously with events from its DMAMUX synchronization inputs. The DMAMUX may also be used as a DMA request generator from programmable events on its input trigger signals.

The number of DMAMUX instances and their main characteristics are specified in

Section 12.3.1

The assignment of DMAMUX request multiplexer inputs to the DMA request lines from peripherals and to the DMAMUX request generator outputs, the assignment of DMAMUX request multiplexer outputs to DMA controller channels, and the assignment of DMAMUX synchronizations and trigger inputs to internal and external signals depend on the product

implementation, and are detailed in Section 12.3.2

310/1202 RM0471 Rev 5

RM0471 DMA request multiplexer (DMAMUX)

12.2 DMAMUX main features

 7-channel programmable DMA request line multiplexer output

 4-channel DMA request generator

 20 trigger inputs to DMA request generator

 20 synchronization inputs

 Per DMA request generator channel:

– DMA request trigger input selector

– DMA request counter

– Event overrun flag for selected DMA request trigger input

 Per DMA request line multiplexer channel output:

– 36 input DMA request lines from peripherals

– One DMA request line output

– Synchronization input selector

– DMA request counter

– Event overrun flag for selected synchronization input

– One event output, for DMA request chaining

DMAMUX is instantiated with the hardware configuration parameters listed in the following table.

Table 47. DMAMUX instantiation

Feature

Number of DMAMUX output request channels

Number of DMAMUX request generator channels

Number of DMAMUX request trigger inputs

Number of DMAMUX synchronization inputs

Number of DMAMUX peripheral request inputs

DMAMUX

The mapping of resources to DMAMUX is hardwired.

DMAMUX is used with DMA1

 DMAMUX channels 0 to 6 are connected to DMA1 channels 1 to 7

RM0471 Rev 5 311/1202

325

DMA request multiplexer (DMAMUX) RM0471

Table 48. DMAMUX: assignment of multiplexer inputs to resources

DMA request

MUX input

Resource

DMA request

MUX input

Resource

DMA request

MUX input

Resource

21 dmamux_req_gen0 dmamux_req_gen1 dmamux_req_gen2 dmamux_req_gen3

ADC1

SPI1_RX

SPI1_TX

Reserved

I2C1_RX

I2C1_TX

Reserved

USART1_RX

USART1_TX

Reserved

TIM1_CH1

TIM1_CH2

TIM1_CH3

TIM1_CH4

TIM1_UP

TIM1_TRIG

TIM1_COM

TIM2_CH1

TIM2_CH2

TIM2_CH3

TIM2_CH4

TIM2_UP

TIM16_CH1

TIM16_UP

TIM17_CH1

TIM17_UP

Reserved

AES2_IN

AES2_OUT

Reserved

Table 49. DMAMUX: assignment of trigger inputs to resources

Trigger input Resource Trigger input Resource

EXTI LINE0

EXTI LINE1

EXTI LINE2

EXTI LINE3

EXTI LINE4

EXTI LINE5

EXTI LINE6

EXTI LINE7

EXTI LINE8

EXTI LINE9

EXTI LINE10

26 dmamux_evt0 dmamux_evt1

LPTIM1_OUT

LPTIM2_OUT

Reserved

312/1202 RM0471 Rev 5

RM0471 DMA request multiplexer (DMAMUX)

Table 49. DMAMUX: assignment of trigger inputs to resources (continued)

Trigger input Resource Trigger input Resource

EXTI LINE11

EXTI LINE12

EXTI LINE13

EXTI LINE14

EXTI LINE15

Reserved

Table 50. DMAMUX: assignment of synchronization inputs to resources

Sync. input Resource Sync. input Resource

EXTI LINE0

EXTI LINE1

EXTI LINE2

EXTI LINE3

EXTI LINE4

EXTI LINE5

EXTI LINE6

EXTI LINE7

EXTI LINE8

EXTI LINE9

EXTI LINE10

EXTI LINE11

EXTI LINE12

EXTI LINE13

EXTI LINE14

EXTI LINE15

22 dmamux_evt0 dmamux_evt1

LPTIM1_OUT

LPTIM2_OUT

Reserved

RM0471 Rev 5 313/1202

325

DMA request multiplexer (DMAMUX)

12.4 DMAMUX functional description

RM0471

Figure 25

shows the DMAMUX block diagram.

DMA requests from peripherals: dmamux_req_inx

Figure 25. DMAMUX block diagram

32-bit AHB bus dmamux_hclk

DMAMUX

AHB slave interface dmamux_reqx

Request multiplexer

Channel m

DMAMUX_CmCR

Channel 1

Channel 0

DMAMUX_C0CR n+p+2

Channel select

Ctrl

Request generator

Channel n

DMAMUX_RGCnCR n

Channel 1

DMAMUX_RGC1CR

Channel 0

DMAMUX_RGC0CR

0 n+3 n+2 n+1

1 s

Sync

1 0 m

0 m

DMA requests to DMA controller: dmamux_req_outx

DMA channels events: dmamux_evtx

Interrupt interface t 1 0 s 1 0

Control registers Trigger inputs: dmamux_trgx dmamux_ovr_it

Synchronization inputs: dmamux_syncx

MS52648V1

DMAMUX features two main sub-blocks: the request line multiplexer and the request line generator.

The implementation assigns:

 DMAMUX request multiplexer sub-block inputs (dmamux_reqx) from peripherals

(dmamux_req_inx) and from channels of the DMAMUX request generator sub-block

(dmamux_req_genx)

 DMAMUX request outputs to channels of DMA controllers (dmamux_req_outx)

 Internal or external signals to DMA request trigger inputs (dmamux_trgx)

 Internal or external signals to synchronization inputs (dmamux_syncx)

314/1202 RM0471 Rev 5

RM0471 DMA request multiplexer (DMAMUX)

Table 51 lists the DMAMUX signals.

Signal name dmamux_hclk dmamux_req_inx dmamux_trgx dmamux_req_genx dmamux_reqx dmamux_syncx dmamux_req_outx dmamux_evtx dmamux_ovr_it

Table 51. DMAMUX signals

Description

DMAMUX AHB clock

DMAMUX DMA request line inputs from peripherals

DMAMUX DMA request triggers inputs (to request generator sub-block)

DMAMUX request generator sub-block channels outputs

DMAMUX request multiplexer sub-block inputs (from peripheral requests and request generator channels)

DMAMUX synchronization inputs (to request multiplexer sub-block)

DMAMUX requests outputs (to DMA controller)

DMAMUX events outputs

DMAMUX overrun interrupts

A DMAMUX channel is a DMAMUX request multiplexer channel that may include, depending on the selected input of the request multiplexer, an additional DMAMUX request generator channel.

A DMAMUX request multiplexer channel is connected and dedicated to one single channel of DMA controller.

Channel configuration procedure

Follow the sequence below to configure both a DMAMUX x channel and the related DMA channel y:

Set and configure completely the DMA channel y, except enabling the channel y.

2. Set and configure completely the related DMAMUX y channel.

3. Last, activate the DMA channel y by setting the EN bit in the DMA y channel register.

12.4.4 DMAMUX request line multiplexer

Note:

The DMAMUX request multiplexer with its multiple channels ensures the actual routing of

DMA request/acknowledge control signals, named DMA request lines.

Each DMA request line is connected in parallel to all the channels of the DMAMUX request line multiplexer.

A DMA request is sourced either from the peripherals or from the DMAMUX request generator.

The DMAMUX request line multiplexer channel x selects the DMA request line number as configured by the DMAREQ_ID field in the DMAMUX_CxCR register.

The null value in the field DMAREQ_ID corresponds to no DMA request line selected.

RM0471 Rev 5 315/1202

325

DMA request multiplexer (DMAMUX) RM0471

Caution: A same non-null DMAREQ_ID must not be programmed to different x and y DMAMUX request multiplexer channels (via DMAMUX_CxCR and DMAMUX_CyCR), except if application guarantees that the two connected DMA channels are not simultaneously active.

On top of the DMA request selection, the synchronization mode and/or the event generation may be configured and enabled, if required.

Note:

Synchronization mode and channel event generation

Each DMAMUX request line multiplexer channel x can be individually synchronized by setting the synchronization enable (SE) bit in the DMAMUX_CxCR register.

DMAMUX has multiple synchronization inputs. The synchronization inputs are connected in parallel to all the channels of the request multiplexer.

The synchronization input is selected via the SYNC_ID field in the DMAMUX_CxCR register of a given channel x.

When a channel is in this synchronization mode, the selected input DMA request line is propagated to the multiplexer channel output, once is detected a programmable rising/falling edge on the selected input synchronization signal, via the SPOL[1:0] field of the

DMAMUX_CxCR register.

Additionally, there is a programmable DMA request counter, internally to the DMAMUX request multiplexer, which may be used for the channel request output generation and also possibly for an event generation. An event generation on the channel x output is enabled through the EGE bit (event generation enable) of the DMAMUX_CxCR register.

As shown in

Figure 27

, upon the detected edge of the synchronization input, the pending selected input DMA request line is connected to the DMAMUX multiplexer channel x output.

If a synchronization event occurs while there is no pending selected input DMA request line, it is discarded. The following asserted input request lines is not connected to the DMAMUX multiplexer channel output until a synchronization event occurs again.

From this point on, each time the connected DMAMUX request is served by the DMA controller (a served request is deasserted), the DMAMUX request counter is decremented.

At its underrun, the DMA request counter is automatically loaded with the value in NBREQ field of the DMAMUX_CxCR register and the input DMA request line is disconnected from the multiplexer channel x output.

Thus, the number of DMA requests transferred to the multiplexer channel x output following a detected synchronization event, is equal to the value in NBREQ field, plus one.

The NBREQ field value shall only be written by software when both synchronization enable bit SE and event generation enable EGE bit of the corresponding multiplexer channel x are disabled.

316/1202 RM0471 Rev 5

RM0471 DMA request multiplexer (DMAMUX)

Figure 26. Synchronization mode of the DMAMUX request line multiplexer channel

Selected DMA request line transferred to the output

DMA requests served

DMA request pending

Selected dmamux_reqx

Not pending dmamux_syncx dmamux_req_outx

DMA request counter 4 3 2 1 0 4 dmamux_evtx

Synchronization event

Input DMA request line connected to output

DMA request counter underrun

DMA request counter auto-reload to NBREQ

Input DMA request line disconnected from output

Example: DMAMUX_CCRx configured with: NBREQ=4, SE=1, EGE=1, SPOL=01 (rising edge)

MSv41974V1

Figure 27. Event generation of the DMA request line multiplexer channel

Selected DMA request line transferred to the output

DMA request pending

Selected dmamux_reqx

Not pending dmamux_req_outx

DMA request counter

3 2 1 0 3 2 1 0 3 2 1 0

EGE dmamux_evtx

DMA request counter reaches zero

Event is generated on the output

DMA request counter auto-reloads with NBREQ value

Example with: DMAMUX_CCRx configured with: NBREQ=3, SE=0, EGE=1

MSv41975V1

If EGE is enabled, the multiplexer channel generates a channel event, as a pulse of one

AHB clock cycle, when its DMA request counter is automatically reloaded with the value of the programmed NBREQ field, as shown in

Figure 26 and Figure 27 .

RM0471 Rev 5 317/1202

325

DMA request multiplexer (DMAMUX)

Note:

RM0471

If EGE is enabled and NBREQ = 0, an event is generated after each served DMA request.

A synchronization event (edge) is detected if the state following the edge remains stable for more than two AHB clock cycles.

Upon writing into DMAMUX_CxCR register, the synchronization events are masked during three AHB clock cycles.

Synchronization overrun and interrupt

If a new synchronization event occurs before the request counter underrun (the internal request counter programmed via the NBREQ field of the DMAMUX_CxCR register), the synchronization overrun flag bit SOFx is set in the DMAMUX_CSR status register.

The request multiplexer channel x synchronization must be disabled

(DMAMUX_CxCR.SE = 0) at the completion of the use of the related channel of the DMA controller. Else, upon a new detected synchronization event, there is a synchronization overrun due to the absence of a DMA acknowledge (that is, no served request) received from the DMA controller.

The overrun flag SOFx is reset by setting the associated clear synchronization overrun flag bit CSOFx in the DMAMUX_CFR register.

Setting the synchronization overrun flag generates an interrupt if the synchronization overrun interrupt enable bit SOIE is set in the DMAMUX_CxCR register.

The DMAMUX request generator produces DMA requests following trigger events on its

DMA request trigger inputs.

The DMAMUX request generator has multiple channels. DMA request trigger inputs are connected in parallel to all channels.

The outputs of DMAMUX request generator channels are inputs to the DMAMUX request line multiplexer.

Each DMAMUX request generator channel x has an enable bit GE (generator enable) in the corresponding DMAMUX_RGxCR register.

The DMA request trigger input for the DMAMUX request generator channel x is selected through the SIG_ID (trigger signal ID) field in the corresponding DMAMUX_RGxCR register.

Trigger events on a DMA request trigger input can be rising edge, falling edge or either edge. The active edge is selected through the GPOL (generator polarity) field in the corresponding DMAMUX_RGxCR register.

Upon the trigger event, the corresponding generator channel starts generating DMA requests on its output. Each time the DMAMUX generated request is served by the connected DMA controller (a served request is deasserted), a built-in (inside the DMAMUX request generator) DMA request counter is decremented. At its underrun, the request generator channel stops generating DMA requests and the DMA request counter is automatically reloaded to its programmed value upon the next trigger event.

Thus, the number of DMA requests generated after the trigger event is GNBREQ + 1.

318/1202 RM0471 Rev 5

RM0471

Note:

DMA request multiplexer (DMAMUX)

The GNBREQ field value must be written by software only when the enable GE bit of the corresponding generator channel x is disabled.

There is no hardware write protection.

A trigger event (edge) is detected if the state following the edge remains stable for more than two AHB clock cycles.

Upon writing into DMAMUX_RGxCR register, the trigger events are masked during three

AHB clock cycles.

Trigger overrun and interrupt

If a new DMA request trigger event occurs before the DMAMUX request generator counter underrun (the internal counter programmed via the GNBREQ field of the DMAMUX_RGxCR register), and if the request generator channel x was enabled via GE, then the request trigger event overrun flag bit OFx is asserted by the hardware in the status

DMAMUX_RGSR register.

The request generator channel x must be disabled (DMAMUX_RGxCR.GE = 0) at the completion of the usage of the related channel of the DMA controller. Else, upon a new detected trigger event, there is a trigger overrun due to the absence of an acknowledge (that is, no served request) received from the DMA.

The overrun flag OFx is reset by setting the associated clear overrun flag bit COFx in the

DMAMUX_RGCFR register.

Setting the DMAMUX request trigger overrun flag generates an interrupt if the DMA request trigger event overrun interrupt enable bit OIE is set in the DMAMUX_RGxCR register.

An interrupt can be generated upon:

 a synchronization event overrun in each DMA request line multiplexer channel

 a trigger event overrun in each DMA request generator channel

For each case, per-channel individual interrupt enable, status and clear flag register bits are available.

Interrupt signal dmamuxovr_it

Table 52. DMAMUX interrupts

Interrupt event Event flag Clear bit

Synchronization event overrun on channel x of the

DMAMUX request line multiplexer

Trigger event overrun on channel x of the

DMAMUX request generator

SOFx

OFx

CSOFx

COFx

Enable bit

SOIE

OIE

RM0471 Rev 5 319/1202

325

DMA request multiplexer (DMAMUX) RM0471

Refer to the table containing register boundary addresses for the DMAMUX base address.

DMAMUX registers may be accessed per (8-bit) byte, (16-bit) half-word, or (32-bit) word.

The address must be aligned with the data size.

12.6.1 DMAMUX request line multiplexer channel x configuration register

(DMAMUX_CxCR)

Address offset: 0x000 + 0x04 * x (x = 0 to 6)

Reset value: 0x0000 0000

Res.

28 rw

Res.

27 26 25 rw

SYNC_ID[4:0] rw rw

Res.

EGE rw

24 rw

SOIE rw

23 rw

Res.

22 rw

Res.

NBREQ[4:0] rw

5 rw

20 rw

4 rw

19 rw

DMAREQ_ID[5:0]

SPOL[1:0] rw rw

1 rw rw rw

SE rw

0 rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SYNC_ID[4:0] : Synchronization identification

Selects the synchronization input (see Table 50: DMAMUX: assignment of synchronization inputs to resources

Bits 23:19 NBREQ[4:0] : Number of DMA requests minus 1 to forward

Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated.

This field shall only be written when both SE and EGE bits are low.

Bits 18:17 SPOL[1:0] : Synchronization polarity

Defines the edge polarity of the selected synchronization input:

00: No event, i.e. no synchronization nor detection.

01: Rising edge

10: Falling edge

11: Rising and falling edges

Bit 16 SE : Synchronization enable

0: Synchronization disabled

1: Synchronization enabled

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 EGE : Event generation enable

0: Event generation disabled

1: Event generation enabled

Bit 8 SOIE : Synchronization overrun interrupt enable

0: Interrupt disabled

1: Interrupt enabled

320/1202 RM0471 Rev 5

RM0471 DMA request multiplexer (DMAMUX)

Bits 76 Reserved, must be kept at reset value.

Bits 5:0 DMAREQ_ID[5:0] : DMA request identification

Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.

12.6.2 DMAMUX request line multiplexer interrupt channel status register

(DMAMUX_CSR)

Address offset: 0x080

Reset value: 0x0000 0000

Res.

6 5 4 3 2 1 0

SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 r r r r r r r

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:0 SOF[6:0] : Synchronization overrun event flag

The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ.

The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.

12.6.3 DMAMUX request line multiplexer interrupt clear flag register

(DMAMUX_CFR)

Address offset: 0x084

Reset value: 0x0000 0000

Res.

CSOF

6 w

CSOF

5 w

CSOF

4 w

CSOF

3 w

CSOF

2 w

CSOF

1 w

CSOF

0 w

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:0 CSOF[6:0] : Clear synchronization overrun event flag

Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.

RM0471 Rev 5 321/1202

325

DMA request multiplexer (DMAMUX) RM0471

Res.

(DMAMUX_RGxCR)

Address offset: 0x100 + 0x04 * x (x = 0 to 3)

Reset value: 0x0000 0000

Res.

OIE rw

23 rw

Res.

22 21

GNBREQ[4:0]

20 rw

Res.

4 rw

19 rw

3 rw

18 17

GPOL[1:0] rw

2 rw

SIG_ID[4:0] rw rw

GE rw

0 rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:19 GNBREQ[4:0] : Number of DMA requests to be generated (minus 1)

Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1.

Note: This field must be written only when GE bit is disabled.

Bits 18:17 GPOL[1:0] : DMA request generator trigger polarity

Defines the edge polarity of the selected trigger input

00: No event, i.e. no trigger detection nor generation.

01: Rising edge

10: Falling edge

11: Rising and falling edges

Bit 16 GE : DMA request generator channel x enable

0: DMA request generator channel x disabled

1: DMA request generator channel x enabled

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 OIE : Trigger overrun interrupt enable

0: Interrupt on a trigger overrun event occurrence is disabled

1: Interrupt on a trigger overrun event occurrence is enabled

Bits 7:5 Reserved, must be kept at reset value.

Bits 4:0 SIG_ID[:0] : Signal identification

Selects the DMA request trigger input used for the channel x of the DMA request generator

322/1202 RM0471 Rev 5

RM0471 DMA request multiplexer (DMAMUX)

Res.

(DMAMUX_RGSR)

Address offset: 0x140

Reset value: 0x0000 0000

Res.

OF3 r

OF2 r

OF1 r

OF0 r

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 OF[3:0] : Trigger overrun event flag

The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register).

The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register.

Res.

(DMAMUX_RGCFR)

Address offset: 0x144

Reset value: 0x0000 0000

Res.

3 2 1 0

COF3 COF2 COF1 COF0 w w w w

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 COF[3:0] : Clear trigger overrun event flag

Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register.

RM0471 Rev 5 323/1202

325

DMA request multiplexer (DMAMUX) RM0471

The following table summarizes the DMAMUX registers and reset values. Refer to the register boundary address table for the DMAMUX register base address.

Table 53. DMAMUX register map and reset values

Register Offset

0x000

0x004

0x008

0x00C

0x010

0x014

0x018

0x01C -

0x07C

0x080

0x084

DMAMUX_C0CR

Reset value

DMAMUX_C1CR

Reset value

DMAMUX_C2CR

Reset value

DMAMUX_C3CR

Reset value

DMAMUX_C4CR

Reset value

DMAMUX_C5CR

Reset value

DMAMUX_C6CR

Reset value

Reserved

DMAMUX_CSR

Reset value

DMAMUX_CFR

Reset value

Reserved

0x088 -

0x0FC

0x100

0x104

0x108

0x10C

0x110 -

0x13C

0x140

DMAMUX_RG0CR

Reset value

DMAMUX_RG1CR

Reset value

DMAMUX_RG2CR

Reset value

DMAMUX_RG3CR

Reset value

Reserved

DMAMUX_RGSR

Reset value

SYNC_ID[4:0] NBREQ[4:0]

0 0 0 0 0 0 0 0 0 0 0 0 0

SYNC_ID[4:0] NBREQ[4:0]

0 0 0 0 0 0 0 0 0 0 0 0 0

SYNC_ID[4:0] NBREQ[4:0]

0 0 0 0 0 0 0 0 0 0 0 0 0

SYNC_ID[4:0] NBREQ[4:0]

0 0 0 0 0 0 0 0 0 0 0 0 0

SYNC_ID[4:0] NBREQ[4:0]

0 0 0 0 0 0 0 0 0 0 0 0 0

SYNC_ID[4:0] NBREQ[4:0]

0 0 0 0 0 0 0 0 0 0 0 0 0

SYNC_ID[4:0] NBREQ[4:0]

0 0 0 0 0 0 0 0 0 0 0 0 0

GNBREQ[4:0]

0 0 0 0 0 0 0 0

GNBREQ[4:0]

0 0 0 0 0 0 0 0

GNBREQ[4:0]

0 0 0 0 0 0 0 0

GNBREQ[4:0]

0 0 0 0 0 0 0 0

0 0

0 0 0 0 0 0 0

SIG_ID[4:0]

0 0 0 0 0

SIG_ID[4:0]

0 0 0 0 0

SIG_ID[4:0]

0 0 0 0 0

SIG_ID[4:0]

0 0 0 0 0

0 0 0 0

DMAREQ_ID[5:0]

0 0 0 0 0 0

DMAREQ_ID[5:0]

0 0 0 0 0 0

DMAREQ_ID[5:0]

0 0 0 0 0 0

DMAREQ_ID[5:0]

0 0 0 0 0 0

DMAREQ_ID[5:0]

0 0 0 0 0 0

DMAREQ_ID[5:0]

0 0 0 0 0 0

DMAREQ_ID[5:0]

0 0 0 0 0 0

324/1202 RM0471 Rev 5

RM0471 DMA request multiplexer (DMAMUX)

Register

Table 53. DMAMUX register map and reset values (continued)

Offset

0x144

0x148 -

0x3FC

DMAMUX_RGCFR

Reset value

Reserved

Refer to Section 2.2 on page 55 for the register boundary addresses.

0 0 0 0

RM0471 Rev 5 325/1202

325

Nested vectored interrupt controller (NVIC)

13 Nested vectored interrupt controller (NVIC)

RM0471

13.1 NVIC main features

The CPU1 NVIC features:

 63 maskable interrupt channels (not including the sixteen Cortex ® -M4 with FPU interrupt lines)

 16 programmable priority levels (four bits of interrupt priority are used)

 Low-latency exception interrupt handling

 Power management control

 Implementation of System control registers

The CPU2 NVIC features:

 32 maskable interrupt channels (not including the sixteen Cortex

-M0+ interrupt lines)

 Four programmable priority levels (two bits of interrupt priority are used)

 Low-latency exception interrupt handling

 Power management control

The NVICs and the processor cores interfaces are closely coupled, resulting in low latency interrupt processing and efficient processing of late arriving interrupts.

All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to the PM0214 programming manual for Cortex ® -M4, and

PM0223 programming manual for Cortex ® -M0+.

The different peripheral interrupts are connected in different ways, depending on the sharing between the two CPUs. To prevent a peripheral or EXTI interrupt to trigger both CPUs, they can be masked either in the NVIC, or, for the NVIC vector sharing multiple peripheral interrupts, by a pre-mask in the SYSCFG

registers, see Section 9: System configuration controller (SYSCFG)

The interrupt block diagram is shown in

Figure 28

326/1202 RM0471 Rev 5

RM0471

Peripheral

interrupt

Peripheral

interrupt

EXTI

interrupt interrupt

Peripheral

interrupt

Peripheral

interrupt

Peripheral

interrupt

Nested vectored interrupt controller (NVIC)

Figure 28. Interrupt block diagram

CPU1

SYSCFG

C1IMRn

C2IMRn

NVIC

CPU2

NVIC

MS45410V2

Each of the CPU1 and CPU2 has its own vector table, see, respectively, Table 54

and

Table 55 , where

shaded cells indicate the processor exceptions.

RM0471 Rev 5 327/1202

334

Nested vectored interrupt controller (NVIC) RM0471

Table 54. CPU1 vector table

Type of priority

Acronym Description Address

-3

-2

-1

Fixed

Reset

NMI

HardFault

Settable MemManager

Settable BusFault

Settable UsageFault

Reserved

Reset

Non maskable interrupt HSE CSS, Flash ECC, and

SRAM2 parity

All classes of fault

Memory manager

Pre-fetch fault, memory access fault

Undefined instruction or illegal state

Reserved

3 Settable SVCall

4 Settable Debug

5 Settable PendSV

6 Settable Systick

System service can via SWI instruction

Debug monitor

Reserved

Pendable request for system service

System tick timer

0 7 Settable WWDG

1 8 Settable PVD

2 9 Settable

TAMP, RTC_STAMP,

LSE_CSS

3 10 Settable RTC_WKUP

4 11 Settable Flash

5 12 Settable RCC

6 13 Settable EXTI0

Window watchdog early wakeup

PVD through EXTI[16] (C1IMR2[20])

Tamper, TimeStamp, LSECSS interrupt through

EXTI[18]

RTC wakeup interrupt through EXTI[19]

Flash memory global interrupt and Flash memory ECC single error interrupt

RCC global interrupt

7 14 Settable EXTI1

8 15 Settable EXTI2

9 16 Settable EXTI3

10 17 Settable EXTI4

11 18 Settable DMA1_CH1

EXTI Line 0 interrupt through EXTI[0]

EXTI Line 1 interrupt through EXTI[1]

EXTI Line 2 interrupt through EXTI[2]

EXTI Line 3 interrupt through EXTI[3]

EXTI Line 4 interrupt through EXTI[4]

DMA1 channel 1 interrupt

12 19 Settable DMA1_CH2

13 20 Settable DMA1_CH3

14 21 Settable DMA1_CH4

15 22 Settable DMA1_CH5

16 23 Settable DMA1_CH6

17 24 Settable DMA1_CH7

DMA1 channel 2 interrupt

DMA1 channel 3 interrupt

DMA1 channel 4 interrupt

DMA1 channel 5 interrupt

DMA1 channel 6 interrupt

DMA1 channel 7 interrupt

0x0000 0000

0x0000 0004

0x0000 0008

0x0000 000C

0x0000 0010

0x0000 0014

0x0000 0018

0x0000 001C

0x0000 0028

0x0000 002C

0x0000 0030

0x0000 0034

0x0000 0038

0x0000 003C

0x0000 0040

0x0000 0044

0x0000 0048

0x0000 004C

0x0000 0050

0x0000 0054

0x0000 0058

0x0000 005C

0x0000 0060

0x0000 0064

0x0000 0068

0x0000 006C

0x0000 0070

0x0000 0074

0x0000 0078

0x0000 007C

0x0000 0080

0x0000 0084

328/1202 RM0471 Rev 5

RM0471 Nested vectored interrupt controller (NVIC)

Table 54. CPU1 vector table (continued)

Type of priority

Acronym

18 25 Settable ADC1

19 26

20 27

21 28 Settable

22 29 -

C2SEV

PWR_C2H

23 30 Settable EXTI[9:5]

24 31 Settable TIM1_BRK

25 32 Settable

TIM1_UP,

TIM16

26 33 Settable

TIM1_TRG_COM,

TIM17

27 34 Settable TIM1_CC

28 35 Settable TIM2

29 36 Settable PKA

30 37 Settable I2C1_EV

31 38 Settable I2C1_ER

32 39 -

33 40 -

34 41 Settable SPI1

35 42 -

36 43 Settable USART1

37 44 -

38 45

39 46

40 47 Settable EXTI[15:10]

41 48 Settable RTC_ALARM

42 49 -

43 50 Settable

PWR_SOTF

PWR_BLEACT

PWR_802ACT

PWR_RFPHASE

44 51 Settable IPCC_C1_RX_IT

Description

ADC1 global interrupt

Reserved

CPU2 SEV through EXTI[40]

PWR CPU2 HOLD wakeup interrupt

Reserved

EXTI Line [9:5] interrupt through EXTI[9:5]

(C1IMR1[25:21])

Timer 1 break interrupt

Timer 1 Update (C1IMR1[13])

Timer 16 global interrupt (C1IMR1[14])

Timer 1 trigger and communication (C1IMR1[13])

Timer 17 global interrupt (C1IMR1[15])

Timer 1 capture compare interrupt

Timer 2 global interrupt

Private key accelerator interrupt

I2C1 event interrupt

I2C1 error interrupt

Reserved

SPI 1 global interrupt

Reserved

USART1 global interrupt

Reserved

EXTI Line [15:10] interrupt through EXTI[15:10]

(C1IMR1[31:26])

RTC alarms (A and B) interrupt through EXTI[17]

Reserved

PWR switching on the fly interrupt

PWR end of BLE activity interrupt

PWR end of 802.15.4 activity interrupt

PWR end of critical radio phase interrupt

IPCC CPU1 RX occupied interrupt

Address

0x0000 00EC

0x0000 00F0

0x0000 0088

0x0000 008C

0x0000 0090

0x0000 0094

0x0000 0098

0x0000 009C

0x0000 00A0

0x0000 00A4

0x0000 00A8

0x0000 00AC

0x0000 00B0

0x0000 00B4

0x0000 00B8

0x0000 00BC

0x0000 00C0

0x0000 00C4

0x0000 00C8

0x0000 00CC

0x0000 00D0

0x0000 00D4

0x0000 00D8

0x0000 00DC

0x0000 00E0

0x0000 00E4

0x0000 00E8

RM0471 Rev 5 329/1202

334

Nested vectored interrupt controller (NVIC)

Table 54. CPU1 vector table (continued)

Type of priority

Acronym

45 52 Settable IPCC_C1_TX_IT

46 53 Settable HSEM

47 54 Settable LPTIM1

48 55 Settable LPTIM2

49 56

50 57

51 58

52 59 Settable AES2

53 60 Settable True RNG

54 61 Settable FPU

55 62

56 63

57 64

58 65

59 66

60 67

61 68 -

62 69 Settable DMAMUX1_OVR

Description

IPCC CPU1 TX free interrupt

Semaphore interrupt 0 to CPU1

LPtimer 1 global interrupt

LPtimer 2 global interrupt

Reserved

AES2 global interrupt

True random number generator interrupt

Floating point unit interrupt

Reserved

DMAMUX1 overrun interrupt

RM0471

Address

0x0000 00F4

0x0000 00F8

0x0000 00FC

0x0000 0100

0x0000 0104

0x0000 0108

0x0000 010C

0x0000 0110

0x0000 0114

0x0000 0118

0x0000 011C

0x0000 0120

0x0000 0124

0x0000 0128

0x0000 012C

0x0000 0130

0x0000 0134

0x0000 0138

330/1202 RM0471 Rev 5

RM0471 Nested vectored interrupt controller (NVIC)

Table 55. CPU2 vector table

Type of priority

Acronym Description Address

-3

-14 -2

-13 -1

-5

Fixed

Reset

-2 1 Settable PendSV

-1 2 Settable Systick

0 3 Settable -

1 4 Settable PVD

2 5 Settable

RTC_WKUP, TAMP,

RTC_STAMP

LSE_CSS,

RTC_ALARM

Fixed

NMI

HardFault

0 Settable SVCall

6 -

4 7 Settable

RCC

FLASH

C1SEV

8 Settable EXTI[1:0]

9 Settable EXTI[3:2]

10 Settable EXTI[15:4]

11 Settable 802_IT0

12 Settable DMA1_CH[3:1]

10 13 Settable DMA1_CH[7:4]

11 14 Settable DMAMUX1_OVR

12 15 Settable ADC1

13 16 Settable LPTIM1

14 17 Settable LPTIM2

Reserved

Reset

Non maskable interrupt HSE CSS, Flash ECC, and

SRAM2 parity

All classes of fault

0x0000 0000

0x0000 0004

0x0000 0008

Reserved

System service can via SWI instruction

Reserved

Pendable request for system service

System tick timer

Reserved

PVD through EXTI[16] (C2IMR2[20])

RTC wakeup interrupt through EXTI[19] (C2IMR1[3])

Tamper, TimeStamp

LSECSS interrupt through EXTI[18] (C2IMR1[0])

RTC Alarms (A and B) interrupt through EXTI[17]

(C2IMR1[4])

Reserved

RCC global interrupt (C2IMR1[5])

Flash memory global interrupt and Flash memory ECC single error interrupt (C2IMR1[6])

CPU1 SEV through EXTI[41]

EXTI Line 1:0 interrupt through EXTI[1:0]

(C2IMR1[17:16])

EXTI Line 3:2 interrupt through EXTI[3:2]

(C2IMR1[19:18])

EXTI Line 15:4 interrupt through EXTI[15:4]

(C2IMR1[31:20])

802.15.4 interrupt 0

DMA1 channel 3:1 interrupt (C2IMR2[2:0])

DMA1 channel 7:4 interrupt (C2IMR2[6:3])

DMAMUX1 overrun interrupt (C2IMR2[15])

ADC1 global interrupt (C2IMR1[12])

LPtimer 1 global interrupt

LPtimer 2 global interrupt

0x0000 000C

0x0000 0010

0x0000 0028

0x0000 002C

0x0000 0030

0x0000 0034

0x0000 0038

0x0000 003C

0x0000 0040

0x0000 0044

0x0000 0048

0x0000 004C

0x0000 0050

0x0000 0054

0x0000 0058

0x0000 005C

0x0000 0060

0x0000 0064

0x0000 0068

0x0000 006C

0x0000 0070

0x0000 0074

0x0000 0078

RM0471 Rev 5 331/1202

334

Nested vectored interrupt controller (NVIC) RM0471

Table 55. CPU2 vector table (continued)

Type of priority

Acronym Description Address

15 18 Settable

TIM1_BRK,

TIM1_UP,

TIM1_TRG_COM,

TIM1_CC

16 19 Settable TIM2

17 20 Settable TIM16

18 21 Settable TIM17

19 22 Settable

IPCC_C2_RX_IT

IPCC_C2_TX_IT

HSEM

20 23 Settable

PKA

True RNG

21 24 Settable AES2

22 25 Settable 802_IT1

23 26 Settable

24 27 -

I2C1_EV

I2C1_ER

25 28 Settable SPI1

26 29 -

27 30 Settable USART1

28 31

29 32 -

30 33 Settable

BLE_BLUE_IT

BLE_RFC_IT

BLE_RFFMS_IT

BLE_HOST_WKUP

31 34 Settable

802_IT2

802_HOST_WKUP

Timer 1 break, update, trigger and communication, capture compare interrupt

Timer 2 global interrupt

Timer 16 global interrupt

Timer 17 global interrupt

IPCC CPU2 RX occupied interrupt

IPCC CPU2 TX free interrupt

Semaphore interrupt 1 o CPU2

Private key accelerator interrupt (C2IMR1[8])

True random number generator interrupt (C2IMR1[9])

AES2 global interrupt

802.15.4 interrupt 1

I2C1 event interrupt

I2C1 error interrupt

Reserved

SPI1 global interrupt

Reserved

USART1 global interrupt

Reserved

BLE blue controller interrupt

BLE radio control interrupt

BLE radio states interrupt

BLE host wakeup interrupt

802.15.4 interrupt 2

802.15.4 host wakeup interrupt

0x0000 007C

0x0000 0080

0x0000 0084

0x0000 0088

0x0000 008C

0x0000 0090

0x0000 0094

0x0000 0098

0x0000 009C

0x0000 00A0

0x0000 00A4

0x0000 00A8

0x0000 00AC

0x0000 00B0

0x0000 00B4

0x0000 00B8

0x0000 00BC

The different wakeup sources are listed in Table 56

. Depending on its origin, the wakeup is handled

according to different types, see Section 14.4: EXTI functional behavior

for more information.

Some wakeup sources are able to generate an event to the CPUs. see Event column.

The wakeup source capability to wakeup CPU1 and or CPU2 is listed in

Wakeup column.

For CPUs interrupt handling see Section 13: Nested vectored interrupt controller (NVIC)

For Wakeup handling see Section 14: Extended interrupt and event controller (EXTI)

332/1202 RM0471 Rev 5

RM0471 Nested vectored interrupt controller (NVIC)

Table 56. Wakeup interrupt table

Description EXTI type Acronym

0 EXTI[0]

1 EXTI[1]

2 EXTI[2]

3 EXTI[3]

4 EXTI[4]

5 EXTI[5]

6 EXTI[6]

7 EXTI[7]

8 EXTI[8]

9 EXTI[8]

10 EXTI[10]

11 EXTI[11]

12 EXTI[12]

13 EXTI[13]

14 EXTI[14]

EXTI Line 0 from SYSCFG

EXTI Line 1 from SYSCFG

EXTI Line 2 from SYSCFG

EXTI Line 3 from SYSCFG

EXTI Line 4 from SYSCFG

EXTI Line 5 from SYSCFG

EXTI Line 6 from SYSCFG

EXTI Line 7 from SYSCFG

EXTI Line 8 from SYSCFG

EXTI Line 9 from SYSCFG

EXTI Line 10 from SYSCFG

EXTI Line 11 from SYSCFG

EXTI Line 12 from SYSCFG

EXTI Line 13 from SYSCFG

EXTI Line 14 from SYSCFG

15 EXTI[15]

16 PVD

17 RTC_ALARM

EXTI Line 15 from SYSCFG

PVD line

RTC Alarms (A and B) interrupt

TAMP, RTC_STAMP,

LSE_CSS

RTC Tamper interrupt

RTC TimeStamp interrupt

RCC LSECSS interrupt

19 RTC_WKUP

20 Reserved

RTC wakeup interrupt

21 Reserved

22 I2C1 wakeup

23 Reserved

I2C1 wakeup

24 USART1

25 Reserved

26 Reserved

27 Reserved

28 Reserved

29 LPTIM1 wakeup

30 LPTIM2 wakeup

31 Reserved

USART1 wakeup

LPtimer 1 wakeup

LPtimer 2 wakeup

Event Wakeup

Configurable A

Yes

Configurable A Yes

CPU1 and CPU2

Configurable A

Direct B

Yes

CPU1 and CPU2

RM0471 Rev 5 333/1202

334

Nested vectored interrupt controller (NVIC)

Acronym

Table 56. Wakeup interrupt table (continued)

Description EXTI type Event

RM0471

Wakeup

32 Reserved

33 Reserved

34 Reserved

35 Reserved

IPCC CPU1 interrupts

IPCC CPU2 interrupts

38 HSEM interrupt 0

39 HSEM interrupt 1

40 C2SEV

41 C1SEV

42 Flash interrupt

43 Reserved

44 HSE CSS interrupt

45 BLE interrupts

IPCC CPU1 RX occupied & TX free interrupts

IPCC CPU2 RX occupied & TX free interrupts

Semaphore interrupt 0 for CPU1

Semaphore interrupt 1 for CPU2

CPU2 SEV line

CPU1 SEV line

Flash ECC and global interrupts

RCC HSE CSS interrupt

BLE, RADIO, & RF_FSM interrupts

Direct C

Configurable A

Direct C

Direct B

Yes

CPU1

CPU2

(1)

(2)

CPU1

(1)

CPU2

(2)

CPU1

(3)

CPU2

(4)

CPU1 and CPU2

CPU2

(2)

CPU2

(2)

46 802 interrupts

47 Reserved

802.15.4 Int0 and Int1 interrupts

Direct B

48 CDBGPWRUPREQ Debug power up request wakeup Direct No CPU1 and CPU2

1. For correct operation the EXTI direct event C2IMRx.IMn bit must be set to 0 before CPU1 uses this direct event.

2. For correct operation the EXTI direct event C1IMRx.IMn bit must be set to 0 before CPU2 uses this direct event.

3. For correct operation the EXTI configurable event both C2IMRx.IMn and C2EMRx.EMn bits must be set to 0 before CPU1 uses this configurable event.

4. For correct operation the EXTI configurable event both C1IMRx.IMn and C1EMRx.EMn bits must be set to 0 before CPU2 uses this configurable event.

334/1202 RM0471 Rev 5

RM0471

14

Extended interrupt and event controller (EXTI)

Extended interrupt and event controller (EXTI)

The Extended interrupt and event controller (EXTI) manages the individual CPU and system wakeup through configurable and direct event inputs. It provides wakeup requests to the power control, and generates an interrupt request to the CPUs interrupt controller and events to the CPUs event input. For each CPU an additional event generation block (EVG) is needed to generate the CPU event signal.

The EXTI wakeup requests allow the system to be woken up from STOP modes, and the

CPU to be woken up from the CSTOP and CSTANDBY modes.

The interrupt request and event request generation can also be used in RUN modes.

14.1 EXTI main features

The EXTI main features are the following:

 49 input events supported

 Two CPUs supported

 All event inputs allow to wake up the system

 Events which do not have an associated wakeup flag in the peripheral, have a flag in the EXTI and generate an interrupt to the CPU from the EXTI

 Some events can be used to generate a CPU wakeup event

The asynchronous event inputs are classified in two groups:

 Configurable events (signals from I/Os or peripherals able to generate a pulse)

– Configurable events have the following features:

- Selectable active trigger edge

- Interrupt pending status register bit.

- Individual interrupt and event generation mask, used for conditioning the CPU wakeup, interrupt and event generation

- SW trigger possibility

 Direct events (interrupt and wakeup sources from peripherals having an associated flag which requiring to be cleared in the peripheral)

– Direct events have the following features:

- Fixed rising edge active trigger

- No interrupt pending status register bit in the EXTI (the interrupt pending status flag is provided by the peripheral generating the event)

- Individual interrupt and event generation mask, used for conditioning the CPU wakeup and event generation

- No SW trigger possibility

14.2 EXTI block diagram

The EXTI consists of a register block accessed via an AHB interface, the event input Trigger block, and the masking block as shown in

Figure 29

The register block contains all the EXTI registers.

The event input trigger block provides event input edge trigger logic.

RM0471 Rev 5 335/1202

352

Extended interrupt and event controller (EXTI) RM0471

The masking block provides the event input distribution to the different wakeup, interrupt and event outputs, and the masking of these.

Figure 29. EXTI block diagram

AHB interface hclk

Registers sys_wakeup c1_wakeup

PWR c(m)_wakeup it_exti_per(y)

Wakeup

Direct event(x) or

Configurable event(y)

Event

Trigger events Masking

Interrupt Direct event(x) c1_evt_exti c1_evt_rst

Pulse c1_event

EVG c1_fclk rxev nvic(x) CPU1 nvic(y)

EXTI

* it_exti_per(y) are only available for Configurable events (y)

Pin name

AHB interface hclk

Configurable event(y)

Direct event(x) it_exti_per (y) c(m)_evt_exti c(m)_evt_rst sys_wakeup c(m)_wakeup

Pin name c_fclk c_evt_in c_event c_evt_rst c(m)_evt_exti c(m)_evt_rst

Pulse c(m)_event

EVG c(m)_fclk rxev nvic(x) CPU(m) nvic(y)

MS44723V1

I/O

Table 57. EXTI pin overview

Description

I/O

EXTI register bus interface. When one event is configured to allow security, the AHB interface supports secure accesses.

I AHB bus clock and EXTI system clock.

Asynchronous wakeup events from peripherals that do not have an associated interrupt and flag in the peripheral.

Synchronous and asynchronous wakeup events from peripherals having an associated interrupt and flag in the peripheral.

O Interrupts to the CPU1 to CPU(m) associated with Configurable event (y).

O High level sensitive event output for CPU(m) synchronous to hclk. (m= 1 to 2)

I Asynchronous reset input to clear c(m)_evt_exti. (m= 1 to 2)

O Asynchronous system wakeup request to PWR for ck_sys and hclk.

O Wakeup request to PWR for CPU(m), synchronous to hclk. (m= 1 to 2)

I/O

Table 58. EVG pin overview

Description

I CPU free running clock.

I High level sensitive Events input from EXTI, asynchronous to CPU clock.

O Event pulse, synchronous to CPU clock.

O Event reset signal, synchronous to CPU clock.

336/1202 RM0471 Rev 5

RM0471 Extended interrupt and event controller (EXTI)

14.2.1 EXTI connections between peripherals and CPU

The peripherals able to generate wakeup or interrupt events when the system is in STOP mode or a CPU is in CSTOP mode are connected to the EXTI.

 Peripheral wakeup signals that generate a pulse or which do not have an interrupt status bits in the peripheral, are connected to an EXTI configurable event input. For these events the EXTI provides a status pending bit that has to be cleared. It is the

EXTI interrupt associated with the status bit that will interrupt the CPU.

 Peripheral interrupt and wakeup signals that have a status bit in the peripheral that has to be cleared in the peripheral, are connected to an EXTI direct event input. There is no status pending bit within the EXTI. The interrupt or wakeup is cleared by the CPU in the peripheral. It is the peripheral interrupt that will interrupt the CPU directly.

The EXTI configurable event interrupts are connected to the respective interrupt controller of each CPU(m).

The dedicated EXTI/EVG CPU(m) event is connected to the respective CPU(m) rxev input.

The EXTI CPU(m) wakeup signals are connected to the PWR block, and are used to wake up the system and CPU(m) sub-system bus clocks.

RM0471 Rev 5 337/1202

352

Extended interrupt and event controller (EXTI)

14.3 EXTI functional description

Depending on the EXTI event input type and wakeup target(s), different logic implementations are used. The applicable features are controlled from register bits:

 Active trigger edge enable, by rising edge selection

EXTI rising trigger selection register (EXTI_RTSR1) ,

EXTI rising trigger selection register (EXTI_RTSR2) ,

and falling edge selection

EXTI falling trigger selection register (EXTI_FTSR1) ,

EXTI falling trigger selection register (EXTI_FTSR2) .

 Software trigger, by

EXTI software interrupt event register (EXTI_SWIER1)

EXTI software interrupt event register (EXTI_SWIER2)

 Interrupt pending flag, by

EXTI pending register (EXTI_PR1) ,

EXTI pending register (EXTI_PR2) .

 CPU wakeup and interrupt enable, by

EXTI CPU wakeup with interrupt mask register (EXTI_IMR1) ,

EXTI CPU2 wakeup with interrupt mask register (EXTI_C2IMR1)

EXTI CPU wakeup with interrupt mask register (EXTI_IMR2) ,

EXTI CPU2 wakeup with interrupt mask register (EXTI_C2IMR2)

 CPU wakeup and event enable, by

EXTI CPU wakeup with event mask register (EXTI_EMR1)

EXTI CPU2 wakeup with event mask register (EXTI_C2EMR1)

EXTI CPU wakeup with event mask register (EXTI_EMR2)

EXTI CPU2 wakeup with event mask register (EXTI_C2EMR2) .

Table 59. EXTI event input configurations and register control

RM0471

Event input type

Logic implementation

Configurable

Direct

Configurable event input wakeup logic

Direct event input wakeup logic

1. Only for input events with configuration “rxev generation” enabled.

x x x x

14.3.1 EXTI configurable event input wakeup

Figure 30

is a detailed representation of the logic associated with configurable event inputs which will wake up the CPU(m) sub-system bus clocks and generated an EXTI pending flag and interrupt to the CPU(m) and or a CPU(m) wakeup event.

338/1202 RM0471 Rev 5

RM0471 Extended interrupt and event controller (EXTI)

Figure 30. Configurable event trigger logic CPU wakeup

AHB interface hclk

Configurable

Event input(y)

Falling trigger selection register

Rising trigger selection register

Software interrupt event register

Asynchronous Edge detection circuit rst

Peripheral interface hclk

Rising Edge detect Pulse generator

CPU(m)

Event mask register

CPU(m)

Interrupt mask register

Pending request register it_exti_per(y)

CPU(other) Imask(y)

(1)

CPU(m) Event(y)

Other CPU(m) Events(x,y)

Same circuit for Configurable and Direct events hclk

Rising

Edge detect rst c(m)_evt_rst c(m)_evt_exti

EVG ck_fclk_c(m)

CPU(m)

Rising Edge detect Pulse generator c(m)_event hclk

Other CPU(m) Wakeups

CPU(m) Wakeup(y) c(m)_wakeup

Other Wakeups

Wakeup(y) sys_wakeup

Logic duplicated for each CPU

EXTI

MS46538V1

1. Only for the input events that support CPU rxev generation c(n)_event.

The software interrupt event register allows to trigger configurable events by software, writing the corresponding register bit, irrespective of the edge selection setting.

The rising edge and falling edge selection registers allow to enable and select the configurable event active trigger edge or both edges.

Each CPU has its dedicated interrupt mask register and a dedicated event mask registers.

The enabled event allows to generate an event on the CPU. All events for a CPU are OR-ed together into a single CPU event signal. The event pending register (EXTI_PR) is not set for an unmasked CPU event.

Note:

The configurable events have unique interrupt pending request registers, shared by the

CPUs. The pending register is only set for an unmasked interrupt. Each configurable event provides a common interrupt to all CPUs. The configurable event interrupts need to be acknowledged by software in the EXTI_PR register.

When a CPU(m) interrupt or CPU(m) event is enabled the asynchronous edge detection circuit is reset by the clocked delay and rising edge detect pulse generator. This guarantees that the EXTI hclk clock is woken up before the asynchronous edge detection circuit is reset.

A detected configurable event interrupt pending request, may be cleared by any CPU. The system is unable to enter into Low-power modes as long as an interrupt pending request is active.

RM0471 Rev 5 339/1202

352

Extended interrupt and event controller (EXTI) RM0471

14.3.2 EXTI direct event input wakeup

Note:

Figure 31

is a detailed representation of the logic associated with direct event inputs waking up the system.

The direct events do not have an associated EXTI interrupt. The EXTI only wakes up the system and CPU sub-system clocks and may generate a CPU wakeup event. The peripheral synchronous interrupt, associated with the direct wakeup event wakes up the

CPU.

The EXTI direct event is able to generate a CPU event. This CPU event wakes up the CPU.

The CPU event may occur before the associated Peripheral interrupt flag is set.

The direct events are cleared in the peripheral generating the event. When a direct event input enabled by CPU(m) is cleared by another CPU before the CPU(m) clock is running, the CPU(m) no longer receives a CPU(m) interrupt nor a CPU(m) event and does not wake up. However the system stays in RUN mode, generating the CPU(m) clock. For this reason

CPU(m) direct events must NOT be cleared by the other CPU.

Figure 31. Direct event trigger logic CPU wakeup

AHB interface hclk hclk

Peripheral interface

CPU(m)

Interrupt mask register

CPU(m)

Event mask register

Direct

Event input(x)

Asynchronous

Rising Edge detect circuit rst

Falling Edge detect

Pulse generator

EXTI hclk

CPU(m) Event(x)

(1)

Other CPU(m)Events(x,y)

Same circuit for Configurable and Direct events hclk

Rising

Edge detect rst

CPU(m) Wakeup(x)

Other CPU(m) Wakeups hclk

Other Wakeups

Wakeup(x) c(m)_evt_rst c(m)_evt_exti

EVG ck_fclk_c(m)

CPU(m)

Rising Edge detect Pulse generator c(m)_event c(m)_wakeup sys_wakeup

Logic duplicated for each CPU

1. Only for the input events that support CPU rxev generation c(n)_event.

MS44725V1

14.4 EXTI functional behavior

The direct event inputs are enabled in the respective peripheral generating the wakeup event. The configurable events are enabled by enabling at least one of the trigger edges.

Once an event input is enabled, the generation of a CPU(m) wakeup is conditioned by the

CPU(m) interrupt mask and CPU(m) event mask.

340/1202 RM0471 Rev 5

RM0471 Extended interrupt and event controller (EXTI)

CPU interrupt enable

EXTI_CmIMR.IMn

Table 60. Masking functionality

CPU event enable

EXTI_CmEMR.EMn

Configurable event inputs

EXTI_PR.PIFn

exti(n) interrupt

(1)

CPU(m) event

CPU(m) wakeup

0 for all CPUs

1 for any CPU

Status latched

Masked

Yes

Masked

Yes

Masked

Yes

Masked

Yes

(2)

Yes

1. The single exti(n) interrupt goes to all CPUs. If no interrupt is required for CPU(m), the exti(n) interrupt must be masked in the CPU(m) interrupt controller.

2. Only if CPU(m) interrupt is enabled in EXTI_CmIMR.IMn.

For configurable event inputs, when the enabled edge(s) occur on the event input, an event request is generated. When the associated CPU(m) interrupt is unmasked the corresponding pending bit EXTI_PR.PIFn is set and the CPU(m) sub-system is woken up and CPU interrupt signal is activated. The EXTI_PR.PIFn pending bit must be cleared by software writing, it to ‘1’. This clears the CPU interrupt.

For direct event inputs, when enabled in the associated peripheral, an event request is generated on the rising edge only. There is no corresponding CPU pending bit in the EXTI.

When the associated CPU(m) interrupt is unmasked the corresponding CPU sub-system is woken up. The CPU is woken up (interrupted) by the peripheral synchronous interrupt.

The CPU(m) event must be unmasked to generate an event. When the enabled edge(s) occur on the event input a CPU(m) event pulse is generated. There is no event pending bit.

For the configurable event inputs an event request can be generated by software when writing a ‘1’ in the software interrupt/event register EXTI_SWIER, generating a rising edge on the event. The edge event pending bit is set in EXTI_PR, irrespective of the setting in

EXTI_RTSR.

RM0471 Rev 5 341/1202

352

Extended interrupt and event controller (EXTI) RM0471

The EXTI register map is divided as detailed in Table 61

Address

0x000 - 0x01C

0x020 - 0x03C

0x040 - 0x05C

0x080 - 0x0BC

0x0C0 - 0x0FC

Table 61. EXTI register map sections

Description

General configurable event [31:0] configuration

General configurable event [63:32] configuration

General configurable event [95:64] configuration

CPU1 input event configuration

CPU2 input event configuration

All the registers can be accessed with word (32-bit), half-word (16-bit) and byte (8-bit) access.

14.5.1 EXTI rising trigger selection register (EXTI_RTSR1)

Address offset: 0x000

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Res.

RT15 rw

RT14 rw

RT13 rw

RT12 rw

RT11 rw

RT10 rw

RT9 rw

RT8 rw

RT7 rw

RT6 rw

RT5 rw

RT4 rw

RT19 rw

RT3 rw

RT18 rw

RT2 rw

RT17 rw

RT1 rw

RT16 rw

RT0 rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 RT[19:0]: Rising trigger event configuration bit of configurable event input x (x = 19 to 0)

(1)

0: Rising trigger disabled (for event and Interrupt) for input line

1: Rising trigger enabled (for event and Interrupt) for input line

1. The configurable event inputs are edge triggered, no glitch must be generated on these inputs. If a rising edge on the configurable event input occurs during writing of the register, the associated pending bit is not set. Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

342/1202 RM0471 Rev 5

RM0471 Extended interrupt and event controller (EXTI)

14.5.2 EXTI falling trigger selection register (EXTI_FTSR1)

Address offset: 0x004

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Res.

FT15 rw

FT14 rw

FT13 rw

FT12 rw

FT11 rw

FT10 rw

FT9 rw

FT8 rw

FT7 rw

FT6 rw

FT5 rw

Res.

FT4 rw

FT19 rw

FT3 rw

FT18 rw

FT2 rw

FT17 rw

FT1 rw

FT16 rw

FT0 rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 FT[19:0]: Falling trigger event configuration bit of configurable event input x (x = 19 to 0) (1) .

0: Falling trigger disabled (for event and Interrupt) for input line

1: Falling trigger enabled (for event and Interrupt) for input line.

1. The configurable event inputs are edge triggered, no glitch must be generated on these inputs. If a falling edge on the configurable event input occurs during writing of the register, the associated pending bit is not set. Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

Res.

Address offset: 0x008

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Res.

15 14 13 12 11 10 9

SWI15 SWI14 SWI13 SWI12 SWI11 SWI10 SWI9 rw rw rw rw rw rw rw

Res.

SWI8 rw

Res.

20 19 18 17 16

Res.

SWI19 SWI18 SWI17 SWI16

4 rw

3 rw

2 rw

1 rw

0 7 6 5

SWI7 SWI6 SWI5 SWI4 SWI3 SWI2 rw rw rw rw rw rw

SWI1 rw

SWI0 rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 SWI[19:0]: Software interrupt on event x (x = 19 to 0)

A software interrupt is generated independent from the setting in EXTI_RTSR and

EXTI_FTSR. Will always return 0 when read.

0: Writing 0 has no effect.

1: Writing a 1 to this bit will trigger a rising edge event on event x.

This bit is auto cleared by HW.

RM0471 Rev 5 343/1202

352

Extended interrupt and event controller (EXTI) RM0471

14.5.4 EXTI pending register (EXTI_PR1)

Address offset: 0x00C

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Res.

20 19 18 17 16

Res.

PIF19 PIF18 PIF17 PIF16

4 rc_w1 rc_w1 rc_w1 rc_w1

3 2 1 0 15 14 13 12 11 10 9 8 7 6 5

PIF15 PIF14 PIF13 PIF12 PIF11 PIF10 PIF9 PIF8 PIF7 PIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

14.5.5 EXTI rising trigger selection register (EXTI_RTSR2)

Address offset: 0x020

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Res.

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 PIF[19:0]: configurable event inputs x (x = 19 to 0) Pending bit.

0: No trigger request occurred

1: Selected trigger request occurred

This bit is set when the selected edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing a 1 into the bit.

Res.

RT41 rw

RT40 rw

Res.

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 RT41: Rising trigger event configuration bit of configurable event input 41

(1)

0: Rising trigger disabled (for event and interrupt) for input line

1: Rising trigger enabled (for event and interrupt) for input line

Bit 8 RT40: Rising trigger event configuration bit of configurable event input 40

(1)

0: Rising trigger disabled (for event and interrupt) for input line

1: Rising trigger enabled (for event and interrupt) for input line

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 RT33: Rising trigger event configuration bit of configurable event input 33

(1)

0: Rising trigger disabled (for event and interrupt) for input line

1: Rising trigger enabled (for event and interrupt) for input line

Bit 0 Reserved, must be kept at reset value.

RT33 rw

Res.

344/1202 RM0471 Rev 5

RM0471 Extended interrupt and event controller (EXTI)

1. The configurable event inputs are edge triggered, no glitch must be generated on these inputs. If a rising edge on the configurable event input occurs during writing of the register, the associated pending bit is not set. Rising and falling edge triggers can be set for the same configurable Event input. In this case, both edges generate a trigger.

14.5.6 EXTI falling trigger selection register (EXTI_FTSR2)

Address offset: 0x024

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Res.

FT41 rw

FT40 rw

Res.

FT33 rw

Res.

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 FT41: Falling trigger event configuration bit of configurable event input 41

(1)

0: Falling trigger disabled (for event and interrupt) for input line

1: Falling trigger enabled (for event and interrupt) for input line

Bit 8 FT40: Falling trigger event configuration bit of configurable event input 40

(1)

0: Falling trigger disabled (for event and interrupt) for input line

1: Falling trigger enabled (for event and interrupt) for input line

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 FT33: Falling trigger event configuration bit of configurable event input 33 (1)

0: Falling trigger disabled (for event and interrupt) for input line

1: Falling trigger enabled (for event and interrupt) for input line

Bit 0 Reserved, must be kept at reset value.

Res.

Address offset: 0x028

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Res.

9 8 7

SWI41 SWI40 Res.

rw rw

Bits 31:10 Reserved, must be kept at reset value.

Res.

2 1

Res.

SWI33 rw

Res.

RM0471 Rev 5 345/1202

352

Extended interrupt and event controller (EXTI) RM0471

Bit 9 SWI41: Software interrupt on event 41

A software interrupt is generated independent from the setting in EXTI_RTSR and

EXTI_FTSR. Will always return 0 when read.

0: Writing 0 has no effect.

1: Writing a 1 to this bit will trigger a rising edge event on event 41.

This bit is auto cleared by HW.

Bit 8 SWI40: Software interrupt on event 40

A software interrupt is generated independent from the setting in EXTI_RTSR and

EXTI_FTSR. Will always return 0 when read.

0: Writing 0 has no effect.

1: Writing a 1 to this bit will trigger a rising edge event on event 40.

This bit is auto cleared by HW.

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 SWI33: Software interrupt on event 33

A software interrupt is generated independent from the setting in EXTI_RTSR and

EXTI_FTSR. Will always return 0 when read.

0: Writing 0 has no effect.

1: Writing a 1 to this bit will trigger a rising edge event on event 33.

This bit is auto cleared by HW.

Bit 0 Reserved, must be kept at reset value.

14.5.8 EXTI pending register (EXTI_PR2)

Address offset: 0x02C

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Res.

9 8

PIF41 PIF40 rc_w1 rc_w1

Res.

PIF33 rc_w1

Res.

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 PIF41: configurable event inputs 41 pending bit

0: No trigger request occurred

1: selected trigger request occurred

This bit is set when the selected edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing a 1 into the bit.

Bit 8 PIF40: configurable event inputs 40 pending bit

0: No trigger request occurred

1: selected trigger request occurred

This bit is set when the selected edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing a 1 into the bit.

346/1202 RM0471 Rev 5

RM0471 Extended interrupt and event controller (EXTI)

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 PIF33: configurable event inputs 33 pending bit

0: No trigger request occurred

1: selected trigger request occurred

This bit is set when the selected edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing a 1 into the bit.

Bit 0 Reserved, must be kept at reset value.

14.5.9 EXTI CPU wakeup with interrupt mask register (EXTI_IMR1)

Address offset: 0x080

Reset value: 0x7FC0 0000

Contains register bits for configurable events and direct events.

Res.

IM15 rw

IM30 rw

IM14 rw

IM29 rw

IM13 rw

Res.

IM12 rw

IM27 rw

IM11 rw

IM26 rw

IM10 rw

Res.

IM9 rw

IM24 rw

IM8 rw

Res.

IM7 rw

IM22 rw

IM6 rw

Res.

IM5 rw

Res.

IM4 rw

IM19 rw

IM3 rw

IM18 rw

IM2 rw

IM17 rw

IM1 rw

IM16 rw

IM0 rw

Bits 31, 28, 25, 23,

21:20

Reserved, must be kept at reset value.

Bits 30:29, 27:26,

24, 22, 19:0

IM[30:29, 27:26, 24, 22, 19:0]: CPU wakeup with interrupt mask on event input x (x = 30:29,

27:26, 24, 22, 19:0)

(1)(2)

0: Wakeup with interrupt request from Line x is masked

1: Wakeup with interrupt request from Line x is unmasked

1. The reset value for configurable event inputs is set to ‘0’ in order to disable the interrupt by default.

2. The reset value for direct event inputs is set to ‘1’ in order to enable the interrupt by default.

14.5.10 EXTI CPU2 wakeup with interrupt mask register (EXTI_C2IMR1)

Address offset: 0x0C0

Reset value: 0x7FC0 0000

Contains register bits for configurable events and direct events.

Res.

IM15 rw

IM30 rw

IM14 rw

IM29 rw

IM13 rw

Res.

IM12 rw

IM27 rw

IM11 rw

IM26 rw

IM10 rw

Res.

IM9 rw

IM24 rw

IM8 rw

Res.

IM7 rw

IM22 rw

IM6 rw

Res.

IM5 rw

Res.

IM4 rw

IM19 rw

IM3 rw

IM18 rw

IM2 rw

IM17 rw

IM1 rw

IM16 rw

IM0 rw

RM0471 Rev 5 347/1202

352

Extended interrupt and event controller (EXTI) RM0471

Bits 31, 28, 25, 23,

21:20

Reserved, must be kept at reset value.

Bits 30:29, 27:26,

24, 22, 19:0

IM[30:29, 27:26, 24, 22, 19 :0]: CPU2 wakeup with interrupt mask on event input x (x = 30:29,

27:26, 24, 22, 19 to 0)

(1)(2)

0: Wakeup with interrupt request from Line x is masked

1: Wakeup with interrupt request from Line x is unmasked

1. The reset value for configurable event inputs is set to ‘0’ in order to disable the interrupt by default.

2. The reset value for direct event inputs is set to ‘1’ in order to enable the interrupt by default.

14.5.11 EXTI CPU wakeup with event mask register (EXTI_EMR1)

Address offset: 0x084

Reset value: 0x0000 0000

Res.

15 14 13 12 11 10

EM15 EM14 EM13 EM12 EM11 EM10 rw rw rw rw rw rw

EM9 rw

EM8 rw

EM7 rw

EM6 rw

EM5 rw

Res.

EM4 rw

19 18 17

EM19 EM18 EM17 rw

3 rw

2 rw

EM3 rw

EM2 rw

EM1 rw

EM0 rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:17 EM[19:17]: CPU wakeup with event generation mask on event input x (x = 19 to 17)

0: Wakeup with event generation from Line x is masked

1: Wakeup with event generation from Line x is unmasked

Bit 16 Reserved, must be kept at reset value.

Bits 15:0 EM[15:0]: CPU wakeup with event generation mask on event input x (x = 15 to 0)

0: Wakeup with event generation from Line x is masked

1: Wakeup with event generation from Line x is unmasked

14.5.12 EXTI CPU2 wakeup with event mask register (EXTI_C2EMR1)

Address offset: 0x0C4

Reset value: 0x0000 0000

Res.

15 14 13 12 11 10

EM15 EM14 EM13 EM12 EM11 EM10 rw rw rw rw rw rw

EM9 rw

EM8 rw

EM7 rw

EM6 rw

EM5 rw

Res.

EM4 rw

19 18 17

EM19 EM18 EM17 rw rw rw

EM3 rw

EM2 rw

EM1 rw

Res.

EM0 rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:17 EM[19:17]: CPU2 wakeup with event generation mask on event input x (x = 19 to 17)

0: Wakeup with event generation from Line x is masked

1: Wakeup with event generation from Line x is unmasked

Bit 16 Reserved, must be kept at reset value.

348/1202 RM0471 Rev 5

RM0471 Extended interrupt and event controller (EXTI)

Bits 15:0 EM[:0]: CPU2 wakeup with event generation mask on event input x (x = 15 to 0)

0: Wakeup with event generation from Line x is masked

1: Wakeup with event generation from Line x is unmasked

14.5.13 EXTI CPU wakeup with interrupt mask register (EXTI_IMR2)

Address offset: 0x090

Reset value: 0x0001 FCFD

Contains register bits for configurable events and direct events.

Res.

IM46 rw

IM45 rw

IM44 rw

Res.

IM42 rw

IM41 rw

IM40 rw

IM39 rw

IM38 rw

IM37 rw

IM36 rw

Res.

IM33 rw

IM48 rw

Res.

Bits 31:17, 15, 11,

3:2, 0

Reserved, must be kept at reset value.

Bits 16, 14:12,

10:4, 1

IM[48, 46:44, 42:36, 33]: CPU wakeup with interrupt mask on event input x (x = 48, 46 to 44,

42 to 36, 33)

(1)(2)

0: Wakeup with interrupt request from Line x is masked

1: Wakeup with interrupt request from Line x is unmasked

1. The reset value for configurable event inputs is set to ‘0’ in order to disable the interrupt by default.

2. The reset value for direct event inputs is set to ‘1’ in order to enable the interrupt by default.

14.5.14 EXTI CPU2 wakeup with interrupt mask register (EXTI_C2IMR2)

Address offset: 0x0D0

Reset value: 0x0001 FCFD

Contains register bits for configurable events and direct events.

Res.

IM46 rw

IM45 rw

IM44 rw

Res.

IM42 rw

IM41 rw

IM40 rw

IM39 rw

IM38 rw

IM37 rw

IM36 rw

Res.

IM33 rw

IM48 rw

Res.

Bits 31:17, 15, 11,

3:2, 0

Reserved, must be kept at reset value.

Bits 16, 14:12, 10:4,

IM[48, 46:44, 42:36, 33]: CPU wakeup with interrupt mask on event input x (x = 48, 46 to 44,

42 to 36, 33)

(1)(2)

0: Wakeup with interrupt request from Line x is masked

1: Wakeup with interrupt request from Line x is unmasked

1. The reset value for configurable event inputs is set to ‘0’ in order to disable the interrupt by default.

2. The reset value for direct event inputs is set to ‘1’ in order to enable the interrupt by default.

RM0471 Rev 5 349/1202

352

Extended interrupt and event controller (EXTI) RM0471

14.5.15 EXTI CPU wakeup with event mask register (EXTI_EMR2)

Address offset: 0x094

Reset value: 0x0000 0000

Res.

EM41 rw

EM40 rw

Res.

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 EM41: CPU wakeup with event generation mask on event input 41

0: Wakeup with event generation from Line 41 is masked

1: Wakeup with event generation from Line 41 is unmasked

Bit 8 EM40: CPU wakeup with event generation mask on event input 40.

0: Wakeup with event generation from Line 40 is masked

1: Wakeup with event generation from Line 40 is unmasked

Bits 7:0 Reserved, must be kept at reset value.

14.5.16 EXTI CPU2 wakeup with event mask register (EXTI_C2EMR2)

Address offset: 0x0D4

Reset value: 0x0000 0000

Res.

EM41 rw

EM40 rw

Res.

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 EM41: CPU2 wakeup with event generation mask on event input 41

0: Wakeup with event generation from Line 41 is masked

1: Wakeup with event generation from Line 41 is unmasked

Bit 8 EM40: CPU2 wakeup with event generation mask on event input 40.

0: Wakeup with event generation from Line 40 is masked

1: Wakeup with event generation from Line 40 is unmasked

Bits 7:0 Reserved, must be kept at reset value.

350/1202 RM0471 Rev 5

RM0471 Extended interrupt and event controller (EXTI)

14.5.17 EXTI register map

The following table gives the EXTI register map and the reset values.

Table 62. EXTI register map and reset values

Offset Register

0x000

0x004

0x020

0x024

EXTI_RTSR1

Reset value

EXTI_FTSR1

Reset value

0x008

EXTI_SWIER1

Reset value

0x00C

0x010-

0x01C

EXTI_RPR1

Reset value

Reserved

EXTI_RTSR2

Reset value

EXTI_FTSR2

Reset value

0x028

EXTI_SWIER2

Reset value

0x02C

0x030-

0x07C

EXTI_PR2

Reset value

Reserved

0x080

0x084

0x088-

0x08C

EXTI_IMR1

Reset value

EXTI_EMR1

Reset value

Reserved

0x090

0x094

EXTI_IMR2

Reset value

EXTI_EMR2

0x098-

0x0BC

Reset value

Reserved

1 1 1 1

RT[19:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FT[19:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SW[19:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIF[19:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0

IM[19:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EM[19:17]

0 0 0 0 0 0 0 0 0 0

EM[15:0]

0 0 0 0 0 0 0 0 0

IM[46:44]

1 1 1

IM [42:36]

1 0 0 1 1 1 1

0 0

RM0471 Rev 5 351/1202

352

Extended interrupt and event controller (EXTI) RM0471

Table 62. EXTI register map and reset values (continued)

Offset Register

0x0C0

EXTI_C2IMR1

Reset value

0x0C4

EXTI_C2EMR1

0x0C8-

0x0CC

Reset value

Reserved

0x0D0

EXTI_CIMR2

Reset value

0x0D4

EXTI_C2EMR2

Reset value

1 1 1 1

IM[19:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EM[19:17]

0 0 0 0 0 0 0 0 0 0

EM[15:0]

0 0 0 0 0 0 0 0 0

IM[46:44]

1 1 1

IM [42:36]

1 0 0 1 1 1 1

0 0

Refer to Section 2.2 on page 55 for the register boundary addresses.

352/1202 RM0471 Rev 5

RM0471

15

Analog-to-digital converter (ADC)

Analog-to-digital converter (ADC)

15.1 Introduction

The ADC consists of a 12-bit successive approximation analog-to-digital converter.

The ADC has up to 14 multiplexed channels. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit data register.

The ADC is mapped on the AHB bus to allow fast data handling.

The analog watchdog features allow the application to detect if the input voltage goes outside the user-defined high or low thresholds.

A built-in hardware oversampler allows to improve analog performance while off-loading the related computational burden from the CPU.

An efficient low-power mode is implemented to allow very low consumption at low frequency.

15.2 ADC main features

 High-performance features

– 12, 10, 8 or 6-bit configurable resolution

– ADC conversion time is independent from the AHB bus clock frequency

– Faster conversion time by lowering resolution

– Manage single-ended or differential inputs

– AHB slave bus interface to allow fast data handling

– Self-calibration

– Channel-wise programmable sampling time

– Up to four injected channels (analog inputs assignment to regular or injected channels is fully configurable)

– Hardware assistant to prepare the context of the injected channels to allow fast context switching

– Data alignment with in-built data coherency

– Data can be managed by DMA for regular channel conversions

– 4 dedicated data registers for the injected channels

 Oversampler

– 16-bit data register

– Oversampling ratio adjustable from 2 to 256

– Programmable data shift up to 8-bit

 Low-power features

– Speed adaptive low-power mode to reduce ADC consumption when operating at low frequency

– Allows slow bus frequency application while keeping optimum ADC performance

– Provides automatic control to avoid ADC overrun in low AHB bus clock frequency

RM0471 Rev 5 353/1202

443

Analog-to-digital converter (ADC) RM0471 application (auto-delayed mode)

 11 external analog input channels

 In addition, there are several internal dedicated channels

– The internal reference voltage (V

REFINT

)

– The internal temperature sensor (V

)

– The V

BAT

monitoring channel (V

BAT

/3)

 Start-of-conversion can be initiated:

– By software for both regular and injected conversions

– By hardware triggers with configurable polarity (internal timers events or GPIO input events) for both regular and injected conversions

 Conversion modes

– The ADC can convert a single channel or can scan a sequence of channels

– Single mode converts selected inputs once per trigger

– Continuous mode converts selected inputs continuously

– Discontinuous mode

 Interrupt generation at ADC ready, the end of sampling, the end of conversion (regular or injected), end of sequence conversion (regular or injected), analog watchdog 1, 2 or

3 or overrun events

 3 analog watchdogs

 ADC input range: V

SSA

≤ V

DDA

Figure 32

shows the block diagram of one ADC.

354/1202 RM0471 Rev 5

RM0471

15.3 ADC functional description

Analog-to-digital converter (ADC)

Figure 32

shows the ADC block diagram and

Table 64 gives the ADC pin description.

Figure 32. ADC block diagram

VDDA

2.0 to 3.6 V

ADC_INP[16:15,

13:5]

ADC_INN[15,

12:5] adc_ext0_trg adc_ext1_trg adc_ext2_trg

.......

adc_ext13_trg adc_ext14_trg adc_ext15_trg

JAUTO

ADC_JSQRx

ADC_SQRx

CONT single/cont

REFINT

BAT

ADCAL self calibration

INP[18:0]

INN[18:0] analog input channels

Input selection & scan control

SMPx[2:0] sampling time

Start & Stop

Control

AUTDLY

Bias & Ref

SAR ADC

CONVERTED

DATA start

ADSTP stop conv

RDATA[11:0]

JDATA1[11:0]

JDATA2[11:0]

JDATA3[11:0]

JDATA4[11:0]

AREADY

EOSMP

EOC

EOS

OVR

JEOS

JQOVF

AWDx slave adc_it master

AHB interface adc_dma

Oversampler

OVRMOD overrun mode

ALIGN left/right

RES[1:0]

12, 10, 8 bits

JOFFSETx[11:0]

JOFFSETx_CH[11:0]

DMACFG

DMAEN

ROVSM

TROVS

OVSS[3:0]

OVSR[2:0]

JOVSE

ROVSE

Oversampling options adc_ker_ck adc_hclk

HW trigger

EXTEN[1:0] trigger enable and edge selection

DISCEN

DISCNU[:0]

Discontinuous mode

Analog watchdog 1,2,3

EXTi mapped at product level

EXTSEL[3:0] trigger selection

AWD1

AWD2

AWD3 adc_awd1 adc_awd2 adc_awd3

J SW trigger adc_jext0_trg adc_jext1_trg adc_jext2_trg adc_jext13_trg adc_jext14_trg adc_jext15_trg

JEXTi mapped at product level

HW trigger

JEXTEN[1:0] trigger enable and edge selection

JEXTSEL[3:0] trigger selection

AWD1EN

JAWD1EN

AWD1SGL

JDISCEN

JDISCNUM[2:0]

AWDCH1[4:0]

LT1[11:0]

JQM

HT1[11:0]

Injected context

AWDCH2[18:0]

Queue mode

LT2[7:0]

AWDCH3[18:0]

HT2[7:0]

HT3[7:0]

LT3[7:0]

MSv62446V2

RM0471 Rev 5 355/1202

443

Analog-to-digital converter (ADC) RM0471

BAT

Table 63. ADC internal input/output signals

Internal signal name

Signal type

Description

EXT[15:0]

JEXT[15:0]

ADC_AWDx_OUT

REFINT

Inputs

Output

Input

Input supply

Up to 16 external trigger inputs for the regular conversions (can be connected to on-chip timers).

Up to 16 external trigger inputs for the injected conversions (can be connected to on-chip timers).

Internal analog watchdog output signal connected to on-chip timers (x = Analog watchdog number 1,2,3)

Output voltage from internal temperature sensor

Output voltage from internal reference voltage

External battery voltage supply

Pin name

VDDA

VSSA

INP i

INN i

ADC1_INNi

ADC1_INPi

Table 64. ADC input/output pins

Signal type Comments

Input, analog supply

Input, analog supply ground

Positive analog input channels

Analog power supply equal V

DDA

2.0 V ≤ V

DDA

≤ 3.6 V

Ground for analog power supply. On device package which do not have a dedicated V

SSA internally connected to V

pin, V

SSA

Connected either to ADC1_INP i external channels or to internal channels. This input is converted in singleended mode

Connected either to V

SSA

or to external channels:

ADC1_INNi and ADC1_INP[i+1].

Negative analog input channels

Negative external analog input signals

Up to 9 analog input channels

Refer to

Section 15.3.4: ADC1 connectivity for details.

Positive external analog input signals

Up to 11 analog input channels

Refer to Section 15.3.4: ADC1 connectivity for details

356/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Note:

Dual clock domain architecture

The dual clock-domain architecture means that the ADC clock is independent from the AHB bus clock.

The input clock is and can be selected between two different clock sources (see

Figure 33:

ADC clock scheme ):

The ADC clock can be a specific clock source, derived from the following clock sources:

– The system clock

– PLL “P” clock

Refer to RCC Section for more information on how to generate ADC dedicated clock.

To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be reset.

2. The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). In this mode, a programmable divider factor can be selected (/1, 2 or 4 according to bits CKMODE[1:0]).

To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be different from “00”.

For option 2), a prescaling factor of 1 (CKMODE[1:0]=01) can be used only if the AHB prescaler is set to 1 (HPRE[3:0] = 0xxx in RCC_CFGR register).

Option 1) has the advantage of reaching the maximum ADC clock frequency whatever the

AHB clock scheme selected. The ADC clock can eventually be divided by the following ratio:

1, 2, 4, 6, 8, 12, 16, 32, 64, 128, 256; using the prescaler configured with bits PRESC[3:0] in the ADCx_CCR register.

Option 2) has the advantage of bypassing the clock domain resynchronizations. This can be useful when the ADC is triggered by a timer and if the application requires that the ADC is precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant time is added by the resynchronizations between the two clock domains).

RM0471 Rev 5 357/1202

443

Analog-to-digital converter (ADC)

Figure 33. ADC clock scheme

RM0471

RCC

(Reset and clock controller)

HCLK

ADC1

AHB interface

Bits CKMODE[1:0] of ADC1_CCR

ADC1_CK

/1 or /2 or /4

/1, 2, 4, 6, 8, 10,

12, 16, 32, 64,

128, 256

Others

Analog ADC1

Bits PREC[3:0] of ADC1_CCR

Bits CKMODE[1:0] of ADC1_CCR

MSv41966V1

Clock ratio constraint between ADC clock and AHB clock

There are generally no constraints to be respected for the ratio between the ADC clock and the AHB clock except if some injected channels are programmed. In this case, it is mandatory to respect the following ratio:

 F

HCLK

≥ F

ADC

/ 4 if the resolution of all channels are 12-bit or 10-bit

 F

HCLK

≥ F

ADC

/ 3 if there are some channels with resolutions equal to 8-bit (and none with lower resolution)

 F

HCLK

≥ F

ADC

/ 2 if there are some channels with resolutions equal to 6-bit

358/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Figure 34. ADC1 connectivity

Channel selection

ADC1_INP5

ADC1_INN5

ADC1_INP6

ADC1_INN6

ADC1_INP7

ADC1_INN7

ADC1_INP8

ADC1_INN8

ADC1_INP9

ADC1_INN9

ADC1_INP10

ADC1_INN10

ADC1_INP11

ADC1_INN11

ADC1_INP12

ADC1_INN12

ADC1_INP13

ADC1_INP15

ADC1_INN15

ADC1_INP16

BAT

ADC1

REFINT

SSA reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved

SSA

INP

[8]

INN

[8]

INP

[9]

INN

[9]

INP

[10]

INN

[10]

INP

[11]

INN

[11]

INP

[12]

INN

[12]

INP

[13]

INN

[13]

INP

[14]

INN

[14]

INP

[0]

INN

[0]

INP

[1]

INN

[1]

INP

[2]

INN

[2]

INP

[3]

INN

[3]

INP

[4]

INN

[4]

INP

[5]

INN

[5]

INP

[6]

INN

[6]

INP

[7]

INN

[7]

INP

[15]

INN

[15]

INP

[16]

INN

[16]

INP

[17]

INN

[17]

INP

[18]

INN

[18]

DDA

INP

INN

SAR

ADC1

SSA

MSv62447V2

RM0471 Rev 5 359/1202

443

Analog-to-digital converter (ADC) RM0471

The ADC implements an AHB slave port for control/status register and data access. The features of the AHB interface are listed below:

 Word (32-bit) accesses

 Single cycle response

 Response to all read/write accesses to the registers with zero wait states.

The AHB slave interface does not support split/retry requests, and never generates AHB errors.

15.3.6 ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator

(ADVREGEN)

Note:

By default, the ADC is in Deep-power-down mode where its supply is internally switched off to reduce the leakage currents (the reset state of bit DEEPPWD is 1 in the ADC_CR register).

To start ADC operations, it is first needed to exit Deep-power-down mode by setting bit

DEEPPWD=0.

When ADC operations are complete, the ADC can be disabled (ADEN=0). It is possible to save power by also disabling the ADC voltage regulator. This is done by writing bit

ADVREGEN=0.

Then, to save more power by reducing the leakage currents, it is also possible to re-enter in

ADC Deep-power-down mode by setting bit DEEPPWD=1 into ADC_CR register. This is particularly interesting before entering Stop mode.

Writing DEEPPWD=1 automatically disables the ADC voltage regulator and bit ADVREGEN is automatically cleared.

When the internal voltage regulator is disabled (ADVREGEN=0), the internal analog calibration is kept.

In ADC Deep-power-down mode (DEEPPWD=1), the internal analog calibration is lost and it is necessary to either relaunch a calibration or re-apply the calibration factor which was

previously saved (refer to Section 15.3.8: Calibration (ADCAL, ADCALDIF,

ADC_CALFACT)

15.3.7 Single-ended and differential input channels

Channels can be configured to be either single-ended input or differential input by programming DIFSEL[i] bits in the ADC_DIFSEL register. This configuration must be written while the ADC is disabled (ADEN=0). Note that the DIFSEL[i] bits corresponding to singleended channels are always programmed at 0.

In single-ended input mode, the analog voltage to be converted for channel “i” is the difference between the ADCy_INPx external voltage equal to V

SSA

INP[i]

(positive input) and

In differential input mode, the analog voltage to be converted for channel “i” is the difference between the ADCy_INPx external voltage positive input equal to V

ADCy_INNx negative input equal to V

INN[i]

INP[i]

, and the

When ADC is configured as differential mode, both inputs should be biased at (V

DDA

) / 2 voltage. Refer to the device datasheet for the allowed common mode input voltage V

CMIN

360/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

The input signals are supposed to be differential (common mode voltage should be fixed).

Internal channels (such as V

and V

REFINT

) are used in single-ended mode only.

For a complete description of how the input channels are connected, refer to Section 15.3.4:

ADC1 connectivity

Caution: When configuring the channel “i” in differential input mode, its negative input voltage V

INN[i] is connected to another channel. As a consequence, this channel is no longer usable in single-ended mode or in differential mode and must never be configured to be converted.

15.3.8 Calibration (ADCAL, ADCALDIF, ADC_CALFACT)

The ADC provides an automatic calibration procedure which drives all the calibration sequence including the power-on/off sequence of the ADC. During the procedure, the ADC calculates a calibration factor which is 7-bit wide and which is applied internally to the ADC until the next ADC power-off. During the calibration procedure, the application must not use the ADC and must wait until calibration is complete.

Calibration is preliminary to any ADC operation. It removes the offset error which may vary from chip to chip due to process or bandgap variation.

The calibration factor to be applied for single-ended input conversions is different from the factor to be applied for differential input conversions:

 Write ADCALDIF=0 before launching a calibration which will be applied for singleended input conversions.

 Write ADCALDIF=1 before launching a calibration which will be applied for differential input conversions.

The calibration is then initiated by software by setting bit ADCAL=1. Calibration can only be initiated when the ADC is disabled (when ADEN=0). ADCAL bit stays at 1 during all the calibration sequence. It is then cleared by hardware as soon the calibration completes. At this time, the associated calibration factor is stored internally in the analog ADC and also in the bits CALFACT_S[6:0] or CALFACT_D[6:0] of ADC_CALFACT register (depending on single-ended or differential input calibration)

The internal analog calibration is kept if the ADC is disabled (ADEN=0). However, if the ADC is disabled for extended periods, then it is recommended that a new calibration cycle is run before re-enabling the ADC.

The internal analog calibration is lost each time the power of the ADC is removed (example, when the product enters in Standby or VBAT mode). In this case, to avoid spending time recalibrating the ADC, it is possible to re-write the calibration factor into the ADC_CALFACT register without recalibrating, supposing that the software has previously saved the calibration factor delivered during the previous calibration.

The calibration factor can be written if the ADC is enabled but not converting (ADEN=1 and

ADSTART=0 and JADSTART=0). Then, at the next start of conversion, the calibration factor will automatically be injected into the analog ADC. This loading is transparent and does not add any cycle latency to the start of the conversion. It is recommended to recalibrate when

DDA

voltage changed more than 10%.

RM0471 Rev 5 361/1202

443

Analog-to-digital converter (ADC) RM0471

Software procedure to calibrate the ADC

Ensure DEEPPWD=0, ADVREGEN=1 and that ADC voltage regulator startup time has elapsed.

3. Select the input mode for this calibration by setting ADCALDIF=0 (single-ended input) or ADCALDIF=1 (differential input).

6. The calibration factor can be read from ADC_CALFACT register.

Figure 35. ADC calibration

ADCALDIF 0: Single-ended input 1: Differential input t

CAB

ADCAL

ADC State

CALFACT_x[6:0]

OFF Startup

0x00

Calibrate OFF

Calibration factor by S/W by H/W Indicative timings

MSv30263V2

Software procedure to re-inject a calibration factor into the ADC

Ensure ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing).

2. Write CALFACT_S and CALFACT_D with the new calibration factors.

3. When a conversion is launched, the calibration factor will be injected into the analog

ADC only if the internal analog calibration factor differs from the one stored in bits

CALFACT_S for single-ended input channel or bits CALFACT_D for differential input channel.

362/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Figure 36. Updating the ADC calibration factor

ADC state

Internal calibration factor[6:0]

Ready (not converting) Converting channel Ready Converting channel

(Single ended) (Single ended)

Updating calibration

F1 F2

Start conversion

(hardware or sofware)

WRITE ADC_CALFACT

CALFACT_S[6:0] F2 by s/w by h/w

MSv30529V2

Converting single-ended and differential analog inputs with a single ADC

If the ADC is supposed to convert both differential and single-ended inputs, two calibrations must be performed, one with ADCALDIF=0 and one with ADCALDIF=1. The procedure is the following:

Disable the ADC.

4. Enable the ADC, configure the channels and launch the conversions. Each time there is a switch from a single-ended to a differential inputs channel (and vice-versa), the calibration will automatically be injected into the analog ADC.

Figure 37. Mixing single-ended and differential channels

Trigger event

ADC state RDY CONV CH 1

Single ended inputs channel)

RDY CONV CH2

(Differential inputs channel)

RDY CONV CH3

(Differential inputs channel)

RDY CONV CH4

(Single inputs

channel)

Internal calibration factor[6:0]

F2 F3 F2

CALFACT_S[6:0] F2

CALFACT_D[6:0]

RM0471 Rev 5

MSv30530V2

363/1202

443

Analog-to-digital converter (ADC) RM0471

First of all, follow the procedure explained in

Section 15.3.6: ADC Deep-power-down mode

(DEEPPWD) and ADC voltage regulator (ADVREGEN)

Once DEEPPWD=0 and ADVREGEN=1, the ADC can be enabled and the ADC needs a stabilization time of t

STAB

before it starts converting accurately, as shown in

Figure 38

. Two control bits enable or disable the ADC:

 ADEN=1 enables the ADC. The flag ADRDY will be set once the ADC is ready for operation.

 ADDIS=1 disables the ADC. ADEN and ADDIS are then automatically cleared by hardware as soon as the analog ADC is effectively disabled.

Regular conversion can then start either by setting ADSTART=1 (refer to Section 15.3.18:

Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) )

or when an external trigger event occurs, if triggers are enabled.

Injected conversions start by setting JADSTART=1 or when an external injected trigger event occurs, if injected triggers are enabled.

Software procedure to enable the ADC

Clear the ADRDY bit in the ADC_ISR register by writing ‘1’.

3. Wait until ADRDY=1 (ADRDY is set after the ADC startup time). This can be done using the associated interrupt (setting ADRDYIE=1).

4. Clear the ADRDY bit in the ADC_ISR register by writing ‘1’ (optional).

Caution: ADEN bit cannot be set when ADCAL is set and during four ADC clock cycles after the

ADCAL bit is cleared by hardware (end of the calibration).

Software procedure to disable the ADC

Check that both ADSTART=0 and JADSTART=0 to ensure that no conversion is ongoing. If required, stop any regular and injected conversion ongoing by setting

ADSTP=1 and JADSTP=1 and then wait until ADSTP=0 and JADSTP=0.

3. If required by the application, wait until ADEN=0, until the analog ADC is effectively disabled (ADDIS will automatically be reset once ADEN=0).

364/1202 RM0471 Rev 5

RM0471

ADEN

ADRDY t

STAB

ADDIS

ADC state

OFF Startup by S/W by H/W

Analog-to-digital converter (ADC)

Figure 38. Enabling / disabling the ADC

RDY Converting CH RDY

REQ

-OF

OFF

MSv30264V2

Note:

The software is allowed to write the RCC control bits to configure and enable the ADC clock

(refer to RCC Section), the DIFSEL[i] control bits in the ADC_DIFSEL register and the control bits ADCAL and ADEN in the ADC_CR register, only if the ADC is disabled (ADEN must be equal to 0).

The software is then allowed to write the control bits ADSTART, JADSTART and ADDIS of the ADC_CR register only if the ADC is enabled and there is no pending request to disable the ADC (ADEN must be equal to 1 and ADDIS to 0).

For all the other control bits of the ADC_CFGR, ADC_SMPRx, ADC_SQRy, ADC_JDRy,

ADC_OFRy, ADC_OFCHRy and ADC_IER registers:

 For control bits related to configuration of regular conversions, the software is allowed to write them only if the ADC is enabled (ADEN=1) and if there is no regular conversion ongoing (ADSTART must be equal to 0).

 For control bits related to configuration of injected conversions, the software is allowed to write them only if the ADC is enabled (ADEN=1) and if there is no injected conversion ongoing (JADSTART must be equal to 0).

The software is allowed to write the ADSTP or JADSTP control bits of the ADC_CR register only if the ADC is enabled, possibly converting, and if there is no pending request to disable the ADC (ADSTART or JADSTART must be equal to 1 and ADDIS to 0).

The software can write the register ADC_JSQR at any time, when the ADC is enabled

(ADEN=1). Refer to Section 15.5.16: ADC injected sequence register (ADC_JSQR)

for additional details.

There is no hardware protection to prevent these forbidden write accesses and ADC behavior may become in an unknown state. To recover from this situation, the ADC must be disabled (clear ADEN=0 as well as all the bits of ADC_CR register).

RM0471 Rev 5 365/1202

443

Analog-to-digital converter (ADC) RM0471

Note:

There are up to 14 multiplexed channels:

 11 analog inputs coming from GPIO pads

 The ADC is connected to the following internal analog inputs:

– The internal reference voltage (V

REFINT

) is connected to ADC1_INP0.

– The internal temperature sensor (V

) is connected to ADC1_INP17.

– The V

BAT

monitoring channel (V

BAT

/3) is connected to ADC1_INP18.

To convert one of the internal analog channels, the corresponding analog sources must first be enabled by programming bits VREFEN, CH17SEL or CH18SEL in the ADCx_CCR registers.

It is possible to organize the conversions in two groups: regular and injected. A group consists of a sequence of conversions that can be done on any channel and in any order.

For instance, it is possible to implement the conversion sequence in the following order:

ADC1_INP/INN5, ADC1_INP/INN8, ADC1_INP/INN7, ADC1_INN/INP7, ADC1_INP/INN0,

ADC1_INP/INN7, ADC1_INP/INN7, ADC1_INP/INN15.

 A regular group is composed of up to 16 conversions. The regular channels and their order in the conversion sequence must be selected in the ADC_SQRy registers. The total number of conversions in the regular group must be written in the L[3:0] bits in the

ADC_SQR1 register.

 An injected group is composed of up to 4 conversions. The injected channels and their order in the conversion sequence must be selected in the ADC_JSQR register.

The total number of conversions in the injected group must be written in the L[1:0] bits in the ADC_JSQR register.

ADC_SQRy registers must not be modified while regular conversions can occur. For this, the ADC regular conversions must be first stopped by writing ADSTP=1 (refer to

Section 15.3.17: Stopping an ongoing conversion (ADSTP, JADSTP) ).

The software is allowed to modify on-the-fly the ADC_JSQR register when JADSTART is set to 1 (injected conversions ongoing) only when the context queue is enabled (JQDIS=0 in

ADC_CFGR register). Refer to Section 15.3.21: Queue of context for injected conversions

366/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Before starting a conversion, the ADC must establish a direct connection between the voltage source under measurement and the embedded sampling capacitor of the ADC. This sampling time must be enough for the input voltage source to charge the embedded capacitor to the input voltage level.

Each channel can be sampled with a different sampling time which is programmable using the SMP[2:0] bits in the ADC_SMPR1 and ADC registers. It is therefore possible to select among the following sampling time values:

 SMP = 000: 2.5 ADC clock cycles

 SMP = 001: 6.5 ADC clock cycles

 SMP = 010: 12.5 ADC clock cycles

 SMP = 011: 24.5 ADC clock cycles

 SMP = 100: 47.5 ADC clock cycles

 SMP = 101: 92.5 ADC clock cycles

 SMP = 110: 247.5 ADC clock cycles

 SMP = 111: 640.5 ADC clock cycles

The total conversion time is calculated as follows:

CONV

= Sampling time + 12.5 ADC clock cycles

Example:

With F

ADC_CLK

= 30 MHz and a sampling time of 2.5 ADC clock cycles:

CONV

= (2.5 + 12.5) ADC clock cycles = 15 ADC clock cycles = 500 ns

The ADC notifies the end of the sampling phase by setting the status bit EOSMP (only for regular conversion).

Constraints on the sampling time

For each channel, SMP[2:0] bits must be programmed to respect a minimum sampling time as specified in the ADC characteristics section of the datasheets.

I/O analog switches voltage booster

The I/O analog switches resistance increases when the V

DDA

voltage is too low. This requires to have the sampling time adapted accordingly (cf datasheet for electrical characteristics). This resistance can be minimized at low V

DDA

by enabling an internal voltage booster with BOOSTEN bit in the SYSCFG_CFGR1 register.

15.3.13 Single conversion mode (CONT=0)

In Single conversion mode, the ADC performs once all the conversions of the channels.

This mode is started with the CONT bit at 0 by either:

 Setting the ADSTART bit in the ADC_CR register (for a regular channel)

 Setting the JADSTART bit in the ADC_CR register (for an injected channel)

 External hardware trigger event (for a regular or injected channel)

RM0471 Rev 5 367/1202

443

Analog-to-digital converter (ADC) RM0471

Note:

Inside the regular sequence, after each conversion is complete:

 The converted data are stored into the 16-bit ADC_DR register

 The EOC (end of regular conversion) flag is set

 An interrupt is generated if the EOCIE bit is set

Inside the injected sequence, after each conversion is complete:

 The converted data are stored into one of the four 16-bit ADC_JDRy registers

 The JEOC (end of injected conversion) flag is set

 An interrupt is generated if the JEOCIE bit is set

After the regular sequence is complete:

 The EOS (end of regular sequence) flag is set

 An interrupt is generated if the EOSIE bit is set

After the injected sequence is complete:

 The JEOS (end of injected sequence) flag is set

 An interrupt is generated if the JEOSIE bit is set

Then the ADC stops until a new external regular or injected trigger occurs or until bit

ADSTART or JADSTART is set again.

To convert a single channel, program a sequence with a length of 1.

15.3.14 Continuous conversion mode (CONT=1)

Note:

This mode applies to regular channels only.

In continuous conversion mode, when a software or hardware regular trigger event occurs, the ADC performs once all the regular conversions of the channels and then automatically restarts and continuously converts each conversions of the sequence. This mode is started with the CONT bit at 1 either by external trigger or by setting the ADSTART bit in the

ADC_CR register.

Inside the regular sequence, after each conversion is complete:

 The converted data are stored into the 16-bit ADC_DR register

 The EOC (end of conversion) flag is set

 An interrupt is generated if the EOCIE bit is set

After the sequence of conversions is complete:

 The EOS (end of sequence) flag is set

 An interrupt is generated if the EOSIE bit is set

Then, a new sequence restarts immediately and the ADC continuously repeats the conversion sequence.

To convert a single channel, program a sequence with a length of 1.

It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1.

Injected channels cannot be converted continuously. The only exception is when an injected channel is configured to be converted automatically after regular channels in continuous mode (using JAUTO bit), refer to Auto-injection mode section)

.

368/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Note:

Software starts ADC regular conversions by setting ADSTART=1.

When ADSTART is set, the conversion starts:

 Immediately: if EXTEN[1:0] = 00 (software trigger)

 At the next active edge of the selected regular hardware trigger: if EXTEN[1:0] is not equal to 00

Software starts ADC injected conversions by setting JADSTART=1.

When JADSTART is set, the conversion starts:

 Immediately, if JEXTEN[1:0] = 00 (software trigger)

 At the next active edge of the selected injected hardware trigger: if JEXTEN[1:0] is not equal to 00

In auto-injection mode (JAUTO=1), use ADSTART bit to start the regular conversions followed by the auto-injected conversions (JADSTART must be kept cleared).

ADSTART and JADSTART also provide information on whether any ADC operation is currently ongoing. It is possible to re-configure the ADC while ADSTART=0 and

JADSTART=0 are both true, indicating that the ADC is idle.

ADSTART is cleared by hardware:

 In single mode with software regular trigger (CONT=0, EXTSEL=0x0)

– At any end of regular conversion sequence (EOS assertion) or at any end of subgroup processing if DISCEN = 1

 In all cases (CONT=x, EXTSEL=x)

– After execution of the ADSTP procedure asserted by the software.

In continuous mode (CONT=1), ADSTART is not cleared by hardware with the assertion of

EOS because the sequence is automatically relaunched.

When a hardware trigger is selected in single mode (CONT=0 and EXTSEL ≠ 0x00),

ADSTART is not cleared by hardware with the assertion of EOS to help the software which does not need to reset ADSTART again for the next hardware trigger event. This ensures that no further hardware triggers are missed.

JADSTART is cleared by hardware:

 In single mode with software injected trigger (JEXTSEL = 0x0)

– At any end of injected conversion sequence (JEOS assertion) or at any end of subgroup processing if JDISCEN = 1

 in all cases (JEXTSEL=x)

– After execution of the JADSTP procedure asserted by the software.

When the software trigger is selected, ADSTART bit should not be set if the EOC flag is still high.

RM0471 Rev 5 369/1202

443

Analog-to-digital converter (ADC) RM0471

The elapsed time between the start of a conversion and the end of conversion is the sum of the configured sampling time plus the successive approximation time depending on data resolution:

CONV

= T

SMPL

+ T

SAR

= [2.5

|min

+ 12.5

|12bit

] x T

ADC_CLK

CONV

= T

SMPL

+ T

SAR

= 83.33

|min

+ 416.67

|12bit

= 500.0 ns (for F

ADC_CLK

= 30 MHz)

Figure 39. Analog to digital conversion time

ADC state RDY

Analog channel

Sampling Ch(N)

Ch(N)

Converting Ch(N) Sampling Ch(N+1)

Ch(N+1)

Internal S/H Sample AIN(N) t

SMPL

(1)

Hold AIN(N) t

SAR

(2)

Sample AIN(N+1)

ADSTART

Set by

EOSMP

Set by

Cleared by SW

Set by

Cleared by SW

EOC

ADC_DR Data N-1

Indicative timings

Data N

MS30532V1

1. T

SMPL

depends on SMP[2:0].

2. T

SAR

depends on RES[2:0].

15.3.17 Stopping an ongoing conversion (ADSTP, JADSTP)

The software can decide to stop regular conversions ongoing by setting ADSTP=1 and injected conversions ongoing by setting JADSTP=1.

Stopping conversions will reset the ongoing ADC operation. Then the ADC can be reconfigured (ex: changing the channel selection or the trigger) ready for a new operation.

Note that it is possible to stop injected conversions while regular conversions are still operating and vice-versa. This allows, for instance, re-configuration of the injected conversion sequence and triggers while regular conversions are still operating (and viceversa).

When the ADSTP bit is set by software, any ongoing regular conversion is aborted with partial result discarded (ADC_DR register is not updated with the current conversion).

When the JADSTP bit is set by software, any ongoing injected conversion is aborted with partial result discarded (ADC_JDRy register is not updated with the current conversion).

The scan sequence is also aborted and reset (meaning that relaunching the ADC would restart a new sequence).

Once this procedure is complete, bits ADSTP/ADSTART (in case of regular conversion), or

JADSTP/JADSTART (in case of injected conversion) are cleared by hardware and the software must poll ADSTART (or JADSTART) until the bit is reset before assuming the ADC is completely stopped.

370/1202 RM0471 Rev 5

RM0471

Note:

Analog-to-digital converter (ADC)

In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected conversions (JADSTP must not be used).

Figure 40. Stopping ongoing regular conversions

ADC state RDY

Trigger

Sample

Ch(N-1)

Convert

Ch(N-1)

Trigger

RDY

Sample

Ch(N)

C RDY

JADSTART

ADSTART

Cleared by

HW REGULAR CONVERSIONS ongoing

Cleared by

(software is not allowed to configure regular conversions selection and triggers)

ADSTP

Set by

Cleared by

ADC_DR

Data N-2 Data N-1

MSv30533V2

Figure 41. Stopping ongoing regular and injected conversions

Regular trigger Injected trigger Regular trigger

ADC state

RDY

Sample

Ch(N-1)

Convert

Ch(N-1)

RDY

Sample

Ch(M)

C RDY Sampl RDY

JADSTART

Set by

SW INJECTED CONVERSIONS ongoing

Cleared by HW

(software is not allowed to configure injected conversions selection and triggers)

Set by

Cleared

JADSTP SW by HW

ADC_JDR

DATA M-1

ADSTART

Set by

SW REGULAR CONVERSIONS ongoing

Cleared by HW

(software is not allowed to configure regular conversions selection and triggers)

ADSTP

Set by

Cleared by HW

ADC_DR DATA N-2 DATA N-1

MS30534V1

RM0471 Rev 5 371/1202

443

Analog-to-digital converter (ADC) RM0471

15.3.18 Conversion on external trigger and trigger polarity

(EXTSEL, EXTEN, JEXTSEL, JEXTEN)

A conversion or a sequence of conversions can be triggered either by software or by an external event (e.g. timer capture, input pins). If the EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from 0b00, then external events are able to trigger a conversion with the selected polarity.

When the Injected Queue is enabled (bit JQDIS=0), injected software triggers are not possible.

The regular trigger selection is effective once software has set bit ADSTART=1 and the injected trigger selection is effective once software has set bit JADSTART=1.

Any hardware triggers which occur while a conversion is ongoing are ignored.

 If bit ADSTART=0, any regular hardware triggers which occur are ignored.

 If bit JADSTART=0, any injected hardware triggers which occur are ignored.

Table 65 provides the correspondence between the EXTEN[1:0] and JEXTEN[1:0] values

and the trigger polarity.

Table 65. Configuring the trigger polarity for regular external triggers

EXTEN[1:0] Source

Hardware Trigger detection disabled, software trigger detection enabled

Hardware Trigger with detection on the rising edge

Hardware Trigger with detection on the falling edge

Hardware Trigger with detection on both the rising and falling edges

Note:

The polarity of the regular trigger cannot be changed on-the-fly.

Table 66. Configuring the trigger polarity for injected external triggers

JEXTEN[1:0] Source

– If JQDIS=1 (Queue disabled): Hardware trigger detection disabled, software trigger detection enabled

– If JQDIS=0 (Queue enabled), Hardware and software trigger detection disabled

Hardware Trigger with detection on the rising edge

Hardware Trigger with detection on the falling edge

Hardware Trigger with detection on both the rising and falling edges

The polarity of the injected trigger can be anticipated and changed on-the-fly when the

queue is enabled (JQDIS=0). Refer to Section 15.3.21: Queue of context for injected conversions .

The EXTSEL and JEXTSEL control bits select which out of 16 possible events can trigger conversion for the regular and injected groups.

A regular group conversion can be interrupted by an injected trigger.

372/1202 RM0471 Rev 5

Name

JEXT0

JEXT1

JEXT2

JEXT3

JEXT4

JEXT5

JEXT6

JEXT8

JEXT14

JEXT15

RM0471 Analog-to-digital converter (ADC)

Note:

Name

EXT0

EXT1

EXT2

EXT3

EXT4

EXT5

EXT6

EXT9

EXT10

EXT11

EXT13

EXT14

The regular trigger selection cannot be changed on-the-fly.

The injected trigger selection can be anticipated and changed on-the-fly. Refer to

Section 15.3.21: Queue of context for injected conversions on page 376

Table 67 to Table 68 give all the possible external triggers of the three ADCs for regular and

injected conversions.

Table 67. ADC1 - External triggers for regular channels

Source Type

TIM1_CC1

TIM1_CC2

TIM1_CC3

TIM2_CC2

EXTI Line 11

TIM1_TRGO

TIM1_TRGO2

TIM2_TRGO

Internal signal from on-chip timers

External pin

Internal signal from on-chip timers

EXTSEL[3:0]

0000

0001

0010

0011

0100

0101

0110

1001

1010

1011

1101

1110

Table 68. ADC1 - External trigger for injected channels

Source Type

TIM1_TRGO

TIM1_CC4

TIM2_TRGO

TIM2_CH1

EXTI Line 15

TIM1_TRGO2

Internal signal from on-chip timers

External pin

Internal signal from on-chip timers

JEXTSEL[3:0]

0000

0001

0010

0011

0100

0101

0110

1000

1110

1111

RM0471 Rev 5 373/1202

443

Analog-to-digital converter (ADC) RM0471

15.3.19 Injected channel management

Note:

Triggered injection mode

To use triggered injection, the JAUTO bit in the ADC_CFGR register must be cleared.

Start the conversion of a group of regular channels either by an external trigger or by setting the ADSTART bit in the ADC_CR register.

2. If an external injected trigger occurs, or if the JADSTART bit in the ADC_CR register is set during the conversion of a regular group of channels, the current conversion is reset and the injected channel sequence switches are launched (all the injected channels are converted once).

3. Then, the regular conversion of the regular group of channels is resumed from the last interrupted regular conversion.

4. If a regular event occurs during an injected conversion, the injected conversion is not interrupted but the regular sequence is executed at the end of the injected sequence.

Figure 42

shows the corresponding timing diagram.

When using triggered injection, one must ensure that the interval between trigger events is longer than the injection sequence. For instance, if the sequence length is 30 ADC clock cycles (that is two conversions with a sampling time of 2.5 clock periods), the minimum interval between triggers must be 31 ADC clock cycles.

Auto-injection mode

If the JAUTO bit in the ADC_CFGR register is set, then the channels in the injected group are automatically converted after the regular group of channels. This can be used to convert a sequence of up to 20 conversions programmed in the ADC_SQRy and ADC_JSQR registers.

In this mode, the ADSTART bit in the ADC_CR register must be set to start regular conversions, followed by injected conversions (JADSTART must be kept cleared). Setting the ADSTP bit aborts both regular and injected conversions (JADSTP bit must not be used).

In this mode, external trigger on injected channels must be disabled.

If the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected channels are continuously converted.

It is not possible to use both the auto-injected and discontinuous modes simultaneously.

When the DMA is used for exporting regular sequencer’s data in JAUTO mode, it is necessary to program it in circular mode (CIRC bit set in DMA_CCRx register). If the CIRC bit is reset (single-shot mode), the JAUTO sequence will be stopped upon DMA Transfer

Complete event.

374/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Figure 42. Injected conversion latency

ADCCLK

Injection event

Reset ADC max. latency

(1)

SOC

1. The maximum latency value can be found in the electrical characteristics of the device datasheet.

ai16049b

Regular group mode

This mode is enabled by setting the DISCEN bit in the ADC_CFGR register.

It is used to convert a short sequence (subgroup) of n conversions (n ≤ 8) that is part of the sequence of conversions selected in the ADC_SQRy registers. The value of n is specified by writing to the DISCNUM[2:0] bits in the ADC_CFGR register.

When an external trigger occurs, it starts the next n conversions selected in the ADC_SQRy registers until all the conversions in the sequence are done. The total sequence length is defined by the L[3:0] bits in the ADC_SQR1 register.

Example:

 DISCEN=1, n=3, channels to be converted = 1, 2, 3, 6, 7, 8, 9, 10, 11

– 1st trigger: channels converted are 1, 2, 3 (an EOC event is generated at each conversion).

– 2nd trigger: channels converted are 6, 7, 8 (an EOC event is generated at each conversion).

– 3rd trigger: channels converted are 9, 10, 11 (an EOC event is generated at each conversion) and an EOS event is generated after the conversion of channel 11.

– 4th trigger: channels converted are 1, 2, 3 (an EOC event is generated at each conversion).

– ...

 DISCEN=0, channels to be converted = 1, 2, 3, 6, 7, 8, 9, 10,11

– 1st trigger: the complete sequence is converted: channel 1, then 2, 3, 6, 7, 8, 9, 10 and 11. Each conversion generates an EOC event and the last one also generates an EOS event.

– All the next trigger events will relaunch the complete sequence.

RM0471 Rev 5 375/1202

443

Analog-to-digital converter (ADC) RM0471

Note:

The channel numbers referred to in the above example might not be available on all microcontrollers.

When a regular group is converted in discontinuous mode, no rollover occurs (the last subgroup of the sequence can have less than n conversions).

When all subgroups are converted, the next trigger starts the conversion of the first subgroup. In the example above, the 4th trigger reconverts the channels 1, 2 and 3 in the

1st subgroup.

It is not possible to have both discontinuous mode and continuous mode enabled. In this case (if DISCEN=1, CONT=1), the ADC behaves as if continuous mode was disabled.

Injected group mode

This mode is enabled by setting the JDISCEN bit in the ADC_CFGR register. It converts the sequence selected in the ADC_JSQR register, channel by channel, after an external injected trigger event. This is equivalent to discontinuous mode for regular channels where

‘n’ is fixed to 1.

When an external trigger occurs, it starts the next channel conversions selected in the

ADC_JSQR registers until all the conversions in the sequence are done. The total sequence length is defined by the JL[1:0] bits in the ADC_JSQR register.

Example:

 JDISCEN=1, channels to be converted = 1, 2, 3

– 1st trigger: channel 1 converted (a JEOC event is generated)

– 2nd trigger: channel 2 converted (a JEOC event is generated)

– 3rd trigger: channel 3 converted and a JEOC event + a JEOS event are generated

– ...

The channel numbers referred to in the above example might not be available on all microcontrollers.

When all injected channels have been converted, the next trigger starts the conversion of the first injected channel. In the example above, the 4th trigger reconverts the 1st injected channel 1.

It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.

15.3.21 Queue of context for injected conversions

A queue of context is implemented to anticipate up to 2 contexts for the next injected sequence of conversions. JQDIS bit of ADC_CFGR register must be reset to enable this feature. Only hardware-triggered conversions are possible when the context queue is enabled.

This context consists of:

 Configuration of the injected triggers (bits JEXTEN[1:0] and JEXTSEL bits in

ADC_JSQR register)

 Definition of the injected sequence (bits JSQx[4:0] and JL[1:0] in ADC_JSQR register)

376/1202 RM0471 Rev 5

RM0471

Note:

Analog-to-digital converter (ADC)

All the parameters of the context are defined into a single register ADC_JSQR and this register implements a queue of 2 buffers, allowing the bufferization of up to 2 sets of parameters:

 The JSQR register can be written at any moment even when injected conversions are ongoing.

 Each data written into the JSQR register is stored into the Queue of context.

 At the beginning, the Queue is empty and the first write access into the JSQR register immediately changes the context and the ADC is ready to receive injected triggers.

 Once an injected sequence is complete, the Queue is consumed and the context changes according to the next JSQR parameters stored in the Queue. This new context is applied for the next injected sequence of conversions.

 A Queue overflow occurs when writing into register JSQR while the Queue is full. This overflow is signaled by the assertion of the flag JQOVF. When an overflow occurs, the write access of JSQR register which has created the overflow is ignored and the queue of context is unchanged. An interrupt can be generated if bit JQOVFIE is set.

 Two possible behaviors are possible when the Queue becomes empty, depending on the value of the control bit JQM of register ADC_CFGR:

– If JQM=0, the Queue is empty just after enabling the ADC, but then it can never be empty during run operations: the Queue always maintains the last active context and any further valid start of injected sequence will be served according to the last active context.

– If JQM=1, the Queue can be empty after the end of an injected sequence or if the

Queue is flushed. When this occurs, there is no more context in the queue and hardware triggers are disabled. Therefore, any further hardware injected triggers are ignored until the software re-writes a new injected context into JSQR register.

 Reading JSQR register returns the current JSQR context which is active at that moment. When the JSQR context is empty, JSQR is read as 0x0000.

 The Queue is flushed when stopping injected conversions by setting JADSTP=1 or when disabling the ADC by setting ADDIS=1:

– If JQM=0, the Queue is maintained with the last active context.

– If JQM=1, the Queue becomes empty and triggers are ignored.

When configured in discontinuous mode (bit JDISCEN=1), only the last trigger of the injected sequence changes the context and consumes the Queue.The 1 st trigger only consumes the queue but others are still valid triggers as shown by the discontinuous mode example below (length = 3 for both contexts):

 1 st

trigger, discontinuous. Sequence 1: context 1 consumed, 1 st

conversion carried out

 2 nd trigger, disc. Sequence 1: 2 nd conversion.

 3 rd

trigger, discontinuous. Sequence 1: 3 rd

conversion.

 4 th trigger, discontinuous. Sequence 2: context 2 consumed, 1 st conversion carried out.

 5 th

trigger, discontinuous. Sequence 2: 2 nd

conversion.

 6 th trigger, discontinuous. Sequence 2: 3 rd conversion.

RM0471 Rev 5 377/1202

443

Analog-to-digital converter (ADC) RM0471

Behavior when changing the trigger or sequence context

The

Figure 43

and

Figure 44 show the behavior of the context Queue when changing the

sequence or the triggers.

Write JSQR

Figure 43. Example of JSQR queue of context (sequence change)

P1 P2 P3

JSQR queue

EMPTY P1 P1,P2 P2 P2,P3 P3

Trigger 1

ADC J context

(returned by reading

JQSR)

ADC state

EMPTY P1 P2 P3

RDY Conversion1 Conversion2 Conversion3 RDY Conversion1 RDY

MS30536V2

1. Parameters:

P1: sequence of 3 conversions, hardware trigger 1

P2: sequence of 1 conversion, hardware trigger 1

P3: sequence of 4 conversions, hardware trigger 1

Figure 44. Example of JSQR queue of context (trigger change)

P1 P2 P3

Write JSQR

JSQR queue EMPTY P1 P1,P2 P2 P2,P3

Ignored

Trigger 1

Trigger 2

ADC J context

(returned by reading

JQSR)

ADC state

EMPTY P1

RDY

Ignored

Conversion1 Conversion2

RDY

Conversion1 RDY

MS30537V2

1. Parameters:

P1: sequence of 2 conversions, hardware trigger 1

P2: sequence of 1 conversion, hardware trigger 2

P3: sequence of 4 conversions, hardware trigger 1

378/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Queue of context: Behavior when a queue overflow occurs

The

Figure 45

and

Figure 46 show the behavior of the context Queue if an overflow occurs

before or during a conversion.

Figure 45. Example of JSQR queue of context with overflow before conversion

P1 P2 P3

=> Overflow, ignored

Write JSQR

JSQR queue

EMPTY P1 P1, P2 P2 P2, P4

Cleared by SW

JQOVF

Trigger 1

Trigger 2

ADC

J context

(returned by reading JQSR)

EMPTY

ADC state

RDY

JEOS

Conversion1 Conversion2

RDY Conversion1

MS30538V2

1. Parameters:

P1: sequence of 2 conversions, hardware trigger 1

P2: sequence of 1 conversion, hardware trigger 2

P3: sequence of 3 conversions, hardware trigger 1

P4: sequence of 4 conversions, hardware trigger 1

Figure 46. Example of JSQR queue of context with overflow during conversion

=> Overflow, ignored

Write JSQR

JSQR queue

EMPTY

JQOVF

Trigger 1

Trigger 2

ADC

J context

(returned by reading JQSR)

EMPTY

ADC state

RDY

JEOS

P1, P2

Conversion1 Conversion2

P2 P2, P4

Cleared by SW

RDY Conversion1

MS30539V2

1. Parameters:

P1: sequence of 2 conversions, hardware trigger 1

P2: sequence of 1 conversion, hardware trigger 2

P3: sequence of 3 conversions, hardware trigger 1

P4: sequence of 4 conversions, hardware trigger 1

RM0471 Rev 5 379/1202

443

Analog-to-digital converter (ADC) RM0471

It is recommended to manage the queue overflows as described below:

 After each P context write into JSQR register, flag JQOVF shows if the write has been ignored or not (an interrupt can be generated).

 Avoid Queue overflows by writing the third context (P3) only once the flag JEOS of the previous context P2 has been set. This ensures that the previous context has been consumed and that the queue is not full.

Queue of context: Behavior when the queue becomes empty

Figure 47

and

Figure 48 show the behavior of the context Queue when the Queue becomes

empty in both cases JQM=0 or 1.

Figure 47. Example of JSQR queue of context with empty queue (case JQM=0)

Write JSQR

JSQR queue

EMPTY

P1, P2

Trigger 1

ADC J context

(returned by reading JQSR)

EMPTY P1

ADC state RDY Conversion1

The queue is not empty and maintains P2 because JQM=0

RDY Conversion1 RDY Conversion1

RDY Conversion1

Queue not empty

(P3 maintained)

RDY Conv

MS30540V3

1. Parameters:

P1: sequence of 1 conversion, hardware trigger 1

P2: sequence of 1 conversion, hardware trigger 1

P3: sequence of 1 conversion, hardware trigger 1

Note: When writing P3, the context changes immediately. However, because of internal resynchronization, there is a latency and if a trigger occurs just after or before writing P3, it can happen that the conversion is launched considering the context P2. To avoid this situation, the user must ensure that there is no ADC trigger happening when writing a new context that applies immediately.

380/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Figure 48. Example of JSQR queue of context with empty queue (case JQM=1)

P1 P2

Queue becomes empty and triggers are ignored because JQM=1

Write JSQR

JSQR queue

EMPTY P1

Trigger 1

ADC

J context

EMPTY P1

(returned by reading JQSR)

ADC state RDY

P1,P2

Conversion1 RDY

Conversion1

EMPTY

Ignored

EMPTY (0x0000)

RDY

Conversion1

EMPTY

Ignored

EMPTY

RDY

MS30541V1

1. Parameters:

P1: sequence of 1 conversion, hardware trigger 1

P2: sequence of 1 conversion, hardware trigger 1

P3: sequence of 1 conversion, hardware trigger 1

Flushing the queue of context

The figures below show the behavior of the context Queue in various situations when the queue is flushed.

Figure 49. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).

Case when JADSTP occurs during an ongoing conversion.

Queue is flushed and maintains the last active context

(P2 is lost)

Write JSQR

JSQR queue EMPTY

JADSTP

JADSTART

P1 P1, P2

Set by S/W

Reset by H/W

Set by S/W

Trigger 1

ADC J context EMPTY

(returned by reading JSQR)

ADC state

RDY

STP

RDY

Conversion1 RDY

MS30544V2

1. Parameters:

P1: sequence of 1 conversion, hardware trigger 1

P2: sequence of 1 conversion, hardware trigger 1

P3: sequence of 1 conversion, hardware trigger 1

RM0471 Rev 5 381/1202

443

Analog-to-digital converter (ADC) RM0471

Figure 50. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).

Case when JADSTP occurs during an ongoing conversion and a new trigger occurs.

Write JSQR

JSQR queue

EMPTY P1

JADSTP

JADSTART

Queue is flushed and maintains

the last active context

P1, P2

Set by S/W

(P2 is lost)

Reset by H/W

Reset by H/W Set

P3 by S/W

P1, P3

Trigger 1

ADC J context

EMPTY P1

(returned by reading JSQR)

ADC state RDY Conv1 STP

(Aborted)

RDY

Conversion1 RDY Conversion1 RDY

MS30543V1

1. Parameters:

P1: sequence of 1 conversion, hardware trigger 1

P2: sequence of 1 conversion, hardware trigger 1

P3: sequence of 1 conversion, hardware trigger 1

Figure 51. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).

Case when JADSTP occurs outside an ongoing conversion

the last active context

(P2 is lost)

Write JSQR

P1 P2 P3

JSQR queue EMPTY P1

JADSTP

JADSTART

P1, P2

Set by S/W

Reset by H/W

Set by S/W

Trigger 1

ADC J context EMPTY P1 P3

ADC state RDY STP RDY Conversion1 RDY

MS30544V1

1. Parameters:

P1: sequence of 1 conversion, hardware trigger 1

P2: sequence of 1 conversion, hardware trigger 1

P3: sequence of 1 conversion, hardware trigger 1

382/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Figure 52. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1)

P1 P2

Queue is flushed and

becomes empty (P2 is lost)

Write JSQR

JSQR queue EMPTY P1 P1, P2

Set by S/W

P3 EMPTY

JADSTP

JADSTART

Reset by H/W

EMPTY

Reset by H/W

Set by S/W

Ignored

Trigger 1

ADC J context EMPTY P1

(returned by reading JSQR)

EMPTY (0x0000) P3 EMPTY

ADC state RDY Conv1

(Aborted)

STP RDY Conversion1

1. Parameters:

P1: sequence of 1 conversion, hardware trigger 1

P2: sequence of 1 conversion, hardware trigger 1

P3: sequence of 1 conversion, hardware trigger 1

Figure 53. Flushing JSQR queue of context by setting ADDIS=1 (JQM=0)

RDY

MS30545V1

Queue is flushed and maintains

the last active context

(P2 which was not consumed is lost)

JSQR queue

ADDIS

P1, P2

Set by S/W

ADC J context P1

(returned by reading JSQR)

ADC state RDY

REQ-OFF

Reset by H/W

OFF

MS30546V1

1. Parameters:

P1: sequence of 1 conversion, hardware trigger 1

P2: sequence of 1 conversion, hardware trigger 1

P3: sequence of 1 conversion, hardware trigger 1

RM0471 Rev 5 383/1202

443

Analog-to-digital converter (ADC) RM0471

Figure 54. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1)

Queue is flushed and beomes empty

(JSQR is read as 0x0000)

JSQR queue

ADDIS

P1, P2

Set by S/W

EMPTY

Reset by H/W

ADC J context P1

(returned by reading JSQR)

ADC state RDY

EMPTY (0x0000)

REQ-OFF OFF

MS30547V1

1. Parameters:

P1: sequence of 1 conversion, hardware trigger 1

P2: sequence of 1 conversion, hardware trigger 1

P3: sequence of 1 conversion, hardware trigger 1

Queue of context: Starting the ADC with an empty queue

The following procedure must be followed to start ADC operation with an empty queue, in case the first context is not known at the time the ADC is initialized. This procedure is only applicable when JQM bit is reset:

5. Write a dummy JSQR with JEXTEN[1:0] not equal to 00 (otherwise triggering a software conversion)

8. Wait until JADSTART is reset

Disabling the queue

It is possible to disable the queue by setting bit JQDIS=1 into the ADC_CFGR register.

It is possible to perform faster conversion by reducing the ADC resolution.

The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the control bits RES[1:0].

Figure 59

, Figure 60 , Figure 61

and

Figure 62

show the conversion result format with respect to the resolution as well as to the data alignment.

Lower resolution allows faster conversion time for applications where high-data precision is not required. It reduces the conversion time spent by the successive approximation steps according to

Table 69 .

384/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

RES

(bits)

Table 69. T

SAR

timings depending on resolution

SAR

(ADC clock cycles) F

SAR

ADC

(ns) at

= 30 MHz

CONV

(ADC clock cycles)

(with Sampling Time=

2.5 ADC clock cycles)

12.5 ADC clock cycles

10.5 ADC clock cycles

8.5 ADC clock cycles

6.5 ADC clock cycles

416.67 ns

350.0 ns

203.33 ns

216.67 ns

15 ADC clock cycles

13 ADC clock cycles

11 ADC clock cycles

9 ADC clock cycles

CONV

(ns) at

ADC

= 30 MHz

500.0 ns

433.33 ns

366.67 ns

300.0 ns

15.3.23 End of conversion, end of sampling phase (EOC, JEOC, EOSMP)

The ADC notifies the application for each end of regular conversion (EOC) event and each injected conversion (JEOC) event.

The ADC sets the EOC flag as soon as a new regular conversion data is available in the

ADC_DR register. An interrupt can be generated if bit EOCIE is set. EOC flag is cleared by the software either by writing 1 to it or by reading ADC_DR.

The ADC sets the JEOC flag as soon as a new injected conversion data is available in one of the ADC_JDRy register. An interrupt can be generated if bit JEOCIE is set. JEOC flag is cleared by the software either by writing 1 to it or by reading the corresponding ADC_JDRy register.

The ADC also notifies the end of Sampling phase by setting the status bit EOSMP (for regular conversions only). EOSMP flag is cleared by software by writing 1 to it. An interrupt can be generated if bit EOSMPIE is set.

The ADC notifies the application for each end of regular sequence (EOS) and for each end of injected sequence (JEOS) event.

The ADC sets the EOS flag as soon as the last data of the regular conversion sequence is available in the ADC_DR register. An interrupt can be generated if bit EOSIE is set. EOS flag is cleared by the software either by writing 1 to it.

The ADC sets the JEOS flag as soon as the last data of the injected conversion sequence is complete. An interrupt can be generated if bit JEOSIE is set. JEOS flag is cleared by the software either by writing 1 to it.

RM0471 Rev 5 385/1202

443

Analog-to-digital converter (ADC) RM0471

hardware/software triggers)

Figure 55. Single conversions of a sequence, software trigger

ADSTART

(1)

EOC

EOS

ADC state

(2)

ADC_DR

RDY by SW

CH1 CH9

CH10 CH17

D9 D10 by HW

RDY

D17

CH1 CH9 CH10 CH17

D1 D9 D10

RDY

D17

Indicative timings

MS30549V1

1. EXTEN[1:0]=00, CONT=0

2. Channels selected = 1,9, 10, 17; AUTDLY=0.

Figure 56. Continuous conversion of a sequence, software trigger

ADCSTART

(1)

EOC

EOS

ADSTP

ADC state

(2)

READY CH1

ADC_DR

CH9

CH10 CH17 CH1

D9 D10 D17

CH9 CH10 STP

READY

CH1 CH9

D1 by SW by HW Indicative timings

MS30550V1

1. EXTEN[1:0]=00, CONT=1

2. Channels selected = 1,9, 10, 17; AUTDLY=0.

386/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Figure 57. Single conversions of a sequence, hardware trigger

ADSTART

EOC

EOS

TRGX

(1)

ADC state

(2)

ADC_DR by s/w

RDY by h/w

CH1 CH2

CH3

D2 triggered

CH4 READY CH1

D3 D4 ignored

CH2

CH3

Indicative timings

CH4

RDY

MS31013V2

1. TRGx (over-frequency) is selected as trigger source, EXTEN[1:0] = 01, CONT = 0

2. Channels selected = 1, 2, 3, 4; AUTDLY=0.

Figure 58. Continuous conversions of a sequence, hardware trigger

ADSTART

EOC

EOS

ADSTP

TRGx

(1)

ADC

(2)

ADC_DR

RDY by s/w

CH1 CH2

CH3

CH4

D3 by h/w triggered

CH1

CH2

CH3

D2 ignored

CH4

CH1

STOP RDY

Not in scale timings

MS31014V2

1. TRGx is selected as trigger source, EXTEN[1:0] = 10, CONT = 1

2. Channels selected = 1, 2, 3, 4; AUTDLY=0.

RM0471 Rev 5 387/1202

443

Analog-to-digital converter (ADC) RM0471

Note:

Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH,

ALIGN)

Data and alignment

At the end of each regular conversion channel (when EOC event occurs), the result of the converted data is stored into the ADC_DR data register which is 16 bits wide.

At the end of each injected conversion channel (when JEOC event occurs), the result of the converted data is stored into the corresponding ADC_JDRy data register which is 16 bits wide.

The ALIGN bit in the ADC_CFGR register selects the alignment of the data stored after

conversion. Data can be right- or left-aligned as shown in Figure 59 ,

Figure 60

Figure 61

and Figure 62

Special case: when left-aligned, the data are aligned on a half-word basis except when the resolution is set to 6-bit. In that case, the data are aligned on a byte basis as shown in

Figure 61

and

Figure 62 .

Left-alignment is not supported in oversampling mode. When ROVSE and/or JOVSE bit is set, the ALIGN bit value is ignored and the ADC only provides right-aligned data.

Offset

An offset y (y=1,2,3,4) can be applied to a channel by setting the bit OFFSETy_EN=1 into

ADC_OFRy register. The channel to which the offset will be applied is programmed into the bits OFFSETy_CH[4:0] of ADC_OFRy register. In this case, the converted value is decreased by the user-defined offset written in the bits OFFSETy[11:0]. The result may be a negative value so the read data is signed and the SEXT bit represents the extended sign value.

Offset correction is not supported in oversampling mode. When ROVSE and/or JOVSE bit is set, the value of the OFFSETy_EN bit in ADC_OFRy register is ignored (considered as reset).

Table 72 describes how the comparison is performed for all the possible resolutions for

analog watchdog 1.

Table 70. Offset computation versus data resolution

Subtraction between raw converted data and offset

Resolution

(bits

RES[1:0])

Raw converted

Data, left aligned

Offset

Result

00: 12-bit DATA[11:0] OFFSET[11:0]

01: 10-bit DATA[11:2],00 OFFSET[11:0]

Signed

12-bit data

Signed

10-bit data

Comments

The user must configure OFFSET[1:0] to “00”

388/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Resolution

(bits

RES[1:0])

Table 70. Offset computation versus data resolution (continued)

Subtraction between raw converted data and offset

Raw converted

Data, left aligned

Offset

Result Comments

10: 8-bit

11: 6-bit

DATA[11:4],00

DATA[11:6],00

0000

OFFSET[11:0]

Signed

8-bit data

Signed

6-bit data

The user must configure OFFSET[3:0] to “0000”

The user must configure OFFSET[5:0] to “000000”

When reading data from ADC_DR (regular channel) or from ADC_JDRy (injected channel, y=1,2,3,4) corresponding to the channel “i”:

 If one of the offsets is enabled (bit OFFSETy_EN=1) for the corresponding channel, the read data is signed.

 If none of the four offsets is enabled for this channel, the read data is not signed.

Figure 59

Figure 60 , Figure 61 and

Figure 62

show alignments for signed and unsigned data.

Figure 59. Right alignment (offset disabled, unsigned value)

12-bit data bit15

0 0 0 bit7

0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 bit0

10-bit data bit15

0 0 0 0 0 0 bit7

D9 D8 D7 D6 D5 D4 D3 D2 D1 bit0

8-bit data bit15

0 0 0 0 0 0 0 0 bit7

D7 D6 D5 D4 D3 D2 D1 bit0

6-bit data bit15

0 0 0 0 0 0 0 0 bit7

0 0 D5 D4 D3 D2 D1 bit0

MS31015V1

RM0471 Rev 5 389/1202

443

Analog-to-digital converter (ADC) RM0471

Figure 60. Right alignment (offset enabled, signed value)

12-bit data bit15

SEXT SEXT SEXT SEXT D11 D10 D9 D8 bit7

D7 D6 D5 D4 D3 D2 D1 bit0

10-bit data bit15

SEXT SEXT SEXT SEXT SEXT SEXT D9 D8 bit7

D7 D6 D5 D4 D3 D2 D1 bit0

8-bit data bit15 bit7

SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT D7 D6 D5 D4 D3 D2 D1 bit0

6-bit data bit15 bit7

SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT D5 D4 D3 D2 D1 bit0

MS31016V1

Figure 61. Left alignment (offset disabled, unsigned value)

12-bit data bit15

D11 D10 D9 D8 D7 D6 D5 D4 bit7

D3 D2 D1 D0 0 0

10-bit data bit15

D9 D8 D7 D6 D5 D4 D3 D2 bit7

D1 D0 0 0 0 0

0 bit0

8-bit data bit15

D7 D6 D5 D4 D3 D2 D1 D0 bit7

0 0 0 0 0 0 0 bit0

6-bit data bit15

0 0 0 0 0 0 0 0 bit7

D5 D4 D3 D2 D1 D0 0 bit0

MS31017V1

390/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Figure 62. Left alignment (offset enabled, signed value)

12-bit data bit15 bit7

SEXT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0

10-bit data bit15 bit7

SEXT D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0

0 bit0

8-bit data bit15 bit7

SEXT D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 bit0

6-bit data bit15 bit7

SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT D5 D4 D3 D2 D1 D0 bit0

MS31018V1

ADC overrun (OVR, OVRMOD)

The overrun flag (OSR) notifies of that a buffer overrun event occurred when the regular converted data has not been read (by the CPU or the DMA) before new converted data became available.

The OVR flag is set if the EOC flag is still 1 at the time when a new conversion completes.

An interrupt can be generated if bit OVRIE=1.

When an overrun condition occurs, the ADC is still operating and can continue converting unless the software decides to stop and reset the sequence by setting bit ADSTP=1.

OVR flag is cleared by software by writing 1 to it.

It is possible to configure if data is preserved or overwritten when an overrun event occurs by programming the control bit OVRMOD:

 OVRMOD=0: The overrun event preserves the data register from being overrun: the old data is maintained and the new conversion is discarded and lost. If OVR remains at

1, any further conversions will occur but the result data will be also discarded.

 OVRMOD=1: The data register is overwritten with the last conversion result and the previous unread data is lost. If OVR remains at 1, any further conversions will operate normally and the ADC_DR register will always contain the latest converted data.

RM0471 Rev 5 391/1202

443

Analog-to-digital converter (ADC)

Figure 63. Example of overrun (OVR)

RM0471

ADSTART (1)

EOC

EOS

OVR

ADSTP

TRGx (1)

ADC state (2) RDY

ADC_DR read access

ADC_DR

(OVRMOD=0)

ADC_DR

(OVRMOD=1) by s/w

Note:

CH1 CH2

CH3 CH4 CH5

Overun

CH6 CH7 STOP

D4 D5 D6

RDY by h/w triggered Indicative timings

MS31019V1

There is no overrun detection on the injected channels since there is a dedicated data register for each of the four injected channels.

Managing a sequence of conversions without using the DMA

If the conversions are slow enough, the conversion sequence can be handled by the software. In this case the software must use the EOC flag and its associated interrupt to handle each data. Each time a conversion is complete, EOC is set and the ADC_DR register can be read. OVRMOD should be configured to 0 to manage overrun events as an error.

Managing conversions without using the DMA and without overrun

It may be useful to let the ADC convert one or more channels without reading the data each time (if there is an analog watchdog for instance). In this case, the OVRMOD bit must be configured to 1 and OVR flag should be ignored by the software. An overrun event will not prevent the ADC from continuing to convert and the ADC_DR register will always contain the latest conversion.

Managing conversions using the DMA

Since converted channel values are stored into a unique data register, it is useful to use

DMA for conversion of more than one channel. This avoids the loss of the data already stored in the ADC_DR register.

When the DMA mode is enabled (DMAEN bit set to 1 in the ADC_CFGR register, a DMA request is generated after each conversion of a channel. This allows the transfer of the converted data from the ADC_DR register to the destination location selected by the software.

392/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Despite this, if an overrun occurs (OVR=1) because the DMA could not serve the DMA transfer request in time, the ADC stops generating DMA requests and the data corresponding to the new conversion is not transferred by the DMA. Which means that all the data transferred to the RAM can be considered as valid.

Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten

(refer to

Section : ADC overrun (OVR, OVRMOD) ).

The DMA transfer requests are blocked until the software clears the OVR bit.

Two different DMA modes are proposed depending on the application use and are configured with bit DMACFG of the ADC_CFGR register:

 DMA one shot mode (DMACFG=0).

This mode is suitable when the DMA is programmed to transfer a fixed number of data.

 DMA circular mode (DMACFG=1)

This mode is suitable when programming the DMA in circular mode.

DMA one shot mode (DMACFG=0)

In this mode, the ADC generates a DMA transfer request each time a new conversion data is available and stops generating DMA requests once the DMA has reached the last DMA transfer (when DMA_EOT interrupt occurs - refer to DMA paragraph) even if a conversion has been started again.

When the DMA transfer is complete (all the transfers configured in the DMA controller have been done):

 The content of the ADC data register is frozen.

 Any ongoing conversion is aborted with partial result discarded.

 No new DMA request is issued to the DMA controller. This avoids generating an overrun error if there are still conversions which are started.

 Scan sequence is stopped and reset.

 The DMA is stopped.

DMA circular mode (DMACFG=1)

In this mode, the ADC generates a DMA transfer request each time a new conversion data is available in the data register, even if the DMA has reached the last DMA transfer. This allows configuring the DMA in circular mode to handle a continuous analog input data stream.

15.3.27 Dynamic low-power features

Auto-delayed conversion mode (AUTDLY)

The ADC implements an auto-delayed conversion mode controlled by the AUTDLY configuration bit. Auto-delayed conversions are useful to simplify the software as well as to optimize performance of an application clocked at low frequency where there would be risk of encountering an ADC overrun.

When AUTDLY=1, a new conversion can start only if all the previous data of the same group has been treated:

 For a regular conversion: once the ADC_DR register has been read or if the EOC bit

has been cleared (see Figure 64 ).

 For an injected conversion: when the JEOS bit has been cleared (see

Figure 65

RM0471 Rev 5 393/1202

443

Analog-to-digital converter (ADC)

Note:

RM0471

This is a way to automatically adapt the speed of the ADC to the speed of the system which will read the data.

The delay is inserted after each regular conversion (whatever DISCEN=0 or 1) and after each sequence of injected conversions (whatever JDISCEN=0 or 1).

There is no delay inserted between each conversions of the injected sequence, except after the last one.

During a conversion, a hardware trigger event (for the same group of conversions) occurring during this delay is ignored.

This is not true for software triggers where it remains possible during this delay to set the bits ADSTART or JADSTART to restart a conversion: it is up to the software to read the data before launching a new conversion.

No delay is inserted between conversions of different groups (a regular conversion followed by an injected conversion or conversely):

 If an injected trigger occurs during the automatic delay of a regular conversion, the injected conversion starts immediately (see

Figure 65 ).

 Once the injected sequence is complete, the ADC waits for the delay (if not ended) of the previous regular conversion before launching a new regular conversion (see

Figure 67

The behavior is slightly different in auto-injected mode (JAUTO=1) where a new regular conversion can start only when the automatic delay of the previous injected sequence of conversion has ended (when JEOS has been cleared). This is to ensure that the software

can read all the data of a given sequence before starting a new sequence (see Figure 68

To stop a conversion in continuous auto-injection mode combined with autodelay mode

(JAUTO=1, CONT=1 and AUTDLY=1), follow the following procedure:

Wait until JEOS=1 (no more conversions are restarted)

4. Read the regular data.

If this procedure is not respected, a new regular sequence can restart if JEOS is cleared after ADSTP has been set.

In AUTDLY mode, a hardware regular trigger event is ignored if it occurs during an already ongoing regular sequence or during the delay that follows the last regular conversion of the sequence. It is however considered pending if it occurs after this delay, even if it occurs during an injected sequence of the delay that follows it. The conversion then starts at the end of the delay of the injected sequence.

In AUTDLY mode, a hardware injected trigger event is ignored if it occurs during an already ongoing injected sequence or during the delay that follows the last injected conversion of the sequence.

394/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Figure 64. AUTODLY=1, regular conversion in continuous mode, software trigger

ADSTART (1)

EOC

EOS

ADSTP

ADC_DR read access

RDY ADC state

ADC_DR

CH1 by SW

DLY

CH2 DLY CH3

D2 by HW

DLY

CH1 DLY STOP

RDY

Indicative timings

MS31020V1

1. AUTDLY=1

2. Regular configuration: EXTEN[1:0]=00 (SW trigger), CONT=1, CHANNELS = 1,2,3

3. Injected configuration DISABLED

Figure 65. AUTODLY=1, regular HW conversions interrupted by injected conversions

(DISCEN=0; JDISCEN=0)

Ignored

Not ignored

(occurs during injected sequence)

Regular trigger

ADC state

RDY CH1 regular

DLY

DLY (CH1)

CH2 DLY regular

DLY (CH2)

CH5 CH6 CH3 injected regular

DLY CH1 injected

DLY (CH3) regular

DLY

DLY (CH1)

CH2 regular

EOC

EOS

ADC_DR read access

ADC_DR

Injected trigger

JEOS

ADC_JDR1

ADC_JDR2

D1 D2

Ignored

DLY (inj)

D5 by s/w by h/w Indicative timings

1. AUTDLY=1

2. Regular configuration: EXTEN[1:0]=01 (HW trigger), CONT=0, DISCEN=0, CHANNELS = 1, 2, 3

3. Injected configuration: JEXTEN[1:0]=01 (HW Trigger), JDISCEN=0, CHANNELS = 5,6

MS31021V2

RM0471 Rev 5 395/1202

443

Analog-to-digital converter (ADC) RM0471

Figure 66. AUTODLY=1, regular HW conversions interrupted by injected conversions

(DISCEN=1, JDISCEN=1)

Ignored

Not ignored (occurs during injected sequence)

Regular trigger

ADC state

RDY CH1 regular

DLY RDY CH2 regular

DLY (CH1)

DLY RDY CH5

DLY (CH2) injected

RDY CH6 injected

CH3 regular

DLY RDY CH1 regular

DLY (CH3)

DLY RDY CH2

DLY (CH1) regular

EOC

EOS

ADC_DR read access

ADC_DR

Injected trigger

JEOS

ADC_JDR1

ADC_JDR2 by SW

D1 by HW

Ignored

DLY (inj)

Indicative timings

MS31022V1

1. AUTDLY=1

2. Regular configuration: EXTEN[1:0]=01 (HW trigger), CONT=0, DISCEN=1, DISCNUM=1, CHANNELS = 1, 2, 3.

3. Injected configuration: JEXTEN[1:0]=01 (HW Trigger), JDISCEN=1, CHANNELS = 5,6

396/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Figure 67. AUTODLY=1, regular continuous conversions interrupted by injected conversions

ADSTART

(1)

ADC state

RDY CH1 regular

DLY

DLY (CH1)

EOC

EOS

ADC_DR read access

ADC_DR

Injected trigger

JEOS

ADC_JDR1

ADC_JDR2

D1 by s/w by h/w

CH2 regular

DLY

DLY (CH2)

CH5 CH6 injected injected

DLY

Ignored

DLY (inj) regular

CH3

Indicative timings

DLY CH1

MS31023V3

1. AUTDLY=1

2. Regular configuration: EXTEN[1:0]=00 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2, 3

3. Injected configuration: JEXTEN[1:0]=01 (HW Trigger), JDISCEN=0, CHANNELS = 5,6

Figure 68. AUTODLY=1 in auto- injected mode (JAUTO=1)

ADSTART

(1)

ADC state RDY

EOC

EOS

ADC_DR read access

CH1 regular

ADC_DR

JEOS

ADC_JDR1

ADC_JDR2 by s/w

DLY (CH1) by h/w

No delay

CH2 CH5 regular injected

CH6 injected

DLY (inj) DLY(CH2) CH3 regular

DLY CH1 regular

Indicative timings

MS31024V3

1. AUTDLY=1

2. Regular configuration: EXTEN[1:0]=00 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2

3. Injected configuration: JAUTO=1, CHANNELS = 5,6

RM0471 Rev 5 397/1202

443

Analog-to-digital converter (ADC)

15.3.28 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL,

AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)

The three AWD analog watchdogs monitor whether some channels remain within a configured voltage range (window).

Figure 69. Analog watchdog guarded area

RM0471

Analog voltage

Higher threshold HTx

Guarded area

Lower threshold LTx

MS45396V1

AWDx flag and interrupt

An interrupt can be enabled for each of the 3 analog watchdogs by setting AWDxIE in the

ADC_IER register (x=1,2,3).

AWDx (x=1,2,3) flag is cleared by software by writing 1 to it.

The ADC conversion result is compared to the lower and higher thresholds before alignment.

Description of analog watchdog 1

The AWD analog watchdog 1 is enabled by setting the AWD1EN bit in the ADC_CFGR register. This watchdog monitors whether either one selected channel or all enabled channels

(1) remain within a configured voltage range (window).

Table 71 shows how the ADC_CFGR registers should be configured to enable the analog

watchdog on one or more channels.

Table 71. Analog watchdog channel selection

Channels guarded by the analog watchdog

AWD1SGL bit AWD1EN bit JAWD1EN bit

None

All injected channels

All regular channels

All regular and injected channels

Single (1) injected channel

Single

(1)

regular channel

Single (1) regular or injected channel x

1. Selected by the AWD1CH[4:0] bits. The channels must also be programmed to be converted in the appropriate regular or injected sequence.

The AWD1 analog watchdog status bit is set if the analog voltage converted by the ADC is below a lower threshold or above a higher threshold.

398/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

These thresholds are programmed in bits HT1[11:0] and LT1[11:0] of the ADC_TR1 register for the analog watchdog 1. When converting data with a resolution of less than 12 bits

(according to bits RES[1:0]), the LSB of the programmed thresholds must be kept cleared because the internal comparison is always performed on the full 12-bit raw converted data

(left aligned).

Table 72 describes how the comparison is performed for all the possible resolutions for

analog watchdog 1.

Resolution( bit

RES[1:0])

00: 12-bit

01: 10-bit

10: 8-bit

11: 6-bit

Table 72. Analog watchdog 1 comparison

Analog watchdog comparison between:

Comments

Raw converted data, left aligned

Thresholds

DATA[11:0]

DATA[11:2],00

DATA[11:4],0000

DATA[11:6],000000

LT1[11:0] and

HT1[11:0]

LT1[11:0] and

HT1[11:0]

LT1[11:0] and

HT1[11:0]

LT1[11:0] and

HT1[11:0]

User must configure LT1[1:0] and HT1[1:0] to 00

User must configure LT1[3:0] and HT1[3:0] to 0000

User must configure LT1[5:0] and HT1[5:0] to 000000

Description of analog watchdog 2 and 3

The second and third analog watchdogs are more flexible and can guard several selected channels by programming the corresponding bits in AWDxCH[18:0] (x=2,3).

The corresponding watchdog is enabled when any bit of AWDxCH[18:0] (x=2,3) is set.

They are limited to a resolution of 8 bits and only the 8 MSBs of the thresholds can be programmed into HTx[7:0] and LTx[7:0].

Table 73 describes how the comparison is

performed for all the possible resolutions.

00: 12-bit

01: 10-bit

10: 8-bit

11: 6-bit

Resolution

(bits RES[1:0])

Table 73. Analog watchdog 2 and 3 comparison

Analog watchdog comparison between:

Comments

Raw converted data, left aligned

Thresholds

DATA[11:4]

DATA[11:6],00

LTx[7:0] and HTx[7:0] DATA[3:0] are not relevant for the comparison

LTx[7:0] and HTx[7:0] DATA[3:2] are not relevant for the comparison

LTx[7:0] and HTx[7:0] -

LTx[7:0] and HTx[7:0] User must configure LTx[1:0] and HTx[1:0] to 00

RM0471 Rev 5 399/1202

443

Analog-to-digital converter (ADC) RM0471

Note:

ADCy_AWDx_OUT signal output generation

Each analog watchdog is associated to an internal hardware signal ADCy_AWDx_OUT

(y=ADC number, x=watchdog number) which is directly connected to the ETR input

(external trigger) of some on-chip timers. Refer to the on-chip timers section to understand how to select the ADCy_AWDx_OUT signal as ETR.

ADCy_AWDx_OUT is activated when the associated analog watchdog is enabled:

 ADCy_AWDx_OUT is set when a guarded conversion is outside the programmed thresholds.

 ADCy_AWDx_OUT is reset after the end of the next guarded conversion which is inside the programmed thresholds (It remains at 1 if the next guarded conversions are still outside the programmed thresholds).

 ADCy_AWDx_OUT is also reset when disabling the ADC (when setting ADDIS=1).

Note that stopping regular or injected conversions (setting ADSTP=1 or JADSTP=1) has no influence on the generation of ADCy_AWDx_OUT.

AWDx flag is set by hardware and reset by software: AWDx flag has no influence on the generation of ADCy_AWDx_OUT (ex: ADCy_AWDx_OUT can toggle while AWDx flag remains at 1 if the software did not clear the flag).

Figure 70. ADCy_AWDx_OUT signal generation (on all regular channels)

ADC

STATE

RDY Conversion1 inside

EOC FLAG

Conversion2 Conversion3 Conversion4 Conversion5 Conversion6 Conversion7 outside inside outside outside outside inside

AWDx FLAG

ADCy_AWDx_OUT cleared by S/W cleared by S/W cleared by S/W cleared by S/W

- Converting regular channels 1,2,3,4,5,6,7

- Regular channels 1,2,3,4,5,6,7 are all guarded

MS31025V1

400/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Figure 71. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by software)

ADC

STATE

RDY Conversion1 inside

EOC FLAG

Conversion2 Conversion3 Conversion4 Conversion5 Conversion6 Conversion7 outside inside outside outside outside inside not cleared by S/W

AWDx FLAG

ADCy_AWDx_OUT

- Converting regular channels 1,2,3,4,5,6,7

- Regular channels 1,2,3,4,5,6,7 are all guarded

MS31026V1

Figure 72. ADCy_AWDx_OUT signal generation (on a single regular channel)

ADC

STATE

Conversion1 outside

EOC FLAG

Conversion2 Conversion1 Conversion2 Conversion1 Conversion2 Conversion1 inside outside outside

Conversion2

EOS FLAG

AWDx FLAG

ADCy_AWDx_OUT cleared by S/W cleared by S/W

- Converting regular channels 1 and 2

- Only channel 1 is guarded

MS31027V1

Figure 73. ADCy_AWDx_OUT signal generation (on all injected channels)

ADC

STATE

RDY Conversion1 Conversion2 Conversion3 Conversion4 Conversion Conversion inside outside inside outside outside outside

Conversion inside

JEOS FLAG

AWDx FLAG cleared by S/W cleared by S/W cleared by S/W cleared by S/W

ADCy_AWDx_OUT

- Converting the injected channels 1, 2, 3, 4

- All injected channels 1, 2, 3, 4 are guarded

MS31028V1

RM0471 Rev 5 401/1202

443

Analog-to-digital converter (ADC) RM0471

15.3.29 Oversampler

The oversampling unit performs data pre-processing to offload the CPU. It is able to handle multiple conversions and average them into a single data with increased data width, up to

16-bit.

It provides a result with the following form, where N and M can be adjusted:

Result =

 n = N 1

 n = 0

Note:

It allows to perform by hardware the following functions: averaging, data rate reduction,

SNR improvement, basic filtering.

The oversampling ratio N is defined using the OVFS[2:0] bits in the ADC_CFGR2 register, and can range from 2x to 256x. The division coefficient M consists of a right bit shift up to

8 bits, and is defined using the OVSS[3:0] bits in the ADC_CFGR2 register.

The summation unit can yield a result up to 20 bits (256x 12-bit results), which is first shifted right. It is then truncated to the 16 least significant bits, rounded to the nearest value using the least significant bits left apart by the shifting, before being finally transferred into the

ADC_DR data register.

If the intermediary result after the shifting exceeds 16-bit, the result is truncated as is, without saturation.

Figure 74. 20-bit to 16-bit result truncation

Raw 20-bit data

19 15 11 7 3 0

Shifting

15 0

Truncation and rounding

MS34453V1

Figure 75

gives a numerical example of the processing, from a raw 20-bit accumulated data to the final 16-bit result.

Figure 75. Numerical example with 5-bit shift and rounding

Raw 20-bit data

Final result after 5-bit shift and rounding to nearest

1 D B F

MS34454V1

Table 74 gives the data format for the various N and M combinations, for a raw conversion

data equal to 0xFFF.

402/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Table 74. Maximum output results versus N and M (gray cells indicate truncation)

Over sampling ratio

Max

Raw data

No-shift

OVSS =

0000

1-bit shift

OVSS =

0001

2-bit shift

OVSS =

0010

3-bit shift

OVSS =

0011

4-bit shift

OVSS =

0100

5-bit shift

OVSS =

0101

6-bit shift

OVSS =

0110

7-bit shift

OVSS =

0111

8-bit shift

OVSS =

1000

16x

32x

64x

128x

256x

0x1FFE 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 0x020

0x3FFC 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040

0x7FF8 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080

0xFFF0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100

0x1FFE0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200

0x3FFC0 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400

0x7FF80 0xFF80 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800

0xFFF00 0xFF00 0xFF80 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF

Note:

There are no changes for conversion timings in oversampled mode: the sample time is maintained equal during the whole oversampling sequence. A new data is provided every N conversions, with an equivalent delay equal to N x T

CONV set as follows:

= N x (t

SMPL

+ t

SAR

). The flags are

 The end of the sampling phase (EOSMP) is set after each sampling phase

 The end of conversion (EOC) occurs once every N conversions, when the oversampled result is available

 The end of sequence (EOS) occurs once the sequence of oversampled data is completed (i.e. after N x sequence length conversions total)

ADC operating modes supported when oversampling

In oversampling mode, most of the ADC operating modes are maintained:

 Single or continuous mode conversions

 ADC conversions start either by software or with triggers

 ADC stop during a conversion (abort)

 Data read via CPU or DMA with overrun detection

 Low-power modes (AUTDLY)

 Programmable resolution: in this case, the reduced conversion values (as per RES[1:0] bits in ADC_CFGR1 register) are accumulated, truncated, rounded and shifted in the same way as 12-bit conversions are

The alignment mode is not available when working with oversampled data. The ALIGN bit in

ADC_CFGR1 is ignored and the data are always provided right-aligned.

Offset correction is not supported in oversampling mode. When ROVSE and/or JOVSE bit is set, the value of the OFFSETy_EN bit in ADC_OFRy register is ignored (considered as reset).

RM0471 Rev 5 403/1202

443

Analog-to-digital converter (ADC)

Note:

RM0471

Analog watchdog

The analog watchdog functionality is maintained (AWDSGL and AWDEN bits), with the following difference:

– The RES[1:0] bits are ignored, comparison is always done using the full 12-bit values HT[11:0] and LT[11:0]

– the comparison is performed on the most significant 12-bit of the 16-bit oversampled results ADC_DR[15:4]

Care must be taken when using high shifting values, this will reduce the comparison range.

For instance, if the oversampled result is shifted by 4 bits, thus yielding a 12-bit data rightaligned, the effective analog watchdog comparison can only be performed on 8 bits. The comparison is done between ADC_DR[11:4] and HT[0:7] / LT[[0:7], and HT[11:8] / LT[11:8] must be kept reset.

Triggered mode

The averager can also be used for basic filtering purpose. Although not a very powerful filter

(slow roll-off and limited stop band attenuation), it can be used as a notch filter to reject constant parasitic frequencies (typically coming from the mains or from a switched mode power supply). For this purpose, a specific discontinuous mode can be enabled with

TROVS bit in ADC_CFGR2, to be able to have an oversampling frequency defined by a user and independent from the conversion time itself.

Figure 76

below shows how conversions are started in response to triggers during discontinuous mode.

If the TROVS bit is set, the content of the DISCEN bit is ignored and considered as 1.

Figure 76. Triggered regular oversampling mode (TROVS bit = 1)

CONT=0

DISCEN = 1

TROVS = 0

Trigger

Ch(N)

Trigger

Ch(N)

EOC flag set

CONT=0

DISCEN = 1

TROVS = 1

Trigger

Ch(N)

Trigger

Ch(N)

Trigger

Ch(N)

Trigger

Ch(N)

Trigger

Ch(N)

Trigger

Ch(N)

Trigger

Ch(N)

EOC flag set

MS34455V2

Injected and regular sequencer management when oversampling

In oversampling mode, it is possible to have differentiated behavior for injected and regular sequencers. The oversampling can be enabled for both sequencers with some limitations if they have to be used simultaneously (this is related to a unique accumulation unit).

404/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Oversampling regular channels only

The regular oversampling mode bit ROVSM defines how the regular oversampling sequence is resumed if it is interrupted by injected conversion:

 In continued mode, the accumulation restarts from the last valid data (prior to the conversion abort request due to the injected trigger). This ensures that oversampling will be complete whatever the injection frequency (providing at least one regular conversion can be complete between triggers);

 In resumed mode, the accumulation restarts from 0 (previous conversion results are ignored). This mode allows to guarantee that all data used for oversampling were converted back-to-back within a single timeslot. Care must be taken to have a injection trigger period above the oversampling period length. If this condition is not respected, the oversampling cannot be complete and the regular sequencer will be blocked.

Figure 77

gives examples for a 4x oversampling ratio.

Figure 77. Regular oversampling modes (4x ratio)

Oversampling stopped

Oversampling continued

Regular channels Ch(N)

Ch(N)

Ch(M)

Abort

Trigger

Injected channels Ch(J) Ch(K)

Ch(M)

Ch(O)

JEOC

Continued mode: ROVSE = 1, JOVSE = 0, ROVSM = 0, TROVS = X

Oversampling aborted

Oversampling resumed

Regular channels Ch(N)

Ch(N)

Ch(M)

Abort

Trigger

Injected channels Ch(J) Ch(K)

Ch(M)

JEOC

Resumed mode: ROVSE = 1, JOVSE = 0, ROVSM = 1, TROVS = X

MS34456V1

Oversampling Injected channels only

The Injected oversampling mode bit JOVSE enables oversampling solely for conversions in the injected sequencer.

RM0471 Rev 5 405/1202

443

Analog-to-digital converter (ADC) RM0471

Oversampling regular and Injected channels

It is possible to have both ROVSE and JOVSE bits set. In this case, the regular oversampling mode is forced to resumed mode (ROVSM bit ignored), as represented on

Figure 78

below.

Figure 78. Regular and injected oversampling modes used simultaneously

Oversampling aborted

Oversampling resumed

Regular channels Ch(N)

Ch(N)

Ch(M)

Abort

Trigger

Injected channels Ch(J)

Ch(J)

Ch(M)

JEOC

ROVSE = 1, JOVSE = 1, ROVSM = X, TROVS = 0

MS34457V1

Triggered regular oversampling with injected conversions

It is possible to have triggered regular mode with injected conversions. In this case, the injected mode oversampling mode must be disabled, and the ROVSM bit is ignored

(resumed mode is forced). The JOVSE bit must be reset. The behavior is represented on

Figure 79

below.

Figure 79. Triggered regular oversampling with injection

Oversampling resumed

Trigger Trigger Trigger Trigger Trigger

Regular channels Ch(N)

Ch(N)

Trigger

Ch(N)

Abort

Injected channels Ch(J) Ch(K)

ROVSE = 1, JOVSE = 0, ROVSM = X, TROVS = 1

Ch(N)

MS34458V2

406/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Auto-injected mode

It is possible to oversample auto-injected sequences and have all conversions results stored in registers to save a DMA resource. This mode is available only with both regular and injected oversampling active: JAUTO = 1, ROVSE = 1 and JOVSE = 1, other combinations

are not supported. The ROVSM bit is ignored in auto-injected mode. The Figure 80 below

shows how the conversions are sequenced.

Figure 80. Oversampling in auto-injected mode

Regular channels N

Injected channels I

JAUTO =1, ROVSE = 1, JOVSE = 1, ROVSM = X, TROVS = 0

MS34459V1

It is possible to have also the triggered mode enabled, using the TROVS bit. In this case, the ADC must be configured as following: JAUTO = 1, DISCEN = 0, JDISCEN = 0, ROVSE

= 1, JOVSE = 1 and TROVSE = 1.

The temperature sensor can be used to measure the junction temperature (Tj) of the device.

The temperature sensor is internally connected to the ADC input channels which are used to convert the sensor output voltage to a digital value. When not in use, the sensor can be put in power down mode. It support the temperature range –40 to 125 °C.

Figure 81

shows the block diagram of connections between the temperature sensor and the

ADC.

The temperature sensor output voltage changes linearly with temperature. The offset of this line varies from chip to chip due to process variation (up to 45 °C from one chip to another).

The uncalibrated internal temperature sensor is more suited for applications that detect temperature variations instead of absolute temperatures. To improve the accuracy of the temperature sensor measurement, calibration values are stored in system memory for each device by ST during production.

During the manufacturing process, the calibration data of the temperature sensor and the internal voltage reference are stored in the system memory area. The user application can then read them and use them to improve the accuracy of the temperature sensor or the internal reference (refer to the datasheet for additional information).

The temperature sensor is internally connected to the ADC input channel which is used to convert the sensor’s output voltage to a digital value. Refer to the electrical characteristics section of the device datasheet for the sampling time value to be applied when converting the internal temperature sensor.

When not in use, the sensor can be put in power-down mode.

Figure 81

shows the block diagram of the temperature sensor.

RM0471 Rev 5 407/1202

443

Analog-to-digital converter (ADC)

Figure 81. Temperature sensor channel block diagram

RM0471

CH17SEL control bit

Converted data

ADCx

Temperature sensor

ADC input

MSv37243V3

Reading the temperature

To use the sensor:

Select the ADC input channel that is connected to V

2. Program with the appropriate sampling time (refer to electrical characteristics section of the device datasheet).

3. Set the CH17SEL bit in the ADCx_CCR register to wake up the temperature sensor from power-down mode.

4. Start the ADC conversion.

5. Read the resulting V

data in the ADC data register.

6. Calculate the actual temperature using the following formula:

 =

TS_CAL2_TEMP TS_CAL1_TEMP

  –  + 30 °C

Note:

Where:

 TS_CAL2 is the temperature sensor calibration value acquired at TS_CAL2_TEMP.

 TS_CAL1 is the temperature sensor calibration value acquired at TS_CAL1_TEMP.

 TS_DATA is the actual temperature sensor output value converted by ADC.

Refer to the device datasheet for more information about TS_CAL1 and TS_CAL2 calibration points.

The sensor has a startup time after waking from power-down mode before it can output V

TS at the correct level. The ADC also has a startup time after power-on, so to minimize the delay, the ADEN and CH17SEL bits should be set at the same time.

The above formula is given for TS_DATA measurement done with the same V

DDA

TS_CAL1/TS_CAL2 values. If V

DDA if V

DDA by TS_DATA x (3.3/3.0).

is different, the formula must be adapted. For example

= 3.3 V and TS_CAL data are acquired at V

DDA voltage as

= 3.0 V, TS_DATA must be replaced

408/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

15.3.31 V

BAT

supply monitoring

The CH18SEL bit in the ADCx_CCR register is used to switch to the battery voltage. As the

BAT

voltage could be higher than V

DDA

, to ensure the correct operation of the ADC, the

pin is internally connected to a bridge divider by 3. This bridge is automatically enabled when CH18SEL is set, to connect V

BAT

/3 to the ADC input channels. As a consequence, the converted digital value is one third of the V

BAT

voltage. To prevent any unwanted consumption on the battery, it is recommended to enable the bridge divider only when needed, for ADC conversion.

Refer to the electrical characteristics of the device datasheet for the sampling time value to be applied when converting the V

BAT

/3 voltage.

The figure below shows the block diagram of the V

BAT

sensing feature.

Figure 82. V

BAT

channel block diagram

BAT

CH18SEL control bit

ADCx

BAT

ADC input

MSv37245V1

1. The CH18SEL bit must be set to enable the conversion of internal channel for V

BAT

/3.

It is possible to monitor the internal voltage reference (V

REFINT evaluating the ADC V

DDA

voltage level.

) to have a reference point for

The internal voltage reference is internally connected to the input channel 0 of the ADC1

(ADC1_INP0).

Refer to the electrical characteristics section of the product datasheet for the sampling time value to be applied when converting the internal voltage reference voltage.

Figure 83

shows the block diagram of the V

REFINT

sensing feature.

RM0471 Rev 5 409/1202

443

Analog-to-digital converter (ADC)

Figure 83. V

REFINT

channel block diagram

RM0471

Internal power block

VREFEN control bit

REFINT

ADCx

ADC input

MSv34467V5

1. The VREFEN bit into ADCx_CCR register must be set to enable the conversion of internal channels

REFINT

Calculating the actual

DDA

voltage using the internal reference voltage

The power supply voltage applied to the device may be subject to variations or not precisely known. V

REFINT

and its calibration data, acquired by the ADC during the manufacturing process at V

DDA_Charac

, can be used to evaluate the actual V

DDA

voltage level.

The following formula gives the actual V

DDA

voltage supplying the device:

DDA

= V

DDA_Charac



Where:

 V

DDA_Charac

is the value of V

DDA

voltage characterized at V

REFINT manufacturing process. It is specified in the device datasheet.

during the

 VREFINT_CAL is the V

REFINT

calibration value

 VREFINT_DATA is the actual V

REFINT

output value converted by ADC

Converting a supply-relative ADC measurement to an absolute voltage value

The ADC is designed to deliver a digital value corresponding to the ratio between V

DDA the voltage applied on the converted channel.

and

410/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

For most applications V

DDA value is unknown and ADC converted values are right-aligned.

In this case, it is necessary to convert this ratio into a voltage independent from V

DDA

CHANNELx

DDA

FULL_SCALE

 ADC_DATA

Note:

For applications where V

DDA

is known and ADC converted values are right-aligned, the absolute voltage value can be obtained by using the following formula:

CHANNELx

DDA

FULL_SCALE

 ADC_DATA

Where:

– V

DDA_Charac

is the value of V manufacturing process.

DDA

voltage characterized at V

REFINT

during the

– VREFINT_CAL is the V

REFINT

calibration value

– ADC_DATA is the value measured by the ADC on channel x (right-aligned)

– VREFINT_DATA is the actual V

REFINT

output value converted by the ADC

– FULL_SCALE is the maximum digital value of the ADC output. For example with

12-bit resolution, it will be 2 12 - 1 = 4095 or with 8-bit resolution, 2 8 - 1 = 255.

If ADC measurements are done using an output format other than 16 -bit right-aligned, all the parameters must first be converted to a compatible format before the calculation is done.

An interrupt can be generated:

 After ADC power-up, when the ADC is ready (flag ADRDY)

 On the end of any conversion for regular groups (flag EOC)

 On the end of a sequence of conversion for regular groups (flag EOS)

 On the end of any conversion for injected groups (flag JEOC)

 On the end of a sequence of conversion for injected groups (flag JEOS)

 When an analog watchdog detection occurs (flag AWD1, AWD2 and AWD3)

 When the end of sampling phase occurs (flag EOSMP)

 When the data overrun occurs (flag OVR)

 When the injected sequence context queue overflows (flag JQOVF)

Separate interrupt enable bits are available for flexibility.

Table 75. ADC interrupts

Interrupt event Event flag

ADC ready

End of conversion of a regular group

End of sequence of conversions of a regular group

ADRDY

EOC

EOS

Enable control bit

ADRDYIE

EOCIE

EOSIE

RM0471 Rev 5 411/1202

443

Analog-to-digital converter (ADC) RM0471

Table 75. ADC interrupts (continued)

Interrupt event Event flag

End of conversion of a injected group

End of sequence of conversions of an injected group

Analog watchdog 1 status bit is set

Analog watchdog 2 status bit is set

Analog watchdog 3 status bit is set

End of sampling phase

Overrun

Injected context queue overflows

JEOC

JEOS

AWD1

AWD2

AWD3

EOSMP

OVR

JQOVF

Enable control bit

JEOCIE

JEOSIE

AWD1IE

AWD2IE

AWD3IE

EOSMPIE

OVRIE

JQOVFIE

412/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Refer to Section 1.2 on page 50 for a list of abbreviations used in register descriptions.

15.5.1 ADC interrupt and status register (ADC_ISR)

Address offset: 0x00

Reset value: 0x0000 0000

Res.

11 10 9 8 7 6 5 4 3 2 1 0

Res.

JQOVF AWD3 AWD2 AWD1 JEOS JEOC OVR EOS EOC EOSMP ADRDY rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 JQOVF : Injected context queue overflow

This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared

by software writing 1 to it. Refer to Section 15.3.21: Queue of context for injected conversions

for more information.

0: No injected context queue overflow occurred (or the flag event was already acknowledged and cleared by software)

1: Injected context queue overflow has occurred

Bit 9 AWD3 : Analog watchdog 3 flag

This bit is set by hardware when the converted voltage crosses the values programmed in the fields

LT3[7:0] and HT3[7:0] of ADC_TR3 register. It is cleared by software writing 1 to it.

0: No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared by software)

1: Analog watchdog 3 event occurred

Bit 8 AWD2 : Analog watchdog 2 flag

This bit is set by hardware when the converted voltage crosses the values programmed in the fields

LT2[7:0] and HT2[7:0] of ADC_TR2 register. It is cleared by software writing 1 to it.

0: No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared by software)

1: Analog watchdog 2 event occurred

Bit 7 AWD1 : Analog watchdog 1 flag

This bit is set by hardware when the converted voltage crosses the values programmed in the fields

LT1[11:0] and HT1[11:0] of ADC_TR1 register. It is cleared by software. writing 1 to it.

0: No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared by software)

1: Analog watchdog 1 event occurred

Bit 6 JEOS: Injected channel end of sequence flag

This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it.

0: Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software)

1: Injected conversions complete

RM0471 Rev 5 413/1202

443

Analog-to-digital converter (ADC) RM0471

Bit 5 JEOC: Injected channel end of conversion flag

This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register

0: Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software)

1: Injected channel conversion complete

Bit 4 OVR : ADC overrun

This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it.

0: No overrun occurred (or the flag event was already acknowledged and cleared by software)

1: Overrun has occurred

Bit 3 EOS : End of regular sequence flag

This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it.

0: Regular Conversions sequence not complete (or the flag event was already acknowledged and cleared by software)

1: Regular Conversions sequence complete

Bit 2 EOC : End of conversion flag

This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register

0: Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software)

1: Regular channel conversion complete

Bit 1 EOSMP : End of sampling flag

This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase.

0: not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)

1: End of sampling phase reached

Bit 0 ADRDY : ADC ready

This bit is set by hardware after the ADC has been enabled (bit ADEN=1) and when the ADC reaches a state where it is ready to accept conversion requests.

It is cleared by software writing 1 to it.

0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)

1: ADC is ready to start conversion

414/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

15.5.2 ADC interrupt enable register (ADC_IER)

Address offset: 0x04

Reset value: 0x0000 0000

Res.

10 9 8 7 6 5 4 3 2

JQOVF

IE rw

AWD3IE AWD2IE AWD1IE JEOSIE JEOCIE OVRIE EOSIE EOCIE rw rw rw rw rw rw rw rw

1 0

EOSMP

ADRDY

IE rw rw

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 JQOVFIE : Injected context queue overflow interrupt enable

This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow interrupt.

0: Injected Context Queue Overflow interrupt disabled

1: Injected Context Queue Overflow interrupt enabled. An interrupt is generated when the JQOVF bit is set.

Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing).

Bit 9 AWD3IE : Analog watchdog 3 interrupt enable

This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt.

0: Analog watchdog 3 interrupt disabled

1: Analog watchdog 3 interrupt enabled

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bit 8 AWD2IE : Analog watchdog 2 interrupt enable

This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt.

0: Analog watchdog 2 interrupt disabled

1: Analog watchdog 2 interrupt enabled

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bit 7 AWD1IE : Analog watchdog 1 interrupt enable

This bit is set and cleared by software to enable/disable the analog watchdog 1 interrupt.

0: Analog watchdog 1 interrupt disabled

1: Analog watchdog 1 interrupt enabled

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bit 6 JEOSIE : End of injected sequence of conversions interrupt enable

This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt.

0: JEOS interrupt disabled

1: JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set.

Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing).

RM0471 Rev 5 415/1202

443

Analog-to-digital converter (ADC) RM0471

Bit 5 JEOCIE : End of injected conversion interrupt enable

This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt.

0: JEOC interrupt disabled.

1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.

Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing).

Bit 4 OVRIE : Overrun interrupt enable

This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular conversion.

0: Overrun interrupt disabled

1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.

Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 3 EOSIE : End of regular sequence of conversions interrupt enable

This bit is set and cleared by software to enable/disable the end of regular sequence of conversions interrupt.

0: EOS interrupt disabled

1: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.

Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 2 EOCIE : End of regular conversion interrupt enable

This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt.

0: EOC interrupt disabled.

1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.

Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 1 EOSMPIE : End of sampling flag interrupt enable for regular conversions

This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for regular conversions.

0: EOSMP interrupt disabled.

1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.

Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 0 ADRDYIE : ADC ready interrupt enable

This bit is set and cleared by software to enable/disable the ADC Ready interrupt.

0: ADRDY interrupt disabled

1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

416/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

15.5.3 ADC control register (ADC_CR)

Address offset: 0x08

Reset value: 0x2000 0000

ADCA

L rs

ADCA

LDIF rw

DEEP

PWD rw

ADVREG

EN rw

Res.

JADST

P rs

ADSTP rs

JADST

ART rs

ADSTA

RT rs

ADDIS ADEN rs

0 rs

Bit 31 ADCAL : ADC calibration

This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF to determine if this calibration applies for single-ended or differential inputs mode.

It is cleared by hardware after calibration is complete.

0: Calibration complete

1: Write 1 to calibrate the ADC. Read at 1 means that a calibration in progress.

Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN=0.

The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing)

Bit 30 ADCALDIF : Differential mode for calibration

This bit is set and cleared by software to configure the single-ended or differential inputs mode for the calibration.

0: Writing ADCAL will launch a calibration in single-ended inputs mode.

1: Writing ADCAL will launch a calibration in differential inputs mode.

Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

Bit 29 DEEPPWD : Deep-power-down enable

This bit is set and cleared by software to put the ADC in Deep-power-down mode.

0: ADC not in Deep-power down

1: ADC in Deep-power-down (default reset state)

Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL=0,

JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

Bit 28 ADVREGEN : ADC voltage regulator enable

This bits is set by software to enable the ADC voltage regulator.

Before performing any operation such as launching a calibration or enabling the ADC, the

ADC voltage regulator must first be enabled and the software must wait for the regulator start-up time.

0: ADC Voltage regulator disabled

1: ADC Voltage regulator enabled.

For more details about the ADC voltage regulator enable and disable sequences, refer to

Section 15.3.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator

(ADVREGEN) .

The software can program this bit field only when the ADC is disabled (ADCAL=0,

JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

RM0471 Rev 5 417/1202

443

Analog-to-digital converter (ADC) RM0471

Bits 27:6 Reserved, must be kept at reset value.

Bit 5 JADSTP : ADC stop of injected conversion command

This bit is set by software to stop and discard an ongoing injected conversion (JADSTP

Command).

It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected conversions (JADSTART command).

0: No ADC stop injected conversion command ongoing

1: Write 1 to stop injected conversions ongoing. Read 1 means that an ADSTP command is in progress.

Note: The software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 (ADC is enabled and eventually converting an injected conversion and there is no pending request to disable the ADC)

In Auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP)

Bit 4 ADSTP : ADC stop of regular conversion command

This bit is set by software to stop and discard an ongoing regular conversion (ADSTP

Command).

It is cleared by hardware when the conversion is effectively discarded and the ADC regular sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular conversions (ADSTART command).

0: No ADC stop regular conversion command ongoing

1: Write 1 to stop regular conversions ongoing. Read 1 means that an ADSTP command is in progress.

Note: The software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 (ADC is enabled and eventually converting a regular conversion and there is no pending request to disable the ADC).

In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP).

Bit 3 JADSTART : ADC start of injected conversion

This bit is set by software to start ADC conversion of injected channels. Depending on the configuration bits JEXTEN[1:0], a conversion will start immediately (software trigger configuration) or once an injected hardware trigger event occurs (hardware trigger configuration).

It is cleared by hardware:

– in single conversion mode when software trigger is selected (JEXTSEL=0x0): at the assertion of the End of Injected Conversion Sequence (JEOS) flag.

– in all cases: after the execution of the JADSTP command, at the same time that JADSTP is cleared by hardware.

0: No ADC injected conversion is ongoing.

1: Write 1 to start injected conversions. Read 1 means that the ADC is operating and eventually converting an injected channel.

Note: The software is allowed to set JADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC).

In auto-injection mode (JAUTO=1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared)

418/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Bit 2 ADSTART : ADC start of regular conversion

This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN[1:0], a conversion will start immediately (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration).

It is cleared by hardware:

– in single conversion mode when software trigger is selected (EXTSEL=0x0): at the assertion of the End of Regular Conversion Sequence (EOS) flag.

– in all cases: after the execution of the ADSTP command, at the same time that ADSTP is cleared by hardware.

0: No ADC regular conversion is ongoing.

1: Write 1 to start regular conversions. Read 1 means that the ADC is operating and eventually converting a regular channel.

Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC)

In auto-injection mode (JAUTO=1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared)

Bit 1 ADDIS : ADC disable command

This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state).

It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time).

0: no ADDIS command ongoing

1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.

Note: The software is allowed to set ADDIS only when ADEN=1 and both ADSTART=0 and

JADSTART=0 (which ensures that no conversion is ongoing)

Bit 0 ADEN : ADC enable control

This bit is set by software to enable the ADC. The ADC will be effectively ready to operate once the flag ADRDY has been set.

It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command.

0: ADC is disabled (OFF state)

1: Write 1 to enable the ADC.

Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0

(ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0) except for bit ADVREGEN which must be 1 (and the software must have wait for the startup time of the voltage regulator)

RM0471 Rev 5 419/1202

443

Analog-to-digital converter (ADC) RM0471

Address offset: 0x0C

Reset value: 0x8000 0000

JQDIS rw

Res.

30 rw

AUT

DLY rw

29 28

AWD1CH[4:0]

27 rw

CONT rw rw

OVR

MOD rw rw

26 rw

EXTEN[1:0] rw rw

JAUTO rw

EXTSE

L3 rw

JAWD1

EN rw

EXTSE

L2 rw

AWD1

EN rw

EXTSE

L1 rw

AWD1S

GL rw

EXTSE

L0 rw

JQM rw

ALIGN rw

JDISC

EN rw

4 rw

19 rw

RES[1:0]

3 rw

DISCNUM[2:0] rw

Res.

17 rw

DMA

CFG rw

Bit 31 JQDIS : Injected Queue disable

These bits are set and cleared by software to disable the Injected Queue mechanism :

0: Injected Queue enabled

1: Injected Queue disabled

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no regular nor injected conversion is ongoing).

A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is cleared.

Bits 30:26 AWD1CH[4:0] : Analog watchdog 1 channel selection

These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog.

00000: ADC analog input channel 0 monitored by AWD1

00001: ADC analog input channel 1 monitored by AWD1

.....

10010: ADC analog input channel 18 monitored by AWD1 others: reserved, must not be used

Note: Some channels are not connected physically. Keep the corresponding AWD1CH[4:0] setting to the reset value.

The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers.

The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bit 25 JAUTO: Automatic injected group conversion

This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion.

0: Automatic injected group conversion disabled

1: Automatic injected group conversion enabled

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no regular nor injected conversion is ongoing).

DISC

EN rw

DMA

EN rw

Bit 24 JAWD1EN : Analog watchdog 1 enable on injected channels

This bit is set and cleared by software

0: Analog watchdog 1 disabled on injected channels

1: Analog watchdog 1 enabled on injected channels

Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing).

420/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Bit 23 AWD1EN : Analog watchdog 1 enable on regular channels

This bit is set and cleared by software

0: Analog watchdog 1 disabled on regular channels

1: Analog watchdog 1 enabled on regular channels

Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 22 AWD1SGL : Enable the watchdog 1 on a single channel or on all channels

This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels

0: Analog watchdog 1 enabled on all channels

1: Analog watchdog 1 enabled on a single channel

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bit 21 JQM : JSQR queue mode

This bit is set and cleared by software.

It defines how an empty Queue is managed.

0: JSQR mode 0: The Queue is never empty and maintains the last written configuration into JSQR.

1: JSQR mode 1: The Queue can be empty and when this occurs, the software and hardware triggers of the injected sequence are both internally disabled just after the completion of the last valid injected sequence.

Refer to Section 15.3.21: Queue of context for injected conversions

for more information.

Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing).

Bit 20 JDISCEN: Discontinuous mode on injected channels

This bit is set and cleared by software to enable/disable discontinuous mode on the injected channels of a group.

0: Discontinuous mode on injected channels disabled

1: Discontinuous mode on injected channels enabled

Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing).

It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.

Bits 19:17 DISCNUM[2:0]: Discontinuous mode channel count

These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger.

000: 1 channel

001: 2 channels

...

111: 8 channels

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

RM0471 Rev 5 421/1202

443

Analog-to-digital converter (ADC) RM0471

Bit 16 DISCEN : Discontinuous mode for regular channels

This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels.

0: Discontinuous mode for regular channels disabled

1: Discontinuous mode for regular channels enabled

Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1.

It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.

The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 15 Reserved, must be kept at reset value.

Bit 14 AUTDLY : Delayed conversion mode

This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode.

0: Auto-delayed conversion mode off

1: Auto-delayed conversion mode on

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bit 13 CONT : Single / continuous conversion mode for regular conversions

This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared.

0: Single conversion mode

1: Continuous conversion mode

Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1.

The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 12 OVRMOD : Overrun mode

This bit is set and cleared by software and configure the way data overrun is managed.

0: ADC_DR register is preserved with the old data when an overrun is detected.

1: ADC_DR register is overwritten with the last conversion result when an overrun is detected.

Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bits 11:10 EXTEN[1:0] : External trigger enable and polarity selection for regular channels

These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group.

00: Hardware trigger detection disabled (conversions can be launched by software)

01: Hardware trigger detection on the rising edge

10: Hardware trigger detection on the falling edge

11: Hardware trigger detection on both the rising and falling edges

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

422/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Bits 9:6 EXTSEL[3:0] : External trigger selection for regular group

These bits select the external event used to trigger the start of conversion of a regular group:

0000: Event 0

0001: Event 1

0010: Event 2

0011: Event 3

0100: Event 4

0101: Event 5

0110: Event 6

0111: Event 7

...

1111: Event 15

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 5 ALIGN : Data alignment

This bit is set and cleared by software to select right or left alignment. Refer to

Section : Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN)

0: Right alignment

1: Left alignment

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bits 4:3 RES[1:0] : Data resolution

These bits are written by software to select the resolution of the conversion.

00: 12-bit

01: 10-bit

10: 8-bit

11: 6-bit

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bit 2 Reserved, must be kept at reset value.

Bit 1 DMACFG : Direct memory access configuration

This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN=1.

0: DMA One Shot mode selected

1: DMA Circular mode selected

For more details, refer to Section : Managing conversions using the DMA

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bit 0 DMAEN : Direct memory access enable

This bit is set and cleared by software to enable the generation of DMA requests. This allows to use the DMA to manage automatically the converted data. For more details, refer to Section : Managing conversions using the DMA .

0: DMA disabled

1: DMA enabled

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

RM0471 Rev 5 423/1202

443

Analog-to-digital converter (ADC) RM0471

Res.

Address offset: 0x10

Reset value: 0x0000 0000

Res.

ROV

SM rw

TROVS rw

8 7 6

OVSS[3:0] rw rw

5 4 3 2 rw

OVSR[2:0] rw rw

1 0

JOVSE ROVSE rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:17 Reserved, must be kept at reset value.

Bits 16:11 Reserved, must be kept at reset value.

Bit 10 ROVSM : Regular Oversampling mode

This bit is set and cleared by software to select the regular oversampling mode.

0: Continued mode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)

1: Resumed mode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)

Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).

Bit 9 TROVS : Triggered Regular Oversampling

This bit is set and cleared by software to enable triggered oversampling

0: All oversampled conversions for a channel are done consecutively following a trigger

1: Each oversampled conversion for a channel needs a new trigger

Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).

Bits 8:5 OVSS[3:0] : Oversampling shift

This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling result.

0000: No shift

0001: Shift 1-bit

0010: Shift 2-bits

0011: Shift 3-bits

0100: Shift 4-bits

0101: Shift 5-bits

0110: Shift 6-bits

0111: Shift 7-bits

1000: Shift 8-bits

Other codes reserved

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no conversion is ongoing).

424/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Bits 4:2 OVSR[2:0] : Oversampling ratio

This bitfield is set and cleared by software to define the oversampling ratio.

000: 2x

001: 4x

010: 8x

011: 16x

100: 32x

101: 64x

110: 128x

111: 256x

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no conversion is ongoing).

Bit 1 JOVSE : Injected Oversampling Enable

This bit is set and cleared by software to enable injected oversampling.

0: Injected Oversampling disabled

1: Injected Oversampling enabled

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)

Bit 0 ROVSE : Regular Oversampling Enable

This bit is set and cleared by software to enable regular oversampling.

0: Regular Oversampling disabled

1: Regular Oversampling enabled

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)

Address offset: 0x14

Reset value: 0x0000 0000

Res.

SMP5[

0] rw

Res.

29 rw

SMP9[2:0] rw

27 rw

11 rw

SMP4[2:0] rw rw rw

26 rw

SMP8[2:0] rw

SMP3[2:0] rw rw

24 rw

8 rw

23 rw

SMP2[2:0] rw

SMP7[2:0] rw

6 rw

21 rw

5 rw

20 rw

SMP1[2:0] rw

SMP6[2:0] rw

3 rw

18 rw

2 rw

17 16

SMP5[2:1] rw

1 rw

SMP0[2:0] rw rw

RM0471 Rev 5 425/1202

443

Analog-to-digital converter (ADC) RM0471

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:0 SMP[9:0][2:0]: Channel x sampling time selection

These bits are written by software to select the sampling time individually for each channel.

During sample cycles, the channel selection bits must remain unchanged.

000: 2.5 ADC clock cycles

001: 6.5 ADC clock cycles

010: 12.5 ADC clock cycles

011: 24.5 ADC clock cycles

100: 47.5 ADC clock cycles

101: 92.5 ADC clock cycles

110: 247.5 ADC clock cycles

111: 640.5 ADC clock cycles

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0

(which ensures that no conversion is ongoing).

Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.

Address offset: 0x18

Reset value: 0x0000 0000

Res.

SMP15[0] rw

14 13

SMP14[2:0]

12 rw rw rw

Res.

26 rw

SMP18[2:0] rw

SMP13[2:0] rw rw rw

24 rw

8 rw

23 rw

SMP17[2:0] rw

SMP12[2:0] rw rw

21 rw

5 rw

20 rw

SMP16[2:0] rw

SMP11[2:0] rw rw

18 rw

2 rw

SMP10[2:0]

SMP15[2:1] rw rw

0 rw rw

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:0 SMP[18:10][2:0]: Channel x sampling time selection

These bits are written by software to select the sampling time individually for each channel.

During sampling cycles, the channel selection bits must remain unchanged.

000: 2.5 ADC clock cycles

001: 6.5 ADC clock cycles

010: 12.5 ADC clock cycles

011: 24.5 ADC clock cycles

100: 47.5 ADC clock cycles

101: 92.5 ADC clock cycles

110: 247.5 ADC clock cycles

111: 640.5 ADC clock cycles

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0

(which ensures that no conversion is ongoing).

Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.

426/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Address offset: 0x20

Reset value: 0x0FFF 0000

Res.

27 rw

26 rw

25 rw

24 rw

23 rw

22 21

HT1[11:0] rw

6 rw

LT1[11:0] rw rw

20 rw

19 rw

18 rw

17 rw

16 rw

0 rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 HT1[11:0] : Analog watchdog 1 higher threshold

These bits are written by software to define the higher threshold for the analog watchdog 1.

Refer to Section 15.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,

AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:0 LT1[11:0] : Analog watchdog 1 lower threshold

These bits are written by software to define the lower threshold for the analog watchdog 1.

Refer to Section 15.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,

AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Res.

Address offset: 0x24

Reset value: 0x00FF 0000

Res.

7 rw

22 rw

6 rw

21 rw

5 rw

20 19

HT2[7:0] rw

LT2[7:0] rw

3 rw rw

18 rw

2 rw

17 rw

1 rw

16 rw

0 rw

RM0471 Rev 5 427/1202

443

Analog-to-digital converter (ADC) RM0471

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 HT2[7:0] : Analog watchdog 2 higher threshold

These bits are written by software to define the higher threshold for the analog watchdog 2.

Refer to Section 15.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,

AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:0 LT2[7:0] : Analog watchdog 2 lower threshold

These bits are written by software to define the lower threshold for the analog watchdog 2.

Refer to Section 15.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,

AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Address offset: 0x28

Reset value: 0x00FF 0000

Res.

23 rw

22 rw

21 rw

20 19

HT3[7:0] rw

4 rw

3 rw

LT3[7:0] rw

18 rw

17 rw

16 rw

0 rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 HT3[7:0] : Analog watchdog 3 higher threshold

These bits are written by software to define the higher threshold for the analog watchdog 3.

Refer to Section 15.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,

AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:0 LT3[7:0] : Analog watchdog 3 lower threshold

These bits are written by software to define the lower threshold for the analog watchdog 3.

This watchdog compares the 8-bit of LT3 with the 8 MSB of the converted data.

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

428/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Res.

15 rw

Note:

Address offset: 0x30

Reset value: 0x0000 0000

Res.

14 13

SQ2[3:0] rw rw

28 rw

12 rw

27 rw

Res.

SQ4[4:0] rw

10 rw

25 rw

9 rw

24 23

Res.

SQ1[4:0] rw

7 rw

22 rw

6 rw

21 rw

Res.

SQ3[4:0] rw

Res.

19 rw

3 rw

18 rw

L[3:0]

17 16

Res.

SQ2[4]

1 rw

0 rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SQ4[4:0]: 4th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 4th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 23 Reserved, must be kept at reset value.

Bits 22:18 SQ3[4:0]: 3rd conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 3rd in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 17 Reserved, must be kept at reset value.

Bits 16:12 SQ2[4:0]: 2nd conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 2nd in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 11 Reserved, must be kept at reset value.

Bits 10:6 SQ1[4:0]: 1st conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 1st in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bits 5:4 Reserved, must be kept at reset value.

Bits 3:0 L[3:0]: Regular channel sequence length

These bits are written by software to define the total number of conversions in the regular channel conversion sequence.

0000: 1 conversion

0001: 2 conversions

...

1111: 16 conversions

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Some channels are not connected physically and must not be selected for conversion.

RM0471 Rev 5 429/1202

443

Analog-to-digital converter (ADC) RM0471

Res.

15 rw

Note:

Address offset: 0x34

Reset value: 0x0000 0000

Res.

14 13

SQ7[3:0] rw rw

28 rw

12 rw

27 rw

Res.

SQ9[4:0] rw

10 rw

25 rw

9 rw

24 23

Res.

SQ6[4:0] rw

7 rw

22 rw

21 rw

Res.

SQ8[4:0] rw

4 rw

19 rw

3 rw

18 rw

SQ5[4:0] rw

17 16

Res.

SQ7[4]

1 rw

0 rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SQ9[4:0]: 9th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 9th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 23 Reserved, must be kept at reset value.

Bits 22:18 SQ8[4:0]: 8th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 8th in the regular conversion sequence

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 17 Reserved, must be kept at reset value.

Bits 16:12 SQ7[4:0]: 7th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 7th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 11 Reserved, must be kept at reset value.

Bits 10:6 SQ6[4:0]: 6th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 6th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 5 Reserved, must be kept at reset value.

Bits 4:0 SQ5[4:0]: 5th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 5th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Some channels are not connected physically and must not be selected for conversion.

430/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Res.

15 rw

Note:

Address offset: 0x38

Reset value: 0x0000 0000

Res.

14 13

SQ12[3:0] rw rw

28 rw

12 rw

27 rw

Res.

SQ14[4:0] rw

10 rw

25 rw

9 rw

24 23

Res.

SQ11[4:0] rw

7 rw

22 rw

6 rw

21 rw

Res.

SQ13[4:0] rw

4 rw

19 rw

3 rw

18 rw

SQ10[4:0] rw

17 16

Res.

SQ12[4]

1 rw

0 rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SQ14[4:0]: 14th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 14th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 23 Reserved, must be kept at reset value.

Bits 22:18 SQ13[4:0]: 13th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 13th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 17 Reserved, must be kept at reset value.

Bits 16:12 SQ12[4:0]: 12th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 12th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 11 Reserved, must be kept at reset value.

Bits 10:6 SQ11[4:0]: 11th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 11th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 5 Reserved, must be kept at reset value.

Bits 4:0 SQ10[4:0]: 10th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 10th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Some channels are not connected physically and must not be selected for conversion.

RM0471 Rev 5 431/1202

443

Analog-to-digital converter (ADC) RM0471

Res.

Address offset: 0x3C

Reset value: 0x0000 0000

Res.

Note:

Res.

10 rw

9 rw

SQ16[4:0] rw

7 rw

6 rw

Res.

4 rw

3 rw

SQ15[4:0] rw

1 rw

0 rw

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:6 SQ16[4:0]: 16th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 16th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 5 Reserved, must be kept at reset value.

Bits 4:0 SQ15[4:0]: 15th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 15th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Some channels are not connected physically and must not be selected for conversion.

Res.

Address offset: 0x40

Reset value: 0x0000 0000

Res.

15 14 13 12 11 10 9 8 7

RDATA[15:0] r r

6 5 4 3 2 1 0 r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 RDATA[15:0] : Regular data converted

These bits are read-only. They contain the conversion result from the last converted regular channel.

The data are left- or right-aligned as described in

Section 15.3.26: Data management .

432/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

15.5.16 ADC injected sequence register (ADC_JSQR)

Address offset: 0x4C

Reset value: 0x0000 0000

Res.

15 rw

JSQ2[1:0] rw rw

29 rw

Res.

JSQ4[4:0] rw

12 rw

27 rw

11 rw

26 25

Res.

JSQ1[4:0] rw

9 rw

24 rw

8 rw

23 rw

JSQ3[4:0] rw

JEXTEN[1:0] rw rw

21 rw

5 rw

20 19

Res.

4 3

JEXTSEL[3:0] rw rw

18 rw

2 rw

JSQ2[4:2] rw

16 rw

0 rw

JL[1:0] rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:26 JSQ4[4:0]: 4th conversion in the injected sequence

These bits are written by software with the channel number (0 to 18) assigned as the 4th in the injected conversion sequence.

Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that no injected conversion is ongoing).

Bit 25 Reserved, must be kept at reset value.

Bits 24:20 JSQ3[4:0]: 3rd conversion in the injected sequence

These bits are written by software with the channel number (0 to 18) assigned as the 3rd in the injected conversion sequence.

Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that no injected conversion is ongoing).

Bit 19 Reserved, must be kept at reset value.

Bits 18:14 JSQ2[4:0]: 2nd conversion in the injected sequence

These bits are written by software with the channel number (0 to 18) assigned as the 2nd in the injected conversion sequence.

Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that no injected conversion is ongoing).

Bit 13 Reserved, must be kept at reset value.

Bits 12:8 JSQ1[4:0]: 1st conversion in the injected sequence

These bits are written by software with the channel number (0 to 18) assigned as the 1st in the injected conversion sequence.

Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that no injected conversion is ongoing).

RM0471 Rev 5 433/1202

443

Analog-to-digital converter (ADC)

Note:

RM0471

Bits 7:6 JEXTEN[1:0] : External Trigger Enable and Polarity Selection for injected channels

These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group.

00: If JQDIS=0 (queue enabled), Hardware and software trigger detection disabled

00: If JQDIS=1 (queue disabled), Hardware trigger detection disabled (conversions can be launched by software)

01: Hardware trigger detection on the rising edge

10: Hardware trigger detection on the falling edge

11: Hardware trigger detection on both the rising and falling edges

Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that no injected conversion is ongoing).

If JQM=1 and if the Queue of Context becomes empty, the software and hardware triggers of the injected sequence are both internally disabled (refer to

Section 15.3.21:

Queue of context for injected conversions )

Bits 5:2 JEXTSEL[3:0] : External Trigger Selection for injected group

These bits select the external event used to trigger the start of conversion of an injected group:

0000: Event 0

0001: Event 1

0010: Event 2

0011: Event 3

0100: Event 4

0101: Event 5

0110: Event 6

0111: Event 7

...

1111: Event 15

Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that no injected conversion is ongoing).

Bits 1:0 JL[1:0]: Injected channel sequence length

These bits are written by software to define the total number of conversions in the injected channel conversion sequence.

00: 1 conversion

01: 2 conversions

10: 3 conversions

11: 4 conversions

Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that no injected conversion is ongoing).

Some channels are not connected physically and must not be selected for conversion.

434/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

offset register (ADC_OFRy)

Address offset: 0x60 + 0x04 * (y -1), (y= 1 to 4)

Reset value: 0x0000 0000

OFFSETy

_EN rw

Res.

30 29 28 rw

14 rw

13 rw

Res.

OFFSETy_CH[4:0] rw

11 rw

26 rw

10 rw

Res.

9 rw

Res.

8 rw

Res.

7 rw

Res.

6 5

OFFSETy[11:0] rw rw

Res.

4 rw

Res.

3 rw

Res.

2 rw

Res.

1 rw

Res.

0 rw

Bit 31 OFFSETy_EN: Offset y enable

This bit is written by software to enable or disable the offset programmed into bits

OFFSETy[11:0].

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0

(which ensures that no conversion is ongoing).

Bits 30:26 OFFSETy_CH[4:0]: Channel selection for the data offset y

These bits are written by software to define the channel to which the offset programmed into bits OFFSETy[11:0] will apply.

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0

(which ensures that no conversion is ongoing).

Some channels are not connected physically and must not be selected for the data offset y.

Bits 25:12 Reserved, must be kept at reset value.

Bits 11:0 OFFSETy[11:0]: Data offset y for the channel programmed into bits OFFSETy_CH[4:0]

These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion).

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0

(which ensures that no conversion is ongoing).

If several offset (OFFSETy) point to the same channel, only the offset with the lowest x value is considered for the subtraction.

Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[11:0] which is subtracted when converting channel 4.

RM0471 Rev 5 435/1202

443

Analog-to-digital converter (ADC) RM0471

15.5.18 ADC injected channel y data register (ADC_JDRy)

Address offset: 0x80 + 0x04 * (y - 1), (y = 1 to 4)

Reset value: 0x0000 0000

Res.

15 r

14 r

13 r

12 r

11 r

10 r

9 r

8 7 r

JDATA[15:0] r

6 r

5 r

4 r

3 r

2 r

1 r

0 r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 JDATA[15:0]: Injected data

These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in

Section 15.3.26: Data management .

15.5.19 ADC analog watchdog 2 configuration register (ADC_AWD2CR)

Address offset: 0xA0

Reset value: 0x0000 0000

Res.

14 13

Res.

18 17

AWD2CH[18:16]

16 rw

2 rw

1 rw

0 rw rw rw rw rw rw rw

8 7

AWD2CH[15:0] rw rw

6 rw rw rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 AWD2CH[18:0] : Analog watchdog 2 channel selection

These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2.

AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2

AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2

When AWD2CH[18:0] = 000..0, the analog watchdog 2 is disabled

Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers.

The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Some channels are not connected physically and must not be selected for the analog watchdog.

436/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

15.5.20 ADC analog watchdog 3 configuration register (ADC_AWD3CR)

Address offset: 0xA4

Reset value: 0x0000 0000

Res.

14 13

Res.

18 17

AWD3CH[18:16]

16 rw

2 rw

1 rw

0 rw rw rw rw rw rw rw

8 7

AWD3CH[15:0] rw rw rw rw rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 AWD3CH[18:0] : Analog watchdog 3 channel selection

These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3.

AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3

AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3

When AWD3CH[18:0] = 000..0, the analog watchdog 3 is disabled

Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers.

The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Some channels are not connected physically and must not be selected for the analog watchdog.

15.5.21 ADC differential mode selection register (ADC_DIFSEL)

Address offset: 0xB0

Reset value: 0x0000 0000

Res.

15 14 13 12 11 10 9 6 5 4 3

18 17

DIFSEL[18:16]

16 rw

2 rw

1 rw

0 rw rw rw rw rw rw rw

8 7

DIFSEL[15:0] rw rw rw rw rw rw rw rw r

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 DIFSEL[18:0] : Differential mode for channels 18 to 0.

These bits are set and cleared by software. They allow to select if a channel is configured as singleended or differential mode.

DIFSEL[i] = 0: ADC analog input channel is configured in single ended mode

DIFSEL[i] = 1: ADC analog input channel i is configured in differential mode

Note: The DIFSEL bits corresponding to channels that are either connected to a single-ended I/O port or to an internal channel must be kept their reset value (single-ended input mode).

The software is allowed to write these bits only when the ADC is disabled (ADCAL=0,

JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

RM0471 Rev 5 437/1202

443

Analog-to-digital converter (ADC) RM0471

Res.

Address offset: 0xB4

Reset value: 0x0000 0000

Res.

22 rw

21 rw

20 19 18

CALFACT_D[6:0] rw

4 rw

3 rw

2 rw

CALFACT_S[6:0] rw rw

17 rw

16 rw

0 rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 CALFACT_D[6:0] : Calibration Factors in differential mode

These bits are written by hardware or by software.

Once a differential inputs calibration is complete, they are updated by hardware with the calibration factors.

Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it will then be applied once a new differential calibration is launched.

Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0

(ADC is enabled and no calibration is ongoing and no conversion is ongoing).

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:0 CALFACT_S[6:0] : Calibration Factors In single-ended mode

These bits are written by hardware or by software.

Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors.

Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0

(ADC is enabled and no calibration is ongoing and no conversion is ongoing).

These registers define the control and status registers common to master and slave ADCs:

Address offset: 0x300

Reset value: 0x0000 0000

This register provides an image of the status bits of the different ADCs. Nevertheless it is read-only and does not allow to clear the different status bits. Instead each status bit must be cleared by writing 0 to it in the corresponding ADC_ISR register.

438/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

29 31 30 28 27

Res. Res. Res. Res. Res.

Res.

15 14 13 12 11

Res. Res. Res. Res. Res.

JQOVF_

MST r

AWD3_

MST r

AWD2_

MST r

AWD1_

MST r

JEOS_

MST r

JEOC_

MST r

OVR_

MST r

EOS_

MST r

EOC_

MST r

EOSMP_

MST r

ADRDY_

MST r

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 JQOVF_MST: Injected Context Queue Overflow flag of the master ADC

This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register.

Bit 9 AWD3_MST: Analog watchdog 3 flag of the master ADC

This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register.

Bit 8 AWD2_MST: Analog watchdog 2 flag of the master ADC

This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register.

Bit 7 AWD1_MST: Analog watchdog 1 flag of the master ADC

This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register.

Bit 6 JEOS_MST: End of injected sequence flag of the master ADC

This bit is a copy of the JEOS bit in the corresponding ADC_ISR register.

Bit 5 JEOC_MST: End of injected conversion flag of the master ADC

This bit is a copy of the JEOC bit in the corresponding ADC_ISR register.

Bit 4 OVR_MST: Overrun flag of the master ADC

This bit is a copy of the OVR bit in the corresponding ADC_ISR register.

Bit 3 EOS_MST: End of regular sequence flag of the master ADC

This bit is a copy of the EOS bit in the corresponding ADC_ISR register.

Bit 2 EOC_MST: End of regular conversion of the master ADC

This bit is a copy of the EOC bit in the corresponding ADC_ISR register.

Bit 1 EOSMP_MST: End of Sampling phase flag of the master ADC

This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register.

Bit 0 ADRDY_MST: Master ADC ready

This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register.

Address offset: 0x308

Reset value: 0x0000 0000

Res.

CH18S

EL rw

Res.

CH17SEL rw

Res.

VREF

EN rw

Res.

21 rw

Res.

20 19

PRESC[3:0] rw

Res.

18 rw

Res.

17 16

CKMODE[1:0] rw

Res.

RM0471 Rev 5 439/1202

443

Analog-to-digital converter (ADC) RM0471

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 CH18SEL : CH18 selection

This bit is set and cleared by software to control channel 18.

0: V

BAT

1: V

BAT

channel disabled.

channel enabled

Bit 23 CH17SEL : CH17 selection

This bit is set and cleared by software to control channel 17.

0: Temperature sensor channel disabled

1: Temperature sensor channel enabled

Bit 22 VREFEN : V

REFINT

enable

This bit is set and cleared by software to enable/disable the V

REFINT

0: V

REFINT

1: V

REFINT

channel disabled

channel enabled

channel.

Bits 21:18 PRESC[3:0] : ADC prescaler

These bits are set and cleared by software to select the frequency of the clock to the ADC.

The clock is common for all the ADCs.

0000: input ADC clock not divided

0001: input ADC clock divided by 2

0010: input ADC clock divided by 4

0011: input ADC clock divided by 6

0100: input ADC clock divided by 8

0101: input ADC clock divided by 10

0110: input ADC clock divided by 12

0111: input ADC clock divided by 16

1000: input ADC clock divided by 32

1001: input ADC clock divided by 64

1010: input ADC clock divided by 128

1011: input ADC clock divided by 256 other: reserved

Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL=0,

JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00.

Bits 17:16 CKMODE[1:0]: ADC clock mode

These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs):

00: CK_ADCx (x=123) (Asynchronous clock mode), generated at product level (refer to

Section 6: Reset and clock control (RCC) )

01: HCLK/1 (Synchronous clock mode). This configuration must be enabled only if the AHB clock prescaler is set to 1 (HPRE[3:0] = 0xxx in RCC_CFGR register) and if the system clock has a 50% duty cycle.

10: HCLK/2 (Synchronous clock mode)

11: HCLK/4 (Synchronous clock mode)

In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion.

Note: The software is allowed to write these bits only when the ADCs are disabled

(ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

Bits 15:0 Reserved, must be kept at reset value.

440/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

15.7 ADC register map

Table 76. ADC register map and reset values

Offset Register

31 30

0x00

0x04

ADC_ISR

Reset value

ADC_IER

Reset value

0 0 0 0 0 0 0 0 0 0 0

0x08

ADC_CR

0x0C

0x10

0x14

0x18

0x1C

0x20

0x24

0x28

0x2C

0x30

0x34

0x38

0x3C

0x40

0x44-

0x48

Reset value

ADC_CFGR

0 0 1 0

AWD1CH[4:0]

DISCNUM

[2:0]

0 0 0 0 0 0

RES

[1:0]

Reset value

ADC_CFGR2

Reset value

ADC_SMPR1

Reset value

ADC_SMPR2

Reset value

Reserved

ADC_TR1

Reset value

ADC_TR2

Reset value

ADC_TR3

Reset value

Reserved

ADC_SQR1

Reset value

ADC_SQR2

Reset value

ADC_SQR3

Reset value

ADC_SQR4

Reset value

ADC_DR

Reset value

Reserved

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OVSS[3:0]

OVSR

[2:0]

0 0

SMP9

[2:0]

SMP8

[2:0]

SMP7

[2:0]

SMP6

[2:0]

SMP5

[2:0]

SMP4

[2:0]

0 0 0 0 0 0 0 0 0 0 0

SMP3

[2:0]

SMP2

[2:0]

SMP1

[2:0]

SMP0

[2:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SMP18

[2:0]

SMP17

[2:0]

SMP16

[2:0]

SMP15

[2:0]

SMP14

[2:0]

SMP13

[2:0]

SMP12

[2:0]

SMP11

[2:0]

SMP10

[2:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Res.

HT1[11:0] LT1[11:0]

1 1 1 1 1 1 1 1 1 1 1 1

HT2[[7:0]

0 0 0 0 0 0 0 0 0

LT2[7:0]

0 0 0

1 1 1 1 1 1 1 1

HT3[[7:0]

1 1 1 1 1 1 1 1

Res.

SQ3[4:0] SQ2[4:0]

LT3[7:0]

SQ4[4:0]

0 0 0 0 0

SQ9[4:0]

0 0 0 0 0

SQ14[4:0]

0 0 0 0

SQ8[4:0]

SQ13[4:0]

0 0 0 0 0

SQ7[4:0]

SQ12[4:0]

SQ1[4:0]

0 0 0 0 0

SQ6[4:0]

0 0 0 0 0

SQ11[4:0]

0 0 0 0

SQ16[4:0]

0 0 0 0 0

L[3:0]

0 0 0 0

SQ5[4:0]

0 0 0 0 0

SQ10[4:0]

SQ15[4:0]

0 regular RDATA[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Res.

RM0471 Rev 5 441/1202

443

Analog-to-digital converter (ADC) RM0471

Offset Register

Table 76. ADC register map and reset values (continued)

31 30

0x4C

ADC_JSQR JSQ4[4:0]

0x50-

0x5C

Reset value

Reserved

0 0 0 0 0

0x60

ADC_OFR1

OFFSET1_

CH[4:0]

Reset value 0 0 0 0 0 0

ADC_OFR2

OFFSET2_

CH[4:0]

0x64

Reset value 0 0 0 0 0 0

ADC_OFR3

OFFSET3_

CH[4:0]

0x68

Reset value 0 0 0 0 0 0

0x6C

ADC_OFR4

OFFSET4_

CH[4:0]

0x70-

0x7C

0x80

0x84

0x88

0x8C

0x8C-

0x9C

0xA0

0xA4

Reset value

Reserved

ADC_JDR1

Reset value

ADC_JDR2

Reset value

ADC_JDR3

Reset value

ADC_JDR4

Reset value

Reserved

ADC_AWD2CR

Reset value

ADC_AWD3CR

Reset value

0 0 0 0 0 0

0xA8-

0xAC

Reserved

0xB0

ADC_DIFSEL

Reset value

JSQ3[4:0]

0 0 0 0 0

JSQ2[4:0]

0 0 0 0 0

Res.

JSQ1[4:0]

JEXTSEL

[3:0]

JL[1:0]

0 0 0 0 0 0 0 0 0 0 0 0 0

OFFSET1[11:0]

0 0 0 0 0 0 0 0 0 0 0 0

OFFSET2[11:0]

0 0 0 0 0 0 0 0 0 0 0 0

OFFSET3[11:0]

0 0 0 0 0 0 0 0 0 0 0 0

OFFSET4[11:0]

0 0 0 0 0 0 0 0 0 0 0 0

Res.

JDATA1[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

JDATA2[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

JDATA3[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

JDATA4[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Res.

AWD2CH[18:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AWD3CH[18:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DIFSEL[18:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

442/1202 RM0471 Rev 5

RM0471 Analog-to-digital converter (ADC)

Table 76. ADC register map and reset values (continued)

Offset Register

0xB4

31 30

ADC_CALFACT

Reset value

CALFACT_D[6:0]

0 0 0 0 0 0 0

CALFACT_S[6:0]

0 0 0 0 0 0 0

Table 77. ADC register map and reset values (master and slave ADC common registers) offset = 0x300

Offset Register

0x00

ADC_CSR

0x04

Reset value

Reserved Res.

0 0 0 0 0 0 0 0 0 0 0

0x08

ADC_CCR PRESC[3:0]

Reset value 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 55 for the register boundary addresses.

RM0471 Rev 5 443/1202

443

True random number generator (RNG)

16 True random number generator (RNG)

RM0471

16.1 Introduction

The RNG is a true random number generator that provides full entropy outputs to the application as 32-bit samples. It is composed of a live entropy source (analog) and an internal conditioning component.

The RNG can be used to construct a NIST compliant Deterministic Random Bit Generator

(DRBG), acting as a live entropy source.

The RNG true random number generator has been tested using German BSI statistical tests of AIS-31 (T0 to T8).

16.2 RNG main features

 The RNG delivers 32-bit true random numbers, produced by an analog entropy source processed by a high quality conditioning stage.

 It produces four 32-bit random samples every 16x higher than 213 cycles (213 cycles otherwise).

------------

RNG

AHB clock cycles, if value is

 It allows embedded continuous basic health tests with associated error management

– Includes too low sampling clock detection and repetition count tests.

 It can be disabled to reduce power consumption.

 It has an AMBA AHB slave peripheral, accessible through 32-bit word single accesses only (else an AHB bus error is generated, and the write accesses are ignored).

444/1202 RM0471 Rev 5

RM0471

16.3 RNG functional description

True random number generator (RNG)

Figure 84

shows the RNG block diagram.

Figure 84. RNG block diagram rng_it

Conditioning logic

True RNG

AHB interface

Banked Registers control RNG_CR data

RNG_DR status

RNG_SR rng_clk

AHB clock domain

RNG clock domain

Fault detection

Clock checker

128-bit

Raw data shift reg

2-bit

Sampling &

Normalization (x 2) en_osc

Analog noise source 1

Analog noise source 2

Analog noise source

MSv42097V2

Table 78 describes a list of useful-to-know internal signals available at the RNG level, not at

the STM32 product level (on pads).

Signal name rng_it rng_hclk rng_clk

Table 78. RNG internal input/output signals

Signal type Description

Digital output RNG global interrupt request

Digital input

AHB clock

RNG dedicated clock, asynchronous to rng_hclk

RM0471 Rev 5 445/1202

456

True random number generator (RNG) RM0471

16.3.3 Random number generation

The true random number generator (RNG) delivers truly random data through its AHB interface at deterministic intervals. Within its boundary the RNG implements the entropy

source model pictured on Figure 85 .

It includes an analog noise source, a digitization stage with post-processing, a conditioning algorithm, a health monitoring block and two interfaces that are used to interact with the entropy source: GetEntropy and HealthTest.

Figure 85. Entropy source model

Error message

(HealthTest)

Output

(GetEntropy)

Note:

Heath tests

Conditioning

Raw data

Post-processing

Digitization

Noise Source

Entropy source

MSv42099V2

The components pictured above are detailed hereafter:

Noise source

The noise source is the component that contains the non-deterministic, entropy-providing activity that is ultimately responsible for the uncertainty associated with the bitstring output by the entropy source. It is composed of:

 Two analog noise sources, each based on three XORed free-running ring oscillator outputs. It is possible to disable those analog oscillators to save power, as described in

Section 16.3.8: RNG low-power usage .

 A sampling stage of these outputs clocked by a dedicated clock input ( rng_clk ), delivering a 2-bit raw data output.

This noise source sampling is independent to the AHB interface clock frequency ( rng_hclk ).

Section 16.6: RNG entropy source validation

recommended RNG clock frequencies are given.

446/1202 RM0471 Rev 5

RM0471

Note:

True random number generator (RNG)

Post processing

The sample values obtained from a true random noise source consist of 2-bit bitstrings.

Because this noise source output is biased, the RNG implements a post-processing component that reduces that bias to a tolerable level.

More specifically, for each of the two noise source bits the RNG takes half of the bits from the sampled noise source, and half of the bits from inverted sampled noise source. Thus, if the source generates more ‘1’ than ‘0’ (or the opposite), it is filtered

Conditioning

The conditioning component in the RNG is a deterministic function that increases the entropy rate of the resulting fixed-length bitstrings output (128-bit).

Also note that post-processing computations are triggered when at least 32 bits of raw data are received and when output FIFO needs a refill. Thus the RNG output entropy is maximum when the RNG 128-bit FIFO is emptied by application after 64 RNG clock cycles.

The times required between two random number generations, and between the RNG

initialization and availability of first sample are described in Section 16.5: RNG processing time

The conditioning component is clocked by the faster AHB clock.

Output buffer

A data output buffer can store up to four 32-bit words which have been output from the conditioning component. When four words have been read from the output FIFO through the RNG_DR register, the content of the 128-bit conditioning output register is pushed into the output FIFO, and a new conditioning round is automatically started. Four new words are added to the conditioning output register 213 AHB clock cycles later.

Whenever a random number is available through the RNG_DR register the DRDY flag transitions from 0 to 1. This flag remains high until output buffer becomes empty after reading four words from the RNG_DR register.

When interrupts are enabled an interrupt is generated when this data ready flag transitions from 0 to 1. Interrupt is then cleared automatically by the RNG as explained above.

RM0471 Rev 5 447/1202

456

True random number generator (RNG)

Note:

RM0471

Health checks

This component ensures that the entire entropy source (with its noise source) starts then operates as expected, obtaining assurance that failures are caught quickly and with a high probability and reliability.

The RNG implements the following health check features.

Continuous health tests, running indefinitely on the output of the noise source

– Repetition count test, flagging an error when: a) One of the noise source has provided more than 64 consecutive bits at a constant value (“0” or “1”), or more than 32 consecutive occurrence of two bits patterns

(“01” or “10”) b) Both noise sources have delivered more than 32 consecutive bits at a constant value (“0” or “1”), or more than 16 consecutive occurrence of two bits patterns

(“01” or “10”)

2. Vendor specific continuous test

– Real-time “too slow” sampling clock detector, flagging an error when one RNG clock cycle is smaller than AHB clock cycle divided by 32.

The CECS and SECS status bits in the RNG_SR register indicate when an error condition is

detected, as detailed in Section 16.3.7: Error management

An interrupt can be generated when an error is detected.

The RNG simplified state machine is pictured on

Figure 86

After enabling the RNG (RNGEN = 1 in RNG_CR) the following chain of events occurs:

The analog noise source is enabled, and logic immediately starts sampling the analog output, filling 128-bit conditioning shift register

2. The conditioning logic is enabled and post-processing context is initialized using two

128 noise source bits.

3. The conditioning stage internal input data buffer is filled again with 128-bit and one conditioning round is performed. The output buffer is then filled with post processing result.

4. The output buffer is refilled automatically according to the RNG usage.

448/1202 RM0471 Rev 5

RM0471 True random number generator (RNG)

The associated initialization time can be found in

Section 16.5: RNG processing time .

Figure 86. RNG initialization overview

RNGEN=0, then

RNGEN=1

Noise source enable

Conditioning hardware init

Drop samples then check again

Error state

Generate samples

Continuous test(s) not OK

MSv44203V3

Normal operations

To run the RNG using interrupts, the following steps are recommended:

Enable the interrupts by setting the IE bit in the RNG_CR register. At the same time enable the RNG by setting the bit RNGEN=1.

2. An interrupt is now generated when a random number is ready or when an error occurs. Therefore at each interrupt, check that:

– No error occurred. The SEIS and CEIS bits must be set to 0 in the RNG_SR register.

– A random number is ready. The DRDY bit must be set to 1 in the RNG_SR register.

– If above two conditions are true the content of the RNG_DR register can be read up to four consecutive times. If valid data is available in the conditioning output buffer, four additional words can be read by the application (in this case the DRDY bit is still high). If one or both of above conditions are false, the RNG_DR register must not be read. If an error occurred error recovery sequence described in

Section 16.3.7

must be used.

RM0471 Rev 5 449/1202

456

True random number generator (RNG)

Note:

RM0471

To run the RNG in polling mode following steps are recommended:

Enable the random number generation by setting the RNGEN bit to “1” in the RNG_CR register.

2. Read the RNG_SR register and check that:

– No error occurred (the SEIS and CEIS bits must be set to 0)

– A random number is ready (the DRDY bit must be set to 1)

3. If above conditions are true read the content of the RNG_DR register up to four consecutive times. If valid data is available in the conditioning output buffer four additional words can be read by the application (in this case the DRDY bit is still high).

If one or both of above conditions are false, the RNG_DR register must not be read. If an error occurred error recovery sequence described in

Section 16.3.7

must be used.

When data is not ready (DRDY = 0) RNG_DR returns zero.

It is recommended to always verify that RNG_DR is different from zero. Because when it is the case a seed error occurred between RNG_SR polling and RND_DR output reading (rare event).

Low-power operations

If the power consumption is a concern to the application, low-power strategies can be used, as described in

Section 16.3.8: RNG low-power usage .

Software post-processing

If a NIST approved DRBG with 128 bits of security strength is required an approved random generator software must be built around the RNG true random number generator.

Built-in health check functions are described in

Section 16.3.3: Random number generation .

Note:

The RNG runs on two different clocks: the AHB bus clock and a dedicated RNG clock.

The AHB clock is used to clock the AHB banked registers and conditioning component. The

RNG clock is used for noise source sampling. Recommended clock configurations are

detailed in Section 16.6: RNG entropy source validation

When the CED bit in the RNG_CR register is set to 0, the RNG clock frequency must be higher than AHB clock frequency divided by 32, otherwise the clock checker always flags a clock error (CECS = 1 in the RNG_SR register).

See

Section 16.3.1: RNG block diagram for details (AHB and RNG clock domains).

In parallel to random number generation an health check block verifies the correct noise source behavior and the frequency of the RNG source clock as detailed in this section.

Associated error state is also described.

Clock error detection

When the clock error detection is enabled (CED = 0) and if the RNG clock frequency is too low, the RNG sets to 1 both the CEIS and CECS bits to indicate that a clock error occurred.

In this case, the application should check that the RNG clock is configured correctly (see

450/1202 RM0471 Rev 5

RM0471 True random number generator (RNG)

Note:

Section 16.3.6: RNG clocking ) and then it must clear the CEIS bit interrupt flag. The CECS

bit is automatically cleared when clocking condition is normal.

The clock error has no impact on generated random numbers, i.e. application can still read

RNG_DR register.

CEIS is set only when CECS is set to 1 by RNG.

Noise source error detection

When a noise source (or seed) error occurs, the RNG stops generating random numbers and sets to 1 both SEIS and SECS bits to indicate that a seed error occurred. If a value is available in the RNG_DR register, it must not be used as it may not have enough entropy. If the error was detected during the initialization phase the whole initialization sequenceis automatically restarted by the RNG.

The following sequence must be used to fully recover from a seed error after the RNG initialization:

Clear the SEIS bit by writing it to “0”.

2. Read out 12 words from the RNG_DR register, and discard each of them in order to clean the pipeline.

3. Confirm that SEIS is still cleared. Random number generation is back to normal.

16.3.8 RNG low-power usage

If power consumption is a concern, the RNG can be disabled as soon as the DRDY bit is set to 1 by setting the RNGEN bit to 0 in the RNG_CR register. As the post-processing logic and the output buffer remain operational while RNGEN = 0 following features are available to software:

 If there are valid words in the output buffer four random numbers can still be read from the RNG_DR register.

 If there are valid bits in the conditioning output internal register four additional random numbers can be still be read from the RNG_DR register. If it is not the case the RNG must be re-enabled by the application until at least 32 new bits are collected from the noise source and a complete conditioning round is done. It corresponds to 16 RNG clock cycles to sample new bits, and 216 AHB clock cycles to run a conditioning round.

When disabling the RNG the user deactivates all the analog seed generators, whose power consumption is given in the datasheet electrical characteristics section. The user also gates all the logic clocked by the RNG clock. Note that this strategy is adding latency before a random sample is available on the RNG_DR register, because of the RNG initialization time.

If the RNG block is disabled during initialization (i.e. well before the DRDY bit rises for the first time), the initialization sequence resumes from where it was stopped when RNGEN bit is set to 1.

RM0471 Rev 5 451/1202

456

True random number generator (RNG) RM0471

Interrupt acronym

RNG

In the RNG an interrupt can be produced on the following events:

 Data ready flag

 Seed error, see

Section 16.3.7: Error management

 Clock error, see

Section 16.3.7: Error management

Dedicated interrupt enable control bits are available as shown in Table 79

Table 79. RNG interrupt requests

Interrupt event Event flag Enable control bit

Data ready flag

Seed error flag

Clock error flag

DRDY

SEIS

CEIS

Interrupt clear method

None (automatic)

Write 0 to SEIS

Write 0 to CEIS

Note:

The user can enable or disable the above interrupt sources individually by changing the mask bits or the general interrupt control bit IE in the RNG_CR register. The status of the individual interrupt sources can be read from the RNG_SR register.

Interrupts are generated only when RNG is enabled.

16.5 RNG processing time

The conditioning stage can produce four 32-bit random numbers every 16x cycles, if the value is higher than 213 cycles (213 cycles otherwise). f f

------------

RNG

clock

More time is needed for the first set of random numbers after the device exits reset (see

Section 16.3.4: RNG initialization

). Indeed, after enabling the RNG for the first time, random data is first available after either:

 128 RNG clock cycles + 426 AHB cycles, if f

AHB

< f threshold

 192 RNG clock cycles + 213 AHB cycles, if f

AHB

≥ f threshold

With f threshold

= (213 x f

RNG

)/ 64

16.6 RNG entropy source validation

16.6.1 Introduction

In order to assess the amount of entropy available from the RNG, STMicroelectronics has tested the peripheral using German BSI AIS-31 statistical tests (T0 to T8).

452/1202

STMicroelectronics has tested the RNG true random number generator in the following conditions:

 RNG clock rng_clk= 48 MHz (CED bit = ’0’ in RNG_CR register) and rng_clk = 400 kHz

(CED bit = ‘1’ in RNG_CR register).

RM0471 Rev 5

RM0471 True random number generator (RNG)

The RNG is associated with a control register, a data register and a status register.

16.7.1 RNG control register (RNG_CR)

Address offset: 0x000

Reset value: 0x0000 0000

Res.

CED rw

Res.

IE rw

2 1

RNGEN Res.

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 CED: Clock error detection

0: Clock error detection is enable

1: Clock error detection is disable

The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is enabled, i.e. to enable or disable CED the RNG must be disabled.

Res.

Bit 4 Reserved, must be kept at reset value.

Bit 3 IE: Interrupt Enable

0: RNG Interrupt is disabled

1: RNG Interrupt is enabled. An interrupt is pending as soon as DRDY = 1, SEIS = 1 or

CEIS = 1 in the RNG_SR register.

Bit 2 RNGEN: True random number generator enable

0: True random number generator is disabled. Analog noise sources are powered off and logic clocked by the RNG clock is gated.

1: True random number generator is enabled.

Bits 1:0 Reserved, must be kept at reset value.

RM0471 Rev 5 453/1202

456

True random number generator (RNG) RM0471

16.7.2 RNG status register (RNG_SR)

Address offset: 0x004

Reset value: 0x0000 0000

Res.

6 5

SEIS CEIS rc_w0 rc_w0

Res.

2 1 0

SECS CECS DRDY r r r

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 SEIS: Seed error interrupt status

This bit is set at the same time as SECS. It is cleared by writing 0. Writing 1 has no effect.

0: No faulty sequence detected

1: At least one faulty sequence is detected. See SECS bit description for details.

An interrupt is pending if IE = 1 in the RNG_CR register.

Bit 5 CEIS: Clock error interrupt status

This bit is set at the same time as CECS. It is cleared by writing 0. Writing 1 has no effect.

0: The RNG clock is correct (fRNGCLK> fHCLK/32)

1: The RNG is detected too slow (fRNGCLK< fHCLK/32)

An interrupt is pending if IE = 1 in the RNG_CR register.

Bits 4:3 Reserved, must be kept at reset value.

Bit 2 SECS: Seed error current status

0: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered.

1: At least one of the following faulty sequence has been detected:

– One of the noise source has provided more than 64 consecutive bits at a constant value (“0” or “1”), or more than 32 consecutive occurrence of two bit patterns (“01” or “10”)

– Both noise sources have delivered more than 32 consecutive bits at a constant value (“0” or “1”), or more than 16 consecutive occurrence of two bit patterns (“01” or “10”)

Bit 1 CECS: Clock error current status

0: The RNG clock is correct (fRNGCLK> fHCLK/32). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered.

1: The RNG clock is too slow (fRNGCLK< fHCLK/32).

Note: CECS bit is valid only if the CED bit in the RNG_CR register is set to 0.

Bit 0 DRDY: Data Ready

0: The RNG_DR register is not yet valid, no random data is available.

1: The RNG_DR register contains valid random data.

Once the output buffer becomes empty (after reading the RNG_DR register), this bit returns to 0 until a new random value is generated.

Note: The DRDY bit can rise when the peripheral is disabled (RNGEN = 0 in the RNG_CR register).

If IE=1 in the RNG_CR register, an interrupt is generated when DRDY = 1.

454/1202 RM0471 Rev 5

RM0471 True random number generator (RNG)

16.7.3 RNG data register (RNG_DR)

Address offset: 0x008

Reset value: 0x0000 0000

The RNG_DR register is a read-only register that delivers a 32-bit random value when read.

After being read this register delivers a new random value after 216 periods of AHB clock if the output FIFO is empty.

The content of this register is valid when DRDY = 1 and value is not 0x0, even if

RNGEN = 0.

31 r

15 r

30 29 r

14 r r

28 r

27 r

26 r

25 r

24 23

RNDATA[31:16] r

8 r

RNDATA[15:0] r r

22 r

21 r

20 r

19 r

18 r

17 r

16 r

0 r r r r r r r r r r r r

Bits 31:0 RNDATA[31:0]: Random data

32-bit random data which are valid when DRDY = 1. When DRDY = 0 RNDATA value is zero.

It is recommended to always verify that RNG_DR is different from zero. Because when it is the case a seed error occurred between RNG_SR polling and RND_DR output reading

(rare event).

RM0471 Rev 5 455/1202

456

True random number generator (RNG) RM0471

Table 80 gives the RNG register map and reset values.

Table 80. RNG register map and reset map

Offset Register name

0x000

RNG_CR

0x004

0x008

Reset value

RNG_SR

0 0 0

Reset value

RNG_DR RNDATA[31:0]

0 0 0 0 0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2

for the register boundary addresses.

456/1202 RM0471 Rev 5

RM0471

17 AES hardware accelerator (AES)

AES hardware accelerator (AES)

17.1 Introduction

The AES hardware accelerator (AES) encrypts or decrypts data, using an algorithm and implementation fully compliant with the advanced encryption standard (AES) defined in

Federal information processing standards (FIPS) publication 197.

The peripheral supports CTR, GCM, GMAC, CCM, ECB, and CBC chaining modes for key sizes of 128 or 256 bits.

AES is an AMBA AHB slave peripheral accessible through 32-bit single accesses only.

Other access types generate an AHB error, and other than 32-bit writes may corrupt the register content.

The peripheral supports DMA single transfers for incoming and outgoing data (two DMA channels required).

17.2 AES main features

 Compliance with NIST “Advanced encryption standard (AES) , FIPS publication 197 ” from November 2001

 128-bit data block processing

 Support for cipher key lengths of 128-bit and 256-bit

 Encryption and decryption with multiple chaining modes:

– Electronic codebook (ECB) mode

– Cipher block chaining (CBC) mode

– Counter (CTR) mode

– Galois counter mode (GCM)

– Galois message authentication code (GMAC) mode

– Counter with CBC-MAC (CCM) mode

 51 or 75 clock cycle latency in ECB mode for processing one 128-bit block of data with, respectively, 128-bit or 256-bit key

 Integrated round key scheduler to compute the last round key for ECB/CBC decryption

 AMBA AHB slave peripheral, accessible through 32-bit word single accesses only

 256-bit register for storing the cryptographic key (eight 32-bit registers)

 128-bit register for storing initialization vector (four 32-bit registers)

 32-bit buffer for data input and output

 Automatic data flow control with support of single-transfer direct memory access (DMA) using two channels (one for incoming data, one for processed data)

 Data-swapping logic to support 1-, 8-, 16- or 32-bit data

 Possibility for software to suspend a message if AES needs to process another message with a higher priority, then resume the original message

RM0471 Rev 5 457/1202

505

AES hardware accelerator (AES)

The devices have one AES peripheral, AES2.

RM0471

Figure 87

shows the block diagram of AES.

Figure 87. AES block diagram

32-bit

AHB bus aes_hclk aes_in_dma aes_out_dma aes_it

AES

AHB interface

32-bit access key

IV, counter status control data in data out

Banked registers

AES_KEYRx

AES_IVRx

AES_SR

AES_CR

AES_DINR

AES_DOUTR

AES_SUSPRx

DMA interface

IRQ interface

Control Logic

KEY

IVI

DIN

DOUT

Save / Restore swap AES

Core

(AEA)

MSv42154V1

Table 81 describes the user relevant internal signals interfacing the AES peripheral.

Signal name aes_hclk aes_it aes_in_dma aes_out_dma

Table 81. AES internal input/output signals

Signal type Description

Input

Output

AHB bus clock

AES interrupt request

Input/Output Input DMA single request/acknowledge

Input/Output Output DMA single request/acknowledge

458/1202 RM0471 Rev 5

RM0471 AES hardware accelerator (AES)

Note:

Overview

The AES cryptographic core consists of the following components:

 AES core algorithm (AEA)

 multiplier over a binary Galois field (GF2mul)

 key input

 initialization vector (IV) input

 chaining algorithm logic (XOR, feedback/counter, mask)

The AES core works on 128-bit data blocks (four words) with 128-bit or 256-bit key length.

Depending on the chaining mode, the AES requires zero or one 128-bit initialization vector

IV.

The AES features the following modes of operation:

 Mode 1:

Plaintext encryption using a key stored in the AES_KEYRx registers

 Mode 2:

ECB or CBC decryption key preparation. It must be used prior to selecting Mode 3 with

ECB or CBC chaining modes. The key prepared for decryption is stored automatically in the AES_KEYRx registers. Now the AES peripheral is ready to switch to Mode 3 for executing data decryption.

 Mode 3:

Ciphertext decryption using a key stored in the AES_KEYRx registers. When ECB and

CBC chaining modes are selected, the key must be prepared beforehand, through

Mode 2.

 Mode 4:

ECB or CBC ciphertext single decryption using the key stored in the AES_KEYRx registers (the initial key is derived automatically).

Mode 2 and mode 4 are only used when performing ECB and CBC decryption.

When Mode 4 is selected only one decryption can be done, therefore usage of Mode 2 and

Mode 3 is recommended instead.

The operating mode is selected by programming the MODE[1:0] bitfield of the AES_CR register. It may be done only when the AES peripheral is disabled.

Typical data processing

Typical usage of the AES is described in

Section 17.4.4: AES procedure to perform a cipher operation on page 464 .

The outputs of the intermediate AEA stages are never revealed outside the cryptographic boundary, with the exclusion of the IVI bitfield.

RM0471 Rev 5 459/1202

505

AES hardware accelerator (AES)

Note:

RM0471

Chaining modes

The following chaining modes are supported by AES, selected through the CHMOD[2:0] bitfield of the AES_CR register:

 Electronic code book (ECB)

 Cipher block chaining (CBC)

 Counter (CTR)

 Galois counter mode (GCM)

 Galois message authentication code (GMAC)

 Counter with CBC-MAC (CCM)

The chaining mode may be changed only when AES is disabled (bit EN of the AES_CR register cleared).

Principle of each AES chaining mode is provided in the following subsections.

Detailed information is in dedicated sections, starting from Section 17.4.8: AES basic chaining modes (ECB, CBC) .

Electronic codebook (ECB) mode

Figure 88. ECB encryption and decryption principle

Plaintext block 1

Encryption

Plaintext block 2 Plaintext block 3 key

Encrypt key

Encrypt

Note:

Ciphertext block 1 Ciphertext block 2

Decryption

Plaintext block 2

Ciphertext block 3

Plaintext block 1 Plaintext block 3

Legend input output key scheduling key

Decrypt key

Decrypt

Ciphertext block 1 Ciphertext block 2 Ciphertext block 3

MSv42140V1

ECB is the simplest mode of operation. There are no chaining operations, and no special initialization stage. The message is divided into blocks and each block is encrypted or decrypted separately.

For decryption, a special key scheduling is required before processing the first block.

460/1202 RM0471 Rev 5

RM0471 AES hardware accelerator (AES)

Cipher block chaining (CBC) mode

Figure 89. CBC encryption and decryption principle

Encryption

Plaintext block 2 Plaintext block 3 Plaintext block 1 initialization vector key

Encrypt key

Encrypt

Note:

Ciphertext block 1 Ciphertext block 2 Ciphertext block 3

Legend input output key scheduling

Plaintext block 1 initialization vector key

Decrypt

Ciphertext block 1

Decryption

Plaintext block 2 key

Decrypt key

Plaintext block 3

Decrypt

Ciphertext block 2 Ciphertext block 3

MSv42141V1

In CBC mode the output of each block chains with the input of the following block. To make each message unique, an initialization vector is used during the first block processing.

For decryption, a special key scheduling is required before processing the first block.

RM0471 Rev 5 461/1202

505

AES hardware accelerator (AES)

Counter (CTR) mode

Figure 90. CTR encryption and decryption principle

Counter value

Encryption

Counter value + 1

+1 Counter value + 2 key

Encrypt key

Encrypt

Plaintext block 1 Plaintext block 2

Ciphertext block 1

Plaintext block 3

Ciphertext block 2 Ciphertext block 3

Note:

RM0471

Counter value

Decryption

Counter value + 1

+1 Counter value + 2

Legend input output

XOR key

Decrypt key

Decrypt

Plaintext block 1 Plaintext block 2

Ciphertext block 1

Plaintext block 3

Ciphertext block 2 Ciphertext block 3

MSv42142V1

The CTR mode uses the AES core to generate a key stream. The keys are then XOR-ed with the plaintext to obtain the ciphertext as specified in NIST Special Publication 800-38A,

Recommendation for Block Cipher Modes of Operation .

Unlike with ECB and CBC modes, no key scheduling is required for the CTR decryption, since in this chaining scheme the AES core is always used in encryption mode for producing the key stream, or counter blocks.

462/1202 RM0471 Rev 5

RM0471 AES hardware accelerator (AES)

Galois/counter mode (GCM)

Figure 91. GCM encryption and authentication principle

Initialization vector

Counter value

+1 Counter value + 1

+1 Counter value + 2 key Init

(Encrypt) key

Encrypt key

Encrypt

Plaintext block 1 Plaintext block 2

Ciphertext block 1

Plaintext block 3

Ciphertext block 2 Ciphertext block 3

Legend input output

XOR

GF2mul GF2mul GF2mul

Final TAG

MSv42143V1

In Galois/counter mode (GCM), the plaintext message is encrypted while a message authentication code (MAC) is computed in parallel, thus generating the corresponding ciphertext and its MAC (also known as authentication tag). It is defined in NIST Special

Publication 800-38D, Recommendation for Block Cipher Modes of Operation -

Galois/Counter Mode (GCM) and GMAC.

GCM mode is based on AES in counter mode for confidentiality. It uses a multiplier over a fixed finite field for computing the message authentication code. It requires an initial value and a particular 128-bit block at the end of the message.

Galois message authentication code (GMAC) principle

Figure 92. GMAC authentication principle

Initialization vector key Init

(Encrypt)

Plaintext block 1 Plaintext block 2 Plaintext block 3

Legend

GF2mul GF2mul GF2mul input output

Final TAG

XOR

MSv42144V1

Galois message authentication code (GMAC) allows authenticating a message and generating the corresponding message authentication code (MAC). It is defined in NIST

Special Publication 800-38D, Recommendation for Block Cipher Modes of Operation -

Galois/Counter Mode (GCM) and GMAC.

RM0471 Rev 5 463/1202

505

AES hardware accelerator (AES) RM0471

GMAC is similar to GCM, except that it is applied on a message composed only by plaintext authenticated data (that is, only header, no payload).

Counter with CBC-MAC (CCM) principle

Figure 93. CCM encryption and authentication principle

B0 Count 1 +1 Count 2 +1 Count 3 key Init

(Encrypt) key

Encrypt key

Encrypt

Initialization vector

Plaintext block 1 Plaintext block 2

Ciphertext block 1

Plaintext block 3

Ciphertext block 2 Ciphertext block 3

Legend input output

XOR key

Encrypt Encrypt Encrypt

Final TAG

MSv42145V1

In Counter with cipher block chaining-message authentication code (CCM) mode, the plaintext message is encrypted while a message authentication code (MAC) is computed in parallel, thus generating the corresponding ciphertext and the corresponding MAC (also known as tag). It is described by NIST in Special Publication 800-38C, Recommendation for

Block Cipher Modes of Operation - The CCM Mode for Authentication and Confidentiality .

CCM mode is based on AES in counter mode for confidentiality and it uses CBC for computing the message authentication code. It requires an initial value.

Like GCM, the CCM chaining mode can be applied on a message composed only by plaintext authenticated data (that is, only header, no payload). Note that this way of using

CCM is not called CMAC (it is not similar to GCM/GMAC), and its use is not recommended by NIST.

17.4.4 AES procedure to perform a cipher operation

Introduction

A typical cipher operation is explained below. Detailed information is provided in sections

starting from Section 17.4.8: AES basic chaining modes (ECB, CBC)

464/1202 RM0471 Rev 5

RM0471

Note:

AES hardware accelerator (AES)

Initialization of AES

To initialize AES, first disable it by clearing the EN bit of the AES_CR register. Then perform the following steps in any order:

 Configure the AES mode, by programming the MODE[1:0] bitfield of the AES_CR register.

– For encryption, select Mode 1 (MODE[1:0] = 00).

– For decryption, select Mode 3 (MODE[1:0] = 10), unless ECB or CBC chaining modes are used. In this latter case, perform an initial key derivation of the encryption key, as described in

Section 17.4.5: AES decryption round key preparation .

 Select the chaining mode, by programming the CHMOD[2:0] bitfield of the AES_CR register.

 Configure the data type (1-, 8-, 16- or 32-bit), with the DATATYPE[1:0] bitfield in the

AES_CR register.

 When it is required (for example in CBC or CTR chaining modes), write the initialization vector into the AES_IVRx registers.

 Configure the key size (128-bit or 256-bit), with the KEYSIZE bitfield of the AES_CR register.

 Write a symmetric key into the AES_KEYRx registers (4 or 8 registers depending on the key size).

Data append

This section describes different ways of appending data for processing, where the size of data to process is not a multiple of 128 bits.

For ECB or CBC mode, refer to Section 17.4.6: AES ciphertext stealing and data padding

The last block management in these cases is more complex than in the sequence described in this section.

Data append through polling

This method uses flag polling to control the data append through the following sequence:

Enable the AES peripheral by setting the EN bit of the AES_CR register.

2. Repeat the following sub-sequence until the payload is entirely processed: a) Write four input data words into the AES_DINR register.

b) Wait until the status flag CCF is set in the AES_SR, then read the four data words from the AES_DOUTR register.

c) Clear the CCF flag, by setting the CCFC bit of the AES_CR register.

d) If the data block just processed is the second-last block of the message and the significant data in the last block to process is inferior to 128 bits, pad the remainder of the last block with zeros and, in case of GCM payload encryption or

CCM payload decryption, specify the number of non-valid bytes, using the NPBLB bitfield of the AES_CR register, for AES to compute a correct tag;.

3. As it is the last block, discard the data that is not part of the data, then disable the AES peripheral by clearing the EN bit of the AES_CR register.

Up to three wait cycles are automatically inserted between two consecutive writes to the

AES_DINR register, to allow sending the key to the AES processor.

NPBLB bits are not used in header phase of GCM, GMAC and CCM chaining modes.

RM0471 Rev 5 465/1202

505

AES hardware accelerator (AES)

Note:

RM0471

Data append using interrupt

The method uses interrupt from the AES peripheral to control the data append, through the following sequence:

Enable interrupts from AES by setting the CCFIE bit of the AES_CR register.

2. Enable the AES peripheral by setting the EN bit of the AES_CR register.

4. Handle the data in the AES interrupt service routine, upon interrupt: a) Read four output data words from the AES_DOUTR register.

b) Clear the CCF flag and thus the pending interrupt, by setting the CCFC bit of the

AES_CR register.

c) If the data block just processed is the second-last block of an message and the significant data in the last block to process is inferior to 128 bits, pad the remainder of the last block with zeros and, in case of GCM payload encryption or

CCM payload decryption, specify the number of non-valid bytes, using the NPBLB bitfield of the AES_CR register, for AES to compute a correct tag;. Then proceed with point 4e).

d) If the data block just processed is the last block of the message, discard the data that is not part of the data, then disable the AES peripheral by clearing the EN bit of the AES_CR register and quit the interrupt service routine.

e) Write next four input data words into the AES_DINR register and quit the interrupt service routine.

AES is tolerant of delays between consecutive read or write operations, which allows, for example, an interrupt from another peripheral to be served between two AES computations.

NPBLB bits are not used in header phase of GCM, GMAC and CCM chaining modes.

Data append using DMA

With this method, all the transfers and processing are managed by DMA and AES. To use the method, proceed as follows:

Prepare the last four-word data block (if the data to process does not fill it completely), by padding the remainder of the block with zeros.

2. Configure the DMA controller so as to transfer the data to process from the memory to the AES peripheral input and the processed data from the AES peripheral output to the

memory, as described in Section 17.4.16: AES DMA interface . Configure the DMA

controller so as to generate an interrupt on transfer completion. In case of GCM payload encryption or CCM payload decryption, DMA transfer must not include the last four-word block if padded with zeros. The sequence described in

Data append through polling

must be used instead for this last block, because NPBLB bits must be setup before processing the block, for AES to compute a correct tag.

3. Enable the AES peripheral by setting the EN bit of the AES_CR register

4. Enable DMA requests by setting the DMAINEN and DMAOUTEN bits of the AES_CR register.

5. Upon DMA interrupt indicating the transfer completion, get the AES-processed data from the memory.

The CCF flag has no use with this method, because the reading of the AES_DOUTR register is managed by DMA automatically, without any software action, at the end of the computation phase.

NPBLB bits are not used in header phase of GCM, GMAC, and CCM chaining modes.

466/1202 RM0471 Rev 5

RM0471 AES hardware accelerator (AES)

17.4.5 AES decryption round key preparation

Note:

Internal key schedule is used to generate AES round keys. In AES encryption, the round 0 key is the one stored in the key registers. AES decryption must start using the last round key. As the encryption key is stored in memory, a special key scheduling must be performed to obtain the decryption key. This key scheduling is only required for AES decryption in ECB and CBC modes.

Recommended method is to select the Mode 2 by setting to 01 the MODE[1:0] bitfield of the

AES_CR (key process only), then proceed with the decryption by setting MODE[1:0] to 10

(Mode 3, decryption only). Mode 2 usage is described below:

Disable the AES peripheral by clearing the EN bit of the AES_CR register.

2. Select Mode 2 by setting to 01 the MODE[1:0] bitfield of the AES_CR. The

CHMOD[2:0] bitfield is not significant in this case because this key derivation mode is independent of the chaining algorithm selected.

3. Set key length to 128 or 256 bits, via KEYSIZE bit of AES_CR register.

4. Write the AES_KEYRx registers (128 or 256 bits) with encryption key, as shown in

Figure 94

. Writes to the AES_IVRx registers have no effect.

5. Enable the AES peripheral, by setting the EN bit of the AES_CR register.

6. Wait until the CCF flag is set in the AES_SR register.

7. Clear the CCF flag. Derived key is available in AES core, ready to use for decryption.

Application can also read the AES_KEYRx register to obtain the derived key if needed,

as shown in Figure 94 (the processed key is loaded automatically into the AES_KEYRx

registers).

The AES is disabled by hardware when the derivation key is available.

To restart a derivation key computation, repeat steps

4 , 5 , 6

, and

Figure 94. Encryption key derivation for ECB/CBC decryption (Mode 2)

Note:

EK3

MSB

EK2

EK1

EK0

LSB

Wait until flag CCF = 1

DK3

MSB

DK2

DK1

DK0

LSB

Input phase

4 write operations into

AES_KEYRx[31:0]

Computation phase

Output phase (optional)

4 read operations of

AES_KEYRx[31:0]

EN = 1 into AES_CR 128-bit derivation key stored into AES_KEYRx

EK = encryption key = 4 words (EK3, … , EK0)

DK = decryption key = 4 words (DK3, … , DK0)

MS18937V2

If the software stores the initial key prepared for decryption, it is enough to do the key schedule operation only once for all the data to be decrypted with a given cipher key.

The operation of the key preparation lasts 59 or 82 clock cycles, depending on the key size

(128- or 256-bit).

RM0471 Rev 5 467/1202

505

AES hardware accelerator (AES) RM0471

17.4.6 AES ciphertext stealing and data padding

Note:

When using AES in ECB or CBC modes to manage messages the size of which is not a multiple of the block size (128 bits), ciphertext stealing techniques are used, such as those described in NIST Special Publication 800-38A, Recommendation for Block Cipher Modes of Operation: Three Variants of Ciphertext Stealing for CBC Mode . Since the AES peripheral does not support such techniques, the application must complete the last block of input data using data from the second last block.

Ciphertext stealing techniques are not documented in this reference manual.

Similarly, when AES is used in other modes than ECB or CBC, an incomplete input data block (that is, block with input data shorter than 128 bits) must be padded with zeros prior to encryption (that is, extra bits must be appended to the trailing end of the data string). After decryption, the extra bits must be discarded. As AES does not implement automatic data padding operation to the last block , the application must follow the recommendation given in

Section 17.4.4: AES procedure to perform a cipher operation on page 464

to manage messages the size of which is not a multiple of 128 bits.

Padding data are swapped in a similar way as normal data, according to the

DATATYPE[1:0] field of the AES_CR register (see Section 17.4.13: AES data registers and data swapping for details).

17.4.7 AES task suspend and resume

A message can be suspended if another message with a higher priority must be processed.

When this highest priority message is sent, the suspended message can resume in both encryption or decryption mode.

Suspend/resume operations do not break the chaining operation and the message processing can resume as soon as AES is enabled again to receive the next data block.

Figure 95

gives an example of suspend/resume operation: Message 1 is suspended in order to send a shorter and higher-priority Message 2.

Figure 95. Example of suspend mode management

Message 1

128-bit block 1

Message 2

New higher-priority message 2 to be processed

128-bit block 2

AES suspend sequence

128-bit block 3

128-bit block 1

128-bit block 2

128-bit block 4

128-bit block 5

128-bit block 6

...

AES resume sequence

MSv42148V1

468/1202 RM0471 Rev 5

RM0471 AES hardware accelerator (AES)

A detailed description of suspend/resume operations is in the sections dedicated to each

AES mode.

Overview

This section gives a brief explanation of the four basic operation modes provided by the

AES core: ECB encryption, ECB decryption, CBC encryption and CBC decryption. For detailed information, refer to the FIPS publication 197 from November 26, 2001.

Figure 96

illustrates the electronic codebook (ECB) encryption.

Figure 96. ECB encryption

Block 1

AES_DINR (plaintext P1)

Block 2

AES_DINR (plaintext P2)

DATATYPE[1:0]

AES_KEYRx (KEY)

Swap management

Encrypt

DATATYPE[1:0]

AES_KEYRx (KEY)

Swap management

Encrypt

Legend

DATATYPE[1:0]

Swap management

AES core

DATATYPE[1:0]

Swap management input output

AES_DOUTR (ciphertext C1) AES_DOUTR (ciphertext C2)

MSv19105V2

In ECB encrypt mode, the 128-bit plaintext input data block Px in the AES_DINR register first goes through bit/byte/half-word swapping. The swap result Ix is processed with the AES core set in encrypt mode, using a 128- or 256-bit key. The encryption result Ox goes through bit/byte/half-word swapping, then is stored in the AES_DOUTR register as 128-bit ciphertext output data block Cx. The ECB encryption continues in this way until the last complete plaintext block is encrypted.

Figure 97

illustrates the electronic codebook (ECB) decryption.

Figure 97. ECB decryption

Block 1

AES_DINR (ciphertext C1)

Block 2

AES_DINR (ciphertext C2)

DATATYPE[1:0]

AES_KEYRx (KEY)

Swap management

Decrypt

DATATYPE[1:0]

AES_KEYRx (KEY)

Swap management

Decrypt

Legend

DATATYPE[1:0]

Swap management

DATATYPE[1:0]

Swap management input output

AES_DOUTR (plaintext P1) AES_DOUTR (plaintext P2)

MSv19106V2

To perform an AES decryption in the ECB mode, the secret key has to be prepared by collecting the last-round encryption key (which requires to first execute the complete key schedule for encryption), and using it as the first-round key for the decryption of the ciphertext. This preparation is supported by the AES core.

RM0471 Rev 5 469/1202

505

AES hardware accelerator (AES) RM0471

In ECB decrypt mode, the 128-bit ciphertext input data block C1 in the AES_DINR register first goes through bit/byte/half-word swapping. The keying sequence is reversed compared to that of the ECB encryption. The swap result I1 is processed with the AES core set in decrypt mode, using the formerly prepared decryption key. The decryption result goes through bit/byte/half-word swapping, then is stored in the AES_DOUTR register as 128-bit plaintext output data block P1. The ECB decryption continues in this way until the last complete ciphertext block is decrypted.

Figure 98

illustrates the cipher block chaining (CBC) encryption.

Figure 98. CBC encryption

Block 1

AES_DINR (plaintext P1)

Block 2

AES_DINR (plaintext P2)

Legend

DATATYPE[1:0]

AES_IVRx (init. vector)

AES_KEYRx (KEY)

DATATYPE[1:0]

Swap management

IVI

P1'

Block cipher encryption

Swap management

DATATYPE[1:0]

AES_KEYRx (KEY)

DATATYPE[1:0]

Swap management

P2'

Block cipher encryption

Swap management input output

XOR

AES_DOUTR (ciphertext C1) AES_DOUTR (ciphertext C2)

MSv19107V2

In CBC encrypt mode, the first plaintext input block, after bit/byte/half-word swapping (P1’), is XOR-ed with a 128-bit IVI bitfield (initialization vector and counter), producing the I1 input data for encrypt with the AES core, using a 128- or 256-bit key. The resulting 128-bit output block O1, after swapping operation, is used as ciphertext C1. The O1 data is then XOR-ed with the second-block plaintext data P2’ to produce the I2 input data for the AES core to produce the second block of ciphertext data. The chaining of data blocks continues in this way until the last plaintext block in the message is encrypted.

If the message size is not a multiple of 128 bits, the final partial data block is encrypted in the way explained in

Section 17.4.6: AES ciphertext stealing and data padding .

Figure 99

illustrates the cipher block chaining (CBC) decryption.

Figure 99. CBC decryption

Block 1

AES_DINR (ciphertext C1)

Block 2

AES_DINR (ciphertext C2)

DATATYPE[1:0]

AES_KEYRx (KEY)

Legend input output

XOR

AES_IVRx (IV)

DATATYPE[1:0]

Swap management

Decrypt

IVI

P1'

Swap management

AES_DOUTR (plaintext P1)

DATATYPE[1:0]

AES_KEYRx (KEY)

DATATYPE[1:0]

Swap management

Decrypt

P2'

Swap management

AES_DOUTR (plaintext P2)

MSv19104V2

470/1202 RM0471 Rev 5

RM0471 AES hardware accelerator (AES)

In CBC decrypt mode, like in ECB decrypt mode, the secret key must be prepared to perform an AES decryption.

After the key preparation process, the decryption goes as follows: the first 128-bit ciphertext block (after the swap operation) is used directly as the AES core input block I1 for decrypt operation, using the 128-bit or 256-bit key. Its output O1 is XOR-ed with the 128-bit IVI field

(that must be identical to that used during encryption) to produce the first plaintext block P1.

The second ciphertext block is processed in the same way as the first block, except that the

I1 data from the first block is used in place of the initialization vector.

The decryption continues in this way until the last complete ciphertext block is decrypted.

If the message size is not a multiple of 128 bits, the final partial data block is decrypted in the way explained in

Section 17.4.6: AES ciphertext stealing and data padding .

For more information on data swapping, refer to

Section 17.4.13: AES data registers and data swapping .

ECB/CBC encryption sequence

The sequence of events to perform an ECB/CBC encryption (more detail in

Section 17.4.4

Disable the AES peripheral by clearing the EN bit of the AES_CR register.

2. Select the Mode 1 by setting to 00 the MODE[1:0] bitfield of the AES_CR register and select ECB or CBC chaining mode by setting the CHMOD[2:0] bitfield of the AES_CR register to 000 or 001, respectively. Data type can also be defined, using

DATATYPE[1:0] bitfield.

3. Select 128- or 256-bit key length through the KEYSIZE bit of the AES_CR register.

4. Write the AES_KEYRx registers (128 or 256 bits) with encryption key. Fill the

AES_IVRx registers with the initialization vector data if CBC mode has been selected.

5. Enable the AES peripheral by setting the EN bit of the AES_CR register.

6. Write the AES_DINR register four times to input the plaintext (MSB first), as shown in

Figure 100 .

7. Wait until the CCF flag is set in the AES_SR register.

8. Read the AES_DOUTR register four times to get the ciphertext (MSB first) as shown in

Figure 100 . Then clear the CCF flag by setting the CCFC bit of the AES_CR register.

steps 7

to process all the blocks with the same encryption key.

Figure 100. ECB/CBC encryption (Mode 1)

PT3

MSB

PT2

PT1

PT0

LSB

Input phase

4 write operations into

AES_DINR[31:0]

PT = plaintext = 4 words (PT3, … , PT0)

CT = ciphertext = 4 words (CT3, … , CT0)

Wait until flag CCF = 1

Computation phase

CT3

MSB

CT2

CT1

CT0

LSB

Output phase

4 read operations of

AES_DOUTR[31:0]

MS18936V3

RM0471 Rev 5 471/1202

505

AES hardware accelerator (AES) RM0471

ECB/CBC decryption sequence

The sequence of events to perform an AES ECB/CBC decryption is as follows (More detail in

Section 17.4.4

Follow the steps described in Section 17.4.5: AES decryption round key preparation , in

order to prepare the decryption key in AES core.

2. Select the Mode 3 by setting to 10 the MODE[1:0] bitfield of the AES_CR register and select ECB or CBC chaining mode by setting the CHMOD[2:0] bitfield of the AES_CR register to 000 or 001, respectively. Data type can also be defined, using

DATATYPE[1:0] bitfield. KEYSIZE bitfield must be kept as-is.

3. Write the AES_IVRx registers with the initialization vector (required in CBC mode only).

4. Enable AES by setting the EN bit of the AES_CR register.

5. Write the AES_DINR register four times to input the cipher text (MSB first), as shown in

Figure 101 .

6. Wait until the CCF flag is set in the AES_SR register.

7. Read the AES_DOUTR register four times to get the plain text (MSB first), as shown in

Figure 101 . Then clear the CCF flag by setting the CCFC bit of the AES_CR register.

steps 6

to process all the blocks encrypted with the same key.

Figure 101. ECB/CBC decryption (Mode 3)

CT3

MSB

CT2

CT1

CT0

LSB

Input phase

4 write operations into

AES_DINR[31:0]

Wait until flag CCF = 1

Computation phase

PT3

MSB

PT2

PT1

PT0

LSB

Output phase

4 read operations from

AES_DOUTR[31:0]

PT = plaintext = 4 words (PT3, … , PT0)

CT = ciphertext = 4 words (CT3, … , CT0)

MS18938V3

Suspend/resume operations in ECB/CBC modes

To suspend the processing of a message , proceed as follows:

If DMA is used, stop the AES DMA transfers to the IN FIFO by clearing the DMAINEN bit of the AES_CR register.

2. If DMA is not used, read four times the AES_DOUTR register to save the last processed block. If DMA is used, wait until the CCF flag is set in the AES_SR register then stop the DMA transfers from the OUT FIFO by clearing the DMAOUTEN bit of the

AES_CR register.

3. If DMA is not used, poll the CCF flag of the AES_SR register until it becomes 1

(computation completed).

4. Clear the CCF flag by setting the CCFC bit of the AES_CR register.

are altered during the data processing).

472/1202 RM0471 Rev 5

RM0471

Note:

AES hardware accelerator (AES)

6. Disable the AES peripheral by clearing the bit EN of the AES_CR register.

7. Save the AES_CR register and clear the key registers if they are not needed, to process the higher priority message.

8. If DMA is used, save the DMA controller status (pointers for IN and OUT data transfers, number of remaining bytes, and so on).

In point 7, the derived key information stored in AES_KEYRx registers can optionally be saved in memory if the interrupted process is a decryption. Otherwise those registers do not need to be saved as the original key value is known by the application

To resume the processing of a message , proceed as follows:

If DMA is used, configure the DMA controller so as to complete the rest of the FIFO IN and FIFO OUT transfers.

2. Disable the AES peripheral by clearing the EN bit of the AES_CR register.

3. Restore AES_CR register (with correct KEYSIZE) then restore AES_KEYRx registers.

In case of decryption, derived key information can be written in AES_KEYRx register instead of the original key value.

4. Prepare the decryption key as described in Section 17.4.5: AES decryption round key preparation (only required for ECB or CBC decryption). This step is not necessary if

derived key information is loaded in AES_KEYRx registers.

5. Restore AES_IVRx registers using the saved configuration (only required in CBC mode).

6. Enable the AES peripheral by setting the EN bit of the AES_CR register.

7. If DMA is used, enable AES DMA transfers by setting the DMAINEN and DMAOUTEN bits of the AES_CR register.

Alternative single ECB/CBC decryption using Mode 4

The sequence of events to perform a single round of ECB/CBC decryption using Mode 4 is:

Disable the AES peripheral by clearing the EN bit of the AES_CR register.

2. Select the Mode 4 by setting to 11 the MODE[1:0] bitfield of the AES_CR register and select ECB or CBC chaining mode by setting the CHMOD[2:0] bitfield of the AES_CR register to 0x0 or 0x1, respectively.

3. Select key length of 128 or 256 bits via KEYSIZE bitfield of the AES_CR register.

4. Write the AES_KEYRx registers with the encryption key. Write the AES_IVRx registers if the CBC mode is selected.

5. Enable the AES peripheral by setting the EN bit of the AES_CR register.

6. Write the AES_DINR register four times to input the cipher text (MSB first).

7. Wait until the CCF flag is set in the AES_SR register.

8. Read the AES_DOUTR register four times to get the plain text (MSB first). Then clear the CCF flag by setting the CCFC bit of the AES_CR register.

When mode 4 is selected mode 3 cannot be used.

In mode 4, the AES_KEYRx registers contain the encryption key during all phases of the processing. No derivation key is stored in these registers. It is stored internally in AES.

RM0471 Rev 5 473/1202

505

AES hardware accelerator (AES) RM0471

17.4.9 AES counter (CTR) mode

Overview

The counter mode (CTR) uses AES as a key-stream generator. The generated keys are then XOR-ed with the plaintext to obtain the ciphertext.

CTR chaining is defined in NIST Special Publication 800-38A, Recommendation for Block

Cipher Modes of Operation.

A typical message construction in CTR mode is given in

Figure 102 .

Figure 102. Message construction in CTR mode

16-byte boundaries

ICB Ciphertext (C) 0

Zero padding

4-byte boundaries

Initialization vector (IV) Counter

Plaintext (P)

MSv42156V1

The structure of this message is:

 A 16-byte initial counter block (ICB), composed of two distinct fields:

– Initialization vector (IV): a 96-bit value that must be unique for each encryption cycle with a given key.

– Counter : a 32-bit big-endian integer that is incremented each time a block processing is completed. The initial value of the counter must be set to 1.

 The plaintext P is encrypted as ciphertext C, with a known length. This length can be non-multiple of 16 bytes, in which case a plaintext padding is required.

CTR encryption and decryption

Figure 103 and Figure 104 describe the CTR encryption and decryption process,

respectively, as implemented in the AES peripheral. The CTR mode is selected by writing

010 to the CHMOD[2:0] bitfield of AES_CR register.

474/1202 RM0471 Rev 5

RM0471 AES hardware accelerator (AES)

AES_KEYRx (KEY)

AES_DINR (plaintext P1)

Figure 103. CTR encryption

Block 1

AES_IVRx

Nonce + 32-bit counter

Counter increment (+1)

AES_KEYRx (KEY)

Encrypt

AES_DINR (plaintext P2)

Block 2

AES_IVRx

Nonce + 32-bit counter (+1)

Encrypt

Legend input output

XOR

Swap management

DATATYPE[1:0]

P1'

C1'

Swap management

AES_DOUTR (ciphertext C1)

Swap management

DATATYPE[1:0]

P2'

C2'

Swap management

AES_DOUTR (ciphertext C2)

MSv19102V3

AES_KEYRx (KEY)

AES_DINR (ciphertext C1)

Figure 104. CTR decryption

Block 1

AES_IVRx

Nonce + 32-bit counter

Counter increment (+1)

AES_KEYRx (KEY)

Encrypt

AES_DINR (ciphertext C2)

Block 2

AES_IVRx

Nonce + 32-bit counter (+1)

Encrypt

Legend

Swap management

DATATYPE[1:0]

C1'

P1'

Swap management

DATATYPE[1:0]

C2'

P2'

Swap management input output

XOR

AES_DOUTR (plaintext P1) AES_DOUTR (plaintext P2)

MSv18942V2

In CTR mode, the cryptographic core output (also called keystream) Ox is XOR-ed with relevant input block (Px' for encryption, Cx' for decryption), to produce the correct output block (Cx' for encryption, Px' for decryption). Initialization vectors in AES must be initialized

as shown in Table 82

AES_IVR3[31:0]

Table 82. CTR mode initialization vector definition

AES_IVR2[31:0] AES_IVR1[31:0] AES_IVR0[31:0]

IVI[127:96] IVI[95:64] IVI[63:32]

IVI[31:0}

32-bit counter = 0x0001

Unlike in CBC mode that uses the AES_IVRx registers only once when processing the first data block, in CTR mode AES_IVRx registers are used for processing each data block, and the AES peripheral increments the counter bits of the initialization vector (leaving the nonce bits unchanged).

RM0471 Rev 5 475/1202

505

AES hardware accelerator (AES)

Note:

RM0471

CTR decryption does not differ from CTR encryption, since the core always encrypts the current counter block to produce the key stream that is then XOR-ed with the plaintext (CTR encryption) or ciphertext (CTR decryption) input. In CTR mode, the MODE[1:0] bitfield setting 01 (key derivation) is forbidden and all the other settings default to encryption mode.

The sequence of events to perform an encryption or a decryption in CTR chaining mode:

Disable the AES peripheral by clearing the EN bit of the AES_CR register.

2. Select CTR chaining mode by setting to 010 the CHMOD[2:0] bitfield of the AES_CR register. Set MODE[1:0] bitfield to any value other than 01.

3. Initialize the AES_KEYRx registers, and load the AES_IVRx registers as described in

Table 82 .

4. Set the EN bit of the AES_CR register, to start encrypting the current counter (EN is automatically reset when the calculation finishes).

5. If it is the last block, pad the data with zeros to have a complete block, if needed.

6. Append data in AES, and read the result. The three possible scenarios are described in

Section 17.4.4: AES procedure to perform a cipher operation .

7. Repeat the previous step till the second-last block is processed. For the last block, apply the two previous steps and discard the bits that are not part of the payload (if the size of the significant data in the last input block is less than 16 bytes).

Suspend/resume operations in CTR mode

Like for the CBC mode, it is possible to interrupt a message to send a higher priority message, and resume the message that was interrupted. Detailed CBC suspend/resume sequence is described in

Section 17.4.8: AES basic chaining modes (ECB, CBC) .

Like for CBC mode, the AES_IVRx registers must be reloaded during the resume operation.

Overview

The AES Galois/counter mode (GCM) allows encrypting and authenticating a plaintext message into the corresponding ciphertext and tag (also known as message authentication code). To ensure confidentiality, GCM algorithm is based on AES counter mode. It uses a multiplier over a fixed finite field to generate the tag.

GCM chaining is defined in NIST Special Publication 800-38D, Recommendation for Block

Cipher Modes of Operation - Galois/Counter Mode (GCM) and GMAC. A typical message

construction in GCM mode is given in Figure 105

476/1202 RM0471 Rev 5

RM0471 AES hardware accelerator (AES)

Figure 105. Message construction in GCM

[Len(A)]

[Len(C)]

16-byte

boundaries

Len(A)

ICB

Additional authenticated data

(AAD)

Len(P) = Len(C)

Plaintext (P) 0

Last block

4-byte boundaries

Initialization vector (IV) Counter

Authenticated & encrypted ciphertext (C) 0

Authentication tag (T)

Zero padding / zeroed bits

MSv42157V1

The message has the following structure:

 16-byte initial counter block (ICB) , composed of two distinct fields:

– Initialization vector (IV): a 96-bit value that must be unique for each encryption cycle with a given key. Note that the GCM standard supports IVs with less than 96 bits, but in this case strict rules apply.

– Counter: a 32-bit big-endian integer that is incremented each time a block processing is completed. According to NIST specification, the counter value is 0x2 when processing the first block of payload.

 Authenticated header AAD (also knows as additional authentication data) has a known length Len(A) that may be a non-multiple of 16 bytes, and must not exceed

– 1 bits. This part of the message is only authenticated, not encrypted.

 Plaintext message P is both authenticated and encrypted as ciphertext C, with a known length Len(P) that may be non-multiple of 16 bytes, and cannot exceed 2 32

128-bit blocks.

- 2

 Last block contains the AAD header length (bits [32:63]) and the payload length (bits

[96:127]) information, as shown in Table 83

The GCM standard specifies that ciphertext C has the same bit length as the plaintext P.

When a part of the message (AAD or P) has a length that is a non-multiple of 16-bytes a special padding scheme is required.

Table 83. GCM last block definition

Endianness Bit[0] ---------- Bit[31] Bit[32]---------- Bit[63] Bit[64] -------- Bit[95] Bit[96] --------- Bit[127]

Input data 0x0 AAD length[31:0] 0x0 Payload length[31:0]

RM0471 Rev 5 477/1202

505

AES hardware accelerator (AES) RM0471

GCM processing

Figure 106 describes the GCM implementation in the AES peripheral. The GCM is selected

by writing 011 to the CHMOD[2:0] bitfield of the AES_CR register.

(1) Init

AES_KEYRx (KEY)

[0]

128

Encrypt

Figure 106. GCM authenticated encryption

(3) Payload

Block 1

AES_IVRx

ICB + (32-bit counter = 0x02)

Counter increment (+1)

CB1

AES_KEYRx (KEY)

CBn

AES_KEYRx (KEY)

Encrypt

AES_DINR (plaintext P1) AES_DINR (plaintext Pn)

Block n

AES_IVRx

CBn

Encrypt

Swap management

DATATYPE

[1:0]

Swap management

DATATYPE

[1:0]

(2) Header

AES_DINR (AAD 0) AES_DINR (AAD i)

DATATYPE

[1:0]

Swap management

DATATYPE[1:0]

Swap management

Swap management DATATYPE

[1:0]

Swap management

AES_DOUTR

(ciphertext C1)

AES_DOUTR

(ciphertext Cn)

H GF2mul H GF2mul

(4) Final

AES_DINR

Len(A)

|| Len(C)

Legend input output

XOR

AES_IVRx

(IV + 32-bit counter (= 0x0))

Encrypt

H GF2mul

AES_KEYRx (key)

AES_DOUTR

(Authentication TAG T)

MSv42149V1

The mechanism for the confidentiality of the plaintext in GCM mode is similar to that in the

Counter mode, with a particular increment function (denoted 32-bit increment) that generates the sequence of input counter blocks.

AES_IVRx registers keeping the counter block of data are used for processing each data block. The AES peripheral automatically increments the Counter[31:0] bitfield. The first counter block (CB1) is derived from the initial counter block ICB by the application software

(see Table 84

Table 84. Initialization of SAES_IVRx registers in GCM mode

AES_IVR3[31:0] AES_IVR2[31:0] AES_IVR1[31:0] AES_IVR0[31:0]

ICB[127:96] ICB[95:64] ICB[63:32]

ICB[31:0]

32-bit counter = 0x0002

Note: In this mode, the settings 01 and 11 of the MODE[1:0] bitfield are forbidden.

478/1202 RM0471 Rev 5

RM0471

Note:

AES hardware accelerator (AES)

The authentication mechanism in GCM mode is based on a hash function called GF2mul that performs multiplication by a fixed parameter, called hash subkey (H), within a binary

Galois field.

A GCM message is processed through the following phases, further described in next subsections:

 Init phase : AES prepares the GCM hash subkey (H).

 Header phase : AES processes the additional authenticated data (AAD), with hash computation only.

 Payload phase : AES processes the plaintext (P) with hash computation, counter block encryption and data XOR-ing. It operates in a similar way for ciphertext (C).

 Final phase : AES generates the authenticated tag (T) using the last block of the message.

GCM init phase

During this first step, the GCM hash subkey (H) is calculated and saved internally, to be used for processing all the blocks. The recommended sequence is:

Disable the AES peripheral by clearing the EN bit of the AES_CR register.

2. Select GCM chaining mode, by setting to 011 the CHMOD[2:0] bitfield of the AES_CR register, and optionally, set the DATATYPE[1:0] bitfield.

3. Indicate the Init phase, by setting to 00 the GCMPH[1:0] bitfield of the AES_CR register.

4. Set the MODE[1:0] bitfield of the AES_CR register to 00 or 10. Although the bitfield is only used in payload phase, it is recommended to set it in the Init phase and keep it unchanged in all subsequent phases.

5. Initialize the AES_KEYRx registers with a key, and initialize AES_IVRx registers with

the information as defined in Table 84

6. Start the calculation of the hash key, by setting to 1 the EN bit of the AES_CR register

(EN is automatically reset when the calculation finishes).

7. Wait until the end of computation, indicated by the CCF flag of the AES_SR transiting to 1. Alternatively, use the corresponding interrupt.

8. Clear the CCF flag of the AES_SR register, by setting the CCFC bit of the AES_CR register.

GCM header phase

This phase coming after the GCM Init phase must be completed before the payload phase.

The sequence to execute, identical for encryption and decryption, is:

Indicate the header phase, by setting to 01 the GCMPH[1:0] bitfield of the AES_CR register. Do not modify the MODE[1:0] bitfield as set in the Init phase.

2. Enable the AES peripheral by setting the EN bit of the AES_CR register.

3. If it is the last block and the AAD size in the block is inferior to 128 bits, pad the remainder of the block with zeros. Then append the data block into AES in one of ways described in

Section 17.4.4: AES procedure to perform a cipher operation . No data is

read during this phase.

4. Repeat the step 3 until the last additional authenticated data block is processed.

The header phase can be skipped if there is no AAD, that is, Len(A) = 0.

RM0471 Rev 5 479/1202

505

AES hardware accelerator (AES)

Note:

RM0471

GCM payload phase

This phase, identical for encryption and decryption, is executed after the GCM header phase. During this phase, the encrypted/decrypted payload is stored in the AES_DOUTR register. The sequence to execute is:

Indicate the payload phase, by setting to 10 the GCMPH[1:0] bitfield of the AES_CR register. Do not modify the MODE[1:0] bitfield as set in the Init phase.

2. If the header phase was skipped, enable the AES peripheral by setting the EN bit of the

AES_CR register.

3. If it is the last block and the plaintext (encryption) or ciphertext (decryption) size in the block is inferior to 128 bits, pad the remainder of the block with zeros.

4. Append the data block into AES in one of ways described in

Section 17.4.4: AES procedure to perform a cipher operation on page 464 , and read the result.

5. Repeat the previous step till the second-last plaintext block is encrypted or till the last block of ciphertext is decrypted. For the last block of plaintext (encryption only), execute the two previous steps. For the last block, discard the bits that are not part of the payload when the last block size is less than 16 bytes.

The payload phase can be skipped if there is no payload data, that is, Len(C) = 0 (see

GMAC mode).

GCM final phase

In this last phase, the AES peripheral generates the GCM authentication tag and stores it in the AES_DOUTR register. The sequence to execute is:

Indicate the final phase, by setting to 11 the GCMPH[1:0] bitfield of the AES_CR register.

2. Compose the data of the block, by concatenating the AAD bit length and the payload

bit length, as shown in Table 83

. Write the block into the AES_DINR register.

3. Wait until the end of computation, indicated by the CCF flag of the AES_SR transiting to 1.

4. Get the GCM authentication tag, by reading the AES_DOUTR register four times.

5. Clear the CCF flag of the AES_SR register, by setting the CCFC bit of the AES_CR register.

6. Disable the AES peripheral, by clearing the bit EN of the AES_CR register. If it is an authenticated decryption, compare the generated tag with the expected tag passed with the message.

In the final phase, data is written to AES_DINR normally (no swapping), while swapping is applied to tag data read from AES_DOUTR.

When transiting from the header or the payload phase to the final phase, the AES peripheral must not be disabled, otherwise the result is wrong.

480/1202 RM0471 Rev 5

RM0471 AES hardware accelerator (AES)

Suspend/resume operations in GCM mode

To suspend the processing of a message , proceed as follows:

If DMA is used, stop the AES DMA transfers to the IN FIFO by clearing the DMAINEN bit of the AES_CR register. If DMA is not used, make sure that the current computation is completed, which is indicated by the CCF flag of the AES_SR register set to 1.

2. In the payload phase, if DMA is not used, read four times the AES_DOUTR register to save the last-processed block. If DMA is used, wait until the CCF flag is set in the

AES_SR register then stop the DMA transfers from the OUT FIFO by clearing the

DMAOUTEN bit of the AES_CR register.

3. Clear the CCF flag of the AES_SR register, by setting the CCFC bit of the AES_CR register.

4. Save the AES_SUSPxR registers in the memory, where x is from 0 to 7.

5. In the payload phase, save the AES_IVRx registers as, during the data processing, they changed from their initial values. In the header phase, this step is not required.

6. Disable the AES peripheral, by clearing the EN bit of the AES_CR register.

7. Save the current AES configuration in the memory, excluding the initialization vector registers AES_IVRx. Key registers do not need to be saved as the original key value is known by the application.

8. If DMA is used, save the DMA controller status (pointers for IN data transfers, number of remaining bytes, and so on). In the payload phase, pointers for OUT data transfers must also be saved.

To resume the processing of a message , proceed as follows:

If DMA is used, configure the DMA controller in order to complete the rest of the FIFO

IN transfers. In the payload phase, the rest of the FIFO OUT transfers must also be configured in the DMA controller.

2. Disable the AES peripheral by clearing the EN bit of the AES_CR register.

3. Write the suspend register values, previously saved in the memory, back into their corresponding AES_SUSPxR registers, where x is from 0 to 7.

4. In the payload phase, write the initialization vector register values, previously saved in the memory, back into their corresponding AES_IVRx registers. In the header phase, write initial setting values back into the AES_IVRx registers.

6. Enable the AES peripheral by setting the EN bit of the AES_CR register.

If DMA is used, enable AES DMA requests by setting the DMAINEN bit (and DMAOUTEN bit if in payload phase) of the AES_CR register.

Overview

The Galois message authentication code (GMAC) allows the authentication of a plaintext, generating the corresponding tag information (also known as message authentication code). It is based on GCM algorithm, as defined in NIST Special Publication 800-38D,

Recommendation for Block Cipher Modes of Operation - Galois/Counter Mode (GCM) and

GMAC.

RM0471 Rev 5 481/1202

505

AES hardware accelerator (AES) RM0471

A typical message construction for GMAC is given in

Figure 107

Figure 107. Message construction in GMAC mode

[Len(A)]

[0]

Len(A)

16-byte

boundaries

ICB Authenticated data 0

Last block

4-byte boundaries

Initialization vector (IV) Counter

Authentication tag (T)

482/1202

Zero padding

AES GMAC processing

Figure 108 describes the GMAC mode implementation in the AES peripheral. This mode is

selected by writing 011 to the CHMOD[2:0] bitfield of the AES_CR register.

Figure 108. GMAC authentication mode

MSv42158V2

(1) Init (4) Final

[0]

128 AES_IVRx

IV + 32-bit counter (= 0x0)

AES_KEYRx (KEY)

Encrypt

AES_KEYRx (KEY)

Encrypt

(2) Header

AES_DINR

(message block 1)

AES_DINR

(message block n)

AES_DINR len(A)

|| [0]

Swap management DATATYPE

[1:0]

Swap management

H GF2mul

Legend input output

XOR

GF2mul H GF2mul

AES_DOUTR

(authentication tag T)

MSv42150V2

The GMAC algorithm corresponds to the GCM algorithm applied on a message only containing a header. As a consequence, all steps and settings are the same as with the

GCM, except that the payload phase is omitted.

Suspend/resume operations in GMAC

In GMAC mode, the sequence described for the GCM applies except that only the header phase can be interrupted.

RM0471 Rev 5

RM0471 AES hardware accelerator (AES)

Note:

16-byte

boundaries

Overview

The AES counter with cipher block chaining-message authentication code (CCM) algorithm allows encryption and authentication of plaintext, generating the corresponding ciphertext and tag (also known as message authentication code). To ensure confidentiality, the CCM algorithm is based on AES in counter mode. It uses cipher block chaining technique to generate the message authentication code. This is commonly called CBC-

MAC.

NIST does not approve this CBC-MAC as an authentication mode outside the context of the

CCM specification.

CCM chaining is specified in NIST Special Publication 800-38C, Recommendation for Block

Cipher Modes of Operation - The CCM Mode for Authentication and Confidentiality . A typical message construction for CCM is given in

Figure 109

Figure 109. Message construction in CCM mode

Len(A) Len(P)

Len(C)

Len(T)

[a]

Associated data (A) 0 Plaintext (P) 0

Enc

(T)

4-byte boundaries

Authenticated & encrypted ciphertext (C) flags Nonce (N)

Len(N)

MAC (T) Decrypt and compare

Zero padding

MSv42159V2

The structure of the message is:

 16-byte first authentication block (B0) , composed of three distinct fields:

– Q: a bit string representation of the octet length of P (Len(P))

– Nonce (N): a single-use value (that is, a new nonce must be assigned to each new communication) of Len(N) size. The sum Len(N) + Len(P) must be equal to

15 bytes.

– Flags: most significant octet containing four flags for control information, as specified by the standard. It contains two 3-bit strings to encode the values t (MAC length expressed in bytes) and Q (plaintext length such that Len(P) < 2

bytes).

The counter blocks range associated to Q is equal to 2

8Q-4

, that is, if the maximum value of Q is 8, the counter blocks used in cipher must be on 60 bits.

 16-byte blocks (B) associated to the Associated Data (A).

This part of the message is only authenticated, not encrypted. This section has a known length Len(A) that can be a non-multiple of 16 bytes (see

Figure 109 ). The

RM0471 Rev 5 483/1202

505

AES hardware accelerator (AES)

Note:

RM0471 standard also states that, on MSB bits of the first message block (B1), the associated data length expressed in bytes (a) must be encoded as follows:

–

If 0 < a < 2

If 2 16 - 2 8

- 2

< a < 2

, then it is encoded as [a]

, that is, on two bytes.

, then it is encoded as 0xff || 0xfe || [a]

, that is, on six bytes.

– If 2

< a < 2

, then it is encoded as 0xff || 0xff || [a]

, that is, on ten bytes.

 16-byte blocks (B) associated to the plaintext message P, which is both authenticated and encrypted as ciphertext C, with a known length Len(P). This length can be a non-

multiple of 16 bytes (see Figure 109

 Encrypted MAC (T) of length Len(T) appended to the ciphertext C of overall length

Len(C) .

When a part of the message (A or P) has a length that is a non-multiple of 16-bytes, a special padding scheme is required.

CCM chaining mode can also be used with associated data only (that is, no payload).

As an example, the C.1 section in NIST Special Publication 800-38C gives the following values (hexadecimal numbers):

N: 10111213 141516 (Len(N)= 56 bits or 7 bytes)

A: 00010203 04050607 (Len(A)= 64 bits or 8 bytes)

P: 20212223 (Len(P)= 32 bits or 4 bytes)

T: 6084341B (Len(T)= 32 bits or t = 4)

B0: 4F101112 13141516 00000000 00000004

B1: 00080001 02030405 06070000 00000000

B2: 20212223 00000000 00000000 00000000

CTR0: 0710111213 141516 00000000 00000000

CTR1: 0710111213 141516 00000000 00000001

Generation of formatted input data blocks Bx (especially B0 and B1) must be managed by the application.

484/1202 RM0471 Rev 5

RM0471 AES hardware accelerator (AES)

CCM processing

Figure 110 describes the CCM implementation within the AES peripheral (encryption

example). This mode is selected by writing 100 into the CHMOD[2:0] bitfield of the AES_CR register.

(1) Init mask

AES_IVRx (CTR0)

Figure 110. CCM mode authenticated encryption

Block 1 (3) Payload

AES_IVRx (CTR1)

Counter increment (+1)

AES_IVRx (First block B0)

AES_KEYRx (KEY) AES_KEYRx (KEY)

Encrypt

AES_DINR (plaintext P1) AES_DINR (plaintext last block Pm )

AES_KEYRx (KEY)

Swap management

DATATYPE

[1:0]

Swap management

Block m

AES_IVRx (CTRm)

DATATYPE

[1:0]

Encrypt

(2) Header

AES_DINR (associated data block B1)

AES_DINR (associated data last block Bu)

DATATYPE

[1:0]

Swap management

DATATYPE

[1:0]

Swap management

AES_DOUTR (ciphertext C1)

Swap management

DATATYPE[1:0]

Swap management

DATATYPE[1:0]

B u+1

AES_DOUTR

(ciphertext last block Cm)

B r

AES_KEYRx (KEY)

Encrypt Encrypt Encrypt Encrypt

AES_DINR (CTR0)

AES_KEYRx (KEY) AES_KEYRx (KEY) AES_KEYRx (KEY)

MAC (T)

Note:

Legend input output

XOR

Encrypt

AES_KEYRx (KEY)

AES_DOUTR

(EncTAG)

(4) Final

MSv42152V2

The data input to the generation-encryption process are a valid nonce, a valid payload string, and a valid associated data string, all properly formatted. The CBC chaining mechanism is applied to the formatted plaintext data to generate a MAC, with a known length. Counter mode encryption that requires a sufficiently long sequence of counter blocks as input, is applied to the payload string and separately to the MAC. The resulting ciphertext

C is the output of the generation-encryption process on plaintext P.

AES_IVRx registers are used for processing each data block, AES automatically

incrementing the CTR counter with a bit length defined by the first block B0. Table 85 shows

how the application must load the B0 data.

The AES peripheral in CCM mode supports counters up to 64 bits, as specified by NIST.

Table 85. Initialization of AES_IVRx registers in CCM mode

AES_IVR3[31:0] AES_IVR2[31:0] AES_IVR1[31:0] AES_IVR0[31:0]

B0[127:96] B0[95:64] B0[63:32] B0[31:0]

RM0471 Rev 5 485/1202

505

AES hardware accelerator (AES)

Note:

RM0471

In this mode, the settings 01 and 11 of the MODE[1:0] bitfield are forbidden.

A CCM message is processed through the following phases, further described in next subsections:

 Init phase : AES processes the first block and prepares the first counter block.

 Header phase : AES processes associated data (A), with tag computation only.

 Payload phase : IP processes plaintext (P), with tag computation, counter block encryption, and data XOR-ing. It works in a similar way for ciphertext (C).

 Final phase : AES generates the message authentication code (MAC).

CCM Init phase

In this phase, the first block B0 of the CCM message is written into the AES_IVRx register.

The AES_DOUTR register does not contain any output data. The recommended sequence is:

Disable the AES peripheral by clearing the EN bit of the AES_CR register.

2. Select CCM chaining mode, by setting to 100 the CHMOD[2:0] bitfield of the AES_CR register, and optionally, set the DATATYPE[1:0] bitfield.

3. Indicate the Init phase, by setting to 00 the GCMPH[1:0] bitfield of the AES_CR register.

5. Initialize the AES_KEYRx registers with a key, and initialize AES_IVRx registers with

B0 data as described in

Table 85 .

6. Start the calculation of the counter, by setting to 1 the EN bit of the AES_CR register

(EN is automatically reset when the calculation finishes).

7. Wait until the end of computation, indicated by the CCF flag of the AES_SR transiting to 1. Alternatively, use the corresponding interrupt.

8. Clear the CCF flag in the AES_SR register, by setting to 1 the CCFC bit of the AES_CR register.

CCM header phase

This phase coming after the GCM Init phase must be completed before the payload phase.

During this phase, the AES_DOUTR register does not contain any output data.

The sequence to execute, identical for encryption and decryption, is:

Indicate the header phase, by setting to 01 the GCMPH[1:0] bitfield of the AES_CR register. Do not modify the MODE[1:0] bitfield as set in the Init phase.

2. Enable the AES peripheral by setting the EN bit of the AES_CR register.

3. If it is the last block and the AAD size in the block is inferior to 128 bits, pad the remainder of the block with zeros. Then append the data block into AES in one of ways described in

Section 17.4.4: AES procedure to perform a cipher operation . No data is

read during this phase.

4. Repeat the step 3 until the last additional authenticated data block is processed.

The header phase can be skipped if there is no associated data, that is, Len(A) = 0.

The first block of the associated data (B1) must be formatted by software, with the associated data length.

486/1202 RM0471 Rev 5

RM0471

Note:

AES hardware accelerator (AES)

CCM payload phase (encryption or decryption)

This phase, identical for encryption and decryption, is executed after the CCM header phase. During this phase, the encrypted/decrypted payload is stored in the AES_DOUTR register. The sequence to execute is:

Indicate the payload phase, by setting to 10 the GCMPH[1:0] bitfield of the AES_CR register. Do not modify the MODE[1:0] bitfield as set in the Init phase.

2. If the header phase was skipped, enable the AES peripheral by setting the EN bit of the

AES_CR register.

3. If it is the last data block to encrypt and the plaintext size in the block is inferior to 128 bits, pad the remainder of the block with zeros.

4. Append the data block into AES in one of ways described in

Section 17.4.4: AES procedure to perform a cipher operation on page 464 , and read the result.

5. Repeat the previous step till the second-last plaintext block is encrypted or till the last block of ciphertext is decrypted. For the last block of plaintext (encryption only), apply the two previous steps. For the last block, discard the data that is not part of the payload when the last block size is less than 16 bytes.

The payload phase can be skipped if there is no payload data, that is, Len(P) = 0 or

Len(C) = Len(T).

Remove LSB

Len(T)

(C) encrypted tag information when decrypting ciphertext C.

CCM final phase

In this last phase, the AES peripheral generates the GCM authentication tag and stores it in the AES_DOUTR register. The sequence to execute is:

Indicate the final phase, by setting to 11 the GCMPH[1:0] bitfield of the AES_CR register.

2. Wait until the end-of-computation flag CCF of the AES_SR register is set.

3. Read four times the AES_DOUTR register: the output corresponds to the CCM authentication tag.

4. Clear the CCF flag of the AES_SR register by setting the CCFC bit of the AES_CR register.

5. Disable the AES peripheral, by clearing the EN bit of the AES_CR register.

6. For authenticated decryption, compare the generated encrypted tag with the encrypted tag padded in the ciphertext.

In this final phase, swapping is applied to tag data read from AES_DOUTR register.

When transiting from the header phase to the final phase, the AES peripheral must not be disabled, otherwise the result is wrong.

Application must mask the authentication tag output with tag length to obtain a valid tag.

Suspend/resume operations in CCM mode

To suspend the processing of a message in header or payload phase, proceed as follows:

2. In the payload phase, if DMA is not used, read four times the AES_DOUTR register to save the last-processed block. If DMA is used, wait until the CCF flag is set in the

RM0471 Rev 5 487/1202

505

AES hardware accelerator (AES) RM0471

AES_SR register then stop the DMA transfers from the OUT FIFO by clearing the

DMAOUTEN bit of the AES_CR register.

3. Clear the CCF flag of the AES_SR register, by setting to 1 the CCFC bit of the AES_CR register.

4. Save the AES_SUSPxR registers (where x is from 0 to 7) in the memory.

5. Save the AES_IVRx registers as, during the data processing, they changed from their initial values.

6. Disable the AES peripheral, by clearing the EN bit of the AES_CR register.

8. If DMA is used, save the DMA controller status (pointers for IN data transfers, number of remaining bytes, and so on). In the payload phase, pointers for OUT data transfers must also be saved.

To resume the processing of a message , proceed as follows:

If DMA is used, configure the DMA controller in order to complete the rest of the FIFO

IN transfers. In the payload phase, the rest of the FIFO OUT transfers must also be configured in the DMA controller.

2. Disable the AES peripheral by clearing the EN bit of the AES_CR register.

3. Write the suspend register values, previously saved in the memory, back into their corresponding AES_SUSPxR registers (where x is from 0 to 7).

4. Write the initialization vector register values, previously saved in the memory, back into their corresponding AES_IVRx registers.

6. Enable the AES peripheral by setting the EN bit of the AES_CR register.

7. If DMA is used, enable AES DMA requests by setting to 1 the DMAINEN bit (and

DMAOUTEN bit if in payload phase) of the AES_CR register.

488/1202

Data input and output

A 128-bit data block is entered into the AES peripheral with four successive 32-bit word writes into the AES_DINR register (bitfield DIN[31:0]), the most significant word (bits

[127:96]) first, the least significant word (bits [31:0]) last.

A 128-bit data block is retrieved from the AES peripheral with four successive 32-bit word reads from the AES_DOUTR register (bitfield DOUT[31:0]), the most significant word (bits

[127:96]) first, the least significant word (bits [31:0]) last.

The 32-bit data word for AES_DINR register or from AES_DOUTR register is organized in big endian order, that is:

 the most significant byte of a word to write into AES_DINR must be put on the lowest address out of the four adjacent memory locations keeping the word to write, or

 the most significant byte of a word read from AES_DOUTR goes to the lowest address out of the four adjacent memory locations receiving the word

For using DMA for input data block write into AES, the four words of the input block must be stored in the memory consecutively and in big-endian order, that is, the most significant word on the lowest address. See

Section 17.4.16: AES DMA interface

RM0471 Rev 5

RM0471 AES hardware accelerator (AES)

Data swapping

The AES peripheral can be configured to perform a bit-, a byte-, a half-word-, or no swapping on the input data word in the AES_DINR register, before loading it to the AES processing core, and on the data output from the AES processing core, before sending it to the AES_DOUTR register. The choice depends on the type of data. For example, a byte swapping is used for an ASCII text stream.

The data swap type is selected through the DATATYPE[1:0] bitfield of the AES_CR register.

The selection applies both to the input and the output of the AES core.

For different data swap types, Figure 111 shows the construction of AES processing core

input buffer data P127 to P0, from the input data entered through the AES_DINR register, or the construction of the output data available through the AES_DOUTR register, from the

AES processing core output buffer data P127 to P0.

Figure 111. 128-bit block construction with respect to data swap increasing memory address byte 3

D63 byte 2

D56 D55 byte 1

D48 D47 byte 0

D40 D39 D32

DATATYPE[1:0] = 00: no swapping

MSB

Word 3

D127 D96 D95

1 2

Word 2

D64 D63

Word 1

D32 D31

Word 0

D127

MSB

D96 D64 D63 D32 D31

DATATYPE[1:0] = 01: 16-bit (half-word) swapping

MSB

D127

Word 3

D112 D111 D96 D95

Word 2

D80 D79

1 2

D64 D63

Word 1

D48 D47 D32 D31

Word 0

D16 D15

D111

MSB

D96 D127 D112 D79 D64 D95 D80 D47 D32 D63 D48 D15 D0 D31

LSB

D16

LSB

DATATYPE[1:0] = 10: 8-bit (byte) swapping

MSB

Word 3

D127..120

D119..112

D111.104

D103..96

Word 2

D95..88

D87..80

D79..72

1 2

D71...64

D103..96

D111.104

D119..112 D127..120

D71...64

MSB

D79..72

D87..80

D95..88

D63...56

Word 1

D55...48

D47...40

D39...32

D47...40

D55...48

D63...56

LSB

Word 0

D31...24

D23...16

D15...8

D7...0

D15...8

D7...0

D23...16

D31...24

LSB

DATATYPE[1:0] = 11: bit swapping

MSB

Word 3

D127 D126 D125

Word 2

D98 D97 D96 D95 D94 D93

1 2

D96 D97 D98

MSB

Legend:

D125 D126 D127 D64 D65 D66

AES input/output data block in memory

AES core input/output buffer data

Zero padding (example)

Data swap

Word 1

D66 D65 D64 D63 D62 D61

D93 D94 D95 D32 D33 D34

D34 D33 D32

Word 0

D31 D30 D29

D61 D62 D63 D0 D1 D2

LSB

D2 D1 D0

D29 D30 D31

LSB

MSB most significant bit (127) of memory data block / AEC core buffer

LSB least significant bit (0) of memory data block / AEC core buffer

1 4

Order of write to AES_DINR / read from AES_DOUTR input/output data bit ‘x’

MSv42153V2

RM0471 Rev 5 489/1202

505

AES hardware accelerator (AES) RM0471

Note: The data in AES key registers (AES_KEYRx) and initialization registers (AES_IVRx) are not sensitive to the swap mode selection.

Data padding

Figure 111

also gives an example of memory data block padding with zeros such that the zeroed bits after the data swap form a contiguous zone at the MSB end of the AES core input buffer. The example shows the padding of an input data block containing:

 48 message bits, with DATATYPE[1:0] = 01

 56 message bits, with DATATYPE[1:0] = 10

 34 message bits, with DATATYPE[1:0] = 11

17.4.14 AES key registers

The AES_KEYRx registers store the encryption or decryption key bitfield KEY[127:0] or

KEY[255:0]. The data to write to or to read from each register is organized in the memory in little-endian order, that is, with most significant byte on the highest address.

The key is spread over eight registers as shown in Table 86

Table 86. Key endianness in AES_KEYRx registers (128- or 256-bit key length)

AES_KEYR7

[31:0]

AES_KEYR6

[31:0]

AES_KEYR5

[31:0]

AES_KEYR4

[31:0]

AES_KEYR3

[31:0]

AES_KEYR2

[31:0]

AES_KEYR1

[31:0]

AES_KEYR0

[31:0]

KEY[255:224]

KEY[223:192]

KEY[191:160]

KEY[159:128]

KEY[127:96]

KEY[95:64]

KEY[63:32]

KEY[31:0]

The key for encryption or decryption may be written into these registers when the AES peripheral is disabled, by clearing the EN bit of the AES_CR register.

The key registers are not affected by the data swapping controlled by DATATYPE[1:0] bitfield of the AES_CR register.

17.4.15 AES initialization vector registers

The four AES_IVRx registers keep the initialization vector input bitfield IVI[127:0]. The data to write to or to read from each register is organized in the memory in little-endian order, that is, with most significant byte on the highest address. The registers are also ordered from lowest address (AES_IVR0) to highest address (AES_IVR3).

The signification of data in the bitfield depends on the chaining mode selected. When used, the bitfield is updated upon each computation cycle of the AES core.

Write operations to the AES_IVRx registers when the AES peripheral is enabled have no effect to the register contents. For modifying the contents of the AES_IVRx registers, the EN bit of the AES_CR register must first be cleared.

Reading the AES_IVRx registers returns the latest counter value (useful for managing suspend mode).

The AES_IVRx registers are not affected by the data swapping feature controlled by the

DATATYPE[1:0] bitfield of the AES_CR register.

490/1202 RM0471 Rev 5

RM0471 AES hardware accelerator (AES)

Note:

The AES peripheral provides an interface to connect to the DMA (direct memory access) controller. The DMA operation is controlled through the AES_CR register.

Data input using DMA

Setting the DMAINEN bit of the AES_CR register enables DMA writing into AES. The AES peripheral then initiates a DMA request during the input phase each time it requires to write a 128-bit block (quadruple word) to the AES_DINR register, as shown in

Figure 112

According to the algorithm and the mode selected, special padding / ciphertext stealing might be required. For example, in case of AES GCM encryption or AES CCM decryption, a

DMA transfer must not include the last block. For details, refer to

Section 17.4.4: AES procedure to perform a cipher operation

Figure 112. DMA transfer of a 128-bit data block during input phase

Chronological order

Increasing address

Word3

DIN[127:96] D96 D95

Memory accessed through DMA

Word2

DIN[95:64] D64 D63

Word1

DIN[63:32] D32 D31

Word0

DIN[31:0] D127

MSB

DMA req N

DMA single write

DMA req N+1

(No swapping) 1

I127

MSB

1 4

I96 I95

Order of write to AES_DINR

DMA single write

DMA req N+2

DMA single write

AES_DINR

AES core input buffer

I64 I63

DMA req N+3

I32 I31

DMA single write

LSB

MSv42160V1

Note:

Data output using DMA

Setting the DMAOUTEN bit of the AES_CR register enables DMA reading from AES. The

AES peripheral then initiates a DMA request during the Output phase each time it requires

to read a 128-bit block (quadruple word) to the AES_DINR register, as shown in Figure 113 .

According to the message size, extra bytes might need to be discarded by application in the last block.

RM0471 Rev 5 491/1202

505

AES hardware accelerator (AES) RM0471

D127

MSB

Figure 113. DMA transfer of a 128-bit data block during output phase

Chronological order

Increasing address

Word3

DOUT[127:96] D96 D95

Memory accessed through DMA

Word2 Word1

DOUT[95:64] D64 D63 DOUT[63:32] D32 D31

Word0

DOUT[31:0]

DMA req N+3

DMA single read

DMA req N

DMA single read

(No swapping) 1

O127

MSB

1 4

DMA req N+1

O96 O95

DMA single read

DMA req N+2

DMA single read

AES_DOUTR

AES core output buffer

O64 O63

Order of read from AES_DOUTR

O32 O31

LSB

MSv42161V1

DMA operation in different operating modes

DMA operations are usable when Mode 1 (encryption) or Mode 3 (decryption) are selected via the MODE[1:0] bitfield of the register AES_CR. As in Mode 2 (key derivation) the

AES_KEYRx registers must be written by software, enabling the DMA transfer through the

DMAINEN and DMAOUTEN bits of the AES_CR register have no effect in that mode.

DMA single requests are generated by AES until it is disabled. So, after the data output phase at the end of processing of a 128-bit data block, AES switches automatically to a new data input phase for the next data block, if any.

When the data transferring between AES and memory is managed by DMA, the CCF flag is not relevant and can be ignored (left set) by software. It must only be cleared when

transiting back to data transferring managed by software. See Suspend/resume operations in ECB/CBC modes in

Section 17.4.8: AES basic chaining modes (ECB, CBC) as example.

17.4.17 AES error management

AES configuration can be changed at any moment by clearing the EN bit of the AES_CR register.

Note:

Read error flag (RDERR)

Unexpected read attempt of the AES_DOUTR register sets the RDERR flag of the AES_SR register, and returns zero.

RDERR is triggered during the computation phase or during the input phase.

AES is not disabled upon a RDERR error detection and continues processing.

An interrupt is generated if the ERRIE bit of the AES_CR register is set. For more details, refer to

Section 17.5: AES interrupts

The RDERR flag is cleared by setting the ERRIE bit of the AES_CR register.

Write error flag (WDERR)

Unexpected write attempt of the AES_DINR register sets the WRERR flag of the AES_SR register, and has no effect on the AES_DINR register. The WRERR is triggered during the computation phase or during the output phase.

492/1202 RM0471 Rev 5

RM0471

Note:

AES hardware accelerator (AES)

AES is not disabled after a WRERR error detection and continues processing.

An interrupt is generated if the ERRIE bit of the AES_CR register is set. For more details, refer to

Section 17.5: AES interrupts

The WRERR flag is cleared by setting the ERRC bit of the AES_CR register.

Individual maskable interrupt sources generated by the AES peripheral signal the following events:

 computation completed

 read error

 write error

The individual sources are combined into the common interrupt signal aes_it that connects to NVIC (nested vectored interrupt controller). Each can individually be enabled/disabled, by setting/clearing the corresponding enable bit of the AES_CR register, and cleared by setting the corresponding bit of the AES_CR register.

The status of each can be read from the AES_SR register.

Table 87 gives a summary of the interrupt sources, their event flags and enable bits.

Table 87. AES interrupt requests

Interrupt acronym

AES interrupt event

AES computation completed flag read error flag write error flag

1. Bit of the AES_CR register.

Event flag

CCF

RDERR

WRERR

Enable bit

CCFIE

ERRIE

Interrupt clear method set CCFC

(1) set ERRC

(1)

RM0471 Rev 5 493/1202

505

AES hardware accelerator (AES) RM0471

17.6 AES processing latency

The tables below summarize the latency to process a 128-bit block for each mode of operation.

Key size

Table 88. Processing latency for ECB, CBC and CTR

Mode of operation Algorithm

128-bit

256-bit

Mode 1: Encryption

Mode 2: Key derivation

Mode 3: Decryption

Mode 4: Key derivation then decryption

Mode 1: Encryption

Mode 2: Key derivation

Mode 3: Decryption

Mode 4: Key derivation then decryption

ECB, CBC, CTR

ECB, CBC

ECB, CBC, CTR

ECB, CBC

Clock cycles

145

106

Key size

Table 89. Processing latency for GCM and CCM (in clock cycles)

Mode of operation Algorithm Init Phase

Header phase

(1)

Payload

phase

(1)

128-bit

256-bit

Mode 1: Encryption/

Mode 3: Decryption

Mode 1: Encryption/

Mode 3: Decryption

GCM

CCM

GCM

CCM

114

162

1. Data insertion can include wait states forced by AES on the AHB bus (maximum 3 cycles, typical 1 cycle).

Tag phase

(1)

17.7.1 AES control register (AES_CR)

Address offset: 0x00

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23

Res.

15 14 13 12

Res.

GCMPH[1:0] rw rw rw

11 10 9 8 rw

22 21

NPBLB[3:0] rw

6 rw

20 19

Res.

18 17

Res.

16 rw

4 3 rw

2 1 rw

0 rw

ERRIE CCFIE ERRC CCFC CHMOD[1:0] MODE[1:0] DATATYPE[1:0] EN rw rw rw rw rw rw rw rw rw rw rw

494/1202 RM0471 Rev 5

RM0471 AES hardware accelerator (AES)

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:20 NPBLB[3:0]: Number of padding bytes in last block

The bitfield sets the number of padding bytes in last block of payload:

0000: All bytes are valid (no padding)

0001: Padding for one least-significant byte of last block

...

1111: Padding for 15 least-significant bytes of last block

Bit 19 Reserved, must be kept at reset value.

Bit 18 KEYSIZE: Key size selection

This bitfield defines the length of the key used in the AES cryptographic core, in bits:

0: 128

1: 256

Attempts to write the bit are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access.

Bit 17 Reserved, must be kept at reset value.

Bit 15 Reserved, must be kept at reset value.

Bits 14:13 GCMPH[1:0]: GCM or CCM phase selection

This bitfield selects the phase of GCM, GMAC or CCM algorithm:

00: Init phase

01: Header phase

10: Payload phase

11: Final phase

The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the

ALGOMODE bitfield).

Bit 12 DMAOUTEN : DMA output enable

This bit enables/disables data transferring with DMA, in the output phase:

0: Disable

1: Enable

When the bit is set, DMA requests are automatically generated by AES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation).

Use of DMA with Mode 4 (single decryption) is not recommended.

Bit 11 DMAINEN : DMA input enable

This bit enables/disables data transferring with DMA, in the input phase:

0: Disable

1: Enable

When the bit is set, DMA requests are automatically generated by AES during the input data phase.

This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation).

Use of DMA with Mode 4 (single decryption) is not recommended.

Bit 10 ERRIE : Error interrupt enable

This bit enables or disables (masks) the AES interrupt generation when RDERR and/or WRERR is set:

0: Disable (mask)

1: Enable

RM0471 Rev 5 495/1202

505

AES hardware accelerator (AES) RM0471

Bit 9 CCFIE : CCF interrupt enable

This bit enables or disables (masks) the AES interrupt generation when CCF (computation complete flag) is set:

0: Disable (mask)

1: Enable

Bit 8 ERRC : Error flag clear

Upon written to 1, this bit clears the RDERR and WRERR error flags in the AES_SR register:

0: No effect

1: Clear RDERR and WRERR flags

Reading the flag always returns zero.

Bit 7 CCFC: Computation complete flag clear

Upon written to 1, this bit clears the computation complete flag (CCF) in the AES_SR register:

0: No effect

1: Clear CCF

Reading the flag always returns zero.

Bits 16, 6:5 CHMOD[2:0] : Chaining mode selection

This bitfield selects the AES chaining mode:

000: Electronic codebook (ECB)

001: Cipher-block chaining (CBC)

010: Counter mode (CTR)

011: Galois counter mode (GCM) and Galois message authentication code (GMAC)

100: Counter with CBC-MAC (CCM) others: Reserved

Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access.

Bits 4:3 MODE[1:0] : AES operating mode

This bitfield selects the AES operating mode:

00: Mode 1: encryption

01: Mode 2: key derivation (or key preparation for ECB/CBC decryption)

10: Mode 3: decryption

11: Mode 4: key derivation then single decryption

Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access. Any attempt to selecting Mode 4 while either

ECB or CBC chaining mode is not selected, defaults to effective selection of Mode 3. It is not possible to select a Mode 3 following a Mode 4.

Bits 2:1 DATATYPE[1:0] : Data type selection

This bitfield defines the format of data written in the AES_DINR register or read from the

AES_DOUTR register, through selecting the mode of data swapping:

00: None

01: Half-word (16-bit)

10: Byte (8-bit)

11: Bit

For more details, refer to

Section 17.4.13: AES data registers and data swapping

Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access.

496/1202 RM0471 Rev 5

RM0471 AES hardware accelerator (AES)

Bit 0 EN : AES enable

This bit enables/disables the AES peripheral:

0: Disable

1: Enable

At any moment, clearing then setting the bit re-initializes the AES peripheral.

This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase.

17.7.2 AES status register (AES_SR)

Address offset: 0x04

Reset value: 0x0000 0000

Res.

30 29

Res.

28 27

Res.

14 13

Res.

12 11

Res.

3 2 1 0

BUSY WRERR RDERR CCF r r r r

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 BUSY: Busy

This flag indicates whether AES is idle or busy during GCM payload encryption phase:

0: Idle

1: Busy

When the flag indicates “idle”, the current GCM encryption processing may be suspended to process a higher-priority message. In other chaining modes, or in GCM phases other than payload encryption, the flag must be ignored for the suspend process.

Bit 2 WRERR : Write error

This flag indicates the detection of an unexpected write operation to the AES_DINR register (during computation or data output phase):

0: Not detected

1: Detected

The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR register.

Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR register.

The flag setting has no impact on the AES operation. Unexpected write is ignored.

Bit 1 RDERR : Read error flag

This flag indicates the detection of an unexpected read operation from the AES_DOUTR register

(during computation or data input phase):

0: Not detected

1: Detected

The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR register.

Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR register.

The flag setting has no impact on the AES operation. Unexpected read returns zero.

RM0471 Rev 5 497/1202

505

AES hardware accelerator (AES) RM0471

Bit 0 CCF : Computation completed flag

This flag indicates whether the computation is completed:

0: Not completed

1: Completed

The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCFC bit of the AES_CR register.

Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the AES_CR register.

The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1.

Address offset: 0x08

Reset value: 0x0000 0000

Only 32-bit access type is supported.

31 rw

15 rw

30 29 rw

14 rw rw

13 rw

28 rw

12 rw

27 rw

11 rw

26 rw

10 rw

25 rw

9 rw

24 23

DIN[31:16] rw

8 rw

7 rw

DIN[15:0] rw

22 rw

6 rw

21 rw

5 rw

20 rw

4 rw

19 rw

3 rw

18 rw

2 rw

17 rw

1 rw

16 rw

0 rw

Bits 31:0 DIN[31:0] : Input data word

A four-fold sequential write to this bitfield during the input phase results in writing a complete 128-bit block of input data to the AES peripheral. From the first to the fourth write, the corresponding data weights are [127:96], [95:64], [63:32], and [31:0]. Upon each write, the data from the 32-bit input buffer are handled by the data swap block according to the DATATYPE[1:0] bitfield, then written into the AES core 128-bit input buffer.

The data signification of the input data block depends on the AES operating mode:

- Mode 1 (encryption): plaintext

- Mode 2 (key derivation): the bitfield is not used (AES_KEYRx registers used for input)

- Mode 3 (decryption) and Mode 4 (key derivation then single decryption): ciphertext

The data swap operation is described in

Section 17.4.13: AES data registers and data swapping on page 488 .

31 r

15 r

Address offset: 0x0C

Reset value: 0x0000 0000

Only 32-bit read access type is supported.

30 29 28 27 26 25 r

14 r r

13 r r

12 r r

11 r r

10 r r

9 r

24 23

DOUT[31:16] r

8 r

DOUT[15:0] r r

22 r

6 r

21 r

5 r

20 r

4 r

19 r

3 r

18 r

2 r

17 r

1 r

16 r

0 r

498/1202 RM0471 Rev 5

RM0471 AES hardware accelerator (AES)

Bits 31:0 DOUT[31:0] : Output data word

This read-only bitfield fetches a 32-bit output buffer. A four-fold sequential read of this bitfield, upon the computation completion (CCF set), virtually reads a complete 128-bit block of output data from the AES peripheral. Before reaching the output buffer, the data produced by the AES core are handled by the data swap block according to the DATATYPE[1:0] bitfield.

Data weights from the first to the fourth read operation are: [127:96], [95:64], [63:32], and [31:0].

The data signification of the output data block depends on the AES operating mode:

- Mode 1 (encryption): ciphertext

- Mode 2 (key derivation): the bitfield is not used (AES_KEYRx registers used for output)

- Mode 3 (decryption) and Mode 4 (key derivation then single decryption): plaintext

The data swap operation is described in

Section 17.4.13: AES data registers and data swapping on page 488 .

17.7.5 AES key register 0 (AES_KEYR0)

Address offset: 0x10

Reset value: 0x0000 0000

31 rw

30 29 rw

14 rw

28 rw

27 rw

26 rw

25 rw

24 23

KEY[31:16] rw rw

8 7

KEY[15:0] rw rw

22 rw

21 rw

20 rw

19 rw

18 rw

17 rw

16 rw

0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 KEY[31:0] : Cryptographic key, bits [31:0]

This bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on the operating mode:

- In Mode 1 (encryption), Mode 2 (key derivation) and Mode 4 (key derivation then single decryption): the value to write into the bitfield is the encryption key.

- In Mode 3 (decryption): the value to write into the bitfield is the encryption key to be derived before being used for decryption. After writing the encryption key into the bitfield, its reading before enabling AES returns the same value. Its reading after enabling AES and after the CCF flag is set returns the decryption key derived from the encryption key.

Note: In mode 4 (key derivation then single decryption) the bitfield always contains the encryption key.

The AES_KEYRx registers may be written only when KEYSIZE value is correct and when the AES peripheral is disabled (EN bit of the AES_CR register cleared). Note that, if, the key is directly loaded to AES_KEYRx registers (hence writes to key register is ignored and KEIF is set).

Refer to Section 17.4.14: AES key registers on page 490

for more details.

RM0471 Rev 5 499/1202

505

AES hardware accelerator (AES)

17.7.6 AES key register 1 (AES_KEYR1)

Address offset: 0x14

Reset value: 0x0000 0000

31 30 29 28 27 26 25 rw

15 rw rw

14 rw rw

13 rw rw

12 rw rw

11 rw rw

10 rw rw

9 rw

24 23

KEY[63:48] rw

8 rw

KEY[47:32] rw rw

22 rw

6 rw

21 rw

5 rw

20 rw

4 rw

19 rw

3 rw

Bits 31:0 KEY[63:32] : Cryptographic key, bits [63:32]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

17.7.7 AES key register 2 (AES_KEYR2)

Address offset: 0x18

Reset value: 0x0000 0000

31 rw

30 29 rw

14 rw

28 rw

27 rw

26 rw

25 rw

24 23

KEY[95:80] rw rw

8 7

KEY[79:64] rw rw

22 rw

21 rw

20 rw

19 rw

3 rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 KEY[95:64] : Cryptographic key, bits [95:64]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

17.7.8 AES key register 3 (AES_KEYR3)

Address offset: 0x1C

Reset value: 0x0000 0000

31 rw

30 rw

29 rw

28 rw

27 rw

26 rw

25 rw

24 23

KEY[127:112] rw

8 rw

7 rw

KEY[111:96] rw

22 rw

6 rw

21 rw

20 rw

19 rw

3 rw rw rw rw rw rw rw rw rw rw

Bits 31:0 KEY[127:96] : Cryptographic key, bits [127:96]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

18 rw

2 rw

18 rw

2 rw

18 rw

2 rw

17 rw

1 rw

RM0471

17 rw

1 rw

16 rw

0 rw

17 rw

1 rw

16 rw

0 rw

16 rw

0 rw

500/1202 RM0471 Rev 5

RM0471 AES hardware accelerator (AES)

17.7.9 AES initialization vector register 0 (AES_IVR0)

Address offset: 0x20

Reset value: 0x0000 0000

31 rw

15 rw

30 29 rw

14 rw rw

13 rw

28 rw

12 rw

27 rw

11 rw

26 rw

10 rw

25 rw

9 rw

24 23

IVI[31:16] rw

8 rw

7 rw

IVI[15:0] rw

22 rw

6 rw

21 rw

5 rw

20 rw

4 rw

19 rw

3 rw

18 rw

2 rw

17 rw

1 rw

Bits 31:0 IVI[31:0] : Initialization vector input, bits [31:0]

Refer to Section 17.4.15: AES initialization vector registers on page 490

for description of the

IVI[127:0] bitfield.

The initialization vector is only used in chaining modes other than ECB.

The AES_IVRx registers may be written only when the AES peripheral is disabled

16 rw

0 rw

Address offset: 0x24

Reset value: 0x0000 0000

31 rw

15 rw

30 29 rw

14 rw rw

13 rw

28 rw

12 rw

27 rw

11 rw

26 rw

10 rw

25 rw

9 rw

24 23

IVI[63:48] rw

8 rw

IVI[47:32] rw rw

22 rw

6 rw

21 rw

5 rw

20 rw

4 rw

Bits 31:0 IVI[63:32] : Initialization vector input, bits [63:32]

Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.

19 rw

3 rw

18 rw

2 rw

17 rw

1 rw

16 rw

0 rw

31 rw

15 rw rw

14 rw

Address offset: 0x28

Reset value: 0x0000 0000

30 29 28 27 26 25 rw

13 rw rw

12 rw rw

11 rw rw

10 rw rw

9 rw

24 23

IVI[95:80] rw rw

8 7

IVI[79:64] rw rw

22 rw

6 rw

21 rw

5 rw

20 rw

4 rw

19 rw

3 rw

18 rw

2 rw

17 rw

1 rw

16 rw

0 rw

RM0471 Rev 5 501/1202

505

AES hardware accelerator (AES)

Bits 31:0 IVI[95:64] : Initialization vector input, bits [95:64]

Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.

RM0471

Address offset: 0x2C

Reset value: 0x0000 0000

31 rw

30 29 rw

14 rw

28 rw

27 rw

26 rw

25 rw

24 23

IVI[127:112] rw

8 rw

IVI[111:96] rw rw

22 rw

21 rw

20 rw

4 rw rw rw rw rw rw rw rw rw rw

Bits 31:0 IVI[127:96] : Initialization vector input, bits [127:96]

Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.

19 rw

3 rw

17.7.13 AES key register 4 (AES_KEYR4)

Address offset: 0x30

Reset value: 0x0000 0000

31 rw

30 29 rw

14 rw

28 rw

27 rw

26 rw

25 rw

24 23

KEY[159:144] rw rw

8 7

KEY[143:128] rw rw

22 rw

21 rw

20 rw

19 rw

3 rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 KEY[159:128] : Cryptographic key, bits [159:128]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

17.7.14 AES key register 5 (AES_KEYR5)

Address offset: 0x34

Reset value: 0x0000 0000

31 rw

30 29 rw

14 rw

28 rw

27 rw

26 rw

25 rw

24 23

KEY[191:176] rw

8 rw

KEY[175:160] rw rw

22 rw

21 rw

20 rw

19 rw

3 rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 KEY[191:160] : Cryptographic key, bits [191:160]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

18 rw

2 rw

17 rw

1 rw

16 rw

0 rw

18 rw

2 rw

17 rw

1 rw

16 rw

0 rw

18 rw

2 rw

17 rw

1 rw

16 rw

0 rw

502/1202 RM0471 Rev 5

RM0471 AES hardware accelerator (AES)

17.7.15 AES key register 6 (AES_KEYR6)

Address offset: 0x38

Reset value: 0x0000 0000

31 rw

30 29 rw

14 rw

28 rw

27 rw

26 rw

25 rw

24 23

KEY[223:208] rw

8 rw

KEY[207:192] rw rw

22 rw

21 rw

20 rw

19 rw

3 rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 KEY[223:192] : Cryptographic key, bits [223:192]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

18 rw

2 rw

17 rw

1 rw

16 rw

0 rw

17.7.16 AES key register 7 (AES_KEYR7)

Address offset: 0x3C

Reset value: 0x0000 0000

31 rw

15 rw

30 29 rw

14 rw rw

13 rw

28 rw

12 rw

27 rw

11 rw

26 rw

10 rw

25 rw

9 rw

24 23

KEY[255:240] rw rw

8 7

KEY[239:224] rw rw

22 rw

6 rw

21 rw

5 rw

20 rw

4 rw

19 rw

3 rw

18 rw

2 rw

17 rw

1 rw

16 rw

0 rw

Bits 31:0 KEY[255:224] : Cryptographic key, bits [255:224]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

Note: The key registers from 4 to 7 are used only when the key length of 256 bits is selected. They have no effect when the key length of 128 bits is selected (only key registers 0 to 3 are used in that case).

Note:

Address offset: 0x040 + x * 0x4, (x = 0 to 7)

Reset value: 0x0000 0000

These registers contain the complete internal register states of the AES processor when the

AES processing of the current task is suspended to process a higher-priority task.

Upon suspend, the software reads and saves the AES_SUSPxR register contents (where x is from 0 to 7) into memory, before using the AES processor for the higher-priority task.

Upon completion, the software restores the saved contents back into the corresponding suspend registers, before resuming the original task.

These registers are used only when GCM, GMAC, or CCM chaining mode is selected.

These registers can be read only when AES is enabled. Reading these registers while AES is disabled returns 0x0000 0000.

RM0471 Rev 5 503/1202

505

AES hardware accelerator (AES) RM0471

31 rw

30 29 rw

14 rw

28 rw

27 rw

26 rw

25 rw

24 23

SUSP[31:16] rw rw

8 7

SUSP[15:0] rw rw

22 rw

21 rw

20 rw

19 rw

18 rw

17 rw

16 rw

0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 SUSP[31:0] : AES suspend

Upon suspend operation, this bitfield of the corresponding AES_SUSPxR register takes the value of one of internal AES registers.

17.7.18 AES register map

Table 90. AES register map and reset values

Offset Register

AES_CR

0x000

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_SR

0x004

0x008

0x00C

0x010

0x014

0x018

0x01C

0x020

0x024

0x028

0x02C

Reset value

AES_DINR

Reset value

AES_DOUTR

Reset value

AES_KEYR0

Reset value

AES_KEYR1

Reset value

AES_KEYR2

Reset value

AES_KEYR3

Reset value

AES_IVR0

Reset value

AES_IVR1

Reset value

AES_IVR2

Reset value

AES_IVR3

Reset value

0 0 0 0

DIN[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DOUT[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

KEY[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

KEY[63:32]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

KEY[95:64]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

KEY[127:96]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IVI[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IVI[63:32]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IVI[95:64]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IVI[127:96]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

504/1202 RM0471 Rev 5

RM0471 AES hardware accelerator (AES)

Table 90. AES register map and reset values (continued)

Offset Register

0x030

0x034

0x038

0x03C

0x040

0x044

0x048

0x04C

0x050

0x054

0x058

0x05C

0x060-

0x3FF

AES_KEYR4

Reset value

AES_KEYR5

Reset value

AES_KEYR6

Reset value

AES_KEYR7

Reset value

AES_SUSP0R

Reset value

AES_SUSP1R

Reset value

AES_SUSP2R

Reset value

AES_SUSP3R

Reset value

AES_SUSP4R

Reset value

AES_SUSP5R

Reset value

AES_SUSP6R

Reset value

AES_SUSP7R

Reset value

Reserved

KEY[159:128]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

KEY[191:160]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

KEY[223:192]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

KEY[255:224]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SUSP[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SUSP[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SUSP[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SUSP[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SUSP[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SUSP[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SUSP[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SUSP[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 55 for the register boundary addresses.

RM0471 Rev 5 505/1202

505

Public key accelerator (PKA)

18 Public key accelerator (PKA)

RM0471

18.1 Introduction

PKA (public key accelerator) is intended for the computation of cryptographic public key primitives, specifically those related to RSA, Diffie-Hellmann or ECC (elliptic curve cryptography) over GF( p ) (Galois fields). To achieve high performance at a reasonable cost, these operations are executed in the Montgomery domain.

All needed computations are performed within the accelerator, so no further hardware/software elaboration is needed to process the inputs or the outputs.

 Acceleration of RSA, DH and ECC over GF( p ) operations, based on the Montgomery method for fast modular multiplications. More specifically:

– RSA modular exponentiation, RSA Chinese Remainder Theorem (CRT) exponentiation

– ECC scalar multiplication, point on curve check

– ECDSA signature generation and verification

 Capability to handle operands up to 3136 bits for RSA/DH and 640 bits for ECC.

 Arithmetic and modular operations such as addition, subtraction, multiplication, modular reduction, modular inversion, comparison, and Montgomery multiplication.

 Built-in Montgomery domain inward and outward transformations.

 AMBA AHB slave peripheral, accessible through 32-bit word single accesses only

(otherwise, for writes, an AHB bus error is generated, and write accesses are ignored).

18.3.1 PKA block diagram

Figure 114 shows the block diagram of the public key accelerator PKA.

506/1202 RM0471 Rev 5

RM0471 pka_hclk pka_it

Public key accelerator (PKA)

Figure 114. PKA block diagram

AHB interface control status clear

Banked registers (main)

PKA_CR

PKA_SR

PKA_CLRFR

32-bit access

PKA32

894x32-bit

PKA RAM

IRQ interface

Control logic

PKA core

32-bit

MS45419V1

18.3.2 PKA internal signals

Table 91 lists internal signals available at the IP level, not necessarily available on product

bonding pads.

Signal name pka_hclk pka_it

Table 91. Internal input/output signals

Signal type Description

Digital input

Digital output

AHB bus clock

Public key accelerator IP global interrupt request

18.3.3 PKA reset and clocks

PKA is clocked on the AHB bus clock. The RAM receives this clock directly, the core is clocked at half the frequency.

Note:

Overview

Public key accelerator (PKA) is used to accelerate Rivest, Shamir and Adleman (RSA),

Diffie-Hellman (DH) as well as ECC over prime field operations. Supported operand sizes is up to 3136 bits for RSA and DH, and up to 640 bits for ECC.

The PKA supports all non-singular elliptic curves defined over prime fields, that can be described with a short Weierstrass equation y 2 = x 3 + a x + b (mod p). More information is

found in Section 18.5.1: Supported elliptic curves .

Binary curves, Edwards curves and Curve25519 are not supported by the PKA.

A memory of 3576 bytes (894 words of 32 bits) called PKA RAM is used for providing initial data to the PKA, and for holding the results after computation is completed. Access is done though the PKA AHB interface.

RM0471 Rev 5 507/1202

531

Public key accelerator (PKA) RM0471

PKA operating modes

The list of operations the PKA can perform is detailed in Table 92 and Table 93

, respectively, for integer arithmetic functions and prime field (Fp) elliptic curve functions.

Each of these operating modes has an associated code that has to be written to the MODE field in the PKA_CR register.

PKA_CR.MODE[5:0]

Table 92. PKA integer arithmetic functions list

Performed operation

Hex Binary

0x08

0x0D

0x09

0x0A

0x0B

0x0C

0x07

0x01

0x0E

0x0F

0x10

0x00

0x02

000001 Montgomery parameter computation R2 mod n

001110 Modular addition (A+B) mod n

001111 Modular subtraction (A-B) mod n

010000 Montgomery multiplication (AxB) mod n

000000 Modular exponentiation A e mod n

000010 Modular exponentiation A e

mod n (fast mode)

001000 Modular inversion A-1 mod n

001101 Modular reduction A mod n

001001 Arithmetic addition A+B

001010 Arithmetic subtraction A-B

001011 Arithmetic multiplication AxB

001100

000111

Arithmetic comparison (A=B, A>B, A<B)

RSA CRT exponentiation

Reference

Table 93. PKA prime field (Fp) elliptic curve functions list

PKA_CR.MODE[5:0]

Performed operation

Hex Binary

Reference

Section 18.4.14

0x28

0x20

0x22

0x24

0x26

101000 Point on elliptic curve Fp check

100000 ECC scalar multiplication kP

100010 ECC scalar multiplication kP (fast mode)

100100 ECDSA sign

100110 ECDSA verification

Section 18.4.15

Section 18.4.16

Section 18.4.17

Montgomery space and fast mode operations

For efficiency reason the PKA internally performs modular multiply operations in the

Montgomery domain, automatically performing inward and outward transformations.

As Montgomery parameter computation is time consuming the application can decide to use a faster mode of operation, during which the precomputed Montgomery parameter is

508/1202 RM0471 Rev 5

RM0471 Public key accelerator (PKA) supplied before starting the operation. Performance improvement is detailed in

Section 18.5.2: Computation times

The operations using fast mode are modular exponentiation and scalar multiplication.

18.3.5 Typical applications for PKA

Introduction

The PKA can be used to accelerate a number of public key cryptographic functions. In particular:

 RSA encryption and decryption

 RSA key finalization

 CRT-RSA decryption

 DSA and ECDSA signature generation and verification

 DH and ECDH key agreement

Specifications of the above functions are given in following publications:

 FIPS PUB 186-4, Digital Signature Standard (DSS), July 2013 by NIST

 PKCS #1, RSA Cryptography Standard, v1.5, v2.1 and v2.2. by RSA Laboratories

 IEEE1363-2000, IEEE Standard Specifications for Public-Key Cryptography, January

2000

 ANSI X9.62-2005, Public Key Cryptography for the Financial Services Industry, The

Elliptic Curve Digital Signature Algorithm (ECDSA), November 2005

The principles of the main functions are described in this section, for a more detailed description refer to the above cited documents.

RSA key pair

For following RSA operations a public key and a private key information are defined as below:

 Alice transmits her public key ( n , e ) to Bob. Numbers n and e are very large positive integers.

 Alice keeps secret her private key d, also a very large positive integer. Alternatively this private key can also be represented by a quintuple (p, q, dp, dq, qInv).

For more information on above representations refer to the RSA specification.

RSA encryption/decryption principle

As recommended by the PKCS#1 specification, Bob, to encrypt message M using Alice’s public key ( n , e ) must go through the following steps:

Compute the encoded message EM = ENCODE(M), where ENCODE is an encoding method.

2. Turn EM into an integer m , with 0 ≤ m < n and ( m , n ) being co-primes.

3. Compute ciphertext c = m e mod n .

4. Convert the integer c into a string ciphertext C.

RM0471 Rev 5 509/1202

531

Public key accelerator (PKA)

Note:

RM0471

Alice, to decrypt ciphertext c using her private key, follows the steps indicated below:

Convert the ciphertext C to an integer ciphertext representative c.

plaintext = c d mod n = ( m e ) d mod n . If the private key is the quintuple (p, q, dp, dq, qInv), then plaintext m is obtained by performing the operations: a) m

= c dp b) m

= c dq

mod p

mod q c) h = qInv ( m

– m

) mod p d) m = m

+ h q

3. Convert the integer message representative m to an encoded message EM.

4. Recover message M= DECODE(EM), where DECODE is a decoding method.

Above operations can be accelerated by PKA using Modular exponentiation A

e mod n if the private key is d , or

RSA CRT exponentiation

if the private key is the quintuple (p, q, dp, dq, qInv).

The decoding operation and the conversion operations between message and integers are specified in PKCS#1 standard.

Elliptic curve selection

For following ECC operations curve parameters are defined as below:

 Curve corresponds to the elliptic curve field agreed among actors (Alice and Bob).

Supported curves parameters are summarized in Section 18.5.1: Supported elliptic curves .

 G is the chosen elliptic curve base point (also known as generator), with a large prime order n (i.e. n x G = identity element O).

ECDSA message signature generation

ECDSA (Elliptic Curve Digital Signature Algorithm) signature generation function principle is the following: Alice, to sign a message m using her private key integer d

A below.

, follows the steps

Calculate e = HASH( m ), where HASH is a cryptographic hash function.

2. Let z be the L n

leftmost bits of e, where L n

is the bit length of the group order n .

3. Select a cryptographically secure random integer k where 0 < k < n .

4. Calculate the curve point (x

, y

) = k x G.

6. Calculate = k

mod

-1 n . If

(z + rd

A r =0 go back to step 3.

) mod n . If s =0 go back to step 3.

7. The signature is the pair ( r , s ).

Steps 4 to 7 are accelerated by PKA using:



ECDSA sign or

 All of the operations below:

–

ECC Fp scalar multiplication

k x P

–

Modular reduction A mod

–

Modular inversion

A -1 mod n

–

Modular addition and

Modular and Montgomery multiplication

510/1202 RM0471 Rev 5

RM0471 Public key accelerator (PKA)

ECDSA signature verification

ECDSA (elliptic curve digital signature algorithm) signature verification function principle is the following: Bob, to authenticate Alice's signature, must have a copy of her public key curve point Q

Bob can verify that Q

is a valid curve point going through the following steps:

check that Q

is not equal to the identity element O

is on the agreed curve

3. check that n x Q

= O.

Then Bob follows the procedure detailed below:

verify that r and s are integer in [1, n-1]

2. calculate = HASH( m ), where HASH is the agreed cryptographic hash function

3. let z be the L n

leftmost bits of e

4. calculate s

-1

mod n

5. calculate = zw mod n and u

= rw mod n

6. calculate the curve point (x

, y

) = u

x G + u

x Q

7. the signature is valid if r = x

(mod n ), it is invalid otherwise.

Steps 4 to 7 are accelerated by PKA using

ECDSA verification .

18.3.6 PKA procedure to perform an operation

Note:

Enabling/disabling PKA

Setting the EN bit to 1 in PKA_CR register enables the PKA peripheral. When EN = 0, the

PKA peripheral is kept under reset, with PKA memory still accessible by the application through the AHB interface.

Clearing EN bit to 0 while a calculation is in progress causes the operation to be aborted. In this case, the content of the PKA memory is not guaranteed.

Data formats

The format of the input data and the results in the PKA RAM are specified, for each operation, in

Section 18.4

Executing a PKA operation

Each of the supported PKA operation is executed using the following procedure:

Load initial data into the PKA internal RAM, which is located at address offset 0x400.

2. Write in the MODE field of PKA_CR register, specifying the operation which is to be executed and then assert the START bit, also in PKA_CR register.

3. Wait until the PROCENDF bit in the PKA_SR register is set to “1”, indicating that the computation is complete.

4. Read the result data from the PKA internal RAM, then clear PROCENDF bit by setting

PROCENDFC bit in PKA_CLRFR.

When PKA is busy (BUSY = 1) any access by the application to PKA RAM is ignored, and the flag RAMERRF is set in PKA_SR.

RM0471 Rev 5 511/1202

531

Public key accelerator (PKA) RM0471

Using precomputed Montgomery parameters (PKA fast mode)

As explained in Section 18.3.4

, when computing many operations with the same modulus it can be beneficial for the application to compute only once the corresponding Montgomery parameter (see, for example,

Section 18.4.5

). This is know as “fast mode”.

To manage Fast Mode usage the recommended procedure is described below:

Load in PKA RAM the modulus size and value information. Such information is compiled in

Section 18.5.1

2. Program in PKA_CR register the PKA in

Montgomery parameter computation

mode

(MODE=”0x1”) then assert the START bit.

3. Wait until the PROCENDF bit in the PKA_SR register is set to “1”, then read back from

PKA memory the corresponding Montgomery parameter, and then clear PROCENDF bit by setting PROCENDFC bit in PKA_CLRFR.

4. Proceed with the required PKA operation, loading on top of regular input data the

Montgomery information R2 mod m. All addresses are indicated in Section 18.4

18.3.7 PKA error management

When PKA is used some errors can occur:

 The access to PKA RAM falls outside the expected range. In this case the Address

Error flag (ADDRERRF) is set in the PKA_SR register.

 An AHB access to the PKA RAM occurred while the PKA core was using it. In this case the RAM Error Flag (RAMERRF) is set in the PKA_SR register, reads to PKA RAM return zero, while writes are ignored.

For each error flag above PKA generates an interrupt if the application sets the corresponding bit in PKA_CR register (see

Section 18.6

for details).

ADDRERRF and RAMERRF errors are cleared by setting the corresponding bit in

PKA_CLRFR.

The PKA can be re-initialized at any moment by resetting the EN bit in the PKA_CR register.

18.4 PKA operating modes

18.4.1 Introduction

The various operations supported by PKA are described in the following subsections, clarifying the associated format of the input data and of the results, both stored in the PKA

RAM.

The following information applies to all PKA operations.

 PKA core processes 32-bit words

 Supported operand “Size” are:

– ROS (RSA operand size): data size is ( rsa_size /32+1) words, with rsa_size equal to the chosen modulus length. For example, when computing RSA with an operand size of 1024 bits, ROS is equal to 33 words, or 1056 bits.

– EOS (ECC operand size): data size is ( ecc_size /32+1) words, with ecc_size equal to the chosen prime modulus length. For example, when computing ECC with an operand size of 192 bits, EOS is equal to 7 words, or 224 bits.

512/1202 RM0471 Rev 5

RM0471 Public key accelerator (PKA)

Note:

Fractional results for above formulas are rounded up to the nearest integer since PKA core processes 32-bit words.

The maximum ROS is 99 words (3136-bit max exponent size), while the maximum EOS is

21 words (640-bit max operand size).

 The column indicated with Storage in the following tables indicates either the Register

PKA_CR, or the address offset within the PKA, located in the PKA RAM area (starting from 0x400). To recover the physical address of an operand the application must add to the indicated offset the base address of the PKA.

 About writing parameters (“IN” direction)

– When elements are written as input in the PKA memory, an additional word with all bits equal to zero must be added. As an example, when ECC P256 is used and when loading an input (represented on 256 bits or 8 words), an additional word is expected by the PKA and it has to be filled with zeros.

– About endianess, for example to prepare the operation ECC Fp scalar multiplication, when application writes x p

coordinate for an ECC P256 curve

(EOS= 9 words) the least significant bit is to be placed in bit 0 at address offset

0x55C; the most significant bit is to be placed in bit 31 of address offset 0x578.

Then, as mentioned above, word 0x00000000 should also be written at address offset 0x57C.

– Unless indicated otherwise all operands in the tables are integers.

 About PKA outputs (“OUT” direction)

– Unless specified in the tables PKA does not provide an error output when a wrong parameter is written by the application.

Caution: Validity of all input parameters to the PKA must be checked before issuing any PKA operation. Indeed, the PKA assumes that all input parameters are valid and consistent with each other.

18.4.2 Montgomery parameter computation

This function is used to compute the Montgomery parameter (R 2 mod n ) used by PKA to convert operands into the Montgomery residue system representation.

Note: This operation can also be used with ECC curves. In this case prime modulus length and

EOS size must be used.

Operation instructions for Montgomery parameter computation are summarized in

Table 94 .

Table 94. Montgomery parameter computation

Parameters with direction Value (Note) Storage

MODE

Modulus length

Modulus value n

OUT Result: R 2 n

0x01

(In bits, 0 ≤ value < 3136bits)

(Odd integer only, n < 2

3136

)

PKA_CR

RAM@0x404

RAM@0xD5C

RAM@0x594

Size

6 bits

32 bits

ROS

Modular addition operation consists in the computation of A + B mod n . Operation

instructions are summarized in Table 95

RM0471 Rev 5 513/1202

531

Public key accelerator (PKA)

Parameters with direction

Table 95. Modular addition

Value (Note)

MODE

Operand length

0x0E

(In bits, not null)

IN Operand A

Operand B

Modulus value n

(0 ≤ A < n)

(0 ≤ B < n)

(n < 2

3136

)

OUT Result: A+B mod n (0 ≤ result < n)

Storage

PKA_CR

RAM@0x404

RAM@0x8B4

RAM@0xA44

RAM@0xD5C

RAM@0xBD0

RM0471

Size

6 bits

32 bits

ROS

Modular subtraction operation consists in the following computations:

 If A ≥ B result equals A - B mod n

 If A < B result equals A + n - B mod n

Operation instructions are summarized in Table 96

Parameters with direction

Table 96. Modular subtraction

Value (Note)

MODE

Operand length

Operand A

0x0F

(In bits, not null)

(0 ≤ A < n)

Operand B

Modulus value n

(0 ≤ B < n)

(n < 2 3136 )

OUT Result: A-B mod n (0 ≤ result < n)

Storage

PKA_CR

RAM@0x404

RAM@0x8B4

RAM@0xA44

RAM@0xD5C

RAM@0xBD0

Size

6 bits

32 bits

ROS

18.4.5 Modular and Montgomery multiplication

To be more efficient when performing a sequence of multiplications the PKA accelerates multiplication which has at least one input in the Montgomery domain. The two main uses of this operation are:

 Map a value from natural domain to Montgomery domain and vice-versa

 Perform a modular multiplication A x B mod n

The method to perform above operations are described below. Note that “x” function is this operation, and A, B, C operands are in the natural domain.

514/1202 RM0471 Rev 5

RM0471 Public key accelerator (PKA)

Inward (or outward) conversion into (or from) Montgomery domain a) Let’s assume A is an integer in the natural domain

Compute r2modn using

Montgomery parameter computation

Result AR= A x r2modn mod n is A in the Montgomery domain b) Let’s assume BR is an integer in the Montgomery domain

Result B = BR x 1 mod n is B in the natural domain

Similarly, above value AR computed in a) can be converted into the natural domain by computing A = AR x 1 mod n

2. Simple modular multiplication A x B mod n a) Compute using

Montgomery parameter computation

AR A mod n . Output is in the Montgomery domain c) Compute AB= AR x B mod n . Output is in natural domain

3. Multiple modular multiplication A x B x C mod n a) Compute using

Montgomery parameter computation

AR A mod n . Output is in the Montgomery domain c) Compute BR = B x r2modn mod n . Output is in the Montgomery domain d) Compute ABR= AR x BR mod n . Output is in the Montgomery domain e) Compute CR = C x r2modn mod n . Output is in the Montgomery domain f) Compute ABCR= ABR x CR mod n . Output is in the Montgomery domain g) (optional) Repeat the two steps above if more operands need to be multiplied h) Compute ABC= ABCR x 1 mod n to retrieve the result in natural domain

Operation instructions for Montgomery multiplication are summarized in Table 97

Table 97. Montgomery multiplication

Parameters with direction Value (Note) Storage Size

MODE

Operand length

Operand A IN

Operand B

Modulus value n

OUT Result: AxB mod n

(1)

0x10

(In bits, not null)

(0 ≤ A < n)

(0 ≤ B < n)

(Odd integer only, n < 2 3136 )

PKA_CR

RAM@0x404

RAM@0x8B4

RAM@0xA44

RAM@0xD5C

RAM@0xBD0

6 bits

32 bits

ROS

1. Result in Montgomery domain or in natural domain, depending upon the inputs nature (see examples

2 and 3 ).

Modular exponentiation operation is commonly used to perform a single-step RSA operation. It consists in the computation of A e

mod n .

Operation instructions for modular exponentiation are summarized in Table 98

(normal mode) and in

Table 99

(fast mode). Fast mode usage is explained in Section 18.3.6

RM0471 Rev 5 515/1202

531

Public key accelerator (PKA)

Table 98. Modular exponentiation (normal mode)

Parameters with direction Value (Note) Storage

IN/OUT

MODE

Exponent length

Operand length

Exponent e

Modulus value n

OUT Result: A e

mod n

0x00

(in bits, not null)

Operand A (base of exponentiation)

(0 ≤ A < n)

≤

(Odd integer only, n < 2

≤

e < n)

result < n)

3136

)

PKA_CR

RAM@0x400

RAM@0x404

RAM@0xA44

RAM@0xBD0

RAM@0xD5C

RAM@0x724

Table 99. Modular exponentiation (fast mode)

Parameters with direction Value (Note) Storage

MODE

Exponent length

Operand length

0x02

(in bits, not null)

IN/OUT

Operand A (base of exponentiation)

(0 ≤ A < n)

Exponent e

Modulus value n

(0 ≤ e < n)

(Odd integer only, n < 2

3136

)

IN/OUT

Montgomery param

R2 mod n

OUT Result: A e

mod n

(mandatory)

(0 ≤ result < n)

PKA_CR

RAM@0x400

RAM@0x404

RAM@0xA44

RAM@0xBD0

RAM@0xD5C

RAM@0x594

RAM@0x724

RM0471

Size

6 bits

32 bits

ROS

Size

6 bits

32 bits

ROS

516/1202

Modular inversion operation consists in the computation of multiplicative inverse A

-1

mod n .

If the modulus n is prime, for all values of A (1 ≤ A < n ) modular inversion output is valid. If the modulus n is not prime, A has an inverse only if the largest common divisor between A and n is 1.

If the operand A is a divisor of the modulus n, the result is a multiple of a factor of n .

Operation instructions for modular inversion are summarized in

Table 100 .

Parameters with direction

Table 100. Modular inversion

Value (Note)

MODE 0x08

Operand length (In bits, not null)

Operand A (0 ≤ A < n)

Modulus value n (Odd integer only, n < 2

OUT Result: A -1 mod n 0 < result < n

3136

)

Storage

PKA_CR

RAM@0x404

RAM@0x8B4

RAM@0xA44

RAM@0xBD0

Size

6 bits

32 bits

ROS

RM0471 Rev 5

RM0471 Public key accelerator (PKA)

Modular reduction operation consists in the computation of the remainder of A divided by n.

Operation instructions are summarized in Table 101 .

Parameters with direction

MODE

Operand length

Modulus length

Operand A

Modulus value n

OUT Result A mod n

Table 101. Modular reduction

Value (Note)

0x0D

(In bits, not null)

(In bits, 8 < value < 3136)

(0 ≤ A < 2n < 2

3136

)

(Odd integer only, n < 2 3136 )

(0 < result < n)

Storage

PKA_CR

RAM@0x400

RAM@0x404

RAM@0x8B4

RAM@0xA44

RAM@0xBD0

Size

6 bits

32 bits

ROS

Arithmetic addition operation consists in the computation of A + B. Operation instructions

are summarized in Table 102 .

Parameters with direction

Table 102. Arithmetic addition

Value (Note)

MODE 0x09

OUT

Operand length M (In bits, not null)

Operand A (0 ≤ < A < 2

)

Operand B (0 ≤ < B < 2

)

Result: A+B (0 ≤ result < 2

M+1

)

Storage

PKA_CR

RAM@0x404

RAM@0x8B4

RAM@0xA44

RAM@0xBD0

Size

6 bits

32 bits

ROS

ROS + 1

Arithmetic subtraction operation consists in the following computations:

 If A ≥ B result equals A - B

 If A < B and M/32 residue is >0 result equals A + 2 int(M/32)*32+1 - B

 If A < B and M/32 residue is 0 result equals A + 2 int(M/32)*32

- B

Operation instructions are summarized in Table 103 .

Parameters with direction

Table 103. Arithmetic subtraction

Value (Note) Storage

MODE 0x0A

OUT

Operand length M (In bits, not null)

Operand A (0 ≤ < A < 2

)

Operand B

Result: A-B

(0 ≤ < B < 2

)

(0 ≤ result < 2 M )

PKA_CR

RAM@0x404

RAM@0x8B4

RAM@0xA44

RAM@0xBD0

RM0471 Rev 5

Size

6 bits

32 bits

ROS

517/1202

531

Public key accelerator (PKA) RM0471

Arithmetic multiplication operation consists in the computation of AxB. Operation

instructions are summarized in Table 104 .

Parameters with direction

Table 104. Arithmetic multiplication

Value (Note) Storage

MODE 0x0B

OUT

Operand length M (In bits, not null)

Operand A (0 ≤ < A < 2

)

Operand B

Result: AxB

(0 ≤ < B < 2

)

(0 ≤ result < 2 M )

PKA_CR

RAM@0x404

RAM@0x8B4

RAM@0xA44

RAM@0xBD0

Size

6 bits

32 bits

ROS

2xROS

Arithmetic comparison operation consists in the following computation:

 If A=B then result=0x0

 If A>B then result=0x1

 If A<B then result=0x2

Operation instructions for arithmetic comparison are summarized in

Table 105

Table 105. Arithmetic comparison

Parameters with direction Value (Note) Storage

MODE

Operand length M

Operand A

Operand B

0x0C

(In bits, not null)

(0 ≤ < A < 2

)

(0 ≤ < B < 2 M )

OUT Result A=B or A>B or A<B 0x0, 0x1 or 0x02

PKA_CR

RAM@0x404

RAM@0x8B4

RAM@0xA44

RAM@0xBD0

Size

6 bits

32 bits

ROS

32 bits

For efficiency many popular crypto libraries like OpenSSL RSA use the following optimization for decryption and signing based on the Chinese remainder theorem (CRT):

 p and q are precomputed primes, stored as part of the private key

 d

= d mod ( p -1)

 d

= d mod ( q -1) and

 q inv

= q -1 mod p

518/1202 RM0471 Rev 5

RM0471 Public key accelerator (PKA)

These values allow the recipient to compute the exponentiation m = A d (mod pq) more efficiently as follows:

 m

= A dP

mod p

 m

= A dQ mod p

 h = q inv

- m

) mod p , with m

> m

 m = m

+ h q

Operation instructions for computing CRT exponentiation A d mod pq are summarized in

Table 106

Parameters with direction

Table 106. CRT exponentiation

Value (Note)

IN MODE 0x07

Operand length

Operand d

Operand q

Prime p

(1)

Q inv

(in bits, not null)

(0 ≤ d

< 2

M/2

)

(0 ≤ d

< 2

M/2

)

(0 ≤ q inv

< 2

M/2

)

(0 ≤ p < 2

M/2

)

Prime q

(1)

Operand A

(0 ≤ q< 2

M/2

)

(0 ≤ A< 2 M/2 )

OUT Result: A d

mod pq (0 ≤ result < pq )

1. Must be different from 2.

Storage

PKA_CR

RAM@0x404

RAM@0x65C

RAM@0xBD0

RAM@0x7EC

RAM@0x97C

RAM@0xD5C

RAM@0xEEC

RAM@0x724

Size

6 bits

32 bits

ROS/2

ROS

18.4.14 Point on elliptic curve Fp check

This operation consists in checking whether a given point P (x, y) satisfies or not the curves over prime fields equation y

= ( x

+ ax + b ) mod p, where a and b are elements of the curve.

Operation instructions for point on elliptic curve Fp check are summarized in Table 107 .

RM0471 Rev 5 519/1202

531

Public key accelerator (PKA) RM0471

Table 107. Point on elliptic curve Fp check

Parameters with direction Value (Note) Storage

MODE PKA_CR

Modulus length

Curve coefficient a sign

Curve coefficient |a|

Curve coefficient b

Curve modulus value p

Point P coordinate x

Point P coordinate y

OUT Result: P on curve

0x28

(In bits, not null,

8 < value < 640)

0x0: positive

0x1: negative

(Absolute value, |a| < p)

(|b| < p)

(Odd integer prime,

0 < p < 2640)

(x < p )

(y < p )

0x0: point on curve

Not 0x0: point not on curve

RAM@0x404

RAM@0x408

RAM@0x40C

RAM@0x7FC

RAM@0x460

RAM@0x55C

RAM@0x5B0

RAM@0x400

Size

6 bits

32 bits

EOS

32 bits

18.4.15 ECC Fp scalar multiplication

This operation consists in the computation of a k x P (x

, y

), where P is a point on a curve over prime fields and “x” is the elliptic curve scalar point multiplication. Result of the computation is a point that belongs to the same curve or a point at infinity.

Operation instructions for ECC Fp scalar multiplication are summarized in

Table 108

(normal mode) and

Table 109

(fast mode). Fast mode usage is explained in

Section 18.3.6

Table 108. ECC Fp scalar multiplication

Parameters with direction Value (Note) Storage

PKA_CR IN

OUT

MODE

Scalar multiplier k length

Modulus length

Curve coefficient a sign

0x20

(In bits, not null,

8 < value < 640)

(In bits, not null,

8 < value < 640)

0x0: positive

0x1: negative

(Absolute value, |a| < p) Curve coefficient |a|

Curve modulus value

Scalar multiplier k p

(Odd integer prime,

0 < p < 2 640 )

(0 ≤ k < 2

640

)

Point P coordinate x

(x < p )

Point P coordinate y

(y < p )

Result: k x P coordinate x (result < p )

Result: k x P coordinate y (result < p )

RAM@0x400

RAM@0x404

RAM@0x408

RAM@0x40C

RAM@0x460

RAM@0x508

RAM@0x55C

RAM@0x5B0

RAM@0x55C

RAM@0x5B0

Size

6 bits

32 bits

EOS

520/1202 RM0471 Rev 5

RM0471 Public key accelerator (PKA)

Table 109. ECC Fp scalar multiplication (Fast Mode)

Parameters with direction Value (Note) Storage

PKA_CR IN

OUT

MODE

Scalar multiplier k length

Modulus length

Curve coefficient a sign

0x22

(In bits, not null,

8 < value < 640)

(In bits, not null,

8 < value < 640)

0x0: positive

0x1: negative

(Absolute value, |a| < p) Curve coefficient |a|

Curve modulus value

Scalar multiplier k p

Point P coordinate x

Point P coordinate y

Montgomery parameter

mod p

(Odd integer prime,

0 < p < 2 640 )

(0 ≤ k < 2

640

)

(x <

(y < p p

)

(mandatory)

Result: k x P coordinate x (result < p )

Result: k x P coordinate y (result < p )

RAM@0x400

RAM@0x404

RAM@0x408

RAM@0x40C

RAM@0x460

RAM@0x508

RAM@0x55C

RAM@0x5B0

RAM@0x4B4

RAM@0x55C

RAM@0x5B0

Size

6 bits

32 bits

EOS

When performing this operation following special cases should be noted:

 For k = 0, this function returns a point at infinity, that is (0, 0) if curve parameter b is nonzero and (0, 1) otherwise. For k different from 0 it might happen that a point at infinity is returned. When the application detects this behavior a new computation should be carried out.

 For k < 0 (i.e. a negative scalar multiplication is required) multiplier absolute value k = |-k| should be provided to the PKA. After the computation completion, the formula

-P = (x, -y) can be used to compute the y coordinate of the effective final result (the x coordinate remains the same).

ECDSA signing operation (outlined in

Section 18.3.5

) is summarized in Table 110 (input

parameters) and in

Table 111 (output parameters).

The application should check if the output error is equal to zero, if it is different from zero a new k should be generated and the ECDSA sign operation should be repeated.

RM0471 Rev 5 521/1202

531

Public key accelerator (PKA) RM0471

Parameters with direction

Table 110. ECDSA sign - Inputs

Value (Note) Storage

MODE

Curve prime order n length

0x24

(in bits, not null)

Curve modulus p length (in bits, 8 < value < 640)

Curve coefficient a sign

0x0: positive

0x1: negative

Curve coefficient |a|

Curve modulus value p

(Absolute value, |a| < p)

(Odd integer prime,

0 < p < 2

640

)

(0 ≤ k < 2 640 ) Integer k (1)

Curve base point G coordinate x

Curve base point G coordinate y

Hash of message z

Private key d

Curve prime order n

(x <

(y < p p )

)

(z < 2M)

(positive integer)

(integer prime)

PKA_CR

RAM@0x400

RAM@0x404

RAM@0x408

RAM@0x40C

RAM@0x460

RAM@0x508

RAM@0x55C

RAM@0x5B0

RAM@0xDE8

RAM@0xE3C

RAM@0xE94

1. This integer is usually a cryptographically secure random number, but in some cases k could be deterministically generated.

Size

6 bits

32 bits

EOS

Parameters with direction

Table 111. ECDSA sign - Outputs

Value (Note)

OUT

Signature part r

Signature part s

ERROR Result of signature

(0 < r < n)

(0 < s < n)

– 0x0: no error

– 0x1: signature part r is equal to 0

– 0x2: signature part s is equal to 0

Storage

RAM@0x700

RAM@0x754

RAM@0xEE8

Size

EOS

32 bits

Note: If error output is different from zero the content of the PKA memory should be cleared to avoid leaking information about the private key.

Extended ECDSA support

PKA also supports Extended ECDSA signature, for which the inputs and the outputs have

the same ECDSA signature ( Table 110

and

Table 111 , respectively), with the addition of the

coordinates of the point kG. This extra output is defined in

Table 112

522/1202 RM0471 Rev 5

RM0471 Public key accelerator (PKA)

OUT

Table 112. Extended ECDSA sign (extra outputs)

Parameters with direction Value (Note) Storage

Curve point kG coordinate x

Curve point kG coordinate y

(0 ≤ x

< p)

(0 ≤ y

< p)

RAM@0x103C

RAM@0x1090

Size

EOS

ECDSA verification operation (outlined in

Section 18.3.5

) is summarized in

Table 113

(input

parameters) and Table 114

(output parameters).

The epplication should check if the output error is equal to zero, if it is different from zero, the signature is not verified.

Table 113. ECDSA verification (inputs)

Parameters with direction Value (Note) Storage

0x26 PKA_CR MODE

Curve prime order n length

(In bits, not null) RAM@0x404

Curve modulus p length

Curve coefficient a sign

Curve coefficient |a|

Curve modulus value p

(In bits, not null,

8 < value < 640)

0x0: positive

0x1: negative

(Absolute value, |a| < p)

(Odd integer prime,

0 < p < 2

640

)

RAM@0x4B4

RAM@0x45C

RAM@0x460

RAM@0x4B8

Curve base point G coordinate x

Curve base point G coordinate y

Public-key curve point Q coordinate x

Public-key curve point Q coordinate y

Signature part r

Signature part s

Hash of message z

Curve prime order n

(x < p )

(y < p )

< p )

(0 < r < n)

(0 < s < n)

(z < 2 M )

(integer prime)

RAM@0x5E8

RAM@0x63C

RAM@0xF40

RAM@0xF94

RAM@0x1098

RAM@0xA44

RAM@0xFE8

RAM@0xD5C

Size

6 bits

32 bits

EOS

Table 114. ECDSA verification (outputs)

Parameters with direction Value (Note) Storage

OUT Result: ECDSA verify

0x0: valid signature

Not 0x0: invalid signature

RAM@0x5B0

Size

32 bits

RM0471 Rev 5 523/1202

531

Public key accelerator (PKA) RM0471

18.5 Example of configurations and processing times

18.5.1 Supported elliptic curves

Note:

The PKA supports all non-singular elliptic curves defined over prime fields. Those curvescan be described with a short Weierstrass equation y

= x

+ a x + b (mod p ).

Binary curves, Edwards curves and Curve25519 are not supported by the PKA.

The maximum supported operand size for ECC operations is 640 bits.

When publishing the ECC domain parameters of those elliptic curves, standard bodies define the following parameters:

 the prime integer p , used as the modulus for all point arithmetic in the finite field GF( p )

 the (usually prime) integer n , the order of the group generated by G, defined below

 the base point of the curve G, defined by its coordinates ( Gx , Gy )

 the integers a and b , coefficients of the short Weierstrass equation.

For the last bullet, when standard bodies define a as negative, PKA supports two representations:

a defined as p -| a | in the finite field GF( p ), for example p-3 :

Curve coefficient p = 0xFFFFFFFE FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF

00000000 FFFFFFFF FFFFFFF F

Curve coefficient a sign= 0x0 (positive)

Curve coefficient a = 0xFFFFFFFE FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF

00000000 FFFFFFFF FFFFFFF C

2. a defined as negative , for example -3 :

Curve coefficient p = 0xFFFFFFFE FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF

00000000 FFFFFFFF FFFFFFFF

Curve coefficient a sign= 0x 1 (negative)

Curve coefficient a = 0x00000000 00000000 00000000 00000000 00000000 00000000

00000000 0000000 3

Table 115

summarizes the family of curves supported by PKA for ECC operations.

Table 115. Family of supported curves for ECC operations

Standard Reference

P-192

P-224

P-256

P-384

P-521

Curve name

NIST Digital Signature Standard (DSS) , NIST FIPS 186-4

524/1202 RM0471 Rev 5

RM0471 Public key accelerator (PKA)

Table 115. Family of supported curves for ECC operations (continued)

Curve name Standard Reference brainpoolP224r1, brainpoolP224t1 brainpoolP256r1, brainpoolP256t1 brainpoolP320r1, brainpoolP320t1 brainpoolP384r1, brainpoolP384t1 brainpoolP512r1, brainpoolP512t1 secp192k1, secp192r1 secp224k1, secp224r1 secp256k1, secp256r1 secp384r1 secp521r1

IETF

SEC

– Brainpool Elliptic Curves , IETF RFC 5639

– Brainpool Elliptic Curves for the Internet Key

Exchange (IKE) Group Description Registry , IETF

RFC 6932 https://tools.ietf.org

Standards for Efficient Cryptography SEC 2 curves https://www.secg.org

Recommended curve parameters for public key cryptographic algorithm SM2

OSCCA

– Public key cryptographic algorithm SM2 based on elliptic curves ,

Organization of State Commercial Administration of China OSCCA SM2,

December 2010

– Digital signatures - Part 3 Discrete logarithm based mechanisms , ISO/IEC

14888-3, November 2018

RM0471 Rev 5 525/1202

531

Public key accelerator (PKA) RM0471

526/1202

The following tables summarize the PKA computation times, expressed in clock cycles.

Exponent length

(in bits)

Table 116. Modular exponentiation computation times

Modulus length (in bits)

Mode

1024 2048

+ 1

1024

2048

3072

Normal

Fast

Normal

Fast

Normal

Fast

Normal

Fast

CRT

(1)

Normal

Fast

CRT

(1)

Normal

Fast

CRT

(1)

304000

46000

326000

68000

416000

158000

11664000

11280000

3546000

1. CRT stands for chinese remainder theorem optimization (MODE bitfield = 0x07).

814000

164000

896000

246000

1222000

572000

83834000

82046000

23468000

3072

1728000

356000

1910000

534000

2616000

1244000

274954000

273522000

73378000

Table 117. ECC scalar multiplication computation times (1)

Modulus length (in bits)

Mode

160 192 256 320 384 512 521

Normal

Fast

1634000

1630000

2500000

2494000

4924000

4916000

8508000

8494000

13642000

13614000

1. These times depend on the number of “1”s included in the scalar parameter.

28890000

28842000

33160000

33158000

Table 118. ECDSA signature average computation times (1) (2)

Modulus length (in bits)

160 192 256 320 384 512 521

1760000 2664000 5249000 9016000 14596000 30618000 35540000

1. These values are average execution times of random moduli of given length, as they depend upon the length and the value of the modulus.

2. The execution time for the moduli that define the finite field of NIST elliptic curves is shorter than that needed for the moduli used for Brainpool elliptic curves or for random moduli of the same size.

RM0471 Rev 5

RM0471 Public key accelerator (PKA)

160

3500000

Table 119. ECDSA verification average computation times

Modulus length (in bits)

192

5350000

256

10498000

320

18126000

384

29118000

512

61346000

521

71588000

Table 120. Point on elliptic curve Fp check average computation times

Modulus length (in bits)

160

10800

192

14200

256

20400

320

31000

384

49600

512

82400

Table 121. Montgomery parameters average computation times (1)

Modulus length (in bits)

160 192 256 320 384 512 521 1024 2048 3072

4518 7846 11848 14902 21682 35012 64000 119536 466146 1104642

1. The computation times depend upon the length and the value of the modulus, hence these values are average execution times of random moduli of given length.

Interrupt acronym

There are three individual maskable interrupt sources generated by the public key accelerator, signaling the following events:

access to unmapped address (ADDRERRF), see

Section 18.3.7

2. PKA RAM access while PKA operation is in progress (RAMERRF), see

Section 18.3.7

3. PKA end of operation (PROCENDF)

The three interrupt sources are connected to the same global interrupt request signal pka_it.

The user can enable or disable above interrupt sources individually by changing the mask

bits in the PKA control register (PKA_CR) . Setting the appropriate mask bit to 1 enables the

interrupt. The status of the individual interrupt events can be read from the PKA status register (PKA_SR), and it is cleared in PKA_CLRFR register.

Table 122

gives a summary of the available features.

Table 122. PKA interrupt requests

Interrupt event Event flag Enable control bit Interrupt clear method

PKA

Access to unmapped address error

PKA RAM access error

PKA end of operation

ADDRERRF

RAMERRF

PROCENDF

ADDRERRIE

RAMERRIE

PROCENDIE

Set ADDRERRFC bit

Set RAMERRFC bit

Set PROCENDFC bit

RM0471 Rev 5 527/1202

531

Public key accelerator (PKA) RM0471

18.7.1 PKA control register (PKA_CR)

Address offset: 0x00

Reset value: 0x0000 0000

Res.

28 27

Res.

11 10

MODE[5:0] rw rw

Res.

ADDR

ERRIE rw

RAM

ERRIE rw

Res.

PROC

ENDIE rw

START rw

Res.

EN rw rw rw rw rw

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 ADDRERRIE : Address error interrupt enable

0: No interrupt is generated when ADDRERRF flag is set in PKA_SR.

1: An interrupt is generated when ADDRERRF flag is set in PKA_SR.

Bit 19 RAMERRIE : RAM error interrupt enable

0: No interrupt is generated when RAMERRF flag is set in PKA_SR.

1: An interrupt is generated when RAMERRF flag is set in PKA_SR.

Bit 18 Reserved, must be kept at reset value.

Bit 17 PROCENDIE : End of operation interrupt enable

0: No interrupt is generated when PROCENDF flag is set in PKA_SR.

1: An interrupt is generated when PROCENDF flag is set in PKA_SR.

Bits 16:14 Reserved, must be kept at reset value.

Bits 13:8 MODE[5:0] : PKA operation code

000000: Montgomery parameter computation then modular exponentiation

000001: Montgomery parameter computation only

000010: Modular exponentiation only (Montgomery parameter must be loaded first)

100000: Montgomery parameter computation then ECC scalar multiplication

100010: ECC scalar multiplication only (Montgomery parameter must be loaded first)

100100: ECDSA sign

100110: ECDSA verification

101000: Point on elliptic curve Fp check

000111: RSA CRT exponentiation

001000: Modular inversion

001001: Arithmetic addition

001010: Arithmetic subtraction

001011: Arithmetic multiplication

001100: Arithmetic comparison

001101: Modular reduction

001110: Modular addition

001111: Modular subtraction

010000: Montgomery multiplication

Others: Reserved

528/1202 RM0471 Rev 5

RM0471 Public key accelerator (PKA)

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 START : start the operation

Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0.

Note: START is ignored if PKA is busy.

Bit 0 EN : PKA enable.

0: Disable PKA

1: Enable PKA

Note: When EN=0 PKA RAM can still be accessed by the application.

Res.

Address offset: 0x04

Reset value: 0x0000 0000

30 29 28 27

Res.

14 13 12 11

Res.

ADDR

ERRF r

Res.

RAM

ERRF r

Res.

PROC

ENDF r

Res.

BUSY r

Res.

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 ADDRERRF : Address error flag

0: No Address error

1: Address access is out of range (unmapped address)

This bit is cleared using ADDRERRFC bit in PKA_CLRFR.

Bit 19 RAMERRF : PKA RAM error flag

0: No PKA RAM access error

1: An AHB access to the PKA RAM occurred while the PKA core was computing and using its internal RAM (AHB PKA_RAM access are not allowed while PKA operation is in progress).

This bit is cleared using RAMERRFC bit in PKA_CLRFR.

Bit 18 Reserved, must be kept at reset value.

Bit 17 PROCENDF : PKA End of Operation flag

0: Operation in progress

1: PKA operation is completed. This flag is set when the BUSY bit is deasserted.

Bit 16 BUSY : PKA operation is in progress

This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started.

0: No operation is in progress (default)

1: An operation is in progress

If PKA is started with a wrong opcode the peripheral is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0).

Bits 15:0 Reserved, must be kept at reset value.

RM0471 Rev 5 529/1202

531

Public key accelerator (PKA) RM0471

Address offset: 0x08

Reset value: 0x0000 0000

Res.

30 29 28 27

Res.

14 13 12 11

Res.

ADDR

ERRFC w

RAM

ERRFC w

Res.

PROC

ENDFC w

Res.

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 ADDRERRFC : Clear Address error flag

0: No action

1: Clear the ADDRERRF flag in PKA_SR

Bit 19 RAMERRFC : Clear PKA RAM error flag

0: No action

1: Clear the RAMERRF flag in PKA_SR

Bit 18 Reserved, must be kept at reset value.

Bit 17 PROCENDFC : Clear PKA End of Operation flag

0: No action

1: Clear the PROCENDF flag in PKA_SR

Bits 16:0 Reserved, must be kept at reset value.

Note: Reading PKA_CLRFR returns all 0s.

The PKA RAM is mapped at the offset address of 0x0400 compared to the PKA base address. Only 32-bit word single accesses are supported, through PKA.AHB interface.

RAM size is 3576 bytes (max word offset: 0x11F4).

530/1202 RM0471 Rev 5

RM0471 Public key accelerator (PKA)

18.7.5 PKA register map

Table 123. PKA register map and reset values

Offset

Register name

MODE[5:0] PKA_CR

0x000

0x004

Reset value

PKA_SR

Reset value

0 0 0

0 0 0 0

0 0 0 0 0 0 0 0

0x008

PKA_CLRFR

Reset value 0 0 0

Refer to Section 2.2 on page 55 for the register boundary addresses.

RM0471 Rev 5 531/1202

531

Advanced-control timer (TIM1)

19 Advanced-control timer (TIM1)

RM0471

In this section, “TIMx” should be understood as “TIM1” since there is only one instance of this type of timer for the products to which this reference manual applies.

The advanced-control timer (TIM1) consists of a 16-bit auto-reload counter driven by a programmable prescaler.

It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion).

Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers.

The advanced-control (TIM1) and general-purpose (TIMy) timers are completely independent, and do not share any resources. They can be synchronized together as described in

Section 19.3.26: Timer synchronization .

532/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

19.2 TIM1 main features

TIM1 timer features include:

 16-bit up, down, up/down auto-reload counter.

 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency either by any factor between 1 and 65536.

 Up to 6 independent channels for:

– Input Capture (but channels 5 and 6)

– Output Compare

– PWM generation (Edge and Center-aligned Mode)

– One-pulse mode output

 Complementary outputs with programmable dead-time

 Synchronization circuit to control the timer with external signals and to interconnect several timers together.

 Repetition counter to update the timer registers only after a given number of cycles of the counter.

 2 break inputs to put the timer’s output signals in a safe user selectable configuration.

 Interrupt/DMA generation on the following events:

– Update: counter overflow/underflow, counter initialization (by software or internal/external trigger)

– Trigger event (counter start, stop, initialization or count by internal/external trigger)

– Input capture

– Output compare

 Supports incremental (quadrature) encoder and Hall-sensor circuitry for positioning purposes

 Trigger input for external clock or cycle-by-cycle current management

RM0471 Rev 5 533/1202

631

Advanced-control timer (TIM1)

TIMx_ETR

On-chip ETR sources

Figure 115. Advanced-control timer block diagram

Internal clock (CK_INT) from RCC

ETRF

Trigger controller

ETR

ETRP

Polarity selection & edgedetector & prescaler

Input filter

TRGO to other timers to peripherals

ITR[0..15]

ITR

TRC

TRG

TRGI

Slave controller mode

Reset, enable, up/down, count

TI1F_ED

RM0471

TI1FP1

TI2FP2

Encoder

Interface

TIMx_CH1

TI1[0]

TI1[1..15]

TIMx_CH2

TI2[0]

TI2[1..15]

TIMx_CH3

TI3[0]

TI3[1..15]

TIMx_CH4

TI4[0]

TI4[1..15]

XOR

REP register

Auto-reload register

Stop, clear or up/down

Repetition counter

TI1

Input filter & edge detector

TI1FP1

TI1FP2

TRC

CK_PSC PSC prescaler

CK_CNT

CC1I

IC1

Prescaler

IC1PS

TI2

Input

TI2FP1 filter & edge detector

TI2FP2

TRC

CC2I

IC2

Prescaler

IC2PS

CC3I

TI3

Input filter & edge detector

TI3FP3

TI3FP4

TRC

TI4

Input filter &

TI4FP3 edge detector

TI4FP4

TRC

IC3

IC4

Prescaler

IC3PS

CC4I

IC4PS

+/CNT counter

CC1I

DTG registers

Capture/Compare 1 register

OC1REF

DTG

Output control

OC1

OC1N

CC2I

Capture/Compare 2 register

OC2REF

DTG

Output control

OC2

OC2N

CC3I

Capture/Compare 3 register

OC3REF

DTG

CC4I

Capture/Compare 4 register

OC4REF

Output control

OC3

OC3N

OC4

TIMx_CH1

TIMx_CH1N

TIMx_CH2

TIMx_CH2N

TIMx_CH3

TIMx_CH3N

TIMx_CH4

Capture/Compare 5 register

OC5REF

Output

OC5 control

Output

OC6 control

Internal sources

SBIF

Capture/Compare 6 register

OC6REF

TIMx_BKIN

Break and Break2 circuitry (1)

BIF

ETRF

BRK request

B2IF

BRK2 request

TIMx_BKIN2

Notes:

Reg

Preload registers transferred to active registers on U event according to control bit

Event

Interrupt & DMA output

MSv40115V4

1. The internal break event source can be:

- A clock failure event generated by CSS. For further information on the CSS, refer to Section 7.2.11:

Clock security system (CSS) on HSE

- A PVD output

- SRAM parity error signal

- CPU1 Cortex ® -M4 LOCKUP (Hardfault) output.

534/1202 RM0471 Rev 5

RM0471

19.3 TIM1 functional description

Advanced-control timer (TIM1)

The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.

The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

 Counter register (TIMx_CNT)

 Prescaler register (TIMx_PSC)

 Auto-reload register (TIMx_ARR)

 Repetition counter register (TIMx_RCR)

The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the

TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detailed for each configuration.

The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling).

Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register.

Prescaler description

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).

It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.

Figure 116 and Figure 117

give some examples of the counter behavior when the prescaler ratio is changed on the fly:

RM0471 Rev 5 535/1202

631

Advanced-control timer (TIM1) RM0471

Figure 116. Counter timing diagram with prescaler division change from 1 to 2

CK_PSC

CEN

Timerclock = CK_CNT

Counter register

Update event (UEV)

Prescaler control register

F7 F8 F9 FA FB FC 00 01 02 03

0 1

Write a new value in TIMx_PSC

Prescaler buffer

0 1

Prescaler counter

0 0 1 0 1 0 1 0 1

MS31076V2

Figure 117. Counter timing diagram with prescaler division change from 1 to 4

CK_PSC

CEN

Timerclock = CK_CNT

Counter register

Update event (UEV)

Prescaler control register

F8 F9

Write a new value in TIMx_PSC

Prescaler buffer

Prescaler counter

FA FB FC 00

0 1 2 3 0 1 2 3

MS31077V2

536/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Upcounting mode

In upcounting mode, the counter counts from 0 to the auto-reload value (content of the

TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register

(TIMx_RCR) + 1. Else the update event is generated at each counter overflow.

Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event.

The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0.

However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in

TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

 The repetition counter is reloaded with the content of TIMx_RCR register,

 The auto-reload shadow register is updated with the preload value (TIMx_ARR),

 The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.

RM0471 Rev 5 537/1202

631

Advanced-control timer (TIM1)

Figure 118. Counter timing diagram, internal clock divided by 1

RM0471

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Figure 119. Counter timing diagram, internal clock divided by 2

MS31078V2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

0034 0035 0036 0000 0001 0002 0003

MS31079V2

538/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Figure 120. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0035 0036 0000 0001

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Figure 121. Counter timing diagram, internal clock divided by N

MS31080V2

CK_PSC

Timerclock = CK_CNT

Counter register 1F 20 00

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31081V2

RM0471 Rev 5 539/1202

631

Advanced-control timer (TIM1) RM0471

Figure 122. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register

Counter overflow

32 33 34 35 36 00 01 02 03 04 05 06 07

Update event (UEV)

Update interrupt flag (UIF)

540/1202

Auto-reload preload register FF 36

Write a new value in TIMx_ARR

MS31082V3

Figure 123. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload register

Auto-reload shadow register

Write a new value in TIMx_ARR

MS31083V2

RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Downcounting mode

In downcounting mode, the counter counts from the auto-reload value (content of the

TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event.

If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register

(TIMx_RCR) + 1. Else the update event is generated at each counter underflow.

Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event.

The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0.

However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change).

In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the

UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or

DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

 The repetition counter is reloaded with the content of TIMx_RCR register.

 The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).

 The auto-reload active register is updated with the preload value (content of the

TIMx_ARR register). Note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one.

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.

RM0471 Rev 5 541/1202

631

Advanced-control timer (TIM1)

Figure 124. Counter timing diagram, internal clock divided by 1

RM0471

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F

Counter underflow

(cnt_udf)

Update event (UEV)

Update interrupt flag

(UIF)

MS31184V1

Figure 125. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

0002 0001 0000 0036 0035 0034 0033

MS31185V1

542/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Figure 126. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0001 0000 0000 0001

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

Figure 127. Counter timing diagram, internal clock divided by N

MS31186V1

CK_PSC

Timerclock = CK_CNT

Counter register 20 1F 00 36

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31187V1

RM0471 Rev 5 543/1202

631

Advanced-control timer (TIM1) RM0471

Figure 128. Counter timing diagram, update event when repetition counter is not used

CK_PSC

CEN

Timerclock = CK_CNT

Counter register

Counter underflow

05 04 03 02 01 00 36 35 34 33 32 31 30 2F

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload register

FF 36

Write a new value in TIMx_ARR

MS31188V1

Center-aligned mode (up/down counting)

In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the

TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting from 0.

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to

'00'. The Output compare interrupt flag of channels configured in output is set when: the counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3,

CMS = "11").

In this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated by hardware and gives the current direction of the counter.

The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from

0, as well as the counter of the prescaler.

The UEV update event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0.

However, the counter continues counting up and down, based on the current auto-reload value.

In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the

UG bit generates an UEV update event but without setting the UIF flag (thus no interrupt or

544/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

 The repetition counter is reloaded with the content of TIMx_RCR register

 The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register)

 The auto-reload active register is updated with the preload value (content of the

TIMx_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected one (the counter is loaded with the new value).

The following figures show some examples of the counter behavior for different clock frequencies.

Figure 129. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6

CK_PSC

CEN

Timerclock = CK_CNT

Counter register

Counter underflow

Counter overflow

04 03 02 01 00 01 02 03 04 05 06 05 04 03

Update event (UEV)

Update interrupt flag (UIF)

Here, center-aligned mode 1 is used (for more details refer to

Section 19.4: TIM1 registers ).

MS31189V3

RM0471 Rev 5 545/1202

631

Advanced-control timer (TIM1)

Figure 130. Counter timing diagram, internal clock divided by 2

RM0471

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0003 0002 0001 0000 0001 0002 0003

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31190V1

Figure 131. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Note: Here, center_aligned mode 2 or 3 is updated with an UIF on overflow

0036 0035

MS31191V1

546/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Figure 132. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 20 1F 01 00

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31192V1

Figure 133. Counter timing diagram, update event with ARPE=1 (counter underflow)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register

06 05 04 03 02 01 00

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload register

Write a new value in TIMx_ARR

Auto-reload active register

01 02 03 04 05 06 07

MS31193V1

RM0471 Rev 5 547/1202

631

Advanced-control timer (TIM1) RM0471

Figure 134. Counter timing diagram, Update event with ARPE=1 (counter overflow)

CK_PSC

CEN

Timer clock = CK_CNT

Counter register F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload register

Write a new value in TIMx_ARR

Auto-reload active register

MS31194V1

Section 19.3.1: Time-base unit

describes how the update event (UEV) is generated with respect to the counter overflows/underflows. It is actually generated only when the repetition counter has reached zero. This can be useful when generating PWM signals.

This means that data are transferred from the preload registers to the shadow registers

(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx capture/compare registers in compare mode) every N+1 counter overflows or underflows, where N is the value in the TIMx_RCR repetition counter register.

The repetition counter is decremented:

 At each counter overflow in upcounting mode,

 At each counter underflow in downcounting mode,

 At each counter overflow and at each counter underflow in center-aligned mode.

Although this limits the maximum number of repetition to 32768 PWM cycles, it makes it possible to update the duty cycle twice per PWM period. When refreshing compare registers only once per PWM period in center-aligned mode, maximum resolution is

2xT ck

, due to the symmetry of the pattern.

The repetition counter is an auto-reload type; the repetition rate is maintained as defined by the TIMx_RCR register value (refer to

Figure 135

). When the update event is generated by software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave mode controller, it occurs immediately whatever the value of the repetition counter is and the repetition counter is reloaded with the content of the TIMx_RCR register.

548/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

In Center aligned mode, for odd values of RCR, the update event occurs either on the overflow or on the underflow depending on when the RCR register was written and when the counter was launched: if the RCR was written before launching the counter, the UEV occurs on the underflow. If the RCR was written after launching the counter, the UEV occurs on the overflow.

For example, for RCR = 3, the UEV is generated each 4th overflow or underflow event depending on when the RCR was written.

Figure 135. Update rate examples depending on mode and TIMx_RCR register settings

Counter

TIMx_CNT

Counter-aligned mode

Upcounting

Edge-aligned mode

Downcounting

TIMx_RCR = 0

UEV

TIMx_RCR = 1

UEV

TIMx_RCR = 2

UEV

TIMx_RCR = 3

UEV

TIMx_RCR = 3 and re-synchronization

UEV

(by SW) (by SW) (by SW)

UEV

Update event : Preload registers transferred to active registers and update interrupt generated

Update Event if the repetition counter underflow occurs when the counter is equal to the auto-reload value.

MSv31195V1

RM0471 Rev 5 549/1202

631

Advanced-control timer (TIM1) RM0471

The timer features an external trigger input ETR. It can be used as:



external clock (external clock mode 2, see Section 19.3.5

)



trigger for the slave mode (see Section 19.3.26

)

 PWM reset input for cycle-by-cycle current regulation (see

Section 19.3.7

)

Figure 136 below describes the ETR input conditioning. The input polarity is defined with the

ETP bit in TIMxSMCR register. The trigger can be prescaled with the divider programmed by the ETPS[1:0] bitfield and digitally filtered with the ETF[3:0] bitfield.

Figure 136. External trigger input block

ETR input

ETR

Divider

/1, /2, /4, /8

ETRP f

DTS

Filter downcounter

To the Output mode controller

To the CK_PSC circuitry

To the Slave mode controller

ETP

TIMx_SMCR

ETPS[1:0]

TIMx_SMCR

ETF[3:0]

TIMx_SMCR

MS34403V2

The ETR input comes from multiple sources: input pins (default configuration) and analog watchdogs. The selection is done with the ETRSEL[3:0] and the TIM1_OR1[1:0] bitfields.

Figure 137. TIM1 ETR input circuitry

ETR inputs from

AF controller

TIM1_OR1[1:0]

ADC_AWD1

ADC_AWD2

ADC_AWD3

TIM1_AF1[17:14]

ETR legacy mode

ETR input

MSv63010V2

550/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

The counter clock can be provided by the following clock sources:

 Internal clock (CK_INT)

 External clock mode1: external input pin

 External clock mode2: external trigger input ETR

 Encoder mode

Internal clock source (CK_INT)

If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.

Figure 138 shows the behavior of the control circuit and the upcounter in normal mode,

without prescaler.

Figure 138. Control circuit in normal mode, internal clock divided by 1

Internal clock

CEN=CNT_EN

Counter initialization (internal)

Counter clock = CK_CNT = CK_PSC

Counter register 31 3 2 33 34 35 36 00 01 02 03 04 05 06 07

MSv31085V3

External clock source mode 1

This mode is selected when SMS=111 in the TIMx_SMCR register.

The counter can count at each rising or falling edge on a selected input.

RM0471 Rev 5 551/1202

631

Advanced-control timer (TIM1) RM0471

Figure 139. TI2 external clock connection example

TIMx_SMCR

TS[4:0]

TIMx_CH2

TI2[0]

TI2[1..15]

TI2

Filter

ICF[3:0]

TIMx_CCMR1

Edge detector

TI2F_Rising

TI2F_Falling

CC2P

TIMx_CCER

ITRx

TI1_ED

TI1FP1

TI2FP2

ETRF

000xx

00100

00101

00110

00111

(1) or

TI2F or

TI1F or

TRGI

ETRF

CK_INT

(internal clock)

Encoder mode

External clock mode 1

External clock mode 2

Internal clock mode

ECE SMS[2:0]

TIMx_SMCR

CK_PSC

MSv40117V1

1. Codes ranging from 01000 to 11111 are reserved

For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure:

Select the proper TI2x source (internal or external) with the TI2SEL[3:0] bits in the

TIMx_TISEL register.

2. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register.

3. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000).

4. Select rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER register.

5. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register.

6. Select TI2 as the trigger input source by writing TS=00110 in the TIMx_SMCR register.

7. Enable the counter by writing CEN=1 in the TIMx_CR1 register.

Note: The capture prescaler is not used for triggering, so the user does not need to configure it.

When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.

The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input.

552/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Figure 140. Control circuit in external clock mode 1

TI2

CNT_EN

Counter clock = CK_CNT = CK_PSC

Counter register

TIF

34 35 36

Write TIF=0

MS31087V2

External clock source mode 2

This mode is selected by writing ECE=1 in the TIMx_SMCR register.

The counter can count at each rising or falling edge on the external trigger input ETR.

The

Figure 141 gives an overview of the external trigger input block.

Figure 141. External trigger input block

TIM1_AF1[17:14] and

TIM1_OR1[1:0] or

TI2F or

TI1F or Encoder mode

ETR pin

(1)

ETR

Divider

/1, /2, /4, /8 f

ETRP

DTS

Filter downcounter

TRGI

ETRF

External clock mode 1

External clock mode 2

Internal clock mode

CK_PSC

ETP ETPS[1:0]

TIMx_SMCR TIMx_SMCR

ETF[3:0]

TIMx_SMCR

CK_INT

(internal clock)

ECE SMS[2:0]

TIMx_SMCR

MSv47461V1

1. Refer to Figure 137: TIM1 ETR input circuitry .

For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure:

RM0471 Rev 5 553/1202

631

Advanced-control timer (TIM1) RM0471

As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.

2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register

3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register

4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.

5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.

The counter counts once each 2 ETR rising edges.

The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal. As a consequence, the maximum frequency which can be correctly captured by the counter is at most ¼ of TIMxCLK frequency. When the ETRP signal is faster, the user should apply a division of the external signal by proper

ETPS prescaler setting.

Figure 142. Control circuit in external clock mode 2 f

CK_INT

CNT_EN

ETR

ETRP

ETRF

Counter clock =

CK_CNT =CK_PSC

Counter register 34 35 36

MSv33111V3

554/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

TIMx_CH1

Each Capture/Compare channel is built around a capture/compare register (including a shadow register), an input stage for capture (with digital filter, multiplexing, and prescaler, except for channels 5 and 6) and an output stage (with comparator and output control).

Figure 143

to Figure 146

give an overview of one Capture/Compare channel.

The input stage samples the corresponding TIx input to generate a filtered signal TIxF.

Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS).

Figure 143. Capture/compare channel (example: channel 1 input stage)

TIMx_TISEL[3:0]

TI1F_ED

TI1[0]

To the slave mode controller

TI1[1..15] f

DTS

Filter downcounter

TI1F Edge detector

TI1F_Rising

TI1F_Falling

0 TI1FP1

TI2FP1

IC1

Divider

/1, /2, /4, /8

IC1PS

ICF[3:0]

TIMx_CCMR1

CC1P/CC1NP

TIMx_CCER

TI2F_Rising

(from channel 2)

TI2F_Falling

(from channel 2)

TRC

(from slave mode controller)

CC1S[1:0] ICPS[1:0]

TIMx_CCMR1

CC1E

TIMx_CCER

MSv40120V2

The output stage generates an intermediate waveform which is then used for reference:

OCxRef (active high). The polarity acts at the end of the chain.

Figure 144. Capture/compare channel 1 main circuit

APB Bus

CC1S[1]

CC1S[0]

IC1PS

CC1E

Input mode

CC1G

TIMx_EGR

MCU-peripheral interface

16/32-bit

Output mode

Capture/compare preload register

CC1S[1]

CC1S[0]

Capture

Counter

Compare transfer compare shadow register

Comparator

CNT>CCR1

CNT=CCR1

OC1PE

UEV

(from time base unit)

TIMx_CCMR1

MSv63030V1

RM0471 Rev 5 555/1202

631

Advanced-control timer (TIM1) RM0471

Figure 145. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3)

TIMx_SMCR

OCREF_CLR

OCCS

ETRF

1 ocref_clr_int OC1REF

CNT>CCR1

CNT=CCR1

Output mode controller

Output selector

OCxREF

OC5REF

(1)

To the master mode controller

OC1REFC

OC1_DT

Dead-time generator

OC1N_DT

‘0’ x0

‘0’

CC1P

TIM1_CCER

Output enable circuit

OC1

Output enable circuit

OC1N

CC1NE CC1E TIM1_CCER

OC1CE OC1M[3:0]

TIM1_CCMR1

DTG[7:0]

TIM1_BDTR

CC1NE CC1E

TIM1_CCER

CC1NP

TIM1_CCER

MOE OSSI OSSR

TIM1_BDTR

OIS1 OIS1N

TIM1_CR2

MS31199V2

1. OCxREF, where x is the rank of the complementary channel

Figure 146. Output stage of capture/compare channel (channel 4)

TIMx_SMCR

OCCS

OCREF_CLR

ETRF

OC4REFC ocref_clr_int

CNT > CCR4

CNT = CCR4

Output mode controller

OC4REF

Output selector

OC3REF

‘0’

To the master mode controller

CC4E

TIM1_CCER

CC4P

TIM1_CCER

Output enable circuit

OC4

CC4E TIM1_CCER

OC4CE OC4M[3:0]

TIM1_CCMR2

MOE OSSI TIM1_BDTR

OIS4 TIM1_CR2

MS33100V2

556/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Figure 147. Output stage of capture/compare channel (channel 5, idem ch. 6)

TIMx_SMCR

OCCS

OCREF_CLR

To the master mode controller

ETRF 1 ocref_clr_int

CNT > CCR5

CNT = CCR5

Output mode controller

‘0’

OC5REF

Output enable circuit

OC5

(1)

CC5E

TIM1_CCER

CC5P

TIM1_CCER CC5E TIM1_CCER

OC5CE OC5M[3:0]

TIM1_CCMR2

MOE OSSI TIM1_BDTR

OIS5 TIM1_CR2

MS33101V2

1. Not available externally.

The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register.

In capture mode, captures are actually done in the shadow register, which is copied into the preload register.

In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter.

In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to ‘0’ or by reading the captured data stored in the

TIMx_CCRx register. CCxOF is cleared when written with ‘0’.

The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure:

Select the proper TI1x source (internal or external) with the TI1SEL[3:0] bits in the

TIMx_TISEL register.

2. Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input and the TIMx_CCR1 register becomes read-only.

3. Program the appropriate input filter duration in relation with the signal connected to the timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s imagine that, when toggling, the input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been

RM0471 Rev 5 557/1202

631

Advanced-control timer (TIM1) RM0471

Note: detected (sampled at f

DTS

TIMx_CCMR1 register.

frequency). Then write IC1F bits to 0011 in the

4. Select the edge of the active transition on the TI1 channel by writing CC1P and CC1NP bits to 0 in the TIMx_CCER register (rising edge in this case).

5. Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the

TIMx_CCMR1 register).

6. Enable capture from the counter into the capture register by setting the CC1E bit in the

TIMx_CCER register.

7. If needed, enable the related interrupt request by setting the CC1IE bit in the

TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the

TIMx_DIER register.

When an input capture occurs:

 The TIMx_CCR1 register gets the value of the counter on the active transition.

 CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared.

 An interrupt is generated depending on the CC1IE bit.

 A DMA request is generated depending on the CC1DE bit.

In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data.

IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register.

19.3.8 PWM input mode

This mode is a particular case of input capture mode. The procedure is the same except:

 Two ICx signals are mapped on the same TIx input.

 These 2 ICx signals are active on edges with opposite polarity.

 One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode.

For example, the user can measure the period (in TIMx_CCR1 register) and the duty cycle

(in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure

(depending on CK_INT frequency and prescaler value):

558/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Select the proper TI1x source (internal or external) with the TI1SEL[3:0] bits in the

TIMx_TISEL register.

2. Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected).

3. Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P and CC1NP bits to ‘0’ (active on rising edge).

4. Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1 selected).

5. Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P and CC2NP bits to CC2P/CC2NP=’10’ (active on falling edge).

6. Select the valid trigger input: write the TS bits to 00101 in the TIMx_SMCR register

(TI1FP1 selected).

7. Configure the slave mode controller in reset mode: write the SMS bits to 0100 in the

TIMx_SMCR register.

8. Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.

Figure 148. PWM input mode timing

19.3.9 Forced output mode

In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal

(OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter.

To force an output compare signal (OCXREF/OCx) to its active level, user just needs to write 0101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.

For example: CCxP=0 (OCx active high) => OCx is forced to high level.

The OCxREF signal can be forced low by writing the OCxM bits to 0100 in the

TIMx_CCMRx register.

Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the output compare mode section below.

RM0471 Rev 5 559/1202

631

Advanced-control timer (TIM1) RM0471

19.3.10 Output compare mode

This function is used to control an output waveform or indicate when a period of time has elapsed. Channels 1 to 4 can be output, while Channel 5 and 6 are only available inside the device (for instance, for compound waveform generation or for ADC triggering).

When a match is found between the capture/compare register and the counter, the output compare function:

 Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=0000), be set active (OCxM=0001), be set inactive (OCxM=0010) or can toggle (OCxM=0011) on match.

 Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).

 Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the

TIMx_DIER register).

 Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the

TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection).

The TIMx_CCRx registers can be programmed with or without preload registers using the

OCxPE bit in the TIMx_CCMRx register.

In output compare mode, the update event UEV has no effect on OCxREF and OCx output.

The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One Pulse mode).

Procedure

Select the counter clock (internal, external, prescaler).

2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.

3. Set the CCxIE bit if an interrupt request is to be generated.

4. Select the output mode. For example:

– Write OCxM = 0011 to toggle OCx output pin when CNT matches CCRx

– Write OCxPE = 0 to disable preload register

– Write CCxP = 0 to select active high polarity

– Write CCxE = 1 to enable the output

5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.

The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in

Figure 149 .

560/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Figure 149. Output compare mode, toggle on OC1

Write B201h in the CC1R register

TIM1_CNT 0039

TIM1_CCR1

OC1REF= OC1

003A

003B B200

B201

Match detected on CCR1

Interrupt generated if enabled

MS31092V1

Pulse Width Modulation mode allows a signal to be generated with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the

TIMx_CCRx register.

The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing ‘0110’ (PWM mode 1) or ‘0111’ (PWM mode 2) in the OCxM bits in the

TIMx_CCMRx register. The corresponding preload register must be enabled by setting the

OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.

As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, all registers must be initialized by setting the UG bit in the TIMx_EGR register.

OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by a combination of the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers).

Refer to the TIMx_CCER register description for more details.

In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction of the counter).

The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register.

RM0471 Rev 5 561/1202

631

Advanced-control timer (TIM1) RM0471

PWM edge-aligned mode

 Upcounting configuration

Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the

Upcounting mode on page 537 .

In the following example, we consider PWM mode 1. The reference PWM signal

OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’.

Figure 150 shows some edge-aligned PWM waveforms in an example where

TIMx_ARR=8.

Figure 150. Edge-aligned PWM waveforms (ARR=8)

Counter register

CCRx=4

OCXREF

CCxIF

0 1 2 3 4 5 6 7 8 0 1

CCRx=8

OCXREF

CCxIF

CCRx>8

OCXREF ‘1’

CCxIF

CCRx=0

OCXREF ‘0’

CCxIF

MS31093V1

 Downcounting configuration

Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to the

Downcounting mode on page 541

In PWM mode 1, the reference signal OCxRef is low as long as

TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM is not possible in this mode.

PWM center-aligned mode

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from

‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals).

The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the

562/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to the

Center-aligned mode (up/down counting) on page 544 .

Figure 151 shows some center-aligned PWM waveforms in an example where:

 TIMx_ARR=8,

 PWM mode is the PWM mode 1,

 The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register.

Figure 151. Center-aligned PWM waveforms (ARR=8)

Counter register 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1

OCxREF

CCRx = 4

CCxIF CMS=01

CMS=10

CMS=11

CCRx=7

OCxREF

CMS=10 or 11

CCxIF

CCRx=8

OCxREF

‘1’

CCxIF

CMS=01

CMS=10

CMS=11

CCRx>8

OCxREF

‘1’

CCxIF CMS=01

CMS=10

CMS=11

CCRx=0

OCxREF

‘0’

CCxIF

CMS=01

CMS=10

CMS=11

AI14681b

Hints on using center-aligned mode

 When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit

RM0471 Rev 5 563/1202

631

Advanced-control timer (TIM1) RM0471 in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software.

 Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. In particular:

– The direction is not updated if a value greater than the auto-reload value is written in the counter (TIMx_CNT>TIMx_ARR). For example, if the counter was counting up, it continues to count up.

– The direction is updated if 0 or the TIMx_ARR value is written in the counter but no

Update Event UEV is generated.

 The safest way to use center-aligned mode is to generate an update by software

(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to write the counter while it is running.

19.3.12 Asymmetric PWM mode

Note:

Asymmetric mode allows two center-aligned PWM signals to be generated with a programmable phase shift. While the frequency is determined by the value of the

TIMx_ARR register, the duty cycle and the phase-shift are determined by a pair of

TIMx_CCRx register. One register controls the PWM during up-counting, the second during down counting, so that PWM is adjusted every half PWM cycle:

– OC1REFC (or OC2REFC) is controlled by TIMx_CCR1 and TIMx_CCR2

– OC3REFC (or OC4REFC) is controlled by TIMx_CCR3 and TIMx_CCR4

Asymmetric PWM mode can be selected independently on two channel (one OCx output per pair of CCR registers) by writing ‘1110’ (Asymmetric PWM mode 1) or ‘1111’

(Asymmetric PWM mode 2) in the OCxM bits in the TIMx_CCMRx register.

The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones.

When a given channel is used as asymmetric PWM channel, its complementary channel can also be used. For instance, if an OC1REFC signal is generated on channel 1

(Asymmetric PWM mode 1), it is possible to output either the OC2REF signal on channel 2, or an OC2REFC signal resulting from asymmetric PWM mode 1.

Figure 152 represents an example of signals that can be generated using Asymmetric PWM

mode (channels 1 to 4 are configured in Asymmetric PWM mode 1). Together with the deadtime generator, this allows a full-bridge phase-shifted DC to DC converter to be controlled.

564/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Figure 152. Generation of 2 phase-shifted PWM signals with 50% duty cycle

Counter register 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 0 1

OC1REFC

CCR1=0

CCR2=8

CCR3=3

OC3REFC

CCR4=5

MS33117V1

19.3.13 Combined PWM mode

Note:

Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and delay are determined by the two TIMx_CCRx registers. The resulting signals, OCxREFC, are made of an OR or

AND logical combination of two reference PWMs:

– OC1REFC (or OC2REFC) is controlled by TIMx_CCR1 and TIMx_CCR2

– OC3REFC (or OC4REFC) is controlled by TIMx_CCR3 and TIMx_CCR4

Combined PWM mode can be selected independently on two channels (one OCx output per pair of CCR registers) by writing ‘1100’ (Combined PWM mode 1) or ‘1101’ (Combined PWM mode 2) in the OCxM bits in the TIMx_CCMRx register.

When a given channel is used as combined PWM channel, its complementary channel must be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the other in Combined PWM mode 2).

The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones.

Figure 153 represents an example of signals that can be generated using Asymmetric PWM

mode, obtained with the following configuration:

– Channel 1 is configured in Combined PWM mode 2,

– Channel 2 is configured in PWM mode 1,

– Channel 3 is configured in Combined PWM mode 2,

– Channel 4 is configured in PWM mode 1.

RM0471 Rev 5 565/1202

631

Advanced-control timer (TIM1)

Figure 153. Combined PWM mode on channel 1 and 3

RM0471

OC2’

OC1’

OC2

OC1

OC1REF

OC2REF

OC1REF’

OC2REF’

OC1REFC

OC1REFC’

OC1REFC = OC1REF AND OC2REF

OC1REFC’ = OC1REF’ OR OC2REF’

MS31094V1

19.3.14 Combined 3-phase PWM mode

Combined 3-phase PWM mode allows one to three center-aligned PWM signals to be generated with a single programmable signal ANDed in the middle of the pulses. The

OC5REF signal is used to define the resulting combined signal. The 3-bits GC5C[3:1] in the

TIMx_CCR5 allow selection on which reference signal the OC5REF is combined. The resulting signals, OCxREFC, are made of an AND logical combination of two reference

PWMs:

– If GC5C1 is set, OC1REFC is controlled by TIMx_CCR1 and TIMx_CCR5

– If GC5C2 is set, OC2REFC is controlled by TIMx_CCR2 and TIMx_CCR5

– If GC5C3 is set, OC3REFC is controlled by TIMx_CCR3 and TIMx_CCR5

Combined 3-phase PWM mode can be selected independently on channels 1 to 3 by setting at least one of the 3-bits GC5C[3:1].

566/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Figure 154. 3-phase combined PWM signals with multiple trigger pulses per period

OC5

ARR

OC6

OC1

OC4

OC2

OC3

Counter

OC5ref

OC1refC

OC2refC

OC3refC

Preload

100

Active

OC4ref

OC6ref

TRGO2

001 xxx

100 xxx

MS33102V1

The TRGO2 waveform shows how the ADC can be synchronized on given 3-phase PWM

signals. Refer to Section 19.3.27: ADC synchronization

for more details.

The advanced-control timers (TIM1) can output two complementary signals and manage the switching-off and the switching-on instants of the outputs.

This time is generally known as dead-time and it has to be adjusted depending on the devices that are connected to the outputs and their characteristics (intrinsic delays of levelshifters, delays due to power switches...)

The polarity of the outputs (main output OCx or complementary OCxN) can be selected independently for each output. This is done by writing to the CCxP and CCxNP bits in the

TIMx_CCER register.

The complementary signals OCx and OCxN are activated by a combination of several control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx,

OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to

Table 128: Output control bits for complementary OCx and OCxN channels with break feature on page 613

for more details. In particular, the dead-time is activated when switching to the idle state (MOE falling down to 0).

RM0471 Rev 5 567/1202

631

Advanced-control timer (TIM1) RM0471

Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. There is one 10-bit dead-time generator for each channel. From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high:

 The OCx output signal is the same as the reference signal except for the rising edge, which is delayed relative to the reference rising edge.

 The OCxN output signal is the opposite of the reference signal except for the rising edge, which is delayed relative to the reference falling edge.

If the delay is greater than the width of the active output (OCx or OCxN) then the corresponding pulse is not generated.

The following figures show the relationships between the output signals of the dead-time generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1,

CCxE=1 and CCxNE=1 in these examples)

Figure 155. Complementary output with dead-time insertion

OCxREF

OCx

OCxN delay delay

MS31095V1

Figure 156. Dead-time waveforms with delay greater than the negative pulse

OCxREF

OCx

OCxN delay

MS31096V1

568/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Figure 157. Dead-time waveforms with delay greater than the positive pulse

OCxREF

OCx

OCxN delay

Note:

MS31097V1

The dead-time delay is the same for each of the channels and is programmable with the

DTG bits in the TIMx_BDTR register. Refer to Section 19.4.20: TIM1 break and dead-time register (TIM1_BDTR)

for delay calculation.

Re-directing OCxREF to OCx or OCxN

In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER register.

This allows a specific waveform to be sent (such as PWM or static active level) on one output while the complementary remains at its inactive level. Other alternative possibilities are to have both outputs at inactive level or both outputs active and complementary with dead-time.

When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes active when OCxREF is high whereas OCxN is complemented and becomes active when

OCxREF is low.

19.3.16 Using the break function

The purpose of the break function is to protect power switches driven by PWM signals generated with the TIM1 timer. The two break inputs are usually connected to fault outputs of power stages and 3-phase inverters. When activated, the break circuitry shuts down the

PWM outputs and forces them to a predefined safe state. A number of internal MCU events can also be selected to trigger an output shut-down.

The break features two channels. A break channel which gathers both system-level fault

(clock failure, parity error,...) and application fault (from input pins), and can force the outputs to a predefined level (either active or inactive) after a deadtime duration. A break2 channel which only includes application faults and is able to force the outputs to an inactive state.

RM0471 Rev 5 569/1202

631

Advanced-control timer (TIM1) RM0471

The output enable signal and output levels during break are depending on several control bits:

– the MOE bit in TIMx_BDTR register allows the outputs to be enabled/disabled by software and is reset in case of break or break2 event.

– the OSSI bit in the TIMx_BDTR register defines whether the timer controls the output in inactive state or releases the control to the GPIO controller (typically to have it in Hi-Z mode)

– the OISx and OISxN bits in the TIMx_CR2 register which are setting the output shut-down level, either active or inactive. The OCx and OCxN outputs cannot be set both to active level at a given time, whatever the OISx and OISxN values.

Refer to Table 128: Output control bits for complementary OCx and OCxN channels with break feature on page 613 for more details.

When exiting from reset, the break circuit is disabled and the MOE bit is low. The break functions can be enabled by setting the BKE and BK2E bits in the TIMx_BDTR register. The break input polarities can be selected by configuring the BKP and BK2P bits in the same register. BKE/BK2E and BKP/BK2P can be modified at the same time. When the BKE/BK2E and BKP/BK2P bits are written, a delay of 1 APB clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1 APB clock period to correctly read back the bit after the write operation.

Because MOE falling edge can be asynchronous, a resynchronization circuit has been inserted between the actual signal (acting on the outputs) and the synchronous control bit

(accessed in the TIMx_BDTR register). It results in some delays between the asynchronous and the synchronous signals. In particular, if MOE is set to 1 whereas it was low, a delay must be inserted (dummy instruction) before reading it correctly. This is because the write acts on the asynchronous signal whereas the read reflects the synchronous signal.

The break can be generated from multiple sources which can be individually enabled and with programmable edge sensitivity, using the TIMx_AF1 and TIMx_AF2 registers.

The sources for break (BRK) channel are:

 An external source connected to one of the BKIN pin (as per selection done in the

SYSCFG_CFGR2 register), with polarity selection and optional digital filtering

 An internal source:

– the CPU1 Cortex ® -M4 LOCKUP output

– the PVD output

– the SRAM parity error signal

– a Flash memory ECC double error detection

– a clock failure event generated by the CSS detector

The sources for break2 (BRK2) is an external source connected to one of the BKIN pin (as per selection done in the SYSCFG_CFGR2 register), with polarity selection and optional digital filtering

Break events can also be generated by software using BG and B2G bits in the TIMx_EGR register. The software break generation using BG and B2G is active whatever the BKE and

BK2E enable bits values.

All sources are ORed before entering the timer BRK or BRK2 inputs, as per

Figure 158

below.

570/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Figure 158. Break and Break2 circuitry overview

Core Lockup

Lockup LOCK

PVD

PVD LOCK

RAM parity Error

Parity LOCK

Double ECC Error

ECC LOCK

CSS

System break requests

SBIF flag

BKIN inputs from AF controller

BKINP

BKINE

BKF[3:0]

Filter

BKP

Application break requests

Software break requests: BG

BIF flag

BKE

BRK request

BKIN2 inputs from AF controller

BK2INP

BK2INE

BK2F[3:0]

Filter

BK2P

Application break requests

Software break requests: B2G

B2IF flag

BK2E

BRK2 request

Note:

MSv63011V2

An asynchronous (clockless) operation is only guaranteed when the programmable filter is disabled. If it is enabled, a fail safe clock mode (for example by using the internal PLL and/or the CSS) must be used to guarantee that break events are handled.

RM0471 Rev 5 571/1202

631

Advanced-control timer (TIM1)

Note:

RM0471

When one of the breaks occurs (selected level on one of the break inputs):

 The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or even releasing the control to the GPIO controller (selected by the OSSI bit). This feature is enabled even if the MCU oscillator is off.

 Each output channel is driven with the level programmed in the OISx bit in the

TIMx_CR2 register as soon as MOE=0. If OSSI=0, the timer releases the output control

(taken over by the GPIO controller), otherwise the enable output remains high.

 When complementary outputs are used:

– The outputs are first put in inactive state (depending on the polarity). This is done asynchronously so that it works even if no clock is provided to the timer.

– If the timer clock is still present, then the dead-time generator is reactivated in order to drive the outputs with the level programmed in the OISx and OISxN bits after a dead-time. Even in this case, OCx and OCxN cannot be driven to their active level together. Note that because of the resynchronization on MOE, the dead-time duration is slightly longer than usual (around 2 ck_tim clock cycles).

– If OSSI=0, the timer releases the output control (taken over by the GPIO controller which forces a Hi-Z state), otherwise the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high.

 The break status flag (SBIF, BIF and B2IF bits in the TIMx_SR register) is set. An interrupt is generated if the BIE bit in the TIMx_DIER register is set.

 If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again at the next update event (UEV). As an example, this can be used to perform a regulation. Otherwise, MOE remains low until the application sets it to ‘1’ again. In this case, it can be used for security and the break input can be connected to an alarm from power drivers, thermal sensors or any security components.

If the MOE is reset by the CPU while the AOE bit is set, the outputs will be in idle state and forced to inactive level or Hi-Z depending on OSSI value.

If both the MOE and AOE bits are reset by the CPU, the outputs will be in disabled state and driven with the level programmed in the OISx bit in the TIMx_CR2 register.

The break inputs are active on level. Thus, the MOE cannot be set while the break input is active (neither automatically nor by software). In the meantime, the status flag BIF and B2IF cannot be cleared.

In addition to the break input and the output management, a write protection has been implemented inside the break circuit to safeguard the application. It allows the configuration of several parameters to be freezed (dead-time duration, OCx/OCxN polarities and state when disabled, OCxM configurations, break enable and polarity). The application can choose from 3 levels of protection selected by the LOCK bits in the TIMx_BDTR register.

Refer to

Section 19.4.20: TIM1 break and dead-time register (TIM1_BDTR)

. The LOCK bits can be written only once after an MCU reset.

Figure 159 shows an example of behavior of the outputs in response to a break.

572/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Figure 159. Various output behavior in response to a break event on BRK (OSSI = 1)

BREAK (MOE )

OCxREF

OCx

(OCxN not implemented, CCxP=0, OISx=1)

OCx

(OCxN not implemented, CCxP=0, OISx=0)

OCx

(OCxN not implemented, CCxP=1, OISx=1)

OCx

(OCxN not implemented, CCxP=1, OISx=0)

OCx

OCxN delay delay

(CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1) delay

OCx

OCxN delay delay

(CCxE=1, CCxP=0, OISx=1, CCxNE=1, CCxNP=1, OISxN=1) delay

OCx

OCxN

(CCxE=1, CCxP=0, OISx=0, CCxNE=0, CCxNP=0, OISxN=1) delay

OCx

OCxN

(CCxE=1, CCxP=0, OISx=1, CCxNE=0, CCxNP=0, OISxN=0) delay

OCx

OCxN

(CCxE=1, CCxP=0, CCxNE=0, CCxNP=0, OISx=OISxN=0 or OISx=OISxN=1)

MS31098V1

RM0471 Rev 5 573/1202

631

Advanced-control timer (TIM1)

Note:

RM0471

The two break inputs have different behaviors on timer outputs:

– The BRK input can either disable (inactive state) or force the PWM outputs to a predefined safe state.

– BRK2 can only disable (inactive state) the PWM outputs.

The BRK has a higher priority than BRK2 input, as described in Table 124 .

BRK2 must only be used with OSSR = OSSI = 1.

BRK

Active

Inactive

Table 124. Behavior of timer outputs versus BRK/BRK2 inputs

Typical use case

BRK2

Timer outputs state OCxN output

(low side switches)

OCx output

(high side switches)

Active

– Inactive then forced output state (after a deadtime)

– Outputs disabled if OSSI = 0

(control taken over by GPIO logic)

Inactive

ON after deadtime insertion

OFF

Figure 160 gives an example of OCx and OCxN output behavior in case of active signals on

BRK and BRK2 inputs. In this case, both outputs have active high polarities (CCxP =

CCxNP = 0 in TIMx_CCER register).

Figure 160. PWM output state following BRK and BRK2 pins assertion (OSSI=1)

BRK2

BRK

OCx

Deadtime Deadtime

I/O state

Active Inactive Idle

MS34106V1

574/1202 RM0471 Rev 5

RM0471

BRK

Advanced-control timer (TIM1)

Figure 161. PWM output state following BRK assertion (OSSI=0)

OCx

I/O state

Active

Deadtime

Inactive

I/O state defined by the GPIO controller (HI-Z)

Disabled

MS34107V1

The TIM1 are featuring bidirectional break I/Os, as represented on Figure 162 .

They allow the following:

 A board-level global break signal available for signaling faults to external MCUs or gate drivers, with a unique pin being both an input and an output status pin

 Internal break sources and multiple external open drain comparator outputs ORed together to trigger a unique break event, when multiple internal and external break sources must be merged

The break and break2 inputs are configured in bidirectional mode using the BKBID and

BK2BID bits in the TIMxBDTR register. The BKBID programming bits can be locked in readonly mode using the LOCK bits in the TIMxBDTR register (in LOCK level 1 or above).

The bidirectional mode is available for both the break and break2 inputs, and require the I/O to be configured in open-drain mode with active low polarity (using BKINP, BKP, BK2INP and BK2P bits). Any break request coming either from system (e.g. CSS), from on-chip peripherals or from break inputs forces a low level on the break input to signal the fault event. The bidirectional mode is inhibited if the polarity bits are not correctly set (active high polarity), for safety purposes.

The break software events (BG and B2G) also cause the break I/O to be forced to '0' to indicate to the external components that the timer has entered in break state. However, this is valid only if the break is enabled (BK(2)E = 1). When a software break event is generated with BK(2)E = 0, the outputs are put in safe state and the break flag is set, but there is no effect on the break(2) I/O.

A safe disarming mechanism prevents the system to be definitively locked-up (a low level on the break input triggers a break which enforces a low level on the same input).

When the BKDSRM (BK2DSRM) bit is set to 1, this releases the break output to clear a fault signal and to give the possibility to re-arm the system.

At no point the break protection circuitry can be disabled:

 The break input path is always active: a break event is active even if the BKDSRM

(BK2DSRM) bit is set and the open drain control is released. This prevents the PWM output to be re-started as long as the break condition is present.

 The BK(2)DSRM bit cannot disarm the break protection as long as the outputs are

enabled (MOE bit is set) (see Table 125

)

RM0471 Rev 5 575/1202

631

Advanced-control timer (TIM1) RM0471

MOE

Table 125. Break protection disarming conditions

BKDIR

(BK2DIR)

BKDSRM

(BK2DSRM)

Break protection state

Armed

Disarmed

Armed

Arming and re-arming break circuitry

The break circuitry (in input or bidirectional mode) is armed by default (peripheral reset configuration).

The following procedure must be followed to re-arm the protection after a break (break2) event:

 The BKDSRM (BK2DSRM) bit must be set to release the output control

 The software must wait until the system break condition disappears (if any) and clear the SBIF status flag (or clear it systematically before re-arming)

 The software must poll the BKDSRM (BK2DSRM) bit until it is cleared by hardware

(when the application break condition disappears)

From this point, the break circuitry is armed and active, and the MOE bit can be set to reenable the PWM outputs.

Figure 162. Output redirection (BRK2 request not represented)

Other break inputs

Bidirectional

Break I/O

AF input

(active low)

AF output

(open drain)

System break request

Peripheral break sources

AF controller

BKIN inputs from

AF controller

BKF[3:0]

Filter

BKP

Application break requests

SBIF flag

BKE

Software break requests: BG

BIF flag

BRK request

Bidirectional mode control logic

System break request

Vss

BRK request

MOE BKBID BKBDSRM

MSv42028V2

576/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

The OCxREF signal of a given channel can be cleared when a high level is applied on the ocref_clr_int input (OCxCE enable bit in the corresponding TIMx_CCMRx register set to 1).

OCxREF remains low until the next update event (UEV) occurs. This function can only be used in Output compare and PWM modes. It does not work in Forced mode. ocref_clr_int input can be selected between the OCREF_CLR input and ETRF (ETR after the filter) by configuring the OCCS bit in the TIMx_SMCR register.

When ETRF is chosen, ETR must be configured as follows:

The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR register set to ‘00’.

2. The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to

‘0’.

3. The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be configured according to the user needs.

Figure 163 shows the behavior of the OCxREF signal when the ETRF Input becomes High,

for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in

PWM mode.

Figure 163. Clearing TIMx OCxREF

Counter (CNT)

(CCRx)

ETRF

Note:

OCxREF

(OCxCE = ‘0’)

OCxREF

(OCxCE = ‘1’) ocref_clr_int becomes high ocref_clr_int still high

MS33105V2

In case of a PWM with a 100% duty cycle (if CCRx>ARR), then OCxREF is enabled again at the next counter overflow.

RM0471 Rev 5 577/1202

631

Advanced-control timer (TIM1) RM0471

When complementary outputs are used on a channel, preload bits are available on the

OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the

COM commutation event. Thus one can program in advance the configuration for the next step and change the configuration of all the channels at the same time. COM can be generated by software by setting the COM bit in the TIMx_EGR register or by hardware (on

TRGI rising edge).

A flag is set when the COM event occurs (COMIF bit in the TIMx_SR register), which can generate an interrupt (if the COMIE bit is set in the TIMx_DIER register) or a DMA request

(if the COMDE bit is set in the TIMx_DIER register).

The

Figure 164 describes the behavior of the OCx and OCxN outputs when a COM event

occurs, in 3 different examples of programmed configurations.

Figure 164. 6-step generation, COM example (OSSR=1)

578/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.

Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. One-pulse mode is selected by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV.

A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be:

 In upcounting: CNT < CCRx ≤ ARR (in particular, 0 < CCRx)

 In downcounting: CNT > CCRx

Figure 165. Example of one pulse mode.

TI2

OC1REF

OC1

TIM1_ARR

TIM1_CCR1

0 t

DELAY t

PULSE t

MS31099V1

For example one may want to generate a positive pulse on OC1 with a length of t

PULSE after a delay of t

DELAY

as soon as a positive edge is detected on the TI2 input pin.

and

Let’s use TI2FP2 as trigger 1:

Select the proper TI2x source (internal or external) with the TI2SEL[3:0] bits in the

TIMx_TISEL register.

2. Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.

3. TI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER register.

4. Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=00110 in the TIMx_SMCR register.

5. TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register

(trigger mode).

RM0471 Rev 5 579/1202

631

Advanced-control timer (TIM1) RM0471

The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler).

 The t

DELAY is defined by the value written in the TIMx_CCR1 register.

 The t

PULSE

is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1).

 Let’s say one want to build a waveform with a transition from ‘0’ to ‘1’ when a compare match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload value. To do this PWM mode 2 must be enabled by writing OC1M=111 in the

TIMx_CCMR1 register. Optionally the preload registers can be enabled by writing

OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case one has to write the compare value in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0’ in this example.

In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.

Since only 1 pulse (Single mode) is needed, a 1 must be written in the OPM bit in the

TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the Repetitive Mode is selected.

Particular case: OCx fast enable:

In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay t

DELAY

min we can get.

If one wants to output a waveform with the minimum delay, the OCxFE bit can be set in the

TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.

19.3.21 Retriggerable one pulse mode

Note:

This mode allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length, but with the following differences with Non-retriggerable one pulse mode described in

Section 19.3.20

– The pulse starts as soon as the trigger occurs (no programmable delay)

– The pulse is extended if a new trigger occurs before the previous one is completed

The timer must be in Slave mode, with the bits SMS[3:0] = ‘1000’ (Combined Reset + trigger mode) in the TIMx_SMCR register, and the OCxM[3:0] bits set to ‘1000’ or ‘1001’ for

Retrigerrable OPM mode 1 or 2.

If the timer is configured in Up-counting mode, the corresponding CCRx must be set to 0

(the ARR register sets the pulse length). If the timer is configured in Down-counting mode,

CCRx must be above or equal to ARR.

The OCxM[3:0] and SMS[3:0] bit fields are split into two parts for compatibility reasons, the most significant bit are not contiguous with the 3 least significant ones.

This mode must not be used with center-aligned PWM modes. It is mandatory to have

CMS[1:0] = 00 in TIMx_CR1.

580/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Figure 166. Retriggerable one pulse mode

TRGI

Counter

Output

MS33106V1

Note:

To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and

SMS=’011’ if it is counting on both TI1 and TI2 edges.

Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register. When needed, the input filter can be programmed as well. CC1NP and CC2NP must be kept low.

The two inputs TI1 and TI2 are used to interface to a quadrature encoder. Refer to

Table 126

. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2 after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,

TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in

TIMx_CR1 register written to ‘1’). The sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on TI1 only, TI2 only or both TI1 and TI2.

Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value in the

TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So the

TIMx_ARR must be configured before starting. In the same way, the capture, compare, repetition counter, trigger output features continue to work as normal. Encoder mode and

External clock mode 2 are not compatible and must not be selected together.

The prescaler must be set to zero when encoder mode is enabled

In this mode, the counter is modified automatically following the speed and the direction of the quadrature encoder and its content, therefore, always represents the encoder’s position.

The count direction correspond to the rotation direction of the connected sensor. The table summarizes the possible combinations, assuming TI1 and TI2 do not switch at the same time.

RM0471 Rev 5 581/1202

631

Advanced-control timer (TIM1) RM0471

Active edge

Counting on

TI1 only

Counting on

TI2 only

Counting on

TI1 and TI2

Table 126. Counting direction versus encoder signals

Level on opposite signal (TI1FP1 for TI2,

TI2FP2 for

TI1)

TI1FP1 signal

Rising Falling

TI2FP2 signal

Rising Falling

High

Low

High

Low

High

Low

Down

No Count

Down

No Count

Down

No Count

Down

No Count

Down

A quadrature encoder can be connected directly to the MCU without external interface logic.

However, comparators are normally be used to convert the encoder’s differential outputs to digital signals. This greatly increases noise immunity. The third encoder output which indicate the mechanical zero position, may be connected to an external interrupt input and trigger a counter reset.

The

Figure 167 gives an example of counter operation, showing count signal generation

and direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near to one of the switching points. For this example we assume that the configuration is the following:

 CC1S=’01’ (TIMx_CCMR1 register, TI1FP1 mapped on TI1).

 CC2S=’01’ (TIMx_CCMR2 register, TI1FP2 mapped on TI2).

 CC1P=’0’ and CC1NP=’0’ (TIMx_CCER register, TI1FP1 non-inverted, TI1FP1=TI1).

 CC2P=’0’ and CC2NP=’0’ (TIMx_CCER register, TI1FP2 non-inverted, TI1FP2= TI2).

 SMS=’011’ (TIMx_SMCR register, both inputs are active on both rising and falling edges).

 CEN=’1’ (TIMx_CR1 register, Counter enabled).

Figure 167. Example of counter operation in encoder interface mode.

forward jitter backward jitter forward

TI1

TI2

Counter up down up

MS33107V1

582/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Figure 168 gives an example of counter behavior when TI1FP1 polarity is inverted (same

configuration as above except CC1P=’1’).

Figure 168. Example of encoder interface mode with TI1FP1 polarity inverted.

forward jitter backward jitter forward

TI1

TI2

Counter down up down

MS33108V1

The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. Dynamic information can be obtained (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode. The output of the encoder which indicates the mechanical zero can be used for this purpose. Depending on the time between two events, the counter can also be read at regular times. This can be done by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer). when available, it is also possible to read its value through a DMA request.

The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the update interrupt flag (UIF) into the timer counter register’s bit 31 (TIMxCNT[31]). This allows both the counter value and a potential roll-over condition signaled by the UIFCPY flag to be read in an atomic way. It eases the calculation of angular speed by avoiding race conditions caused, for instance, by a processing shared between a background task (counter reading) and an interrupt (update interrupt).

There is no latency between the UIF and UIFCPY flag assertions.

In 32-bit timer implementations, when the IUFREMAP bit is set, bit 31 of the counter is overwritten by the UIFCPY flag upon read access (the counter’s most significant bit is only accessible in write mode).

19.3.23 UIF bit remapping

The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update

Interrupt Flag UIF into the timer counter register’s bit 31 (TIMxCNT[31]). This allows both the counter value and a potential roll-over condition signaled by the UIFCPY flag to be read in an atomic way. In particular cases, it can ease the calculations by avoiding race conditions, caused for instance by a processing shared between a background task

(counter reading) and an interrupt (Update Interrupt).

There is no latency between the UIF and UIFCPY flags assertion.

RM0471 Rev 5 583/1202

631

Advanced-control timer (TIM1) RM0471

19.3.24 Timer input XOR function

The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of an XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and

TIMx_CH3.

The XOR output can be used with all the timer input functions such as trigger or input capture. It is convenient to measure the interval between edges on two input signals, as per

Figure 169 below.

Figure 169. Measuring time interval between edges on 3 signals

TI1

TI2

TI3

XOR

TIMx

Counter

MS33109V1

19.3.25 Interfacing with Hall sensors

This is done using the advanced-control timer (TIM1) to generate PWM signals to drive the motor and another timer TIMx (TIM2) referred to as “interfacing timer” in

Figure 170

. The

“interfacing timer” captures the 3 timer input pins (CC1, CC2, CC3) connected through a

XOR to the TI1 input channel (selected by setting the TI1S bit in the TIMx_CR2 register).

The slave mode controller is configured in reset mode; the slave input is TI1F_ED. Thus, each time one of the 3 inputs toggles, the counter restarts counting from 0. This creates a time base triggered by any change on the Hall inputs.

On the “interfacing timer”, capture/compare channel 1 is configured in capture mode, capture signal is TRC (See

Figure 143: Capture/compare channel (example: channel 1 input stage) on page 555 ). The captured value, which corresponds to the time elapsed

between 2 changes on the inputs, gives information about motor speed.

The “interfacing timer” can be used in output mode to generate a pulse which changes the configuration of the channels of the advanced-control timer (TIM1) (by triggering a COM event). The TIM1 timer is used to generate PWM signals to drive the motor. To do this, the interfacing timer channel must be programmed so that a positive pulse is generated after a programmed delay (in output compare or PWM mode). This pulse is sent to the advancedcontrol timer (TIM1) through the TRGO output.

584/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Example: one wants to change the PWM configuration of the advanced-control timer TIM1 after a programmed delay each time a change occurs on the Hall inputs connected to one of the TIMx timers.

 Configure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the

TIMx_CR2 register to ‘1’,

 Program the time base: write the TIMx_ARR to the max value (the counter must be cleared by the TI1 change. Set the prescaler to get a maximum counter period longer than the time between 2 changes on the sensors,

 Program the channel 1 in capture mode (TRC selected): write the CC1S bits in the

TIMx_CCMR1 register to ‘01’. The digital filter can also be programmed if needed,

 Program the channel 2 in PWM 2 mode with the desired delay: write the OC2M bits to

‘111’ and the CC2S bits to ‘00’ in the TIMx_CCMR1 register,

 Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 register to ‘101’,

In the advanced-control timer TIM1, the right ITR input must be selected as trigger input, the timer is programmed to generate PWM signals, the capture/compare control signals are preloaded (CCPC=1 in the TIMx_CR2 register) and the COM event is controlled by the trigger input (CCUS=1 in the TIMx_CR2 register). The PWM control bits (CCxE, OCxM) are written after a COM event for the next step (this can be done in an interrupt subroutine generated by the rising edge of OC2REF).

The

Figure 170 describes this example.

RM0471 Rev 5 585/1202

631

Advanced-control timer (TIM1)

Figure 170. Example of Hall sensor interface

TIH1

TIH2

TIH3

Counter (CNT)

(CCR2)

CCR1

TRGO=OC2REF

C7A3 C7A8 C794 C7A5 C7AB C796

RM0471

COM

OC1

OC1N

OC2

OC2N

OC3

OC3N

Write CCxE, CCxNE and OCxM for next step

MS32672V1

586/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

The TIMx timers are linked together internally for timer synchronization or chaining. Refer to

Section 20.3.19: Timer synchronization for details. They can be synchronized in several

modes: Reset mode, Gated mode, and Trigger mode.

Slave mode: Reset mode

The counter and its prescaler can be reinitialized in response to an event on a trigger input.

Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.

In the following example, the upcounter is cleared in response to a rising edge on TI1 input:

 Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration

(in this example, we do not need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so it does not need to be configured. The CC1S bits select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write

CC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect rising edges only).

 Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select

TI1 as the input source by writing TS=00101 in TIMx_SMCR register.

 Start the counter by writing CEN=1 in the TIMx_CR1 register.

The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).

The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.

The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input.

Figure 171. Control circuit in reset mode

TI1

Counter clock = ck_cnt = ck_psc

Counter register

TIF

30 31 32 33 34 35 36 00 01 02 03 00 01 02 03

MS31401V1

RM0471 Rev 5 587/1202

631

Advanced-control timer (TIM1) RM0471

Slave mode: Gated mode

The counter can be enabled depending on the level of a selected input.

In the following example, the upcounter counts only when TI1 input is low:

 Configure the channel 1 to detect low levels on TI1. Configure the input filter duration

CC1P=1 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect low level only).

 Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select

TI1 as the input source by writing TS=00101 in TIMx_SMCR register.

 Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=0, whatever is the trigger input level).

The counter starts counting on the internal clock as long as TI1 is low and stops as soon as

TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops.

The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input.

Figure 172. Control circuit in Gated mode

TI1 cnt_en

Counter clock = ck_cnt = ck_psc

Counter register

TIF

30 31 32 33 34 35 36 37 38

Write TIF=0

MS31402V1

Slave mode: Trigger mode

The counter can start in response to an event on a selected input.

In the following example, the upcounter starts in response to a rising edge on TI2 input:

 Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration

(in this example, we do not need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so it does not need to be configured. The CC2S bits are configured to select the input capture source only, CC2S=01 in TIMx_CCMR1

588/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1) register. Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity

(and detect low level only).

 Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select

TI2 as the input source by writing TS=00110 in TIMx_SMCR register.

When a rising edge occurs on TI2, the counter starts counting on the internal clock and the

TIF flag is set.

The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input.

Figure 173. Control circuit in trigger mode

TI2 cnt_en

Counter clock = ck_cnt = ck_psc

Counter register

34 35 36 37 38

TIF

MS31403V1

Slave mode: Combined reset + trigger mode

In this case, a rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers, and starts the counter.

This mode is used for one-pulse mode.

Slave mode: external clock mode 2 + trigger mode

The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock input, and another input can be selected as trigger input (in reset mode, gated mode or trigger mode). It is recommended not to select ETR as TRGI through the TS bits of

TIMx_SMCR register.

RM0471 Rev 5 589/1202

631

Advanced-control timer (TIM1) RM0471

In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs:

Configure the external trigger input circuit by programming the TIMx_SMCR register as follows:

– ETF = 0000: no filter

– ETPS = 00: prescaler disabled

– ETP = 0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2.

2. Configure the channel 1 as follows, to detect rising edges on TI:

– IC1F = 0000: no filter.

– The capture prescaler is not used for triggering and does not need to be configured.

– CC1S = 01in TIMx_CCMR1 register to select only the input capture source

– CC1P = 0 and CC1NP = 0 in TIMx_CCER register to validate the polarity (and detect rising edge only).

3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select

TI1 as the input source by writing TS=00101 in TIMx_SMCR register.

A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on

ETR rising edges.

The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input.

Figure 174. Control circuit in external clock mode 2 + trigger mode

TI1

CEN/CNT_EN

ETR

Note:

Counter clock = CK_CNT = CK_PSC

Counter register 34 35 36

TIF

MS33110V1

The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.

590/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Note:

The timer can generate an ADC triggering event with various internal signals, such as reset, enable or compare events. It is also possible to generate a pulse issued by internal edge detectors, such as:

– Rising and falling edges of OC4ref

– Rising edge on OC5ref or falling edge on OC6ref

The triggers are issued on the TRGO2 internal line which is redirected to the ADC. There is a total of 16 possible events, which can be selected using the MMS2[3:0] bits in the

TIMx_CR2 register.

An example of an application for 3-phase motor drives is given in

Figure 154 on page 567

The clock of the ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the timer.

19.3.28 DMA burst mode

The TIMx timers have the capability to generate multiple DMA requests upon a single event.

The main purpose is to be able to re-program part of the timer multiple times without software overhead, but it can also be used to read several registers in a row, at regular intervals.

The DMA controller destination is unique and must point to the virtual register TIMx_DMAR.

On a given timer event, the timer launches a sequence of DMA requests (burst). Each write into the TIMx_DMAR register is actually redirected to one of the timer registers.

The DBL[4:0] bits in the TIMx_DCR register set the DMA burst length. The timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers (either in half-words or in bytes).

The DBA[4:0] bits in the TIMx_DCR registers define the DMA base address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register:

Example:

00000: TIMx_CR1

00001: TIMx_CR2

00010: TIMx_SMCR

As an example, the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4) upon an update event, with the DMA transferring half words into the

CCRx registers.

RM0471 Rev 5 591/1202

631

Advanced-control timer (TIM1)

Note:

RM0471

This is done in the following steps:

Configure the corresponding DMA channel as follows:

– DMA channel peripheral address is the DMAR register address

– DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers.

– Number of data to transfer = 3 (See note below).

– Circular mode disabled.

2. Configure the DCR register by configuring the DBA and DBL bit fields as follows:

DBL = 3 transfers, DBA = 0xE.

3. Enable the TIMx update DMA request (set the UDE bit in the DIER register).

5. Enable the DMA channel

This example is for the case where every CCRx register to be updated once. If every CCRx register is to be updated twice for example, the number of data to transfer should be 6. Let's take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and data6. The data is transferred to the CCRx registers as follows: on the first update DMA request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to

CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4.

A null value can be written to the reserved registers.

When the system enters debug mode (processor core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIM1_STOP configuration bit in

DBGMCU module.

For safety purposes, when the counter is stopped, the outputs are disabled (as if the MOE bit was reset). The outputs can either be forced to an inactive state (OSSI bit = 1), or have their control taken over by the GPIO controller (OSSI bit = 0), typically to force a Hi-Z.

For more details, refer to section Debug support (DBG).

592/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Refer to for a list of abbreviations used in register descriptions.

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

19.4.1 TIM1 control register 1 (TIM1_CR1)

Address offset: 0x00

Reset value: 0x0000

Res.

UIFRE

MAP rw

Res.

9 8

CKD[1:0] rw rw

ARPE rw

6 5

CMS[1:0] rw rw

DIR rw

OPM rw

URS rw

UDIS rw

CEN rw

Bits 15:12 Reserved, must be kept at reset value.

Bit 11 UIFREMAP : UIF status bit remapping

0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.

1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.

Bit 10 Reserved, must be kept at reset value.

Bits 9:8 CKD[1:0] : Clock division

This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (t

DTS

(ETR, TIx):

)used by the dead-time generators and the digital filters

00: t

DTS

CK_INT

01: t

DTS

=2*t

CK_INT

10: t

DTS

=4*t

CK_INT

11: Reserved, do not program this value

Note: t

DTS

= 1/f

DTS

, t

CK_INT

= 1/f

CK_INT

Bit 7 ARPE : Auto-reload preload enable

0: TIMx_ARR register is not buffered

1: TIMx_ARR register is buffered

Bits 6:5 CMS[1:0] : Center-aligned mode selection

00: Edge-aligned mode. The counter counts up or down depending on the direction bit

(DIR).

01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down.

10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up.

11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.

Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed

RM0471 Rev 5 593/1202

631

Advanced-control timer (TIM1) RM0471

Bit 4 DIR : Direction

0: Counter used as upcounter

1: Counter used as downcounter

Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.

Bit 3 OPM : One pulse mode

0: Counter is not stopped at update event

1: Counter stops counting at the next update event (clearing the bit CEN)

Bit 2 URS : Update request source

This bit is set and cleared by software to select the UEV event sources.

0: Any of the following events generate an update interrupt or DMA request if enabled.

These events can be:

– Counter overflow/underflow

– Setting the UG bit

– Update generation through the slave mode controller

1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.

Bit 1 UDIS : Update disable

This bit is set and cleared by software to enable/disable UEV event generation.

0: UEV enabled. The Update (UEV) event is generated by one of the following events:

– Counter overflow/underflow

– Setting the UG bit

– Update generation through the slave mode controller

Buffered registers are then loaded with their preload values.

1: UEV disabled. The Update event is not generated, shadow registers keep their value

(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

Bit 0 CEN : Counter enable

0: Counter disabled

1: Counter enabled

Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.

19.4.2 TIM1 control register 2 (TIM1_CR2)

Address offset: 0x04

Reset value: 0x0000 0000

Res.

14 13 12 11 10 9 8

OIS4 OIS3N OIS3 OIS2N OIS2 OIS1N OIS1 rw rw rw rw rw rw rw rw

TI1S rw

22 21

MMS2[3:0] rw

6 rw

5 rw

MMS[2:0] rw

20 rw

4 rw

Res.

OIS6 rw

Res.

OIS5 rw

0 3 1

CCDS CCUS Res.

CCPC rw rw rw

594/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:20 MMS2[3:0] : Master mode selection 2

These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows:

0000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on TRGO2 is delayed compared to the actual reset.

0001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the

CEN control bit and the trigger input when configured in Gated mode. When the

Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2, except if the Master/Slave mode is selected (see the MSM bit description in

TIMx_SMCR register).

0010: Update - the update event is selected as trigger output (TRGO2). For instance, a master timer can then be used as a prescaler for a slave timer.

0011: Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs

(TRGO2).

0100: Compare - OC1REFC signal is used as trigger output (TRGO2)

0101: Compare - OC2REFC signal is used as trigger output (TRGO2)

0110: Compare - OC3REFC signal is used as trigger output (TRGO2)

0111: Compare - OC4REFC signal is used as trigger output (TRGO2)

1000: Compare - OC5REFC signal is used as trigger output (TRGO2)

1001: Compare - OC6REFC signal is used as trigger output (TRGO2)

1010: Compare Pulse - OC4REFC rising or falling edges generate pulses on TRGO2

1011: Compare Pulse - OC6REFC rising or falling edges generate pulses on TRGO2

1100: Compare Pulse - OC4REFC or OC6REFC rising edges generate pulses on TRGO2

1101: Compare Pulse - OC4REFC rising or OC6REFC falling edges generate pulses on

TRGO2

1110: Compare Pulse - OC5REFC or OC6REFC rising edges generate pulses on TRGO2

1111: Compare Pulse - OC5REFC rising or OC6REFC falling edges generate pulses on

TRGO2

Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

Bit 19 Reserved, must be kept at reset value.

Bit 18 OIS6 : Output Idle state 6 (OC6 output)

Refer to OIS1 bit

Bit 17 Reserved, must be kept at reset value.

Bit 16 OIS5 : Output Idle state 5 (OC5 output)

Refer to OIS1 bit

Bit 15 Reserved, must be kept at reset value.

Bit 14 OIS4 : Output Idle state 4 (OC4 output)

Refer to OIS1 bit

Bit 13 OIS3N : Output Idle state 3 (OC3N output)

Refer to OIS1N bit

RM0471 Rev 5 595/1202

631

Advanced-control timer (TIM1) RM0471

Bit 12 OIS3 : Output Idle state 3 (OC3 output)

Refer to OIS1 bit

Bit 11 OIS2N : Output Idle state 2 (OC2N output)

Refer to OIS1N bit

Bit 10 OIS2 : Output Idle state 2 (OC2 output)

Refer to OIS1 bit

Bit 9 OIS1N : Output Idle state 1 (OC1N output)

0: OC1N=0 after a dead-time when MOE=0

1: OC1N=1 after a dead-time when MOE=0

Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed

(LOCK bits in TIMx_BDTR register).

Bit 8 OIS1 : Output Idle state 1 (OC1 output)

0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0

1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0

Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed

(LOCK bits in TIMx_BDTR register).

Bit 7 TI1S : TI1 selection

0: The TIMx_CH1 pin is connected to TI1 input

1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)

Bits 6:4 MMS[2:0] : Master mode selection

These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:

000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.

001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter

Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).

010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.

011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred.

(TRGO).

100: Compare - OC1REFC signal is used as trigger output (TRGO)

101: Compare - OC2REFC signal is used as trigger output (TRGO)

110: Compare - OC3REFC signal is used as trigger output (TRGO)

111: Compare - OC4REFC signal is used as trigger output (TRGO)

Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

Bit 3 CCDS : Capture/compare DMA selection

0: CCx DMA request sent when CCx event occurs

1: CCx DMA requests sent when update event occurs

596/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Bit 2 CCUS : Capture/compare control update selection

0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only

1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

Note: This bit acts only on channels that have a complementary output.

Bit 1 Reserved, must be kept at reset value.

Bit 0 CCPC : Capture/compare preloaded control

0: CCxE, CCxNE and OCxM bits are not preloaded

1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on

TRGI, depending on the CCUS bit).

Note: This bit acts only on channels that have a complementary output.

19.4.3 TIM1 slave mode control register (TIM1_SMCR)

Address offset: 0x08

Reset value: 0x0000 0000

Res.

ETP rw

Res.

ECE rw

Res.

13 12

ETPS[1:0] rw rw

Res.

11 rw

Res.

ETF[3:0]

9 rw rw

Res.

8 rw

Res.

MSM rw

Res.

6 rw

TS[2:0]

20 rw

TS[4:3] rw

4 rw rw

Res.

OCCS rw

Res.

2 rw

SMS[2:0]

Res.

SMS[3] rw

0 rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bits 19:17 Reserved, must be kept at reset value.

Bit 15 ETP : External trigger polarity

This bit selects whether ETR or ETR is used for trigger operations

0: ETR is non-inverted, active at high level or rising edge.

1: ETR is inverted, active at low level or falling edge.

Bit 14 ECE : External clock enable

This bit enables External clock mode 2.

0: External clock mode 2 disabled

1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111).

It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111).

If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.

RM0471 Rev 5 597/1202

631

Advanced-control timer (TIM1) RM0471

Bits 13:12 ETPS[1:0] : External trigger prescaler

External trigger signal ETRP frequency must be at most 1/4 of f

CK_INT

frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.

00: Prescaler OFF

01: ETRP frequency divided by 2

10: ETRP frequency divided by 4

11: ETRP frequency divided by 8

Bits 11:8 ETF[3:0] : External trigger filter

This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:

0000: No filter, sampling is done at f

DTS

0001: f

0010: f

0011: f

0100: f

0101: f

0110: f

SAMPLING

DTS

/2, N=8

DTS

/4, N=6

0111: f

1000: f

1001: f

1010: f

1011: f

SAMPLING

CK_INT

, N=2

SAMPLING

CK_INT

, N=4

SAMPLING

CK_INT

, N=8

DTS

/2, N=6

DTS

/4, N=8

DTS

/8, N=6

DTS

/8, N=8

SAMPLING

DTS

/16, N=5

DTS

/16, N=6

1100: f

1101: f

1110: f

1111: f

SAMPLING

DTS

/16, N=8

SAMPLING

DTS

/32, N=5

SAMPLING

DTS

/32, N=6

SAMPLING

DTS

/32, N=8

Bit 7 MSM: Master/slave mode

0: No action

1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

Bits 21, 20, 6, 5, 4 TS[4:0]: Trigger selection

This bit-field selects the trigger input to be used to synchronize the counter.

00000: Internal Trigger 0 (ITR0)

00001: Internal Trigger 1 (ITR1)

00010: Internal Trigger 2 (ITR2)

00011: Internal Trigger 3 (ITR3)

00100: TI1 Edge Detector (TI1F_ED)

00101: Filtered Timer Input 1 (TI1FP1)

00110: Filtered Timer Input 2 (TI2FP2)

00111: External Trigger input (ETRF)

Others: Reserved

See Table 127: TIM1 internal trigger connection on page 599 for more details on ITRx

meaning for each Timer.

Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.

Bit 3 OCCS: OCREF clear selection

This bit is used to select the OCREF clear source.

0: OCREF_CLR_INT is connected to the OCREF_CLR input

1: OCREF_CLR_INT is connected to ETRF

598/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Bits 16, 2, 1, 0 SMS[3:0]: Slave mode selection

When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.

0000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal clock.

0001: Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level.

0010: Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level.

0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.

0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.

0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.

0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.

0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter.

Codes above 1000: Reserved.

Note: The gated mode must not be used if TI1F_ED is selected as the trigger input

(TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal.

Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.

Slave TIM

TIM1

Table 127. TIM1 internal trigger connection

ITR0 (TS = 00000) ITR1 (TS = 00001) ITR2 (TS = 00010) ITR3 (TS = 00011)

TIM2 TIM17 OC1

19.4.4 TIM1 DMA/interrupt enable register (TIM1_DIER)

Address offset: 0x0C

Reset value: 0x0000

Res.

14 13 12 11 10 9 8

TDE COMDE CC4DE CC3DE CC2DE CC1DE UDE rw rw rw rw rw rw rw

BIE rw

TIE rw

5 4 3 2 1

COMIE CC4IE CC3IE CC2IE CC1IE rw rw rw rw rw

UIE rw

RM0471 Rev 5 599/1202

631

Advanced-control timer (TIM1)

Bit 15 Reserved, must be kept at reset value.

Bit 14 TDE : Trigger DMA request enable

0: Trigger DMA request disabled

1: Trigger DMA request enabled

Bit 13 COMDE : COM DMA request enable

0: COM DMA request disabled

1: COM DMA request enabled

Bit 12 CC4DE : Capture/Compare 4 DMA request enable

0: CC4 DMA request disabled

1: CC4 DMA request enabled

Bit 11 CC3DE : Capture/Compare 3 DMA request enable

0: CC3 DMA request disabled

1: CC3 DMA request enabled

Bit 10 CC2DE : Capture/Compare 2 DMA request enable

0: CC2 DMA request disabled

1: CC2 DMA request enabled

Bit 9 CC1DE : Capture/Compare 1 DMA request enable

0: CC1 DMA request disabled

1: CC1 DMA request enabled

Bit 8 UDE : Update DMA request enable

0: Update DMA request disabled

1: Update DMA request enabled

Bit 7 BIE : Break interrupt enable

0: Break interrupt disabled

1: Break interrupt enabled

Bit 6 TIE : Trigger interrupt enable

0: Trigger interrupt disabled

1: Trigger interrupt enabled

Bit 5 COMIE : COM interrupt enable

0: COM interrupt disabled

1: COM interrupt enabled

Bit 4 CC4IE : Capture/Compare 4 interrupt enable

0: CC4 interrupt disabled

1: CC4 interrupt enabled

Bit 3 CC3IE : Capture/Compare 3 interrupt enable

0: CC3 interrupt disabled

1: CC3 interrupt enabled

RM0471

600/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Bit 2 CC2IE : Capture/Compare 2 interrupt enable

0: CC2 interrupt disabled

1: CC2 interrupt enabled

Bit 1 CC1IE : Capture/Compare 1 interrupt enable

0: CC1 interrupt disabled

1: CC1 interrupt enabled

Bit 0 UIE : Update interrupt enable

0: Update interrupt disabled

1: Update interrupt enabled

19.4.5 TIM1 status register (TIM1_SR)

Address offset: 0x10

Reset value: 0x0000 0000

Res.

18 17 16

Res.

CC6IF CC5IF rc_w0 rc_w0

13 12 11 10 9 8

SBIF CC4OF CC3OF CC2OF CC1OF B2IF

BIF

TIF

5 4

COMIF CC4IF

CC3IF

CC2IF

CC1IF

UIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 CC6IF : Compare 6 interrupt flag

Refer to CC1IF description (Note: Channel 6 can only be configured as output)

Bit 16 CC5IF : Compare 5 interrupt flag

Refer to CC1IF description (Note: Channel 5 can only be configured as output)

Bits 15:14 Reserved, must be kept at reset value.

Bit 13 SBIF : System Break interrupt flag

This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active.

This flag must be reset to re-start PWM operation.

0: No break event occurred.

1: An active level has been detected on the system break input. An interrupt is generated if

BIE=1 in the TIMx_DIER register.

Bit 12 CC4OF : Capture/Compare 4 overcapture flag

Refer to CC1OF description

Bit 11 CC3OF : Capture/Compare 3 overcapture flag

Refer to CC1OF description

Bit 10 CC2OF : Capture/Compare 2 overcapture flag

Refer to CC1OF description

RM0471 Rev 5 601/1202

631

Advanced-control timer (TIM1) RM0471

Bit 9 CC1OF : Capture/Compare 1 overcapture flag

This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’.

0: No overcapture has been detected.

1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set

Bit 8 B2IF : Break 2 interrupt flag

This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active.

0: No break event occurred.

1: An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register.

Bit 7 BIF : Break interrupt flag

This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.

0: No break event occurred.

1: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register.

Bit 6 TIF : Trigger interrupt flag

This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software.

0: No trigger event occurred.

1: Trigger interrupt pending.

Bit 5 COMIF : COM interrupt flag

This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE,

CCxNE, OCxM - have been updated). It is cleared by software.

0: No COM event occurred.

1: COM interrupt pending.

Bit 4 CC4IF : Capture/Compare 4 interrupt flag

Refer to CC1IF description

Bit 3 CC3IF : Capture/Compare 3 interrupt flag

Refer to CC1IF description

Bit 2 CC2IF : Capture/Compare 2 interrupt flag

Refer to CC1IF description

Bit 1 CC1IF : Capture/Compare 1 interrupt flag

This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only).

0: No compare match / No input capture occurred

1: A compare match or an input capture occurred.

If channel CC1 is configured as output : this flag is set when he content of the counter

TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of

TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in downcounting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description.

If channel CC1 is configured as input : this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).

602/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Bit 0 UIF : Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0: No update occurred.

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

– At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register.

– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register.

– When CNT is reinitialized by a trigger event (refer to

Section 19.4.3: TIM1 slave mode control register (TIM1_SMCR)

), if URS=0 and UDIS=0 in the TIMx_CR1 register.

Res.

Address offset: 0x14

Reset value: 0x0000

Res.

B2G w

BG w

TG w

5 4 3 2 1

COMG CC4G CC3G CC2G CC1G w w w w w

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 B2G : Break 2 generation

This bit is set by software in order to generate an event, it is automatically cleared by hardware.

0: No action

1: A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled.

Bit 7 BG : Break generation

This bit is set by software in order to generate an event, it is automatically cleared by hardware.

0: No action

1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or

DMA transfer can occur if enabled.

Bit 6 TG : Trigger generation

This bit is set by software in order to generate an event, it is automatically cleared by hardware.

0: No action

1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

Bit 5 COMG : Capture/Compare control update generation

This bit can be set by software, it is automatically cleared by hardware

0: No action

1: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated.

Note: This bit acts only on channels having a complementary output.

Bit 4 CC4G : Capture/Compare 4 generation

Refer to CC1G description

Bit 3 CC3G : Capture/Compare 3 generation

Refer to CC1G description

UG w

RM0471 Rev 5 603/1202

631

Advanced-control timer (TIM1) RM0471

Bit 2 CC2G : Capture/Compare 2 generation

Refer to CC1G description

Bit 1 CC1G : Capture/Compare 1 generation

This bit is set by software in order to generate an event, it is automatically cleared by hardware.

0: No action

1: A capture/compare event is generated on channel 1:

If channel CC1 is configured as output:

CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.

If channel CC1 is configured as input:

The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the

CC1IF flag was already high.

Bit 0 UG : Update generation

This bit can be set by software, it is automatically cleared by hardware.

0: No action

1: Reinitialize the counter and generates an update of the registers. The prescaler internal counter is also cleared (the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting).

19.4.7 TIM1 capture/compare mode register 1 [alternate]

(TIM1_CCMR1)

Address offset: 0x18

Reset value: 0x0000 0000

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding

CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode).

Input capture mode:

Res.

15 rw

14 13

IC2F[3:0] rw rw

12 rw

11 10

IC2PSC[1:0] rw rw

9 8

CC2S[1:0] rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 IC2F[3:0] : Input capture 2 filter

Refer to IC1F[3:0] description.

Bits 11:10 IC2PSC[1:0] : Input capture 2 prescaler

Refer to IC1PSC[1:0] description.

7 rw

IC1F[3:0]

5 rw rw

4 rw

3 2

IC1PSC[1:0] rw rw

1 0

CC1S[1:0] rw rw

604/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Bits 9:8 CC2S[1:0] : Capture/Compare 2 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC2 channel is configured as output

01: CC2 channel is configured as input, IC2 is mapped on TI2

10: CC2 channel is configured as input, IC2 is mapped on TI1

11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).

Bits 7:4 IC1F[3:0] : Input capture 1 filter

This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:

0000: No filter, sampling is done at f

DTS

0001: f

SAMPLING

0010: f

SAMPLING

0011: f

SAMPLING

CK_INT

, N=2

, N=4

, N=8

/2, N=6 0100: f

SAMPLING

0101: f

SAMPLING

0110: f

SAMPLING

DTS

0111: f

SAMPLING

DTS

/2, N=8

/4, N=6

/4, N=8

1000: f

SAMPLING

1001: f

SAMPLING

1010: f

SAMPLING

1011: f

SAMPLING

DTS

/8, N=6

/8, N=8

/16, N=5

/16, N=6

/16, N=8 1100: f

SAMPLING

1101: f

SAMPLING

1110: f

SAMPLING

DTS

1111: f

SAMPLING

DTS

/32, N=5

/32, N=6

/32, N=8

Bits 3:2 IC1PSC[1:0] : Input capture 1 prescaler

This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).

00: no prescaler, capture is done each time an edge is detected on the capture input

01: capture is done once every 2 events

10: capture is done once every 4 events

11: capture is done once every 8 events

Bits 1:0 CC1S[1:0] : Capture/Compare 1 Selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output

01: CC1 channel is configured as input, IC1 is mapped on TI1

10: CC1 channel is configured as input, IC1 is mapped on TI2

11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

19.4.8 TIM1 capture/compare mode register 1 [alternate]

(TIM1_CCMR1)

Address offset: 0x18

Reset value: 0x0000 0000

The same register can be used for output compare mode (this section) or for input capture mode (previous section). The direction of a channel is defined by configuring the

RM0471 Rev 5 605/1202

631

Advanced-control timer (TIM1) RM0471 corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently

(e.g. channel 1 in input capture mode and channel 2 in output compare mode).

Output compare mode:

Res.

OC2

CE rw

Res.

14 13

OC2M[2:0]

12 rw rw rw

Res.

OC2

PE rw

Res.

OC2

FE rw

25 24 23

Res.

OC2M[3] Res.

9 8

CC2S[1:0]

OC1

CE rw rw rw

Res.

6 5

OC1M[2:0] rw rw

4 rw

Res.

OC1

PE rw

Res.

OC1

FE rw

17 16

Res.

OC1M[3] rw

1 0

CC1S[1:0] rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bits 23:17 Reserved, must be kept at reset value.

Bit 15 OC2CE: Output Compare 2 clear enable

Refer to OC1CE description.

Bits 24, 14:12 OC2M[3:0] : Output Compare 2 mode

Refer to OC1M[3:0] description.

Bit 11 OC2PE : Output Compare 2 preload enable

Refer to OC1PE description.

Bit 10 OC2FE : Output Compare 2 fast enable

Refer to OC1FE description.

Bits 9:8 CC2S[1:0] : Capture/Compare 2 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC2 channel is configured as output

01: CC2 channel is configured as input, IC2 is mapped on TI2

10: CC2 channel is configured as input, IC2 is mapped on TI1

11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)

Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).

Bit 7 OC1CE: Output Compare 1 clear enable

0: OC1Ref is not affected by the ocref_clr_int signal

1: OC1Ref is cleared as soon as a High level is detected on ocref_clr_int signal

(OCREF_CLR input or ETRF input)

606/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Bits 16, 6:4 OC1M[3:0] : Output Compare 1 mode

These bits define the behavior of the output reference signal OC1REF from which OC1 and

OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.

0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).

0001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.

0100: Force inactive level - OC1REF is forced low.

0101: Force active level - OC1REF is forced high.

0110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as

TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).

0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as

TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as

TIMx_CNT>TIMx_CCR1 else inactive.

1000: Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update.

1001: Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in

PWM mode 2 and the channels becomes inactive again at the next update. In downcounting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update.

1010: Reserved,

1011: Reserved,

1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1.

OC1REFC is the logical OR between OC1REF and OC2REF.

1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2.

OC1REFC is the logical AND between OC1REF and OC2REF.

1110: Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1.

OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down.

1111: Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2.

OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down.

Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).

Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode.

Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated.

Note: The OC1M[3] bit is not contiguous, located in bit 16.

RM0471 Rev 5 607/1202

631

Advanced-control timer (TIM1) RM0471

Bit 3 OC1PE : Output Compare 1 preload enable

0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.

1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.

Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).

Bit 2 OC1FE : Output Compare 1 fast enable

This bit decreases the latency between a trigger event and a transition on the timer output.

It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger.

0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is

ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles.

1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode.

Bits 1:0 CC1S[1:0] : Capture/Compare 1 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output

01: CC1 channel is configured as input, IC1 is mapped on TI1

10: CC1 channel is configured as input, IC1 is mapped on TI2

11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

19.4.9 TIM1 capture/compare mode register 2 [alternate]

(TIM1_CCMR2)

Address offset: 0x1C

Reset value: 0x0000 0000

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding

Input capture mode:

Res.

15 rw

14 13

IC4F[3:0] rw rw

12 rw

11 10

IC4PSC[1:0] rw rw

9 8

CC4S[1:0] rw rw

7 rw

6 5

IC3F[3:0] rw rw

4 rw

3 2

IC3PSC[1:0] rw rw

1 0

CC3S[1:0] rw rw

608/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 IC4F[3:0] : Input capture 4 filter

Refer to IC1F[3:0] description.

Bits 11:10 IC4PSC[1:0] : Input capture 4 prescaler

Refer to IC1PSC[1:0] description.

Bits 9:8 CC4S[1:0] : Capture/Compare 4 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC4 channel is configured as output

01: CC4 channel is configured as input, IC4 is mapped on TI4

10: CC4 channel is configured as input, IC4 is mapped on TI3

11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER).

Bits 7:4 IC3F[3:0] : Input capture 3 filter

Refer to IC1F[3:0] description.

Bits 3:2 IC3PSC[1:0] : Input capture 3 prescaler

Refer to IC1PSC[1:0] description.

Bits 1:0 CC3S[1:0] : Capture/compare 3 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC3 channel is configured as output

01: CC3 channel is configured as input, IC3 is mapped on TI3

10: CC3 channel is configured as input, IC3 is mapped on TI4

11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).

Res.

OC4

CE rw

(TIM1_CCMR2)

Address offset: 0x1C

Reset value: 0x0000 0000

The same register can be used for output compare mode (this section) or for input capture mode (previous section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently

(e.g. channel 1 in input capture mode and channel 2 in output compare mode).

Output compare mode

Res.

14 13

OC4M[2:0]

12 rw rw rw

Res.

OC4

PE rw

OC4

FE rw

25 24 23

Res.

OC4M[3] Res.

9 8

CC4S[1:0]

OC3

CE rw rw rw

Res.

6 rw

OC3M[2:0] rw

4 rw

Res.

OC3

PE rw

Res.

OC3

FE rw

17 16

Res.

OC3M[3] rw

1 0

CC3S[1:0] rw rw

RM0471 Rev 5 609/1202

631

Advanced-control timer (TIM1) RM0471

Bits 31:25 Reserved, must be kept at reset value.

Bits 23:17 Reserved, must be kept at reset value.

Bit 15 OC4CE : Output compare 4 clear enable

Refer to OC1CE description.

Bits 24, 14:12 OC4M[3:0] : Output compare 4 mode

Refer to OC3M[3:0] description.

Bit 11 OC4PE : Output compare 4 preload enable

Refer to OC1PE description.

Bit 10 OC4FE : Output compare 4 fast enable

Refer to OC1FE description.

Bits 9:8 CC4S[1:0] : Capture/Compare 4 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC4 channel is configured as output

01: CC4 channel is configured as input, IC4 is mapped on TI4

10: CC4 channel is configured as input, IC4 is mapped on TI3

11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER).

Bit 7 OC3CE: Output compare 3 clear enable

Refer to OC1CE description.

Bits 16, 6:4 OC3M[3:0] : Output compare 3 mode

Refer to OC1M[3:0] description.

Bit 3 OC3PE : Output compare 3 preload enable

Refer to OC1PE description.

Bit 2 OC3FE : Output compare 3 fast enable

Refer to OC1FE description.

Bits 1:0 CC3S[1:0] : Capture/Compare 3 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC3 channel is configured as output

01: CC3 channel is configured as input, IC3 is mapped on TI3

10: CC3 channel is configured as input, IC3 is mapped on TI4

11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).

610/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

19.4.11 TIM1 capture/compare enable register

(TIM1_CCER)

Address offset: 0x20

Reset value: 0x0000 0000

Res.

15 14

CC4NP Res.

Res.

21 20

CC6P CC6E rw

5 rw

Res.

17 16

CC5P CC5E rw

1 rw

0 13 12 11 10 9 8 7 6 3 2

CC4P CC4E CC3NP CC3NE CC3P CC3E CC2NP CC2NE CC2P CC2E CC1NP CC1NE CC1P CC1E rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 CC6P : Capture/Compare 6 output polarity

Refer to CC1P description

Bit 20 CC6E : Capture/Compare 6 output enable

Refer to CC1E description

Bits 19:18 Reserved, must be kept at reset value.

Bit 17 CC5P : Capture/Compare 5 output polarity

Refer to CC1P description

Bit 16 CC5E : Capture/Compare 5 output enable

Refer to CC1E description

Bit 15 CC4NP : Capture/Compare 4 complementary output polarity

Refer to CC1NP description

Bit 14 Reserved, must be kept at reset value.

Bit 13 CC4P : Capture/Compare 4 output polarity

Refer to CC1P description

Bit 12 CC4E : Capture/Compare 4 output enable

Refer to CC1E description

Bit 11 CC3NP : Capture/Compare 3 complementary output polarity

Refer to CC1NP description

Bit 10 CC3NE : Capture/Compare 3 complementary output enable

Refer to CC1NE description

Bit 9 CC3P : Capture/Compare 3 output polarity

Refer to CC1P description

Bit 8 CC3E : Capture/Compare 3 output enable

Refer to CC1E description

Bit 7 CC2NP : Capture/Compare 2 complementary output polarity

Refer to CC1NP description

Bit 6 CC2NE : Capture/Compare 2 complementary output enable

Refer to CC1NE description

RM0471 Rev 5 611/1202

631

Advanced-control timer (TIM1) RM0471

Bit 5 CC2P : Capture/Compare 2 output polarity

Refer to CC1P description

Bit 4 CC2E : Capture/Compare 2 output enable

Refer to CC1E description

Bit 3 CC1NP : Capture/Compare 1 complementary output polarity

CC1 channel configured as output :

0: OC1N active high.

1: OC1N active low.

CC1 channel configured as input :

This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description.

Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (channel configured as output).

On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the

TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated.

Bit 2 CC1NE : Capture/Compare 1 complementary output enable

0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.

1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI,

OSSR, OIS1, OIS1N and CC1E bits.

On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the

TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated.

Bit 1 CC1P : Capture/Compare 1 output polarity

0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)

1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)

When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations.

CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge

(capture or trigger operations in reset, external clock or trigger mode),

TIxFP1 is not inverted (trigger operation in gated mode or encoder mode).

CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge

(capture or trigger operations in reset, external clock or trigger mode),

TIxFP1 is inverted (trigger operation in gated mode or encoder mode).

CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode.

CC1NP=1, CC1P=0: The configuration is reserved, it must not be used.

Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).

On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated.

612/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Bit 0 CC1E : Capture/Compare 1 output enable

0: Capture mode disabled / OC1 is not active (see below)

1: Capture mode enabled / OC1 signal is output on the corresponding output pin

When CC1 channel is configured as output , the OC1 level depends on MOE, OSSI,

OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to Table 128

for details.

Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated.

Table 128. Output control bits for complementary OCx and OCxN channels with break feature

Control bits Output states

(1)

MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state OCxN output state

1 X

Output disabled (not driven by the timer: Hi-Z)

OCx=0, OCxN=0

Output disabled (not driven by the timer: Hi-Z)

OCx=0

OCxREF + Polarity

OCxN = OCxREF xor CCxNP

OCxREF + Polarity

OCx=OCxREF xor CCxP

Output Disabled (not driven by the timer: Hi-Z)

OCxN=0

OCREF + Polarity + deadtime

Off-State (output enabled with inactive state)

OCx=CCxP

Complementary to OCREF (not

OCREF) + Polarity + dead-time

OCxREF + Polarity

OCxN = OCxREF x or CCxNP

OCxREF + Polarity

OCx=OCxREF xor CCxP

Off-State (output enabled with inactive state)

OCxN=CCxNP

Output disabled (not driven by the timer: Hi-Z).

Off-State (output enabled with inactive state)

Asynchronously: OCx=CCxP, OCxN=CCxNP (if BRK or

BRK2 is triggered).

Then (this is valid only if BRK is triggered), if the clock is present: OCx=OISx and OCxN=OISxN after a dead-time, assuming that OISx and OISxN do not correspond to OCX and OCxN both in active state (may cause a short circuit when driving switches in half-bridge configuration).

Note : BRK2 can only be used if OSSI = OSSR = 1.

1. When both outputs of a channel are not used (control taken over by GPIO), the OISx, OISxN, CCxP and CCxNP bits must be kept cleared.

Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels depends on the OCx and OCxN channel state and the GPIO registers.

RM0471 Rev 5 613/1202

631

Advanced-control timer (TIM1) RM0471

UIF

CPY r

Address offset: 0x24

Reset value: 0x0000 0000

Res.

14 rw

13 rw

12 rw

11 rw

10 rw

9 rw

8 7

CNT[15:0] rw rw

6 rw

5 rw

4 rw

3 rw

2 rw

1 rw

0 rw

Bit 31 UIFCPY : UIF copy

This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0.

Bits 30:16 Reserved, must be kept at reset value.

Bits 15:0 CNT[15:0] : Counter value

15 rw

Address offset: 0x28

Reset value: 0x0000

14 13 12 11 10 9 8 7

PSC[15:0] rw rw

6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 PSC[15:0] : Prescaler value

The counter clock frequency (CK_CNT) is equal to f

CK_PSC

/ (PSC[15:0] + 1).

PSC contains the value to be loaded in the active prescaler register at each update event

(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).

19.4.14 TIM1 auto-reload register (TIM1_ARR)

Address offset: 0x2C

Reset value: 0xFFFF

15 rw

14 13 12 11 10 9 8 7

ARR[15:0] rw rw

6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 ARR[15:0] : Auto-reload value

ARR is the value to be loaded in the actual auto-reload register.

Refer to the

Section 19.3.1: Time-base unit on page 535 for more details about ARR update

and behavior.

The counter is blocked while the auto-reload value is null.

614/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

19.4.15 TIM1 repetition counter register (TIM1_RCR)

Address offset: 0x30

Reset value: 0x0000

15 rw

14 13 12 11 10 9 8 7

REP[15:0] rw rw

6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 REP[15:0] : Repetition counter value

These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable.

Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event.

It means in PWM mode (REP+1) corresponds to: the number of PWM periods in edge-aligned mode the number of half PWM period in center-aligned mode.

19.4.16 TIM1 capture/compare register 1 (TIM1_CCR1)

Address offset: 0x34

Reset value: 0x0000

15 rw

14 13 12 11 10 9 8 7

CCR1[15:0] rw rw

6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CCR1[15:0] : Capture/Compare 1 value

If channel CC1 is configured as output : CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).

It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register

(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter

TIMx_CNT and signaled on OC1 output.

If channel CC1 is configured as input : CR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed.

RM0471 Rev 5 615/1202

631

Advanced-control timer (TIM1) RM0471

19.4.17 TIM1 capture/compare register 2 (TIM1_CCR2)

Address offset: 0x38

Reset value: 0x0000

15 rw

14 13 12 11 10 9 8 7

CCR2[15:0] rw rw

6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CCR2[15:0] : Capture/Compare 2 value

If channel CC2 is configured as output : CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).

It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register

(bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter

TIMx_CNT and signaled on OC2 output.

If channel CC2 is configured as input : CCR2 is the counter value transferred by the last input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be programmed.

19.4.18 TIM1 capture/compare register 3 (TIM1_CCR3)

Address offset: 0x3C

Reset value: 0x0000

15 rw

14 13 12 11 10 9 8 7

CCR3[15:0] rw rw

6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CCR3[15:0] : Capture/Compare value

If channel CC3 is configured as output : CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).

It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register

(bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter

TIMx_CNT and signalled on OC3 output.

If channel CC3 is configured as input : CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed.

616/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

19.4.19 TIM1 capture/compare register 4 (TIM1_CCR4)

Address offset: 0x40

Reset value: 0x0000

15 rw

14 13 12 11 10 9 8 7

CCR4[15:0] rw rw

6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CCR4[15:0] : Capture/Compare value

If channel CC4 is configured as output : CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).

It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register

(bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter

TIMx_CNT and signalled on OC4 output.

If channel CC4 is configured as input : CCR4 is the counter value transferred by the last input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be programmed.

19.4.20 TIM1 break and dead-time register

(TIM1_BDTR)

Address offset: 0x44

Reset value: 0x0000 0000

Res.

MOE rw

Note:

30 29 28

Res.

BK2BID BKBID

AOE rw rw

BKP rw rw

BKE rw

BK2

DSRM rw

OSSR rw

DSRM rw

OSSI rw

25 24

BK2P BK2E rw rw

9 8

LOCK[1:0] rw rw

23 rw

22 21

BK2F[3:0] rw

6 rw

20 19 rw rw

4 3 rw

DTG[7:0] rw

18 17

BKF[3:0] rw

2 rw

16 rw

0 rw rw rw rw rw rw

As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0],

AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the

TIMx_BDTR register.

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 BK2BID : Break2 bidirectional

Refer to BKBID description

RM0471 Rev 5 617/1202

631

Advanced-control timer (TIM1) RM0471

Bit 28 BKBID : Break Bidirectional

0: Break input BRK in input mode

1: Break input BRK in bidirectional mode

In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the

Break input to indicate an internal break event to external devices.

Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

Bit 27 BK2DSRM : Break2 Disarm

Refer to BKDSRM description

Bit 26 BKDSRM : Break Disarm

0: Break input BRK is armed

1: Break input BRK is disarmed

This bit is cleared by hardware when no break source is active.

The BKDSRM bit must be set by software to release the bidirectional output control (opendrain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared.

Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

Bit 25 BK2P : Break 2 polarity

0: Break input BRK2 is active low

1: Break input BRK2 is active high

Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

Bit 24 BK2E : Break 2 enable

Note: The must only be used with OSSR = OSSI = 1.

Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in

TIMx_BDTR register).

Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

618/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Bits 23:20 BK2F[3:0] : Break 2 filter

This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:

0000: No filter, BRK2 acts asynchronously

0001: f

SAMPLING

0010: f

SAMPLING

0011: f

SAMPLING

0100: f

SAMPLING

CK_INT

DTS

, N=2

, N=4

, N=8

/2, N=6

/2, N=8 0101: f

SAMPLING

0110: f

SAMPLING

DTS

0111: f

SAMPLING

DTS

/4, N=6

/4, N=8

1000: f

SAMPLING

DTS

/8, N=6

/8, N=8 1001: f

SAMPLING

1010: f

SAMPLING

1011: f

SAMPLING

1100: f

SAMPLING

DTS

/16, N=5

/16, N=6

/16, N=8

/32, N=5 1101: f

SAMPLING

1110: f

SAMPLING

1111: f

SAMPLING

DTS

/32, N=6

/32, N=8

Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in

TIMx_BDTR register).

Bits 19:16 BKF[3:0] : Break filter

This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:

0000: No filter, BRK acts asynchronously

0001: f

SAMPLING

0010: f

SAMPLING

0011: f

SAMPLING

0100: f

SAMPLING

CK_INT

DTS

, N=2

, N=4

, N=8

/2, N=6

/2, N=8 0101: f

SAMPLING

0110: f

SAMPLING

DTS

0111: f

SAMPLING

DTS

/4, N=6

/4, N=8

1000: f

SAMPLING

DTS

/8, N=6

/8, N=8 1001: f

SAMPLING

1010: f

SAMPLING

1011: f

SAMPLING

1100: f

SAMPLING

DTS

/16, N=5

/16, N=6

/16, N=8

/32, N=5 1101: f

SAMPLING

1110: f

SAMPLING

1111: f

SAMPLING

DTS

/32, N=6

/32, N=8

Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in

TIMx_BDTR register).

RM0471 Rev 5 619/1202

631

Advanced-control timer (TIM1) RM0471

Bit 15 MOE : Main output enable

This bit is cleared asynchronously by hardware as soon as one of the break inputs is active

(BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output.

0: In response to a break 2 event. OC and OCN outputs are disabled

In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit.

1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in

TIMx_CCER register).

See OC/OCN enable description for more details (

Section 19.4.11: TIM1 capture/compare enable register (TIM1_CCER)

Bit 14 AOE : Automatic output enable

0: MOE can be set only by software

1: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Bit 13 BKP : Break polarity

0: Break input BRK is active low

1: Break input BRK is active high

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

Bit 12 BKE : Break enable

This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per

Figure 158: Break and Break2 circuitry overview

0: Break function disabled

1: Break function enabled

Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in

TIMx_BDTR register).

Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

Bit 11 OSSR : Off-state selection for Run mode

This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer.

See OC/OCN enable description for more details (

Section 19.4.11: TIM1 capture/compare enable register (TIM1_CCER)

0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state).

1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer).

Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).

620/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Bit 10 OSSI : Off-state selection for Idle mode

This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs.

See OC/OCN enable description for more details (

Section 19.4.11: TIM1 capture/compare enable register (TIM1_CCER)

0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state).

1: When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output.

Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).

Bits 9:8 LOCK[1:0] : Lock configuration

These bits offer a write protection against software errors.

00: LOCK OFF - No bit is write protected.

01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and B K2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0],

AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits in TIMx_BDTR register can no longer be written.

10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.

11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in

TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.

Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.

Bits 7:0 DTG[7:0] : Dead-time generator setup

This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration.

DTG[7:5] = 0xx => DT = DTG[7:0] x t

DTG

with t

DTG

DTG[7:5] = 10x => DT = (64 + DTG[5:0]) x t

DTG

DTG[7:5] = 110 => DT = (32 + DTG[4:0]) x t

DTG

DTG[7:5] = 111 => DT = (32 + DTG[4:0]) x t

DTG

Example if t

DTS

= t

DTS

with t

DTG

= 2 x t

DTS

= 8 x t

DTS

= 16 x t

DTS

= 125 ns (8 MHz), dead-time possible values are:

0 to 15875 ns by 125 ns steps,

16 μ s to 31750 ns by 250 ns steps,

32 μ s to 63 μ s by 1 μ s steps,

64 μ s to 126 μ s by 2 μ s steps

Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed

(LOCK bits in TIMx_BDTR register).

19.4.21 TIM1 DMA control register (TIM1_DCR)

Address offset: 0x48

Reset value: 0x0000

Res.

12 11 rw

DBL[4:0] rw

9 rw

8 rw rw

Bits 15:13 Reserved, must be kept at reset value.

Res.

4 rw

3 rw

DBA[4:0] rw

1 rw

0 rw

RM0471 Rev 5 621/1202

631

Advanced-control timer (TIM1) RM0471

Bits 12:8 DBL[4:0] : DMA burst length

This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below).

00000: 1 transfer

00001: 2 transfers

00010: 3 transfers

...

10001: 18 transfers

Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIMx_CR1.

– If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation:

(TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL

In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA

According to the configuration of the DMA Data Size, several cases may occur:

– If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers.

– If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on.

So with the transfer Timer, one also has to specify the size of data transferred by DMA.

Bits 7:5 Reserved, must be kept at reset value.

Bits 4:0 DBA[4:0] : DMA base address

This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register.

Example:

00000: TIMx_CR1,

00001: TIMx_CR2,

00010: TIMx_SMCR,

...

19.4.22 TIM1 DMA address for full transfer

(TIM1_DMAR)

Address offset: 0x4C

Reset value: 0x0000 0000

31 30 29 28 27 26 25 rw

15 rw rw

14 rw rw

13 rw rw

12 rw rw

11 rw rw

10 rw rw

9 rw

24 23

DMAB[31:16] rw rw

8 7

DMAB[15:0] rw rw

22 rw

6 rw

21 rw

5 rw

20 rw

4 rw

19 rw

3 rw

18 rw

2 rw

17 rw

1 rw

16 rw

0 rw

622/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Bits 31:0 DMAB[31:0] : DMA register for burst accesses

A read or write operation to the DMAR register accesses the register located at the address

(TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).

19.4.23 TIM1 option register 1 (TIM1_OR1)

Address offset: 0x50

Reset value: 0x0000 0000

Res.

TI1_

RMP rw

Res.

1 0

TIM1_ETR_

ADC_RMP[1:0] rw rw

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 TI1_RMP : Input Capture 1 remap

0: TIM1 input capture 1 is connected to I/O

Others: Reserved

Bits 3:2 Reserved, must be kept at reset value.

Bits 1:0 TIM1_ETR_ADC_RMP[1:0] : TIM1_ETR_ADC remapping capability

00: TIM1_ETR is not connected to ADC AWDx (must be selected when the ETR comes from the ETR input pin)

01: TIM1_ETR is connected to ADC AWD1

10: TIM1_ETR is connected to ADC AWD2

11: TIM1_ETR is connected to ADC AWD3

Note: ADC AWDx sources are ‘ORed’ with the TIM1_ETR input signals. When ADC AWDx is used, it is necessary to make sure that the corresponding TIM1_ETR input pin is not enabled in the alternate function controller.

19.4.24 TIM1 capture/compare mode register 3

(TIM1_CCMR3)

Address offset: 0x54

Reset value: 0x0000 0000

The channels 5 and 6 can only be configured in output.

Output compare mode:

RM0471 Rev 5 623/1202

631

Advanced-control timer (TIM1) RM0471

Res.

OC6

CE rw

Res.

14 13

OC6M[2:0]

12 rw rw rw

Res.

OC6

PE rw

Res.

OC6FE

25 24 23

Res.

OC6M[3] Res.

9 8

Res.

OC5

CE rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bits 23:17 Reserved, must be kept at reset value.

Bit 15 OC6CE : Output compare 6 clear enable

Refer to OC1CE description.

Bits 24, 14, 13, 12 OC6M[3:0] : Output compare 6 mode

Refer to OC1M description.

Bit 11 OC6PE : Output compare 6 preload enable

Refer to OC1PE description.

Bit 10 OC6FE : Output compare 6 fast enable

Refer to OC1FE description.

Bits 9:8 Reserved, must be kept at reset value.

Bit 7 OC5CE: Output compare 5 clear enable

Refer to OC1CE description.

Bits 16, 6, 5, 4 OC5M[3:0] : Output compare 5 mode

Refer to OC1M description.

Bit 3 OC5PE : Output compare 5 preload enable

Refer to OC1PE description.

Bit 2 OC5FE : Output compare 5 fast enable

Refer to OC1FE description.

Bits 1:0 Reserved, must be kept at reset value.

Res.

OC5M[2:0]

Res.

OC5M[3] rw

OC5PE OC5FE Res.

Res.

rw rw rw rw rw

19.4.25 TIM1 capture/compare register 5 (TIM1_CCR5)

Address offset: 0x58

Reset value: 0x0000 0000

31 30 29 28

GC5C3 GC5C2 GC5C1 Res.

15 rw

14 rw

13 12

Res.

5 rw rw rw rw rw rw rw

8 7

CCR5[15:0] rw rw rw rw

Res.

4 rw

Res.

3 rw

2 rw

1 rw

0 rw

624/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Bit 31 GC5C3 : Group Channel 5 and Channel 3

Distortion on Channel 3 output:

0: No effect of OC5REF on OC3REFC

1: OC3REFC is the logical AND of OC3REFC and OC5REF

This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2).

Note: it is also possible to apply this distortion on combined PWM signals.

Bit 30 GC5C2 : Group Channel 5 and Channel 2

Distortion on Channel 2 output:

0: No effect of OC5REF on OC2REFC

1: OC2REFC is the logical AND of OC2REFC and OC5REF

This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1).

Note: it is also possible to apply this distortion on combined PWM signals.

Bit 29 GC5C1 : Group Channel 5 and Channel 1

Distortion on Channel 1 output:

0: No effect of OC5REF on OC1REFC5

1: OC1REFC is the logical AND of OC1REFC and OC5REF

This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1).

Note: it is also possible to apply this distortion on combined PWM signals.

Bits 28:16 Reserved, must be kept at reset value.

Bits 15:0 CCR5[15:0] : Capture/Compare 5 value

CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value).

It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register

(bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter

TIMx_CNT and signaled on OC5 output.

19.4.26 TIM1 capture/compare register 6 (TIM1_CCR6)

Address offset: 0x5C

Reset value: 0x0000

15 rw

14 13 12 11 10 9 8 7

CCR6[15:0] rw rw

6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CCR6[15:0] : Capture/Compare 6 value

CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value).

It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register

(bit OC6PE). Else the preload value is copied in the active capture/compare 6 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter

TIMx_CNT and signaled on OC6 output.

RM0471 Rev 5 625/1202

631

Advanced-control timer (TIM1) RM0471

Res.

15 14

ETRSEL[1:0] rw rw

Note:

Address offset: 0x60

Reset value: 0x0000 0001

Res.

10 9 8

Res.

BKINP Res.

Res.

17 16

ETRSEL[3:2] rw

1 rw

Res.

BKINE rw

Bits 31:18 Reserved, must be kept at reset value.

Bits 17:14 ETRSEL[3:0] : ETR source selection

These bits select the ETR input source.

0000: ETR legacy mode

Others: Reserved

Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Bits 13:10 Reserved, must be kept at reset value.

Bit 9 BKINP : BRK BKIN input polarity

This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit.

0: BKIN input polarity is not inverted (active low if BKP=0, active high if BKP=1)

1: BKIN input polarity is inverted (active high if BKP=0, active low if BKP=1)

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Bits 8:1 Reserved, must be kept at reset value.

Bit 0 BKINE : BRK BKIN input enable

This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is

‘ORed’ with the other BRK sources.

0: BKIN input disabled

1: BKIN input enabled

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Refer to Figure 137: TIM1 ETR input circuitry

and to

Figure 158: Break and Break2 circuitry overview

626/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Address offset: 0x64

Reset value: 0x0000 0001

Res.

23 22 21

Res.

Note:

BK2

INP rw

Res.

7 6 5

Res.

BK2INE rw

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 BK2INP : BRK2 BKIN2 input polarity

This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit.

0: BKIN2 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1)

1: BKIN2 input polarity is inverted (active high if BK2P=0, active low if BK2P=1)

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Bits 8:1 Reserved, must be kept at reset value.

Bit 0 BK2INE : BRK2 BKIN input enable

This bit enables the BKIN2 alternate function input for the timer’s BRK2 input. BKIN2 input is

‘ORed’ with the other BRK2 sources.

0: BKIN2 input disabled

1: BKIN2 input enabled

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Refer to Figure 158: Break and Break2 circuitry overview .

19.4.29 TIM1 timer input selection register (TIM1_TISEL)

Address offset: 0x68

Reset value: 0x0000 0000

Res.

27 rw

11 rw

26 25

TI4SEL[3:0] rw rw

10 9

TI2SEL[3:0] rw rw

24 rw

8 rw

Res.

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:24 TI4SEL[3:0] : selects TI4[0] to TI4[15] input

0000: TIM1_CH4 input

Others: Reserved

Res.

19 rw

3 rw

18 17

TI3SEL[3:0] rw rw

2 1

TI1SEL[3:0] rw rw

16 rw

0 rw

RM0471 Rev 5 627/1202

631

Advanced-control timer (TIM1)

Bits 23:20 Reserved, must be kept at reset value.

Bits 19:16 TI3SEL[3:0] : selects TI3[0] to TI3[15] input

0000: TIM1_CH3 input

Others: Reserved

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:8 TI2SEL[3:0] : selects TI2[0] to TI2[15] input

0000: TIM1_CH2 input

Others: Reserved

Bits 7:4 Reserved, must be kept at reset value.

Bits 3:0 TI1SEL[3:0] : selects TI1[0] to TI1[15] input

0000: TIM1_CH1 input

Others: Reserved

RM0471

628/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

19.4.30 TIM1 register map

TIM1 registers are mapped as 16-bit addressable registers as described in the table below:

Offset

Register name

Table 129. TIM1 register map and reset values

CKD

[1:0]

CMS

[1:0]

0x00

TIM1_CR1

0x04

0x08

Reset value

TIM1_CR2

Reset value

TIM1_SMCR

Reset value

MMS2[3:0]

0 0 0 0

[4:3]

0 0

0 0 0 0 0 0 0 0 0 0 0

MMS

[2:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0

ETP

[1:0]

ETF[3:0] TS[2:0]

SMS[2:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM1_DIER

0x0C

Reset value

0x10

TIM1_SR

Reset value

TIM1_EGR

0x14

0x18

0x1C

Reset value

TIM1_CCMR1

Output

Compare mode

Reset value

TIM1_CCMR1

Input Capture mode

Reset value

TIM1_CCMR2

Output

Compare mode

Reset value

TIM1_CCMR2

Input Capture mode

Reset value

0x20

TIM1_CCER

Reset value

0 0

OC2M

[2:0]

0 0 0 0 0 0 0 0 0

CC2

[1:0]

OC1M

[2:0]

CC1

[1:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IC2F[3:0]

IC2

PSC

[1:0]

CC2

[1:0]

IC1F[3:0]

IC1

PSC

[1:0]

CC1

[1:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OC4M

[2:0]

CC4

[1:0]

OC3M

[2:0]

CC3

[1:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IC4F[3:0]

IC4

PSC

[1:0]

CC4

[1:0]

IC3F[3:0]

IC3

PSC

[1:0]

CC3

[1:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0

RM0471 Rev 5 629/1202

631

Advanced-control timer (TIM1) RM0471

Offset

Register name

TIM1_CNT

Table 129. TIM1 register map and reset values (continued)

CNT[15:0]

0x24

0x28

0x2C

0x30

0x34

0x38

0x3C

0x40

0x44

0x48

0x4C

Reset value

TIM1_PSC

Reset value

TIM1_ARR

Reset value

TIM1_RCR

Reset value

TIM1_CCR1

Reset value

TIM1_CCR2

Reset value

TIM1_CCR3

Reset value

TIM1_CCR4

Reset value

TIM1_BDTR

Reset value

TIM1_DCR

Reset value

TIM1_DMAR

Reset value

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PSC[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ARR[15:0]

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

REP[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCR1[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCR2[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCR3[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCR4[15:0]

BK2F[3:0] BKF[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LOC

[1:0]

DT[7:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DBL[4:0]

0 0 0 0 0

DBA[4:0]

0 0 0 0 0

DMAB[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x50

TIM1_OR1

Reset value 0 0 0

630/1202 RM0471 Rev 5

RM0471 Advanced-control timer (TIM1)

Offset

0x54

Register name

TIM1_CCMR3

Output

Compare mode

Reset value

Table 129. TIM1 register map and reset values (continued)

OC6M

[2:0]

0 0 0 0 0 0 0

OC5M

[2:0]

0 0 0 0 0 0

CCR5[15:0]

0x58

0x5C

0x60

TIM1_CCR5

Reset value

TIM1_CCR6

Reset value

0 0 0

TIM1_AF1

Reset value

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCR6[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Res

ETRSEL

[3:0]

0 0 0 0 0 1

0x64

0x68

TIM1_AF2

Reset value

TIM1_TISEL

Reset value

TI4SEL[3:0]

0 0 0 0

TI3SEL[3:0]

0 0 0 0

TI2SEL[3:0]

0 0 0 0

TI1SEL[3:0]

0 0 0 0

Refer to Section 2.2 on page 55

for the register boundary addresses.

RM0471 Rev 5 631/1202

631

General-purpose timer (TIM2)

20 General-purpose timer (TIM2)

RM0471

The general-purpose timer TIM2 consists of a 32-bit auto-reload counter driven by a programmable prescaler.

The timer may be used for a variety of purposes, including measuring the pulse lengths of input signals ( input capture ) or generating output waveforms ( output compare and PWM ).

Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers.

20.2 TIM2 main features

 32-bit up, down, up/down auto-reload counter.

 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535.

 Up to 4 independent channels for:

– Input capture

– Output compare

– PWM generation (Edge- and Center-aligned modes)

– One-pulse mode output

 Synchronization circuit to control the timer with external signals and to interconnect several timers.

 Interrupt/DMA generation on the following events:

– Update: counter overflow/underflow, counter initialization (by software or internal/external trigger)

– Trigger event (counter start, stop, initialization or count by internal/external trigger)

– Input capture

– Output compare

 Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes

 Trigger input for external clock or cycle-by-cycle current management

632/1202 RM0471 Rev 5

RM0471 General-purpose timer (TIM2)

Figure 175. General-purpose timer block diagram

TIMx_ETR

ETR

From RCC

Internal clock (CK_INT)

Polarity selection & edge detector & prescaler

ETRP

Input filter

ITR[0..15]

ITR

TRC

TI1F_ED

ETRF

Trigger controller

TRGO to other timers to peripherals

TRG

TRGI

Slave controller mode

Reset, enable, count

TI1FP1

TI2FP2

Encoder interface

TIMx_CH1

TI1[0]

TI1[1..15]

TIMx_CH2

TI2[0]

TI2[1..15]

TIMx_CH3

TI3[0]

TI3[1..15]

TIMx_CH4

TI4[0]

TI4[1..15]

XOR

TI1

Input filter & edge detector

TI1FP1

TI1FP2

TRC

CK_PSC

IC1

PSC prescaler

Prescaler

Auto-reload register

Stop, clear or up/down

CK_CNT

CC1I

IC1PS

+/CNT counter

Capture/Compare 1 register

CC1I

OC1REF

TI2

Input filter & edge detector

TI2FP1

TI2FP2

TRC

CC2I

IC2

Prescaler

IC2PS

Capture/Compare 2 register

CC2I

OC2REF

CC3I

TI3

Input filter & edge detector

TI3FP3

TI3FP4

TRC

IC3

Prescaler

IC3PS

Capture/Compare 3 register

CC3I

OC3REF

TI4

Input filter &

TI4FP3 edge detector

TI4FP4

TRC

CC4I

IC4

Prescaler

IC4PS

Capture/Compare 4 register

CC4I

OC4REF

ETRF

Output control

OC1

TIMx_CH1

Output control

OC2

OC3

OC4

TIMx_CH2

TIMx_CH3

TIMx_CH4

Notes:

Reg

Preload registers transferred to active registers on U event according to control bit

Event

Interrupt & DMA output

MSv40927V4

RM0471 Rev 5 633/1202

702

General-purpose timer (TIM2)

20.3 TIM2 functional description

RM0471

The main block of the programmable timer is a 32-bit counter with its related auto-reload register. The counter can count up, down or both up and down but also down or both up and down. The counter clock can be divided by a prescaler.

The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

 Counter Register (TIMx_CNT)

 Prescaler Register (TIMx_PSC)

 Auto-Reload Register (TIMx_ARR)

TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration.

Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit/32-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.

Figure 176 and Figure 177 give some examples of the counter behavior when the prescaler

ratio is changed on the fly:

634/1202 RM0471 Rev 5

RM0471 General-purpose timer (TIM2)

Figure 176. Counter timing diagram with prescaler division change from 1 to 2

CK_PSC

CEN

Timerclock = CK_CNT

Counter register

Update event (UEV)

Prescaler control register

F8 F9 FA FB

Write a new value in TIMx_PSC

Prescaler buffer

FC 00 01

02 03

Prescaler counter

0 0 1 0 1 0 1 0 1

MS31076V2

Figure 177. Counter timing diagram with prescaler division change from 1 to 4

CK_PSC

CEN

Timerclock = CK_CNT

Counter register

Update event (UEV)

F7 F8 F9

Prescaler control register

Write a new value in TIMx_PSC

Prescaler buffer

Prescaler counter

FA FB FC 00

0 1 2 3 0 1 2 3

MS31077V2

RM0471 Rev 5 635/1202

702

General-purpose timer (TIM2) RM0471

Upcounting mode

In upcounting mode, the counter counts from 0 to the auto-reload value (content of the

TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

An Update event can be generated at each counter overflow or by setting the UG bit in the

TIMx_EGR register (by software or by using the slave mode controller).

The UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register.

This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

 The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register)

 The auto-reload shadow register is updated with the preload value (TIMx_ARR)

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.

Figure 178. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31078V2

636/1202 RM0471 Rev 5

RM0471 General-purpose timer (TIM2)

Figure 179. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035 0036 0000 0001 0002 0003

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Figure 180. Counter timing diagram, internal clock divided by 4

MS31079V2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

0035 0036 0000 0001

MS31080V2

RM0471 Rev 5 637/1202

702

General-purpose timer (TIM2)

Figure 181. Counter timing diagram, internal clock divided by N

RM0471

CK_PSC

Timerclock = CK_CNT

Counter register 1F 20 00

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31081V2

Figure 182. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register

Counter overflow

31 32 33 34 35 36 00 01 02 03 04 05 06 07

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload register

Write a new value in TIMx_ARR

MS31082V2

638/1202 RM0471 Rev 5

RM0471 General-purpose timer (TIM2)

Figure 183. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload register

F5 36

Auto-reload shadow register

F5 36

Write a new value in TIMx_ARR

MS31083V2

Downcounting mode

In downcounting mode, the counter counts from the auto-reload value (content of the

TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event.

An Update event can be generate at each counter underflow or by setting the UG bit in the

TIMx_EGR register (by software or by using the slave mode controller)

However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change).

In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the

UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or

DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

 The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).

 The auto-reload active register is updated with the preload value (content of the

TIMx_ARR register). Note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one.

RM0471 Rev 5 639/1202

702

General-purpose timer (TIM2) RM0471

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.

Figure 184. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F

Counter underflow

(cnt_udf)

Update event (UEV)

Update interrupt flag

(UIF)

MS31184V1

Figure 185. Counter timing diagram, internal clock divided by 2

640/1202

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

0002 0001 0000 0036 0035 0034 0033

MS31185V1

RM0471 Rev 5

RM0471 General-purpose timer (TIM2)

Figure 186. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

0001 0000 0000 0001

Figure 187. Counter timing diagram, internal clock divided by N

MS31186V1

CK_PSC

Timerclock = CK_CNT

Counter register 20 1F 00 36

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31187V1

RM0471 Rev 5 641/1202

702

General-purpose timer (TIM2) RM0471

Figure 188. Counter timing diagram, Update event when repetition counter is not used

CK_PSC

CEN

Timerclock = CK_CNT

Counter register

Counter underflow

05 04 03 02 01 00 36 35 34 33 32 31 30 2F

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload register

FF 36

Write a new value in TIMx_ARR

MS31188V1

Center-aligned mode (up/down counting)

In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the

TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting from 0.

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to

CMS = "11").

In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated by hardware and gives the current direction of the counter.

0, as well as the counter of the prescaler.

However, the counter continues counting up and down, based on the current auto-reload value.

In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the

UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or

642/1202 RM0471 Rev 5

RM0471 General-purpose timer (TIM2)

DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

 The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).

 The auto-reload active register is updated with the preload value (content of the

The following figures show some examples of the counter behavior for different clock frequencies.

Figure 189. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6

CK_PSC

CEN

Timerclock = CK_CNT

Counter register

Counter underflow

Counter overflow

04 03 02 01 00 01 02 03 04 05 06 05 04 03

Update event (UEV)

Update interrupt flag (UIF)

MS31189V3

1. Here, center-aligned mode 1 is used (for more details refer to

Section 20.4.1: TIM2 control register 1

(TIM2_CR1) on page 676

RM0471 Rev 5 643/1202

702

General-purpose timer (TIM2)

Figure 190. Counter timing diagram, internal clock divided by 2

RM0471

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0003 0002 0001 0000 0001 0002 0003

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31190V1

Figure 191. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Note: Here, center_aligned mode 2 or 3 is updated with an UIF on overflow

1. Center-aligned mode 2 or 3 is used with an UIF on overflow.

0036 0035

MS31191V1

644/1202 RM0471 Rev 5

RM0471 General-purpose timer (TIM2)

Figure 192. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 20 1F 01 00

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31192V1

Figure 193. Counter timing diagram, Update event with ARPE=1 (counter underflow)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register

06 05 04 03 02 01 00

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload register

Write a new value in TIMx_ARR

Auto-reload active register

01 02 03 04 05 06 07

MS31193V1

RM0471 Rev 5 645/1202

702

General-purpose timer (TIM2) RM0471

Figure 194. Counter timing diagram, Update event with ARPE=1 (counter overflow)

CK_PSC

CEN

Timer clock = CK_CNT

Counter register F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload register

Write a new value in TIMx_ARR

Auto-reload active register

MS31194V1

The counter clock can be provided by the following clock sources:

 Internal clock (CK_INT)

 External clock mode1: external input pin (TIx)

 External clock mode2: external trigger input (ETR)

 Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for

example, Timer X can be configured to act as a prescaler for Timer Y. Refer to : Using one timer as prescaler for another timer on page 671 for more details.

Internal clock source (CK_INT)

If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the

CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.

Figure 195 shows the behavior of the control circuit and the upcounter in normal mode,

without prescaler.

646/1202 RM0471 Rev 5

RM0471 General-purpose timer (TIM2)

Figure 195. Control circuit in normal mode, internal clock divided by 1

Internal clock

CEN=CNT_EN

CNT_INIT

Counter clock = CK_CNT = CK_PSC

Counter register 31 3 2 33 34 35 36 00 01 02 03 04 05 06 07

MS31085V2

External clock source mode 1

This mode is selected when SMS=111 in the TIMx_SMCR register.

The counter can count at each rising or falling edge on a selected input.

Figure 196. TI2 external clock connection example

TIMx_SMCR

TS[4:0]

TIMx_CH2

TI2[0]

TI2[1..15]

TI2

Filter

Edge detector

TI2F_Rising

TI2F_Falling

ITRx

TI1_ED

000xx

TI1FP1

TI2FP2

ETRF

00100

00101

00110

00111

(1) or

TI2F or

TI1F or

TRGI

ETRF

CK_INT

(internal clock)

Encoder mode

External clock mode 1

External clock mode 2

Internal clock mode

CK_PSC

ICF[3:0]

CC2P

TIMx_CCMR1 TIMx_CCER

ECE SMS[2:0]

TIMx_SMCR

MSv40117V1

1. Codes ranging from 01000 to 11111: ITRy.

For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure:

Select the proper TI2x source (internal or external) with the TI2SEL[3:0] bits in the

TIMx_TISEL register.

2. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the

TIMx_CCMR1 register.

3. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000).

RM0471 Rev 5 647/1202

702

General-purpose timer (TIM2)

Note:

RM0471

The capture prescaler is not used for triggering, so it does not need to be configured.

4. Select rising edge polarity by writing CC2P=0 and CC2NP=0 and CC2NP=0 in the

TIMx_CCER register.

5. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register.

6. Select TI2 as the input source by writing TS=00110 in the TIMx_SMCR register.

7. Enable the counter by writing CEN=1 in the TIMx_CR1 register.

When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.

The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input.

Figure 197. Control circuit in external clock mode 1

TI2

CNT_EN

Counter clock = CK_CNT = CK_PSC

Counter register

TIF

34 35 36

Write TIF=0

MS31087V2

External clock source mode 2

This mode is selected by writing ECE=1 in the TIMx_SMCR register.

The counter can count at each rising or falling edge on the external trigger input ETR.

Figure 198 gives an overview of the external trigger input block.

648/1202 RM0471 Rev 5

RM0471 General-purpose timer (TIM2)

Figure 198. External trigger input block or

TI2F

TI1F or or

ETR input or LSE

(1)

ETR1..15 inputs from on-chip sources

TRGI

ETR

ETP

TIMx_SMCR

Divider

/1, /2, /4, /8

ETRP f

DTS

Filter downcounter

ETPS[1:0]

TIMx_SMCR

ETRF

ETF[3:0]

TIMx_SMCR

CK_INT

(internal clock)

Encoder mode

External clock mode 1

External clock mode 2

Internal clock mode

CK_PSC

ETRSEL[3:0]

TIMx_AF1

ECE SMS[2:0]

TIMx_SMCR

MSv47462V1

1. As per ETR_RMP bit programming.

For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure:

Select the proper ETR source (internal or external) with the ETRSEL[3:0] bits in the

TIMx_AF1 register and the ETR_RMP bit in the TIM2_OR1 register.

2. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.

3. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register

4. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register

5. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.

6. Enable the counter by writing CEN=1 in the TIMx_CR1 register.

The counter counts once each 2 ETR rising edges.

ETPS prescaler setting.

RM0471 Rev 5 649/1202

702

General-purpose timer (TIM2)

Figure 199. Control circuit in external clock mode 2 f

CK_INT

CNT_EN

ETR

ETRP

ETRF

Counter clock =

CK_CNT =CK_PSC

Counter register 34 35

RM0471

MSv33111V3

TIMx_CH1

Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).

The following figure gives an overview of one Capture/Compare channel.

The input stage samples the corresponding TIx input to generate a filtered signal TIxF.

Figure 200. Capture/Compare channel (example: channel 1 input stage)

TI1F_ED

TI1[0]

To the slave mode controller

TI1[1..15] f

DTS

Filter downcounter

TI1F Edge detector

TI1F_Rising

TI1F_Falling

0 TI1FP1

TI2FP1

IC1

Divider

/1, /2, /4, /8

IC1PS

ICF[3:0]

TIMx_CCMR1

CC1P/CC1NP

TIMx_CCER

TI2F_Rising

(from channel 2)

TI2F_Falling

(from channel 2)

TRC

(from slave mode controller)

CC1S[1:0] ICPS[1:0]

TIMx_CCMR1

CC1E

TIMx_CCER

MSv40120V1

The output stage generates an intermediate waveform which is then used for reference:

OCxRef (active high). The polarity acts at the end of the chain.

650/1202 RM0471 Rev 5

RM0471

CC1S[1]

CC1S[0]

IC1PS

CC1E

Input mode

CC1G

TIMx_EGR

General-purpose timer (TIM2)

Figure 201. Capture/Compare channel 1 main circuit

APB Bus

MCU-peripheral interface

16/32-bit

Output mode

Capture/compare preload register

CC1S[1]

CC1S[0]

Capture

Counter

Compare transfer compare shadow register

Comparator

CNT>CCR1

CNT=CCR1

OC1PE

UEV

(from time base unit)

TIMx_CCMR1

MSv63030V1

Figure 202. Output stage of Capture/Compare channel (channel 1)

TIMx_SMCR

OCCS

OCREF_CLR

ETRF

OC1REFC ocref_clr_int

CNT > CCR1

CNT = CCR1

Output mode controller

OC1REF

Output selector

OC2REF

‘0’

To the master mode controller

CC1E

TIMx_CCER

CC1P

TIMx_CCER

OC1CE OC1M[3:0]

TIMx_CCMR1

Output enable circuit

OC1

CC1E TIMx_CCER

MS33145V5

The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register.

In capture mode, captures are actually done in the shadow register, which is copied into the preload register.

In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter.

RM0471 Rev 5 651/1202

702

General-purpose timer (TIM2) RM0471

Note:

TIMx_CCRx register. CCxOF is cleared when it is written with 0.

The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure:

Select the proper TI1x source (internal or external) with the TI1SEL[3:0] bits in the

TIMx_TISEL register.

DTS

TIMx_CCMR1 register.

frequency). Then write IC1F bits to 0011 in the

4. Select the edge of the active transition on the TI1 channel by writing the CC1P and

CC1NP and CC1NP bits to 000 in the TIMx_CCER register (rising edge in this case).

5. Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to 00 in the

TIMx_CCMR1 register).

6. Enable capture from the counter into the capture register by setting the CC1E bit in the

TIMx_CCER register.

7. If needed, enable the related interrupt request by setting the CC1IE bit in the

TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the

TIMx_DIER register.

When an input capture occurs:

 The TIMx_CCR1 register gets the value of the counter on the active transition.

 CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared.

 An interrupt is generated depending on the CC1IE bit.

 A DMA request is generated depending on the CC1DE bit.

IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register.

652/1202 RM0471 Rev 5

RM0471 General-purpose timer (TIM2)

20.3.6 PWM input mode

This mode is a particular case of input capture mode. The procedure is the same except:

 Two ICx signals are mapped on the same TIx input.

 These 2 ICx signals are active on edges with opposite polarity.

 One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode.

For example, one can measure the period (in TIMx_CCR1 register) and the duty cycle (in

TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value):

Select the proper TI1x source (internal or external) with the TI1SEL[3:0] bits in the

TIMx_TISEL register.

2. Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected).

3. Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P to ‘0’ and the CC1NP bit to ‘0’ (active on rising edge).

4. Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1 selected).

5. Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P bit to ‘1’ and the CC2NP bit to ’0’ (active on falling edge).

6. Select the valid trigger input: write the TS bits to 00101 in the TIMx_SMCR register

(TI1FP1 selected).

7. Configure the slave mode controller in reset mode: write the SMS bits to 100 in the

TIMx_SMCR register.

8. Enable the captures: write the CC1E and CC2E bits to ‘1 in the TIMx_CCER register.

Figure 203. PWM input mode timing

1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only

TI1FP1 and TI2FP2 are connected to the slave mode controller.

RM0471 Rev 5 653/1202

702

General-purpose timer (TIM2) RM0471

20.3.7 Forced output mode

In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal

(OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter.

To force an output compare signal (ocxref/OCx) to its active level, one just needs to write

101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus ocxref is forced high

(OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.

e.g.: CCxP=0 (OCx active high) => OCx is forced to high level.

ocxref signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register.

20.3.8 Output compare mode

This function is used to control an output waveform or indicating when a period of time has elapsed.

When a match is found between the capture/compare register and the counter, the output compare function:

 Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.

 Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).

 Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the

TIMx_DIER register).

 Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the

TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection).

The TIMx_CCRx registers can be programmed with or without preload registers using the

OCxPE bit in the TIMx_CCMRx register.

In output compare mode, the update event UEV has no effect on ocxref and OCx output.

The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One-pulse mode).

Procedure

Select the counter clock (internal, external, prescaler).

2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.

3. Set the CCxIE and/or CCxDE bits if an interrupt and/or a DMA request is to be generated.

4. Select the output mode. For example, one must write OCxM=011, OCxPE=0, CCxP=0 and CCxE=1 to toggle OCx output pin when CNT matches CCRx, CCRx preload is not used, OCx is enabled and active high.

5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.

654/1202 RM0471 Rev 5

RM0471 General-purpose timer (TIM2)

The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in

Figure 204 .

Figure 204. Output compare mode, toggle on OC1

Write B201h in the CC1R register

TIM1_CNT 0039

TIM1_CCR1

OC1REF= OC1

003A

003B B200

B201

Match detected on CCR1

Interrupt generated if enabled

MS31092V1

Pulse width modulation mode permits to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the

TIMx_CCRx register.

The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing 110 (PWM mode 1) or ‘111 (PWM mode 2) in the OCxM bits in the

TIMx_CCMRx register. The corresponding preload register must be enabled by setting the

OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.

OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by the CCxE bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details.

In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction of the counter). However, to comply with the OCREF_CLR functionality (OCREF can be

RM0471 Rev 5 655/1202

702

General-purpose timer (TIM2) RM0471 cleared by an external event through the ETR signal until the next PWM period), the

OCREF signal is asserted only:

 When the result of the comparison or

 When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from the “frozen” configuration (no comparison, OCxM=‘000) to one of the PWM modes

(OCxM=‘110 or ‘111).

This forces the PWM by software while the timer is running.

The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register.

PWM edge-aligned mode

Upcounting configuration

Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to

Upcounting mode on page 636 .

In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <TIMx_CCRx else it becomes low. If the compare value in

TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1.

If the compare value is 0 then OCxREF is held at ‘0. Figure 205 shows some edge-aligned

PWM waveforms in an example where TIMx_ARR=8.

Figure 205. Edge-aligned PWM waveforms (ARR=8)

Counter register

CCRx=4

OCXREF

CCxIF

0 1 2 3 4 5 6 7 8 0 1

CCRx=8

OCXREF

CCxIF

CCRx>8

OCXREF ‘1’

CCxIF

CCRx=0

OCXREF ‘0’

CCxIF

MS31093V1

656/1202 RM0471 Rev 5

RM0471 General-purpose timer (TIM2)

Downcounting configuration

Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Downcounting mode on page 639 .

In PWM mode 1, the reference signal ocxref is low as long as TIMx_CNT>TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in

TIMx_ARR, then ocxref is held at 100%. PWM is not possible in this mode.

PWM center-aligned mode

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from

‘00 (all the remaining configurations having the same effect on the ocxref/OCx signals). The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the

TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to

Center-aligned mode (up/down counting) on page 642 .

Figure 206 shows some center-aligned PWM waveforms in an example where:

 TIMx_ARR=8,

 PWM mode is the PWM mode 1,

 The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register.

RM0471 Rev 5 657/1202

702

General-purpose timer (TIM2)

Figure 206. Center-aligned PWM waveforms (ARR=8)

RM0471

Counter register 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1

OCxREF

CCRx = 4

CCxIF CMS=01

CMS=10

CMS=11

CCRx=7

OCxREF

CMS=10 or 11

CCxIF

CCRx=8

OCxREF

‘1’

CCxIF

CMS=01

CMS=10

CMS=11

CCRx>8

OCxREF

‘1’

CCxIF CMS=01

CMS=10

CMS=11

CCRx=0

OCxREF

‘0’

CCxIF CMS=01

CMS=10

CMS=11

AI14681b

Hints on using center-aligned mode:

 When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software.

 Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. In particular:

– The direction is not updated if a value greater than the auto-reload value is written in the counter (TIMx_CNT>TIMx_ARR). For example, if the counter was counting up, it continues to count up.

– The direction is updated if 0 or the TIMx_ARR value is written in the counter but no

Update Event UEV is generated.

 The safest way to use center-aligned mode is to generate an update by software

(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to write the counter while it is running.

658/1202 RM0471 Rev 5

RM0471 General-purpose timer (TIM2)

20.3.10 Asymmetric PWM mode

Note:

Asymmetric mode allows two center-aligned PWM signals to be generated with a programmable phase shift. While the frequency is determined by the value of the

TIMx_ARR register, the duty cycle and the phase-shift are determined by a pair of

TIMx_CCRx registers. One register controls the PWM during up-counting, the second during down counting, so that PWM is adjusted every half PWM cycle:

 OC1REFC (or OC2REFC) is controlled by TIMx_CCR1 and TIMx_CCR2

 OC3REFC (or OC4REFC) is controlled by TIMx_CCR3 and TIMx_CCR4

Asymmetric PWM mode can be selected independently on two channels (one OCx output per pair of CCR registers) by writing ‘1110’ (Asymmetric PWM mode 1) or ‘1111’

(Asymmetric PWM mode 2) in the OCxM bits in the TIMx_CCMRx register.

The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones.

When a given channel is used as asymmetric PWM channel, its secondary channel can also be used. For instance, if an OC1REFC signal is generated on channel 1 (Asymmetric PWM mode 1), it is possible to output either the OC2REF signal on channel 2, or an OC2REFC signal resulting from asymmetric PWM mode 2.

Figure 207 shows an example of signals that can be generated using Asymmetric PWM

mode (channels 1 to 4 are configured in Asymmetric PWM mode 1).

Figure 207. Generation of 2 phase-shifted PWM signals with 50% duty cycle

Counter register 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 0 1

OC1REFC

CCR1=0

CCR2=8

OC3REFC

CCR3=3

CCR4=5

MS33117V1

20.3.11 Combined PWM mode

AND logical combination of two reference PWMs:

– OC1REFC (or OC2REFC) is controlled by TIMx_CCR1 and TIMx_CCR2

– OC3REFC (or OC4REFC) is controlled by TIMx_CCR3 and TIMx_CCR4

RM0471 Rev 5 659/1202

702

General-purpose timer (TIM2)

Note:

RM0471

When a given channel is used as combined PWM channel, its secondary channel must be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the other in Combined PWM mode 2).

The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones.

Figure 208 shows an example of signals that can be generated using Asymmetric PWM

mode, obtained with the following configuration:

 Channel 1 is configured in Combined PWM mode 2,

 Channel 2 is configured in PWM mode 1,

 Channel 3 is configured in Combined PWM mode 2,

 Channel 4 is configured in PWM mode 1

Figure 208. Combined PWM mode on channels 1 and 3

OC2’

OC1’

OC2

OC1

OC1REF

OC2REF

OC1REF’

OC2REF’

OC1REFC

OC1REFC’

OC1REFC = OC1REF AND OC2REF

OC1REFC’ = OC1REF’ OR OC2REF’

MS31094V1

The OCxREF signal of a given channel can be cleared when a high level is applied on the ocref_clr_int input (OCxCE enable bit in the corresponding TIMx_CCMRx register set to 1).

OCxREF remains low until the next update event (UEV) occurs. This function can only be used in Output compare and PWM modes. It does not work in Forced mode.

OCREF_CLR_INPUT can be selected between the OCREF_CLR input and ETRF (ETR after the filter) by configuring the OCCS bit in the TIMx_SMCR register.

660/1202 RM0471 Rev 5

RM0471 General-purpose timer (TIM2)

The OCxREF signal for a given channel can be reset by applying a high level on the ETRF input (OCxCE enable bit set to 1 in the corresponding TIMx_CCMRx register). OCxREF remains low until the next update event (UEV) occurs.

This function can be used only in the output compare and PWM modes. It does not work in forced mode.

For example, the OCxREF signal can be connected to the output of a comparator to be used for current handling. In this case, ETR must be configured as follows:

The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR register are cleared to 00.

2. The external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is cleared to 0.

3. The external trigger polarity (ETP) and the external trigger filter (ETF) can be configured according to the application’s needs.

Figure 209 shows the behavior of the OCxREF signal when the ETRF input becomes high,

for both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in

PWM mode.

Figure 209. Clearing TIMx OCxREF

Counter (CNT)

(CCRx)

ETRF

Note:

OCxREF

(OCxCE = ‘0’)

OCxREF

(OCxCE = ‘1’) ocref_clr_int becomes high ocref_clr_int still high

MS33105V2

In case of a PWM with a 100% duty cycle (if CCRx>ARR), OCxREF is enabled again at the next counter overflow.

RM0471 Rev 5 661/1202

702

General-purpose timer (TIM2) RM0471

A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be:

 CNT<CCRx ≤ ARR (in particular, 0<CCRx),

Figure 210. Example of one-pulse mode.

TI2

OC1REF

OC1

TIM1_ARR

TIM1_CCR1

0 t

DELAY t

PULSE t

MS31099V1

For example one may want to generate a positive pulse on OC1 with a length of t

PULSE after a delay of t

DELAY

as soon as a positive edge is detected on the TI2 input pin.

and

Let’s use TI2FP2 as trigger 1:

Select the proper TI2x source (internal or external) with the TI2SEL[3:0] bits in the

TIMx_TISEL register.

2. Map TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register.

3. TI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=’0’ in the TIMx_CCER register.

4. Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=00110 in the TIMx_SMCR register.

5. TI2FP2 is used to start the counter by writing SMS to ‘110 in the TIMx_SMCR register

(trigger mode).

662/1202 RM0471 Rev 5

RM0471 General-purpose timer (TIM2)

The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler).

 The t

DELAY is defined by the value written in the TIMx_CCR1 register.

 The t

PULSE

is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1).

 Let’s say one want to build a waveform with a transition from ‘0 to ‘1 when a compare match occurs and a transition from ‘1 to ‘0 when the counter reaches the auto-reload value. To do this PWM mode 2 must be enabled by writing OC1M=111 in the

TIMx_CCMR1 register. Optionally the preload registers can be enabled by writing

OC1PE=1 in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case one has to write the compare value in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0 in this example.

In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.

Since only 1 pulse (Single mode) is needed, a 1 must be written in the OPM bit in the

Particular case: OCx fast enable:

DELAY

min we can get.

If one wants to output a waveform with the minimum delay, the OCxFE bit can be set in the

TIMx_CCMRx register. Then OCxRef (and OCx) is forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.

20.3.14 Retriggerable one pulse mode

Note:

This mode allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length, but with the following differences with Non-retriggerable

one pulse mode described in Section 20.3.13

 The pulse starts as soon as the trigger occurs (no programmable delay)

 The pulse is extended if a new trigger occurs before the previous one is completed

The timer must be in Slave mode, with the bits SMS[3:0] = ‘1000’ (Combined Reset + trigger mode) in the TIMx_SMCR register, and the OCxM[3:0] bits set to ‘1000’ or ‘1001’ for

Retriggerable OPM mode 1 or 2.

If the timer is configured in Up-counting mode, the corresponding CCRx must be set to 0

(the ARR register sets the pulse length). If the timer is configured in Down-counting mode

CCRx must be above or equal to ARR.

In retriggerable one pulse mode, the CCxIF flag is not significant.

The OCxM[3:0] and SMS[3:0] bit fields are split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones.

This mode must not be used with center-aligned PWM modes. It is mandatory to have

CMS[1:0] = 00 in TIMx_CR1.

RM0471 Rev 5 663/1202

702

General-purpose timer (TIM2)

Figure 211. Retriggerable one-pulse mode.

TRGI

Counter

RM0471

Output

MS33106V1

To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if it is counting on both TI1 and TI2 edges.

Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register. CC1NP and CC2NP must be kept cleared. When needed, the input filter can be programmed as well. CC1NP and CC2NP must be kept low.

The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to

Table 130

. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2 after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,

TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in

TIMx_CR1 register written to ‘1). The sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on TI1 only, TI2 only or both TI1 and TI2.

Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value in the

TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So the

TIMx_ARR must be configured before starting. In the same way, the capture, compare, prescaler, trigger output features continue to work as normal.

In this mode, the counter is modified automatically following the speed and the direction of the quadrature encoder and its content, therefore, always represents the encoder’s position.

The count direction correspond to the rotation direction of the connected sensor. The table summarizes the possible combinations, assuming TI1 and TI2 do not switch at the same time.

664/1202 RM0471 Rev 5

RM0471 General-purpose timer (TIM2)

Active edge

Counting on

TI1 only

Counting on

TI2 only

Counting on

TI1 and TI2

Table 130. Counting direction versus encoder signals

Level on opposite signal (TI1FP1 for

TI2, TI2FP2 for TI1)

TI1FP1 signal

Rising Falling

TI2FP2 signal

Rising Falling

High

Low

High

Low

High

Low

Down

No Count

Down

No Count

Down

No Count

Down

No Count

Down

An external incremental encoder can be connected directly to the MCU without external interface logic. However, comparators are normally be used to convert the encoder’s differential outputs to digital signals. This greatly increases noise immunity. The third encoder output which indicate the mechanical zero position, may be connected to an external interrupt input and trigger a counter reset.

Figure 212 gives an example of counter operation, showing count signal generation and

direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near to one of the switching points. For this example we assume that the configuration is the following:

 CC1S= 01 (TIMx_CCMR1 register, TI1FP1 mapped on TI1)

 CC2S= 01 (TIMx_CCMR2 register, TI2FP2 mapped on TI2)

 CC1P and CC1NP = ‘0’ (TIMx_CCER register, TI1FP1 noninverted, TI1FP1=TI1)

 CC2P and CC2NP = ‘0’ (TIMx_CCER register, TI2FP2 noninverted, TI2FP2=TI2)

 SMS= 011 (TIMx_SMCR register, both inputs are active on both rising and falling edges)

 CEN= 1 (TIMx_CR1 register, Counter is enabled)

Figure 212. Example of counter operation in encoder interface mode forward jitter backward jitter forward

TI1

TI2

Counter up down up

MS33107V1

Figure 213 gives an example of counter behavior when TI1FP1 polarity is inverted (same

configuration as above except CC1P=1).

RM0471 Rev 5 665/1202

702

General-purpose timer (TIM2) RM0471

Figure 213. Example of encoder interface mode with TI1FP1 polarity inverted forward jitter backward jitter forward

TI1

TI2

Counter down up down

MS33108V1

20.3.16 UIF bit remapping

The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the update interrupt flag (UIF) into bit 31 of the timer counter register’s bit 31 (TIMxCNT[31]). This permits to atomically read both the counter value and a potential roll-over condition signaled by the UIFCPY flag. It eases the calculation of angular speed by avoiding race conditions caused, for instance, by a processing shared between a background task (counter reading) and an interrupt (update interrupt).

There is no latency between the UIF and UIFCPY flag assertions.

20.3.17 Timer input XOR function

The TI1S bit in the TIM1xx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3.

The XOR output can be used with all the timer input functions such as trigger or input capture.

An example of this feature used to interface Hall sensors is given in

Section 19.3.25:

Interfacing with Hall sensors on page 584 .

666/1202 RM0471 Rev 5

RM0471 General-purpose timer (TIM2)

20.3.18 Timers and external trigger synchronization

The TIMx Timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode.

Slave mode: Reset mode

The counter and its prescaler can be reinitialized in response to an event on a trigger input.

Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.

In the following example, the upcounter is cleared in response to a rising edge on TI1 input:

Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration

CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect rising edges only).

2. Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select

TI1 as the input source by writing TS=00101 in TIMx_SMCR register.

3. Start the counter by writing CEN=1 in the TIMx_CR1 register.

The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request can be sent if enabled (depending on the TIE bit in TIMx_DIER register).

The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.

The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input.

Figure 214. Control circuit in reset mode

TI1

Counter clock = ck_cnt = ck_psc

Counter register

TIF

30 31 32 33 34 35 36 00 01 02 03 00 01 02 03

MS31401V2

Slave mode: Gated mode

The counter can be enabled depending on the level of a selected input.

In the following example, the upcounter counts only when TI1 input is low:

RM0471 Rev 5 667/1202

702

General-purpose timer (TIM2) RM0471

Configure the channel 1 to detect low levels on TI1. Configure the input filter duration

CC1P=1 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect low level only).

2. Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select

TI1 as the input source by writing TS=00101 in TIMx_SMCR register.

3. Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=0, whatever is the trigger input level).

The counter starts counting on the internal clock as long as TI1 is low and stops as soon as

TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops.

The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input.

Figure 215. Control circuit in gated mode

Note:

TI1 cnt_en

Counter clock = ck_cnt = ck_psc

Counter register

TIF

30 31 32 33 34 35 36 37 38

Write TIF=0

MS31402V1

1. The configuration “CCxP=CCxNP=1” (detection of both rising and falling edges) does not have any effect in gated mode because gated mode acts on a level and not on an edge.

The configuration “CCxP=CCxNP=1” (detection of both rising and falling edges) does not have any effect in gated mode because gated mode acts on a level and not on an edge.

Slave mode: Trigger mode

The counter can start in response to an event on a selected input.

In the following example, the upcounter starts in response to a rising edge on TI2 input:

Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration

(in this example, we do not need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so it does not need to be configured. CC2S bits are selecting the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write

668/1202 RM0471 Rev 5

RM0471

CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only).

2. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select

TI2 as the input source by writing TS=00110 in TIMx_SMCR register.

When a rising edge occurs on TI2, the counter starts counting on the internal clock and the

TIF flag is set.

The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input.

Figure 216. Control circuit in trigger mode

TI2 cnt_en

Counter clock = ck_cnt = ck_psc

Counter register

General-purpose timer (TIM2)

35 36 37 38

TIF

MS31403V1

Slave mode: External Clock mode 2 + trigger mode

The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock input, and another input can be selected as trigger input when operating in reset mode, gated mode or trigger mode. It is recommended not to select ETR as TRGI through the TS bits of TIMx_SMCR register.

In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs:

Configure the external trigger input circuit by programming the TIMx_SMCR register as follows:

– ETF = 0000: no filter

– ETPS=00: prescaler disabled

– ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2.

2. Configure the channel 1 as follows, to detect rising edges on TI:

– IC1F=0000: no filter.

– The capture prescaler is not used for triggering and does not need to be configured.

– CC1S=01in TIMx_CCMR1 register to select only the input capture source

– CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect rising edge only).

3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select

TI1 as the input source by writing TS=00101 in TIMx_SMCR register.

RM0471 Rev 5 669/1202

702

General-purpose timer (TIM2) RM0471

A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on

ETR rising edges.

The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input.

Figure 217. Control circuit in external clock mode 2 + trigger mode

TI1

CEN/CNT_EN

ETR

Counter clock = CK_CNT = CK_PSC

Counter register

TIF

34 35 36

MS33110V1

Clock

The TIMx timers are linked together internally for timer synchronization or chaining. When one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of another Timer configured in Slave Mode.

Figure 218: Master/Slave timer example and

Figure 219: Master/slave connection example with 1 channel only timers present an overview of the trigger selection and the master mode

selection blocks.

TIM1

Figure 218. Master/Slave timer example

TIM2

UEV

Prescaler Counter

MMS SMS

Master mode control

TRGO1

Input trigger selection

ITR1

Slave mode control

CK_PSC

Prescaler Counter

MS32694V1

670/1202 RM0471 Rev 5

RM0471 General-purpose timer (TIM2)

Figure 219. Master/slave connection example with 1 channel only timers

TIM_mstr TIM_slv

Clock

Prescaler

Note:

Counter TS

SMS

Compare 1

Output tim_oc1 control tim_itr

Slave mode control

CK_PSC

Prescaler Counter

TIM_CH1

Input trigger selection

MSv65225V1

The timers with one channel only (see Figure 219 ) do not feature a master mode. However,

the OC1 output signal can be used to trigger some other timers (including timers described in other sections of this document). Check the “TIMx internal trigger connection” table of any

TIMx_SMCR register on the device to identify which timers can be targeted as slave.

The OC1 signal pulse width must be programmed to be at least 2 clock cycles of the destination timer, to make sure the slave timer will detect the trigger.

For instance, if the destination's timer CK_INT clock is 4 times slower than the source timer, the OC1 pulse width must be 8 clock cycles.

Using one timer as prescaler for another timer

For example, TIM1 can be configured to act as a prescaler for TIM2. Refer to Figure 218 . To

do this:

Configure TIM1 in master mode so that it outputs a periodic trigger signal on each update event UEV. If MMS=010 is written in the TIM1_CR2 register, a rising edge is output on TRGO each time an update event is generated.

2. To connect the TRGO output of TIM1 to TIM2, TIM2 must be configured in slave mode using ITR0 as internal trigger. This is selected through the TS bits in the TIM2_SMCR register (writing TS=00000).

3. Then the slave mode controller must be put in external clock mode 1 (write SMS=111 in the TIM2_SMCR register). This causes TIM2 to be clocked by the rising edge of the periodic TIM1 trigger signal (which correspond to the TIM1 counter overflow).

4. Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1 register).

If OCx is selected on TIM 1 as the trigger output (MMS=1xx), its rising edge is used to clock the counter of TIM 2 .

Using one timer to enable another timer

In this example, we control the enable of TIM2 with the output compare 1 of Timer 1. Refer

to Figure 218 for connections. TIM2 counts on the divided internal clock only when OC1REF

of TIM1 is high. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (f

CK_CNT

= f

CK_INT

/3).

RM0471 Rev 5 671/1202

702

General-purpose timer (TIM2)

Note:

RM0471

Configure TIM1 master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIM1_CR2 register).

2. Configure the TIM1 OC1REF waveform (TIM1_CCMR1 register).

3. Configure TIM2 to get the input trigger from TIM1 (TS=00000 in the TIM2_SMCR register).

4. Configure TIM2 in gated mode (SMS=101 in TIM2_SMCR register).

6. Start TIM by writing ‘1 in the CEN bit (TIM1_CR1 register).

The counter 2 clock is not synchronized with counter 1, this mode only affects the TIM 2 counter enable signal.

Figure 220. Gating TIM2 with OC1REF of TIM1

CK_INT

TIM1-OC1REF

TIM1-CNT

TIM2-CNT

TIM2-TIF

3045

3046

FE FF

3047

3048

Write TIF = 0

MS32695V2

In the example in

Figure 220 , the TIM2 counter and prescaler are not initialized before being

started. So they start counting from their current value. It is possible to start from a given value by resetting both timers before starting TIM1. Then any value can be written in the timer counters. The timers can easily be reset by software using the UG bit in the

TIMx_EGR registers.

In the next example (refer to

Figure 221

), we synchronize TIM1 and TIM2. TIM1 is the master and starts from 0. TIM2 is the slave and starts from 0xE7. The prescaler ratio is the same for both timers. TIM2 stops when TIM1 is disabled by writing ‘0 to the CEN bit in the

TIM1_CR1 register:

Configure TIM1 master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIM1_CR2 register).

2. Configure the TIM1 OC1REF waveform (TIM1_CCMR1 register).

3. Configure TIM2 to get the input trigger from TIM1 (TS=00000 in the TIM2_SMCR register).

4. Configure TIM2 in gated mode (SMS=101 in TIM2_SMCR register).

7. Initialize TIM2 to 0xE7 by writing ‘0xE7’ in the TIM2 counter (TIM2_CNTL).

9. Start TIM1 by writing ‘1 in the CEN bit (TIM1_CR1 register).

10. Stop TIM1 by writing ‘0 in the CEN bit (TIM1_CR1 register).

672/1202 RM0471 Rev 5

RM0471

CK_INT

TIM1-CEN=CNT_EN

TIM1-CNT_INIT

TIM1-CNT

TIM2-CNT

TIM2-CNT_INIT

TIM2-write CNT

TIM2-TIF

General-purpose timer (TIM2)

Figure 221. Gating TIM2 with Enable of TIM1

AB 00

Write TIF = 0

MS32696V1

Using one timer to start another timer

In this example, we set the enable of Timer 2 with the update event of Timer 1. Refer to

Figure 218 for connections. Timer 2 starts counting from its current value (which can be

non-zero) on the divided internal clock as soon as the update event is generated by Timer 1.

When Timer 2 receives the trigger signal its CEN bit is automatically set and the counter counts until we write ‘0 to the CEN bit in the TIM2_CR1 register. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (f

CK_CNT

= f

CK_INT

/3).

Configure TIM1 master mode to send its Update Event (UEV) as trigger output

(MMS=010 in the TIM1_CR2 register).

2. Configure the TIM1 period (TIM1_ARR registers).

3. Configure TIM2 to get the input trigger from TIM1 (TS=00000 in the TIM2_SMCR register).

4. Configure TIM2 in trigger mode (SMS=110 in TIM2_SMCR register).

5. Start TIM1 by writing ‘1 in the CEN bit (TIM1_CR1 register).

Figure 222. Triggering TIM2 with update of TIM1

CK_INT

TIM1-UEV

TIM1-CNT

TIM2-CNT

TIM2-CEN=CNT_EN

TIM2-TIF

FD FE

FF 00

Write TIF = 0

MS32697V1

RM0471 Rev 5 673/1202

702

General-purpose timer (TIM2) RM0471

As in the previous example, both counters can be initialized before starting counting.

Figure 223 shows the behavior with the same configuration as in

Figure 222

but in trigger mode instead of gated mode (SMS=110 in the TIM2_SMCR register).

Figure 223. Triggering TIM2 with Enable of TIM1

CK_INT

TIM1-CEN=CNT_EN

TIM1-CNT_INIT

75 00 01

TIM1-CNT

TIM2-CNT

CD 00 E7 E8

E9 EA

TIM2-CNT_INIT

TIM2 write CNT

TIM2-TIF

Note:

Write TIF = 0

MS32698V1

The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.

20.3.20 DMA burst mode

The TIMx timers have the capability to generate multiple DMA requests upon a single event.

The main purpose is to be able to re-program part of the timer multiple times without software overhead, but it can also be used to read several registers in a row, at regular intervals.

The DMA controller destination is unique and must point to the virtual register TIMx_DMAR.

On a given timer event, the timer launches a sequence of DMA requests (burst). Each write into the TIMx_DMAR register is actually redirected to one of the timer registers.

Example:

00000: TIMx_CR1

00001: TIMx_CR2

00010: TIMx_SMCR

674/1202 RM0471 Rev 5

RM0471

Note:

General-purpose timer (TIM2)

As an example, the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4) upon an update event, with the DMA transferring half words into the

CCRx registers.

This is done in the following steps:

Configure the corresponding DMA channel as follows:

– DMA channel peripheral address is the DMAR register address

– DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers.

– Number of data to transfer = 3 (See note below).

– Circular mode disabled.

2. Configure the DCR register by configuring the DBA and DBL bit fields as follows:

DBL = 3 transfers, DBA = 0xE.

3. Enable the TIMx update DMA request (set the UDE bit in the DIER register).

5. Enable the DMA channel

This example is for the case where every CCRx register has to be updated once. If every

CCRx register is to be updated twice for example, the number of data to transfer should be

6. Let's take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and data6. The data is transferred to the CCRx registers as follows: on the first update DMA request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to

CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4.

A null value can be written to the reserved registers.

When the system enters debug mode (processor core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIM2_STOP configuration bit in

DBGMCU module. For more details, refer to

Section 32.8.3: DBGMCU CPU1 APB1 peripheral freeze register 1 (DBGMCU_APB1FZR1)

RM0471 Rev 5 675/1202

702

General-purpose timer (TIM2) RM0471

In this section, “TIMx” should be understood as “TIM2” since there is only one instance of this type of timer for the products to which this reference manual applies.

Refer to Section 1.2

for a list of abbreviations used in register descriptions.

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

20.4.1 TIM2 control register 1 (TIM2_CR1)

Res.

Address offset: 0x00

Reset value: 0x0000

Res.

UIFRE

MAP rw

Res.

CKD[1:0] rw

8 rw

ARPE rw

6 5

CMS[1:0] rw rw

DIR rw

OPM rw

URS rw

UDIS rw

CEN rw

Bits 15:12 Reserved, must be kept at reset value.

Bit 11 UIFREMAP : UIF status bit remapping

0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.

1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.

Bit 10 Reserved, must be kept at reset value.

Bits 9:8 CKD[1:0] : Clock division

This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),

00: t

DTS

= t

CK_INT

01: t

DTS

= 2 × t

CK_INT

10: t

DTS

= 4 × t

CK_INT

11: Reserved

Bit 7 ARPE : Auto-reload preload enable

0: TIMx_ARR register is not buffered

1: TIMx_ARR register is buffered

Bits 6:5 CMS[1:0] : Center-aligned mode selection

00: Edge-aligned mode. The counter counts up or down depending on the direction bit

(DIR).

Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1)

676/1202 RM0471 Rev 5

RM0471 General-purpose timer (TIM2)

Bit 4 DIR : Direction

0: Counter used as upcounter

1: Counter used as downcounter

Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.

Bit 3 OPM : One-pulse mode

0: Counter is not stopped at update event

1: Counter stops counting at the next update event (clearing the bit CEN)

Bit 2 URS : Update request source

This bit is set and cleared by software to select the UEV event sources.

0: Any of the following events generate an update interrupt or DMA request if enabled.

These events can be:

– Counter overflow/underflow

– Setting the UG bit

– Update generation through the slave mode controller

1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.

Bit 1 UDIS : Update disable

This bit is set and cleared by software to enable/disable UEV event generation.

0: UEV enabled. The Update (UEV) event is generated by one of the following events:

– Counter overflow/underflow

– Setting the UG bit

– Update generation through the slave mode controller

Buffered registers are then loaded with their preload values.

1: UEV disabled. The Update event is not generated, shadow registers keep their value

(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

Bit 0 CEN : Counter enable

0: Counter disabled

1: Counter enabled

Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.

CEN is cleared automatically in one-pulse mode, when an update event occurs.

20.4.2 TIM2 control register 2 (TIM2_CR2)

Res.

Address offset: 0x04

Res.

Reset value: 0x0000

Res.

TI1S rw

6 rw

MMS[2:0] rw

4 rw

3 2

CCDS Res.

Res.

RM0471 Rev 5 677/1202

702

General-purpose timer (TIM2) RM0471

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 TI1S : TI1 selection

0: The TIMx_CH1 pin is connected to TI1 input

1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)

20.4.3 TIM2 slave mode control register (TIM2_SMCR)

Address offset: 0x08

Reset value: 0x0000 0000

Res.

ETP rw

Res.

ECE rw

Res.

13 12

ETPS[1:0] rw rw

Res.

11 rw

Res.

10 9

ETF[3:0] rw rw

Res.

8 rw

Res.

MSM rw

Res.

6 rw

TS[4:3]

20 rw

5 rw

TS[2:0] rw rw

Res.

OCCS rw

Res.

2 rw

17 16

Res.

SMS[3]

1 rw

SMS[2:0] rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bits 19:17 Reserved, must be kept at reset value.

Bit 15 ETP : External trigger polarity

This bit selects whether ETR or ETR is used for trigger operations

0: ETR is non-inverted, active at high level or rising edge

1: ETR is inverted, active at low level or falling edge

Bit 14 ECE : External clock enable

This bit enables External clock mode 2.

0: External clock mode 2 disabled

1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111).

If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.

Bits 13:12 ETPS[1:0] : External trigger prescaler

External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.

00: Prescaler OFF

01: ETRP frequency divided by 2

10: ETRP frequency divided by 4

11: ETRP frequency divided by 8

RM0471 Rev 5 679/1202

702

General-purpose timer (TIM2) RM0471

Bits 11:8 ETF[3:0] : External trigger filter

0000: No filter, sampling is done at f

DTS

0001: f

SAMPLING

CK_INT

0010: f

SAMPLING

0011: f

SAMPLING

0100: f

SAMPLING

0101: f

SAMPLING

0110: f

SAMPLING

CK_INT

DTS

, N=2

, N=4

, N=8

/2, N=6

/2, N=8

/4, N=6

/4, N=8 0111: f

SAMPLING

DTS

1000: f

SAMPLING

1001: f

SAMPLING

1010: f

SAMPLING

1011: f

SAMPLING

1100: f

SAMPLING

DTS

/8, N=6

/8, N=8

/16, N=5

/16, N=6

/16, N=8

/32, N=5 1101: f

SAMPLING

1110: f

SAMPLING

1111: f

SAMPLING

DTS

/32, N=6

/32, N=8

Bit 7 MSM : Master/Slave mode

0: No action

680/1202 RM0471 Rev 5

RM0471 General-purpose timer (TIM2)

Bits 21, 20, 6, 5, 4 TS[4:0] : Trigger selection

This bit-field selects the trigger input to be used to synchronize the counter.

00000: Internal Trigger 0 (ITR0)

00001: Internal Trigger 1 (ITR1)

00010: Internal Trigger 2 (ITR2)

00011: Internal Trigger 3 (ITR3)

00100: TI1 Edge Detector (TI1F_ED)

00101: Filtered Timer Input 1 (TI1FP1)

00110: Filtered Timer Input 2 (TI2FP2)

00111: External Trigger input (ETRF)

01000: Internal Trigger 4 (ITR4)

01001: Internal Trigger 5 (ITR5)

01010: Internal Trigger 6 (ITR6)

01011: Internal Trigger 7 (ITR7)

01100: Internal Trigger 8 (ITR8)

Others: Reserved

See

Table 131: TIM2 internal trigger connection on page 682

for more details on ITRx meaning for each Timer.

Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.

Bit 3 OCCS : OCREF clear selection

This bit is used to select the OCREF clear source

0: OCREF_CLR_INT is connected to the OCREF_CLR input

1: OCREF_CLR_INT is connected to ETRF

RM0471 Rev 5 681/1202

702

General-purpose timer (TIM2) RM0471

Bits 16, 2, 1, 0 SMS[3:0] : Slave mode selection

When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.

0000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.