STMicroelectronics STM32MP153A Reference Manual

RM0442
Reference manual
STM32MP153
advanced Arm®-based 32-bit MPUs
Introduction
This reference manual targets application developers. It provides complete information on
how to use the STM32MP153 microprocessor memory and peripherals.
The STM32MP153 is a family of microprocessors with different packages and peripherals.
Refer to the corresponding datasheets for ordering information, mechanical and electrical
device characteristics.
For information on the Arm® Cortex®-A7 and Cortex®-M4 cores, refer to the Cortex®-A7 and
Cortex®-M4 Technical Reference Manuals.
The STM32MP153 microprocessors include ST state-of-the-art patented technology.
Related documents
• Cortex®-A7 Technical Reference Manual, available from: http://infocenter.arm.com
• Cortex®-M4 Technical Reference Manual, available from: http://infocenter.arm.com
• STM32MP153x datasheet
• STM32 Cortex®-M4 MCUs and MPUs programming manual (PM0214)
• STM32MP151x/3x/7x device errata (ES0438)
March 2025
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Contents
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2
Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
1.1
General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
1.2
List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
1.3
Register reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
1.4
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
1.5
Availability of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Memory and bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
2.1
2.2
2.3
2.4
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System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
2.1.1
Bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
2.1.2
Memory Map organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
AXI interconnect matrix (AXIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
2.2.1
AXIM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
2.2.2
AXIM interconnect configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
2.2.3
Master ports description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
2.2.4
Master ports main characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
2.2.5
Master ports security characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 125
2.2.6
Slave ports description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
2.2.7
Slave ports main characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
2.2.8
Slave ports security characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Multi-layer AHB interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
2.3.1
Multi-layer AHB features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
2.3.2
Multi-layer AHB interconnect configuration . . . . . . . . . . . . . . . . . . . . . 127
2.3.3
Multi-layer AHB master ports characteristics . . . . . . . . . . . . . . . . . . . . 128
2.3.4
Multi-layer AHB slave ports characteristics . . . . . . . . . . . . . . . . . . . . . 129
AXIMC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
2.4.1
AXIMC peripheral ID4 register (AXIMC_PERIPH_ID_4) . . . . . . . . . . . 130
2.4.2
AXIMC peripheral ID5 register (AXIMC_PERIPH_ID_5) . . . . . . . . . . . 130
2.4.3
AXIMC peripheral ID6 register (AXIMC_PERIPH_ID_6) . . . . . . . . . . . 131
2.4.4
AXIMC peripheral ID7 register (AXIMC_PERIPH_ID_7) . . . . . . . . . . . 131
2.4.5
AXIMC peripheral ID0 register (AXIMC_PERIPH_ID_0) . . . . . . . . . . . 131
2.4.6
AXIMC peripheral ID1 register (AXIMC_PERIPH_ID_1) . . . . . . . . . . . 132
2.4.7
AXIMC peripheral ID2 register (AXIMC_PERIPH_ID_2) . . . . . . . . . . . 132
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2.4.8
AXIMC peripheral ID3 register (AXIMC_PERIPH_ID_3) . . . . . . . . . . . 132
2.4.9
AXIMC component ID0 register (AXIMC_COMP_ID_0) . . . . . . . . . . . 133
2.4.10
AXIMC component ID1 register (AXIMC_COMP_ID_1) . . . . . . . . . . . 133
2.4.11
AXIMC component ID2 register (AXIMC_COMP_ID_2) . . . . . . . . . . . 134
2.4.12
AXIMC component ID3 register (AXIMC_COMP_ID_3) . . . . . . . . . . . 134
2.4.13
AXIMC master x packing functionality register
(AXIMC_Mx_FN_MOD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
2.4.14
AXIMC master x AHB conversion override functionality register
(AXIMC_Mx_FN_MOD_AHB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
2.4.15
AXIMC master x read priority register (AXIMC_Mx_READ_QOS) . . . 136
2.4.16
AXIMC master x write priority register (AXIMC_Mx_WRITE_QOS) . . 136
2.4.17
AXIMC master x issuing capability override functionality register
(AXIMC_Mx_FN_MOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
2.4.18
AXIMC master x packing functionality register
(AXIMC_Mx_FN_MOD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
2.4.19
AXIMC master x AHB conversion override functionality register
(AXIMC_Mx_FN_MOD_AHB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
2.4.20
AXIMC master x read priority register (AXIMC_Mx_READ_QOS) . . . 138
2.4.21
AXIMC master x write priority register (AXIMC_Mx_WRITE_QOS) . . 139
2.4.22
AXIMC master x issuing capability override functionality register
(AXIMC_Mx_FN_MOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
2.4.23
AXIMC master x read priority register (AXIMC_Mx_READ_QOS) . . . 140
2.4.24
AXIMC master x write priority register (AXIMC_Mx_WRITE_QOS) . . 140
2.4.25
AXIMC master x packing functionality register
(AXIMC_Mx_FN_MOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
2.4.26
AXIMC master x read priority register (AXIMC_Mx_READ_QOS) . . . 141
2.4.27
AXIMC master x write priority register (AXIMC_Mx_WRITE_QOS) . . 142
2.4.28
AXIMC master x issuing capability override functionality register
(AXIMC_Mx_FN_MOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
2.4.29
AXIMC long burst capability inhibition register
(AXIMC_FN_MOD_LB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
2.4.30
AXIMC master x read priority register (AXIMC_Mx_READ_QOS) . . . 143
2.4.31
AXIMC master x write priority register (AXIMC_Mx_WRITE_QOS) . . 144
2.4.32
AXIMC master x issuing capability override functionality register
(AXIMC_Mx_FN_MOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
2.4.33
AXIMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
2.5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
2.5.2
Memory map and register boundary addresses . . . . . . . . . . . . . . . . . 154
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Boot and security and OTP control (BSEC) . . . . . . . . . . . . . . . . . . . . 165
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
3.2
BSEC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
3.3
BSEC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
3.4
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3.3.1
BSEC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
3.3.2
Interface to OTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
3.3.3
OTP security modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
3.3.4
Automatic OTP load on system-reset . . . . . . . . . . . . . . . . . . . . . . . . . 168
3.3.5
OTP words status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
3.3.6
OTP operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
3.3.7
JTAG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
3.3.8
BSEC lock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
3.3.9
Debug control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
3.3.10
Sticky lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
OTP layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
3.4.1
DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
3.4.2
TrustZone awareness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
3.4.3
BSEC clocking and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
3.5
BSEC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
3.6
BSEC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
3.6.1
BSEC OTP configuration register (BSEC_OTP_CONFIG) . . . . . . . . . 175
3.6.2
BSEC OTP control register (BSEC_OTP_CONTROL) . . . . . . . . . . . . 175
3.6.3
BSEC OTP write data register (BSEC_OTP_WRDATA) . . . . . . . . . . . 176
3.6.4
BSEC OTP status register (BSEC_OTP_STATUS) . . . . . . . . . . . . . . . 176
3.6.5
BSEC OTP lock configuration register (BSEC_OTP_LOCK) . . . . . . . 177
3.6.6
BSEC debug configuration register (BSEC_DENABLE) . . . . . . . . . . . 178
3.6.7
BSEC OTP disturbed status register x (BSEC_OTP_DISTURBEDx) . 179
3.6.8
BSEC OTP error status register x (BSEC_OTP_ERRORx) . . . . . . . . 180
3.6.9
BSEC OTP lock status register x (BSEC_OTP_WRLOCKEDx) . . . . . 180
3.6.10
BSEC OTP sticky programming lock register x
(BSEC_OTP_SPLOCKx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
3.6.11
BSEC OTP shadow write sticky lock register x
(BSEC_OTP_SWLOCKx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
3.6.12
BSEC OTP shadow read sticky lock register x
(BSEC_OTP_SRLOCKx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
3.6.13
BSEC JTAG input register (BSEC_JTAGIN) . . . . . . . . . . . . . . . . . . . . 183
3.6.14
BSEC JTAG output register (BSEC_JTAGOUT) . . . . . . . . . . . . . . . . . 184
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3.6.15
BSEC scratch register (BSEC_SCRATCH) . . . . . . . . . . . . . . . . . . . . . 184
3.6.16
BSEC shadow register x (BSEC_OTP_DATAx) . . . . . . . . . . . . . . . . . 184
3.6.17
BSEC hardware configuration register (BSEC_HWCFGR) . . . . . . . . . 185
3.6.18
BSEC version register (BSEC_VERR) . . . . . . . . . . . . . . . . . . . . . . . . 186
3.6.19
BSEC identification register (BSEC_IPIDR) . . . . . . . . . . . . . . . . . . . . 186
3.6.20
BSEC size identification register (BSEC_SIDR) . . . . . . . . . . . . . . . . . 186
3.6.21
BSEC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
4
OTP mapping (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
5
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL) . . . . . . . . . . . . . . . . . 202
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
5.2
DDRCTRL features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
5.3
DDRCTRL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
5.4
DDRCTRL architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
5.5
5.4.1
AXI Port Interface (XPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
5.4.2
Port arbiter (PA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
5.4.3
Host Interface (HIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
5.4.4
DDR scheduler (DDRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
5.4.5
APB Interface (APB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
5.4.6
DFI Interface (DFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
DDRCTRL functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
5.5.1
Transaction service control (TSC) and quality of service (QoS) . . . . . 208
5.5.2
Paging policy options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
5.5.3
Power saving features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
5.5.4
Address mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
5.5.5
DRAM timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
5.5.6
SDRAM initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
5.5.7
Refresh controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
5.5.8
ZQ calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
5.6
DDRCTRL configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
5.7
DDRCTRL registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
5.7.1
DDRCTRL master register 0 (DDRCTRL_MSTR) . . . . . . . . . . . . . . . . 213
5.7.2
DDRCTRL operating mode status register (DDRCTRL_STAT) . . . . . . 215
5.7.3
DDRCTRL mode register read/write control register 0
(DDRCTRL_MRCTRL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
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5.7.4
DDRCTRL mode register read/write control register 1
(DDRCTRL_MRCTRL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
5.7.5
DDRCTRL mode register read/write status register
(DDRCTRL_MRSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
5.7.6
DDRCTRL temperature derate enable register
(DDRCTRL_DERATEEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
5.7.7
DDRCTRL temperature derate interval register
(DDRCTRL_DERATEINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
5.7.8
DDRCTRL low power control register (DDRCTRL_PWRCTL) . . . . . . 221
5.7.9
DDRCTRL low power timing register (DDRCTRL_PWRTMG) . . . . . . 222
5.7.10
DDRCTRL hardware low power control register
(DDRCTRL_HWLPCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
5.7.11
DDRCTRL refresh control register 0 (DDRCTRL_RFSHCTL0) . . . . . . 224
5.7.12
DDRCTRL refresh control register 3 (DDRCTRL_RFSHCTL3) . . . . . . 226
5.7.13
DDRCTRL refresh timing register (DDRCTRL_RFSHTMG) . . . . . . . . 227
5.7.14
DDRCTRL CRC parity control register 0 (DDRCTRL_CRCPARCTL0) 228
5.7.15
DDRCTRL CRC parity status register (DDRCTRL_CRCPARSTAT) . . 229
5.7.16
DDRCTRL SDRAM initialization register 0 (DDRCTRL_INIT0) . . . . . . 230
5.7.17
DDRCTRL SDRAM initialization register 1 (DDRCTRL_INIT1) . . . . . . 231
5.7.18
DDRCTRL SDRAM initialization register 2 (DDRCTRL_INIT2) . . . . . . 231
5.7.19
DDRCTRL SDRAM initialization register 3 (DDRCTRL_INIT3) . . . . . . 232
5.7.20
DDRCTRL SDRAM initialization register 4 (DDRCTRL_INIT4) . . . . . . 233
5.7.21
DDRCTRL SDRAM initialization register 5 (DDRCTRL_INIT5) . . . . . . 233
5.7.22
DDRCTRL DIMM control register (DDRCTRL_DIMMCTL) . . . . . . . . . 234
5.7.23
DDRCTRL SDRAM timing register 0 (DDRCTRL_DRAMTMG0) . . . . 235
5.7.24
DDRCTRL SDRAM timing register 1 (DDRCTRL_DRAMTMG1) . . . . 236
5.7.25
DDRCTRL SDRAM timing register 2 (DDRCTRL_DRAMTMG2) . . . . 237
5.7.26
DDRCTRL SDRAM timing register 3 (DDRCTRL_DRAMTMG3) . . . . 240
5.7.27
DDRCTRL SDRAM timing register 4 (DDRCTRL_DRAMTMG4) . . . . 241
5.7.28
DDRCTRL SDRAM timing register 5 (DDRCTRL_DRAMTMG5) . . . . 242
5.7.29
DDRCTRL SDRAM timing register 6 (DDRCTRL_DRAMTMG6) . . . . 244
5.7.30
DDRCTRL SDRAM timing register 7 (DDRCTRL_DRAMTMG7) . . . . 245
5.7.31
DDRCTRL SDRAM timing register 8 (DDRCTRL_DRAMTMG8) . . . . 246
5.7.32
DDRCTRL SDRAM timing register 14 (DDRCTRL_DRAMTMG14) . . 246
5.7.33
DDRCTRL SDRAM timing register 15 (DDRCTRL_DRAMTMG15) . . 247
5.7.34
DDRCTRL ZQ control register 0 (DDRCTRL_ZQCTL0) . . . . . . . . . . . 248
5.7.35
DDRCTRL ZQ control register 1 (DDRCTRL_ZQCTL1) . . . . . . . . . . . 249
5.7.36
DDRCTRL ZQ control register 2 (DDRCTRL_ZQCTL2) . . . . . . . . . . . 250
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5.7.37
DDRCTRL ZQ status register (DDRCTRL_ZQSTAT) . . . . . . . . . . . . . 250
5.7.38
DDRCTRL DFI timing register 0 (DDRCTRL_DFITMG0) . . . . . . . . . . 251
5.7.39
DDRCTRL DFI timing register 1 (DDRCTRL_DFITMG1) . . . . . . . . . . 252
5.7.40
DDRCTRL low power configuration register 0
(DDRCTRL_DFILPCFG0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
5.7.41
DDRCTRL DFI update register 0 (DDRCTRL_DFIUPD0) . . . . . . . . . . 256
5.7.42
DDRCTRL DFI update register 1 (DDRCTRL_DFIUPD1) . . . . . . . . . . 257
5.7.43
DDRCTRL DFI update register 2 (DDRCTRL_DFIUPD2) . . . . . . . . . . 258
5.7.44
DDRCTRL DFI miscellaneous control register (DDRCTRL_DFIMISC) 258
5.7.45
DDRCTRL DFI status register (DDRCTRL_DFISTAT) . . . . . . . . . . . . 259
5.7.46
DDRCTRL DFI PHY master register (DDRCTRL_DFIPHYMSTR) . . . 260
5.7.47
DDRCTRL address map register 1 (DDRCTRL_ADDRMAP1) . . . . . . 260
5.7.48
DDRCTRL address map register 2 (DDRCTRL_ADDRMAP2) . . . . . . 261
5.7.49
DDRCTRL address map register 3 (DDRCTRL_ADDRMAP3) . . . . . . 263
5.7.50
DDRCTRL address map register 4 (DDRCTRL_ADDRMAP4) . . . . . . 266
5.7.51
DDRCTRL address map register 5 (DDRCTRL_ADDRMAP5) . . . . . . 267
5.7.52
DDRCTRL address register 6 (DDRCTRL_ADDRMAP6) . . . . . . . . . . 268
5.7.53
DDRCTRL address map register 9 (DDRCTRL_ADDRMAP9) . . . . . . 270
5.7.54
DDRCTRL address map register 10 (DDRCTRL_ADDRMAP10) . . . . 271
5.7.55
DDRCTRL address map register 11 (DDRCTRL_ADDRMAP11) . . . . 272
5.7.56
DDRCTRL ODT configuration register (DDRCTRL_ODTCFG) . . . . . . 272
5.7.57
DDRCTRL ODT/Rank map register (DDRCTRL_ODTMAP) . . . . . . . . 274
5.7.58
DDRCTRL scheduler control register (DDRCTRL_SCHED) . . . . . . . . 275
5.7.59
DDRCTRL scheduler control register 1 (DDRCTRL_SCHED1) . . . . . 276
5.7.60
DDRCTRL high priority read CAM register 1
(DDRCTRL_PERFHPR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
5.7.61
DDRCTRL low priority read CAM register 1 (DDRCTRL_PERFLPR1) 278
5.7.62
DDRCTRL write CAM register 1 (DDRCTRL_PERFWR1) . . . . . . . . . 278
5.7.63
DDRCTRL debug register 0 (DDRCTRL_DBG0) . . . . . . . . . . . . . . . . 279
5.7.64
DDRCTRL debug register 1 (DDRCTRL_DBG1) . . . . . . . . . . . . . . . . 280
5.7.65
DDRCTRL CAM debug register (DDRCTRL_DBGCAM) . . . . . . . . . . 280
5.7.66
DDRCTRL command debug register (DDRCTRL_DBGCMD) . . . . . . 282
5.7.67
DDRCTRL status debug register (DDRCTRL_DBGSTAT) . . . . . . . . . 283
5.7.68
DDRCTRL software register programming control enable
(DDRCTRL_SWCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
5.7.69
DDRCTRL software register programming control status
(DDRCTRL_SWSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
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DDRCTRL AXI Poison configuration register
(DDRCTRL_POISONCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
5.7.71
DDRCTRL AXI Poison status register (DDRCTRL_POISONSTAT) . . 286
5.7.72
DDRCTRL port status register (DDRCTRL_PSTAT) . . . . . . . . . . . . . . 287
5.7.73
DDRCTRL port common configuration register (DDRCTRL_PCCFG) 288
5.7.74
DDRCTRL port x configuration read register (DDRCTRL_PCFGR_x) 289
5.7.75
DDRCTRL port x configuration write register
(DDRCTRL_PCFGW_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
5.7.76
DDRCTRL port x control register (DDRCTRL_PCTRL_x) . . . . . . . . . . 291
5.7.77
DDRCTRL port x read Q0S configuration register 0
(DDRCTRL_PCFGQOS0_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
5.7.78
DDRCTRL port x read Q0S configuration register 1
(DDRCTRL_PCFGQOS1_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
5.7.79
DDRCTRL port x write Q0S configuration register 0
(DDRCTRL_PCFGWQOS0_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
5.7.80
DDRCTRL port x write Q0S configuration register 1
(DDRCTRL_PCFGWQOS1_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
5.7.81
DDRCTRL registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
TrustZone® address space controller for DDR (TZC) . . . . . . . . . . . . 313
6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
6.2
TZC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
6.3
TZC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
6.4
TZC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
6.5
TZC application programming examples . . . . . . . . . . . . . . . . . . . . . . . . 316
6.6
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6.5.1
DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
6.5.2
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
TZC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
6.6.1
TZC configuration register (TZC_BUILD_CONFIG) . . . . . . . . . . . . . . 321
6.6.2
TZC action register (TZC_ACTION) . . . . . . . . . . . . . . . . . . . . . . . . . . 321
6.6.3
TZC gate keeper register (TZC_GATE_KEEPER) . . . . . . . . . . . . . . . 322
6.6.4
TZC speculation control register (TZC_SPECULATION_CTRL) . . . . . 323
6.6.5
TZC interrupt status register (TZC_INT_STATUS) . . . . . . . . . . . . . . . 323
6.6.6
TZC interrupt clear register (TZC_INT_CLEAR) . . . . . . . . . . . . . . . . . 324
6.6.7
TZC fail address low register x (TZC_FAIL_ADDRESS_LOWx) . . . . . 324
6.6.8
TZC fail address high register x (TZC_FAIL_ADDRESS_HIGHx) . . . . 325
6.6.9
TZC fail control register x (TZC_FAIL_CONTROLx) . . . . . . . . . . . . . . 325
6.6.10
TZC fail ID register x (TZC_FAIL_IDx) . . . . . . . . . . . . . . . . . . . . . . . . . 326
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Contents
6.6.11
TZC region 0 base address low register
(TZC_REGION_BASE_LOW0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
6.6.12
TZC region x base address high register (TZC_REGION_BASE_HIGHx)
327
6.6.13
TZC region 0 top address low register
(TZC_REGION_TOP_LOW0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
6.6.14
TZC region x top address high register (TZC_REGION_TOP_HIGHx) 328
6.6.15
TZC region 0 attribute register (TZC_REGION_ATTRIBUTE0) . . . . . . 328
6.6.16
TZC region x ID access register (TZC_REGION_ID_ACCESSx) . . . . 329
6.6.17
TZC region x base address low register
(TZC_REGION_BASE_LOWx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
6.6.18
TZC region x top address low register
(TZC_REGION_TOP_LOWx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
6.6.19
TZC region x attribute register (TZC_REGION_ATTRIBUTEx) . . . . . . 330
6.6.20
TZC peripheral ID 4 register (TZC_PID4) . . . . . . . . . . . . . . . . . . . . . . 331
6.6.21
TZC peripheral ID 5 register (TZC_PID5) . . . . . . . . . . . . . . . . . . . . . . 331
6.6.22
TZC peripheral ID 6 register (TZC_PID6) . . . . . . . . . . . . . . . . . . . . . . 331
6.6.23
TZC peripheral ID 7 register (TZC_PID7) . . . . . . . . . . . . . . . . . . . . . . 332
6.6.24
TZC peripheral ID 0 register (TZC_PID0) . . . . . . . . . . . . . . . . . . . . . . 332
6.6.25
TZC peripheral ID 1 register (TZC_PID1) . . . . . . . . . . . . . . . . . . . . . . 333
6.6.26
TZC peripheral ID 2 register (TZC_PID2) . . . . . . . . . . . . . . . . . . . . . . 333
6.6.27
TZC peripheral ID 3 register (TZC_PID3) . . . . . . . . . . . . . . . . . . . . . . 333
6.6.28
TZC component ID 0 register (TZC_CID0) . . . . . . . . . . . . . . . . . . . . . 334
6.6.29
TZC component ID 1 register (TZC_CID1) . . . . . . . . . . . . . . . . . . . . . 334
6.6.30
TZC component ID 2 register (TZC_CID2) . . . . . . . . . . . . . . . . . . . . . 335
6.6.31
TZC component ID 3 register (TZC_CID3) . . . . . . . . . . . . . . . . . . . . . 335
6.6.32
TZC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
DDR physical interface control (DDRPHYC) . . . . . . . . . . . . . . . . . . . . 342
7.1
DDRPHYC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
7.2
DDRPHYC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
7.3
DDRPHYC SDRAM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
7.4
DDRPHY (DDR multiPHY IP core) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
7.5
7.4.1
DDRPHY overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
7.4.2
Delay locked loop (DLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
7.4.3
Interface timing modules (ITMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
7.4.4
SSTL IO’s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
PUBL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
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7.6
7.7
10/3930
7.5.1
PHY and SDRAM initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
7.5.2
DDR3 initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
7.5.3
LPDDR2 initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
7.5.4
Initialization trigger and bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
7.5.5
DATA training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
7.5.6
DQS gate training (DQSTRN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
7.5.7
Read valid training (RVTRN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
PUBL timings and DFI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
7.6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
7.6.2
Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
7.6.3
Read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
7.6.4
DDRPHY read/write latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
7.6.5
DFI 2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
PUBL registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
7.7.1
DDRPHYC revision ID register (DDRPHYC_RIDR) . . . . . . . . . . . . . . 372
7.7.2
DDRPHYC PHY initialization register (DDRPHYC_PIR) . . . . . . . . . . . 372
7.7.3
DDRPHYC PHY global control register (DDRPHYC_PGCR) . . . . . . . 375
7.7.4
DDRPHYC PHY global status register (DDRPHYC_PGSR) . . . . . . . . 377
7.7.5
DDRPHYC DDR DLL global control register (DDRPHYC_DLLGCR) . 378
7.7.6
DDRPHYC AC DLL control register (DDRPHYC_ACDLLCR) . . . . . . . 380
7.7.7
DDRPHYC PT register 0 (DDRPHYC_PTR0) . . . . . . . . . . . . . . . . . . . 381
7.7.8
DDRPHYC PT register 1 (DDRPHYC_PTR1) . . . . . . . . . . . . . . . . . . . 381
7.7.9
DDRPHYC PT register 2 (DDRPHYC_PTR2) . . . . . . . . . . . . . . . . . . . 382
7.7.10
DDRPHYC ACIOC register (DDRPHYC_ACIOCR) . . . . . . . . . . . . . . . 383
7.7.11
DDRPHYC DXCC register (DDRPHYC_DXCCR) . . . . . . . . . . . . . . . . 384
7.7.12
DDRPHYC DSGC register (DDRPHYC_DSGCR) . . . . . . . . . . . . . . . 385
7.7.13
DDRPHYC DC register (DDRPHYC_DCR) . . . . . . . . . . . . . . . . . . . . . 388
7.7.14
DDRPHYC DTP register 0 (DDRPHYC_DTPR0) . . . . . . . . . . . . . . . . 389
7.7.15
DDRPHYC DTP register 1 (DDRPHYC_DTPR1) . . . . . . . . . . . . . . . . 390
7.7.16
DDRPHYC DTP register 2 (DDRPHYC_DTPR2) . . . . . . . . . . . . . . . . 392
7.7.17
DDRPHYC MR0 register for DDR3 (DDRPHYC_DDR3_MR0) . . . . . . 392
7.7.18
DDRPHYC MR1 register for DDR3 (DDRPHYC_DDR3_MR1) . . . . . . 394
7.7.19
DDRPHYC MR1 register for LPDDR2 [alternate]
(DDRPHYC_LPDDR2_MR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
7.7.20
DDRPHYC MR1 register for LPDDR3 [alternate]
(DDRPHYC_LPDDR3_MR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
7.7.21
DDRPHYC MR2 register for DDR3 (DDRPHYC_DDR3_MR2) . . . . . . 397
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Contents
7.7.22
DDRPHYC MR2 register for LPDDR2 [alternate]
(DDRPHYC_LPDDR2_MR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
7.7.23
DDRPHYC MR2 register for LPDDR3 [alternate]
(DDRPHYC_LPDDR3_MR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
7.7.24
DDRPHYC MR3 register for DDR3 (DDRPHYC_DDR3_MR3) . . . . . . 399
7.7.25
DDRPHYC MR3 register for LPDDR2 [alternate]
(DDRPHYC_LPDDR2_MR3) 399
7.7.26
DDRPHYC MR3 register for LPDDR3 [alternate]
(DDRPHYC_LPDDR3_MR3) 400
7.7.27
DDRPHYC ODTC register (DDRPHYC_ODTCR) . . . . . . . . . . . . . . . . 400
7.7.28
DDRPHYC DTA register (DDRPHYC_DTAR) . . . . . . . . . . . . . . . . . . . 401
7.7.29
DDRPHYC DTD register 0 (DDRPHYC_DTDR0) . . . . . . . . . . . . . . . . 401
7.7.30
DDRPHYC DTD register 1 (DDRPHYC_DTDR1) . . . . . . . . . . . . . . . . 402
7.7.31
DDRPHYC general purpose register 0 (DDRPHYC_GPR0) . . . . . . . . 402
7.7.32
DDRPHYC general purpose register 1 (DDRPHYC_GPR1) . . . . . . . . 402
7.7.33
DDRPHYC ZQ0C register 0 (DDRPHYC_ZQ0CR0) . . . . . . . . . . . . . . 403
7.7.34
DDRPHYC ZQ0CR1 register (DDRPHYC_ZQ0CR1) . . . . . . . . . . . . . 404
7.7.35
DDRPHYC ZQ0S register 0 (DDRPHYC_ZQ0SR0) . . . . . . . . . . . . . . 405
7.7.36
DDRPHYC ZQ0S register 1 (DDRPHYC_ZQ0SR1) . . . . . . . . . . . . . . 405
7.7.37
DDRPHYC byte lane n GC register (DDRPHYC_DXnGCR) . . . . . . . . 406
7.7.38
DDRPHYC byte lane n GS register 0 (DDRPHYC_DXnGSR0) . . . . . 409
7.7.39
DDRPHYC byte lane n GS register 1 (DDRPHYC_DXnGSR1) . . . . . 409
7.7.40
DDRPHYC byte lane n DLLC register (DDRPHYC_DXnDLLCR) . . . . 410
7.7.41
DDRPHYC byte lane n DQT register (DDRPHYC_DXnDQTR) . . . . . . 412
7.7.42
DDRPHYC byte lane n DQST register (DDRPHYC_DXnDQSTR) . . . 413
7.7.43
DDRPHYC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
DDR performance monitor (DDRPERFM) . . . . . . . . . . . . . . . . . . . . . . 421
8.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
8.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
8.3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
8.4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
8.5
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
8.6
8.5.1
Signal set 0: to monitor the DDR utilization . . . . . . . . . . . . . . . . . . . . . 425
8.5.2
Signal set 1: to monitor the HPR and LPR stores . . . . . . . . . . . . . . . . 425
8.5.3
Signal set 2: to monitor the refresh and self-refresh duration . . . . . . . 425
8.5.4
Signal set 3: to monitor the DDR stalling . . . . . . . . . . . . . . . . . . . . . . . 425
DDRPERFM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
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RM0442
8.6.1
DDRPERFM control register (DDRPERFM_CTL) . . . . . . . . . . . . . . . . 426
8.6.2
DDRPERFM configurationl register (DDRPERFM_CFG) . . . . . . . . . . 426
8.6.3
DDRPERFM status register (DDRPERFM_STATUS) . . . . . . . . . . . . . 427
8.6.4
DDRPERFM counter clear register (DDRPERFM_CCR) . . . . . . . . . . 427
8.6.5
DDRPERFM interrupt enable register (DDRPERFM_IER) . . . . . . . . . 428
8.6.6
DDRPERFM interrupt status register (DDRPERFM_ISR) . . . . . . . . . . 428
8.6.7
DDRPERFM interrupt clear register (DDRPERFM_ICR) . . . . . . . . . . 429
8.6.8
DDRPERFM time counter register (DDRPERFM_TCNT) . . . . . . . . . . 429
8.6.9
DDRPERFM event counter x register (DDRPERFM_CNTx) . . . . . . . . 430
8.6.10
DDRPERFM hardware configuration register (DDRPERFM_HWCFG) 430
8.6.11
DDRPERFM version register (DDRPERFM_VER) . . . . . . . . . . . . . . . 430
8.6.12
DDRPERFM ID register (DDRPERFM_ID) . . . . . . . . . . . . . . . . . . . . . 431
8.6.13
DDRPERFM magic ID register (DDRPERFM_SID) . . . . . . . . . . . . . . 431
8.6.14
DDRPERFM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
9.1
PWR main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
9.2
PWR block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
9.2.1
9.3
9.4
12/3930
PWR pin overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
PWR power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
9.3.1
PWR core domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
9.3.2
PWR supply system startup sequence . . . . . . . . . . . . . . . . . . . . . . . . 440
9.3.3
PWR supply Stop sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
9.3.4
PWR supply LP-Stop sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
9.3.5
PWR supply LPLV-Stop sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
9.3.6
PWR supply Standby sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
9.3.7
PWR supply VBAT sequence from Standby. . . . . . . . . . . . . . . . . . . . . 445
9.3.8
PWR VSW domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
9.3.9
PWR VBAT battery charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
9.3.10
PWR analog supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
9.3.11
PWR 1V8 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
9.3.12
PWR 1V1 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
PWR power supply supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
9.4.1
PWR power-on reset (POR)/power-down reset (PDR) . . . . . . . . . . . . 450
9.4.2
PWR brownout reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
9.4.3
PWR VDDCORE OK reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
9.4.4
PWR programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . 453
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9.5
9.6
9.4.5
PWR analog voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . 454
9.4.6
PWR battery voltage thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
9.4.7
PWR temperature thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
PWR power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
9.5.1
PWR operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
9.5.2
PWR power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
9.5.3
PWR system wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
PWR low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
9.6.1
PWR slowing down the CPU clocks and/or the bus matrix clocks . . . 470
9.6.2
PWR controlling peripheral clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
9.6.3
PWR entering to low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
9.6.4
PWR exiting from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 471
9.6.5
PWR CSleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
9.6.6
PWR CStop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
9.6.7
PWR CStandby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
9.6.8
PWR Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
9.6.9
PWR LP-Stop and LPLV-Stop modes . . . . . . . . . . . . . . . . . . . . . . . . . 477
9.6.10
PWR Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
9.6.11
PWR debug Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
9.6.12
PWR debug Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
9.7
PWR WKUP pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
9.8
PWR_ON and PWR_LP pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
9.9
PWR interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
9.10
PWR TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
9.11
PWR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
9.11.1
PWR control register 1 (PWR_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 483
9.11.2
PWR control status register 1 (PWR_CSR1) . . . . . . . . . . . . . . . . . . . . 485
9.11.3
PWR control register 2 (PWR_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 486
9.11.4
PWR control register 3 (PWR_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . 487
9.11.5
PWR MPU control register (PWR_MPUCR) . . . . . . . . . . . . . . . . . . . . 489
9.11.6
PWR MCU control register (PWR_MCUCR) . . . . . . . . . . . . . . . . . . . . 491
9.11.7
PWR wakeup control register (PWR_WKUPCR) . . . . . . . . . . . . . . . . 492
9.11.8
PWR wakeup flag register (PWR_WKUPFR) . . . . . . . . . . . . . . . . . . . 493
9.11.9
PWR MPU wakeup enable register (PWR_MPUWKUPENR) . . . . . . . 494
9.11.10 PWR MCU wakeup enable register (PWR_MCUWKUPENR) . . . . . . . 495
9.11.11
PWR IP version register (PWR_VER) . . . . . . . . . . . . . . . . . . . . . . . . . 495
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9.11.12 PWR IP identification register (PWR_ID) . . . . . . . . . . . . . . . . . . . . . . . 496
9.11.13 PWR size ID register (PWR_SID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
9.11.14 PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
10
Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
10.1
RCC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
10.2
RCC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
10.2.1
10.3
RCC pin overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
RCC functional description - reset part . . . . . . . . . . . . . . . . . . . . . . . . . 501
10.3.1
The power-on/off resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
10.3.2
The application and system resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
10.3.3
The local resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
10.3.4
Resets generated by the CPUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
10.3.5
Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
10.3.6
Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
10.3.7
Coresight debug reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
10.3.8
Option bytes loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
10.3.9
Peripheral reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
10.3.10 Reset pulse control (RPCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
10.3.11 Reset delay control (RDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
10.3.12 Reset coverage summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
10.3.13 Reset source identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
10.3.14 Power-on and wakeup sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
10.4
RCC functional description - clock part . . . . . . . . . . . . . . . . . . . . . . . . . 519
10.4.1
Clock naming convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
10.4.2
Oscillators description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
10.4.3
Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
10.4.4
Clock output generation (MCO1 and MCO2) . . . . . . . . . . . . . . . . . . . . 531
10.4.5
PLLs description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
10.4.6
Sub-system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
10.4.7
Clock generation in Stop and Standby modes . . . . . . . . . . . . . . . . . . . 542
10.4.8
Peripheral clock distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
10.4.9
General clock concept overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
10.4.10 Peripheral allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
10.4.11 Peripheral clock gating control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
10.4.12 Processors and interconnect clocks gating . . . . . . . . . . . . . . . . . . . . . 600
10.4.13 Low-power emulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
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10.4.14 RCC TrustZone function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
10.5
RCC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
10.6
RCC application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .611
10.7
10.6.1
Handling dynamic clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
10.6.2
PLL programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
10.6.3
Configuring the sub-system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
10.6.4
The clock calibration using TIMx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
10.6.5
Clock restore sequence examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
10.7.1
Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
10.7.2
RCC TrustZone control register (RCC_TZCR) . . . . . . . . . . . . . . . . . . 637
10.7.3
RCC oscillator clock enable set register (RCC_OCENSETR) . . . . . . . 638
10.7.4
RCC oscillator clock enable clear register (RCC_OCENCLRR) . . . . . 640
10.7.5
RCC oscillator clock ready register (RCC_OCRDYR) . . . . . . . . . . . . . 642
10.7.6
RCC debug configuration register (RCC_DBGCFGR) . . . . . . . . . . . . 644
10.7.7
RCC HSI configuration register (RCC_HSICFGR) . . . . . . . . . . . . . . . 645
10.7.8
RCC CSI configuration register (RCC_CSICFGR) . . . . . . . . . . . . . . . 646
10.7.9
RCC MCO1 configuration register (RCC_MCO1CFGR) . . . . . . . . . . . 647
10.7.10 RCC MCO2 configuration register (RCC_MCO2CFGR) . . . . . . . . . . . 647
10.7.11 RCC MPU clock selection register (RCC_MPCKSELR) . . . . . . . . . . . 648
10.7.12 RCC AXI sub-system clock selection register (RCC_ASSCKSELR) . . 650
10.7.13 RCC MCU sub-system clock selection register
(RCC_MSSCKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
10.7.14 RCC PLL 1 and 2 reference clock selection register
(RCC_RCK12SELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
10.7.15 RCC PLL 3 reference clock selection register (RCC_RCK3SELR) . . . 653
10.7.16 RCC PLL4 reference clock selection register (RCC_RCK4SELR) . . . 654
10.7.17 RCC TIM group 1 prescaler register (RCC_TIMG1PRER) . . . . . . . . . 655
10.7.18 RCC TIM group 2 prescaler register (RCC_TIMG2PRER) . . . . . . . . . 656
10.7.19 RCC RTC clock division register (RCC_RTCDIVR) . . . . . . . . . . . . . . 657
10.7.20 RCC MPU clock divider register (RCC_MPCKDIVR) . . . . . . . . . . . . . 658
10.7.21 RCC AXI clock divider register (RCC_AXIDIVR) . . . . . . . . . . . . . . . . . 658
10.7.22 RCC APB4 clock divider register (RCC_APB4DIVR) . . . . . . . . . . . . . 660
10.7.23 RCC APB5 clock divider register (RCC_APB5DIVR) . . . . . . . . . . . . . 661
10.7.24 RCC MCU clock divider register (RCC_MCUDIVR) . . . . . . . . . . . . . . 662
10.7.25 RCC APB1 clock divider register (RCC_APB1DIVR) . . . . . . . . . . . . . 662
10.7.26 RCC APB2 clock divider register (RCC_APB2DIVR) . . . . . . . . . . . . . 664
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10.7.27 RCC APB3 clock divider register (RCC_APB3DIVR) . . . . . . . . . . . . . 665
10.7.28 RCC PLL1 control register (RCC_PLL1CR) . . . . . . . . . . . . . . . . . . . . 666
10.7.29 RCC PLL1 configuration register 1 (RCC_PLL1CFGR1) . . . . . . . . . . 668
10.7.30 RCC PLL1 configuration register 2 (RCC_PLL1CFGR2) . . . . . . . . . . 668
10.7.31 RCC PLL1 fractional register (RCC_PLL1FRACR) . . . . . . . . . . . . . . . 669
10.7.32 RCC PLL1 clock spreading generator register (RCC_PLL1CSGR) . . 670
10.7.33 RCC PLL2 control register (RCC_PLL2CR) . . . . . . . . . . . . . . . . . . . . 671
10.7.34 RCC PLL2 configuration register 1 (RCC_PLL2CFGR1) . . . . . . . . . . 673
10.7.35 RCC PLL2 configuration register 2 (RCC_PLL2CFGR2) . . . . . . . . . . 673
10.7.36 RCC PLL2 fractional register (RCC_PLL2FRACR) . . . . . . . . . . . . . . . 674
10.7.37 RCC PLL2 clock spreading generator register (RCC_PLL2CSGR) . . 675
10.7.38 RCC PLL3 control register (RCC_PLL3CR) . . . . . . . . . . . . . . . . . . . . 676
10.7.39 RCC PLL3 configuration register 1 (RCC_PLL3CFGR1) . . . . . . . . . . 678
10.7.40 RCC PLL3 configuration register 2 (RCC_PLL3CFGR2) . . . . . . . . . . 679
10.7.41 RCC PLL3 fractional register (RCC_PLL3FRACR) . . . . . . . . . . . . . . . 680
10.7.42 RCC PLL4 control register (RCC_PLL4CR) . . . . . . . . . . . . . . . . . . . . 680
10.7.43 RCC PLL4 configuration register 1 (RCC_PLL4CFGR1) . . . . . . . . . . 682
10.7.44 RCC PLL4 configuration register 2 (RCC_PLL4CFGR2) . . . . . . . . . . 683
10.7.45 RCC PLL4 fractional register (RCC_PLL4FRACR) . . . . . . . . . . . . . . . 683
10.7.46 RCC I2C1,2 kernel clock selection register (RCC_I2C12CKSELR) . . 684
10.7.47 RCC I2C3,5 kernel clock selection register (RCC_I2C35CKSELR) . . 686
10.7.48 RCC I2C4, 6 kernel clock selection register
(RCC_I2C46CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
10.7.49 RCC SAI1 kernel clock selection register (RCC_SAI1CKSELR) . . . . . 688
10.7.50 RCC SAI2 kernel clock selection register (RCC_SAI2CKSELR) . . . . . 689
10.7.51 RCC SAI3 kernel clock selection register (RCC_SAI3CKSELR) . . . . . 690
10.7.52 RCC SAI4 kernel clock selection register (RCC_SAI4CKSELR) . . . . . 690
10.7.53 RCC SPI/I2S1 kernel clock selection register
(RCC_SPI2S1CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
10.7.54 RCC SPI/I2S2,3 kernel clock selection register
(RCC_SPI2S23CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
10.7.55 RCC SPI4,5 kernel clock selection register (RCC_SPI45CKSELR) . . 693
10.7.56 RCC SPI6 kernel clock selection register (RCC_SPI6CKSELR) . . . . . 694
10.7.57 RCC USART6 kernel clock selection register
(RCC_UART6CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
10.7.58 RCC UART2,4 kernel clock selection register
(RCC_UART24CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
10.7.59 RCC UART3,5 kernel clock selection register
(RCC_UART35CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
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10.7.60 RCC UART7,8 kernel clock selection register
(RCC_UART78CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698
10.7.61 RCC USART1 kernel clock selection register
(RCC_UART1CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
10.7.62 RCC SDMMC1 and 2 kernel clock selection register
(RCC_SDMMC12CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
10.7.63 RCC SDMMC3 kernel clock selection register
(RCC_SDMMC3CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
10.7.64 RCC ethernet kernel clock selection register (RCC_ETHCKSELR) . . 702
10.7.65 RCC QUADSPI kernel clock selection register
(RCC_QSPICKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
10.7.66 RCC FMC kernel clock selection register (RCC_FMCCKSELR) . . . . . 704
10.7.67 RCC FDCAN kernel clock selection register
(RCC_FDCANCKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
10.7.68 RCC SPDIFRX kernel clock selection register
(RCC_SPDIFCKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
10.7.69 RCC CEC kernel clock selection register (RCC_CECCKSELR) . . . . . 707
10.7.70 RCC USB kernel clock selection register (RCC_USBCKSELR) . . . . . 708
10.7.71 RCC RNG1 kernel clock selection register (RCC_RNG1CKSELR) . . 709
10.7.72 RCC RNG2 kernel clock selection register (RCC_RNG2CKSELR) . . 710
10.7.73 RCC common peripheral clock selection register
(RCC_CPERCKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
10.7.74 RCC STGEN clock selection register (RCC_STGENCKSELR) . . . . . 712
10.7.75 RCC DDR interface control register (RCC_DDRITFCR) . . . . . . . . . . . 713
10.7.76 RCC ADC kernel clock selection register (RCC_ADCCKSELR) . . . . . 718
10.7.77 RCC LPTIM4 and 5 kernel clock selection register
(RCC_LPTIM45CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
10.7.78 RCC LPTIM2 and 3 kernel clock selection register
(RCC_LPTIM23CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
10.7.79 RCC LPTIM1 kernel clock selection register
(RCC_LPTIM1CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
10.7.80 RCC boot control register (RCC_MP_BOOTCR) . . . . . . . . . . . . . . . . 722
10.7.81 RCC stop request set register (RCC_MP_SREQSETR) . . . . . . . . . . . 723
10.7.82 RCC stop request clear register (RCC_MP_SREQCLRR) . . . . . . . . . 724
10.7.83 RCC global control register (RCC_MP_GCR) . . . . . . . . . . . . . . . . . . . 725
10.7.84 RCC application reset control register (RCC_MP_APRSTCR) . . . . . . 726
10.7.85 RCC application reset status register (RCC_MP_APRSTSR) . . . . . . . 727
10.7.86 RCC backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . 728
10.7.87 RCC reset duration and LSI control register (RCC_RDLSICR) . . . . . . 729
10.7.88 RCC clock source interrupt enable register (RCC_MP_CIER) . . . . . . 732
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10.7.89 RCC clock source interrupt flag register (RCC_MP_CIFR) . . . . . . . . . 734
10.7.90 RCC clock source interrupt enable register (RCC_MC_CIER) . . . . . . 735
10.7.91 RCC clock source interrupt flag register (RCC_MC_CIFR) . . . . . . . . . 738
10.7.92 RCC PWR_LP delay control register (RCC_PWRLPDLYCR) . . . . . . . 740
10.7.93 RCC APB1 peripheral reset set register (RCC_APB1RSTSETR) . . . . 740
10.7.94 RCC APB1 peripheral reset clear register (RCC_APB1RSTCLRR) . . 744
10.7.95 RCC APB2 peripheral reset set register (RCC_APB2RSTSETR) . . . . 747
10.7.96 RCC APB2 peripheral reset clear register (RCC_APB2RSTCLRR) . . 748
10.7.97 RCC APB3 peripheral reset set register (RCC_APB3RSTSETR) . . . . 750
10.7.98 RCC APB3 peripheral reset clear register (RCC_APB3RSTCLRR) . . 753
10.7.99 RCC AHB2 peripheral reset set register (RCC_AHB2RSTSETR) . . . . 755
10.7.100 RCC AHB2 peripheral reset clear register (RCC_AHB2RSTCLRR) . . 757
10.7.101 RCC AHB3 peripheral reset set register (RCC_AHB3RSTSETR) . . . . 759
10.7.102 RCC AHB3 peripheral reset clear register (RCC_AHB3RSTCLRR) . . 761
10.7.103 RCC AHB4 peripheral reset set register (RCC_AHB4RSTSETR) . . . . 763
10.7.104 RCC AHB4 peripheral reset clear register (RCC_AHB4RSTCLRR) . . 765
10.7.105 RCC APB4 peripheral reset set register (RCC_APB4RSTSETR) . . . . 767
10.7.106 RCC APB4 peripheral reset clear register (RCC_APB4RSTCLRR) . . 767
10.7.107 RCC APB5 peripheral reset set register (RCC_APB5RSTSETR) . . . . 768
10.7.108 RCC APB5 peripheral reset clear register (RCC_APB5RSTCLRR) . . 770
10.7.109 RCC AHB5 peripheral reset set register (RCC_AHB5RSTSETR) . . . . 771
10.7.110 RCC AHB5 peripheral reset clear register (RCC_AHB5RSTCLRR) . . 772
10.7.111 RCC AHB6 peripheral reset set register (RCC_AHB6RSTSETR) . . . . 773
10.7.112 RCC AHB6 peripheral reset clear register (RCC_AHB6RSTCLRR) . . 775
10.7.113 RCC AHB6 secure peripheral reset set register
(RCC_TZAHB6RSTSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
10.7.114 RCC AHB6 secure peripheral reset clear register
(RCC_TZAHB6RSTCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
10.7.115 RCC global reset control set register
(RCC_MP_GRSTCSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
10.7.116 RCC APB1 peripheral enable for MPU set register
(RCC_MP_APB1ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
10.7.117 RCC APB1 peripheral enable for MCU set register
(RCC_MC_APB1ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
10.7.118 RCC APB1 peripheral enable for MPU clear register
(RCC_MP_APB1ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
10.7.119 RCC APB1 peripheral enable for MCU clear register
(RCC_MC_APB1ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
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10.7.120 RCC APB2 peripheral enable for MPU set register
(RCC_MP_APB2ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
10.7.121 RCC APB2 peripheral enable for MCU set register
(RCC_MC_APB2ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
10.7.122 RCC APB2 peripheral enable for MPU clear register
(RCC_MP_APB2ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
10.7.123 RCC APB2 peripheral enable for MCU clear register
(RCC_MC_APB2ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
10.7.124 RCC APB3 peripheral enable for MPU set register
(RCC_MP_APB3ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
10.7.125 RCC APB3 peripheral enable for MCU set register
(RCC_MC_APB3ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
10.7.126 RCC APB3 peripheral enable for MPU clear register
(RCC_MP_APB3ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
10.7.127 RCC APB3 peripheral enable for MCU clear register
(RCC_MC_APB3ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
10.7.128 RCC APB4 peripheral enable for MCU set register
(RCC_MC_APB4ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
10.7.129 RCC APB4 peripheral enable for MPU set register
(RCC_MP_APB4ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
10.7.130 RCC APB4 peripheral enable for MCU clear register
(RCC_MC_APB4ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
10.7.131 RCC APB4 peripheral enable for MPU clear register
(RCC_MP_APB4ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
10.7.132 RCC APB5 peripheral enable for MCU set register
(RCC_MC_APB5ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
10.7.133 RCC APB5 peripheral enable for MPU set register
(RCC_MP_APB5ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
10.7.134 RCC APB5 peripheral enable for MCU clear register
(RCC_MC_APB5ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
10.7.135 RCC APB5 peripheral enable for MPU clear register
(RCC_MP_APB5ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
10.7.136 RCC AHB5 peripheral enable for MCU set register
(RCC_MC_AHB5ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
10.7.137 RCC AHB5 peripheral enable for MPU set register
(RCC_MP_AHB5ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
10.7.138 RCC AHB5 peripheral enable for MCU clear register
(RCC_MC_AHB5ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
10.7.139 RCC AHB5 peripheral enable for MPU clear register
(RCC_MP_AHB5ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
10.7.140 RCC AHB6 peripheral enable for MPU set register
(RCC_MP_AHB6ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838
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10.7.141 RCC AHB6 peripheral enable for MCU set register
(RCC_MC_AHB6ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
10.7.142 RCC AHB6 peripheral enable for MPU clear register
(RCC_MP_AHB6ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
10.7.143 RCC AHB6 peripheral enable for MCU clear register
(RCC_MC_AHB6ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
10.7.144 RCC AHB6 secure peripheral enable for MPU set register
(RCC_MP_TZAHB6ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
10.7.145 RCC AHB6 secure peripheral enable for MPU clear register
(RCC_MP_TZAHB6ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
10.7.146 RCC AHB2 peripheral enable for MPU set register
(RCC_MP_AHB2ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
10.7.147 RCC AHB2 peripheral enable for MCU set register
(RCC_MC_AHB2ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849
10.7.148 RCC AHB2 peripheral enable for MPU clear register
(RCC_MP_AHB2ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
10.7.149 RCC AHB2 peripheral enable for MCU clear register
(RCC_MC_AHB2ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853
10.7.150 RCC AHB3 peripheral enable for MPU set register
(RCC_MP_AHB3ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
10.7.151 RCC AHB3 peripheral enable for MCU set register
(RCC_MC_AHB3ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857
10.7.152 RCC AHB3 peripheral enable for MPU clear register
(RCC_MP_AHB3ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859
10.7.153 RCC AHB3 peripheral enable for MCU clear register
(RCC_MC_AHB3ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861
10.7.154 RCC AHB4 peripheral enable for MPU set register
(RCC_MP_AHB4ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
10.7.155 RCC AHB4 peripheral enable for MCU set register
(RCC_MC_AHB4ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
10.7.156 RCC AHB4 peripheral enable for MPU clear register
(RCC_MP_AHB4ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
10.7.157 RCC AHB4 peripheral enable for MCU clear register
(RCC_MC_AHB4ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
10.7.158 RCC AXI peripheral enable for MCU set register
(RCC_MC_AXIMENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
10.7.159 RCC AXI peripheral enable for MCU clear register
(RCC_MC_AXIMENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
10.7.160 RCC MLAHB peripheral enable for MCU set register
(RCC_MC_MLAHBENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
10.7.161 RCC MLAHB peripheral enable for MCU clear register
(RCC_MC_MLAHBENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
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10.7.162 RCC MLAHB peripheral enable for MPU set register
(RCC_MP_MLAHBENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
10.7.163 RCC MLAHB peripheral enable for MPU clear register
(RCC_MP_MLAHBENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
10.7.164 RCC APB1 sleep clock enable for MPU set register
(RCC_MP_APB1LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
10.7.165 RCC APB1 sleep clock enable for MCU set register
(RCC_MC_APB1LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
10.7.166 RCC APB1 sleep clock enable MPU clear register
(RCC_MP_APB1LPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
10.7.167 RCC APB1 sleep clock enable MCU clear register
(RCC_MC_APB1LPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
10.7.168 RCC APB2 sleep clock enable for MPU set register
(RCC_MP_APB2LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895
10.7.169 RCC APB2 sleep clock enable for MCU set register
(RCC_MC_APB2LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898
10.7.170 RCC APB2 sleep clock enable for MPU clear register
(RCC_MP_APB2LPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901
10.7.171 RCC APB2 sleep clock enable for MCU clear register
(RCC_MC_APB2LPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
10.7.172 RCC APB3 sleep clock enable for MPU set register
(RCC_MP_APB3LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
10.7.173 RCC APB3 sleep clock enable for MCU set register
(RCC_MC_APB3LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909
10.7.174 RCC APB3 sleep clock enable for MPU clear register
(RCC_MP_APB3LPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910
10.7.175 RCC APB3 sleep clock enable for MCU clear register
(RCC_MC_APB3LPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913
10.7.176 RCC APB4 sleep clock enable for MCU set register
(RCC_MC_APB4LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914
10.7.177 RCC APB4 sleep clock enable for MPU set register
(RCC_MP_APB4LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916
10.7.178 RCC APB4 sleep clock enable for MCU clear register
(RCC_MC_APB4LPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918
10.7.179 RCC APB4 sleep clock enable for MPU clear register
(RCC_MP_APB4LPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920
10.7.180 RCC APB5 sleep clock enable for MCU set register
(RCC_MC_APB5LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
10.7.181 RCC APB5 sleep clock enable for MPU set register
(RCC_MP_APB5LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924
10.7.182 RCC APB5 sleep clock enable for MCU clear register
(RCC_MC_APB5LPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
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10.7.183 RCC APB5 sleep clock enable for MPU clear register
(RCC_MP_APB5LPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
10.7.184 RCC AHB5 peripheral enable for MPU set register
(RCC_MP_AHB5LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932
10.7.185 RCC AHB5 peripheral enable for MCU set register
(RCC_MC_AHB5LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934
10.7.186 RCC AHB5 sleep clock enable for MPU clear register
(RCC_MP_AHB5LPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
10.7.187 RCC AHB5 sleep clock enable for MCU clear register
(RCC_MC_AHB5LPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
10.7.188 RCC AHB6 sleep clock enable for MPU set register
(RCC_MP_AHB6LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
10.7.189 RCC AHB6 sleep clock enable for MCU set register
(RCC_MC_AHB6LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943
10.7.190 RCC AHB6 sleep clock enable for MPU clear register
(RCC_MP_AHB6LPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
10.7.191 RCC AHB6 sleep clock enable for MCU clear register
(RCC_MC_AHB6LPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
10.7.192 RCC AHB6 secure sleep clock enable for MPU set register
(RCC_MP_TZAHB6LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952
10.7.193 RCC AHB6 secure sleep clock enable for MPU clear register
(RCC_MP_TZAHB6LPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953
10.7.194 RCC AHB2 sleep clock enable for MPU set register
(RCC_MP_AHB2LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
10.7.195 RCC AHB2 sleep clock enable for MCU set register
(RCC_MC_AHB2LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
10.7.196 RCC AHB2 sleep clock enable for MPU clear register
(RCC_MP_AHB2LPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
10.7.197 RCC AHB2 sleep clock enable for MCU clear register
(RCC_MC_AHB2LPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960
10.7.198 RCC AHB3 sleep clock enable for MPU set register
(RCC_MP_AHB3LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
10.7.199 RCC AHB3 sleep clock enable for MCU set register
(RCC_MC_AHB3LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
10.7.200 RCC AHB3 sleep clock enable for MPU clear register
(RCC_MP_AHB3LPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966
10.7.201 RCC AHB3 sleep clock enable for MCU clear register
(RCC_MC_AHB3LPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
10.7.202 RCC AHB4 sleep clock enable for MPU set register
(RCC_MP_AHB4LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970
10.7.203 RCC AHB4 sleep clock enable for MCU set register
(RCC_MC_AHB4LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
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10.7.204 RCC AHB4 sleep clock enable for MPU clear register
(RCC_MP_AHB4LPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
10.7.205 RCC AHB4 sleep clock enable for MCU clear register
(RCC_MC_AHB4LPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976
10.7.206 RCC AXI sleep clock enable for MPU set register
(RCC_MP_AXIMLPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
10.7.207 RCC AXI sleep clock enable for MCU set register
(RCC_MC_AXIMLPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
10.7.208 RCC AXI sleep clock enable for MPU clear register
(RCC_MP_AXIMLPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980
10.7.209 RCC AXI sleep clock enable for MCU clear register
(RCC_MC_AXIMLPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
10.7.210 RCC MLAHB sleep clock enable for MPU set register
(RCC_MP_MLAHBLPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
10.7.211 RCC MLAHB sleep clock enable for MCU set register
(RCC_MC_MLAHBLPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
10.7.212 RCC MLAHB sleep clock enable for MPU clear register
(RCC_MP_MLAHBLPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984
10.7.213 RCC MLAHB sleep clock enable for MCU clear register
(RCC_MC_MLAHBLPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
10.7.214 RCC BOOTROM reset status clear register
(RCC_BR_RSTSCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986
10.7.215 RCC MCU reset status clear register (RCC_MC_RSTSCLRR) . . . . . 988
10.7.216 RCC MPU reset status clear register (RCC_MP_RSTSCLRR) . . . . . . 989
10.7.217 RCC MPU reset status set register (RCC_MP_RSTSSETR) . . . . . . . 992
10.7.218 RCC IWDG clock freeze set register (RCC_MP_IWDGFZSETR) . . . . 994
10.7.219 RCC IWDG clock freeze clear register
(RCC_MP_IWDGFZCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
10.7.220 RCC version register (RCC_VERR) . . . . . . . . . . . . . . . . . . . . . . . . . . 996
10.7.221 RCC ID register (RCC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
10.7.222 RCC size ID register (RCC_SIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
10.8
11
RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997
Hardware semaphore (HSEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
11.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
11.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
11.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
11.3.1
HSEM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
11.3.2
HSEM internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
11.3.3
HSEM lock procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
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11.4
11.3.4
HSEM write/read/read lock register address . . . . . . . . . . . . . . . . . . . 1030
11.3.5
HSEM unlock procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
11.3.6
HSEM COREID semaphore clear . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
11.3.7
HSEM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
11.3.8
AHB bus master ID verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
HSEM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034
11.4.1
HSEM register semaphore x (HSEM_Rx) . . . . . . . . . . . . . . . . . . . . . 1034
11.4.2
HSEM read lock register semaphore x (HSEM_RLRx) . . . . . . . . . . . 1035
11.4.3
HSEM interrupt enable register (HSEM_CnIER) . . . . . . . . . . . . . . . . 1036
11.4.4
HSEM interrupt clear register (HSEM_CnICR) . . . . . . . . . . . . . . . . . 1036
11.4.5
HSEM interrupt status register (HSEM_CnISR) . . . . . . . . . . . . . . . . 1036
11.4.6
HSEM interrupt status register (HSEM_CnMISR) . . . . . . . . . . . . . . . 1037
11.4.7
HSEM clear register (HSEM_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037
11.4.8
HSEM clear semaphore key register (HSEM_KEYR) . . . . . . . . . . . . 1038
11.4.9
HSEM hardware configuration register 2 (HSEM_HWCFGR2) . . . . . 1038
11.4.10 HSEM hardware configuration register 1 (HSEM_HWCFGR1) . . . . . 1039
11.4.11
HSEM version register (HSEM_VERR) . . . . . . . . . . . . . . . . . . . . . . . 1039
11.4.12 HSEM identification register (HSEM_IPIDR) . . . . . . . . . . . . . . . . . . . 1039
11.4.13 HSEM size identification register (HSEM_SIDR) . . . . . . . . . . . . . . . . 1040
11.4.14 HSEM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041
12
Inter-processor communication controller (IPCC) . . . . . . . . . . . . . . 1043
12.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043
12.2
IPCC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043
12.3
IPCC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043
12.4
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12.3.1
IPCC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044
12.3.2
IPCC Simplex channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044
12.3.3
IPCC Half-duplex channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047
12.3.4
IPCC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
IPCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
12.4.1
IPCC processor 1 control register (IPCC_C1CR) . . . . . . . . . . . . . . . 1051
12.4.2
IPCC processor 1 mask register (IPCC_C1MR) . . . . . . . . . . . . . . . . 1051
12.4.3
IPCC processor 1 status set clear register (IPCC_C1SCR) . . . . . . . 1052
12.4.4
IPCC processor 1 to processor 2 status register
(IPCC_C1TOC2SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
12.4.5
IPCC processor 2 control register (IPCC_C2CR) . . . . . . . . . . . . . . . 1053
12.4.6
IPCC processor 2 mask register (IPCC_C2MR) . . . . . . . . . . . . . . . . 1053
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12.4.7
IPCC processor 2 status set clear register (IPCC_C2SCR) . . . . . . . 1054
12.4.8
IPCC processor 2 to processor 1 status register
(IPCC_C2TOC1SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055
12.4.9
IPCC hardware configuration register (IPCC_HWCFGR) . . . . . . . . . 1055
12.4.10 IPCC version register (IPCC_VERR) . . . . . . . . . . . . . . . . . . . . . . . . . 1056
12.4.11 IPCC identification register (IPCC_IPIDR) . . . . . . . . . . . . . . . . . . . . . 1056
12.4.12 IPCC size identification register (IPCC_SIDR) . . . . . . . . . . . . . . . . . 1056
12.4.13 IPCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
13
General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
13.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
13.2
GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
13.3
GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
13.3.1
General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
13.3.2
I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . 1061
13.3.3
I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
13.3.4
I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
13.3.5
I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
13.3.6
GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
13.3.7
I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
13.3.8
External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
13.3.9
Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
13.3.10 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
13.3.11 I/O compensation cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
13.3.12 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
13.3.13 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066
13.3.14 Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . 1067
13.3.15 Using the GPIO pins in the backup supply domain . . . . . . . . . . . . . . 1067
13.3.16 TrustZone security (only for GPIOZ) . . . . . . . . . . . . . . . . . . . . . . . . . 1067
13.4
GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
13.4.1
GPIO port mode register (GPIOx_MODER)
(x = A to K, Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
13.4.2
GPIO port output type register (GPIOx_OTYPER)
(x = A to K, Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
13.4.3
GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to K, Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
13.4.4
GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to K, Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
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13.4.5
GPIO port input data register (GPIOx_IDR)
(x = A to K, Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
13.4.6
GPIO port output data register (GPIOx_ODR)
(x = A to K, Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071
13.4.7
GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to K, Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071
13.4.8
GPIO port configuration lock register (GPIOx_LCKR)
(x = A to K, Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
13.4.9
GPIO alternate function low register (GPIOx_AFRL)
(x = A to K, Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
13.4.10 GPIO alternate function high register (GPIOx_AFRH)
(x = A to K, Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074
13.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to K, Z) . . . . . . . . . 1075
13.4.12 GPIO secure configuration register (GPIOZ_SECCFGR) . . . . . . . . . 1075
13.4.13 GPIO hardware configuration register 10 (GPIOx_HWCFGR10)
(x = A to K, Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
13.4.14 GPIO hardware configuration register 9 (GPIOx_HWCFGR9)
(x = A to K, Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
13.4.15 GPIO hardware configuration register 8 (GPIOx_HWCFGR8)
(x = A to K, Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
13.4.16 GPIO hardware configuration register 7 (GPIOx_HWCFGR7)
(x = A to K, Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078
13.4.17 GPIO hardware configuration register 6 (GPIOx_HWCFGR6)
(x = A to K, Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078
13.4.18 GPIO hardware configuration register 5 (GPIOx_HWCFGR5)
(x = A to K, Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079
13.4.19 GPIO hardware configuration register 4 (GPIOx_HWCFGR4)
(x = A to K, Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079
13.4.20 GPIO hardware configuration register 3 (GPIOx_HWCFGR3)
(x = A to K, Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079
13.4.21 GPIO hardware configuration register 2 (GPIOx_HWCFGR2)
(x = A to K, Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080
13.4.22 GPIO hardware configuration register 1 (GPIOx_HWCFGR1)
(x = A to K, Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080
13.4.23 GPIO hardware configuration register 0 (GPIOx_HWCFGR0)
(x = A to K, Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080
13.4.24 GPIO version register (GPIOx_VERR) (x = A to K, Z) . . . . . . . . . . . . 1081
13.4.25 GPIO identification register (GPIOx_IPIDR) (x = A to K, Z) . . . . . . . . 1081
13.4.26 GPIO size identification register (GPIOx_SIDR) (x = A to K, Z) . . . . . 1082
13.4.27 GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
14
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System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . 1085
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14.1
I/O compensation cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
14.2
Ethernet clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
14.3
SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
14.3.1
SYSCFG boot pins control register (SYSCFG_BOOTR) . . . . . . . . . . 1088
14.3.2
SYSCFG peripheral mode configuration set register
(SYSCFG_PMCSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089
14.3.3
SYSCFG peripheral mode configuration clear register
(SYSCFG_PMCCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091
14.3.4
SYSCFG IO control set register (SYSCFG_IOCTRLSETR) . . . . . . . 1094
14.3.5
SYSCFG IO control clear register (SYSCFG_IOCTRLCLRR) . . . . . 1095
14.3.6
SYSCFG interconnect control register (SYSCFG_ICNR) . . . . . . . . . 1097
14.3.7
SYSCFG compensation cell control register (SYSCFG_CMPCR) . . 1099
14.3.8
SYSCFG compensation cell enable set register
(SYSCFG_CMPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100
14.3.9
SYSCFG compensation cell enable clear register
(SYSCFG_CMPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101
14.3.10 SYSCFG control timer break register (SYSCFG_CBR) . . . . . . . . . . 1102
14.3.11 SYSCFG version register (SYSCFG_VERR) . . . . . . . . . . . . . . . . . . 1103
14.3.12 SYSCFG identification register (SYSCFG_IPIDR) . . . . . . . . . . . . . . 1103
14.3.13 SYSCFG size identification register (SYSCFG_SIDR) . . . . . . . . . . . 1104
14.3.14 SYSCFG interface register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105
15
Extended TrustZone® protection controller (ETZPC) . . . . . . . . . . . 1107
15.1
ETZPC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1107
15.2
ETZPC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1107
15.3
Extended TrustZone architecture and ETZPC . . . . . . . . . . . . . . . . . . . .1107
15.4
ETZPC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1109
15.5
STM32MP153 security architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . .1109
15.6
STM32MP153 MCU resource isolation . . . . . . . . . . . . . . . . . . . . . . . . . 1112
15.7
ETZPC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119
15.7.1
ETZPC ROM secure size definition (ETZPC_TZMA0_SIZE) . . . . . . 1120
15.7.2
ETZPC RAM secure size definition (ETZPC_TZMA1_SIZE) . . . . . . 1121
15.7.3
ETZPC securable peripheral control register x
(ETZPC_DECPROTx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
15.7.4
ETZPC decprot lock x register (ETZPC_DECPROT_LOCKx) . . . . . 1123
15.7.5
ETZPC HW configuration register (ETZPC_HWCFGR) . . . . . . . . . . 1127
15.7.6
ETZPC version register (ETZPC_VERR) . . . . . . . . . . . . . . . . . . . . . 1127
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ETZPC identification register (ETZPC_IDR) . . . . . . . . . . . . . . . . . . . 1128
15.7.8
ETZPC size identification register (ETZPC_SIDR) . . . . . . . . . . . . . . 1128
15.7.9
ETZPC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129
Block interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131
16.1
16.2
17
15.7.7
Peripheral interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1131
16.1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131
16.1.2
Connection overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131
MDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1150
MDMA controller (MDMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152
17.1
MDMA introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1152
17.2
MDMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1152
17.3
MDMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1154
17.3.1
MDMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154
17.3.2
MDMA internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154
17.3.3
MDMA overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154
17.3.4
MDMA channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1156
17.3.5
Source, destination and transfer modes . . . . . . . . . . . . . . . . . . . . . . 1156
17.3.6
Pointer update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1156
17.3.7
MDMA buffer transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1157
17.3.8
Request arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1158
17.3.9
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1158
17.3.10 Block transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1158
17.3.11 Block repeat mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1159
17.3.12 Linked-list mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1159
17.3.13 MDMA transfer completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1159
17.3.14 MDMA transfer suspension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1159
17.3.15 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1160
28/3930
17.4
MDMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1160
17.5
MDMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1161
17.5.1
MDMA global interrupt status register (MDMA_GISR0) . . . . . . . . . . 1161
17.5.2
MDMA secure global interrupt status register (MDMA_SGISR0) . . . 1161
17.5.3
MDMA channel x interrupt status register (MDMA_CxISR) . . . . . . . . 1162
17.5.4
MDMA channel x interrupt flag clear register (MDMA_CxIFCR) . . . . 1163
17.5.5
MDMA channel x error status register (MDMA_CxESR) . . . . . . . . . . 1164
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17.5.6
MDMA channel x control register (MDMA_CxCR) . . . . . . . . . . . . . . . 1165
17.5.7
MDMA channel x transfer configuration register (MDMA_CxTCR) . . 1167
17.5.8
MDMA channel x block number of data register (MDMA_CxBNDTR) 1170
17.5.9
MDMA channel x source address register (MDMA_CxSAR) . . . . . . . 1171
17.5.10 MDMA channel x destination address register (MDMA_CxDAR) . . . 1172
17.5.11 MDMA channel x block repeat address update register
(MDMA_CxBRUR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1172
17.5.12 MDMA channel x link address register (MDMA_CxLAR) . . . . . . . . . . 1173
17.5.13 MDMA channel x trigger and bus selection register
(MDMA_CxTBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174
17.5.14 MDMA channel x mask address register (MDMA_CxMAR) . . . . . . . 1174
17.5.15 MDMA channel x mask data register (MDMA_CxMDR) . . . . . . . . . . 1175
17.5.16 MDMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175
18
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . 1177
18.1
DMA introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1177
18.2
DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1177
18.3
DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1179
18.3.1
DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
18.3.2
DMA overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
18.3.3
DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1180
18.3.4
DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1180
18.3.5
Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1180
18.3.6
DMA streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1181
18.3.7
Source, destination and transfer modes . . . . . . . . . . . . . . . . . . . . . . 1181
18.3.8
Pointer incrementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184
18.3.9
Circular mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185
18.3.10 Double-buffer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185
18.3.11 Programmable data width, packing/unpacking, endianness . . . . . . . 1186
18.3.12 Single and burst transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187
18.3.13 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1188
18.3.14 DMA transfer completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191
18.3.15 DMA transfer suspension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192
18.3.16 Flow controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193
18.3.17 Summary of the possible DMA configurations . . . . . . . . . . . . . . . . . . 1194
18.3.18 Stream configuration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194
18.3.19 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195
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18.4
DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1196
18.5
DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1197
18.5.1
DMA low interrupt status register (DMA_LISR) . . . . . . . . . . . . . . . . . 1197
18.5.2
DMA high interrupt status register (DMA_HISR) . . . . . . . . . . . . . . . . 1198
18.5.3
DMA low interrupt flag clear register (DMA_LIFCR) . . . . . . . . . . . . . 1199
18.5.4
DMA high interrupt flag clear register (DMA_HIFCR) . . . . . . . . . . . . 1199
18.5.5
DMA stream x configuration register (DMA_SxCR) . . . . . . . . . . . . . . 1200
18.5.6
DMA stream x number of data register (DMA_SxNDTR) . . . . . . . . . 1203
18.5.7
DMA stream x peripheral address register (DMA_SxPAR) . . . . . . . . 1203
18.5.8
DMA stream x memory 0 address register
(DMA_SxM0AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204
18.5.9
DMA stream x memory 1 address register
(DMA_SxM1AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204
18.5.10 DMA stream x FIFO control register (DMA_SxFCR) . . . . . . . . . . . . . 1205
18.5.11 DMA hardware configuration 2 register (DMA_HWCFGR2) . . . . . . . 1206
18.5.12 DMA hardware configuration 1 register (DMA_HWCFGR1) . . . . . . . 1207
18.5.13 DMA version register (DMA_VERR) . . . . . . . . . . . . . . . . . . . . . . . . . 1208
18.5.14 DMA identification register (DMA_IPDR) . . . . . . . . . . . . . . . . . . . . . . 1208
18.5.15 DMA size identification register (DMA_SIDR) . . . . . . . . . . . . . . . . . . 1209
18.5.16 DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1209
19
DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . 1214
19.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1214
19.2
DMAMUX main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215
19.3
DMAMUX implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215
19.4
19.3.1
DMAMUX instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215
19.3.2
DMAMUX mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215
DMAMUX functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218
19.4.1
DMAMUX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218
19.4.2
DMAMUX signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219
19.4.3
DMAMUX channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219
19.4.4
DMAMUX request line multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219
19.4.5
DMAMUX request generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1222
19.5
DMAMUX interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223
19.6
DMAMUX registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224
19.6.1
30/3930
DMAMUX request line multiplexer channel x configuration register
(DMAMUX_CxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224
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19.6.2
DMAMUX request line multiplexer interrupt channel status register
(DMAMUX_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225
19.6.3
DMAMUX request line multiplexer interrupt clear flag register
(DMAMUX_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225
19.6.4
DMAMUX request generator channel x configuration register
(DMAMUX_RGxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226
19.6.5
DMAMUX request generator interrupt status register
(DMAMUX_RGSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227
19.6.6
DMAMUX request generator interrupt clear flag register
(DMAMUX_RGCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227
19.6.7
DMAMUX size identification register (DMAMUX_SIDR) . . . . . . . . . . 1228
19.6.8
DMAMUX IP identification register (DMAMUX_IPIDR) . . . . . . . . . . . 1228
19.6.9
DMAMUX version register (DMAMUX_VERR) . . . . . . . . . . . . . . . . . 1228
19.6.10 DMAMUX hardware configuration 1 register
(DMAMUX_HWCFGR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229
19.6.11 DMAMUX hardware configuration 2 register
(DMAMUX_HWCFGR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229
19.6.12 DMAMUX register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1230
20
21
22
Interrupt list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233
20.1
NVIC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233
20.2
GIC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1238
20.3
EXTI events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245
Nested Vectored Interrupt Controllers (NVIC) . . . . . . . . . . . . . . . . . 1249
21.1
NVIC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249
21.2
SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249
21.3
Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249
Global interrupt controller (GIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250
22.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250
22.2
GIC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250
22.3
GIC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250
22.4
Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251
22.4.1
Software generated interrupts (SGI) . . . . . . . . . . . . . . . . . . . . . . . . . 1251
22.4.2
Private peripheral interrupts (PPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252
22.4.3
Shared peripheral interrupts (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253
22.4.4
Interrupt priority formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253
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22.5
GIC distributor (GICD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253
22.5.1
GICD control register (GICD_CTLR) . . . . . . . . . . . . . . . . . . . . . . . . . 1253
22.5.2
GICD control non-secure access register (GICD_CTLRNS) . . . . . . . 1254
22.5.3
GICD interrupt controller type register (GICD_TYPER) . . . . . . . . . . . 1254
22.5.4
GICD implementer identification register (GICD_IIDR) . . . . . . . . . . . 1255
22.5.5
GICD interrupt group register x (GICD_IGROUPRx) . . . . . . . . . . . . . 1255
22.5.6
GICD interrupt set-enable register (GICD_ISENABLER0) . . . . . . . . 1256
22.5.7
GICD interrupt set-enable register x (GICD_ISENABLERx) . . . . . . . 1256
22.5.8
GICD interrupt clear-enable register (GICD_ICENABLER0) . . . . . . . 1256
22.5.9
GICD interrupt clear-enable register x (GICD_ICENABLERx) . . . . . 1257
22.5.10 GICD interrupt set-pending register x (GICD_ISPENDRx) . . . . . . . . 1257
22.5.11 GICD interrupt clear-pending register x (GICD_ICPENDRx) . . . . . . . 1257
22.5.12 GICD interrupt set-active register x (GICD_ISACTIVERx) . . . . . . . . 1258
22.5.13 GICD interrupt clear-active register x (GICD_ICACTIVERx) . . . . . . . 1258
22.5.14 GICD interrupt priority register x (GICD_IPRIORITYRx) . . . . . . . . . . 1258
22.5.15 GICD interrupt processor target register x (GICD_ITARGETSRx) . . 1259
22.5.16 GICD interrupt processor target register x (GICD_ITARGETSRx) . . 1260
22.5.17 GICD interrupt configuration register (GICD_ICFGR0) . . . . . . . . . . . 1260
22.5.18 GICD interrupt configuration register (GICD_ICFGR1) . . . . . . . . . . . 1261
22.5.19 GICD interrupt configuration register x (GICD_ICFGRx) . . . . . . . . . . 1262
22.5.20 GICD private peripheral interrupt status register (GICD_PPISR) . . . 1263
22.5.21 GICD shared peripheral interrupt register x (GICD_SPISRx) . . . . . . 1264
22.5.22 GICD software generated interrupt register (GICD_SGIR) . . . . . . . . 1264
22.5.23 GICD SGI clear-pending register x (GICD_CPENDSGIRx) . . . . . . . 1265
22.5.24 GICD SGI set-pending register x (GICD_SPENDSGIRx) . . . . . . . . . 1267
22.5.25 GICD peripheral ID4 register (GICD_PIDR4) . . . . . . . . . . . . . . . . . . 1268
22.5.26 GICD peripheral ID5 to ID7 register x (GICD_PIDRx) . . . . . . . . . . . . 1268
22.5.27 GICD peripheral ID0 register (GICD_PIDR0) . . . . . . . . . . . . . . . . . . 1269
22.5.28 GICD peripheral ID1 register (GICD_PIDR1) . . . . . . . . . . . . . . . . . . 1269
22.5.29 GICD peripheral ID2 register (GICD_PIDR2) . . . . . . . . . . . . . . . . . . 1269
22.5.30 GICD peripheral ID3 register (GICD_PIDR3) . . . . . . . . . . . . . . . . . . 1270
22.5.31 GICD component ID0 register (GICD_CIDR0) . . . . . . . . . . . . . . . . . 1270
22.5.32 GICD component ID1 register (GICD_CIDR1) . . . . . . . . . . . . . . . . . 1270
22.5.33 GICD component ID2 register (GICD_CIDR2) . . . . . . . . . . . . . . . . . 1271
22.5.34 GICD component ID3 register (GICD_CIDR3) . . . . . . . . . . . . . . . . . 1271
22.5.35 GICD register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271
22.6
32/3930
GIC CPU Interface (GICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275
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22.6.1
GICC control register (GICC_CTLR) . . . . . . . . . . . . . . . . . . . . . . . . . 1275
22.6.2
GICC control non-secure access register (GICC_CTLRNS) . . . . . . . 1276
22.6.3
GICC input priority mask register (GICC_PMR) . . . . . . . . . . . . . . . . 1277
22.6.4
GICC binary point register (GICC_BPR) . . . . . . . . . . . . . . . . . . . . . . 1277
22.6.5
GICC binary point non-secure access register (GICC_BPRNS) . . . . 1278
22.6.6
GICC interrupt acknowledge register (GICC_IAR) . . . . . . . . . . . . . . 1278
22.6.7
GICC end of interrupt register (GICC_EOIR) . . . . . . . . . . . . . . . . . . 1279
22.6.8
GICC running priority register (GICC_RPR) . . . . . . . . . . . . . . . . . . . 1279
22.6.9
GICC highest priority pending interrupt register (GICC_HPPIR) . . . . 1280
22.6.10 GICC aliased binary point register (GICC_ABPR) . . . . . . . . . . . . . . . 1280
22.6.11 GICC aliased interrupt acknowledge register (GICC_AIAR) . . . . . . . 1281
22.6.12 GICC aliased end of interrupt register (GICC_AEOIR) . . . . . . . . . . . 1281
22.6.13 GICC aliased highest priority pending interrupt register
(GICC_AHPPIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1282
22.6.14 GICC active priority register (GICC_APR0) . . . . . . . . . . . . . . . . . . . . 1282
22.6.15 GICC non-secure active priority register (GICC_NSAPR0) . . . . . . . . 1283
22.6.16 GICC interface identification register (GICC_IIDR) . . . . . . . . . . . . . . 1283
22.6.17 GICC deactivate interrupt register (GICC_DIR) . . . . . . . . . . . . . . . . . 1283
22.6.18 GICC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284
22.7
22.8
GIC virtual interface control, common (GICH) . . . . . . . . . . . . . . . . . . . 1286
22.7.1
GICH hypervisor control register (GICH_HCR) . . . . . . . . . . . . . . . . . 1286
22.7.2
GICH VGIC type register (GICH_VTR) . . . . . . . . . . . . . . . . . . . . . . . 1287
22.7.3
GICH virtual machine control register (GICH_VMCR) . . . . . . . . . . . . 1287
22.7.4
GICH maintenance interrupt status register (GICH_MISR) . . . . . . . . 1288
22.7.5
GICH end of interrupt status register (GICH_EISR0) . . . . . . . . . . . . 1289
22.7.6
GICH empty list status register (GICH_ELSR0) . . . . . . . . . . . . . . . . 1289
22.7.7
GICH active priority register (GICH_APR0) . . . . . . . . . . . . . . . . . . . . 1290
22.7.8
GICH list register x (GICH_LRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1290
22.7.9
GICH register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291
GIC virtual CPU interface (GICV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1292
22.8.1
GICV virtual machine control register (GICV_CTLR) . . . . . . . . . . . . 1292
22.8.2
GICV VM priority mask register (GICV_PMR) . . . . . . . . . . . . . . . . . . 1293
22.8.3
GICV VM binary point register (GICV_BPR) . . . . . . . . . . . . . . . . . . . 1294
22.8.4
GICV VM interrupt acknowledge register (GICV_IAR) . . . . . . . . . . . 1294
22.8.5
GICV VM end of interrupt register (GICV_EOIR) . . . . . . . . . . . . . . . 1294
22.8.6
GICV VM running priority register (GICV_RPR) . . . . . . . . . . . . . . . . 1295
22.8.7
GICV VM highest priority pending interrupt register (GICV_HPPIR) . 1295
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22.8.8
GICV VM aliased binary point register (GICV_ABPR) . . . . . . . . . . . . 1296
22.8.9
GICV VM aliased interrupt register (GICV_AIAR) . . . . . . . . . . . . . . . 1296
22.8.10 GICV VM aliased end of interrupt register (GICV_AEOIR) . . . . . . . . 1297
22.8.11 GICV VM aliased highest priority pending interrupt register
(GICV_AHPPIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1297
22.8.12 GICV VM active priority register (GICV_APR0) . . . . . . . . . . . . . . . . . 1298
22.8.13 GICV VM CPU interface identification register (GICV_IIDR) . . . . . . . 1298
22.8.14 GICV VM deactivate interrupt register (GICV_DIR) . . . . . . . . . . . . . . 1298
22.8.15 GICV register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299
23
Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . 1301
23.1
EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1301
23.2
EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1302
23.2.1
23.3
EXTI connections between peripherals and CPU . . . . . . . . . . . . . . . 1303
EXTI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1304
23.3.1
EXTI configurable event input wakeup . . . . . . . . . . . . . . . . . . . . . . . 1305
23.3.2
EXTI direct event input wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1306
23.3.3
EXTI mux selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1306
23.4
EXTI functional behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1307
23.5
EXTI TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1308
23.6
EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1310
23.6.1
EXTI rising trigger selection register (EXTI_RTSR1) . . . . . . . . . . . . . 1310
23.6.2
EXTI falling trigger selection register (EXTI_FTSR1) . . . . . . . . . . . . 1311
23.6.3
EXTI software interrupt event register (EXTI_SWIER1) . . . . . . . . . . 1311
23.6.4
EXTI rising edge pending register (EXTI_RPR1) . . . . . . . . . . . . . . . 1312
23.6.5
EXTI falling edge pending register (EXTI_FPR1) . . . . . . . . . . . . . . . 1312
23.6.6
EXTI TrustZone enable register (EXTI_TZENR1) . . . . . . . . . . . . . . . 1313
23.6.7
EXTI rising trigger selection register (EXTI_RTSR2) . . . . . . . . . . . . . 1313
23.6.8
EXTI falling trigger selection register (EXTI_FTSR2) . . . . . . . . . . . . 1314
23.6.9
EXTI software interrupt event register (EXTI_SWIER2) . . . . . . . . . . 1314
23.6.10 EXTI rising edge pending register (EXTI_RPR2) . . . . . . . . . . . . . . . 1314
23.6.11 EXTI falling edge pending register (EXTI_FPR2) . . . . . . . . . . . . . . . 1315
23.6.12 EXTI TrustZone enable register (EXTI_TZENR2) . . . . . . . . . . . . . . . 1315
23.6.13 EXTI rising trigger selection register (EXTI_RTSR3) . . . . . . . . . . . . . 1316
23.6.14 EXTI falling trigger selection register (EXTI_FTSR3) . . . . . . . . . . . . 1317
23.6.15 EXTI software interrupt event register (EXTI_SWIER3) . . . . . . . . . . 1318
23.6.16 EXTI rising edge pending register (EXTI_RPR3) . . . . . . . . . . . . . . . 1320
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23.6.17 EXTI falling edge pending register (EXTI_FPR3) . . . . . . . . . . . . . . . 1322
23.6.18 EXTI TrustZone enable register (EXTI_TZENR3) . . . . . . . . . . . . . . . 1323
23.6.19 EXTI external interrupt selection register 1 (EXTI_EXTICR1) . . . . . . 1323
23.6.20 EXTI external interrupt selection register 2 (EXTI_EXTICR2) . . . . . . 1325
23.6.21 EXTI external interrupt selection register 3 (EXTI_EXTICR3) . . . . . . 1327
23.6.22 EXTI external interrupt selection register 4 (EXTI_EXTICR4) . . . . . . 1329
23.6.23 EXTI CPU wakeup with interrupt mask register (EXTI_C1IMR1) . . . 1331
23.6.24 EXTI CPU2 wakeup with interrupt mask register (EXTI_C2IMR1) . . 1332
23.6.25 EXTI CPU2 wakeup with event mask register (EXTI_C2EMR1) . . . . 1332
23.6.26 EXTI CPU wakeup with interrupt mask register (EXTI_C1IMR2) . . . 1333
23.6.27 EXTI CPU2 wakeup with interrupt mask register (EXTI_C2IMR2) . . 1334
23.6.28 EXTI CPU2 wakeup with event mask register (EXTI_C2EMR2) . . . . 1334
23.6.29 EXTI CPU wakeup with interrupt mask register (EXTI_C1IMR3) . . . 1334
23.6.30 EXTI CPUm wakeup with interrupt mask register (EXTI_C2IMR3) . . 1335
23.6.31 EXTI CPU2 wakeup with event mask register (EXTI_C2EMR3) . . . . 1335
23.6.32 EXTI hardware configuration register x (EXTI_HWCFGRx) . . . . . . . 1336
23.6.33 EXTI hardware configuration register x (EXTI_HWCFGRx) . . . . . . . 1336
23.6.34 EXTI hardware configuration register x (EXTI_HWCFGRx) . . . . . . . 1337
23.6.35 EXTI hardware configuration register x (EXTI_HWCFGRx) . . . . . . . 1337
23.6.36 EXTI hardware configuration register 1 (EXTI_HWCFGR1) . . . . . . . 1337
23.6.37 EXTI IP version register (EXTI_VERR) . . . . . . . . . . . . . . . . . . . . . . . 1338
23.6.38 EXTI identification register (EXTI_IPIDR) . . . . . . . . . . . . . . . . . . . . . 1338
23.6.39 EXTI size ID register (EXTI_SIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1339
23.6.40 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1340
24
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . 1344
24.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1344
24.2
CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1344
24.3
CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1345
24.4
24.3.1
CRC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1345
24.3.2
CRC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1345
24.3.3
CRC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1345
CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1347
24.4.1
CRC data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1347
24.4.2
CRC independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . 1347
24.4.3
CRC control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1348
24.4.4
CRC initial value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1349
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24.4.5
CRC polynomial (CRC_POL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1349
24.4.6
CRC hardware configuration register (CRC_HWCFGR) . . . . . . . . . . 1349
24.4.7
CRC version register (CRC_VERR) . . . . . . . . . . . . . . . . . . . . . . . . . 1350
24.4.8
CRC identification register (CRC_IPIDR) . . . . . . . . . . . . . . . . . . . . . 1350
24.4.9
CRC size identification register (CRC_SIDR) . . . . . . . . . . . . . . . . . . 1351
24.4.10 CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1351
25
Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353
25.1
FMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353
25.2
FMC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354
25.3
FMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354
25.4
FMC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355
25.5
AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355
25.6
AXI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356
25.6.1
25.7
25.8
25.9
Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . 1356
External device address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357
25.7.1
NOR/PSRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1358
25.7.2
NAND flash memory address mapping . . . . . . . . . . . . . . . . . . . . . . . 1358
NOR flash/PSRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1360
25.8.1
External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361
25.8.2
Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . 1363
25.8.3
General timing rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1365
25.8.4
NOR flash/PSRAM controller asynchronous transactions . . . . . . . . . 1365
25.8.5
Synchronous transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1385
25.8.6
NOR/PSRAM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1391
NAND flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1403
25.9.1
External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1404
25.9.2
NAND flash supported memories and transactions . . . . . . . . . . . . . . 1405
25.9.3
Timing diagrams for NAND flash memory . . . . . . . . . . . . . . . . . . . . . 1406
25.9.4
NAND flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407
25.9.5
NAND flash prewait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1408
25.9.6
NAND ECC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1408
25.9.7
FMC command sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1411
25.9.8
NAND flash controller interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1418
25.9.9
NAND flash controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1419
25.10 FMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1443
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Quad-SPI interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447
26.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447
26.2
QUADSPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447
26.3
QUADSPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447
26.3.1
QUADSPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447
26.3.2
QUADSPI pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . 1448
26.3.3
QUADSPI command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1449
26.3.4
QUADSPI signal interface protocol modes . . . . . . . . . . . . . . . . . . . . 1451
26.3.5
QUADSPI indirect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1453
26.3.6
QUADSPI automatic status-polling mode . . . . . . . . . . . . . . . . . . . . . 1455
26.3.7
QUADSPI memory-mapped mode . . . . . . . . . . . . . . . . . . . . . . . . . . 1455
26.3.8
QUADSPI free-running clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . 1456
26.3.9
QUADSPI flash memory configuration . . . . . . . . . . . . . . . . . . . . . . . 1456
26.3.10 QUADSPI delayed data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457
26.3.11 QUADSPI configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457
26.3.12 QUADSPI use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1458
26.3.13 Sending the instruction only once . . . . . . . . . . . . . . . . . . . . . . . . . . . 1459
26.3.14 QUADSPI error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1460
26.3.15 QUADSPI busy bit and abort functionality . . . . . . . . . . . . . . . . . . . . . 1460
26.3.16 NCS behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1460
26.4
QUADSPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1462
26.5
QUADSPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1463
26.5.1
QUADSPI control register (QUADSPI_CR) . . . . . . . . . . . . . . . . . . . . 1463
26.5.2
QUADSPI device configuration register (QUADSPI_DCR) . . . . . . . . 1466
26.5.3
QUADSPI status register (QUADSPI_SR) . . . . . . . . . . . . . . . . . . . . 1467
26.5.4
QUADSPI flag clear register (QUADSPI_FCR) . . . . . . . . . . . . . . . . . 1468
26.5.5
QUADSPI data length register (QUADSPI_DLR) . . . . . . . . . . . . . . . 1468
26.5.6
QUADSPI communication configuration register (QUADSPI_CCR) . 1469
26.5.7
QUADSPI address register (QUADSPI_AR) . . . . . . . . . . . . . . . . . . . 1471
26.5.8
QUADSPI alternate-byte register (QUADSPI_ABR) . . . . . . . . . . . . . 1471
26.5.9
QUADSPI data register (QUADSPI_DR) . . . . . . . . . . . . . . . . . . . . . . 1472
26.5.10 QUADSPI polling status mask register (QUADSPI_PSMKR) . . . . . . 1472
26.5.11 QUADSPI polling status match register (QUADSPI_PSMAR) . . . . . 1473
26.5.12 QUADSPI polling interval register (QUADSPI_PIR) . . . . . . . . . . . . . 1473
26.5.13 QUADSPI low-power timeout register (QUADSPI_LPTR) . . . . . . . . . 1474
26.5.14 QUADSPI hardware configuration register (QUADSPI_HWCFGR) . 1474
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26.5.15 QUADSPI version register (QUADSPI_VERR) . . . . . . . . . . . . . . . . . 1474
26.5.16 QUADSPI identification register (QUADSPI_IPIDR) . . . . . . . . . . . . . 1475
26.5.17 QUADSPI size identification register (QUADSPI_SIDR) . . . . . . . . . . 1475
26.5.18 QUADSPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1476
27
Delay block (DLYB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478
27.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478
27.2
DLYB main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478
27.3
DLYB functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478
27.4
28
27.3.1
DLYB diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478
27.3.2
DLYB pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479
27.3.3
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479
27.3.4
Delay line length configuration procedure . . . . . . . . . . . . . . . . . . . . . 1480
27.3.5
Output clock phase configuration procedure . . . . . . . . . . . . . . . . . . . 1480
DLYB registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1481
27.4.1
DLYB control register (DLYB_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1481
27.4.2
DLYB configuration register (DLYB_CFGR) . . . . . . . . . . . . . . . . . . . 1482
27.4.3
DLYB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482
Analog-to-digital converters (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . 1483
28.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1483
28.2
ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1484
28.3
ADC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1485
28.4
ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1486
28.4.1
ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1486
28.4.2
ADC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1487
28.4.3
ADC clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1488
28.4.4
ADC1/2 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490
28.4.5
Slave AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492
28.4.6
ADC deep-power-down mode (DEEPPWD) and ADC voltage regulator
(ADVREGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492
28.4.7
Single-ended and differential input channels . . . . . . . . . . . . . . . . . . . 1493
28.4.8
Calibration (ADCAL, ADCALDIF, ADCALLIN, ADC_CALFACT) . . . . 1493
28.4.9
ADC on-off control (ADEN, ADDIS, ADRDY) . . . . . . . . . . . . . . . . . . . 1499
28.4.10 Constraints when writing the ADC control bits . . . . . . . . . . . . . . . . . . 1500
28.4.11 Channel selection (SQRx, JSQRx) . . . . . . . . . . . . . . . . . . . . . . . . . . 1501
28.4.12 Channel preselection register (ADC_PCSEL) . . . . . . . . . . . . . . . . . . 1501
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28.4.13 Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . 1502
28.4.14 Single conversion mode (CONT=0) . . . . . . . . . . . . . . . . . . . . . . . . . . 1503
28.4.15 Continuous conversion mode (CONT=1) . . . . . . . . . . . . . . . . . . . . . . 1503
28.4.16 Starting conversions (ADSTART, JADSTART) . . . . . . . . . . . . . . . . . . 1504
28.4.17 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505
28.4.18 Stopping an ongoing conversion (ADSTP, JADSTP) . . . . . . . . . . . . . 1505
28.4.19 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN,
JEXTSEL, JEXTEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507
28.4.20 Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1510
28.4.21 Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . . . . . . . . 1512
28.4.22 Queue of context for injected conversions . . . . . . . . . . . . . . . . . . . . . 1513
28.4.23 Programmable resolution (RES) - fast conversion mode . . . . . . . . . 1521
28.4.24 End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . 1521
28.4.25 End of conversion sequence (EOS, JEOS) . . . . . . . . . . . . . . . . . . . . 1521
28.4.26 Timing diagrams example (single/continuous modes,
hardware/software triggers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522
28.4.27 Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1523
28.4.28 Managing conversions using the DFSDM . . . . . . . . . . . . . . . . . . . . . 1531
28.4.29 Dynamic low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1531
28.4.30 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL,
AWD1CH, AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy) . 1536
28.4.31 Oversampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1539
28.4.32 Dual ADC modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1545
28.4.33 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1560
28.4.34 VBAT supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1561
28.4.35 Monitoring the internal voltage reference . . . . . . . . . . . . . . . . . . . . . 1562
28.4.36 VDDCORE supply voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . 1563
28.5
ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564
28.6
ADC registers (for each ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566
28.6.1
ADC interrupt and status register (ADC_ISR) . . . . . . . . . . . . . . . . . . 1566
28.6.2
ADC interrupt enable register (ADC_IER) . . . . . . . . . . . . . . . . . . . . . 1569
28.6.3
ADC control register (ADC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1571
28.6.4
ADC configuration register (ADC_CFGR) . . . . . . . . . . . . . . . . . . . . . 1576
28.6.5
ADC configuration register 2 (ADC_CFGR2) . . . . . . . . . . . . . . . . . . 1580
28.6.6
ADC sample time register 1 (ADC_SMPR1) . . . . . . . . . . . . . . . . . . . 1582
28.6.7
ADC sample time register 2 (ADC_SMPR2) . . . . . . . . . . . . . . . . . . . 1583
28.6.8
ADC channel preselection register (ADC_PCSEL) . . . . . . . . . . . . . . 1584
28.6.9
ADC watchdog threshold register 1 (ADC_LTR1) . . . . . . . . . . . . . . . 1584
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28.6.10 ADC watchdog threshold register 1 (ADC_HTR1) . . . . . . . . . . . . . . . 1585
28.6.11 ADC regular sequence register 1 (ADC_SQR1) . . . . . . . . . . . . . . . . 1586
28.6.12 ADC regular sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . 1587
28.6.13 ADC regular sequence register 3 (ADC_SQR3) . . . . . . . . . . . . . . . . 1588
28.6.14 ADC regular sequence register 4 (ADC_SQR4) . . . . . . . . . . . . . . . . 1589
28.6.15 ADC regular Data Register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . 1590
28.6.16 ADC injected sequence register (ADC_JSQR) . . . . . . . . . . . . . . . . . 1591
28.6.17 ADC injected channel y offset register (ADC_OFRy) . . . . . . . . . . . . 1593
28.6.18 ADC injected channel y data register (ADC_JDRy) . . . . . . . . . . . . . . 1594
28.6.19 ADC analog watchdog 2 configuration register
(ADC_AWD2CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1594
28.6.20 ADC analog watchdog 3 configuration register
(ADC_AWD3CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1595
28.6.21 ADC watchdog lower threshold register 2 (ADC_LTR2) . . . . . . . . . . 1595
28.6.22 ADC watchdog higher threshold register 2 (ADC_HTR2) . . . . . . . . . 1596
28.6.23 ADC watchdog lower threshold register 3 (ADC_LTR3) . . . . . . . . . . 1596
28.6.24 ADC watchdog higher threshold register 3 (ADC_HTR3) . . . . . . . . . 1597
28.6.25 ADC differential mode selection register (ADC_DIFSEL) . . . . . . . . . 1597
28.6.26 ADC calibration factors register (ADC_CALFACT) . . . . . . . . . . . . . . 1598
28.6.27 ADC calibration factor register 2 (ADC_CALFACT2) . . . . . . . . . . . . . 1598
28.6.28 ADC2 option register (ADC2_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1599
28.7
28.8
29
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28.7.1
ADC common status register (ADC_CSR) . . . . . . . . . . . . . . . . . . . . 1599
28.7.2
ADC common control register (ADC_CCR) . . . . . . . . . . . . . . . . . . . . 1602
28.7.3
ADC common regular data register for dual mode
(ADC_CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1605
28.7.4
ADC common regular data register for 32-bit dual mode
(ADC_CDR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1605
28.7.5
ADC hardware configuration register (ADC_HWCFGR0) . . . . . . . . . 1606
28.7.6
ADC version register (ADC_VERR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1606
28.7.7
ADC identification register (ADC_IPIDR) . . . . . . . . . . . . . . . . . . . . . . 1606
28.7.8
ADC size identification register (ADC_SIDR) . . . . . . . . . . . . . . . . . . 1607
ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607
Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612
29.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612
29.2
DTS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612
29.3
DTS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613
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29.3.1
DTS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613
29.3.2
DTS internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613
29.3.3
DTS block operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1614
29.3.4
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1614
29.3.5
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1614
29.3.6
Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1614
29.3.7
Temperature measurement principles . . . . . . . . . . . . . . . . . . . . . . . . 1615
29.3.8
Sampling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1616
29.3.9
Quick measurement mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1616
29.3.10 Trigger input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617
29.3.11 On-off control and ready flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617
29.3.12 Temperature measurement sequence . . . . . . . . . . . . . . . . . . . . . . . . 1618
29.4
DTS low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1619
29.5
DTS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1619
29.6
29.5.1
Temperature window comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . 1619
29.5.2
Synchronous interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1619
29.5.3
Asynchronous wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1619
DTS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1620
29.6.1
Temperature sensor configuration register 1 (DTS_CFGR1) . . . . . . 1620
29.6.2
Temperature sensor T0 value register 1 (DTS_T0VALR1) . . . . . . . . 1622
29.6.3
Temperature sensor ramp value register (DTS_RAMPVALR) . . . . . . 1622
29.6.4
Temperature sensor interrupt threshold register 1 (DTS_ITR1) . . . . 1623
29.6.5
Temperature sensor data register (DTS_DR) . . . . . . . . . . . . . . . . . . 1623
29.6.6
Temperature sensor status register (DTS_SR) . . . . . . . . . . . . . . . . . 1624
29.6.7
Temperature sensor interrupt enable register (DTS_ITENR) . . . . . . 1625
29.6.8
Temperature sensor clear interrupt flag register (DTS_ICIFR) . . . . . 1626
29.6.9
Temperature sensor option register (DTS_OR) . . . . . . . . . . . . . . . . . 1627
29.6.10 DTS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628
30
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1629
30.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1629
30.2
DAC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1629
30.3
DAC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1630
30.4
DAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631
30.4.1
DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631
30.4.2
DAC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632
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30.4.3
DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
30.4.4
DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
30.4.5
DAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1635
30.4.6
DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1635
30.4.7
DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1636
30.4.8
DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1636
30.4.9
Noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1637
30.4.10 Triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1638
30.4.11
DAC channel modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1639
30.4.12 DAC channel buffer calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1642
30.4.13 DAC channel conversion modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643
30.4.14 Dual DAC channel conversion modes (if dual channels are
available) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1644
30.5
DAC in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648
30.6
DAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649
30.7
DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649
30.7.1
DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649
30.7.2
DAC software trigger register (DAC_SWTRGR) . . . . . . . . . . . . . . . . 1653
30.7.3
DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1653
30.7.4
DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654
30.7.5
DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654
30.7.6
DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655
30.7.7
DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655
30.7.8
DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1656
30.7.9
Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1656
30.7.10 Dual DAC 12-bit left aligned data holding register
(DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1657
30.7.11 Dual DAC 8-bit right aligned data holding register
(DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1657
30.7.12 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . 1658
30.7.13 DAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . 1658
30.7.14 DAC status register (DAC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1658
30.7.15 DAC calibration control register (DAC_CCR) . . . . . . . . . . . . . . . . . . 1660
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30.7.16 DAC mode control register (DAC_MCR) . . . . . . . . . . . . . . . . . . . . . . 1660
30.7.17 DAC channel1 sample and hold sample time register
(DAC_SHSR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662
30.7.18 DAC channel2 sample and hold sample time register
(DAC_SHSR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662
30.7.19 DAC sample and hold time register (DAC_SHHR) . . . . . . . . . . . . . . 1662
30.7.20 DAC sample and hold refresh time register (DAC_SHRR) . . . . . . . . 1663
30.7.21 DAC hardware configuration register (DAC_HWCFGR0) . . . . . . . . . 1664
30.7.22 DAC version register (DAC_VERR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1665
30.7.23 DAC identification register (DAC_IPIDR) . . . . . . . . . . . . . . . . . . . . . . 1665
30.7.24 DAC size identification register (DAC_SIDR) . . . . . . . . . . . . . . . . . . 1665
30.7.25 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666
31
32
Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . 1669
31.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669
31.2
VREFBUF functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669
31.3
VREFBUF registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1670
31.3.1
VREFBUF control and status register (VREFBUF_CSR) . . . . . . . . . 1670
31.3.2
VREFBUF calibration control register (VREFBUF_CCR) . . . . . . . . . 1671
31.3.3
VREFBUF register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1671
Digital filter for sigma delta modulators (DFSDM) . . . . . . . . . . . . . . 1672
32.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672
32.2
DFSDM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673
32.3
DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1674
32.4
DFSDM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1675
32.4.1
DFSDM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1675
32.4.2
DFSDM pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1676
32.4.3
DFSDM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1677
32.4.4
Serial channel transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1678
32.4.5
Configuring the input serial interface . . . . . . . . . . . . . . . . . . . . . . . . . 1688
32.4.6
Parallel data inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1688
32.4.7
Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1691
32.4.8
Digital filter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1691
32.4.9
Integrator unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1692
32.4.10 Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1693
32.4.11 Short-circuit detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1695
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32.4.12 Extreme detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1696
32.4.13 Data unit block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1696
32.4.14 Signed data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697
32.4.15 Launching conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698
32.4.16 Continuous and fast continuous modes . . . . . . . . . . . . . . . . . . . . . . . 1698
32.4.17 Request precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1699
32.4.18 Power optimization in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1700
32.5
DFSDM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1700
32.6
DFSDM DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1702
32.7
DFSDM channel y registers (y=0..7) . . . . . . . . . . . . . . . . . . . . . . . . . . 1702
32.8
32.7.1
DFSDM channel y configuration register (DFSDM_CHyCFGR1) . . . 1702
32.7.2
DFSDM channel y configuration register (DFSDM_CHyCFGR2) . . . 1704
32.7.3
DFSDM channel y analog watchdog and short-circuit detector register
(DFSDM_CHyAWSCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705
32.7.4
DFSDM channel y watchdog filter data register
(DFSDM_CHyWDATR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1706
32.7.5
DFSDM channel y data input register (DFSDM_CHyDATINR) . . . . . 1706
32.7.6
DFSDM channel y delay register (DFSDM_CHyDLYR) . . . . . . . . . . . 1707
DFSDM filter x module registers (x=0..5) . . . . . . . . . . . . . . . . . . . . . . . 1708
32.8.1
DFSDM filter x control register 1 (DFSDM_FLTxCR1) . . . . . . . . . . . 1708
32.8.2
DFSDM filter x control register 2 (DFSDM_FLTxCR2) . . . . . . . . . . . 1711
32.8.3
DFSDM filter x interrupt and status register (DFSDM_FLTxISR) . . . . 1712
32.8.4
DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR) . . . . 1714
32.8.5
DFSDM filter x injected channel group selection register
(DFSDM_FLTxJCHGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1715
32.8.6
DFSDM filter x control register (DFSDM_FLTxFCR) . . . . . . . . . . . . . 1715
32.8.7
DFSDM filter x data register for injected group
(DFSDM_FLTxJDATAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1716
32.8.8
DFSDM filter x data register for the regular channel
(DFSDM_FLTxRDATAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1717
32.8.9
DFSDM filter x analog watchdog high threshold register
(DFSDM_FLTxAWHTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1718
32.8.10 DFSDM filter x analog watchdog low threshold register
(DFSDM_FLTxAWLTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1718
32.8.11 DFSDM filter x analog watchdog status register
(DFSDM_FLTxAWSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1719
32.8.12 DFSDM filter x analog watchdog clear flag register
(DFSDM_FLTxAWCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1720
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32.8.13 DFSDM filter x extremes detector maximum register
(DFSDM_FLTxEXMAX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1720
32.8.14 DFSDM filter x extremes detector minimum register
(DFSDM_FLTxEXMIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1721
32.8.15 DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR) . 1721
32.9
33
DFSDM version registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1723
32.9.1
DFSDM hardware configuration register (DFSDM_HWCFGR) . . . . . 1723
32.9.2
DFSDM version register (DFSDM_VERR) . . . . . . . . . . . . . . . . . . . . 1723
32.9.3
DFSDM identification register (DFSDM_IPIDR) . . . . . . . . . . . . . . . . 1724
32.9.4
DFSDM size identification register (DFSDM_SIDR) . . . . . . . . . . . . . 1724
32.9.5
DFSDM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1725
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1738
33.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1738
33.2
DCMI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1738
33.3
DCMI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1738
33.3.1
DCMI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1739
33.3.2
DCMI pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1739
33.3.3
DCMI clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1740
33.3.4
DCMI DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1740
33.3.5
DCMI physical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1740
33.3.6
DCMI synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1742
33.3.7
DCMI capture modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1744
33.3.8
DCMI crop feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1745
33.3.9
DCMI JPEG format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1746
33.3.10 DCMI FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1746
33.3.11 DCMI data format description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1747
33.4
DCMI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1749
33.5
DCMI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1749
33.5.1
DCMI control register (DCMI_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1749
33.5.2
DCMI status register (DCMI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1752
33.5.3
DCMI raw interrupt status register (DCMI_RIS) . . . . . . . . . . . . . . . . 1752
33.5.4
DCMI interrupt enable register (DCMI_IER) . . . . . . . . . . . . . . . . . . . 1753
33.5.5
DCMI masked interrupt status register (DCMI_MIS) . . . . . . . . . . . . . 1754
33.5.6
DCMI interrupt clear register (DCMI_ICR) . . . . . . . . . . . . . . . . . . . . . 1755
33.5.7
DCMI embedded synchronization code register (DCMI_ESCR) . . . . 1756
33.5.8
DCMI embedded synchronization unmask register (DCMI_ESUR) . 1756
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33.5.9
DCMI crop window start (DCMI_CWSTRT) . . . . . . . . . . . . . . . . . . . . 1757
33.5.10 DCMI crop window size (DCMI_CWSIZE) . . . . . . . . . . . . . . . . . . . . . 1758
33.5.11 DCMI data register (DCMI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1758
33.5.12 DCMI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1759
34
LCD-TFT display controller (LTDC) . . . . . . . . . . . . . . . . . . . . . . . . . . 1760
34.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1760
34.2
LTDC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1760
34.3
LTDC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1761
34.4
34.3.1
LTDC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1761
34.3.2
LTDC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1761
34.3.3
LTDC reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1762
LTDC programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1764
34.4.1
LTDC global configuration parameters . . . . . . . . . . . . . . . . . . . . . . . 1764
34.4.2
Layer programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 1766
34.5
LTDC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1770
34.6
LTDC programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1771
34.7
LTDC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1772
34.7.1
LTDC identification register (LTDC_IDR) . . . . . . . . . . . . . . . . . . . . . . 1772
34.7.2
LTDC layer count register (LTDC_LCR) . . . . . . . . . . . . . . . . . . . . . . 1772
34.7.3
LTDC synchronization size configuration register (LTDC_SSCR) . . . 1773
34.7.4
LTDC back porch configuration register (LTDC_BPCR) . . . . . . . . . . 1773
34.7.5
LTDC active width configuration register (LTDC_AWCR) . . . . . . . . . 1774
34.7.6
LTDC total width configuration register (LTDC_TWCR) . . . . . . . . . . . 1775
34.7.7
LTDC global control register (LTDC_GCR) . . . . . . . . . . . . . . . . . . . . 1775
34.7.8
LTDC global configuration 1 register (LTDC_GC1R) . . . . . . . . . . . . . 1776
34.7.9
LTDC global configuration 2 register (LTDC_GC2R) . . . . . . . . . . . . . 1777
34.7.10 LTDC shadow reload configuration register (LTDC_SRCR) . . . . . . . 1778
34.7.11 LTDC background color configuration register (LTDC_BCCR) . . . . . 1778
34.7.12 LTDC interrupt enable register (LTDC_IER) . . . . . . . . . . . . . . . . . . . 1779
34.7.13 LTDC interrupt status register (LTDC_ISR) . . . . . . . . . . . . . . . . . . . . 1780
34.7.14 LTDC interrupt clear register (LTDC_ICR) . . . . . . . . . . . . . . . . . . . . . 1780
34.7.15 LTDC line interrupt position configuration register (LTDC_LIPCR) . . 1781
34.7.16 LTDC current position status register (LTDC_CPSR) . . . . . . . . . . . . 1781
34.7.17 LTDC current display status register (LTDC_CDSR) . . . . . . . . . . . . . 1782
34.7.18 LTDC layer x control register (LTDC_LxCR) . . . . . . . . . . . . . . . . . . . 1782
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34.7.19 LTDC layer x window horizontal position configuration register
(LTDC_LxWHPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1783
34.7.20 LTDC layer x window vertical position configuration register
(LTDC_LxWVPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1784
34.7.21 LTDC layer x color keying configuration register
(LTDC_LxCKCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1785
34.7.22 LTDC layer x pixel format configuration register
(LTDC_LxPFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1785
34.7.23 LTDC layer x constant alpha configuration register
(LTDC_LxCACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1786
34.7.24 LTDC layer x default color configuration register
(LTDC_LxDCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1786
34.7.25 LTDC layer x blending factors configuration register
(LTDC_LxBFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1787
34.7.26 LTDC layer x color frame buffer address register
(LTDC_LxCFBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1788
34.7.27 LTDC layer x color frame buffer length register
(LTDC_LxCFBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1788
34.7.28 LTDC layer x color frame buffer line number register
(LTDC_LxCFBLNR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1789
34.7.29 LTDC layer x CLUT write register (LTDC_LxCLUTWR) . . . . . . . . . . 1789
34.7.30 LTDC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1790
35
True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . 1794
35.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1794
35.2
RNG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1794
35.3
RNG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1795
35.3.1
RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1795
35.3.2
RNG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1795
35.3.3
Random number generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1796
35.3.4
RNG initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1798
35.3.5
RNG operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1799
35.3.6
RNG clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1800
35.3.7
Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1800
35.3.8
RNG low-power use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1801
35.4
RNG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1801
35.5
RNG processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1801
35.6
RNG entropy source validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1802
35.6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1802
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35.7
36
35.6.2
Validation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1802
35.6.3
Data collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1802
RNG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1803
35.7.1
RNG control register (RNG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1803
35.7.2
RNG status register (RNG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1803
35.7.3
RNG data register (RNG_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1804
35.7.4
RNG hardware configuration register (RNG_HWCFGR) . . . . . . . . . . 1805
35.7.5
RNG version register (RNG_VERR) . . . . . . . . . . . . . . . . . . . . . . . . . 1805
35.7.6
RNG identification register (RNG_IPIDR) . . . . . . . . . . . . . . . . . . . . . 1806
35.7.7
RNG size identification register (RNG_SIDR) . . . . . . . . . . . . . . . . . . 1806
35.7.8
RNG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1806
Cryptographic processor (CRYP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1808
36.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1808
36.2
CRYP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1808
36.3
CRYP implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1809
36.4
CRYP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1810
36.4.1
CRYP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1810
36.4.2
CRYP internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1811
36.4.3
CRYP DES/TDES cryptographic core . . . . . . . . . . . . . . . . . . . . . . . . 1811
36.4.4
CRYP AES cryptographic core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1812
36.4.5
CRYP procedure to perform a cipher operation . . . . . . . . . . . . . . . . . 1818
36.4.6
CRYP busy state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1820
36.4.7
Preparing the CRYP AES key for decryption . . . . . . . . . . . . . . . . . . . 1821
36.4.8
CRYP stealing and data padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1821
36.4.9
CRYP suspend/resume operations . . . . . . . . . . . . . . . . . . . . . . . . . . 1822
36.4.10 CRYP DES/TDES basic chaining modes (ECB, CBC) . . . . . . . . . . . 1823
36.4.11 CRYP AES basic chaining modes (ECB, CBC) . . . . . . . . . . . . . . . . . 1828
36.4.12 CRYP AES counter mode (AES-CTR) . . . . . . . . . . . . . . . . . . . . . . . . 1833
36.4.13 CRYP AES Galois/counter mode (GCM) . . . . . . . . . . . . . . . . . . . . . . 1837
36.4.14 CRYP AES Galois message authentication code (GMAC) . . . . . . . . 1842
36.4.15 CRYP AES Counter with CBC-MAC (CCM) . . . . . . . . . . . . . . . . . . . 1843
36.4.16 CRYP data registers and data swapping . . . . . . . . . . . . . . . . . . . . . . 1848
36.4.17 CRYP key registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1852
36.4.18 CRYP initialization vector registers . . . . . . . . . . . . . . . . . . . . . . . . . . 1853
36.4.19 CRYP DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1854
36.4.20 CRYP error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1856
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36.5
CRYP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1857
36.6
CRYP processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1858
36.7
CRYP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1859
36.7.1
CRYP control register (CRYP_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1859
36.7.2
CRYP status register (CRYP_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1861
36.7.3
CRYP data input register (CRYP_DIN) . . . . . . . . . . . . . . . . . . . . . . . 1862
36.7.4
CRYP data output register (CRYP_DOUT) . . . . . . . . . . . . . . . . . . . . 1862
36.7.5
CRYP DMA control register (CRYP_DMACR) . . . . . . . . . . . . . . . . . . 1863
36.7.6
CRYP interrupt mask set/clear register (CRYP_IMSCR) . . . . . . . . . . 1864
36.7.7
CRYP raw interrupt status register (CRYP_RISR) . . . . . . . . . . . . . . 1864
36.7.8
CRYP masked interrupt status register (CRYP_MISR) . . . . . . . . . . . 1865
36.7.9
CRYP key register 0L (CRYP_K0LR) . . . . . . . . . . . . . . . . . . . . . . . . 1866
36.7.10 CRYP key register 0R (CRYP_K0RR) . . . . . . . . . . . . . . . . . . . . . . . . 1866
36.7.11 CRYP key register 1L (CRYP_K1LR) . . . . . . . . . . . . . . . . . . . . . . . . 1867
36.7.12 CRYP key register 1R (CRYP_K1RR) . . . . . . . . . . . . . . . . . . . . . . . . 1867
36.7.13 CRYP key register 2L (CRYP_K2LR) . . . . . . . . . . . . . . . . . . . . . . . . 1868
36.7.14 CRYP key register 2R (CRYP_K2RR) . . . . . . . . . . . . . . . . . . . . . . . . 1868
36.7.15 CRYP key register 3L (CRYP_K3LR) . . . . . . . . . . . . . . . . . . . . . . . . 1869
36.7.16 CRYP key register 3R (CRYP_K3RR) . . . . . . . . . . . . . . . . . . . . . . . . 1869
36.7.17 CRYP initialization vector register 0L (CRYP_IV0LR) . . . . . . . . . . . . 1870
36.7.18 CRYP initialization vector register 0R (CRYP_IV0RR) . . . . . . . . . . . 1870
36.7.19 CRYP initialization vector register 1L (CRYP_IV1LR) . . . . . . . . . . . . 1871
36.7.20 CRYP initialization vector register 1R (CRYP_IV1RR) . . . . . . . . . . . 1871
36.7.21 CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) 1871
36.7.22 CRYP context swap GCM registers (CRYP_CSGCMxR) . . . . . . . . . 1872
36.7.23 CRYP hardware configuration register (CRYP_HWCFGR) . . . . . . . . 1872
36.7.24 CRYP version register (CRYP_VERR) . . . . . . . . . . . . . . . . . . . . . . . 1873
36.7.25 CRYP identification (CRYP_IPIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1873
36.7.26 CRYP size identification register (CRYP_SIDR) . . . . . . . . . . . . . . . . 1874
36.7.27 CRYP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1874
37
Hash processor (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1877
37.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1877
37.2
HASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1877
37.3
HASH implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1878
37.4
HASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1878
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37.4.1
HASH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1878
37.4.2
HASH internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1879
37.4.3
About secure hash algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1879
37.4.4
Message data feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1879
37.4.5
Message digest computing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1881
37.4.6
Message padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1882
37.4.7
HMAC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1884
37.4.8
HASH suspend/resume operations . . . . . . . . . . . . . . . . . . . . . . . . . . 1886
37.4.9
HASH DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1888
37.4.10 HASH error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1888
37.4.11 HASH processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1889
37.5
HASH interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1889
37.6
HASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1890
37.6.1
HASH control register (HASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1890
37.6.2
HASH data input register (HASH_DIN) . . . . . . . . . . . . . . . . . . . . . . . 1892
37.6.3
HASH start register (HASH_STR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1893
37.6.4
HASH digest registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1894
37.6.5
HASH interrupt enable register (HASH_IMR) . . . . . . . . . . . . . . . . . . 1895
37.6.6
HASH status register (HASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1896
37.6.7
HASH context swap registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1896
37.6.8
HASH hardware configuration register (HASH_HWCFGR) . . . . . . . . 1897
37.6.9
HASH version register (HASH_VERR) . . . . . . . . . . . . . . . . . . . . . . . 1897
37.6.10 HASH identification register (HASH_IPIDR) . . . . . . . . . . . . . . . . . . . 1898
37.6.11 HASH size identification register (HASH_SIDR) . . . . . . . . . . . . . . . . 1898
37.6.12 HASH register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1898
38
50/3930
Advanced-control timers (TIM1/TIM8) . . . . . . . . . . . . . . . . . . . . . . . . 1901
38.1
TIM1/TIM8 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1901
38.2
TIM1/TIM8 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1901
38.3
TIM1/TIM8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1903
38.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1903
38.3.2
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1905
38.3.3
Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1916
38.3.4
External trigger input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1918
38.3.5
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1919
38.3.6
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1923
38.3.7
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1925
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38.3.8
PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1926
38.3.9
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1927
38.3.10 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1928
38.3.11 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1929
38.3.12 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1932
38.3.13 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1933
38.3.14 Combined 3-phase PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1934
38.3.15 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . 1935
38.3.16 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1937
38.3.17 Bidirectional break inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1943
38.3.18 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . 1944
38.3.19 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1946
38.3.20 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1947
38.3.21 Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1948
38.3.22 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1949
38.3.23 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1951
38.3.24 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1952
38.3.25 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1952
38.3.26 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1955
38.3.27 ADC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1959
38.3.28 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1959
38.3.29 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1960
38.4
TIM1/TIM8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1961
38.4.1
TIMx control register 1 (TIMx_CR1)(x = 1, 8) . . . . . . . . . . . . . . . . . . 1961
38.4.2
TIMx control register 2 (TIMx_CR2)(x = 1, 8) . . . . . . . . . . . . . . . . . . 1962
38.4.3
TIMx slave mode control register
(TIMx_SMCR)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1965
38.4.4
TIMx DMA/interrupt enable register
(TIMx_DIER)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1967
38.4.5
TIMx status register (TIMx_SR)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . 1969
38.4.6
TIMx event generation register (TIMx_EGR)(x = 1, 8) . . . . . . . . . . . . 1971
38.4.7
TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 1, 8) . . 1972
38.4.8
TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1973
38.4.9
TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 1, 8) . . 1976
38.4.10 TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1977
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38.4.11 TIMx capture/compare enable register
(TIMx_CCER)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1978
38.4.12 TIMx counter (TIMx_CNT)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . 1982
38.4.13 TIMx prescaler (TIMx_PSC)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . 1982
38.4.14 TIMx auto-reload register (TIMx_ARR)(x = 1, 8) . . . . . . . . . . . . . . . . 1982
38.4.15 TIMx repetition counter register (TIMx_RCR)(x = 1, 8) . . . . . . . . . . . 1983
38.4.16 TIMx capture/compare register 1
(TIMx_CCR1)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1983
38.4.17 TIMx capture/compare register 2
(TIMx_CCR2)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1984
38.4.18 TIMx capture/compare register 3
(TIMx_CCR3)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1984
38.4.19 TIMx capture/compare register 4
(TIMx_CCR4)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1985
38.4.20 TIMx break and dead-time register
(TIMx_BDTR)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1985
38.4.21 TIMx DMA control register
(TIMx_DCR)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1989
38.4.22 TIMx DMA address for full transfer
(TIMx_DMAR)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1990
38.4.23 TIMx capture/compare mode register 3
(TIMx_CCMR3)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1991
38.4.24 TIMx capture/compare register 5
(TIMx_CCR5)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1992
38.4.25 TIMx capture/compare register 6
(TIMx_CCR6)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1993
38.4.26 TIM1 alternate function option register 1 (TIM1_AF1) . . . . . . . . . . . . 1993
38.4.27 TIM1 Alternate function register 2 (TIM1_AF2) . . . . . . . . . . . . . . . . . 1994
38.4.28 TIM8 Alternate function option register 1 (TIM8_AF1) . . . . . . . . . . . . 1995
38.4.29 TIM8 Alternate function option register 2 (TIM8_AF2) . . . . . . . . . . . . 1996
38.4.30 TIM1 timer input selection register (TIM1_TISEL) . . . . . . . . . . . . . . . 1997
38.4.31 TIM8 timer input selection register (TIM8_TISEL) . . . . . . . . . . . . . . . 1998
38.4.32 TIM1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1999
38.4.33 TIM8 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2001
39
General-purpose timers (TIM2/TIM3/TIM4/TIM5) . . . . . . . . . . . . . . . . 2004
39.1
TIM2/TIM3/TIM4/TIM5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 2004
39.2
TIM2/TIM3/TIM4/TIM5 main features . . . . . . . . . . . . . . . . . . . . . . . . . . 2004
39.3
TIM2/TIM3/TIM4/TIM5 functional description . . . . . . . . . . . . . . . . . . . . 2006
39.3.1
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Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2006
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39.3.2
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2008
39.3.3
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2018
39.3.4
Capture/Compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2022
39.3.5
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2023
39.3.6
PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2024
39.3.7
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2025
39.3.8
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2026
39.3.9
PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2027
39.3.10 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2030
39.3.11 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2031
39.3.12 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . 2032
39.3.13 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2034
39.3.14 Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2035
39.3.15 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2036
39.3.16 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2038
39.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2038
39.3.18 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . 2039
39.3.19 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2042
39.3.20 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2047
39.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2048
39.4
TIM2/TIM3/TIM4/TIM5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2049
39.4.1
TIMx control register 1 (TIMx_CR1)(x = 2 to 5) . . . . . . . . . . . . . . . . . 2049
39.4.2
TIMx control register 2 (TIMx_CR2)(x = 2 to 5) . . . . . . . . . . . . . . . . . 2050
39.4.3
TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5) . . . . . . . 2052
39.4.4
TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5) . . . . . . 2055
39.4.5
TIMx status register (TIMx_SR)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . 2056
39.4.6
TIMx event generation register (TIMx_EGR)(x = 2 to 5) . . . . . . . . . . 2057
39.4.7
TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 5) . 2058
39.4.8
TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2060
39.4.9
TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 5) . 2062
39.4.10 TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2063
39.4.11 TIMx capture/compare enable register
(TIMx_CCER)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2064
39.4.12 TIMx counter (TIMx_CNT)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . 2065
39.4.13 TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5) . . . . . . . . . . . . . . . . 2066
39.4.14 TIMx prescaler (TIMx_PSC)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . 2066
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39.4.15 TIMx auto-reload register (TIMx_ARR)(x = 2 to 5) . . . . . . . . . . . . . . 2067
39.4.16 TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 5) . . . . . . . 2067
39.4.17 TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 5) . . . . . . . 2067
39.4.18 TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 5) . . . . . . . 2068
39.4.19 TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 5) . . . . . . . 2068
39.4.20 TIMx DMA control register (TIMx_DCR)(x = 2 to 5) . . . . . . . . . . . . . . 2069
39.4.21 TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5) . . . . . . 2070
39.4.22 TIM2 alternate function option register 1 (TIM2_AF1) . . . . . . . . . . . . 2070
39.4.23 TIM3 alternate function option register 1 (TIM3_AF1) . . . . . . . . . . . . 2070
39.4.24 TIM4 alternate function option register 1 (TIM4_AF1) . . . . . . . . . . . . 2071
39.4.25 TIM5 alternate function option register 1 (TIM5_AF1) . . . . . . . . . . . . 2071
39.4.26 TIM2 timer input selection register (TIM2_TISEL) . . . . . . . . . . . . . . . 2072
39.4.27 TIM3 timer input selection register (TIM3_TISEL) . . . . . . . . . . . . . . . 2073
39.4.28 TIM4 timer input selection register (TIM4_TISEL) . . . . . . . . . . . . . . . 2073
39.4.29 TIM5 timer input selection register (TIM5_TISEL) . . . . . . . . . . . . . . . 2074
39.4.30 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2076
40
General-purpose timers (TIM12/TIM13/TIM14) . . . . . . . . . . . . . . . . . 2079
40.1
TIM12/TIM13/TIM14 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2079
40.2
TIM12/TIM13/TIM14 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2079
40.3
40.2.1
TIM12 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2079
40.2.2
TIM13/TIM14 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2080
TIM12/TIM13/TIM14 functional description . . . . . . . . . . . . . . . . . . . . . 2082
40.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2082
40.3.2
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2084
40.3.3
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2087
40.3.4
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2089
40.3.5
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2091
40.3.6
PWM input mode (only for TIM12) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2092
40.3.7
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2093
40.3.8
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2094
40.3.9
PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2095
40.3.10 Combined PWM mode (TIM12 only) . . . . . . . . . . . . . . . . . . . . . . . . . 2096
40.3.11 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2097
40.3.12 Retriggerable one pulse mode (TIM12 only) . . . . . . . . . . . . . . . . . . . 2099
40.3.13 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2099
40.3.14 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2100
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40.3.15 TIM12 external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . . 2100
40.3.16 Slave mode – combined reset + trigger mode . . . . . . . . . . . . . . . . . . 2103
40.3.17 Timer synchronization (TIM12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2104
40.3.18 Using timer output as trigger for other timers (TIM13/TIM14) . . . . . . 2104
40.3.19 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2104
40.4
TIM12 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2104
40.4.1
TIM12 control register 1 (TIM12_CR1) . . . . . . . . . . . . . . . . . . . . . . . 2104
40.4.2
TIM12 control register 2 (TIM12_CR2) . . . . . . . . . . . . . . . . . . . . . . . 2105
40.4.3
TIM12 slave mode control register (TIM12_SMCR) . . . . . . . . . . . . . 2106
40.4.4
TIM12 Interrupt enable register (TIM12_DIER) . . . . . . . . . . . . . . . . . 2108
40.4.5
TIM12 status register (TIM12_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . 2108
40.4.6
TIM12 event generation register (TIM12_EGR) . . . . . . . . . . . . . . . . 2109
40.4.7
TIM12 capture/compare mode register 1 (TIM12_CCMR1) . . . . . . . 2110
40.4.8
TIM12 capture/compare mode register 1 [alternate]
(TIM12_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2111
40.4.9
TIM12 capture/compare enable register (TIM12_CCER) . . . . . . . . . 2114
40.4.10 TIM12 counter (TIM12_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2115
40.4.11 TIM12 prescaler (TIM12_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2116
40.4.12 TIM12 auto-reload register (TIM12_ARR) . . . . . . . . . . . . . . . . . . . . . 2116
40.4.13 TIM12 capture/compare register 1 (TIM12_CCR1) . . . . . . . . . . . . . . 2116
40.4.14 TIM12 capture/compare register 2 (TIM12_CCR2) . . . . . . . . . . . . . . 2117
40.4.15 TIM12 timer input selection register (TIM12_TISEL) . . . . . . . . . . . . . 2117
40.4.16 TIM12 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2118
40.5
TIM13/TIM14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2120
40.5.1
TIMx control register 1 (TIMx_CR1)(x = 13 to 14) . . . . . . . . . . . . . . . 2120
40.5.2
TIMx Interrupt enable register (TIMx_DIER)(x = 13 to 14) . . . . . . . . 2121
40.5.3
TIMx status register (TIMx_SR)(x = 13 to 14) . . . . . . . . . . . . . . . . . . 2121
40.5.4
TIMx event generation register (TIMx_EGR)(x = 13 to 14) . . . . . . . . 2122
40.5.5
TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 13 to 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2123
40.5.6
TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 13 to 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2124
40.5.7
TIMx capture/compare enable register
(TIMx_CCER)(x = 13 to 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2126
40.5.8
TIMx counter (TIMx_CNT)(x = 13 to 14) . . . . . . . . . . . . . . . . . . . . . . 2127
40.5.9
TIMx prescaler (TIMx_PSC)(x = 13 to 14) . . . . . . . . . . . . . . . . . . . . . 2128
40.5.10 TIMx auto-reload register (TIMx_ARR)(x = 13 to 14) . . . . . . . . . . . . 2128
40.5.11 TIMx capture/compare register 1 (TIMx_CCR1)(x = 13 to 14) . . . . . 2128
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40.5.12 TIM13 timer input selection register (TIM13_TISEL) . . . . . . . . . . . . . 2129
40.5.13 TIM14 timer input selection register (TIM14_TISEL) . . . . . . . . . . . . . 2129
40.5.14 TIM13/TIM14 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2130
41
General-purpose timers (TIM15/TIM16/TIM17) . . . . . . . . . . . . . . . . . 2132
41.1
TIM15/TIM16/TIM17 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2132
41.2
TIM15 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2132
41.3
TIM16/TIM17 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2133
41.4
TIM15/TIM16/TIM17 functional description . . . . . . . . . . . . . . . . . . . . . 2136
41.4.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2136
41.4.2
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2138
41.4.3
Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2142
41.4.4
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2143
41.4.5
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2145
41.4.6
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2147
41.4.7
PWM input mode (only for TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2148
41.4.8
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2149
41.4.9
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2150
41.4.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2151
41.4.11 Combined PWM mode (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . . . 2152
41.4.12 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . 2153
41.4.13 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2155
41.4.14 Bidirectional break inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2160
41.4.15 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2161
41.4.16 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2163
41.4.17 Retriggerable one pulse mode (TIM15 only) . . . . . . . . . . . . . . . . . . . 2164
41.4.18 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2165
41.4.19 Timer input XOR function (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . 2166
41.4.20 External trigger synchronization (TIM15 only) . . . . . . . . . . . . . . . . . . 2167
41.4.21 Slave mode – combined reset + trigger mode . . . . . . . . . . . . . . . . . . 2169
41.4.22 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2169
41.4.23 Timer synchronization (TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2171
41.4.24 Using timer output as trigger for other timers (TIM16/TIM17) . . . . . . 2171
41.4.25 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2171
41.5
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41.5.1
TIM15 control register 1 (TIM15_CR1) . . . . . . . . . . . . . . . . . . . . . . . 2172
41.5.2
TIM15 control register 2 (TIM15_CR2) . . . . . . . . . . . . . . . . . . . . . . . 2173
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41.5.3
TIM15 slave mode control register (TIM15_SMCR) . . . . . . . . . . . . . 2175
41.5.4
TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . . . . . . . . . 2176
41.5.5
TIM15 status register (TIM15_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . 2177
41.5.6
TIM15 event generation register (TIM15_EGR) . . . . . . . . . . . . . . . . 2179
41.5.7
TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . . . . 2180
41.5.8
TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2181
41.5.9
TIM15 capture/compare enable register (TIM15_CCER) . . . . . . . . . 2184
41.5.10 TIM15 counter (TIM15_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2187
41.5.11 TIM15 prescaler (TIM15_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2187
41.5.12 TIM15 auto-reload register (TIM15_ARR) . . . . . . . . . . . . . . . . . . . . . 2187
41.5.13 TIM15 repetition counter register (TIM15_RCR) . . . . . . . . . . . . . . . . 2188
41.5.14 TIM15 capture/compare register 1 (TIM15_CCR1) . . . . . . . . . . . . . . 2188
41.5.15 TIM15 capture/compare register 2 (TIM15_CCR2) . . . . . . . . . . . . . . 2189
41.5.16 TIM15 break and dead-time register (TIM15_BDTR) . . . . . . . . . . . . 2189
41.5.17 TIM15 DMA control register (TIM15_DCR) . . . . . . . . . . . . . . . . . . . . 2192
41.5.18 TIM15 DMA address for full transfer (TIM15_DMAR) . . . . . . . . . . . . 2192
41.5.19 TIM15 alternate register 1 (TIM15_AF1) . . . . . . . . . . . . . . . . . . . . . . 2193
41.5.20 TIM15 input selection register (TIM15_TISEL) . . . . . . . . . . . . . . . . . 2194
41.5.21 TIM15 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2194
41.6
TIM16/TIM17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2197
41.6.1
TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . . . . . . . . . . . . 2197
41.6.2
TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . . . . . . . . . . . . 2198
41.6.3
TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . 2199
41.6.4
TIMx status register (TIMx_SR)(x = 16 to 17) . . . . . . . . . . . . . . . . . . 2200
41.6.5
TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . . . . . 2201
41.6.6
TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2202
41.6.7
TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2203
41.6.8
TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . 2205
41.6.9
TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . 2207
41.6.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . 2208
41.6.11 TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . . . . . . . . . 2208
41.6.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . . . . . 2209
41.6.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . . 2209
41.6.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . 2210
41.6.15 TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . . . . . . . . . 2213
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41.6.16 TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . 2213
41.6.17 TIM16 alternate function register 1 (TIM16_AF1) . . . . . . . . . . . . . . . 2214
41.6.18 TIM16 input selection register (TIM16_TISEL) . . . . . . . . . . . . . . . . . 2214
41.6.19 TIM17 alternate function register 1 (TIM17_AF1) . . . . . . . . . . . . . . . 2215
41.6.20 TIM17 input selection register (TIM17_TISEL) . . . . . . . . . . . . . . . . . 2216
41.6.21 TIM16/TIM17 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2217
42
Basic timers (TIM6/TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2219
42.1
TIM6/TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2219
42.2
TIM6/TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2219
42.3
TIM6/TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2220
42.4
43
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42.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2220
42.3.2
Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2222
42.3.3
UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2225
42.3.4
Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2225
42.3.5
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2226
TIM6/TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2226
42.4.1
TIMx control register 1 (TIMx_CR1)(x = 6 to 7) . . . . . . . . . . . . . . . . . 2226
42.4.2
TIMx control register 2 (TIMx_CR2)(x = 6 to 7) . . . . . . . . . . . . . . . . . 2228
42.4.3
TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) . . . . . . 2228
42.4.4
TIMx status register (TIMx_SR)(x = 6 to 7) . . . . . . . . . . . . . . . . . . . . 2229
42.4.5
TIMx event generation register (TIMx_EGR)(x = 6 to 7) . . . . . . . . . . 2229
42.4.6
TIMx counter (TIMx_CNT)(x = 6 to 7) . . . . . . . . . . . . . . . . . . . . . . . . 2229
42.4.7
TIMx prescaler (TIMx_PSC)(x = 6 to 7) . . . . . . . . . . . . . . . . . . . . . . . 2230
42.4.8
TIMx auto-reload register (TIMx_ARR)(x = 6 to 7) . . . . . . . . . . . . . . 2230
42.4.9
TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2231
Low-power timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2232
43.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2232
43.2
LPTIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2232
43.3
LPTIM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2233
43.4
LPTIM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2233
43.4.1
LPTIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2233
43.4.2
LPTIM pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2235
43.4.3
LPTIM input and trigger mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 2235
43.4.4
LPTIM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2238
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43.4.5
Glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2238
43.4.6
Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2239
43.4.7
Trigger multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2240
43.4.8
Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2240
43.4.9
Timeout function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2242
43.4.10 Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2242
43.4.11 Register update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2243
43.4.12 Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2244
43.4.13 Timer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2244
43.4.14 Timer counter reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2245
43.4.15 Encoder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2245
43.4.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2247
43.5
LPTIM low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2247
43.6
LPTIM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2248
43.7
LPTIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2248
43.7.1
LPTIM interrupt and status register (LPTIM_ISR) . . . . . . . . . . . . . . . 2249
43.7.2
LPTIM interrupt clear register (LPTIM_ICR) . . . . . . . . . . . . . . . . . . . 2250
43.7.3
LPTIM interrupt enable register (LPTIM_IER) . . . . . . . . . . . . . . . . . . 2250
43.7.4
LPTIM configuration register (LPTIM_CFGR) . . . . . . . . . . . . . . . . . . 2251
43.7.5
LPTIM control register (LPTIM_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 2254
43.7.6
LPTIM compare register (LPTIM_CMP) . . . . . . . . . . . . . . . . . . . . . . 2256
43.7.7
LPTIM autoreload register (LPTIM_ARR) . . . . . . . . . . . . . . . . . . . . . 2256
43.7.8
LPTIM counter register (LPTIM_CNT) . . . . . . . . . . . . . . . . . . . . . . . . 2257
43.7.9
LPTIM configuration register 2 (LPTIM_CFGR2) . . . . . . . . . . . . . . . 2257
43.7.10 LPTIM x peripheral hardware configuration register
(LPTIMx_HWCFGR)(x = 1 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2258
43.7.11 LPTIM peripheral version identification register (LPTIM_VERR) . . . . 2259
43.7.12 LPTIM peripheral type identification register (LPTIM_PIDR) . . . . . . . 2259
43.7.13 LPTIM registers map size identification register (LPTIM_SIDR) . . . . 2259
43.7.14 LPTIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2261
44
System timer generator (STGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2263
44.1
STGEN introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2263
44.2
STGEN main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2263
44.3
STGEN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2263
44.3.1
44.4
STGEN block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2264
STGEN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2265
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44.4.1
STGENC control register (STGENC_CNTCR) . . . . . . . . . . . . . . . . . 2265
44.4.2
STGENC status register (STGENC_CNTSR) . . . . . . . . . . . . . . . . . . 2265
44.4.3
STGENC value lower register (STGENC_CNTCVL) . . . . . . . . . . . . . 2266
44.4.4
STGENC value upper register (STGENC_CNTCVU) . . . . . . . . . . . . 2266
44.4.5
STGENC base frequency register (STGENC_CNTFID0) . . . . . . . . . 2267
44.4.6
STGENC peripheral ID4 register (STGENC_PIDR4) . . . . . . . . . . . . 2267
44.4.7
STGENC peripheral ID5 register (STGENC_PIDR5) . . . . . . . . . . . . 2268
44.4.8
STGENC peripheral ID6 register (STGENC_PIDR6) . . . . . . . . . . . . 2268
44.4.9
STGENC peripheral ID7 register (STGENC_PIDR7) . . . . . . . . . . . . 2268
44.4.10 STGENC peripheral ID0 register (STGENC_PIDR0) . . . . . . . . . . . . 2269
44.4.11 STGENC peripheral ID1 register (STGENC_PIDR1) . . . . . . . . . . . . 2269
44.4.12 STGENC peripheral ID2 register (STGENC_PIDR2) . . . . . . . . . . . . 2269
44.4.13 STGENC peripheral ID3 register (STGENC_PIDR3) . . . . . . . . . . . . 2270
44.4.14 STGENC component ID0 register (STGENC_CIDR0) . . . . . . . . . . . 2270
44.4.15 STGENC component ID1 register (STGENC_CIDR1) . . . . . . . . . . . 2271
44.4.16 STGENC component ID2 register (STGENC_CIDR2) . . . . . . . . . . . 2271
44.4.17 STGENC component ID3 register (STGENC_CIDR3) . . . . . . . . . . . 2272
44.4.18 STGENR value lower register (STGENR_CNTCVL) . . . . . . . . . . . . . 2272
44.4.19 STGENR value upper register (STGENR_CNTCVU) . . . . . . . . . . . . 2272
44.4.20 STGENR peripheral ID4 register (STGENR_PIDR4) . . . . . . . . . . . . 2273
44.4.21 STGENR peripheral ID5 register (STGENR_PIDR5) . . . . . . . . . . . . 2273
44.4.22 STGENR peripheral ID6 register (STGENR_PIDR6) . . . . . . . . . . . . 2273
44.4.23 STGENR peripheral ID7 register (STGENR_PIDR7) . . . . . . . . . . . . 2274
44.4.24 STGENR peripheral ID0 register (STGENR_PIDR0) . . . . . . . . . . . . 2274
44.4.25 STGENR peripheral ID1 register (STGENR_PIDR1) . . . . . . . . . . . . 2274
44.4.26 STGENR peripheral ID2 register (STGENR_PIDR2) . . . . . . . . . . . . 2275
44.4.27 STGENR peripheral ID3 register (STGENR_PIDR3) . . . . . . . . . . . . 2275
44.4.28 STGENR component ID0 register (STGENR_CIDR0) . . . . . . . . . . . 2276
44.4.29 STGENR component ID1 register (STGENR_CIDR1) . . . . . . . . . . . 2276
44.4.30 STGENR component ID2 register (STGENR_CIDR2) . . . . . . . . . . . 2276
44.4.31 STGENR component ID3 register (STGENR_CIDR3) . . . . . . . . . . . 2277
44.4.32 STGEN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2277
45
60/3930
Watchdogs overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2280
45.1
Watchdog main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2280
45.2
Watchdog brief functional description . . . . . . . . . . . . . . . . . . . . . . . . . 2280
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Contents
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2282
46.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2282
46.2
IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2282
46.3
IWDG implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2282
46.4
IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2283
46.4.1
IWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2283
46.4.2
IWDG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2284
46.4.3
Software and hardware watchdog modes . . . . . . . . . . . . . . . . . . . . . 2284
46.4.4
Window option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2285
46.4.5
Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2288
46.4.6
Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2288
46.5
IWDG low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2288
46.6
IWDG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2289
46.7
IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2290
46.7.1
IWDG key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2290
46.7.2
IWDG prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . 2291
46.7.3
IWDG reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . 2292
46.7.4
IWDG status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2292
46.7.5
IWDG window register (IWDG_WINR) . . . . . . . . . . . . . . . . . . . . . . . 2293
46.7.6
IWDG early wake-up interrupt register (IWDG_EWCR) . . . . . . . . . . 2294
46.7.7
IWDG hardware configuration register (IWDG_HWCFGR) . . . . . . . . 2294
46.7.8
IWDG version register (IWDG_VERR) . . . . . . . . . . . . . . . . . . . . . . . 2295
46.7.9
IWDG identification register (IWDG_IDR) . . . . . . . . . . . . . . . . . . . . . 2296
46.7.10 IWDG size identification register (IWDG_SIDR) . . . . . . . . . . . . . . . . 2296
46.7.11 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2297
47
System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . 2298
47.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2298
47.2
WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2298
47.3
WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2298
47.3.1
WWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2299
47.3.2
WWDG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2299
47.3.3
Enabling the watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2299
47.3.4
Controlling the down-counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2299
47.3.5
How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . 2300
47.3.6
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2301
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48
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47.4
WWDG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2301
47.5
WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2301
47.5.1
WWDG control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . 2302
47.5.2
WWDG configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . 2302
47.5.3
WWDG status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . 2303
47.5.4
WWDG hardware configuration register (WWDG_HWCFGR) . . . . . 2303
47.5.5
WWDG version register (WWDG_VERR) . . . . . . . . . . . . . . . . . . . . . 2304
47.5.6
WWDG identification register (WWDG_IPIDR) . . . . . . . . . . . . . . . . . 2304
47.5.7
WWDG size identification register (WWDG_SIDR) . . . . . . . . . . . . . . 2304
47.5.8
WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2305
Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2306
48.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2306
48.2
RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2306
48.3
RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2308
48.3.1
RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2308
48.3.2
RTC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2310
48.3.3
GPIOs controlled by the RTC and TAMP . . . . . . . . . . . . . . . . . . . . . . 2311
48.3.4
RTC secure protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2315
48.3.5
Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2316
48.3.6
Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2317
48.3.7
Programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2317
48.3.8
Periodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2318
48.3.9
RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 2319
48.3.10 Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2320
48.3.11 Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2321
48.3.12 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2322
48.3.13 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2322
48.3.14 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2323
48.3.15 Timestamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2325
48.3.16 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2326
48.3.17 Tamper and alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2326
48.4
RTC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2327
48.5
RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2327
48.6
RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2328
48.6.1
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RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2329
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Contents
48.6.2
RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2330
48.6.3
RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . 2331
48.6.4
RTC initialization control and status register (RTC_ICSR) . . . . . . . . 2331
48.6.5
RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . 2333
48.6.6
RTC wakeup timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . 2334
48.6.7
RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2334
48.6.8
RTC secure mode control register (RTC_SMCR) . . . . . . . . . . . . . . . 2338
48.6.9
RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . 2339
48.6.10 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . 2340
48.6.11 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . 2341
48.6.12 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . 2342
48.6.13 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . 2343
48.6.14 RTC timestamp sub second register (RTC_TSSSR) . . . . . . . . . . . . . 2343
48.6.15 RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . 2344
48.6.16 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . 2345
48.6.17 RTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . 2346
48.6.18 RTC alarm B sub second register (RTC_ALRMBSSR) . . . . . . . . . . . 2347
48.6.19 RTC status register (RTC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2348
48.6.20 RTC non-secure masked interrupt status register (RTC_MISR) . . . . 2349
48.6.21 RTC secure masked interrupt status register (RTC_SMISR) . . . . . . 2350
48.6.22 RTC status clear register (RTC_SCR) . . . . . . . . . . . . . . . . . . . . . . . . 2351
48.6.23 RTC configuration register (RTC_CFGR) . . . . . . . . . . . . . . . . . . . . . 2352
48.6.24 RTC hardware configuration register (RTC_HWCFGR) . . . . . . . . . . 2352
48.6.25 RTC version register (RTC_VERR) . . . . . . . . . . . . . . . . . . . . . . . . . . 2353
48.6.26 RTC identification register (RTC_IPIDR) . . . . . . . . . . . . . . . . . . . . . . 2354
48.6.27 RTC size identification register (RTC_SIDR) . . . . . . . . . . . . . . . . . . . 2354
48.6.28 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2355
49
Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . 2358
49.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2358
49.2
TAMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2358
49.3
TAMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2359
49.3.1
TAMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2359
49.3.2
TAMP pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2360
49.3.3
TAMP register write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2361
49.3.4
TAMP secure protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2361
49.3.5
Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2361
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49.4
TAMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2365
49.5
TAMP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2365
49.6
TAMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2366
49.6.1
TAMP control register 1 (TAMP_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 2366
49.6.2
TAMP control register 2 (TAMP_CR2) . . . . . . . . . . . . . . . . . . . . . . . . 2368
49.6.3
TAMP filter control register (TAMP_FLTCR) . . . . . . . . . . . . . . . . . . . 2369
49.6.4
TAMP active tamper control register 1 (TAMP_ATCR1) . . . . . . . . . . 2371
49.6.5
TAMP active tamper seed register (TAMP_ATSEEDR) . . . . . . . . . . . 2372
49.6.6
TAMP active tamper output register (TAMP_ATOR) . . . . . . . . . . . . . 2373
49.6.7
TAMP secure mode register (TAMP_SMCR) . . . . . . . . . . . . . . . . . . . 2374
49.6.8
TAMP interrupt enable register (TAMP_IER) . . . . . . . . . . . . . . . . . . . 2374
49.6.9
TAMP status register (TAMP_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2376
49.6.10 TAMP non-secure masked interrupt status register (TAMP_MISR) . . 2377
49.6.11 TAMP secure masked interrupt status register (TAMP_SMISR) . . . . 2378
49.6.12 TAMP status clear register (TAMP_SCR) . . . . . . . . . . . . . . . . . . . . . 2379
49.6.13 TAMP monotonic counter register (TAMP_COUNTR) . . . . . . . . . . . . 2380
49.6.14 TAMP configuration register (TAMP_CFGR) . . . . . . . . . . . . . . . . . . . 2380
49.6.15 TAMP backup x register (TAMP_BKPxR) . . . . . . . . . . . . . . . . . . . . . 2381
49.6.16 TAMP hardware configuration register 2 (TAMP_HWCFGR2) . . . . . 2381
49.6.17 TAMP hardware configuration register 1 (TAMP_HWCFGR1) . . . . . 2382
49.6.18 TAMP version register (TAMP_VERR) . . . . . . . . . . . . . . . . . . . . . . . 2382
49.6.19 TAMP identification register (TAMP_IPIDR) . . . . . . . . . . . . . . . . . . . 2383
49.6.20 TAMP size identification register (TAMP_SIDR) . . . . . . . . . . . . . . . . 2383
49.6.21 TAMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2384
50
64/3930
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . 2386
50.1
I2C introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2386
50.2
I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2386
50.3
I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2387
50.4
I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2387
50.4.1
I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2388
50.4.2
I2C pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2388
50.4.3
I2C clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2389
50.4.4
I2C mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2389
50.4.5
I2C initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2390
50.4.6
I2C reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2394
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50.4.7
I2C data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2395
50.4.8
I2C target mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2397
50.4.9
I2C controller mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2406
50.4.10 I2C_TIMINGR register configuration examples . . . . . . . . . . . . . . . . . 2417
50.4.11 SMBus specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2419
50.4.12 SMBus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2422
50.4.13 SMBus I2C_TIMEOUTR register configuration examples . . . . . . . . . 2424
50.4.14 SMBus target mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2424
50.4.15 SMBus controller mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2428
50.4.16 Wake-up from Stop mode on address match . . . . . . . . . . . . . . . . . . 2431
50.4.17 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2432
50.5
I2C in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2434
50.6
I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2434
50.7
I2C DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2435
50.7.1
Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2435
50.7.2
Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2435
50.8
I2C debug modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2435
50.9
I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2436
50.9.1
I2C control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2436
50.9.2
I2C control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2438
50.9.3
I2C own address 1 register (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . 2440
50.9.4
I2C own address 2 register (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . 2441
50.9.5
I2C timing register (I2C_TIMINGR) . . . . . . . . . . . . . . . . . . . . . . . . . . 2442
50.9.6
I2C timeout register (I2C_TIMEOUTR) . . . . . . . . . . . . . . . . . . . . . . . 2443
50.9.7
I2C interrupt and status register (I2C_ISR) . . . . . . . . . . . . . . . . . . . . 2444
50.9.8
I2C interrupt clear register (I2C_ICR) . . . . . . . . . . . . . . . . . . . . . . . . 2446
50.9.9
I2C PEC register (I2C_PECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2447
50.9.10 I2C receive data register (I2C_RXDR) . . . . . . . . . . . . . . . . . . . . . . . 2447
50.9.11 I2C transmit data register (I2C_TXDR) . . . . . . . . . . . . . . . . . . . . . . . 2448
50.9.12 I2C hardware configuration register (I2C_HWCFGR) . . . . . . . . . . . . 2448
50.9.13 I2C version register (I2C_VERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2449
50.9.14 I2C identification register (I2C_IPIDR) . . . . . . . . . . . . . . . . . . . . . . . . 2449
50.9.15 I2C size identification register (I2C_SIDR) . . . . . . . . . . . . . . . . . . . . 2449
50.9.16 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2450
51
Universal synchronous/asynchronous receiver
transmitter (USART/UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2452
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51.1
USART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2452
51.2
USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2453
51.3
USART extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2454
51.4
USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2454
51.5
USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2455
51.5.1
USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2455
51.5.2
USART signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2456
51.5.3
USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2457
51.5.4
USART FIFOs and thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2459
51.5.5
USART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2459
51.5.6
USART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2463
51.5.7
USART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2470
51.5.8
Tolerance of the USART receiver to clock deviation . . . . . . . . . . . . . 2471
51.5.9
USART auto baud rate detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2473
51.5.10 USART multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . 2475
51.5.11 USART Modbus communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2477
51.5.12 USART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2478
51.5.13 USART LIN (local interconnection network) mode . . . . . . . . . . . . . . 2479
51.5.14 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2481
51.5.15 USART single-wire half-duplex communication . . . . . . . . . . . . . . . . . 2485
51.5.16 USART receiver timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2485
51.5.17 USART smartcard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2486
51.5.18 USART IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2490
51.5.19 Continuous communication using USART and DMA . . . . . . . . . . . . . 2493
51.5.20 RS232 hardware flow control and RS485 Driver Enable . . . . . . . . . . 2495
51.5.21 USART low-power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2498
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51.6
USART in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2501
51.7
USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2502
51.8
USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2503
51.8.1
USART control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . 2503
51.8.2
USART control register 1 [alternate] (USART_CR1) . . . . . . . . . . . . . 2506
51.8.3
USART control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . 2510
51.8.4
USART control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . 2514
51.8.5
USART baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . 2518
51.8.6
USART guard time and prescaler register (USART_GTPR) . . . . . . . 2518
51.8.7
USART receiver timeout register (USART_RTOR) . . . . . . . . . . . . . . 2519
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51.8.8
USART request register (USART_RQR) . . . . . . . . . . . . . . . . . . . . . . 2520
51.8.9
USART interrupt and status register (USART_ISR) . . . . . . . . . . . . . 2521
51.8.10 USART interrupt and status register [alternate] (USART_ISR) . . . . . 2527
51.8.11 USART interrupt flag clear register (USART_ICR) . . . . . . . . . . . . . . 2532
51.8.12 USART receive data register (USART_RDR) . . . . . . . . . . . . . . . . . . 2534
51.8.13 USART transmit data register (USART_TDR) . . . . . . . . . . . . . . . . . . 2534
51.8.14 USART prescaler register (USART_PRESC) . . . . . . . . . . . . . . . . . . 2535
51.8.15 USART hardware configuration register 2 (USART_HWCFGR2) . . . 2535
51.8.16 USART hardware configuration register 1 (USART_HWCFGR1) . . . 2536
51.8.17 USART version register (USART_VERR) . . . . . . . . . . . . . . . . . . . . . 2537
51.8.18 USART Identification register (USART_IPIDR) . . . . . . . . . . . . . . . . . 2537
51.8.19 USART Size Identification register (USART_SIDR) . . . . . . . . . . . . . 2537
51.8.20 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2539
52
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2541
52.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2541
52.2
SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2542
52.3
SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2542
52.4
SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2543
52.4.1
SPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2543
52.4.2
SPI signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2544
52.4.3
SPI communication general aspects . . . . . . . . . . . . . . . . . . . . . . . . . 2545
52.4.4
Communications between one master and one slave . . . . . . . . . . . . 2545
52.4.5
Standard multislave communication . . . . . . . . . . . . . . . . . . . . . . . . . 2547
52.4.6
Multimaster communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2550
52.4.7
Slave select (SS) pin management . . . . . . . . . . . . . . . . . . . . . . . . . . 2550
52.4.8
Communication formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2554
52.4.9
Configuration of SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2556
52.4.10 Procedure for enabling SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2557
52.4.11 SPI data transmission and reception procedures . . . . . . . . . . . . . . . 2557
52.4.12 Procedure for disabling the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2562
52.4.13 Data packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2563
52.4.14 Communication using DMA (direct memory addressing) . . . . . . . . . . 2564
52.5
SPI specific modes and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2566
52.5.1
TI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2566
52.5.2
SPI error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2566
52.5.3
CRC computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2570
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52.6
Low-power mode management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2571
52.7
SPI wakeup and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2574
52.8
I2S main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2575
52.9
I2S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2576
52.9.1
I2S general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2576
52.9.2
Pin sharing with SPI function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2576
52.9.3
Bitfields usable in I2S/PCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 2577
52.9.4
Slave and master modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2578
52.9.5
Supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2578
52.9.6
Additional Serial Interface Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . 2584
52.9.7
Startup sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2586
52.9.8
Stop sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2588
52.9.9
Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2588
52.9.10 Internal FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2591
52.9.11 FIFOs status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2592
52.9.12 Handling of underrun situation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2592
52.9.13 Handling of overrun situation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2593
52.9.14 Frame error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2594
52.9.15 DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2595
52.9.16 Programing examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2597
52.10 I2S wakeup and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2599
52.11 SPI/I2S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2600
52.11.1 SPI/I2S control register 1 (SPI_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 2600
52.11.2 SPI control register 2 (SPI_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2602
52.11.3 SPI configuration register 1 (SPI_CFG1) . . . . . . . . . . . . . . . . . . . . . . 2602
52.11.4 SPI configuration register 2 (SPI_CFG2) . . . . . . . . . . . . . . . . . . . . . . 2605
52.11.5 SPI/I2S interrupt enable register (SPI_IER) . . . . . . . . . . . . . . . . . . . 2607
52.11.6 SPI/I2S status register (SPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2608
52.11.7 SPI/I2S interrupt/status flags clear register (SPI_IFCR) . . . . . . . . . . 2611
52.11.8 SPI/I2S transmit data register (SPI_TXDR) . . . . . . . . . . . . . . . . . . . . 2612
52.11.9 SPI/I2S receive data register (SPI_RXDR) . . . . . . . . . . . . . . . . . . . . 2612
52.11.10 SPI polynomial register (SPI_CRCPOLY) . . . . . . . . . . . . . . . . . . . . . 2613
52.11.11 SPI transmitter CRC register (SPI_TXCRC) . . . . . . . . . . . . . . . . . . . 2613
52.11.12 SPI receiver CRC register (SPI_RXCRC) . . . . . . . . . . . . . . . . . . . . . 2614
52.11.13 SPI underrun data register (SPI_UDRDR) . . . . . . . . . . . . . . . . . . . . 2615
52.11.14 SPI/I2S configuration register (SPI_I2SCFGR) . . . . . . . . . . . . . . . . . 2615
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52.11.15 SPI/I2S hardware configuration register (SPI_I2S_HWCFGR) . . . . . 2617
52.11.16 SPI/I2S version register (SPI_VERR) . . . . . . . . . . . . . . . . . . . . . . . . 2618
52.11.17 SPI/I2S identification register (SPI_IPIDR) . . . . . . . . . . . . . . . . . . . . 2618
52.11.18 SPI/I2S size identification register (SPI_SIDR) . . . . . . . . . . . . . . . . . 2619
52.12 SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2620
53
Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2622
53.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2622
53.2
SAI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2622
53.3
SAI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2623
53.4
SAI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2624
53.4.1
SAI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2624
53.4.2
SAI pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2625
53.4.3
Main SAI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2626
53.4.4
SAI synchronization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2627
53.4.5
Audio data size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2628
53.4.6
Frame synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2628
53.4.7
Slot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2631
53.4.8
SAI clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2633
53.4.9
Internal FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2636
53.4.10 PDM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2638
53.4.11 AC’97 link controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2646
53.4.12 SPDIF output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2648
53.4.13 Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2651
53.4.14 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2655
53.4.15 Disabling the SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2658
53.4.16 SAI DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2658
53.5
SAI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2659
53.6
SAI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2661
53.6.1
SAI global configuration register (SAI_GCR) . . . . . . . . . . . . . . . . . . . 2661
53.6.2
SAI configuration register 1 (SAI_ACR1) . . . . . . . . . . . . . . . . . . . . . . 2661
53.6.3
SAI configuration register 2 (SAI_ACR2) . . . . . . . . . . . . . . . . . . . . . . 2664
53.6.4
SAI frame configuration register (SAI_AFRCR) . . . . . . . . . . . . . . . . . 2666
53.6.5
SAI slot register (SAI_ASLOTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2667
53.6.6
SAI interrupt mask register (SAI_AIM) . . . . . . . . . . . . . . . . . . . . . . . . 2668
53.6.7
SAI status register (SAI_ASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2670
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53.6.8
SAI clear flag register (SAI_ACLRFR) . . . . . . . . . . . . . . . . . . . . . . . . 2672
53.6.9
SAI data register (SAI_ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2673
53.6.10 SAI configuration register 1 (SAI_BCR1) . . . . . . . . . . . . . . . . . . . . . . 2673
53.6.11 SAI configuration register 2 (SAI_BCR2) . . . . . . . . . . . . . . . . . . . . . . 2676
53.6.12 SAI frame configuration register (SAI_BFRCR) . . . . . . . . . . . . . . . . . 2678
53.6.13 SAI slot register (SAI_BSLOTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2679
53.6.14 SAI interrupt mask register (SAI_BIM) . . . . . . . . . . . . . . . . . . . . . . . . 2680
53.6.15 SAI status register (SAI_BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2681
53.6.16 SAI clear flag register (SAI_BCLRFR) . . . . . . . . . . . . . . . . . . . . . . . . 2683
53.6.17 SAI data register (SAI_BDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2684
53.6.18 SAI PDM control register (SAI_PDMCR) . . . . . . . . . . . . . . . . . . . . . . 2685
53.6.19 SAI PDM delay register (SAI_PDMDLY) . . . . . . . . . . . . . . . . . . . . . . 2686
53.6.20 SAI hardware configuration register (SAI_HWCFGR) . . . . . . . . . . . . 2688
53.6.21 SAI version register (SAI_VERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2689
53.6.22 SAI identification register (SAI_IPIDR) . . . . . . . . . . . . . . . . . . . . . . . 2690
53.6.23 SAI size identification register (SAI_SIDR) . . . . . . . . . . . . . . . . . . . . 2690
53.6.24 SAI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2690
54
SPDIF receiver interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 2693
54.1
SPDIFRX interface introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2693
54.2
SPDIFRX main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2693
54.3
SPDIFRX functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2693
54.3.1
SPDIFRX pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . 2694
54.3.2
S/PDIF protocol (IEC-60958) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2695
54.3.3
SPDIFRX decoder (SPDIFRX_DC) . . . . . . . . . . . . . . . . . . . . . . . . . . 2697
54.3.4
SPDIFRX tolerance to clock deviation . . . . . . . . . . . . . . . . . . . . . . . . 2701
54.3.5
SPDIFRX synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2701
54.3.6
SPDIFRX handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2703
54.3.7
Data reception management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2705
54.3.8
Dedicated control flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2707
54.3.9
Reception errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2708
54.3.10 Clocking strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2710
54.3.11 Symbol clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2710
54.3.12 DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2712
54.3.13 Interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2713
54.3.14 Register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2714
54.4
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54.5
54.4.1
Initialization phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2715
54.4.2
Handling of interrupts coming from SPDIFRX . . . . . . . . . . . . . . . . . . 2716
54.4.3
Handling of interrupts coming from DMA . . . . . . . . . . . . . . . . . . . . . . 2716
SPDIFRX interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2717
54.5.1
SPDIFRX control register (SPDIFRX_CR) . . . . . . . . . . . . . . . . . . . . 2717
54.5.2
SPDIFRX interrupt mask register (SPDIFRX_IMR) . . . . . . . . . . . . . . 2719
54.5.3
SPDIFRX status register (SPDIFRX_SR) . . . . . . . . . . . . . . . . . . . . . 2720
54.5.4
SPDIFRX interrupt flag clear register (SPDIFRX_IFCR) . . . . . . . . . . 2722
54.5.5
SPDIFRX data input register (SPDIFRX_FMT0_DR) . . . . . . . . . . . . 2723
54.5.6
SPDIFRX data input register (SPDIFRX_FMT1_DR) . . . . . . . . . . . . 2723
54.5.7
SPDIFRX data input register (SPDIFRX_FMT2_DR) . . . . . . . . . . . . 2724
54.5.8
SPDIFRX channel status register (SPDIFRX_CSR) . . . . . . . . . . . . . 2725
54.5.9
SPDIFRX debug information register (SPDIFRX_DIR) . . . . . . . . . . . 2725
54.5.10 SPDIFRX version register (SPDIFRX_VERR) . . . . . . . . . . . . . . . . . . 2726
54.5.11 SPDIFRX identification register (SPDIFRX_IPIDR) . . . . . . . . . . . . . . 2726
54.5.12 SPDIFRX size identification register (SPDIFRX_SIDR) . . . . . . . . . . 2727
54.5.13 SPDIFRX interface register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2727
55
Management data input/output (MDIOS) . . . . . . . . . . . . . . . . . . . . . . 2729
55.1
MDIOS introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2729
55.2
MDIOS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2729
55.3
MDIOS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2730
55.4
55.3.1
MDIOS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2730
55.3.2
MDIOS protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2730
55.3.3
MDIOS enabling and disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2731
55.3.4
MDIOS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2731
55.3.5
MDIOS APB frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2733
55.3.6
Write/read flags and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2733
55.3.7
MDIOS error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2733
55.3.8
MDIOS in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2734
55.3.9
MDIOS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2734
MDIOS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2735
55.4.1
MDIOS configuration register (MDIOS_CR) . . . . . . . . . . . . . . . . . . . 2735
55.4.2
MDIOS write flag register (MDIOS_WRFR) . . . . . . . . . . . . . . . . . . . . 2736
55.4.3
MDIOS clear write flag register (MDIOS_CWRFR) . . . . . . . . . . . . . . 2736
55.4.4
MDIOS read flag register (MDIOS_RDFR) . . . . . . . . . . . . . . . . . . . . 2736
55.4.5
MDIOS clear read flag register (MDIOS_CRDFR) . . . . . . . . . . . . . . 2737
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55.4.6
MDIOS status register (MDIOS_SR) . . . . . . . . . . . . . . . . . . . . . . . . . 2737
55.4.7
MDIOS clear flag register (MDIOS_CLRFR) . . . . . . . . . . . . . . . . . . . 2738
55.4.8
MDIOS input data register x (MDIOS_DINRx) . . . . . . . . . . . . . . . . . . 2738
55.4.9
MDIOS output data register x (MDIOS_DOUTRx) . . . . . . . . . . . . . . 2739
55.4.10 MDIOS hardware configuration register (MDIOS_HWCFGR) . . . . . . 2739
55.4.11 MDIOS version register (MDIOS_VERR) . . . . . . . . . . . . . . . . . . . . . 2739
55.4.12 MDIOS identification register (MDIOS_IPIDR) . . . . . . . . . . . . . . . . . 2740
55.4.13 MDIOS size identification register (MDIOS_SIDR) . . . . . . . . . . . . . . 2740
55.4.14 MDIOS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2740
56
Secure digital input/output MultiMediaCard interface (SDMMC) . . 2742
56.1
SDMMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2742
56.2
SDMMC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2742
56.3
SDMMC bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2743
56.4
SDMMC operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2745
56.5
SDMMC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2746
56.6
56.5.1
SDMMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2746
56.5.2
SDMMC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 2746
56.5.3
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2747
56.5.4
SDMMC adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2749
56.5.5
SDMMC AHB slave interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2771
56.5.6
SDMMC AHB master interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2772
56.5.7
AHB and SDMMC_CK clock relation . . . . . . . . . . . . . . . . . . . . . . . . . 2775
Card functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2775
56.6.1
SD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2775
56.6.2
CMD12 send timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2783
56.6.3
Sleep (CMD5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2787
56.6.4
Interrupt mode (Wait-IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2788
56.6.5
Boot operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2789
56.6.6
Response R1b handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2792
56.6.7
Reset and card cycle power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2793
56.7
Hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2794
56.8
Ultra-high-speed phase I (UHS-I) voltage switch . . . . . . . . . . . . . . . . . 2794
56.9
SDMMC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2797
56.10 SDMMC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2799
56.10.1 SDMMC power control register (SDMMC_POWER) . . . . . . . . . . . . . 2799
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56.10.2 SDMMC clock control register (SDMMC_CLKCR) . . . . . . . . . . . . . . 2800
56.10.3 SDMMC argument register (SDMMC_ARGR) . . . . . . . . . . . . . . . . . . 2802
56.10.4 SDMMC command register (SDMMC_CMDR) . . . . . . . . . . . . . . . . . 2802
56.10.5 SDMMC command response register (SDMMC_RESPCMDR) . . . . 2804
56.10.6 SDMMC response x register (SDMMC_RESPxR) . . . . . . . . . . . . . . 2805
56.10.7 SDMMC data timer register (SDMMC_DTIMER) . . . . . . . . . . . . . . . 2805
56.10.8 SDMMC data length register (SDMMC_DLENR) . . . . . . . . . . . . . . . 2806
56.10.9 SDMMC data control register (SDMMC_DCTRL) . . . . . . . . . . . . . . . 2807
56.10.10 SDMMC data counter register (SDMMC_DCNTR) . . . . . . . . . . . . . . 2808
56.10.11 SDMMC status register (SDMMC_STAR) . . . . . . . . . . . . . . . . . . . . . 2809
56.10.12 SDMMC interrupt clear register (SDMMC_ICR) . . . . . . . . . . . . . . . . 2812
56.10.13 SDMMC mask register (SDMMC_MASKR) . . . . . . . . . . . . . . . . . . . . 2814
56.10.14 SDMMC acknowledgment timer register (SDMMC_ACKTIMER) . . . 2817
56.10.15 SDMMC DMA control register (SDMMC_IDMACTRLR) . . . . . . . . . . 2817
56.10.16 SDMMC IDMA buffer size register (SDMMC_IDMABSIZER) . . . . . . 2818
56.10.17 SDMMC IDMA buffer base address register
(SDMMC_IDMABASER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2819
56.10.18 SDMMC IDMA linked list address register (SDMMC_IDMALAR) . . . 2819
56.10.19 SDMMC IDMA linked list memory base register
(SDMMC_IDMABAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2820
56.10.20 SDMMC data FIFO registers x (SDMMC_FIFORx) . . . . . . . . . . . . . . 2821
56.10.21 SDMMC version register (SDMMC_VERR) . . . . . . . . . . . . . . . . . . . . 2821
56.10.22 SDMMC identification register (SDMMC_IPIDR) . . . . . . . . . . . . . . . . 2822
56.10.23 SDMMC size identification register (SDMMC_SIDR) . . . . . . . . . . . . 2822
56.10.24 SDMMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2822
57
Controller area network with flexible data rate (FDCAN) . . . . . . . . 2825
57.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2825
57.2
FDCAN main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2828
57.3
FDCAN implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2828
57.4
FDCAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2829
57.4.1
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2830
57.4.2
Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2839
57.4.3
Message RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2839
57.4.4
FIFO acknowledge handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2851
57.4.5
Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2852
57.4.6
Clock calibration on CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2853
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57.4.7
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2857
57.4.8
TTCAN operations (FDCAN1 only) . . . . . . . . . . . . . . . . . . . . . . . . . . 2858
57.4.9
TTCAN configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2859
57.4.10 Message scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2861
57.4.11 TTCAN gap control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2868
57.4.12 Stop watch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2869
57.4.13 Local time, cycle time, global time,
and external clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . 2869
57.4.14 TTCAN error level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2872
57.4.15 TTCAN message handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2873
57.4.16 TTCAN interrupt and error handling . . . . . . . . . . . . . . . . . . . . . . . . . 2876
57.4.17 Level 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2877
57.4.18 Synchronization to external time schedule . . . . . . . . . . . . . . . . . . . . 2879
57.4.19 FDCAN Rx buffer and FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . 2880
57.4.20 FDCAN Tx buffer element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2882
57.4.21 FDCAN Tx event FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2884
57.4.22 FDCAN standard message ID filter element . . . . . . . . . . . . . . . . . . . 2885
57.4.23 FDCAN extended message ID filter element . . . . . . . . . . . . . . . . . . . 2887
57.4.24 FDCAN trigger memory element . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2888
57.5
FDCAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2890
57.5.1
FDCAN core release register (FDCAN_CREL) . . . . . . . . . . . . . . . . . 2890
57.5.2
FDCAN Endian register (FDCAN_ENDN) . . . . . . . . . . . . . . . . . . . . . 2890
57.5.3
FDCAN data bit timing and prescaler register (FDCAN_DBTP) . . . . 2890
57.5.4
FDCAN test register (FDCAN_TEST) . . . . . . . . . . . . . . . . . . . . . . . . 2891
57.5.5
FDCAN RAM watchdog register (FDCAN_RWD) . . . . . . . . . . . . . . . 2892
57.5.6
FDCAN CC control register (FDCAN_CCCR) . . . . . . . . . . . . . . . . . . 2893
57.5.7
FDCAN nominal bit timing and prescaler register (FDCAN_NBTP) . 2895
57.5.8
FDCAN timestamp counter configuration register (FDCAN_TSCC) . 2896
57.5.9
FDCAN timestamp counter value register (FDCAN_TSCV) . . . . . . . 2896
57.5.10 FDCAN timeout counter configuration register (FDCAN_TOCC) . . . 2897
57.5.11 FDCAN timeout counter value register (FDCAN_TOCV) . . . . . . . . . 2898
57.5.12 FDCAN error counter register (FDCAN_ECR) . . . . . . . . . . . . . . . . . 2898
57.5.13 FDCAN protocol status register (FDCAN_PSR) . . . . . . . . . . . . . . . . 2899
57.5.14 FDCAN transmitter delay compensation register (FDCAN_TDCR) . . 2901
57.5.15 FDCAN interrupt register (FDCAN_IR) . . . . . . . . . . . . . . . . . . . . . . . 2901
57.5.16 FDCAN interrupt enable register (FDCAN_IE) . . . . . . . . . . . . . . . . . 2904
57.5.17 FDCAN interrupt line select register (FDCAN_ILS) . . . . . . . . . . . . . . 2906
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57.5.18 FDCAN interrupt line enable register (FDCAN_ILE) . . . . . . . . . . . . . 2907
57.5.19 FDCAN global filter configuration register (FDCAN_GFC) . . . . . . . . 2908
57.5.20 FDCAN standard ID filter configuration register (FDCAN_SIDFC) . . 2909
57.5.21 FDCAN extended ID filter configuration register (FDCAN_XIDFC) . . 2909
57.5.22 FDCAN extended ID and mask register (FDCAN_XIDAM) . . . . . . . . 2910
57.5.23 FDCAN high priority message status register (FDCAN_HPMS) . . . . 2911
57.5.24 FDCAN new data 1 register (FDCAN_NDAT1) . . . . . . . . . . . . . . . . . 2911
57.5.25 FDCAN new data 2 register (FDCAN_NDAT2) . . . . . . . . . . . . . . . . . 2912
57.5.26 FDCAN Rx FIFO 0 configuration register (FDCAN_RXF0C) . . . . . . . 2912
57.5.27 FDCAN Rx FIFO 0 status register (FDCAN_RXF0S) . . . . . . . . . . . . 2913
57.5.28 FDCAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A) . . . . . . 2914
57.5.29 FDCAN Rx buffer configuration register (FDCAN_RXBC) . . . . . . . . . 2914
57.5.30 FDCAN Rx FIFO 1 configuration register (FDCAN_RXF1C) . . . . . . . 2915
57.5.31 FDCAN Rx FIFO 1 status register (FDCAN_RXF1S) . . . . . . . . . . . . 2916
57.5.32 FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A) . . . . . . 2917
57.5.33 FDCAN Rx buffer element size configuration register
(FDCAN_RXESC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2917
57.5.34 FDCAN Tx buffer configuration register (FDCAN_TXBC) . . . . . . . . . 2918
57.5.35 FDCAN Tx FIFO/queue status register (FDCAN_TXFQS) . . . . . . . . 2919
57.5.36 FDCAN Tx buffer element size configuration register
(FDCAN_TXESC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2920
57.5.37 FDCAN Tx buffer request pending register (FDCAN_TXBRP) . . . . . 2920
57.5.38 FDCAN Tx buffer add request register (FDCAN_TXBAR) . . . . . . . . . 2921
57.5.39 FDCAN Tx buffer cancellation request register (FDCAN_TXBCR) . . 2922
57.5.40 FDCAN Tx buffer transmission occurred register (FDCAN_TXBTO) 2922
57.5.41 FDCAN Tx buffer cancellation finished register (FDCAN_TXBCF) . . 2923
57.5.42 FDCAN Tx buffer transmission interrupt enable register
(FDCAN_TXBTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2923
57.5.43 FDCAN Tx buffer cancellation finished interrupt enable register
(FDCAN_TXBCIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2924
57.5.44 FDCAN Tx event FIFO configuration register (FDCAN_TXEFC) . . . 2924
57.5.45 FDCAN Tx event FIFO status register (FDCAN_TXEFS) . . . . . . . . . 2925
57.5.46 FDCAN Tx event FIFO acknowledge register (FDCAN_TXEFA) . . . 2926
57.5.47 FDCAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2926
57.6
TTCAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2930
57.6.1
FDCAN TT trigger memory configuration register
(FDCAN_TTTMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2930
57.6.2
FDCAN TT reference message configuration register
(FDCAN_TTRMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2930
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57.6.3
FDCAN TT operation configuration register (FDCAN_TTOCF) . . . . . 2931
57.6.4
FDCAN TT matrix limits register (FDCAN_TTMLM) . . . . . . . . . . . . . 2933
57.6.5
FDCAN TUR configuration register (FDCAN_TURCF) . . . . . . . . . . . 2934
57.6.6
FDCAN TT operation control register (FDCAN_TTOCN) . . . . . . . . . 2935
57.6.7
FDCAN TT global time preset register (FDCAN_TTGTP) . . . . . . . . . 2937
57.6.8
FDCAN TT time mark register (FDCAN_TTTMK) . . . . . . . . . . . . . . . 2937
57.6.9
FDCAN TT interrupt register (FDCAN_TTIR) . . . . . . . . . . . . . . . . . . 2938
57.6.10 FDCAN TT interrupt enable register (FDCAN_TTIE) . . . . . . . . . . . . . 2940
57.6.11 FDCAN TT interrupt line select register (FDCAN_TTILS) . . . . . . . . . 2942
57.6.12 FDCAN TT operation status register (FDCAN_TTOST) . . . . . . . . . . 2943
57.6.13 FDCAN TUR numerator actual register (FDCAN_TURNA) . . . . . . . . 2945
57.6.14 FDCAN TT local and global time register (FDCAN_TTLGT) . . . . . . . 2946
57.6.15 FDCAN TT cycle time and count register (FDCAN_TTCTC) . . . . . . . 2946
57.6.16 FDCAN TT capture time register (FDCAN_TTCPT) . . . . . . . . . . . . . 2947
57.6.17 FDCAN TT cycle sync mark register (FDCAN_TTCSM) . . . . . . . . . . 2947
57.6.18 FDCAN TT trigger select register (FDCAN_TTTS) . . . . . . . . . . . . . . 2948
57.6.19 FDCAN TT register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2948
57.7
58
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57.7.1
Clock calibration unit core release register (FDCAN_CCU_CREL) . . 2950
57.7.2
Calibration configuration register (FDCAN_CCU_CCFG) . . . . . . . . . 2950
57.7.3
Calibration status register (FDCAN_CCU_CSTAT) . . . . . . . . . . . . . . 2952
57.7.4
Calibration watchdog register (FDCAN_CCU_CWD) . . . . . . . . . . . . 2952
57.7.5
Clock calibration unit interrupt register (FDCAN_CCU_IR) . . . . . . . . 2953
57.7.6
Clock calibration unit interrupt enable register (FDCAN_CCU_IE) . . 2954
57.7.7
CCU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2954
USB on-the-go high-speed (OTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2956
58.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2956
58.2
OTG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2957
58.2.1
General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2957
58.2.2
Host-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2958
58.2.3
Peripheral-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2958
58.3
OTG implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2959
58.4
OTG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2960
58.4.1
OTG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2960
58.4.2
OTG pin and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2960
58.4.3
OTG core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2961
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58.5
58.6
58.7
58.8
58.9
58.4.4
Embedded full-speed OTG PHY connected to OTG . . . . . . . . . . . . . 2961
58.4.5
OTG detections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2962
58.4.6
High-speed OTG PHY connected to OTG_HS . . . . . . . . . . . . . . . . . 2962
OTG dual role device (DRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2963
58.5.1
ID line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2963
58.5.2
HNP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2963
58.5.3
SRP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2964
OTG as a USB peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2964
58.6.1
SRP-capable peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2965
58.6.2
Peripheral states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2965
58.6.3
Peripheral endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2966
OTG as a USB host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2968
58.7.1
SRP-capable host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2969
58.7.2
USB host states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2969
58.7.3
Host channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2971
58.7.4
Host scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2972
OTG SOF trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2973
58.8.1
Host SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2973
58.8.2
Peripheral SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2973
OTG low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2974
58.10 OTG Dynamic update of the OTG_HFIR register . . . . . . . . . . . . . . . . 2975
58.11 OTG data FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2975
58.11.1 Peripheral FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2976
58.11.2 Host FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2977
58.11.3 FIFO RAM allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2978
58.12 OTG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2980
58.13 OTG control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2982
58.13.1 CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2982
58.14 OTG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2987
58.14.1 OTG control and status register (OTG_GOTGCTL) . . . . . . . . . . . . . 2987
58.14.2 OTG interrupt register (OTG_GOTGINT) . . . . . . . . . . . . . . . . . . . . . 2990
58.14.3 OTG AHB configuration register (OTG_GAHBCFG) . . . . . . . . . . . . . 2992
58.14.4 OTG USB configuration register (OTG_GUSBCFG) . . . . . . . . . . . . . 2993
58.14.5 OTG reset register (OTG_GRSTCTL) . . . . . . . . . . . . . . . . . . . . . . . . 2995
58.14.6 OTG core interrupt register (OTG_GINTSTS) . . . . . . . . . . . . . . . . . . 2998
58.14.7 OTG interrupt mask register (OTG_GINTMSK) . . . . . . . . . . . . . . . . . 3002
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58.14.8 OTG receive status debug read register (OTG_GRXSTSR) . . . . . . . 3006
58.14.9 OTG receive status debug read [alternate] (OTG_GRXSTSR) . . . . . 3007
58.14.10 OTG status read and pop registers (OTG_GRXSTSP) . . . . . . . . . . . 3008
58.14.11 OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . 3009
58.14.12 OTG receive FIFO size register (OTG_GRXFSIZ) . . . . . . . . . . . . . . 3010
58.14.13 OTG host non-periodic transmit FIFO size register
(OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size
(OTG_DIEPTXF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3010
58.14.14 OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3011
58.14.15 OTG general core configuration register (OTG_GCCFG) . . . . . . . . . 3012
58.14.16 OTG core ID register (OTG_CID) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3014
58.14.17 OTG core LPM configuration register (OTG_GLPMCFG) . . . . . . . . . 3014
58.14.18 OTG host periodic transmit FIFO size register
(OTG_HPTXFSIZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3018
58.14.19 OTG device IN endpoint transmit FIFO x size register
(OTG_DIEPTXFx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3018
58.14.20 Host-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3019
58.14.21 OTG host configuration register (OTG_HCFG) . . . . . . . . . . . . . . . . . 3019
58.14.22 OTG host frame interval register (OTG_HFIR) . . . . . . . . . . . . . . . . . 3020
58.14.23 OTG host frame number/frame time remaining register
(OTG_HFNUM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3021
58.14.24 OTG_Host periodic transmit FIFO/queue status register
(OTG_HPTXSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3022
58.14.25 OTG host all channels interrupt register (OTG_HAINT) . . . . . . . . . . 3023
58.14.26 OTG host all channels interrupt mask register
(OTG_HAINTMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3023
58.14.27 OTG host frame list base address register
(OTG_HFLBADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3024
58.14.28 OTG host port control and status register (OTG_HPRT) . . . . . . . . . . 3024
58.14.29 OTG host channel x characteristics register (OTG_HCCHARx) . . . . 3027
58.14.30 OTG host channel x split control register (OTG_HCSPLTx) . . . . . . . 3028
58.14.31 OTG host channel x interrupt register (OTG_HCINTx) . . . . . . . . . . . 3029
58.14.32 OTG host channel x interrupt mask register (OTG_HCINTMSKx) . . 3030
58.14.33 OTG host channel x transfer size register (OTG_HCTSIZx) . . . . . . . 3032
58.14.34 OTG host channel x transfer size register (OTG_HCTSIZSGx) . . . . 3033
58.14.35 OTG host channel x DMA address register in buffer DMA [alternate]
(OTG_HCDMAx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3035
58.14.36 OTG host channel x DMA address register in scatter/gather DMA
[alternate] (OTG_HCDMASGx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3035
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58.14.37 OTG host channel-n DMA address buffer register
(OTG_HCDMABx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3036
58.14.38 Device-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3037
58.14.39 OTG device configuration register (OTG_DCFG) . . . . . . . . . . . . . . . 3037
58.14.40 OTG device control register (OTG_DCTL) . . . . . . . . . . . . . . . . . . . . 3038
58.14.41 OTG device status register (OTG_DSTS) . . . . . . . . . . . . . . . . . . . . . 3041
58.14.42 OTG device IN endpoint common interrupt mask register
(OTG_DIEPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3042
58.14.43 OTG device OUT endpoint common interrupt mask register
(OTG_DOEPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3043
58.14.44 OTG device all endpoints interrupt register (OTG_DAINT) . . . . . . . . 3044
58.14.45 OTG all endpoints interrupt mask register
(OTG_DAINTMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3045
58.14.46 OTG device VBUS discharge time register
(OTG_DVBUSDIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3046
58.14.47 OTG device VBUS pulsing time register
(OTG_DVBUSPULSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3046
58.14.48 OTG device threshold control register (OTG_DTHRCTL) . . . . . . . . . 3047
58.14.49 OTG device IN endpoint FIFO empty interrupt mask register
(OTG_DIEPEMPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3048
58.14.50 OTG device IN endpoint x control register (OTG_DIEPCTLx) . . . . . 3048
58.14.51 OTG device IN endpoint x interrupt register (OTG_DIEPINTx) . . . . . 3051
58.14.52 OTG device IN endpoint 0 transfer size register
(OTG_DIEPTSIZ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3052
58.14.53 OTG device IN endpoint x DMA address register
(OTG_DIEPDMAx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3053
58.14.54 OTG device IN endpoint transmit FIFO status register
(OTG_DTXFSTSx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3053
58.14.55 OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) . 3054
58.14.56 OTG device control OUT endpoint 0 control register
(OTG_DOEPCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3055
58.14.57 OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) . . 3056
58.14.58 OTG device OUT endpoint 0 transfer size register
(OTG_DOEPTSIZ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3058
58.14.59 OTG device OUT endpoint x DMA address register
(OTG_DOEPDMAx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3059
58.14.60 OTG device OUT endpoint x control register
(OTG_DOEPCTLx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3059
58.14.61 OTG device OUT endpoint x transfer size register
(OTG_DOEPTSIZx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3062
58.14.62 OTG power and clock gating control register (OTG_PCGCCTL) . . . 3063
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58.14.63 OTG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3064
58.15 OTG programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3075
58.15.1 Core initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3075
58.15.2 Host initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3076
58.15.3 Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3077
58.15.4 DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3077
58.15.5 Host programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3078
58.15.6 Device programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3110
58.15.7 Worst case response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3130
58.15.8 OTG programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3132
59
USB HS PHY controller (USBPHYC) . . . . . . . . . . . . . . . . . . . . . . . . . 3138
59.1
USBPHYC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3138
59.2
USBPHYC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3138
59.3
USBPHYC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3138
59.4
60
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59.3.1
USBPHYC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3138
59.3.2
USBPHYC reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3139
59.3.3
PLL control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3139
USBPHYC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3141
59.4.1
USBPHYC PLL control register (USBPHYC_PLL) . . . . . . . . . . . . . . 3141
59.4.2
USBPHYC misc control register (USBPHYC_MISC) . . . . . . . . . . . . 3143
59.4.3
USBPHYC PHY x MONITOR register (USBPHYC_MONITORx) . . . 3144
59.4.4
USBPHYC PHY x TUNE register (USBPHYC_TUNEx) . . . . . . . . . . 3145
59.4.5
USBPHYC VERSION register (USBPHYC_VERR) . . . . . . . . . . . . . 3147
59.4.6
USBPHYC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3148
USB_EHCI/USB_OHCI high/full-speed link controller (USBH) . . . . 3150
60.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3150
60.2
USBH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3150
60.3
USBH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3151
60.3.1
USBH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3151
60.3.2
USBH reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3151
60.3.3
Description of USBH packet buffer . . . . . . . . . . . . . . . . . . . . . . . . . . 3151
60.3.4
Description of USBH root hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3152
60.4
USBH interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3152
60.5
USBH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3152
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60.5.1
USBH OHCI standard registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3152
60.5.2
USBH OHCI implementation register #6
(USBH_OHCI_INSNREG06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3153
60.5.3
USBH OHCI implementation register #7
(USBH_OHCI_INSNREG07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3154
60.5.4
USBH EHCI standard registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3155
60.5.5
USBH EHCI implementation register #1
(USBH_EHCI_INSNREG01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3155
60.5.6
USBH EHCI implementation register #2
(USBH_EHCI_INSNREG02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3156
60.5.7
USBH EHCI implementation register #3
(USBH_EHCI_INSNREG03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3157
60.5.8
USBH EHCI implementation register #4
(USBH_EHCI_INSNREG04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3158
60.5.9
USBH EHCI implementation register #5
(USBH_EHCI_INSNREG05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3159
60.5.10 USBH EHCI implementation register #6
(USBH_EHCI_INSNREG06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3160
60.5.11 USBH EHCI implementation register #7
(USBH_EHCI_INSNREG07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3161
60.5.12 USBH register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3161
61
Ethernet (ETH): gigabit media access control
(GMAC) with DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3166
61.1
Ethernet introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3166
61.2
Ethernet main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3166
61.2.1
Standard compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3166
61.2.2
MAC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3166
61.2.3
Transaction layer (MTL) features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3168
61.2.4
DMA block features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3169
61.2.5
Bus interface features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3170
61.2.6
Audio and video features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3170
61.2.7
Generic queuing features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3171
61.3
Ethernet pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3171
61.4
Ethernet architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3173
61.4.1
DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3174
61.4.2
MTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3181
61.4.3
MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3181
61.4.4
Multiple channels and queues support . . . . . . . . . . . . . . . . . . . . . . . 3186
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61.5
Ethernet functional description: MAC . . . . . . . . . . . . . . . . . . . . . . . . . . 3194
61.5.1
Double VLAN processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3194
61.5.2
Source address and VLAN insertion, replacement, or deletion . . . . . 3196
61.5.3
Packet filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3197
61.5.4
IEEE 1588 timestamp support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3204
61.5.5
Checksum offload engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3229
61.5.6
TCP segmentation offload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3235
61.5.7
IPv4 ARP offload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3241
61.5.8
Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3242
61.5.9
Flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3243
61.5.10 MAC management counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3246
61.5.11 Interrupts generated by the MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3248
61.5.12 MAC and MMC register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 3248
61.6
61.7
61.8
61.9
82/3930
Ethernet functional description: PHY interfaces . . . . . . . . . . . . . . . . . . 3249
61.6.1
Station management agent (SMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 3249
61.6.2
Media independent interface (MII) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3256
61.6.3
Gigabit media independent interface (GMII) . . . . . . . . . . . . . . . . . . . 3258
61.6.4
Reduced media independent interface (RMII) . . . . . . . . . . . . . . . . . . 3259
61.6.5
Reduced gigabit media independent interface (RGMII) . . . . . . . . . . . 3262
Ethernet low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3265
61.7.1
Low-power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3265
61.7.2
Energy Efficient Ethernet (EEE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3271
Ethernet interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3277
61.8.1
DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3277
61.8.2
MTL interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3279
61.8.3
MAC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3279
Ethernet programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3280
61.9.1
DMA initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3280
61.9.2
MTL initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3281
61.9.3
MAC initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3281
61.9.4
Performing normal receive and transmit operation . . . . . . . . . . . . . . 3282
61.9.5
Stopping and starting transmission . . . . . . . . . . . . . . . . . . . . . . . . . . 3283
61.9.6
Programming guidelines for switching to new descriptor list
in RxDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3283
61.9.7
Programming guidelines for switching the AXI clock frequency . . . . 3284
61.9.8
Programming guidelines for multichannel multiqueue operation . . . . 3284
61.9.9
Programming guidelines for GMII link state transitions . . . . . . . . . . . 3286
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61.9.10 Programming guidelines for IEEE 1588 timestamping . . . . . . . . . . . 3287
61.9.11 Programming guidelines for PTP offload feature . . . . . . . . . . . . . . . . 3288
61.9.12 Programming guidelines for AV feature . . . . . . . . . . . . . . . . . . . . . . . 3292
61.9.13 Programming guidelines for Energy Efficient Ethernet (EEE) . . . . . . 3294
61.9.14 Programming guidelines for flexible pulse-per-second (PPS) output 3295
61.9.15 Programming guidelines for IEEE 1588 auxiliary snapshot . . . . . . . . 3298
61.9.16 Programming guidelines for TSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3298
61.9.17 Programming guidelines to perform VLAN filtering on the receiver . . 3299
61.10 Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3300
61.10.1 Descriptor overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3300
61.10.2 Descriptor structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3300
61.10.3 Transmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3304
61.10.4 Receive descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3317
61.11 Ethernet registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3329
61.11.1 Ethernet register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3329
61.11.2 Ethernet DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3329
61.11.3 Ethernet MTL registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3359
61.11.4 Ethernet MAC and MMC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 3378
62
HDMI-CEC controller (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3483
62.1
HDMI-CEC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3483
62.2
HDMI-CEC controller main features . . . . . . . . . . . . . . . . . . . . . . . . . . . 3483
62.3
HDMI-CEC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3484
62.4
62.3.1
HDMI-CEC pin and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . 3484
62.3.2
HDMI-CEC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3485
62.3.3
Message description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3485
62.3.4
Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3486
Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3486
62.4.1
62.5
SFT option bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3488
Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3488
62.5.1
Bit error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3488
62.5.2
Message error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3489
62.5.3
Bit rising error (BRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3489
62.5.4
Short bit period error (SBPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3489
62.5.5
Long bit period error (LBPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3489
62.5.6
Transmission error detection (TXERR) . . . . . . . . . . . . . . . . . . . . . . . 3491
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62.6
HDMI-CEC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3492
62.7
HDMI-CEC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3493
62.7.1
CEC control register (CEC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3493
62.7.2
CEC configuration register (CEC_CFGR) . . . . . . . . . . . . . . . . . . . . . 3494
62.7.3
CEC Tx data register (CEC_TXDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 3496
62.7.4
CEC Rx data register (CEC_RXDR) . . . . . . . . . . . . . . . . . . . . . . . . . 3496
62.7.5
CEC interrupt and status register (CEC_ISR) . . . . . . . . . . . . . . . . . . 3496
62.7.6
CEC interrupt enable register (CEC_IER) . . . . . . . . . . . . . . . . . . . . . 3498
62.7.7
HDMI-CEC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3500
Hardware debug port (HDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3501
63.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3501
63.2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3501
63.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3502
63.4
HDP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3505
63.4.1
HDP control register (HDP_CTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . 3505
63.4.2
HDP multiplexers control register (HDP_MUX) . . . . . . . . . . . . . . . . . 3505
63.4.3
HDP read back value register (HDP_VAL) . . . . . . . . . . . . . . . . . . . . 3506
63.4.4
HDP general purpose output set register (HDP_GPOSET) . . . . . . . . 3507
63.4.5
HDP general purpose output clear register (HDP_GPOCLR) . . . . . . 3507
63.4.6
HDP general purpose output value register (HDP_GPOVAL) . . . . . . 3508
63.4.7
HDP version register (HDP_VERR) . . . . . . . . . . . . . . . . . . . . . . . . . . 3508
63.4.8
HDP IP identification register (HDP_IPIDR) . . . . . . . . . . . . . . . . . . . 3509
63.4.9
HDP size identification register (HDP_SIDR) . . . . . . . . . . . . . . . . . . 3509
63.4.10 HDP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3509
64
84/3930
Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3511
64.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3511
64.2
Debug use cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3512
64.3
DBG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3513
64.4
DBG pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3514
64.5
DBG power and clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3514
64.5.1
DBG power domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3514
64.5.2
DBG clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3515
64.5.3
Debug and low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3516
64.5.4
DBG reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3516
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Contents
64.6
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3516
64.6.1
Authentication signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3517
64.7
Chip level TAP controller (CLTAPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3518
64.8
Serial wire and JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . 3519
64.9
64.8.1
JTAG debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3520
64.8.2
Serial Wire debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3523
64.8.3
Debug port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3524
Access ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3533
64.9.1
Authentication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3534
64.9.2
MEM-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3535
64.10 System debug features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3545
64.10.1 System ROM tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3545
64.10.2 CoreSight™ global timestamp generator (TSGEN) . . . . . . . . . . . . . . 3554
64.10.3 Cross trigger interface (CTI) and matrix (CTM) . . . . . . . . . . . . . . . . . 3562
64.10.4 Trace funnel (CSTF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3585
64.10.5 Embedded trace FIFO (ETF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3596
64.10.6 Trace port interface unit (TPIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3617
64.10.7 Serial wire output (SWO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3635
64.10.8 System trace macrocell (STM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3647
64.10.9 Microprocessor debug unit (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . 3684
64.11 Cortex®-A7 debug features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3696
64.11.1 Cortex®-A7 debug unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3697
64.11.2 Cortex®-A7 performance monitoring unit (PMU) . . . . . . . . . . . . . . . . 3739
64.11.3 Embedded trace macrocell (ETM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3760
64.11.4 Cross trigger interface (CTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3811
64.12 Cortex®-M4 debug features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3812
64.12.1 ROM tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3812
64.12.2 Data watchpoint and trace unit (DWT) . . . . . . . . . . . . . . . . . . . . . . . . 3818
64.12.3 Instrumentation trace macrocell (ITM) . . . . . . . . . . . . . . . . . . . . . . . . 3832
64.12.4 Breakpoint unit (FPB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3842
64.12.5 Embedded trace macrocell (ETM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3850
64.12.6 Cross trigger interface (CTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3871
64.13 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3872
65
Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3873
65.1
Unique device ID register (96 bits) (UID) . . . . . . . . . . . . . . . . . . . . . . . 3873
RM0442 Rev 7
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Contents
RM0442
65.2
Device part number (RPN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3875
65.3
Device version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3875
65.4
Package data register (PKG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3876
66
Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3877
67
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3878
86/3930
RM0442 Rev 7
RM0442
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Memory map overview STM32MP153 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Master ports main characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Master ports security characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Slave ports main characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Slave ports security characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Multi-layer AHB master ports main characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Multi-layer AHB slave ports main characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
AXIMC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Debugger Register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
OTP modes definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
OTP permanent write lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
BSEC_DENABLE default values after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Write access permissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Read access permissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
BSEC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
OTP list words 0 to 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
OTP list words 32 to 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
DDRCTRL register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
NSAID and AXI _ID mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
TZC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
DDRPHYC I/O list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
MSDLL control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
PHY latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
DFI timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
DDRPHYC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
DDRPERFM signal sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Power control register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
PWR pin overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
MPU Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
MCU Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
PWR system mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
System Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
Functionalities depending on system operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
PDDS low-power mode control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
Low-power mode exit flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
MPU CSleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
MCU CSleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
MPU CStop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
MCU CStop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
MPU CStandby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
LP-Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
LPLV-Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
PWR status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
Register security overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
Power control register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
RM0442 Rev 7
87/3930
98
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
88/3930
RM0442
Pin overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
Reset coverage summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
RCC registers with specific reset and specific voltages . . . . . . . . . . . . . . . . . . . . . . . . . . 511
Reset source identification (RCC_MP/MC/BR_RSTSCLRR,
and PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Oscillator states versus system modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
HSI, CSI and HSE states versus system modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
Resources blocked during clock restore sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
Peripheral clock distribution overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
Kernel clock settings examples for audio applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
Ratio between clock timers and pclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
Gating control of the aclk_[2:1] clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
DDRCKMOD control description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
DDRC low-power (DDRC-LP) states description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
Recommended configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
Peripheral clock enable details for MPU (MCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
MPU mode details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
Bus clock enable details for AXIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
Bus clock enable details for AHB5 and AHB6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
Bus clock enable details for MLAHB and AHB4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
Bus clock enable details for AHB[3:1]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
Bus clock enable details for APB[5:1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
Interrupt sources and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
Clock settings examples for MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
Clock setting examples for AXI, DDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
Access results according to register security attributes . . . . . . . . . . . . . . . . . . . . . . . . . . 630
Register access type versus protection and security . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997
HSEM internal input/output signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
Authorized AHB bus master IDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
HSEM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041
IPCC interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044
Bits used for the communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045
IPCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
GPIO secured bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068
GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
SYSCFG interface register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105
STM32MP153 secure and securable peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110
STM32MP153 TrustZone-aware peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111
STM32MP153 memory firewalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111
STM32MP153 TrustZone-capable bus masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112
decprot bits for securable peripherals (type 1) and behavior . . . . . . . . . . . . . . . . . . . . . 1112
decprot bits for isolable peripherals (type 2) and behavior . . . . . . . . . . . . . . . . . . . . . . . 1113
decprot bits for securable and Isolable Peripherals (type 3) and behavior . . . . . . . . . . . 1113
Programmable options according to resource type . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1114
DECPROT assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1114
ETZPC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129
Peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132
Peripherals interconnect matrix details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135
MDMA connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150
MDMA internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154
RM0442 Rev 7
RM0442
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
Table 131.
Table 132.
Table 133.
Table 134.
Table 135.
Table 136.
Table 137.
Table 138.
Table 139.
Table 140.
Table 141.
Table 142.
Table 143.
Table 144.
Table 145.
Table 146.
Table 147.
Table 148.
Table 149.
Table 150.
Table 151.
List of tables
MDMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1160
MDMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175
Source and destination address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1181
Source and destination address registers in double-buffer mode (DBM = 1) . . . . . . . . . 1186
Packing/unpacking and endian behavior (bit PINC = MINC = 1) . . . . . . . . . . . . . . . . . . 1187
Restriction on NDT versus PSIZE and MSIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187
FIFO threshold configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1190
Possible DMA configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194
DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196
DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1209
DMAMUX instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215
DMAMUX: assignment of multiplexer inputs to resources . . . . . . . . . . . . . . . . . . . . . . . 1216
DMAMUX: assignment of trigger inputs to resources . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217
DMAMUX: assignment of synchronization inputs to resources . . . . . . . . . . . . . . . . . . . 1217
DMAMUX signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219
DMAMUX interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223
DMAMUX register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1230
STM32MP153 interrupt mapping for Cortex®-M4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233
STM32MP153 interrupt mapping for Cortex®-A7 GIC . . . . . . . . . . . . . . . . . . . . . . . . . . 1238
STM32MP153 EXTI Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245
GICD register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271
GICC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284
GICH register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291
GICV register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299
EXTI pin overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1302
EVG pin overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303
EXTI event input configurations and register control . . . . . . . . . . . . . . . . . . . . . . . . . . . 1304
Masking functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1307
Register security overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1308
EXTI register map sections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1310
EXTI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1340
CRC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1345
CRC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1351
FMC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354
FMC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355
FMC memory regions (default mapping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357
NOR/PSRAM subregion selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1358
NOR/PSRAM External memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1358
NAND memory mapping and timing registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1358
NAND flash memory region selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1359
NAND chip enable selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1359
Programmable NOR/PSRAM access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361
Non-multiplexed I/O NOR flash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361
16-bit multiplexed I/O NOR flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1362
Non-multiplexed I/Os PSRAM/SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1362
16-bit multiplexed I/O PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1362
NOR flash/PSRAM: Example of supported memories and transactions . . . . . . . . . . . . 1363
FMC_BCRx bitfields (mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1367
FMC_BTRx bitfields (mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1367
FMC_BCRx bitfields (mode A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1369
FMC_BTRx bitfields (mode A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1370
FMC_BWTRx bitfields (mode A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1370
RM0442 Rev 7
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98
List of tables
RM0442
Table 152.
Table 153.
Table 154.
Table 155.
Table 156.
Table 157.
Table 158.
Table 159.
Table 160.
Table 161.
Table 162.
Table 163.
Table 164.
Table 165.
Table 166.
Table 167.
Table 168.
Table 169.
Table 170.
Table 171.
Table 172.
Table 173.
Table 174.
Table 175.
Table 176.
Table 177.
Table 178.
Table 179.
Table 180.
Table 181.
Table 182.
Table 183.
Table 184.
Table 185.
Table 186.
Table 187.
Table 188.
Table 189.
Table 190.
Table 191.
Table 192.
Table 193.
Table 194.
Table 195.
Table 196.
Table 197.
Table 198.
Table 199.
Table 200.
Table 201.
FMC_BCRx bitfields (mode 2/B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373
FMC_BTRx bitfields (mode 2/B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373
FMC_BWTRx bitfields (mode 2/B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1374
FMC_BCRx bitfields (mode C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1376
FMC_BTRx bitfields (mode C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1376
FMC_BWTRx bitfields (mode C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377
FMC_BCRx bitfields (mode D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1378
FMC_BTRx bitfields (mode D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1379
FMC_BWTRx bitfields (mode D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1379
FMC_BCRx bitfields (muxed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1381
FMC_BTRx bitfields (muxed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1382
FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . . . . . . . . . . . . . . . . . . 1387
FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . . . . . . . . . . . . . . . . . . 1388
FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . . . . . . . . . . . . . . . . . . 1389
FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . . . . . . . . . . . . . . . . . . 1390
Programmable NAND flash access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1404
8-bit NAND flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1404
16-bit NAND flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1405
Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1405
Number of ECC parity bytes per sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1410
FMC NAND controller Interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1418
HPR relevant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424
ECC result relevant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425
FMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1443
QUADSPI internal signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1448
QUADSPI pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1448
QUADSPI interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1462
QUADSPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1476
DLYB internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479
DLYB interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479
Delay block control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1480
DLYB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482
ADC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1485
ADC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1487
ADC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1487
ADC interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1488
Configuring the trigger polarity for regular external triggers . . . . . . . . . . . . . . . . . . . . . . 1507
Configuring the trigger polarity for injected external triggers . . . . . . . . . . . . . . . . . . . . . 1507
ADC1, ADC2 - External triggers for regular channels. . . . . . . . . . . . . . . . . . . . . . . . . . . 1508
ADC1, ADC2- External triggers for injected channels . . . . . . . . . . . . . . . . . . . . . . . . . . 1509
TSAR timings depending on resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1521
Offset computation versus data resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1524
16-bit data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1527
Numerical examples for 16-bit format (bold indicates saturation). . . . . . . . . . . . . . . . . . 1527
Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1536
Analog watchdog 1,2,3 comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1537
Oversampler operating modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1545
ADC interrupts per each ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564
DELAY bits versus ADC resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1604
ADC register map and reset values for each ADC (offset=0x000
for master ADC, 0x100 for slave ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607
Table 202. ADC register map and reset values (master and slave ADC
90/3930
RM0442 Rev 7
RM0442
Table 203.
Table 204.
Table 205.
Table 206.
Table 207.
Table 208.
Table 209.
Table 210.
Table 211.
Table 212.
Table 213.
Table 214.
Table 215.
Table 216.
Table 217.
Table 218.
Table 219.
Table 220.
Table 221.
Table 222.
Table 223.
Table 224.
Table 225.
Table 226.
Table 227.
Table 228.
Table 229.
Table 230.
Table 231.
Table 232.
Table 233.
Table 234.
Table 235.
Table 236.
Table 237.
Table 238.
Table 239.
Table 240.
Table 241.
Table 242.
Table 243.
Table 244.
Table 245.
Table 246.
Table 247.
Table 248.
Table 249.
Table 250.
Table 251.
List of tables
common registers) offset =0x300) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610
DTS internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613
Sampling time configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1616
Trigger configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617
Temperature sensor behavior in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1619
Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1620
DTS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628
DAC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1630
DAC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632
DAC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632
DAC interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
Sample and refresh timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640
Channel output modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1641
Effect of low-power modes on DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648
DAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649
DAC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666
VREF buffer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669
VREFBUF register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1671
DFSDM1 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1674
DFSDM external pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1676
DFSDM internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1676
DFSDM triggers connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1676
DFSDM break connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1677
Filter maximum output resolution (peak data values from filter output)
for some FOSR values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1692
Integrator maximum output resolution (peak data values from integrator
output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data) . . . 1693
DFSDM interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1701
DFSDM register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1725
DCMI input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1739
DCMI internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1739
Positioning of captured data bytes in 32-bit words (8-bit width) . . . . . . . . . . . . . . . . . . . 1741
Positioning of captured data bytes in 32-bit words (10-bit width) . . . . . . . . . . . . . . . . . . 1741
Positioning of captured data bytes in 32-bit words (12-bit width) . . . . . . . . . . . . . . . . . . 1741
Positioning of captured data bytes in 32-bit words (14-bit width) . . . . . . . . . . . . . . . . . . 1742
Data storage in monochrome progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . 1747
Data storage in RGB progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1748
Data storage in YCbCr progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1748
Data storage in YCbCr progressive video format - Y extraction mode . . . . . . . . . . . . . . 1748
DCMI interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1749
DCMI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1759
LTDC external pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1761
LTDC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1762
Clock domain for each register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1762
LTDC register access and update durations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1763
Pixel data mapping versus color format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1767
LTDC interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1771
LTDC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1790
RNG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1795
RNG interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1801
RNG configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1802
RNG register map and reset map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1806
RM0442 Rev 7
91/3930
98
List of tables
Table 252.
Table 253.
Table 254.
Table 255.
Table 256.
Table 257.
Table 258.
Table 259.
Table 260.
Table 261.
Table 262.
Table 263.
Table 264.
Table 265.
Table 266.
Table 267.
Table 268.
Table 269.
Table 270.
Table 271.
Table 272.
Table 273.
Table 274.
Table 275.
Table 276.
Table 277.
Table 278.
Table 279.
Table 280.
Table 281.
Table 282.
Table 283.
Table 284.
Table 285.
Table 286.
Table 287.
Table 288.
Table 289.
Table 290.
Table 291.
Table 292.
Table 293.
Table 294.
Table 295.
Table 296.
Table 297.
Table 298.
Table 299.
92/3930
RM0442
CRYP internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1811
Counter mode initialization vector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1835
GCM last block definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1838
GCM mode IV registers initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1838
CCM mode IV registers initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1845
DES/TDES data swapping example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1849
AES data swapping example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1850
Key endianness in CRYP_KxR/LR registers (AES 128/192/256-bit keys) . . . . . . . . . . . 1852
Key endianness in CRYP_KxR/LR registers (DES K1 and TDES K1/2/3) . . . . . . . . . . . 1853
Initialization vector endianness in CRYP_IVx(L/R)R registers (AES) . . . . . . . . . . . . . . . 1853
Initialization vector endianness in CRYP_IVx(L/R)R registers (DES/TDES) . . . . . . . . . 1853
Cryptographic processor configuration for
memory-to-peripheral DMA transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1854
Cryptographic processor configuration for
peripheral-to-memory DMA transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1855
CRYP interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1857
Processing latency for ECB, CBC and CTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1858
Processing time (in clock cycle) for GCM and CCM per 128-bit block . . . . . . . . . . . . . . 1858
CRYP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1874
HASH features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1878
HASH internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1879
Hash processor outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1882
Processing time (in clock cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1889
HASH interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1889
HASH register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1898
Behavior of timer outputs versus BRK/BRK2 inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1942
Break protection disarming conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1944
Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1950
TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1967
Output control bits for complementary OCx and OCxN channels with break feature . . . 1981
TIM1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1999
TIM8 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2001
Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2037
TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2055
Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2065
TIM2/TIM3/TIM4/TIM5 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 2076
TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2107
Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2115
TIM12 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2118
Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2127
TIM13/TIM14 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2130
Break protection disarming conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2160
TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2176
Output control bits for complementary OCx and OCxN channels with break feature
(TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2186
TIM15 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2194
Output control bits for complementary OCx and OCxN channels with break feature
(TIM16/17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2207
TIM16/TIM17 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2217
TIMx register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2231
STM32MP153 LPTIM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2233
LPTIM input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2235
RM0442 Rev 7
RM0442
Table 300.
Table 301.
Table 302.
Table 303.
Table 304.
Table 305.
Table 306.
Table 307.
Table 308.
Table 309.
Table 310.
Table 311.
Table 312.
Table 313.
Table 314.
Table 315.
Table 316.
Table 317.
Table 318.
Table 319.
Table 320.
Table 321.
Table 322.
Table 323.
Table 324.
Table 325.
Table 326.
Table 327.
Table 328.
Table 329.
Table 330.
Table 331.
Table 332.
Table 333.
Table 334.
Table 335.
Table 336.
Table 337.
Table 338.
Table 339.
Table 340.
Table 341.
Table 342.
Table 343.
Table 344.
Table 345.
Table 346.
Table 347.
Table 348.
Table 349.
Table 350.
Table 351.
List of tables
LPTIM internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2235
LPTIM1 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2235
LPTIM2 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2236
LPTIM3 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2236
LPTIM4 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2236
LPTIM5 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2237
LPTIM1 input 1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2237
LPTIM1 input 2 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2237
LPTIM2 input 1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2237
LPTIM2 input 2 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2238
LPTIM3 input 1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2238
Prescaler division ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2239
Encoder counting scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2246
Effect of low-power modes on the LPTIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2247
Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2248
LPTIM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2261
STGENC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2277
STGENR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2278
STM32MP153x IWDG features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2282
IWDG delays versus actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2284
IWDG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2284
Effect of low power modes on IWDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2288
IWDG interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2290
IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2297
WWDG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2299
WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2305
RTC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2310
RTC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2310
RTC interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2311
RTC pin PC13 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2311
PI8 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2314
RTC_OUT mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2315
Effect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2327
RTC pins functionality over modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2327
Non-secure interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2327
Secure interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2328
RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2355
TAMP input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2360
TAMP internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2360
TAMP interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2360
Minimum ATPER value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2364
Effect of low-power modes on TAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2365
Non-secure interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2366
Secure interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2366
TAMP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2384
I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2387
I2C input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2388
I2C internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2389
Comparison of analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2391
I²C-bus and SMBus specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . 2393
I2C configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2397
I²C-bus and SMBus specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2408
RM0442 Rev 7
93/3930
98
List of tables
Table 352.
Table 353.
Table 354.
Table 355.
Table 356.
Table 357.
Table 358.
Table 359.
Table 360.
Table 361.
Table 362.
Table 363.
Table 364.
Table 365.
Table 366.
Table 367.
Table 368.
Table 369.
Table 370.
Table 371.
Table 372.
Table 373.
Table 374.
Table 375.
Table 376.
Table 377.
Table 378.
Table 379.
Table 380.
Table 381.
Table 382.
Table 383.
Table 384.
Table 385.
Table 386.
Table 387.
Table 388.
Table 389.
Table 390.
Table 391.
Table 392.
Table 393.
Table 394.
Table 395.
Table 396.
Table 397.
Table 398.
Table 399.
Table 400.
Table 401.
Table 402.
Table 403.
94/3930
RM0442
Timing settings for fI2CCLK of 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2418
Timing settings for fI2CCLK of 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2418
Timing settings for fI2CCLK of 48 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2419
SMBus timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2421
SMBus with PEC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2423
TIMEOUTA[11:0] for maximum tTIMEOUT of 25 ms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2424
TIMEOUTB[11:0] for maximum tLOW:SEXT and tLOW:MEXT of 8 ms . . . . . . . . . . . . . . . . 2424
TIMEOUTA[11:0] for maximum tIDLE of 50 µs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2424
Effect of low-power modes to I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2434
I2C interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2434
I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2450
USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2454
USART/UART input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2457
USART internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2457
Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2469
Tolerance of the USART receiver when BRR [3:0] = 0000. . . . . . . . . . . . . . . . . . . . . . . 2472
Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . . . . . . . . . 2473
USART frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2478
Effect of low-power modes on the USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2501
USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2502
USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2539
STM32MP153A SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2542
SPI wakeup and interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2574
Bitfields usable in PCM/I2S mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2577
WS and CK level before SPI/I2S is enabled when AFCNTR = 1 . . . . . . . . . . . . . . . . . . 2585
Serial data line swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2585
CLKGEN programming examples for usual I2S frequencies . . . . . . . . . . . . . . . . . . . . . 2590
I2S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2599
SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2620
STM32MP153 SAI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2623
SAI internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2625
SAI input/output pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2625
External synchronization selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2628
MCLK_x activation conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2633
Clock generator programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2636
SAI_A configuration for TDM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2643
TDM frame configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2645
SOPD pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2649
Parity bit calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2649
Audio sampling frequency versus symbol rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2650
SAI interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2659
SAI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2690
SPDIFRX internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2694
SPDIFRX pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2694
Transition sequence for preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2700
Minimum spdifrx_ker_ck frequency versus audio sampling rate . . . . . . . . . . . . . . . . . . 2710
Conditions of spdifrx_symb_ck generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2711
Bit field property versus SPDIFRX state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2714
SPDIFRX interface register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2727
Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2734
MDIOS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2740
SDMMC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2742
RM0442 Rev 7
RM0442
Table 404.
Table 405.
Table 406.
Table 407.
Table 408.
Table 409.
Table 410.
Table 411.
Table 412.
Table 413.
Table 414.
Table 415.
Table 416.
Table 417.
Table 418.
Table 419.
Table 420.
Table 421.
Table 422.
Table 423.
Table 424.
Table 425.
Table 426.
Table 427.
Table 428.
Table 429.
Table 430.
Table 431.
Table 432.
Table 433.
Table 434.
Table 435.
Table 436.
Table 437.
Table 438.
Table 439.
Table 440.
Table 441.
Table 442.
Table 443.
Table 444.
Table 445.
Table 446.
Table 447.
Table 448.
Table 449.
Table 450.
Table 451.
Table 452.
Table 453.
Table 454.
Table 455.
List of tables
SDMMC operation modes SD and SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2745
SDMMC operation modes e•MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2745
SDMMC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2746
SDMMC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2747
SDMMC Command and data phase selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2748
Command token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2754
Short response with CRC token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2755
Short response without CRC token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2755
Long response with CRC token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2755
Specific Commands overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2756
Command path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2757
Command path error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2757
Data token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2765
Data path status flags and clear bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2765
Data path error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2767
Data FIFO access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2768
Transmit FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2769
Receive FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2770
AHB and SDMMC_CK clock frequency relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2775
SDIO special operation control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2775
4-bit mode Start, interrupt, and CRC-status Signaling detection . . . . . . . . . . . . . . . . . . 2779
CMD12 use cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2784
SDMMC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2798
Response type and SDMMC_RESPxR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2805
SDMMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2822
CAN subsystem I/O signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2825
CAN subsystem I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2826
CAN triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2826
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2828
DLC coding in FDCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2833
Example of filter configuration for Rx buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2846
Example of filter configuration for Debug messages . . . . . . . . . . . . . . . . . . . . . . . . . . . 2847
Possible configurations for frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2847
Tx buffer/FIFO - Queue element size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2848
First byte of level 1 reference message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2858
First four bytes of level 2 reference message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2859
First four bytes of level 0 reference message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2859
TUR configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2860
System matrix, Node A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2865
Trigger list, Node A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2866
Number of data bytes transmitted with a reference message. . . . . . . . . . . . . . . . . . . . . 2873
Rx buffer and FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2880
Rx buffer and FIFO element description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2880
Tx buffer and FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2882
Tx buffer element description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2882
Tx Event FIFO element. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2884
Tx Event FIFO element description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2884
Standard message ID filter element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2885
Standard message ID filter element field description . . . . . . . . . . . . . . . . . . . . . . . . . . . 2886
Extended message ID filter element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2887
Extended message ID filter element field description . . . . . . . . . . . . . . . . . . . . . . . . . . . 2887
Trigger memory element. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2888
RM0442 Rev 7
95/3930
98
List of tables
Table 456.
Table 457.
Table 458.
Table 459.
Table 460.
Table 461.
Table 462.
Table 463.
Table 464.
Table 465.
Table 466.
Table 467.
Table 468.
Table 469.
Table 470.
Table 471.
Table 472.
Table 473.
Table 474.
Table 475.
Table 476.
Table 477.
Table 478.
Table 479.
Table 480.
Table 481.
Table 482.
Table 483.
Table 484.
Table 485.
Table 486.
Table 487.
Table 488.
Table 489.
Table 490.
Table 491.
Table 492.
Table 493.
Table 494.
Table 495.
Table 496.
Table 497.
Table 498.
Table 499.
Table 500.
Table 501.
Table 502.
Table 503.
Table 504.
Table 505.
Table 506.
Table 507.
96/3930
RM0442
Trigger memory element description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2888
FDCAN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2926
FDCAN TT register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2948
CCU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2954
OTG speeds supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2956
OTG implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2959
OTG input/output pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2960
OTG input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2961
Compatibility of STM32 low power modes with the OTG . . . . . . . . . . . . . . . . . . . . . . . . 2974
Core global control and status registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2982
Host-mode control and status registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2983
Device-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2985
Data FIFO (DFIFO) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2987
Power and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 2987
TRDT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2995
Minimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3040
OTG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3064
USBPHYC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3148
USBH register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3161
Ethernet peripheral pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3171
Ethernet internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3172
Fixed priority scheme for DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3186
Weight for DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3190
Example of credit value per transmit cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3191
Double VLAN processing features in Tx path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3195
Double VLAN processing in Rx path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3195
VLAN insertion or replacement based on VLTI bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3197
Destination address filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3200
Source address filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3201
VLAN match status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3202
Ordinary clock: PTP messages for snapshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3205
End-to-end transparent clock: PTP messages for snapshot . . . . . . . . . . . . . . . . . . . . . 3206
Peer-to-peer transparent clock: PTP messages for snapshot . . . . . . . . . . . . . . . . . . . . 3206
Egress and ingress latency for PHY interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3210
Minimum PTP clock frequency example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3211
Message format defined in IEEE 1588-2008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3211
Message format defined in IEEE 1588-2008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3212
IPv6-UDP PTP packet fields required for control and status . . . . . . . . . . . . . . . . . . . . . 3213
Ethernet PTP packet fields required for control and status . . . . . . . . . . . . . . . . . . . . . . 3214
Timestamp Snapshot Dependency on ETH_MACTSCR bits . . . . . . . . . . . . . . . . . . . . . 3216
PTP message generation criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3222
Common PTP message header fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3224
MAC Transmit PTP mode and one-step timestamping operation. . . . . . . . . . . . . . . . . . 3227
Transmit checksum offload engine functions for different packet types . . . . . . . . . . . . . 3232
Receive checksum offload engine functions for different packet types . . . . . . . . . . . . . 3234
TSO: TCP and IP header fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3238
Pause packet fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3243
Tx MAC flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3244
Rx MAC flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3245
Size of the maximum receive packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3247
MCD clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3250
MDIO Clause 45 frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3251
RM0442 Rev 7
RM0442
Table 508.
Table 509.
Table 510.
Table 511.
Table 512.
Table 513.
Table 514.
Table 515.
Table 516.
Table 517.
Table 518.
Table 519.
Table 520.
Table 521.
Table 522.
Table 523.
Table 524.
Table 525.
Table 526.
Table 527.
Table 528.
Table 529.
Table 530.
Table 531.
Table 532.
Table 533.
Table 534.
Table 535.
Table 536.
Table 537.
Table 538.
Table 539.
Table 540.
Table 541.
Table 542.
Table 543.
Table 544.
Table 545.
Table 546.
Table 547.
Table 548.
Table 549.
Table 550.
Table 551.
Table 552.
Table 553.
Table 554.
Table 555.
Table 556.
Table 557.
Table 558.
Table 559.
List of tables
MDIO Clause 22 frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3252
Remote wake-up packet filter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3267
Description of the remote wake-up filter fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3268
Remote wake-up packet and PMT interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . 3269
Transfer complete interrupt behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3278
TDES0 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3304
TDES1 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3305
TDES2 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3305
TDES3 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3306
TDES0 normal descriptor (write-back format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3309
TDES1 normal descriptor (write-back format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3309
TDES2 normal descriptor (write-back format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3310
TDES3 normal descriptor (write-back format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3310
TDES0 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3313
TDES1 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3314
TDES2 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3314
TDES3 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3314
RDES0 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3318
RDES1 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3318
RDES2 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3318
RDES3 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3319
RDES0 normal descriptor (write-back format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3320
RDES1 normal descriptor (write-back format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3321
RDES2 normal descriptor (write-back format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3323
RDES3 normal descriptor (write-back format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3324
RDES0 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3327
RDES1 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3328
RDES2 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3328
RDES3 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3328
ETH_DMA common register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3355
ETH_DMA_CH0 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3356
ETH_DMA_CH1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3357
ETH_MTL register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3374
Giant Packet Status based on S2KP and JE Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3382
Packet Length based on the CST and ACS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3382
Ethernet MAC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3471
HDMI pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3484
HDMI-CEC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3484
Error handling timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3490
TXERR timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3491
HDMI-CEC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3492
HDMI-CEC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3500
HDP signal multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3503
HDP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3509
JTAG/Serial-wire debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3514
Trace port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3514
Serial Wire Trace port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3514
Trigger pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3514
Authentication signal connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3517
Authentication signal initial states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3518
CLTAPC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3518
JTAG-DP data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3521
RM0442 Rev 7
97/3930
98
List of tables
Table 560.
Table 561.
Table 562.
Table 563.
Table 564.
Table 565.
Table 566.
Table 567.
Table 568.
Table 569.
Table 570.
Table 571.
Table 572.
Table 573.
Table 574.
Table 575.
Table 576.
Table 577.
Table 578.
Table 579.
Table 580.
Table 581.
Table 582.
Table 583.
Table 584.
Table 585.
Table 586.
Table 587.
Table 588.
Table 589.
Table 590.
Table 591.
Table 592.
Table 593.
Table 594.
Table 595.
Table 596.
Table 597.
Table 598.
Table 599.
98/3930
RM0442
Packet request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3523
ACK response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3523
Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3523
Debug port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3525
AP0 (system interconnect) authentication behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3534
AP1 (Debug APB) authentication behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3535
AP2 (Cortex®-M4) authentication behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3535
MEM-AP registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3535
Debug subsystem ROM table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3546
Trace subsystem ROM table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3547
ROM table register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3553
TSGEN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3561
Trace Subsystem CTI inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3564
Trace Subsystem CTI outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3564
Cortex®-A7_1/2 CTI inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3565
Cortex®-A7_1/2 CTI outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3565
Cortex®-M4 CTI inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3565
Cortex®-M4 CTI outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3566
CTI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3580
CSTF register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3594
ETF register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3614
TPIU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3632
SWO registers map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3644
STM extended stimulus port memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3647
STM trace packet ID mapping to AXI masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3648
Hardware event mapping 0 to 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3649
Hardware event mapping 4 to 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3651
STM registers map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3679
IWDG1 behavior in debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3686
DBGMCU registers map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3695
Debug unit register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3734
Performance monitoring unit registers map and reset values. . . . . . . . . . . . . . . . . . . . . 3757
ETM registers map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3805
Cortex®-M4 CPU ROM table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3812
Cortex®-M4 CPU ROM table register map and reset values . . . . . . . . . . . . . . . . . . . . . 3817
DWT register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3829
ITM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3839
FPB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3848
Embedded trace macrocell register map and reset values. . . . . . . . . . . . . . . . . . . . . . . 3869
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3878
RM0442 Rev 7
RM0442
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Bus interconnect for STM32MP153 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
NIC-400 interconnect AXIM for STM32MP153 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Multi-layer AHB interconnect for STM32MP153 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
BSEC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Power-on and initial read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
DDRCTRL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
TZC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
TZC example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
TZC example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
TZC example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
DDRPHYC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
DDRPHY block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
MDLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
MSDLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
ITMs block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
ITMC_D2 for LPDDR2/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
ITMC_D2 for DDR3/3L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
ITMS and ITMD for DQ/DQS lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
PUBL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
DDRPHY initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Buit-in DQS gate training flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Software DQS gate training flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Write timing with WL = 5, BL = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Read timing with WL = 5, BL = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
DDRPERFM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Power control block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Device startup supply sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Device low-power Stop supply sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Device low-power LP-Stop supply sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
Device low-power LPLV-Stop supply sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
Device Standby mode power control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
Device VBAT mode power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
Power-on reset/power-down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
NRST_CORE control in Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
AVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
VBAT thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
Temperature thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
Power states and external regulator control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
Power control modes detailed state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
PWR_ON and PWR_LP pins multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
RCC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
Reset circuit overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
Reset pulse control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
RM0442 Rev 7
99/3930
114
List of figures
RM0442
Figure 49. Reset delay control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Figure 50. Reset source registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Figure 51. Boot sequences versus system states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
Figure 52. HOLD_BOOT examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
Figure 53. Hold function handled by the BOOTROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
Figure 54. Top-level clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
Figure 55. HSE clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
Figure 56. HSE clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
Figure 57. HSI calibration flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
Figure 58. CSI calibration flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
Figure 59. LSE clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Figure 60. LSE and HSE CSS function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
Figure 61. PLL1 and PLL2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Figure 62. PLL3 and PLL4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Figure 63. Spread spectrum modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Figure 64. Triangular waveform generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
Figure 65. Dynamic clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
Figure 66. Core and busses clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
Figure 67. Key signals controlling low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
Figure 68. Clock restore activation versus system mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
Figure 69. Clock restore process activated after system Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Figure 70. Wake up from CStop processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
Figure 71. Peripheral clock distribution For SAIs and DFSDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
Figure 72. Peripheral clock distribution for SPI/I2Ss and SPDIFRX . . . . . . . . . . . . . . . . . . . . . . . . . 561
Figure 73. Peripheral clock distribution for SPIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
Figure 74. Peripheral clock distribution for I2Cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
Figure 75. Peripheral clock distribution for UARTs, and USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
Figure 76. Peripheral clock distribution for UARTs, and USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
Figure 77. Peripheral clock distribution for TIMs and LPTIMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
Figure 78. Peripheral clock distribution for LTDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Figure 79. Peripheral clock distribution for QUADSPI and FMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Figure 80. Peripheral clock distribution for SDMMCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
Figure 81. Peripheral clock distribution for USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
Figure 82. Peripheral clock distribution for Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
Figure 83. Kernel clock distribution for RNG1 and RNG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
Figure 84. Kernel clock distribution for FDCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
Figure 85. Kernel clock distribution for ADC12, DACs, STGEN and HDMI-CEC . . . . . . . . . . . . . . . 575
Figure 86. Kernel clock distribution for DTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
Figure 87. Clock distribution for RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
Figure 88. Clock distribution for IWDG[2:1] and WWDG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
Figure 89. Clock distribution for TZC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
Figure 90. Clock distribution for DDRC, DDRPHYC and DDRPERFM . . . . . . . . . . . . . . . . . . . . . . . 581
Figure 91. Entering and exiting self-refresh in ASR1 or ASR2 modes . . . . . . . . . . . . . . . . . . . . . . . 587
Figure 92. Entering and exiting self-refresh in HSR1 or HSR2 modes . . . . . . . . . . . . . . . . . . . . . . . 588
Figure 93. Allowed transitions between SSR, ASR and HSR modes . . . . . . . . . . . . . . . . . . . . . . . . 589
Figure 94. Clock description for DBG and trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
Figure 95. Clock description for IO compensation cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
Figure 96. Peripheral allocation example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
Figure 97. Peripheral kernel clock enable logic details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
Figure 98. MPU low-power interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
Figure 99. Interrupt block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
Figure 100. MPU clock path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
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Figure 101. PLL2 clock path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
Figure 102. MCU clock path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
Figure 103. Exit from Stop due to MPU event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
Figure 104. Exit from Stop due to MCU event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
Figure 105. Exit from Stop for MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
Figure 106. Fast clock restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
Figure 107. HSEM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
Figure 108. Procedure state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
Figure 109. Interrupt state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
Figure 110. IPCC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044
Figure 111. IPCC Simplex channel mode transfer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045
Figure 112. IPCC Simplex - Send procedure state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
Figure 113. IPCC Simplex - Receive procedure state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047
Figure 114. IPCC Half-duplex channel mode transfer timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
Figure 115. IPCC Half-duplex - Send procedure state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
Figure 116. IPCC Half-duplex - Receive procedure state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
Figure 117. Basic structure of an I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
Figure 118. Basic structure of a 5-Volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
Figure 119. Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
Figure 120. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
Figure 121. Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066
Figure 122. High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066
Figure 123. Analog inputs connected to ADC inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
Figure 124. I/O compensation control overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
Figure 125. Ethernet clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
Figure 126. STM32MP153 security architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110
Figure 127. MDMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154
Figure 128. DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
Figure 129. Peripheral-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182
Figure 130. Memory-to-peripheral mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183
Figure 131. Memory-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184
Figure 132. FIFO structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1189
Figure 133. DMAMUX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218
Figure 134. Synchronization mode of the DMAMUX request line multiplexer channel . . . . . . . . . . . 1221
Figure 135. Event generation of the DMA request line multiplexer channel . . . . . . . . . . . . . . . . . . . 1221
Figure 136. GIC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251
Figure 137. EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1302
Figure 138. Configurable event trigger logic CPU wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305
Figure 139. Direct event trigger logic CPU wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1306
Figure 140. EXTI mux GPIO selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1307
Figure 141. CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1345
Figure 142. FMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355
Figure 143. Mode 1 read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1366
Figure 144. Mode 1 write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1366
Figure 145. Mode A read access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368
Figure 146. Mode A write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1369
Figure 147. Mode 2 and mode B read access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371
Figure 148. Mode 2 write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1372
Figure 149. Mode B write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1372
Figure 150. Mode C read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375
Figure 151. Mode C write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375
Figure 152. Mode D read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377
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Figure 153. Mode D write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1378
Figure 154. Muxed read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1380
Figure 155. Muxed write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1381
Figure 156. Asynchronous wait during a read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384
Figure 157. Asynchronous wait during a write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . 1384
Figure 158. Wait configuration waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386
Figure 159. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . . . . . . . 1387
Figure 160. Synchronous multiplexed write mode waveforms - PSRAM (CRAM). . . . . . . . . . . . . . . 1389
Figure 161. NAND flash controller waveforms for common memory access. . . . . . . . . . . . . . . . . . . 1406
Figure 162. NAND flash controller waveforms for TCLR and TAR timings . . . . . . . . . . . . . . . . . . . . 1406
Figure 163. Access to NAND flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1408
Figure 164. NAND flash page (2 Kbytes) layout with BCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412
Figure 165. Example of 2 Kbyte page program sequence with 4-bit BCH. . . . . . . . . . . . . . . . . . . . . 1413
Figure 166. Chained-page read command timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1415
Figure 167. Example of 2-Kbyte page read sequence with 4-bit BCH. . . . . . . . . . . . . . . . . . . . . . . . 1416
Figure 168. QUADSPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447
Figure 169. QUADSPI block diagram when dual-flash mode is enabled. . . . . . . . . . . . . . . . . . . . . . 1448
Figure 170. Example of read command in quad-SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1449
Figure 171. Example of a DDR command in quad-SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1452
Figure 172. NCS when CKMODE = 0 (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1460
Figure 173. NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . 1461
Figure 174. NCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . 1461
Figure 175. NCS when CKMODE = 1 with an abort (T = CLK period). . . . . . . . . . . . . . . . . . . . . . . . 1462
Figure 176. DLYB block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478
Figure 177. ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1486
Figure 178. ADC clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
Figure 179. ADC1 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490
Figure 180. ADC2 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1491
Figure 181. ADC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495
Figure 182. Updating the ADC offset calibration factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495
Figure 183. Mixing single-ended and differential channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1496
Figure 184. Enabling / Disabling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500
Figure 185. Analog-to-digital conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505
Figure 186. Stopping ongoing regular conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1506
Figure 187. Stopping ongoing regular and injected conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1506
Figure 188. Triggers are shared between ADC master and ADC slave . . . . . . . . . . . . . . . . . . . . . . 1508
Figure 189. Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1511
Figure 190. Example of ADC_JSQR queue of context (sequence change) . . . . . . . . . . . . . . . . . . . 1514
Figure 191. Example of ADC_JSQR queue of context (trigger change) . . . . . . . . . . . . . . . . . . . . . . 1515
Figure 192. Example of ADC_JSQR queue of context with overflow before conversion. . . . . . . . . . 1515
Figure 193. Example of ADC_JSQR queue of context with overflow during conversion . . . . . . . . . 1516
Figure 194. Example of ADC_JSQR queue of context with empty queue (case JQM=0) . . . . . . . . . 1516
Figure 195. Example of ADC_JSQR queue of context with empty queue (case JQM=1) . . . . . . . . . 1517
Figure 196. Flushing ADC_JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion. . . . . . . . . . . . . . . . . . . . . . 1517
Figure 197. Flushing ADC_JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion and a new
trigger occurs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1518
Figure 198. Flushing ADC_JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs outside an ongoing conversion . . . . . . . . . . . . . . . . . . . . . 1518
Figure 199. Flushing ADC_JSQR queue of context by setting JADSTP=1 (JQM=1) . . . . . . . . . . . . 1519
Figure 200. Flushing ADC_JSQR queue of context by setting ADDIS=1 (JQM=0) . . . . . . . . . . . . . . 1519
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Figure 201. Flushing ADC_JSQR queue of context by setting ADDIS=1 (JQM=1) . . . . . . . . . . . . . . 1520
Figure 202. Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522
Figure 203. Continuous conversion of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . 1522
Figure 204. Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . 1523
Figure 205. Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . 1523
Figure 206. Right alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1525
Figure 207. Right alignment (offset enabled, signed value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1525
Figure 208. Left alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1526
Figure 209. Left alignment (offset enabled, signed value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1526
Figure 210. Example of overrun (OVRMOD = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1529
Figure 211. Example of overrun (OVRMOD = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1529
Figure 212. AUTDLY=1, regular conversion in continuous mode, software trigger . . . . . . . . . . . . . . 1533
Figure 213. AUTDLY=1, regular HW conversions interrupted by injected conversions
(DISCEN=0; JDISCEN=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1533
Figure 214. AUTDLY=1, regular HW conversions interrupted by injected conversions. . . . . . . . . . . . . . .
(DISCEN=1, JDISCEN=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1534
Figure 215. AUTDLY=1, regular continuous conversions interrupted by injected conversions . . . . . 1535
Figure 216. AUTDLY=1 in auto- injected mode (JAUTO=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1535
Figure 217. Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1536
Figure 218. ADCy_AWDx_OUT signal generation (on all regular channels). . . . . . . . . . . . . . . . . . . 1538
Figure 219. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by SW) . . . . . . . . . . . . . 1538
Figure 220. ADCy_AWDx_OUT signal generation (on a single regular channel) . . . . . . . . . . . . . . . 1539
Figure 221. ADCy_AWDx_OUT signal generation (on all injected channels) . . . . . . . . . . . . . . . . . . 1539
Figure 222. 16-bit result oversampling with 10-bits right shift and rouding . . . . . . . . . . . . . . . . . . . . 1540
Figure 223. Triggered regular oversampling mode (TROVS bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . 1542
Figure 224. Regular oversampling modes (4x ratio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1543
Figure 225. Regular and injected oversampling modes used simultaneously . . . . . . . . . . . . . . . . . . 1543
Figure 226. Triggered regular oversampling with injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1544
Figure 227. Oversampling in auto-injected mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1544
Figure 228. Dual ADC block diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547
Figure 229. Injected simultaneous mode on 4 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . 1548
Figure 230. Regular simultaneous mode on 16 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . 1550
Figure 231. Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode . . . . 1551
Figure 232. Interleaved mode on 1 channel in single conversion mode: dual ADC mode . . . . . . . . 1552
Figure 233. Interleaved conversion with injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1552
Figure 234. Alternate trigger: injected group of each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1553
Figure 235. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . . . . . . . . 1554
Figure 236. Alternate + regular simultaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1555
Figure 237. Case of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 1555
Figure 238. Interleaved single channel CH0 with injected sequence CH11, CH12 . . . . . . . . . . . . . . 1556
Figure 239. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1556
Figure 240. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1556
Figure 241. DMA Requests in regular simultaneous mode when DAMDF=0b00 . . . . . . . . . . . . . . . 1557
Figure 242. DMA requests in regular simultaneous mode when DAMDF=0b10 . . . . . . . . . . . . . . . . 1558
Figure 243. DMA requests in interleaved mode when DAMDF=0b10 . . . . . . . . . . . . . . . . . . . . . . . . 1558
Figure 244. Temperature sensor channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1560
Figure 245. VBAT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1562
Figure 246. VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1562
Figure 247. VDDCORE channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564
Figure 248. Temperature sensor functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613
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Figure 249. Method for low REF_CLK frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1615
Figure 250. Method for high REF_CLK frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1615
Figure 251. Temperature sensor sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1618
Figure 252. Dual-channel DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631
Figure 253. Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634
Figure 254. Data registers in dual DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634
Figure 255. Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . 1635
Figure 256. DAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1637
Figure 257. DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . 1637
Figure 258. DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1638
Figure 259. DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . 1638
Figure 260. DAC sample and hold mode phase diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1641
Figure 261. Single DFSDM block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1675
Figure 262. Input channel pins redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1679
Figure 263. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1682
Figure 264. Clock absence timing diagram for SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1683
Figure 265. Clock absence timing diagram for Manchester coding . . . . . . . . . . . . . . . . . . . . . . . . . . 1684
Figure 266. First conversion for Manchester coding (Manchester synchronization) . . . . . . . . . . . . . 1686
Figure 267. DFSDM_CHyDATINR registers operation modes and assignment . . . . . . . . . . . . . . . . 1690
Figure 268. Example: Sinc3 filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1692
Figure 269. DCMI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1739
Figure 270. DCMI signal waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1740
Figure 271. Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1742
Figure 272. Frame capture waveforms in snapshot mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1744
Figure 273. Frame capture waveforms in continuous grab mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 1745
Figure 274. Coordinates and size of the window after cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1745
Figure 275. Data capture waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1746
Figure 276. Pixel raster scan order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1747
Figure 277. LTDC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1761
Figure 278. LTDC synchronous timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1764
Figure 279. Layer window programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1767
Figure 280. Blending two layers with background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1769
Figure 281. Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1771
Figure 282. RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1795
Figure 283. Entropy source model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1796
Figure 284. RNG initialization overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1798
Figure 285. CRYP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1810
Figure 286. AES-ECB mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1813
Figure 287. AES-CBC mode overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1814
Figure 288. AES-CTR mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1815
Figure 289. AES-GCM mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1816
Figure 290. AES-GMAC mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1816
Figure 291. AES-CCM mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1817
Figure 292. Example of suspend mode management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1822
Figure 293. DES/TDES-ECB mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1823
Figure 294. DES/TDES-ECB mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1824
Figure 295. DES/TDES-CBC mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1825
Figure 296. DES/TDES-CBC mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1826
Figure 297. AES-ECB mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1828
Figure 298. AES-ECB mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1829
Figure 299. AES-CBC mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1830
Figure 300. AES-CBC mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1831
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Figure 301. Message construction for the Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1833
Figure 302. AES-CTR mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1834
Figure 303. AES-CTR mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1835
Figure 304. Message construction for the Galois/counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1837
Figure 305. Message construction for the Galois Message Authentication Code mode . . . . . . . . . . 1842
Figure 306. Message construction for the Counter with CBC-MAC mode. . . . . . . . . . . . . . . . . . . . . 1843
Figure 307. 64-bit block construction according to the data type (IN FIFO). . . . . . . . . . . . . . . . . . . . 1850
Figure 308. 128-bit block construction according to the data type. . . . . . . . . . . . . . . . . . . . . . . . . . . 1852
Figure 309. HASH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1878
Figure 310. Message data swapping feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1880
Figure 311. HASH suspend/resume mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1886
Figure 312. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1902
Figure 313. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1904
Figure 314. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1904
Figure 315. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1906
Figure 316. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1906
Figure 317. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1907
Figure 318. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1907
Figure 319. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . 1908
Figure 320. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . 1908
Figure 321. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1910
Figure 322. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1910
Figure 323. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1911
Figure 324. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1911
Figure 325. Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . 1912
Figure 326. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . 1913
Figure 327. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1914
Figure 328. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . 1914
Figure 329. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1915
Figure 330. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . 1915
Figure 331. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . 1916
Figure 332. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . 1917
Figure 333. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1918
Figure 334. TIM1/TIM8 ETR input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1918
Figure 335. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1919
Figure 336. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1920
Figure 337. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1921
Figure 338. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1921
Figure 339. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1922
Figure 340. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 1923
Figure 341. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1923
Figure 342. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . . . . . . . . 1924
Figure 343. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . 1924
Figure 344. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . . . . . . . . . . . . . 1925
Figure 345. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1927
Figure 346. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1929
Figure 347. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1930
Figure 348. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1931
Figure 349. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . 1933
Figure 350. Combined PWM mode on channel 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1934
Figure 351. 3-phase combined PWM signals with multiple trigger pulses per period . . . . . . . . . . . . 1935
Figure 352. Complementary output with dead-time insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1936
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Figure 353. Dead-time waveforms with delay greater than the negative pulse . . . . . . . . . . . . . . . . . 1936
Figure 354. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . 1937
Figure 355. Break and Break2 circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1939
Figure 356. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . . . . . . . 1941
Figure 357. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . . . . . . . . . . . 1942
Figure 358. PWM output state following BRK assertion (OSSI=0) . . . . . . . . . . . . . . . . . . . . . . . . . . 1943
Figure 359. Output redirection (BRK2 request not represented) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1944
Figure 360. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1945
Figure 361. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1946
Figure 362. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1947
Figure 363. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1949
Figure 364. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . 1950
Figure 365. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . 1951
Figure 366. Measuring time interval between edges on 3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1952
Figure 367. Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1954
Figure 368. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1955
Figure 369. Control circuit in Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1956
Figure 370. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1957
Figure 371. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . 1958
Figure 372. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2005
Figure 373. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 2007
Figure 374. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 2007
Figure 375. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2008
Figure 376. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2009
Figure 377. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2009
Figure 378. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2010
Figure 379. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . 2010
Figure 380. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . 2011
Figure 381. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2012
Figure 382. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2012
Figure 383. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2013
Figure 384. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2013
Figure 385. Counter timing diagram, Update event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2014
Figure 386. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . 2015
Figure 387. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2016
Figure 388. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . 2016
Figure 389. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2017
Figure 390. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . 2017
Figure 391. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . 2018
Figure 392. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 2019
Figure 393. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2019
Figure 394. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2020
Figure 395. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2021
Figure 396. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2022
Figure 397. Capture/Compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . 2022
Figure 398. Capture/Compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2023
Figure 399. Output stage of Capture/Compare channel (channel 1) . . . . . . . . . . . . . . . . . . . . . . . . . 2023
Figure 400. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2025
Figure 401. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2027
Figure 402. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2028
Figure 403. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2029
Figure 404. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . 2030
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Figure 405. Combined PWM mode on channels 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2032
Figure 406. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2033
Figure 407. Example of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2034
Figure 408. Retriggerable one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2036
Figure 409. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . 2037
Figure 410. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . 2038
Figure 411. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2039
Figure 412. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2040
Figure 413. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2041
Figure 414. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . 2042
Figure 415. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2043
Figure 416. Master/slave connection example with 1 channel only timers . . . . . . . . . . . . . . . . . . . . 2043
Figure 417. Gating TIM2 with OC1REF of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2044
Figure 418. Gating TIM2 with Enable of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2045
Figure 419. Triggering TIM2 with update of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2046
Figure 420. Triggering TIM2 with Enable of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2046
Figure 421. Triggering TIM3 and TIM2 with TIM3 TI1 input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2047
Figure 422. General-purpose timer block diagram (TIM12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2080
Figure 423. General-purpose timer block diagram (TIM13/TIM14) . . . . . . . . . . . . . . . . . . . . . . . . . . 2081
Figure 424. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 2083
Figure 425. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 2083
Figure 426. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2084
Figure 427. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2085
Figure 428. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2085
Figure 429. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2086
Figure 430. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2086
Figure 431. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2087
Figure 432. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 2088
Figure 433. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2088
Figure 434. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2089
Figure 435. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 2090
Figure 436. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2090
Figure 437. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . 2091
Figure 438. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2093
Figure 439. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2095
Figure 440. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2096
Figure 441. Combined PWM mode on channel 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2097
Figure 442. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2098
Figure 443. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2099
Figure 444. Measuring time interval between edges on 2 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 2100
Figure 445. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2101
Figure 446. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2102
Figure 447. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2102
Figure 448. TIM15 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2134
Figure 449. TIM16/TIM17 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2135
Figure 450. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 2137
Figure 451. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 2137
Figure 452. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2139
Figure 453. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2139
Figure 454. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2140
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Figure 455. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2140
Figure 456. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2141
Figure 457. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2141
Figure 458. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . 2143
Figure 459. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 2144
Figure 460. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2144
Figure 461. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2145
Figure 462. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 2146
Figure 463. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2146
Figure 464. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . 2147
Figure 465. Output stage of capture/compare channel (channel 2 for TIM15) . . . . . . . . . . . . . . . . . 2147
Figure 466. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2149
Figure 467. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2151
Figure 468. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2152
Figure 469. Combined PWM mode on channel 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2153
Figure 470. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2154
Figure 471. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . 2154
Figure 472. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . 2155
Figure 473. Break circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2157
Figure 474. Output behavior in response to a break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2159
Figure 475. Output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2161
Figure 476. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2162
Figure 477. Example of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2163
Figure 478. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2165
Figure 479. Measuring time interval between edges on 2 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 2166
Figure 480. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2167
Figure 481. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2168
Figure 482. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2169
Figure 483. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2219
Figure 484. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 2221
Figure 485. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 2221
Figure 486. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2222
Figure 487. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2223
Figure 488. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2223
Figure 489. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2224
Figure 490. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2224
Figure 491. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2225
Figure 492. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 2226
Figure 493. Low-power timer block diagram (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . . 2233
Figure 494. Low-power timer block diagram (LPTIM3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2234
Figure 495. Low-power timer block diagram (LPTIM4 and LPTIM5) . . . . . . . . . . . . . . . . . . . . . . . . . 2234
Figure 496. Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2239
Figure 497. LPTIM output waveform, single counting mode configuration . . . . . . . . . . . . . . . . . . . . 2241
Figure 498. LPTIM output waveform, Single counting mode configuration
and Set-once mode activated (WAVE bit is set) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2241
Figure 499. LPTIM output waveform, Continuous counting mode configuration . . . . . . . . . . . . . . . . 2242
Figure 500. Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2243
Figure 501. Encoder mode counting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2247
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Figure 502. STGEN block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2264
Figure 503. Watchdogs top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2281
Figure 504. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2283
Figure 505. Reset timing due to timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2285
Figure 506. Reset timing due to refresh in the not allowed area . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2286
Figure 507. Changing PR, RL, and performing a refresh(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2287
Figure 508. Independent watchdog interrupt timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2289
Figure 509. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2299
Figure 510. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2300
Figure 511. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2309
Figure 512. TAMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2359
Figure 513. Backup registers secure protections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2361
Figure 514. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2388
Figure 515. I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2390
Figure 516. Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2392
Figure 517. I2C initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2394
Figure 518. Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2395
Figure 519. Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2396
Figure 520. Target initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2399
Figure 521. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . . . . . . . . . . . 2401
Figure 522. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . . . . . . . . . . . 2402
Figure 523. Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . . . . . . . 2403
Figure 524. Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . . . . . . . . . . . . . 2404
Figure 525. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . . . . . . . . . . . . . 2405
Figure 526. Transfer bus diagrams for I2C target receiver
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2405
Figure 527. Controller clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2407
Figure 528. Controller initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2409
Figure 529. 10-bit address read access with HEAD10R = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2409
Figure 530. 10-bit address read access with HEAD10R = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2410
Figure 531. Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes. . . . . . . . . . . . . . . 2411
Figure 532. Transfer sequence flow for I2C controller transmitter, N > 255 bytes. . . . . . . . . . . . . . . 2412
Figure 533. Transfer bus diagrams for I2C controller transmitter
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2413
Figure 534. Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes . . . . . . . . . . . . . . . . 2415
Figure 535. Transfer sequence flow for I2C controller receiver, N > 255 bytes. . . . . . . . . . . . . . . . . 2416
Figure 536. Transfer bus diagrams for I2C controller receiver
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2417
Figure 537. Timeout intervals for tLOW:SEXT, tLOW:MEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2421
Figure 538. Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . . . . . . . . . . . 2425
Figure 539. Transfer bus diagram for SMBus target transmitter (SBC = 1). . . . . . . . . . . . . . . . . . . . 2425
Figure 540. Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . . . . . . . . . . . . . 2427
Figure 541. Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . . . . . . . . . . . . . . . . . . 2428
Figure 542. Bus transfer diagrams for SMBus controller transmitter . . . . . . . . . . . . . . . . . . . . . . . . . 2429
Figure 543. Bus transfer diagrams for SMBus controller receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 2431
Figure 544. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2455
Figure 545. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2458
Figure 546. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2460
Figure 547. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2463
Figure 548. Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2464
Figure 549. usart_ker_ck clock divider block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2467
Figure 550. Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2468
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Figure 551. Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2469
Figure 552. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2476
Figure 553. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2477
Figure 554. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . 2480
Figure 555. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . 2481
Figure 556. USART example of synchronous master transmission. . . . . . . . . . . . . . . . . . . . . . . . . . 2482
Figure 557. USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2482
Figure 558. USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2483
Figure 559. USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2484
Figure 560. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2486
Figure 561. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2488
Figure 562. IrDA SIR ENDEC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2492
Figure 563. IrDA data modulation (3/16) - normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2492
Figure 564. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2494
Figure 565. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2495
Figure 566. Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2495
Figure 567. RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2496
Figure 568. RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2497
Figure 569. Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . . . . . . . 2500
Figure 570. Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2500
Figure 571. SPI2S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2543
Figure 572. Full-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2545
Figure 573. Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2546
Figure 574. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2547
Figure 575. Master and three independent slaves at star topology . . . . . . . . . . . . . . . . . . . . . . . . . . 2548
Figure 576. Master and three slaves at circular (daisy chain) topology . . . . . . . . . . . . . . . . . . . . . . . 2549
Figure 577. Multimaster application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2550
Figure 578. Scheme of SS control logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2552
Figure 579. Data flow timing control (SSOE=1, SSOM=0, SSM=0) . . . . . . . . . . . . . . . . . . . . . . . . . 2552
Figure 580. SS interleaving pulses between data (SSOE=1, SSOM=1,SSM=0). . . . . . . . . . . . . . . . 2553
Figure 581. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2555
Figure 582. Data alignment when data size is not equal to 8-bit, 16-bit or 32-bit . . . . . . . . . . . . . . . 2556
Figure 583. Packing data in FIFO for transmission and reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 2564
Figure 584. TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2566
Figure 585. Optional configurations of slave behavior at detection of underrun condition . . . . . . . . 2568
Figure 586. Low-power mode application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2572
Figure 587. Waveform examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2579
Figure 588. Master I2S Philips protocol waveforms (16/32-bit full accuracy) . . . . . . . . . . . . . . . . . . 2580
Figure 589. I2S Philips standard waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2580
Figure 590. Master MSB Justified 16-bit or 32-bit full-accuracy length . . . . . . . . . . . . . . . . . . . . . . . 2581
Figure 591. Master MSB justified 16 or 24-bit data length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2581
Figure 592. Slave MSB justified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2582
Figure 593. LSB justified 16 or 24-bit data length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2582
Figure 594. Master PCM when the frame length is equal the data length . . . . . . . . . . . . . . . . . . . . . 2583
Figure 595. Master PCM standard waveforms (16 or 24-bit data length) . . . . . . . . . . . . . . . . . . . . . 2583
Figure 596. Slave PCM waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2584
Figure 597. Startup sequence, I2S Philips standard, master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2587
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Figure 598. Startup sequence, I2S Philips standard, slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2587
Figure 599. Stop sequence, I2S Philips standard, master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2588
Figure 600. I2S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2589
Figure 601. Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2591
Figure 602. Handling of underrun situation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2593
Figure 603. Handling of overrun situation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2594
Figure 604. Frame error detection, with FIXCH=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2595
Figure 605. Frame error detection, with FIXCH=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2595
Figure 606. SAI functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2624
Figure 607. Audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2628
Figure 608. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . . . . . . . 2630
Figure 609. FS role is start of frame (FSDEF = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2631
Figure 610. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . . . . . . . . . . . . . . . . . . . . . 2632
Figure 611. First bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2632
Figure 612. Audio block clock generator overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2634
Figure 613. PDM typical connection and timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2638
Figure 614. Detailed PDM interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2639
Figure 615. Start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2640
Figure 616. SAI_ADR format in TDM mode, 32-bit slot width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2641
Figure 617. SAI_ADR format in TDM mode, 16-bit slot width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2642
Figure 618. SAI_ADR format in TDM mode, 8-bit slot width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2643
Figure 619. AC’97 audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2646
Figure 620. Example of typical AC’97 configuration on devices featuring at least
two embedded SAIs (three external AC’97 decoders) . . . . . . . . . . . . . . . . . . . . . . . . . . 2647
Figure 621. SPDIF format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2648
Figure 622. SAI_xDR register ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2649
Figure 623. Data companding hardware in an audio block in the SAI . . . . . . . . . . . . . . . . . . . . . . . . 2652
Figure 624. Tristate strategy on SD output line on an inactive slot . . . . . . . . . . . . . . . . . . . . . . . . . . 2654
Figure 625. Tristate on output data line in a protocol like I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2655
Figure 626. Overrun detection error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2656
Figure 627. FIFO underrun event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2656
Figure 628. SPDIFRX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2694
Figure 629. S/PDIF sub-frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2695
Figure 630. S/PDIF block format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2696
Figure 631. S/PDIF Preambles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2696
Figure 632. Channel coding example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2697
Figure 633. SPDIFRX decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2698
Figure 634. Noise filtering and edge detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2698
Figure 635. Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2700
Figure 636. Synchronization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2702
Figure 637. Synchronization process scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2703
Figure 638. SPDIFRX States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2704
Figure 639. SPDIFRX_FMTx_DR register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2706
Figure 640. Channel/user data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2707
Figure 641. S/PDIF overrun error when RXSTEO = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2709
Figure 642. S/PDIF overrun error when RXSTEO = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2710
Figure 643. SPDIFRX interface interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2713
Figure 644. MDIOS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2730
Figure 645. MDIO protocol write frame waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2731
Figure 646. MDIO protocol read frame waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2731
Figure 647. SDMMC “no response” and “no data” operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2743
Figure 648. SDMMC (multiple) block read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2743
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Figure 649. SDMMC (multiple) block write operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2744
Figure 650. SDMMC (sequential) stream read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2744
Figure 651. SDMMC (sequential) stream write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2744
Figure 652. SDMMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2746
Figure 653. SDMMC Command and data phase relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2748
Figure 654. Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2750
Figure 655. Command/response path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2751
Figure 656. Command path state machine (CPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2752
Figure 657. Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2758
Figure 658. DDR mode data packet clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2759
Figure 659. DDR mode CRC status / boot acknowledgment clocking. . . . . . . . . . . . . . . . . . . . . . . . 2759
Figure 660. Data path state machine (DPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2760
Figure 661. CLKMUX unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2771
Figure 662. Linked list structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2773
Figure 663. Asynchronous interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2776
Figure 664. Synchronous interrupt period data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2777
Figure 665. Synchronous interrupt period data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2777
Figure 666. Asynchronous interrupt period data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2778
Figure 667. Asynchronous interrupt period data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2779
Figure 668. Clock stop with SDMMC_CK for DS, HS, SDR12, SDR25. . . . . . . . . . . . . . . . . . . . . . . 2782
Figure 669. Clock stop with SDMMC_CK for DDR50, SDR50, SDR104 . . . . . . . . . . . . . . . . . . . . . . 2782
Figure 670. Read Wait with SDMMC_CK < 50 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2783
Figure 671. Read Wait with SDMMC_CK > 50 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2783
Figure 672. CMD12 stream timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2786
Figure 673. CMD5 Sleep Awake procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2788
Figure 674. Normal boot mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2790
Figure 675. Alternative boot mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2791
Figure 676. Command response R1b busy signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2792
Figure 677. SDMMC state control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2793
Figure 678. Card cycle power / power up diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2794
Figure 679. CMD11 signal voltage switch sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2795
Figure 680. Voltage switch transceiver typical application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2797
Figure 681. CAN subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2827
Figure 682. FDCAN block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2829
Figure 683. Transceiver delay measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2834
Figure 684. Pin control in bus monitoring mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2836
Figure 685. Pin control in loop back mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2838
Figure 686. CAN error state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2839
Figure 687. Message RAM configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2840
Figure 688. Standard message ID filter path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2843
Figure 689. Extended message ID filter path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2844
Figure 690. Example of mixed configuration dedicated Tx buffers / Tx FIFO . . . . . . . . . . . . . . . . . . 2850
Figure 691. Example of mixed configuration dedicated Tx buffers / Tx queue . . . . . . . . . . . . . . . . . 2850
Figure 692. Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2852
Figure 693. Bypass operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2854
Figure 694. FSM calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2855
Figure 695. Cycle time and global time synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2870
Figure 696. TTCAN level 0 and level 2 drift compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2871
Figure 697. Level 0 schedule synchronization state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2878
Figure 698. Level 0 master to slave relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2879
Figure 699. OTG high-speed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2960
Figure 700. OTG A-B device connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2963
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Figure 701. OTG peripheral-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2965
Figure 702. OTG host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2969
Figure 703. SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . . . . . . . . . . . . 2973
Figure 704. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2975
Figure 705. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . 2976
Figure 706. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . . 2977
Figure 707. Interrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2981
Figure 708. Transmit FIFO write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3080
Figure 709. Receive FIFO read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3081
Figure 710. Normal bulk/control OUT/SETUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3082
Figure 711. Bulk/control IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3086
Figure 712. Normal interrupt OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3089
Figure 713. Normal interrupt IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3094
Figure 714. Isochronous OUT transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3096
Figure 715. Isochronous IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3099
Figure 716. Normal bulk/control OUT/SETUP transactions - DMA . . . . . . . . . . . . . . . . . . . . . . . . . . 3101
Figure 717. Normal bulk/control IN transaction - DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3103
Figure 718. Normal interrupt OUT transactions - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3104
Figure 719. Normal interrupt IN transactions - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3105
Figure 720. Normal isochronous OUT transaction - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3106
Figure 721. Normal isochronous IN transactions - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3107
Figure 722. Receive FIFO packet read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3113
Figure 723. Processing a SETUP packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3115
Figure 724. Bulk OUT transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3122
Figure 725. TRDT max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3131
Figure 726. A-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3132
Figure 727. B-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3133
Figure 728. A-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3134
Figure 729. B-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3136
Figure 730. USBPHYC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3139
Figure 731. USBH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3151
Figure 732. Ethernet high-level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3173
Figure 733. DMA transmission flow (standard mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3176
Figure 734. DMA transmission flow (OSP mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3178
Figure 735. Receive DMA flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3180
Figure 736. Overview of MAC transmission flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3183
Figure 737. MAC reception flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3185
Figure 738. Packet filtering sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3198
Figure 739. Networked time synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3207
Figure 740. Propagation delay calculation in clocks supporting
peer-to-peer path correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3208
Figure 741. System time update using fine correction method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3218
Figure 742. TCP segmentation offload overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3235
Figure 743. TCP segmentation offload flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3236
Figure 744. Header and payload fields of segmented packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3239
Figure 745. Supported PHY interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3249
Figure 746. SMA Interface block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3250
Figure 747. MDIO packet structure (Clause 45) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3250
Figure 748. MDIO packet structure (Clause 22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3251
Figure 749. SMA write operation flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3253
Figure 750. Write data packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3254
Figure 751. Read data packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3254
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Figure 752. Media independent interface (MII) signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3256
Figure 753. Giga media independent interface (GMII) signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3258
Figure 754. RMII block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3260
Figure 755. Transmission bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3261
Figure 756. Receive bit order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3262
Figure 757. RGMII block diagram and interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3263
Figure 758. LPI transitions (Transmit, 100 Mbds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3272
Figure 759. LPI Tx clock gating (when LPITCSE = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3273
Figure 760. LPI transitions (receive, 100 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3274
Figure 761. Descriptor ring structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3300
Figure 762. DMA descriptor ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3302
Figure 763. Descriptor tail pointer example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3302
Figure 764. Descriptor tail pointer example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3303
Figure 765. Transmit descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3304
Figure 766. Transmit descriptor write-back format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3309
Figure 767. Transmit context descriptor format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3313
Figure 768. Receive normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3317
Figure 769. Receive normal descriptor (write-back format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3320
Figure 770. Receive context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3327
Figure 771. Generation of ETH_DMAISR flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3347
Figure 772. HDMI-CEC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3485
Figure 773. Message structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3485
Figure 774. Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3486
Figure 775. Bit timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3486
Figure 776. Signal free time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3487
Figure 777. Arbitration phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3487
Figure 778. SFT of three nominal bit periods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3487
Figure 779. Error bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3488
Figure 780. Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3490
Figure 781. TXERR detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3491
Figure 782. Hardware debug port block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3501
Figure 783. Block diagram of debug support infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3513
Figure 784. Debug clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3515
Figure 785. JTAG TAP state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3520
Figure 786. SWD successful data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3524
Figure 787. Debug and access port connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3533
Figure 788. Debug APB CoreSight™ topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3548
Figure 789. CoreSight™ timestamp distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3555
Figure 790. Embedded cross trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3563
Figure 791. Mapping trigger inputs to outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3566
Figure 792. Cross trigger configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3567
Figure 793. System Trace Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3647
Figure 794. Cortex®-M4 CoreSight™ topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3813
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Documentation conventions
1.1
General information
The STM32MP153 devices embed an Arm®(a) Cortex®-M4 with FPU and a dual Arm®
Cortex®-A7 with FPU cores.
1.2
List of abbreviations for registers
The following abbreviations(b) are used in register descriptions:
read/write (rw)
Software can read and write to this bit.
read-only (r)
Software can only read this bit.
write-only (w)
Software can only write to this bit. Reading this bit returns the reset value.
read/clear write0 (rc_w0)
Software can read as well as clear this bit by writing 0. Writing 1 has no
effect on the bit value.
read/clear write1 (rc_w1)
Software can read as well as clear this bit by writing 1. Writing 0 has no
effect on the bit value.
read/clear write (rc_w)
Software can read as well as clear this bit by writing to the register. The
value written to this bit is not important.
read/clear by read (rc_r)
Software can read this bit. Reading this bit automatically clears it to 0.
Writing this bit has no effect on the bit value.
read/set by read (rs_r)
Software can read this bit. Reading this bit automatically sets it to 1.
Writing this bit has no effect on the bit value.
read/set (rs)
Software can read as well as set this bit. Writing 0 has no effect on the bit
value.
read/write once (rwo)
Software can only write once to this bit and can also read it at any time.
Only a reset can return the bit to its reset value.
toggle (t)
The software can toggle this bit by writing 1. Writing 0 has no effect.
read-only write trigger (rt_w1) Software can read this bit. Writing 1 triggers an event but has no effect on
the bit value.
Reserved (Res.)
Reserved bit, must be kept at reset value.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
b. This is an exhaustive list of all abbreviations applicable to STMicroelectronics microcontrollers, some of
them may not be used in the current document.
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Register reset value
Bits (binary notation) or bits nibbles (hexadecimal notation) of which the reset value is
undefined are marked as X.
Bits (binary notation) or bits nibbles (hexadecimal notation) of which the reset value is
unmodified are marked as U.
1.4
Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
•
1.5
The product integrates two debug ports:
–
JTAG debug port (JTAG-DP) provides a 5-pin standard interface based on the
Joint Test Action Group (JTAG) protocol.
–
SWD debug port (SWD-DP) provides a 2-pin (clock and data) interface based on
the Serial Wire Debug (SWD) protocol.
•
Word: data of 32-bit length.
•
Half-word: data of 16-bit length.
•
Byte: data of 8-bit length.
•
Double word: data of 64-bit length.
•
Option bytes: product configuration bits stored in internal fuses.
•
OTP: one-time programming (fuses).
•
AHB: advanced high-performance bus.
•
APB: advanced peripheral bus.
•
AXI: Advanced extensible interface protocol.
•
ECC: error code correction.
•
DMA: direct memory access.
•
AHBS: AHB slave bus.
•
AXIM: AXI interconnect matrix.
Availability of peripherals
For availability of peripherals and their number across all devices, refer to the particular
device datasheet.
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Memory and bus architecture
2
Memory and bus architecture
2.1
System architecture
2.1.1
Bus architecture
The bus architecture is organized around two interconnect matrix, which operate in different
frequency domains, as described in Figure 1.
•
One high speed Arm® CoreLink™ NIC-400 network interconnect AXI-based:
This interconnect is dedicated to Cortex-A7 CPU subsystem and high bandwidth
masters (this part of the system is called MPU-side in the following): USBH, ETH,
SDMMC1/2, MDMA, LTDC.
It manages accesses to:
•
–
external memories DDR (through DDRCTRL), NAND/NOR (through FMC or
QUADSPI)
–
main system internal memories SYSRAM and ROM
–
main cluster of security peripherals through AHB5 bus
–
some low-speed communication peripherals through APB5 bus
–
control and configuration of the high-bandwidth masters
–
STM (system trace macrocell)
One multi-layer AHB interconnect with an architecture inherited from former MCU
families (this part of the system is called MCU-side in the following).
This interconnect is dedicated to Cortex-M4 subsystem and associated masters: OTG,
DMA1/2, SDMMC3.
It manages accesses to:
–
Cortex-M4 dedicated SRAM1,2,3,4
–
most timers and low-speed communication peripherals through AHB2 bus
–
Cortex-M4 dedicated retention memory (RETRAM)
–
secondary cluster of security peripherals and camera interface through AHB3 bus
–
resources dedicated to communication with Cortex-A7 cluster: mailbox and
semaphore through AHB3 bus
–
main infrastructure blocks as clock generation, power control, system
configuration, and miscellaneous peripherals through AHB4 bus
AXI and multi-layer AHB matrix are connected to each other through one dedicated datapath in both directions:
•
AXIM master port has access to all multi-layer AHB slaves. Some of them can become
not accessible when the M4 isolation feature is activated.
•
Multi-layer AHB master has access to all AXI slaves except:
–
ROM
–
slaves that can be accessed in secure mode only.
The bus architecture diagram in Figure 1 describes the interconnect for STM32MP153
family.
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Cortex-A7 core
Dual
Cortex-A7
CPU
subsystem
Cortex-A7 core
FPU
Data RAM 256 KB
Tags
M1
M2
M3
L2 subsystem
AXI 64 asynchronous slave port
AHB 32 synchronous master port
AHB 32 synchronous slave port
AXI 64 bit bus
AHB 32 bit bus
GIC
ck_mpuss
SD
MMC1
SD
MMC2
MDMA
M5
M6
M7
AHB 32 asynchronous master port
Frequency domain boundary
ck_aclk = 266 MHz
M4
AXI 64 asynchronous master port
Master Mx can access
S0 XOR S1 slave
AHB 32 asynchronous slave port
ck_mcu = 209 MHz
LTDC
M9
S1
S2
DDRCTRL
533 MHz
DMA1
DMA2
M1 M2
M3 M4
SD
MMC3
OTG
_HS
M5
M6
AHB Bridge
to AHB6
Cortex_M4
S3
I-BUS
RM0442 Rev 7
S0
S-BUS
M0
Snoop
control
unit
AXI 64 synchronous master port
AXI 64 synchronous slave port
Master Mx access
slave Sy enabled
D-BUS
M10
ETH
USBH
L1 instruction
cache 32 KB
128 bits
L1 data
cache 32 KB
DBG
NEON
CPU
Memory and bus architecture
118/3930
Figure 1. Bus interconnect for STM32MP153
S4
FMC
S5
M0
QUADSPI
S6
SYSRAM
256 KB
S7
M7 M8 M9 S0
SRAM2
S2
SRAM3
S8
SRAM4
STM
S3
AHB bridge
to AHB3
S9
AHB bridge
to AHB5
S4
AHB bridge
to AHB2
S10
APB bridge
to APB5
S11
APB bridge to
debug APB
S5
S6
Retention
RAM
S7
AHB bridge
to AHB
Main AHB interconnect matrix
MSv43999V4
RM0442
ROM 128 KB
S8
AXI interconnect matrix
SRAM1
S1
RM0442
2.1.2
Memory and bus architecture
Memory Map organization
Introduction
For the detailed mapping of available memory and register areas, please refer to
Section 2.5: Memory organization.
The following paragraphs describe the various resources in the system.
Embedded Memories
•
ROM
The 128 Kbyte embedded ROM is a fast access memory (no wait states). It is
dedicated to Cortex-A7 CPU subsystem for boot code execution.This memory and the
associated memory controller operate at aclk = 266 MHz.
•
Cortex-A7 CPU subsystem cache memories
Please refer to Cortex-A7 CPU subsystem description for cache memories
characteristics.
•
SYSRAM
The 256 Kbyte embedded SYSRAM is a fast access static RAM, dedicated to
Cortex-A7 CPU subsystem for code execution and low-latency data management. The
SRAM itself is 0 wait-states. Some latency is added when data is propagated through
the AXI interconnect.This memory and the associated memory controller operate at
aclk = 266 MHz.
•
MCU SRAM1,2,3,4
The SRAM1,2,3,4 are two 128 Kbyte and two 64 Kbyte fast access static RAMs
dedicated to Cortex-M4 MCU for code execution, low-latency data management, and
data storage for exchange with the Cortex-A7 CPU subsystem.The SRAM1,2,3,4 are 0
wait-states. Some latency is added when data is propagated through the AHB
interconnect. These memories and the associated memory controllers operate at
mcu_ck = 209 MHz.
•
Retention RAM (RETRAM)
The RETRAM is a 64 Kbyte fast access static RAMs with specific supply providing data
retention in all power modes including VBAT and STANDBY. The RETRAM is 0 waitstates. Some latency is added when data is propagated through the AHB interconnect
(access from MCU-side), or AXI and AHB interconnects (access from MPU-side).This
memory and the associated memory controllers operate at mcu_ck = 209 MHz.
•
Backup RAM
The backup RAM is a 4 Kbyte static RAMs with dual-rail supply providing data backup
for the whole system, whatever the power mode, with standard latency.This memory
and the associated memory control operate at hclk5 = 266 MHz.
•
OTP
OTP is a secure one-time-programmed non volatile memory with 3072 effective bits in
total. It contains system configuration information.This memory and the associated
memory controllers operate at pclk5 = 133 MHz.
OTP is auto-loaded after reset. Bits are held in shadow registers accessible at
133 MHz.
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Memory and bus architecture
RM0442
External memories support
•
DDR3/LPDDR2 controller (DDRCTRL)
The DDR supported types are LPDDR2, LPDDR3, DDR3/3L. Regarding external
memory, 16 or 32 bits data width are possible, while internally, the DDRCTRL is
connected to 64-bit data width interconnect. The maximum supported size is 1 Gbytes.
The DDRCTRL is accessible through two AXI data ports, which have same
characteristics. A system configuration register allows a given master to select which
port to use, to balance traffic between the two ports.
More information on memory characteristics and controller parametrization are
available in Section 5: DDR3/LPDDR2/LPDDR3 controller (DDRCTRL) and Section 7:
DDR physical interface control (DDRPHYC).
The DDRCTRL operates at aclk = 266 MHz. The external memory operates at up to
pll2_r = 533 MHz depending on the system configuration.
•
Flexible memory controller (FMC) / QUADSPI
There is no internal Flash memory in the SoC. The system initial-boot-phase and selfinitialization is supported by boot ROM and BSEC.
External Flash memory is accessible through NAND configurable FMC, or through
QUADSPI.
The FMC also allows parallel connection of a SRAM/PSRAM instead of Flash memory
if needed.
•
SD/SDIO/MMC card host interfaces (SDMMCx)
There is no internal Flash memory in the SoC. The system initial-boot-phase and selfinitialization is supported by boot ROM and BSEC.
External Flash memory such as SD card or e•MMC are accessible through SDMMCx
SD, SDIO, eMMC devices are interfaced through three SDMMC controllers. Two of
them are hooked to the AXIM interconnect and the third one to multi-layer AHB
subsystem.
These controllers are masters of the interconnect and originate the transfers to/from
SD/SDIO/MMC memories.
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RM0442
Memory and bus architecture
Peripherals clusters
There are seven peripherals clusters in the system, briefly described hereafter.
Note:
the AHBx/APBy notation means that the resources are accessed through bus AHBx, and for
some of them through bus AHBx in combination with bus APBy.
•
AHB4/APB3
This cluster groups important system functions as clock and power control, system
configuration, most GPIOs control, plus some additional timers and low-speed
communication interfaces.
•
AHB3
This cluster groups some security blocks dedicated to Cortex-M4, camera interface
and interprocessor communication resources.
•
AHB2/APB1-APB2
This cluster groups most of the usual MCU peripherals: timers, low-speed
communication interfaces (SPI, I2C, U(S)ART, SAI), ADC, DAC, FDCAN and DFSDM.
All those IPs are typically controlled by Cortex-M4, directly or through DMA1/2, but can
also be managed by Cortex-A7 CPU subsystem as well.
•
AHB5
•
APB5
This cluster groups security blocks dedicated to Cortex-A7 and the backup RAM.
This cluster groups some low-speed secure communication blocks dedicated for
Cortex-A7, in addition to BSEC and chip configuration control resources.
Real time clock generation and anti-tamper features also belong to this cluster.
•
AHB6/APB4
This cluster groups most of the graphic/display resources control, as well as access to
configuration registers of the fast masters: MDMA, ETHernet, SDMMC1/2,USBH.
•
Debug
This cluster groups all debug features including Arm® CoreSight™ infrastructure.
Memory map overview
Table 1 summarizes which master (cf Figure 1) can access which memory-mapped
resource.
Table 1. Memory map overview STM32MP153
Resource
DDR
Cortex-A7 debug
Cortex-M4 debug
Cortex-A7 GIC
STM
Ext FMC interface
Ext QUADSPI
Ext NOR interface
AXIM registers
APB5 peripherals
CortexA7
CortexM4
Debugger
MDMA /
DMA1 /
DMA2
ETH
x
x(1)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
-
RM0442 Rev 7
OTG /
USBH / SDMMC1,2 /
SDMMC3
LTDC
x
-
x
-
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Memory and bus architecture
RM0442
Table 1. Memory map overview STM32MP153 (continued)
Resource
AHB6/APB4 peripherals
AHB5 peripherals
APB debug peripherals
AHB4/APB3 peripherals
AHB2/APB1,2 peripherals
AHB3/APB1,2 peripherals
RETRAM
SRAM 1,2,3,4
SYSRAM
ROM/RETRAM
@0x0000 0000
CortexA7
CortexM4
Debugger
MDMA /
DMA1 /
DMA2
ETH
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x(2)
x(2)
x(2)
-
-
-
-
OTG /
USBH / SDMMC1,2 /
SDMMC3
LTDC
1. Cortex-A7 accesses its own debug resources through CoreSight infrastructure.
2. Cortex-A7 and debugger see the ROM, while the Cortex-M4 access RETRAM at this location.
2.2
AXI interconnect matrix (AXIM)
2.2.1
AXIM features
The AXIM is implemented with NIC-400 network interconnect. Its main features are:
122/3930
•
10 masters, and 12 slave layers (plus 2 internal slaves), with optimized interconnect
topology from masters to slaves (no full interconnect)
•
Simultaneous accesses support from different masters to slaves connected to
separated layers
•
Protocol conversion (AXI, AHB) support
•
Internal data and commands buffering for improved traffic efficiency
•
QoS programming support
•
Asynchronism management
•
Software configuration of internal parameters (QOS, bypass,...) through user
accessible registers.
RM0442 Rev 7
RM0442
Memory and bus architecture
2.2.2
AXIM interconnect configuration
The NIC-400 interconnect configuration is described in Figure 2.
Figure 2. NIC-400 interconnect AXIM for STM32MP153
From MCU
interconnect
DBG
ETH
USBH
CPU
SD
MMC1
SD
MMC2
Master Mx access
slave Sy enabled
AXI 64 synchronous master port
AXI 64 synchronous slave port
Master Mx can access
S0 XOR S1 slave
AXI 64 asynchronous master port
AXI 64 asynchronous slave port
AHB 32 synchronous master port
AHB 32 synchronous slave port
MDMA
LTDC
AHB 32 asynchronous master port
128 bits
AHB 32 asynchronous slave port
M10
M0
M1
M2
M3
M4
M5
M6
M7
M9
S0
MPU_AXI_DDR1
S1
MPU_AXI_DDR2
S2
MPU_AHB6
S3
MPU_AHB_MCU
S4
MPU_AXI_FMC
S5
MPU_AXI_QSPI
DDRCTRL
400/533 MHz
AHB bridge
to AHB6
To MCU
interconnect
FMC
QUADSPI
S6
MPU_AXI_SYSRAM
S7
MPU_AXI_ROM
SYSRAM 256
KB
ROM 128 KB
S8
MPU_AXI_STM
S9
MPU_AHB5
S10
MPU_APB5
S11
MPU_DBG_APB
STM
AHB bridge
to AHB5
APB bridge
to APB5
APB bridge to
debug APB
Default
slave
AXIMC
Multi-layer AXI
Interconnect AXI 64 bits, 266 MHz, 10 masters, 12 slaves
MSv46618V3
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Memory and bus architecture
2.2.3
RM0442
Master ports description
•
M0: asynchronous port connected to MCU interconnect master port
Allows masters from the MCU subsystem to have access to all blocks in the system,
except ROM and AXIMC internal slave (also known as GPV, global programmer view)
which contains all NIC-400 programming registers.
•
M1/M2: two AHB-Lite ports connected to USBHost master ports, with same capacities
Accesses are limited to DDR and SYSRAM memories.
•
M3: AXI4 port connected to ETHernet gigabit interface
Accesses are limited to DDR and SYSRAM memories, plus memories located in MCU
subsystem.
•
M4: AXI3 port connected to Cortex-A7 CPU subsystem (128-bit wide)
The asynchronism is managed inside the CPU subsystem. The conversion to 64 bits is
done inside the NIC-400. The CPU subsystem is connected to DDR controller port 0
only. The user can choose to hook other masters on this layer, or leave the CPU as
single master, depending on application needs.
•
M5/M6: two AHB-Lite ports connected to SDMMC1 and SDMMC2 master ports
Accesses are limited to DDR, and SYSRAM memories.
•
M7: AXI4 port connected to MDMA
MDMA is able to access all slaves in the system including the configuration ports of
master IPs. It can be used to perform the entire programing of such blocks thanks to its
linked list support. This master has important read issuing capabilities and is able to
generate peak traffic approaching the layer theoretical max throughput.
•
M9: AXI4 port connected to LTDC display driver
Accesses are limited to DDR and SYSRAM memories.
•
M10: AXI4 port connected to debug access port (DAP) AXI
This master port has access to all slaves, except S11 going back to the DAP to avoid
dual data-path in the system topology. M10 also accesses the AXIMC internal slave
which contains all interconnect programming registers.
2.2.4
Master ports main characteristics
Table 2 summarizes the master ports main characteristics.
Table 2. Master ports main characteristics
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Master port
Nb
Protocol
Data bus
width
Synchronicity
ID
width
Default
QOS
value(1)
Read/write
issuing
capability
MCU interco
USBH p1
USBH p2
ETH
CPU
SDMMC1
SDMMC2
MDMA
LTDC
DEBUG / DAP
M0
M1
M2
M3
M4
M5
M6
M7
M9
M10
AHB_Lite
AHB_Lite
AHB_Lite
AXI4
AXI3
AHB_Lite
AHB_Lite
AXI4
AXI4
AXI4
32
32
32
64
128
32
32
64
64
64
Async
Sync
Sync
Sync
Sync
Sync
Sync
Sync
Sync
Sync
1
1
1
4
6
1
1
1
4
1
6
5
5
7
12
4
4
8
11
2
1/1
1/1
1/1
1/1
8/8
1/1
1/1
8/1
2/1
1/1
RM0442 Rev 7
RM0442
Memory and bus architecture
1. Master priorities can be modified by software.
2.2.5
Master ports security characteristics
Table 3 lists the master ports security characteristics.
Table 3. Master ports security characteristics
Nb
NIC input signals
used for security
propagation
TrustZone
configuration
MCU interco
M0
HAuser(5:0)
Non-secure
USBH p1
USBH p2
M1
M2
Non-secure
Non-secure
ETH
M3
Non-secure
0b1010
CPU
M4
Per-access
0b0000
SDMMC1
SDMMC2
M5
M6
Non-secure
Non-secure
0b1001
0b1001
MDMA
M7
Per-access
0b0101
LTDC
M9
Non-secure
0b0011
DEBUG / DAP
M10
HAuser(5:0)
HAuser(5:0)
ARuser(5:0)
AWuser(5:0)
ARuser(5:0)
AWuser(5:0)
HAuser(5:0)
HAuser(5:0)
ARuser(5:0)
AWuser(5:0)
ARuser(5:0)
AWuser(5:0)
ARuser(5:0)
AWuser(5:0)
0b0001 for Cortex-M4
ob0110 for DMA1 / DMA2
0b1000 for OTG
0b0111
0b0111
Per-access
0b1111
Master ports
NSAID(1)
1. Master M0 transmits several NSAIDs corresponding to multi-layer AHB masters. Different masters of same
type (SDMMC1/2 and USBH1/2) generate the same NSAID value.
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Memory and bus architecture
2.2.6
RM0442
Slave ports description
•
S0, S1: AXI3 synchronous ports 0 and 1 of DDR controller. Asynchronism is managed
inside the DDR controller.
•
S2: AHB-Lite synchronous port connected to AHB6, which is the bridge to configuration
ports of all masters.
•
S3: AHB-Lite asynchronous port connected to main MCU multi-layer AHB interconnect,
giving access to Cortex-A7 to all MCU peripherals.
•
S4: AXI3 synchronous port to NAND/NOR controller
•
S5:AXI3 synchronous port to QUADSPI controller
•
S6:AXI3 synchronous port to SYSRAM controller
•
S7:AXI3 synchronous port to ROM controller
•
S8: AXI3 synchronous port to STM trace data buffer
•
S9: AHB-Lite synchronous port to AHB5. This bridge controls access to crypto
resources, secure GPI0s and backup RAM.
•
S10: AHB-Lite synchronous port to protocol converter for APB5. APB5 is an APB3 bus
supporting security signals propagation. This bus controls access to security
management blocks and a set of secure peripherals.
•
S11: AHB-Lite synchronous port to protocol converter for APB_DEBUG access located
in DAP.
Internal slaves:
2.2.7
•
Default slave: defines the interconnect behavior when accesses are done in a nonvalid region.
•
AXIMC (also known as GPV): contains all NIC-400 interconnect configuration registers.
The interconnect configuration register set can be accessed only by two masters:
Cortex-A7 CPU (software configuration in early stage of application) and DAP (debug,
mainly for check).
Slave ports main characteristics
Table 4 lists the slave ports main characteristics.
Table 4. Slave ports main characteristics
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Slave port
Nb
Protocol
Data bus
width
Synchronicity
Read / write
acceptance capability
DDR p0
DDR p1
AHB6
Multi-layer AHB
FMC
QUADSPI
SYSRAM
ROM
STM
AHB5
APB5
DEBUG/DAP
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
AXI4
AXI4
AHB_Lite
AXI4
AXI4
AXI4
AXI3
AXI3
AXI4
AXI4
AHB_Lite
AHB_Lite
64
64
32
32
64
64
64
64
64
32
32
32
Sync
Sync
Sync
Async
Sync
Sync
Sync
Sync
Sync
Sync
Sync
Sync
20/20(1)
20/20(1)
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
RM0442 Rev 7
RM0442
Memory and bus architecture
1. DDR read / write acceptance capability = CAM size (16) + internal AXI port interface FIFO (4)
2.2.8
Slave ports security characteristics
Table 5 lists the slave ports security characteristics.
Table 5. Slave ports security characteristics
Slave ports
Nb
DDR p0
S0
DDR p1
S1
AHB6
Multi-layer AHB
S2
S3
FMC
S4
QUADSPI
S5
SYSRAM
S6
ROM
S7
STM
S8
AHB5
S9
APB5
S10
DEBUG/DAP
S11
NIC input signals used for
security propagation
ARuser(5:0)
AWuser(5:0)
ARuser(5:0)
AWuser(5:0)
HAuser(5:0)
HAuser(5:0)
ARuser(5:0)
AWuser(5:0)
HAuser(5:0)
ARuser(5:0)
AWuser(5:0)
ARuser(5:0)
AWuser(5:0)
ARuser(5:0)
AWuser(5:0)
ARuser(5:0)
AWuser(5:0)
ARuser(5:0)
AWuser(5:0)
HAuser(5:0)
2.3
Multi-layer AHB interconnect
2.3.1
Multi-layer AHB features
TrustZone configuration
Secure and non-secure
Secure and non-secure
Secure and non-secure
Secure and non-secure
Secure and non-secure
Secure and non-secure
Secure and non-secure
Secure and non-secure
Secure and non-secure
Secure and non-secure
Secure and non-secure
Per-access
The multi-layer AHB interconnect is an optimized version of Arm BP010 interconnect.
Its main features are:
2.3.2
•
10 masters, and 9 slave layers, all 32-bit data
•
Simultaneous accesses support from different masters to slaves connected to
separated layers
•
Internal data and commands buffering for improved traffic efficiency
Multi-layer AHB interconnect configuration
The multi-layer AHB interconnect configuration is described in Figure 3.
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Memory and bus architecture
RM0442
Figure 3. Multi-layer AHB interconnect for STM32MP153
SD
MMC3
OTG
_HS
M0
M1 M2
M3 M4
M5
M6
Master Mx access
slave Sy enabled
Cortex_M4
AHB 32 synchronous master port
AHB 32 synchronous slave port
I-BUS
DMA2
S-BUS
DMA1
D-BUS
From MPU
interconnect
M7 M8 M9 S0
S1
S2
S8
S3
S4
MCU_AHB_MEM0
SRAM1
MCU_AHB_MEM1
SRAM2
MCU_AHB_MEM2
SRAM3
MCU_AHB_MEM3
SRAM4
MCU_AHB3
MCU_AHB2
AHB bridge
to AHB3
AHB bridge
to AHB2
S5
MCU_AHB_MPU
S6
MCU_AHB_RET
Retention
RAM
S7
MCU_AHB4
AHB bridge
to AHB4
To MPU
interconnect
Multi-layer AHB
Interconnnect AHB 32 bits, 209 MHz, 10 masters, 9 slaves
MSv46620V2
2.3.3
Multi-layer AHB master ports characteristics
•
M0: AHB-Lite connected to MPU interconnect master port
It allows masters from the MPU subsystem to have access to all slaves in the system,
except the path to MPU to avoid loopback.
•
M1, M2, M3, M4: four AHB-Lite ports connected to DMA1 and DMA2 dual-master
blocks, with same capacities.
Accesses are granted to all slaves in the subsystem: Cortex-M4 SRAMs and bridges to
all peripherals.
•
M5: AHB-Lite ports connected to SDMMC3 interface.
Accesses are limited to Cortex-M4 RAMs, retention RAM and memories located in
MPU subsystem (SYSRAM, DDR) through the main NIC-400 AXI interconnect.
•
M6: AHB-Lite port connected to OTG interface.
Accesses are limited to Cortex-M4 RAMs, retention RAM and memories located in
MPU subsystem (SYSRAM, DDR) through the main NIC-400 AXI interconnect.
•
M7: AHB-Lite port connected to the S-bus Cortex-M4 subsystem.
It allows the Cortex-M4 to have access to all slaves in the system, including a number
of those located in MPU subsystem through the main NIC-400 AXI interconnect.
•
M8, M9: AHB-Lite port connected to the I-bus and D-bus of Cortex-M4 subsystem.
It allows the Cortex-M4 to have access to slaves in the system located below 0x20 000
000, which are retention RAM and SRAM1,2,3,4. No peripherals are re-mapped below
0x20 000 000.
Table 6 lists the main characteristics of multi-layer AHB master ports.
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Memory and bus architecture
Table 6. Multi-layer AHB master ports main characteristics
2.3.4
Master ports
Nb
Protocol
Data bus width
Synchronicity
AHB_MPU
DMA1 p1
DMA1 p2
DMA2 p1
DMA2 p2
SDMMC3
OTG
SBUS of Cortex-M4
DBUS of Cortex-M4
IBUS of Cortex-M4
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
AHB-Lite
AHB-Lite
AHB-Lite
AHB-Lite
AHB-Lite
AHB-Lite
AHB-Lite
AHB-Lite
AHB-Lite
AHB-Lite
32
32
32
32
32
32
32
32
32
32
Sync
Sync
Sync
Sync
Sync
Sync
Sync
Sync
Sync
Sync
Multi-layer AHB slave ports characteristics
•
S0, S1, S2, S8: AHB-Lite synchronous ports to SRAM1,2,3,4.
S1 is the slave which provides the best latency when accessed from M4 S-port.
•
S3: AHB-Lite synchronous port to AHB3
This bridge controls access to crypto resources and communications IPs with CortexA7 cluster.
•
S4: AHB-Lite synchronous port connected to AHB2
It is the bridge to configuration ports of all masters connected to multi-layer AHB. This
port also allows to access all resources located in APB1 and APB2 clusters, and ADCs.
•
S5: AHB-Lite synchronous port connected to main NIC-400 interconnect
It gives access to multi-layer AHB master to most SoC peripherals.
•
S6: AHB-Lite synchronous port to retention RAM controller
•
S7: AHB-Lite synchronous port to AHB4
This bridge controls access to a cluster comprising main system management utilities
(clock, power), all non-secure GPIOs and a complementary set of peripherals, allowing
to activate only this cluster for simple applications.
The following table lists the multi-layer AHB slave ports main characteristics.
Table 7. Multi-layer AHB slave ports main characteristics
Slave port
Nb
Protocol
Data bus
width
Synchronicity
Clock ratio
SRAM1
SRAM2
SRAM3
SRAM4
AHB3
AHB2
MPU_NIC400
RETRAM
AHB4
S0
S1
S2
S8
S3
S4
S5
S6
S7
AHB-Lite
AHB-Lite
AHB-Lite
AHB-Lite
AHB-Lite
AHB-Lite
AHB-Lite
AHB-Lite
AHB-Lite
32
32
32
32
32
32
32
32
32
sync
sync
sync
sync
sync
sync
sync
sync
sync
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
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2.4
RM0442
AXIMC registers
The following register description is only about AXIM interconnect, as multi-layer AHB
interconnect has no configuration registers.
x is the number of the master (Mx with x=10 means M10). Parameters of the masters vary
depending on their capabilities, so the number of registers may differ from one to another.
2.4.1
AXIMC peripheral ID4 register (AXIMC_PERIPH_ID_4)
Address offset: 0x1FD0
Reset value: 0x0000 0004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
K4COUNT[3:0]
r
r
r
JEP106CON[3:0]
r
r
r
r
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 K4COUNT[3:0]: register file size
Bits 3:0 JEP106CON[3:0]: JEP106 continuation code
2.4.2
AXIMC peripheral ID5 register (AXIMC_PERIPH_ID_5)
Address offset: 0x1FD4
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
r
r
r
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PERIPH_ID_5[7:0]
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PERIPH_ID_5[7:0]: reserved, not used.
130/3930
RM0442 Rev 7
r
r
r
r
RM0442
Memory and bus architecture
2.4.3
AXIMC peripheral ID6 register (AXIMC_PERIPH_ID_6)
Address offset: 0x1FD8
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
r
r
r
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PERIPH_ID_6[7:0]
r
r
r
r
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PERIPH_ID_6[7:0]: reserved, not used.
2.4.4
AXIMC peripheral ID7 register (AXIMC_PERIPH_ID_7)
Address offset: 0x1FDC
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
r
r
r
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PERIPH_ID_7[7:0]
r
r
r
r
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PERIPH_ID_7[7:0]: reserved, not used.
2.4.5
AXIMC peripheral ID0 register (AXIMC_PERIPH_ID_0)
Address offset: 0x1FE0
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
r
r
r
r
r
r
PERIPH_ID_0[7:0]
r
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PERIPH_ID_0[7:0]: part number [7:0]
RM0442 Rev 7
131/3930
152
Memory and bus architecture
2.4.6
RM0442
AXIMC peripheral ID1 register (AXIMC_PERIPH_ID_1)
Address offset: 0x1FE4
Reset value: 0x0000 00B4
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
r
r
r
r
r
r
PERIPH_ID_1[7:0]
r
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PERIPH_ID_1[7:0]: JEP106 identity [3:0], part number [11:8]
2.4.7
AXIMC peripheral ID2 register (AXIMC_PERIPH_ID_2)
Address offset: 0x1FE8
Reset value: 0x0000 003B
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
r
r
r
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PERIPH_ID_2[7:0]
r
r
r
r
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PERIPH_ID_2[7:0]: part revision, JEP106 code flag, JEP106 identity [6:4]
2.4.8
AXIMC peripheral ID3 register (AXIMC_PERIPH_ID_3)
Address offset: 0x1FEC
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
REV_AND[3:0]
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 REV_AND[3:0]: customer version
0: none
132/3930
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r
r
CUST_MOD_NUM[3:0]
r
r
r
r
r
RM0442
Memory and bus architecture
Bits 3:0 CUST_MOD_NUM[3:0]: customer modification
0: none
2.4.9
AXIMC component ID0 register (AXIMC_COMP_ID_0)
Address offset: 0x1FF0
Reset value: 0x0000 000D
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
r
r
r
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PREAMBLE[7:0]
r
r
r
r
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[7:0]: preamble bits [7:0]
2.4.10
AXIMC component ID1 register (AXIMC_COMP_ID_1)
Address offset: 0x1FF4
Reset value: 0x0000 00F0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CLASS[3:0]
r
r
r
PREAMBLE[11:8]
r
r
r
r
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 CLASS[3:0]: Component class
0xF: generic IP component class
Bits 3:0 PREAMBLE[11:8]: preamble bits [11:8]
0x0: common ID value
RM0442 Rev 7
133/3930
152
Memory and bus architecture
2.4.11
RM0442
AXIMC component ID2 register (AXIMC_COMP_ID_2)
Address offset: 0x1FF8
Reset value: 0x0000 0005
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
r
r
r
r
r
r
r
PREAMBLE[19:12]
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[19:12]: preamble bits [19:12]
2.4.12
AXIMC component ID3 register (AXIMC_COMP_ID_3)
Address offset: 0x1FFC
Reset value: 0x0000 00B1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
r
r
r
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PREAMBLE[27:20]
r
r
r
r
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[27:20]: preamble bits [27:20]
2.4.13
AXIMC master x packing functionality register
(AXIMC_Mx_FN_MOD2)
Address offset: 0x42024 + 0x1000 * x, (x = 0 to 2)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BYPASS_MERGE
Reset value: 0x0000 0000
rw
134/3930
RM0442 Rev 7
RM0442
Memory and bus architecture
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 BYPASS_MERGE: Disable packing of beats to match the output data width
Unaligned transactions are not realigned to the input data word boundary.
0: normal operation
1: disable packing
2.4.14
AXIMC master x AHB conversion override functionality register
(AXIMC_Mx_FN_MOD_AHB)
Address offset: 0x42028 + 0x1000 * x, (x = 0 to 2)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WR_INC_OVERRIDE
RD_INC_OVERRIDE
Reset value: 0x0000 0000
rw
rw
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 WR_INC_OVERRIDE: Converts all AHB-Lite write transactions to a series of single beat AXI
transactions, and each AHB-Lite write beat is acknowledged with the AXI buffered write
response.
0: override disabled
1: override enabled
Bit 0 RD_INC_OVERRIDE: Converts all AHB-Lite read transactions to a series of single beat AXI
transactions.
0: override disabled
1: override enabled
RM0442 Rev 7
135/3930
152
Memory and bus architecture
2.4.15
RM0442
AXIMC master x read priority register (AXIMC_Mx_READ_QOS)
Address offset: 0x42100 + 0x1000 * x, (x = 0 to 2)
Reset value: Block 0: 0x0000 0006
Reset value: Block 1: 0x0000 0005
Reset value: Block 2: 0x0000 0005
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AR_QOS[3:0]
rw
rw
rw
rw
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 AR_QOS[3:0]: read channel QoS setting
0x0: lowest priority
0xF: highest priority
2.4.16
AXIMC master x write priority register (AXIMC_Mx_WRITE_QOS)
Address offset: 0x42104 + 0x1000 * x, (x = 0 to 2)
Reset value: Block 0: 0x0000 0006
Reset value: Block 1: 0x0000 0005
Reset value: Block 2: 0x0000 0005
31
30
29
28
27
26
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23
22
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19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AW_QOS[3:0]
rw
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 AW_QOS[3:0]: write channel QoS setting
0x0: lowest priority
0xF: highest priority
136/3930
RM0442 Rev 7
rw
rw
rw
RM0442
Memory and bus architecture
2.4.17
AXIMC master x issuing capability override functionality register
(AXIMC_Mx_FN_MOD)
Address offset: 0x42108 + 0x1000 * x, (x = 0 to 2)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WRITE_ISS_OVERRIDE
READ_ISS_OVERRIDE
Reset value: 0x0000 0000
rw
rw
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 WRITE_ISS_OVERRIDE: override AMIB write issuing capability
0: normal issuing capability
1: force issuing capability to 1
Bit 0 READ_ISS_OVERRIDE: override AMIB read issuing capability
0: normal issuing capability
1: force issuing capability to 1
2.4.18
AXIMC master x packing functionality register
(AXIMC_Mx_FN_MOD2)
Address offset: 0x42024 + 0x1000 * x, (x = 5 to 6)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BYPASS_MERGE
Reset value: 0x0000 0000
rw
Bits 31:1 Reserved, must be kept at reset value.
RM0442 Rev 7
137/3930
152
Memory and bus architecture
RM0442
Bit 0 BYPASS_MERGE: Disable packing of beats to match the output data width
Unaligned transactions are not realigned to the input data word boundary.
0: normal operation
1: disable packing
2.4.19
AXIMC master x AHB conversion override functionality register
(AXIMC_Mx_FN_MOD_AHB)
Address offset: 0x42028 +0x1000 * x, (x = 5 to 6)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WR_INC_OVERRIDE
RD_INC_OVERRIDE
Reset value: 0x0000 0000
rw
rw
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 WR_INC_OVERRIDE: converts all AHB-Lite write transactions to a series of single beat AXI
transactions, and each AHB-Lite write beat is acknowledged with the AXI buffered write
response.
0: override disabled
1: override enabled
Bit 0 RD_INC_OVERRIDE: converts all AHB-Lite read transactions to a series of single beat AXI
transactions.
0: override disabled
1: override enabled
2.4.20
AXIMC master x read priority register (AXIMC_Mx_READ_QOS)
Address offset: 0x42100 +0x1000 * x, (x = 5 to 6)
Reset value: 0x0000 0004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AR_QOS[3:0]
rw
Bits 31:4 Reserved, must be kept at reset value.
138/3930
RM0442 Rev 7
rw
rw
rw
RM0442
Memory and bus architecture
Bits 3:0 AR_QOS[3:0]: read channel QoS setting
0x0: lowest priority
0xF: highest priority
2.4.21
AXIMC master x write priority register (AXIMC_Mx_WRITE_QOS)
Address offset: 0x42104 + 0x1000 * x, (x = 5 to 6)
Reset value: 0x0000 0004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AW_QOS[3:0]
rw
rw
rw
rw
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 AW_QOS[3:0]: write channel QoS setting
0x0: lowest priority
0xF: highest priority
2.4.22
AXIMC master x issuing capability override functionality register
(AXIMC_Mx_FN_MOD)
Address offset: 0x42108 + 0x1000 * x, (x = 5 to 6)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WRITE_ISS_OVERRIDE
READ_ISS_OVERRIDE
Reset value: 0x0000 0000
rw
rw
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 WRITE_ISS_OVERRIDE: override AMIB write issuing capability
0: normal issuing capability
1: force issuing capability to 1
RM0442 Rev 7
139/3930
152
Memory and bus architecture
RM0442
Bit 0 READ_ISS_OVERRIDE: override AMIB read issuing capability
0: normal issuing capability
1: force issuing capability to 1
2.4.23
AXIMC master x read priority register (AXIMC_Mx_READ_QOS)
Address offset: 0x42100 + 0x1000 * x, (x = 3 to 4)
Reset value: Block 3: 0x0000 0007
Reset value: Block 4: 0x0000 000C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AR_QOS[3:0]
rw
rw
rw
rw
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 AR_QOS[3:0]: read channel QoS setting
0x0: lowest priority
0xF: highest priority
2.4.24
AXIMC master x write priority register (AXIMC_Mx_WRITE_QOS)
Address offset: 0x42104 + 0x1000 * x, (x = 3 to 4)
Reset value: Block 3: 0x0000 0007
Reset value: Block 4: 0x0000 000C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AW_QOS[3:0]
rw
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 AW_QOS[3:0]: write channel QoS setting
0x0: lowest priority
0xF: highest priority
140/3930
RM0442 Rev 7
rw
rw
rw
RM0442
Memory and bus architecture
2.4.25
AXIMC master x packing functionality register
(AXIMC_Mx_FN_MOD)
Address offset: 0x42108 + 0x1000 * x, (x = 3 to 4)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WRITE_ISS_OVERRIDE
READ_ISS_OVERRIDE
Reset value: 0x0000 0000
rw
rw
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 WRITE_ISS_OVERRIDE: override AMIB write issuing capability
0: normal issuing capability
1: force issuing capability to 1
Bit 0 READ_ISS_OVERRIDE: override AMIB read issuing capability
0: normal issuing capability
1: force issuing capability to 1
2.4.26
AXIMC master x read priority register (AXIMC_Mx_READ_QOS)
Address offset: 0x42100 + 0x1000 * x, (x = 7 to 8)
Reset value: Block 7: 0x0000 0008
Reset value: Block 8: 0x0000 0003
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AR_QOS[3:0]
rw
rw
rw
rw
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 AR_QOS[3:0]: read channel QoS setting
0x0: lowest priority
0xF: highest priority
RM0442 Rev 7
141/3930
152
Memory and bus architecture
2.4.27
RM0442
AXIMC master x write priority register (AXIMC_Mx_WRITE_QOS)
Address offset: 0x42104 + 0x1000 * x, (x = 7 to 8)
Reset value: Block 7: 0x0000 0008
Reset value: Block 8: 0x0000 0003
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AW_QOS[3:0]
rw
rw
rw
rw
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 AW_QOS[3:0]: write channel QoS setting
0x0: lowest priority
0xF: highest priority
2.4.28
AXIMC master x issuing capability override functionality register
(AXIMC_Mx_FN_MOD)
Address offset: 0x42108 + 0x1000 * x, (x = 7 to 8)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WRITE_ISS_OVERRIDE
READ_ISS_OVERRIDE
Reset value: 0x0000 0000
rw
rw
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 WRITE_ISS_OVERRIDE: override AMIB write issuing capability
0: normal issuing capability
1: force issuing capability to 1
Bit 0 READ_ISS_OVERRIDE: override AMIB read issuing capability
0: normal issuing capability
1: force issuing capability to 1
142/3930
RM0442 Rev 7
RM0442
Memory and bus architecture
2.4.29
AXIMC long burst capability inhibition register
(AXIMC_FN_MOD_LB)
Address offset: 0x4A02C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FN_MOD_LB
Reset value: 0x0000 0000
rw
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 FN_MOD_LB: controls burst breaking of long bursts
0: long bursts can not be generated at the output of the ASIB
1: long bursts can be generated at the output of the ASIB
2.4.30
AXIMC master x read priority register (AXIMC_Mx_READ_QOS)
Address offset: 0x42100 + 0x1000 * x, (x = 9 to 10)
Reset value: Block 9: 0x0000 000B
Reset value: Block 10: 0x0000 0002
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AR_QOS[3:0]
rw
rw
rw
rw
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 AR_QOS[3:0]: read channel QoS setting
0x0: lowest priority
0xF: highest priority
RM0442 Rev 7
143/3930
152
Memory and bus architecture
2.4.31
RM0442
AXIMC master x write priority register (AXIMC_Mx_WRITE_QOS)
Address offset: 0x42104 + 0x1000 * x, (x = 9 to 10)
Reset value: Block 9: 0x0000 000B
Reset value: Block 9: 0x0000 0002
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AW_QOS[3:0]
rw
rw
rw
rw
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 AW_QOS[3:0]: write channel QoS setting
0x0: lowest priority
0xF: highest priority
2.4.32
AXIMC master x issuing capability override functionality register
(AXIMC_Mx_FN_MOD)
Address offset: 0x42108 + 0x1000 * x, (x = 9 to 10)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WRITE_ISS_OVERRIDE
READ_ISS_OVERRIDE
Reset value: 0x0000 0000
rw
rw
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 WRITE_ISS_OVERRIDE: override AMIB write issuing capability
0: normal issuing capability
1: force issuing capability to 1
Bit 0 READ_ISS_OVERRIDE: override AMIB read issuing capability
0: normal issuing capability
1: force issuing capability to 1
144/3930
RM0442 Rev 7
0x1FFC
0x2000 0x42020
AXIMC_COMP_ID_3
Reserved
RM0442 Rev 7
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AXIMC_COMP_ID_2
Res.
0x1FF8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AXIMC_COMP_ID_1
Res.
0x1FF4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Reset value
0
Reset value
0
Reset value
0
Reset value
1
Reset value
Reset value
Reset value
Reset value
1
Reset value
0
1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
1
0
1
CUST_MOD_NUM[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
REV_AND[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
PREAMBLE[11:8]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
CLASS[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AXIMC_COMP_ID_0
Res.
0x1FF0
AXIMC_PERIPH_ID_3
Res.
0x1FEC
AXIMC_PERIPH_ID_2
Res.
0x1FE8
AXIMC_PERIPH_ID_1
Res.
0x1FE4
AXIMC_PERIPH_ID_0
Res.
0x1FE0
AXIMC_PERIPH_ID_7
Res.
0x1FDC
AXIMC_PERIPH_ID_6
Res.
0x1FD8
AXIMC_PERIPH_ID_5
Res.
0x1FD4
JEP106CON[3:0]
K4COUNT[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AXIMC_PERIPH_ID_4
Res.
0x1FD0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
Res.
Offset
Res.
2.4.33
Res.
RM0442
Memory and bus architecture
AXIMC register map
Table 8. AXIMC register map and reset values
PERIPH_ID_5[7:0]
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
PERIPH_ID_6[7:0]
0
PERIPH_ID_7[7:0]
0
PERIPH_ID_0[7:0]
0
PERIPH_ID_1[7:0]
0
PERIPH_ID_2[7:0]
0
1
0
PREAMBLE[7:0]
1
PREAMBLE[19:12]
0
PREAMBLE[27:20]
1
Reserved
1
145/3930
152
0x43028
0x4302C
0x430FC
146/3930
AXIMC_M1_FN_
MOD_AHB
Reserved
RM0442 Rev 7
Reserved
0
Reserved
READ_ISS_OVERRIDE
1
0
0
BYPASS_MERGE
1
Res.
AW_QOS[3:0]
0
WRTIE_ISS_OVERRIDE
1
Res.
Res.
Reset value
RD_INC_OVERRIDE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AR_QOS[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RD_INC_OVERRIDE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WR_INC_OVERRIDE
Reset value
WR_INC_OVERRIDE
Reset value
Res.
Res.
Res.
Res.
Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AXIMC_M1_FN_MOD2
Res.
0x4210C
- 0x43020
Res.
AXIMC_M0_FN_MOD
Res.
AXIMC_M0_
WRITE_QOS
Res.
0x42104
Res.
AXIMC_M0_
READ_QOS
Res.
0x42100
Res.
0x4202C
0x420FC
Res.
0x43024
AXIMC_M0_FN_
MOD_AHB
Res.
0x42028
Res.
0x42108
Reset value
1
Reset value
BYPASS_MERGE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AXIMC_M0_FN_MOD2
Res.
0x42024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
Res.
Offset
Res.
Memory and bus architecture
RM0442
Table 8. AXIMC register map and reset values (continued)
0
0
0
Reserved
0
0
0
0
0x44104
AXIMC_M2_
WRITE_QOS
Reset value
RM0442 Rev 7
Reset value
Reset value
0
1
0
1
RD_INC_OVERRIDE
AW_QOS[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
1
Reserved
READ_ISS_OVERRIDE
1
0
0
BYPASS_MERGE
0
WRTIE_ISS_OVERRIDE
1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
WR_INC_OVERRIDE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
AR_QOS[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
AW_QOS[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AXIMC_M2_
READ_QOS
Res.
0x44100
Res.
0x4402C
0x440FC
AXIMC_M2_FN_
MOD_AHB
Res.
0x44028
AXIMC_M2_FN_MOD2
Res.
0x44024
Res.
0x4310C
- 0x44020
AXIMC_M1_FN_MOD
Res.
0x43108
AXIMC_M1_
WRITE_QOS
Res.
0x43104
Res.
Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x43100
AXIMC_M1_
READ_QOS
AR_QOS[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Offset
Res.
RM0442
Memory and bus architecture
Table 8. AXIMC register map and reset values (continued)
0
Reset value
0
0
1
0
0
0
Reserved
1
1
147/3930
152
0x46108
AXIMC_M4_FN_MOD
0x4C10C
- 0x47020
148/3930
Reserved
RM0442 Rev 7
Reserved
1
1
1
1
0
0
READ_ISS_OVERRIDE
Reset value
AW_QOS[3:0]
Reset value
WRTIE_ISS_OVERRIDE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AR_QOS[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
1
1
READ_ISS_OVERRIDE
AW_QOS[3:0]
0
WRTIE_ISS_OVERRIDE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
Res.
Reset value
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AR_QOS[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AXIMC_M4_
WRITE_QOS
Res.
0x46104
Res.
AXIMC_M4_
READ_QOS
Res.
0x46100
Res.
0x4510C
0x460FC
Res.
AXIMC_M3_FN_MOD
Res.
AXIMC_M3_
WRITE_QOS
Res.
0x45104
Res.
AXIMC_M3_
READ_QOS
Res.
0x45100
Res.
0x4410C
0x450FC
Res.
0x45108
READ_ISS_OVERRIDE
Reset value
WRTIE_ISS_OVERRIDE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AXIMC_M2_FN_MOD
Res.
0x44108
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
Res.
Offset
Res.
Memory and bus architecture
RM0442
Table 8. AXIMC register map and reset values (continued)
0
0
Reserved
0
0
1
0
0
0
1
Reserved
0
0x48028
0x4802C
0x480FC
AXIMC_M6_FN_
MOD_AHB
Reserved
RM0442 Rev 7
0
Reserved
READ_ISS_OVERRIDE
0
0
0
BYPASS_MERGE
1
Res.
AW_QOS[3:0]
0
WRTIE_ISS_OVERRIDE
1
Res.
Res.
Reset value
RD_INC_OVERRIDE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AR_QOS[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RD_INC_OVERRIDE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WR_INC_OVERRIDE
Reset value
WR_INC_OVERRIDE
Reset value
Res.
Res.
Res.
Res.
Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AXIMC_M6_FN_MOD2
Res.
0x48024
Res.
0x4710C
- 0x48020
AXIMC_M5_FN_MOD
Res.
0x47108
AXIMC_M5_
WRITE_QOS
Res.
0x47104
AXIMC_ M5_
READ_QOS
Res.
0x47100
Res.
0x4702C
0x470FC
AXIMC_M5_FN_
MOD_AHB
Res.
0x47028
Reset value
0
Reset value
BYPASS_MERGE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AXIMC_M5_FN_MOD2
Res.
0x47024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
Res.
Offset
Res.
RM0442
Memory and bus architecture
Table 8. AXIMC register map and reset values (continued)
0
0
0
Reserved
0
0
0
0
Reserved
149/3930
152
0x4A100
150/3930
AXIMC_M8_
READ_QOS
Reset value
RM0442 Rev 7
1
0
Reset value
Reserved
0
0
0
0
FN_MOD_LB
0
FN_MOD[1:0]
AW_QOS[3:0]
1
Res.
AR_QOS[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
1
0
0
READ_ISS_OVERRIDE
AW_QOS[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
WRTIE_ISS_OVERRIDE
Reset value
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
AR_QOS[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
Res.
Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x4A030
0x4A0FC
Res.
AXIMC_M8_FN_MOD_
LB
Res.
0x4910C
0x4A028
Res.
AXIMC_M7_FN_MOD
Res.
AXIMC_M7_
WRITE_QOS
Res.
0x49104
Res.
0x4A02C
AXIMC_M7_
READ_QOS
Res.
0x49100
Res.
0x4810C
0x490FC
Res.
0x49108
AXIMC_M6_FN_MOD
Res.
0x48108
AXIMC_M6_
WRITE_QOS
Res.
0x48104
Res.
Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x48100
AXIMC_M6_
READ_QOS
AR_QOS[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Offset
Res.
Memory and bus architecture
RM0442
Table 8. AXIMC register map and reset values (continued)
0
0
0
0
0
Reset value
1
0
Reserved
0
0
0
Reserved
1
0x4C108
AXIMC_M10_FN_MOD
RM0442 Rev 7
Reset value
0
0
0
0
1
0
READ_ISS_OVERRIDE
Reset value
Res.
AR_QOS[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
0
1
1
READ_ISS_OVERRIDE
AW_QOS[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Reset value
1
WRTIE_ISS_OVERRIDE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
AW_QOS[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AR_QOS[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Reset value
Res.
FN_MOD[1:0]
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
WRTIE_ISS_OVERRIDE
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AXIMC_M10_
WRITE_QOS
Res.
0x4C104
AXIMC_M10_
READ_QOS
Res.
0x4C100
Res.
0x4B10C
0x4C0FC
AXIMC_M9_FN_MOD
Res.
0x4B108
AXIMC_M9_
WRITE_QOS
Res.
0x4B104
AXIMC_M9_
READ_QOS
Res.
0x4B100
Res.
0x4A10C
0x4B0FC
AXIMC_M8_FN_MOD
Res.
0x4A108
Res.
AW_QOS[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AXIMC_M8_
WRITE_QOS
Res.
0x4A104
Res.
Register
Res.
Offset
Res.
RM0442
Memory and bus architecture
Table 8. AXIMC register map and reset values (continued)
1
0
0
0
1
0
0
1
1
0
Reserved
1
Reserved
0
151/3930
152
Memory and bus architecture
RM0442
Refer to Section 2.5 on page 153 for the register boundary addresses.
152/3930
RM0442 Rev 7
RM0442
2.5
Memory organization
2.5.1
Introduction
Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the word’s least significant byte and the highest numbered byte the most
significant.
The access to some part of the address space is master dependent, see Section 2: Memory
and bus architecture for details.
RM0442 Rev 7
153/3930
153
RM0442
2.5.2
Memory map and register boundary addresses
Figure 4. Memory map
0x5FFF FFFF
0x5C00 A3FF
APB5
Secure comm
peripherals /
TZC / TZPC
0x5C00 0000
0x5A00 73FF
0xFFFF FFFF
0xFFFF FFFF
DDR extension
(CA7 only)
or Debug
0xE00D DDFF
CA7 debug peripherals
0xE00C 0000
APB4
DDRC / DDRPHY /
DDRPERFM /
LTDC / USBPHYC
0x5A00 0000
System debug peripherals
0xE004 4000
0x5903 FFFF
CM4 debug peripherals
0xE000 0000
0xE000 0000
DDR
AHB6
USBH / ETH /
SDMMC / MDMA
0x5800 0000
0x570F FFFF
0xC000 0000
0xBFFF FFFF
AXIMC
0x5700 0000
CA7
0xA0027FFF
GIC
0xA002 1000
0xA000 0000
0xA000 0000
STM
0x90FF FFFF
STM 16 MB
0x9000 0000
0x9000 0000
FMC NAND
0x8FFF FFFF
APB-DBG
Coresight
peripherals
0x5400 43FF
0x5400 0000
0x500D DFFF
0x5008 0000
NAND 256 MB
0x8000 0000
0x8000 0000
QUADSPI
AHB5
Backup RAM /
HW accelerators
0x7FFF FFFF
QUADSPI 256 MB
0x7000 0000
0x7000 0000
FMC NOR
0x5002 A3FF
APB3
SYSCFG / LPTIM /
SAI / HDP
0x5002 0000
0x5001 FFFF
AHB4
PWR / RCC / GPIOs
0x5000 0000
0x6000 0000
Peripherals 2
AHB3
HSEM / IPCC /
HW accelerators
0x5000 0000
Peripherals 1
AHB2
DMA / ADC /
SDMMC2
0x4000 0000
RAM aliases
0x2FFF FFFF
0x3000 0000
APB2
CAN / SAI / TIM /
USART
0x4C00 63FF
0x4C00 0000
0x4903 FFFF
0x4800 0000
0x4401 37FF
0x4400 0000
SYSRAM 256 KB
0x2FFC 0000
SYSRAM
0x4001 C3FF
0x4000 0000
0x2000 0000
0x2000 0000
SRAMs
SRAM4 64 KB
SRAM3 64 KB
SRAM2 128 KB
SRAM1 128 KB
0x1000 0000
BOOT
0x0000 0000
APB1
I2C / DAC / TIM /
UART / USART
0x1006 0000
0x1005 0000
0x1004 0000
0x1002 0000
0x1000 0000
0x0FFF FFFF
0x0002 0000
0x3FFF FFFF
0x3800 FFFF
RETRAM 64 KB
0x3800 0000
ROM 128 KB
(CA7)
RETRAM 64KB
(CM4)
0x0001 0000
0x0000 0000
SRAM4 64 KB
SRAM3 64 KB
SRAM2 128 KB
0x3006 0000
0x3005 0000
0x3004 0000
0x3002 0000
SRAM1 128 KB
0x3000 0000
Reserved
154/3930
MSv45733V4
RM0442 Rev 7
RM0442
All the memory map areas that are not allocated to on-chip memories and peripherals are
considered “Reserved”. For the detailed mapping of available memory and register areas,
refer to the following table.
The following table gives the boundary addresses of the peripherals available in the
devices.
Peripheral mapping
Table 9. Register boundary addresses
Bus
CortexA7
internal
APB5
Boundary address
Size (Bytes)
Peripheral
0xA0026000 - 0xA0027FFF
8 KB
GICV
GIC virtual CPU interface (GICV)
0xA0024000 - 0xA0025FFF
8 KB
GICH
GIC virtual interface control, common
(GICH)
0xA0022000 - 0xA0023FFF
8 KB
GICC
GIC CPU Interface (GICC)
0xA0021000 - 0xA0021FFF
4 KB
GICD
GIC distributor (GICD)
0xA0000000 - 0xA0020FFF
132 KB
Reserved
-
0x5C00A400 - 0x5FFFFFFF
65495 KB
Reserved
-
0x5C00A000 - 0x5C00A3FF
1 KB
TAMP
0x5C009400 - 0x5C009FFF
3 KB
Reserved
0x5C009000 - 0x5C0093FF
1 KB
I2C6
I2C registers
0x5C008000 - 0x5C008FFF
4 KB
STGENC
STGEN registers
0x5C007400 - 0x5C007FFF
3 KB
Reserved
0x5C007000 - 0x5C0073FF
1 KB
ETZPC
ETZPC registers
0x5C006000 - 0x5C006FFF
4 KB
TZC
TZC registers
0x5C005000 - 0x5C005FFF
4 KB
BSEC
BSEC registers
0x5C004400 - 0x5C004FFF
3 KB
Reserved
0x5C004000 - 0x5C0043FF
1 KB
RTC
0x5C003400 - 0x5C003FFF
3 KB
Reserved
0x5C003000 - 0x5C0033FF
1 KB
IWDG1
0x5C002400 - 0x5C002FFF
3 KB
Reserved
0x5C002000 - 0x5C0023FF
1 KB
I2C4
0x5C001400 - 0x5C001FFF
3 KB
Reserved
0x5C001000 - 0x5C0013FF
1 KB
SPI6
0x5C000400 - 0x5C000FFF
3 KB
Reserved
0x5C000000 - 0x5C0003FF
1 KB
USART1
RM0442 Rev 7
Peripheral Register map
TAMP registers
-
-
RTC registers
IWDG registers
I2C registers
SPI/I2S registers
USART registers
155/3930
164
RM0442
Table 9. Register boundary addresses (continued)
Bus
APB4
AHB6
AXIM
156/3930
Boundary address
Size (Bytes)
Peripheral
0x5A007400 - 0x5BFFFFFF
32739 KB
Reserved
0x5A007000 - 0x5A0073FF
1 KB
DDRPERFM
DDRPERFM registers
0x5A006000 - 0x5A006FFF
4 KB
USBPHYC
USBPHYC registers
0x5A005000 - 0x5A005FFF
4 KB
STGENR
STGEN registers
0x5A004000 - 0x5A004FFF
4 KB
DDRPHYC
PUBL registers
0x5A003000 - 0x5A003FFF
4 KB
DDRCTRL
DDRCTRL registers
0x5A002400 - 0x5A002FFF
3 KB
Reserved
0x5A002000 - 0x5A0023FF
1 KB
IWDG2
0x5A001400 - 0x5A001FFF
3 KB
Reserved
0x5A001000 - 0x5A0013FF
1 KB
LTDC
0x5A000000 - 0x5A000FFF
4 KB
Reserved
-
0x5800E000 - 0x59FFFFFF
32712 KB
Reserved
-
0x5800D000 - 0x5800DFFF
4 KB
USBH_EHCI
0x5800C000 - 0x5800CFFF
4 KB
USBH_OHCI USBH registers
0x5800A000 - 0x5800BFFF
8 KB
ETH1
Ethernet registers
0x58009000 - 0x58009FFF
4 KB
CRC1
CRC registers
0x58008000 - 0x58008FFF
4 KB
DLYBSD2
DLYB registers
0x58007000 - 0x58007FFF
4 KB
SDMMC2
SDMMC registers
0x58006000 - 0x58006FFF
4 KB
DLYBSD1
DLYB registers
0x58005000 - 0x58005FFF
4 KB
SDMMC1
SDMMC registers
0x58004000 - 0x58004FFF
4 KB
DLYBQS
DLYB registers
0x58003000 - 0x58003FFF
4 KB
QUADSPI
QUADSPI registers
0x58002000 - 0x58002FFF
4 KB
FMC
NOR/PSRAM controller registers
NAND flash controller registers
0x58001000 - 0x58001FFF
4 KB
Reserved
0x58000000 - 0x58000FFF
4 KB
MDMA
0x57100000 - 0x57FFFFFF
15360 KB
Reserved
0x57000000 - 0x570FFFFF
1024 KB
AXIMC
RM0442 Rev 7
Peripheral Register map
-
IWDG registers
LTDC registers
USBH registers
MDMA registers
AXIMC registers
RM0442
Table 9. Register boundary addresses (continued)
Bus
AHB5
APB3
Boundary address
Size (Bytes)
Peripheral
0x54004400 - 0x56FFFFFF
49135 KB
Reserved
0x54004000 - 0x540043FF
1 KB
GPIOZ
0x54003400 - 0x54003FFF
3 KB
Reserved
0x54003000 - 0x540033FF
1 KB
RNG1
0x54002400 - 0x54002FFF
3 KB
Reserved
0x54002000 - 0x540023FF
1 KB
HASH1
0x54001400 - 0x54001FFF
3 KB
Reserved
0x54001000 - 0x540013FF
1 KB
CRYP1(1)
0x54000000 - 0x54000FFF
4 KB
BKPSRAM
-
0x5002A400 - 0x5007FFFF
343 KB
Reserved
-
0x5002A000 - 0x5002A3FF
1 KB
HDP
0x50028400 - 0x50029FFF
7 KB
Reserved
0x50028000 - 0x500283FF
1 KB
DTS
0x50027400 - 0x50027FFF
3 KB
Reserved
0x50027000 - 0x500273FF
1 KB
SAI4
0x50025400 - 0x50026FFF
7 KB
Reserved
0x50025000 - 0x500253FF
1 KB
VREFBUF
0x50024400 - 0x50024FFF
3 KB
Reserved
0x50024000 - 0x500243FF
1 KB
LPTIM5
0x50023400 - 0x50023FFF
3 KB
Reserved
0x50023000 - 0x500233FF
1 KB
LPTIM4
0x50022400 - 0x50022FFF
3 KB
Reserved
0x50022000 - 0x500223FF
1 KB
LPTIM3
0x50021400 - 0x50021FFF
3 KB
Reserved
0x50021000 - 0x500213FF
1 KB
LPTIM2
0x50020400 - 0x50020FFF
3 KB
Reserved
0x50020000 - 0x500203FF
1 KB
SYSCFG
RM0442 Rev 7
Peripheral Register map
GPIO registers
RNG registers
HASH registers
CRYP registers
HDP registers
DTS registers
SAI registers
VREFBUF registers
LPTIM registers
LPTIM registers
LPTIM registers
LPTIM registers
SYSCFG registers
157/3930
164
RM0442
Table 9. Register boundary addresses (continued)
Bus
AHB4
158/3930
Boundary address
Size (Bytes)
Peripheral
0x5000D400 - 0x5001FFFF
75 KB
Reserved
0x5000D000 - 0x5000D3FF
1 KB
EXTI
0x5000C400 - 0x5000CFFF
3 KB
Reserved
0x5000C000 - 0x5000C3FF
1 KB
GPIOK
0x5000B400 - 0x5000BFFF
3 KB
Reserved
0x5000B000 - 0x5000B3FF
1 KB
GPIOJ
0x5000A400 - 0x5000AFFF
3 KB
Reserved
0x5000A000 - 0x5000A3FF
1 KB
GPIOI
0x50009400 - 0x50009FFF
3 KB
Reserved
0x50009000 - 0x500093FF
1 KB
GPIOH
0x50008400 - 0x50008FFF
3 KB
Reserved
0x50008000 - 0x500083FF
1 KB
GPIOG
0x50007400 - 0x50007FFF
3 KB
Reserved
0x50007000 - 0x500073FF
1 KB
GPIOF
0x50006400 - 0x50006FFF
3 KB
Reserved
0x50006000 - 0x500063FF
1 KB
GPIOE
0x50005400 - 0x50005FFF
3 KB
Reserved
0x50005000 - 0x500053FF
1 KB
GPIOD
0x50004400 - 0x50004FFF
3 KB
Reserved
0x50004000 - 0x500043FF
1 KB
GPIOC
0x50003400 - 0x50003FFF
3 KB
Reserved
0x50003000 - 0x500033FF
1 KB
GPIOB
0x50002400 - 0x50002FFF
3 KB
Reserved
0x50002000 - 0x500023FF
1 KB
GPIOA
0x50001400 - 0x50001FFF
3 KB
Reserved
0x50001000 - 0x500013FF
1 KB
PWR
PWR registers
0x50000000 - 0x50000FFF
4 KB
RCC
RCC registers
RM0442 Rev 7
Peripheral Register map
EXTI registers
GPIO registers
GPIO registers
GPIO registers
GPIO registers
GPIO registers
GPIO registers
GPIO registers
GPIO registers
GPIO registers
GPIO registers
GPIO registers
-
RM0442
Table 9. Register boundary addresses (continued)
Bus
AHB3
AHB2
Boundary address
Size (Bytes)
Peripheral
0x4C006400 - 0x4FFFFFFF
65511 KB
Reserved
0x4C006000 - 0x4C0063FF
1 KB
DCMI
0x4C005400 - 0x4C005FFF
3 KB
Reserved
0x4C005000 - 0x4C0053FF
1 KB
CRYP2
(1)
0x4C004400 - 0x4C004FFF
3 KB
Reserved
0x4C004000 - 0x4C0043FF
1 KB
CRC2
0x4C003400 - 0x4C003FFF
3 KB
Reserved
0x4C003000 - 0x4C0033FF
1 KB
RNG2
0x4C002400 - 0x4C002FFF
3 KB
Reserved
0x4C002000 - 0x4C0023FF
1 KB
HASH2
0x4C001400 - 0x4C001FFF
3 KB
Reserved
0x4C001000 - 0x4C0013FF
1 KB
IPCC
0x4C000400 - 0x4C000FFF
3 KB
Reserved
0x4C000000 - 0x4C0003FF
1 KB
HSEM
0x49040000 - 0x4BFFFFFF
48896 KB
Reserved
0x49000000 - 0x4903FFFF
256 KB
OTG
0x48005400 - 0x48FFFFFF
16363 KB
Reserved
0x48005000 - 0x480053FF
1 KB
DLYBSD3
0x48004400 - 0x48004FFF
3 KB
Reserved
0x48004000 - 0x480043FF
1 KB
SDMMC3
0x48003400 - 0x48003FFF
3 KB
Reserved
0x48003000 - 0x480033FF
1 KB
ADC12
0x48002400 - 0x48002FFF
3 KB
Reserved
0x48002000 - 0x480023FF
1 KB
DMAMUX1
0x48001400 - 0x48001FFF
3 KB
Reserved
0x48001000 - 0x480013FF
1 KB
DMA2
0x48000400 - 0x48000FFF
3 KB
Reserved
0x48000000 - 0x480003FF
1 KB
DMA1
Peripheral Register map
DCMI registers
RM0442 Rev 7
CRYP registers
CRC registers
RNG registers
HASH registers
IPCC registers
HSEM registers
OTG registers
DLYB registers
SDMMC registers
ADC registers (for each ADC)
DMAMUX registers
DMA registers
DMA registers
159/3930
164
RM0442
Table 9. Register boundary addresses (continued)
Bus
APB2
160/3930
Boundary address
Size (Bytes)
Peripheral
0x44013800 - 0x47FFFFFF
65458 KB
Reserved
-
0x44011000 - 0x440137FF
10 KB
CANSRAM
-
0x44010400 - 0x44010FFF
3 KB
Reserved
-
0x44010000 - 0x440103FF
1 KB
CCU
0x4400F400 - 0x4400FFFF
3 KB
Reserved
0x4400F000 - 0x4400F3FF
1 KB
FDCAN2
0x4400E400 - 0x4400EFFF
3 KB
Reserved
0x4400E000 - 0x4400E3FF
1 KB
FDCAN1
0x4400D800 - 0x4400DFFF
2 KB
Reserved
-
0x4400D000 - 0x4400D7FF
2 KB
DFSDM1
DFSDM channel y registers (y=0..7)
DFSDM filter x module registers (x=0..5)
0x4400C400 - 0x4400CFFF
3 KB
Reserved
-
0x4400C000 - 0x4400C3FF
1 KB
SAI3
0x4400B400 - 0x4400BFFF
3 KB
Reserved
0x4400B000 - 0x4400B3FF
1 KB
SAI2
0x4400A400 - 0x4400AFFF
3 KB
Reserved
0x4400A000 - 0x4400A3FF
1 KB
SAI1
0x44009400 - 0x44009FFF
3 KB
Reserved
0x44009000 - 0x440093FF
1 KB
SPI5
0x44008400 - 0x44008FFF
3 KB
Reserved
0x44008000 - 0x440083FF
1 KB
TIM17
0x44007400 - 0x44007FFF
3 KB
Reserved
0x44007000 - 0x440073FF
1 KB
TIM16
0x44006400 - 0x44006FFF
3 KB
Reserved
0x44006000 - 0x440063FF
1 KB
TIM15
0x44005400 - 0x44005FFF
3 KB
Reserved
0x44005000 - 0x440053FF
1 KB
SPI4
0x44004400 - 0x44004FFF
3 KB
Reserved
0x44004000 - 0x440043FF
1 KB
SPI1
0x44003400 - 0x44003FFF
3 KB
Reserved
0x44003000 - 0x440033FF
1 KB
USART6
0x44001400 - 0x44002FFF
7 KB
Reserved
0x44001000 - 0x440013FF
1 KB
TIM 8
0x44000400 - 0x44000FFF
3 KB
Reserved
0x44000000 - 0x440003FF
1 KB
TIM 1
RM0442 Rev 7
Peripheral Register map
CCU registers
FDCAN registers
FDCAN registers
SAI registers
SAI registers
SAI registers
SPI/I2S registers
TIM16/TIM17 registers
TIM16/TIM17 registers
TIM15 registers
SPI/I2S registers
SPI/I2S registers
USART registers
TIM1/TIM8 registers
TIM1/TIM8 registers
RM0442
Table 9. Register boundary addresses (continued)
Bus
APB1
Boundary address
Size (Bytes)
Peripheral
0x4001C400 - 0x43FFFFFF
65423 KB
Reserved
0x4001C000 - 0x4001C3FF
1 KB
MDIOS
0x40019400 - 0x4001BFFF
11 KB
Reserved
0x40019000 - 0x400193FF
1 KB
UART8
0x40018400 - 0x40018FFF
3 KB
Reserved
0x40018000 - 0x400183FF
1 KB
UART7
0x40017400 - 0x40017FFF
3 KB
Reserved
0x40017000 - 0x400173FF
1 KB
DAC1
0x40016400 - 0x40016FFF
3 KB
Reserved
0x40016000 - 0x400163FF
1 KB
CEC
0x40015400 - 0x40015FFF
3 KB
Reserved
0x40015000 - 0x400153FF
1 KB
I2C5
0x40014400 - 0x40014FFF
3 KB
Reserved
0x40014000 - 0x400143FF
1 KB
I2C3
0x40013400 - 0x40013FFF
3 KB
Reserved
0x40013000 - 0x400133FF
1 KB
I2C2
0x40012400 - 0x40012FFF
3 KB
Reserved
0x40012000 - 0x400123FF
1 KB
I2C1
0x40011400 - 0x40011FFF
3 KB
Reserved
0x40011000 - 0x400113FF
1 KB
UART5
0x40010400 - 0x40010FFF
3 KB
Reserved
0x40010000 - 0x400103FF
1 KB
UART4
RM0442 Rev 7
Peripheral Register map
MDIOS registers
USART registers
USART registers
DAC registers
HDMI-CEC registers
I2C registers
I2C registers
I2C registers
I2C registers
USART registers
USART registers
161/3930
164
RM0442
Table 9. Register boundary addresses (continued)
Bus
APB1
Boundary address
Size (Bytes)
Peripheral
0x4000F400 - 0x4000FFFF
3 KB
Reserved
0x4000F000 - 0x4000F3FF
1 KB
USART3
0x4000E400 - 0x4000EFFF
3 KB
Reserved
0x4000E000 - 0x4000E3FF
1 KB
USART2
0x4000D400 - 0x4000DFFF
3 KB
Reserved
0x4000D000 - 0x4000D3FF
1 KB
SPDIFRX
0x4000C400 - 0x4000CFFF
3 KB
Reserved
0x4000C000 - 0x4000C3FF
1 KB
SPI3
0x4000B400 - 0x4000BFFF
3 KB
Reserved
0x4000B000 - 0x4000B3FF
1 KB
SPI2
0x4000A400 - 0x4000AFFF
3 KB
Reserved
0x4000A000 - 0x4000A3FF
1 KB
WWDG1
0x40009400 - 0x40009FFF
3 KB
Reserved
0x40009000 - 0x400093FF
1 KB
LPTIM1
0x40008400 - 0x40008FFF
3 KB
Reserved
0x40008000 - 0x400083FF
1 KB
TIM14
0x40007400 - 0x40007FFF
3 KB
Reserved
0x40007000 - 0x400073FF
1 KB
TIM13
0x40006400 - 0x40006FFF
3 KB
Reserved
0x40006000 - 0x400063FF
1 KB
TIM12
0x40005400 - 0x40005FFF
3 KB
Reserved
0x40005000 - 0x400053FF
1 KB
TIM7
0x40004400 - 0x40004FFF
3 KB
Reserved
0x40004000 - 0x400043FF
1 KB
TIM6
0x40003400 - 0x40003FFF
3 KB
Reserved
0x40003000 - 0x400033FF
1 KB
TIM5
0x40002400 - 0x40002FFF
3 KB
Reserved
0x40002000 - 0x400023FF
1 KB
TIM4
0x40001400 - 0x40001FFF
3 KB
Reserved
0x40001000 - 0x400013FF
1 KB
TIM3
0x40000400 - 0x40000FFF
3 KB
Reserved
0x40000000 - 0x400003FF
1 KB
TIM2
1. Check device datasheet for availability.
162/3930
RM0442 Rev 7
Peripheral Register map
USART registers
USART registers
SPDIFRX interface registers
SPI/I2S registers
SPI/I2S registers
WWDG registers
LPTIM registers
TIM13/TIM14 registers
TIM13/TIM14 registers
TIM12 registers
TIM6/TIM7 registers
TIM6/TIM7 registers
TIM2/TIM3/TIM4/TIM5 registers
TIM2/TIM3/TIM4/TIM5 registers
TIM2/TIM3/TIM4/TIM5 registers
TIM2/TIM3/TIM4/TIM5 registers
RM0442
Debugger mapping
Table 10. Debugger Register boundary addresses
Bus
Boundary address
Size (Bytes)
0xE0100000 - 0xFFFFFFFF
523264 KB
0xE00FF000 - 0xE00FFFFF
4 KB
CM4 ROM Table(2)
0xE00DE000 - 0xE00FEFFF
132 KB
Reserved
0xE00DD000 - 0xE00DDFFF
4 KB
CA7_ETM1
0xE00DC000 - 0xE00DCFFF
4 KB
CA7_ETM0
0xE00DA000 - 0xE00DBFFF
8 KB
Reserved
0xE00D9000 - 0xE00D9FFF
4 KB
CA7_CTI1
0xE00D8000 - 0xE00D8FFF
4 KB
CA7_CTI0
0xE00D4000 - 0xE00D7FFF
16 KB
Reserved
0xE00D3000 - 0xE00D3FFF
4 KB
CA7_PMU1
0xE00D2000 - 0xE00D2FFF
4 KB
CA7_DBG1
0xE00D1000 - 0xE00D1FFF
4 KB
CA7_PMU0
0xE00D0000 - 0xE00D0FFF
4 KB
CA7_DBG0
0xE00C1000 - 0xE00CFFFF
60 KB
Reserved
0xE00C0000 - 0xE00C0FFF
4 KB
CA7_ROM
DAPBUS 0xE00A1000 - 0xE00BFFFF
124 KB
Reserved
0xE00A0000 - 0xE00A0FFF
4 KB
STM registers
0xE0095000 - 0xE009FFFF
44 KB
Reserved
0xE0094000 - 0xE0094FFF
4 KB
CTI
0xE0093000 - 0xE0093FFF
4 KB
TPIU
0xE0092000 - 0xE0092FFF
4 KB
ETF
0xE0091000 - 0xE0091FFF
4 KB
Main Funnel
0xE0090000 - 0xE0090FFF
4 KB
Trace Subsystem ROM Table
0xE0084000 - 0xE008FFFF
48 KB
Reserved
0xE0083000 - 0xE0083FFF
4 KB
SWO
0xE0082000 - 0xE0082FFF
4 KB
TSGEN1 non-secure PORT
0xE0081000 - 0xE0081FFF
4 KB
DBG_MCU
0xE0080000 - 0xE0080FFF
4 KB
DAP ROM Table
0xE0044000 - 0xE007FFFF
240 KB
Reserved
0xE0043000 - 0xE0043FFF
4 KB
CM4 CTI(2)
0xE0042000 - 0xE0042FFF
4 KB
Reserved
0xE0041000 - 0xE0041FFF
4 KB
CM4 ETM(2)
(1)
RM0442 Rev 7
Peripheral
Reserved
163/3930
164
RM0442
Table 10. Debugger Register boundary addresses (continued)
Bus
Boundary address
Size (Bytes)
0xE000F000 - 0xE0040FFF
200 KB
Reserved
0xE000E000 - 0xE000EFFF
4 KB
CM4 SCS(2)
DAPBUS 0xE0003000 - 0xE000DFFF
44 KB
Reserved
0xE0002000 - 0xE0002FFF
4 KB
CM4 FPB(2)
0xE0001000 - 0xE0001FFF
4 KB
CM4 DWT(2)
0xE0000000 - 0xE0000FFF
4 KB
CM4 ITM(2)
0x500DE000 - 0x53FFFFFF
64648 KB
Reserved
0x500DD000 - 0x500DDFFF
4 KB
CA7_ETM1
0x500DC000 - 0x500DCFFF
4 KB
CA7_ETM0
0x500DA000 - 0x500DBFFF
8 KB
Reserved
0x500D9000 - 0x500D9FFF
4 KB
CA7_CTI1
0x500D8000 - 0x500D8FFF
4 KB
CA7_CTI0
0x500D4000 - 0x500D7FFF
16 KB
Reserved
0x500D3000 - 0x500D3FFF
4 KB
CA7_PMU1
0x500D2000 - 0x500D2FFF
4 KB
CA7_DBG1
0x500D1000 - 0x500D1FFF
4 KB
CA7_PMU0
0x500D0000 - 0x500D0FFF
4 KB
CA7_DBG0
0x500C1000 - 0x500CFFFF
60 KB
Reserved
0x500C0000 - 0x500C0FFF
4 KB
CA7_ROM
0x500A1000 - 0x500BFFFF
124 KB
Reserved
0x500A0000 - 0x500A0FFF
4 KB
STM registers
0x50095000 - 0x5009FFFF
44 KB
Reserved
0x50094000 - 0x50094FFF
4 KB
CTI
0x50093000 - 0x50093FFF
4 KB
TPIU
0x50092000 - 0x50092FFF
4 KB
ETF
0x50091000 - 0x50091FFF
4 KB
Funnel
0x50090000 - 0x50090FFF
4 KB
Trace Subsystem ROM Table
0x50084000 - 0x5008FFFF
48 KB
Reserved
0x50083000 - 0x50083FFF
4 KB
SWO
0x50082000 - 0x50082FFF
4 KB
TSGEN1
0x50081000 - 0x50081FFF
4 KB
DBGMCU
0x50080000 - 0x50080FFF
4 KB
DAP ROM Table
(1)
Debug
APB(3)
1. Accessible by debugger only.
2. Also accessible locally by Cortex®-M4.
3. Accessible by Debugger, Cortex®-M4 and Cortex®-A7
164/3930
RM0442 Rev 7
Peripheral
RM0442
Boot and security and OTP control (BSEC)
3
Boot and security and OTP control (BSEC)
3.1
Introduction
The BSEC (boot and security and OTP control) is intended to control an OTP (one time
programmable) fuse box, used for on-chip non-volatile storage for device configuration and
security parameters.
3.2
BSEC main features
•
32-bit APB4 interface
•
4096 OTP bits (with 3072 effective bits)
•
Valid power-supply pwrok input so that OTP is only operated within a VDD/VDD1 valid
range
•
Scratch register for communication with external agent and to store boot parameters
•
Feature locking mechanism: BSEC provides 15 hardware signals, controlled by OTP to
disable specific SoC features for product differentiation
•
JTAG SOC interface via BSEC_JTAGIN and BSEC_JTAGOUT registers for
communication channel to JTAG TAP controller.
•
Two OTP regions designated as lower OTP (1 Kbits) and upper OTP (2 Kbits) having
different properties
•
Lower OTP bits (1 Kbits), with 2:1 redundancy, are intended to store:
–
Device configuration: BSEC OTP mode and device features
–
Boot parameters
–
Engineering data and analog trim
–
Public root key (256 bits)
All basic security features, including secure Boot with code authentication, are
supported only with lower OTP region.
•
Upper OTP bits (2 Kbits) with 6 bits per 32-bit word ECC support, are intended to store
security sensitive information
–
ST secret keys
–
OEM secrets
Upper OTP should only be treated by 32-bit words
•
Improved resistance to hardware attacks by clock and power glitches during OTP read
•
OTP bits are always read with disturbcheck.
Every OTP word read is internally compared to an internal reference level. The
disturbcheck information is provided to BSEC to qualify the OTP word value.
•
Global programming locking by sticky bits
•
Permanent OTP program locking per word
•
OTP word programming lock by sticky bits during Boot
•
Shadow OTP registers can be individually write locked by sticky bits during Boot
•
Shadow OTP registers can be individually read locked by sticky bits during Boot (to
prevent reloading)
•
Arm® TrustZone® awareness applicable to:
RM0442 Rev 7
165/3930
189
Boot and security and OTP control (BSEC)
–
BSEC control registers
–
BSEC shadow registers from lower OTP region (words 0 to 31)
–
•
•
3.3
RM0442
BSEC shadow registers from upper OTP region (words 32 to 95)
®
Arm CoreSight™ debug authentication interface with six signals:
–
dbgen (debug enable)
–
devicen (external debug enable)
–
niden (non-invasive debug enable)
–
spiden (secure privilege invasive debug enable)
–
spniden (secure privilege non-invasive debug enable)
–
dbgswenable (self hosted debug enable)
Up to 256 hardware signals hws[255:0] for analog trim, factory settings and SoC RAM
repair
BSEC functional description
BSEC provides an interface to the OTP (also known as anti-fuse macro) containing 3072
useful bits. BSEC also provides several registers used by the Boot process as well as
mechanisms to prevent access to security sensitive information.
3.3.1
BSEC block diagram
Figure 5. BSEC block diagram
clk
pdn
rstn
other signals
BSEC
SoC
system
control
APB
pwrok
rstcore_n
fuseok
otp_data_valid
Upper
OTP
shadow
register
SAFMEM
sequencer
(2 flexible
memories)
Lower
OTP
shadow
register
Read
initialization
of flexible
memories
APB
interface
decoder
TrustZone
Control
and
security
logic
Program /
read
flexible
memories
jtagin[15:0]
jtagout[15:0]
fdis[14:0]
hws[255:0]
dbgen
niden
spiden
spniden
deviceen
dbgswenable
cfgsdisable
cp15sdisable[1:0]
hdpen
166/3930
RM0442 Rev 7
SAFMEM
interface
SoC
CoreSight
authentication
interface
Cortex-A7
HDP MSv46603V4
RM0442
3.3.2
Boot and security and OTP control (BSEC)
Interface to OTP
OTP bits are grouped in words of 32 bits each and are organized in two regions:
Note:
•
the lower region: 32 words of 32 bits (lower 2 Kbits), using a 2:1 redundancy. SoC and
Boot configuration parameters, engineering data and public root key hash are stored in
this lower region.
•
the upper region: 64 words of 32 bits (2 Kbits upper half), using ECC scheme (32 bits
encoded into 38 bits). Security sensitive parameters such as secret keys are stored in
this upper region.
OTP bits are initially set to 0 and can be programmed once to one.
Lower OTP words, using 2:1 redundancy, can be bitwise programmed in several operations
Upper OTP words, using internal ECC, must be programmed in a single operation as a bulk
32 bits data.
The OTP bits are not directly accessible by the CPU. Instead the CPU must access shadow
registers that contain copies of the OTP useful bits.
There are 96 shadow registers: BSEC_OTP_DATA0 to BSEC_OTP_DATA95.
These 32-bit registers are copies of actual OTP bits. Redundancy and ECC are made
transparent to the user. BSEC_OTP_DATAx are also referred to OTP word #x in this
document.
There are two possibilities to udpate the shadow registers:
•
a system reset, where BSEC automatically copies the whole set of OTP useful bits to
the shadow registers.
•
an OTP read operation requested by the CPU, used after an OTP programming
operation to update the corresponding shadow register.
The following OTP useful bits have a special meaning for BSEC:
3.3.3
•
word #0: bits 0 to 6 reserved to determine OTP security mode
•
word #1: bits 0 to 15 used to control feature disabling
•
words #16 to word #23 are connected to the SoC signals hws[255:0].
These signals are either:
–
connected to SoC peripherals (example: for analog peripheral factory trimming, or
for memory repair).
–
left unconnected if OTP bits are only used by software (see Section 4: OTP
mapping (OTP)).
OTP security modes
OTP word#0 bits 0 to 6 (with their potential disturbed state) are used to determine the OTP
security mode.
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The following OTP security modes are available:
•
•
OTP-SECURED, including sub-modes, according to OTP word#0 as described in
Table 11:
–
open_device
–
closed_device
OTP-INVALID
–
In this state the upper OTP shadow registers are cleared and not accessible, the
lower OTP shadow registers are not accessible, BSEC control interface is
read/write accessible to secure only.
The OTP mode is made visible to software by register BSEC_OTP_STATUS.
Table 11. OTP modes definition
BSEC_OTP_DATA0
[6:0]
OTP mode
BSEC_OTP_STATUS
SECURE
BSEC_OTP_STATUS
INVALID
OTP-SECURED
open_device
1
0
OTP-SECURED
closed_device
1
0
OTP-INVALID
x
1
0xxx1x1
01x1xxx
0xx11xx
01xxxx1
1xxx1x1
11x1xxx
1xx11xx
11xxxx1
All other values
Note:
The OTP mode is computed from BSEC_OTP_DATA0[6:0] only if
BSEC_OTP_DISTURBED[0] is equal to zero. Otherwise the OTP mode is forced to
OTP-INVALID.
3.3.4
Automatic OTP load on system-reset
On a system-reset, BSEC automatically updates all shadow registers. The OTP mode is
determined during this phase.
For OTP-SECURED mode, all OTP words are read and BSEC_OTP_DATA0 to
BSEC_OTP_DATA95 are updated.
For OTP-INVALID mode, only BSEC_OTP_DATA0 to BSEC_OTP_DATA31 are updated.
BSEC_OTP_DATA32 to BSEC_OTP_DATA95
are set to 0.
BSEC_OTP_STATUS, BSEC_OTP_DISTURBEDx and BSEC_OTP_ERRORx registers are
also updated.
fuseok signal is asserted at the end of this phase. This signal is used to release the reset to
the SoC.
Note:
168/3930
the OTP word reading starts from word 0, in order for the BSEC to determine the OTP mode
from the beginning.
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Boot and security and OTP control (BSEC)
Figure 6. Power-on and initial read timing diagram
System power-up sequence
Power ranking
VDD
>Vdd_min
>Vdd_core_min
VDD_CORE
pwrok
rstcore_n
pclk
(~64 MHz )
BSEC / SAFMEM interface
safmem_pdn
>1ȝs
safmem_resetn
safmem_clk
~100ȝs to read SAFMEM
fuseok
SoC reset sequence
Mrepair_done
MEM repair
CPU Boot
(CPU_resetn)
MSv46604V1
3.3.5
Note:
OTP words status
•
BSEC_OTP_DISTURBEDx registers (x = 0...2) provide the disturbed status for each
OTP word. Any bit set to 1 means that the last reading of the corresponding word has
been disturbed. Abnormal reading conditions in circuitry decoding and voltages reading
have been detected.
•
BSEC_OTP_ERRORx registers (x = 0...2) provide error status for each OTP word.
Any bit set to 1 means that the last read operation of the word concerned revealed a
redundancy or ECC check error.
•
BSEC_OTP_WRLOCKEDx registers (x = 0...2) provide a permanent write lock
status for each OTP word. Any bit set to 1 means that the corresponding word is
permanently locked for writing.
All status registers are updated during the initial read, but the disturbed and error status
registers are also updated after each OTP read operation.
The first 32 OTP words implement a scheme to improve OTP robustness against hardware
attacks during read as follows: Spare bits 32 to 37 are intended to support ECC and are not
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used by 2:1 redundancy. They are therefore written with a simple pattern (for example OTP
word address on 5 bits with even parity on the 6th bit).This pattern is checked during every
OTP read. If the value read on bit 32 to 37 does not match the expected value, a disturbed
information is reported to BSEC_OTP_DISTURBED0 register.
3.3.6
OTP operations
BSEC is clocked by PCLK clock source (single clock for functional and interface registers).
An OTP word reading, writing (programming) or locking is called an OTP operation.
One OTP operation is performed via the BSEC_OTP_CONTROL register. It starts when the
software writes a valid request to BSEC_OTP_CONTROL register and when no other
operation is on going (an OTP operation cannot start until the previous one is finished).
Specific read, programming or permanent write lock operations are detailed below.
OTP read
A read operation consists in updating one of BSEC_OTP_DATA0 to BSEC_OTP_DATA95
registers with the corresponding word from OTP word.
To trigger a read operation, the software must set BSEC_OTP_CONTROL register with the
word number given in ADDR field and with PROG bit set to 0.
The software can check the BUSY bit from the BSEC_OTP_STATUS register: Once
cleared, this BUSY bit indicates that the read operation is complete.
When the read operation is finished, the BSEC state machine updates the “disturbed” and
“error” status registers.
BSEC parameters depending on OTP content, are also updated when the corresponding
OTP words are read. The OTP mode is updated when a read operation of the word 0 is
performed.
Note:
In OTP-INVALID mode, or if bit OTP in BSEC_OTP_LOCK register is set, words 32 to 95
cannot be read. The corresponding shadow registers are not modified.
OTP programming
A programming operation consists in programming one or several bits of an OTP word to
one.
OTP word bits may be incrementally programmed to one but bits programmed to one can
not be written to zero.
Lower OTP words are bitwise programmable and can be programmed incrementally to
one's, upper OTP words have to be programmed in a single operation because of ECC
encoding.
To trigger a programming operation, the two following steps are required:
•
set the word value to write in the BSEC_OTP_WRDATA register
•
set the BSEC_OTP_CONTROL register with:
–
word number given in ADDR field
–
PROG bit set to 1
–
LOCK bit set to 0.
The software checks then the BUSY bit from the BSEC_OTP_STATUS register: Once
cleared, this BUSY bit indicates that the write operation is complete.
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In the same register, the progfail bit is set if the write operation has failed.
Note:
a programming operation to an OTP word does not update the corresponding shadow
register. If needed, the software can update the shadow register with a read operation.
In OTP-INVALID mode, the upper OTP (words 32 to 95) can not be programmed,
regardless of bit GPLOCK in BSEC_OTP_LOCK register and regardless of registers
BSEC_OTP_SPLOCK2/3.
OTP permanent write lock
A permanent write lock operation consists in forcing an OTP word to be permanently
write-locked and not programmable.
For permanent write lock of an OTP word, the software must perform the same sequence as
a normal programming operation with bit LOCK in BSEC_OTP_CONTROL register, with
field ADDR in BSEC_OTP_CONTROL register and with BSEC_OTP_WRDATA register
(see Table 12). After permanent lock programming, it is required to update
BSEC_OTP_WRLOCKEDx registers with OTP content. In order to do this, the software
must perform a word read with LOCK bit set and word address provided in
BSEC_OTP_CONTROL register.
Table 12. OTP permanent write lock
OTP word to be
locked
BSEC control register value
Comment
ADDR[6:0]
WRDATA[31:0]
0
0x00
0x0000 0003
1
0x00
0x0000 000C
...
...
...
7
0x00
0x0000 C000
8
0x01
0x0000 0003
...
...
...
15
0x01
0x0000 C000
16
0x02
0x0000 0003
...
...
...
31
0x03
0x0000 C000
32
0x04
0x0000 0001
33
0x04
0x0000 0002
...
...
...
47
0x04
0x0000 8000
48
0x05
0x0000 0001
...
...
...
63
0x05
0x0000 8000
...
...
...
95
0x07
0x0000 8000
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lower OTPs
Use 1 bit per word for
upper OTPs
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3.3.7
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JTAG registers
The BSEC_JTAGIN and BSEC_JTAGOUT registers are two 16-bit registers used to
communicate between software and JTAG SoC interface. This interface is used during Boot
as communication channel to the external JTAG TAP controller.
3.3.8
BSEC lock registers
BSEC_OTP_LOCK register is used to lock access to security sensitive areas with sticky
bits. The locks are active until the next system-reset (see Section 3.6.5: BSEC OTP lock
configuration register (BSEC_OTP_LOCK)).
3.3.9
Debug control
The software controls the scope of the Debug by BSEC_DENABLE register. The access to
this register can be locked until next system-reset with bit DENREG in BSEC_OTP_LOCK
register.
BSEC_DENABLE is driving hardware signals to the SoC (such as CoreSight authentication
interface and other specific control listed in Table 13).
For more information, see Section 64: Debug support (DBG).
BSEC_DENABLE default values depends on BSEC OTP mode as shown in Table 13.
Table 13. BSEC_DENABLE default values after reset
OTPSECURED
open_device
OTP-SECURED
closed_device
OTPINVALID
dbgen
1
0
0
CoreSight authentication
niden
1
0
0
CoreSight authentication
spiden
0
0
0
CoreSight authentication
spniden
0
0
0
CoreSight authentication
deviceen
1
0
0
CoreSight authentication
dbgswenable
0
0
0
CoreSight authentication
hdpen
0
0
0
Hardware debug port tracing
cfgsdisable
0
0
0
Disable some of Cortex®-A7
GIC secure access
0b00
0b00
0b00
Disable some of Cortex®-A7
CP15 secure access
Signal
cp15sdisable[1:0]
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3.3.10
Boot and security and OTP control (BSEC)
Sticky lock register
Three sticky lock registers are used to control the reload of shadow registers, at OTP word
granularity:
3.4
•
BSEC_SRLOCKx (x = 0..2) to prevent reloading of selected shadow registers until next
system-reset.
•
BSEC_SWLOCKx (x = 0..2) to lock the write to selected shadow register from APB
until next system-reset.
•
BSEC_SPLOCKx (x = 0..2) to prevent programming of selected OTP words until next
system-reset.
OTP layout
Lower OTP words (1 Kbits)
The lower OTP bits are stored in shadow registers BSEC_OTP_DATA0 to
BSEC_OTP_DATA31 and used for general purpose and non-secret data.
These OTP are protected by a 2:1 redundancy implemented with consecutive even/odd bits.
The specific bits impacting hardware such as OTP modes, engineering, trim and memory
repair are located in: CFG0, CFG1 and 8 other words (HW0 to HW7).
Upper OTP words (2 Kbits)
The upper OTP words are stored in shadow registers BSEC_OTP_DATA32 to
BSEC_OTP_DATA95 and are reserved to store security sensitive information (secrets keys,
certificate, RMA key). These words may also store public non-volatile information.
These upper OTP bits can be used during the Boot process to support advanced security
services such as secure secret provisioning (SSP), encrypted Boot or secure storage.
The upper OTP words are protected by ECC and must be used with 32-bit word granularity.
3.4.1
DMA requests
BSEC does not support DMA hardware interface.
3.4.2
TrustZone awareness
BSEC is TrustZone aware. All APB register read and write accesses are checked for
permission. Table 14 and Table 15 describe the permission rules depending on OTP mode
and register type.
If permission check fails:
•
write access is ignored and SLVERR is signaled on APB bus.
•
read access returns zeros and SLVERR is signaled on APB bus.
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Table 14. Write access permissions
Control registers(1)
OTP mode
Lower OTP shadow registers Upper OTP shadow registers
APB secure
APB
non-secure
APB secure
APB
non-secure
APB secure
APB
non-secure
OTP-SECURED
Yes
No
Yes
No
Yes
No
OTP-INVALID
No
No
No
No
No
No
1. BSEC control registers are any BSEC registers except BSEC_OTP_DATA0 to BSEC_OTP_DATA95.
Table 15. Read access permissions
Control registers(1)
OTP mode
Lower OTP shadow registers Upper OTP shadow registers
APB secure
APB
non-secure
APB secure
APB
non-secure
APB secure
APB
non-secure
OTP-SECURED
Yes
Yes
Yes
Yes
Yes
No
OTP-INVALID
Yes
No
No
No
No
No
1. BSEC control registers are any BSEC registers except BSEC_OTP_DATA0 to BSEC_OTP_DATA95.
3.4.3
BSEC clocking and initialization
BSEC has a single clock domain (PCLK).
3.5
•
During read and programming OTPs, PCLK frequency must be ≤ 67 MHz.
•
During write to shadow registers, PCLK frequency must be ≤ 67 MHz.
•
During all other operations, PCLK frequency is not restricted but it is recommended to
keep PCLK ≤ 67 MHz for all operations (to avoid frequency changes).
•
BSEC is enforcing the correct sequencing wrt signals: CLK, PDN, and RESETN during
power-up and power-down sequences.
BSEC interrupts
BSEC does not support any interrupt.
3.6
BSEC registers
The peripheral registers are accessed by words (32-bit).
Any write access to read-only registers are silently ignored.
Any attempt to modify locked registers (locked by sticky locks or by lock bits) are silently
ignored.
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Boot and security and OTP control (BSEC)
3.6.1
BSEC OTP configuration register (BSEC_OTP_CONFIG)
Address offset: 0x000
Reset value: 0x0000 000E
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TREAD[1:0]
rw
rw
PRGWIDTH[3:0]
rw
rw
PWRU
P
FRC[1:0]
rw
rw
rw
rw
rw
Bits 31:9 Reserved, must be kept at reset value.
Bits 8:7 TREAD[1:0]: set OTP reading current level (default = 0b00)
Bits 6:3 PRGWIDTH[3:0]: OTP programming pulse width (default = 0b0001)
Bits 2:1 FRC[1:0]: OTP clock frequency range selection
00: 10 MHz ≤ frequency ≤ 20 MHz
01: 20 MHz ≤ frequency ≤ 30 MHz
10: 30 MHz ≤ frequency ≤ 45 MHz
11: 45 MHz ≤ frequency ≤ 67 MHz
Note: 0b11 is used by default. OTP initial read is always using an internal OSC with 64 MHz
max frequency. Reading OTP at a lower frequency than the range programmed by
FRC[1:0] is possible.
Bit 0 PWRUP: OTP power-up control
0: OTP powered down
1: OTP powered up
Note: After the power-on initial read of OTP, BSEC powers down OTP. PWRUP bit is then
cleared.
Prior to any read or programming operation, OTP must be powered up again by setting
PWRUP bit.
OTP read is qualified by pwrok input signal, which indicates that VDD and VDD1
supplies are in valid range.
3.6.2
BSEC OTP control register (BSEC_OTP_CONTROL)
Address offset: 0x004
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
6
5
4
3
2
1
0
rw
rw
rw
15
14
13
12
11
10
9
8
7
Res.
Res.
Res.
Res.
Res.
Res.
LOCK
PROG
Res.
rw
rw
ADDR[6:0]
rw
rw
rw
rw
Bits 31:10 Reserved, must be kept at reset value.
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Bit 9 LOCK: OTP permanent word lock control
0: OTP normal word programming/read
1: OTP permanent write lock word programming/read
Bit 8 PROG: OTP operation control
0: OTP read operation
1: OTP program operation
Bit 7 Reserved, must be kept at reset value.
Bits 6:0 ADDR[6:0]: OTP word address
Actual OTP word address.
Words address are from 0 to 95 for BSEC
Note: the actual OTP word address is adjusted according to the redundancy or ECC scheme.
3.6.3
BSEC OTP write data register (BSEC_OTP_WRDATA)
Address offset: 0x008
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WRDATA[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
WRDATA[15:0]
rw
rw
Bits 31:0 WRDATA[31:0]: OTP write data
3.6.4
BSEC OTP status register (BSEC_OTP_STATUS)
Address offset: 0x00C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
PWR
ON
PROG
FAIL
BUSY
IN
VALID
Res.
SEC
URE
r
r
r
r
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Bits 31:11 Reserved, must be kept at reset value.
Bits 10:8 Reserved, must be kept at reset value.
Bits 7:6 Reserved, must be kept at reset value.
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Bit 5 PWRON: OTP power status
0: OTP in power off
1: OTP in power on
Note: used to poll pwrok signal value
Bit 4 PROGFAIL: last programming status
0: OTP successful last programming
1: OTP failed last programming
Bit 3 BUSY: OTP operation status
0: OTP idle
1: OTP operation on going
Note: bit polling is used to determine operation completion.
Bit 2 INVALID: OTP invalid mode
0: OTP mode is not OTP-INVALID
1: OTP mode is OTP-INVALID
Bit 1 Reserved, must be kept at reset value.
Bit 0 SECURE: OTP secured mode
0: OTP mode is not OTP-SECURED
1: OTP mode is OTP-SECURED
Note:
The reset value of SECURE and INVALID bits depends on OTP mode.
Note:
The lowest bits SECURE and INVALID must be used to identify the OTP mode instead of
reading shadow register BSEC_OTP_DATA0. Precedence is INVALID > SECURE.
3.6.5
BSEC OTP lock configuration register (BSEC_OTP_LOCK)
Address offset: 0x010
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
GP
LOCK
Res.
DEN
REG
ROM
LOCK
OTP
rs
rs
rs
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rs
Bits 31:5 Reserved, must be kept at reset value.
Bit 4 GPLOCK: programming sticky lock
0: programming allowed
1: programming disabled until next system reset
Bit 3 Reserved, must be kept at reset value.
Bit 2 DENREG: debug enable register sticky lock
0: BSEC_DENABLE register not locked
1: BSEC_DENABLE register locked until next system reset
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Bit 1 ROMLOCK: Upper ROM region read lock
0: Upper ROM region is accessible
1: Upper ROM region is no more accessible until next system reset
The upper ROM region is accessible only in OTP-SECURED open and OTP-SECURED
closed modes and ROMLOCK bit is relevant only in these modes.
Bit 0 OTP: upper OTP read lock
0: upper OTP not locked
1: upper OTP cannot be reloaded until next system reset
3.6.6
BSEC debug configuration register (BSEC_DENABLE)
Address offset: 0x014
Reset value: 0x0000 0000
Note:
reset value depends on OTP secure mode according toTable 13: BSEC_DENABLE default
values after reset on page 172.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
DBG
SWEN
ABLE
CFGS
DIS
ABLE
SPID
EN
HDPEN
DE
VICE
EN
NIDEN
DBG
EN
Res.
rw
rw
rw
rw
rw
rw
rw
Res.
Res.
Res.
Res.
CP15SDISABLE SPNID
[1:0]
EN
rw
rw
rw
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 DBGSWENABLE: control self hosted debug enable with signal dbgswenable
0: Software access to all debug components is disabled
1: Software access to all debug components is enabled
Bit 9 CFGSDISABLE: write access to secure GIC registers disable with signal cfgsdisable
0: no effect, all GIC registers are accessible
1: Disable write access to some secure GIC registers
Bits 8:7 CP15SDISABLE[1:0]: write access to some secure Cortex®-A7 CP15 registers disable
CPDISABLE[0] applies to CPU0. CPDISABLE[1] applies to CPU1.
0: All CP15 registers are accessible
1: Disable write access to some secure CP15 registers into Cortex®-A7 corresponding CPU
Bit 6 SPNIDEN: secure privilege non-invasive debug enable with signal spiden
0: secure privilege non-invasive debug disabled
1: secure privilege non-invasive debug enabled
Bit 5 SPIDEN: secure privilege invasive debug enable with signal spniden
0: secure privilege invasive debug disabled
1: secure privilege invasive debug enabled
Bit 4 HDPEN: hardware debug port enable with signal hdpen
0: hardware debug port disabled
1: hardware debug port enabled
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Bit 3 DEVICEEN: controls access to debug component via external debug port by signal deviceen
0: disabled
1: enabled
Bit 2 NIDEN: non-invasive debug enable with signal niden
0: non-invasive debug disabled
1: non-invasive debug enabled
Bit 1 DBGEN: debug enable with signal dbgen
0: disabled
1: enabled
Bit 0 Reserved, must be kept at reset value.
3.6.7
BSEC OTP disturbed status register x (BSEC_OTP_DISTURBEDx)
BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to
BSEC_OTP_DATA31 (lower 1 Kbits OTP).
BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to
BSEC_OTP_DATA63.
BSEC_OTP_DISTURBED2 is used to report disturbed state of BSEC_OTP_DATA64 to
BSEC_OTP_DATA95.
Address offset: 0x01C + 0x004 * x, (x = 0 to 2)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DIS[31:16]
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
DIS[15:0]
r
r
r
r
r
r
r
r
r
Bits 31:0 DIS[31:0]: disturbed status of the corresponding OTP word
0: OTP word has been read correctly
1: OTP word is disturbed, either because of a read with disturbcheck failed or because the
spare ECC bits [37:32] for words 0 to 31 do not match expected value. It may result from a
possible hardware attack.
Note: ECC bits resilience against hardware attacks is applied only to lower OTP region.
RM0442 Rev 7
179/3930
189
Boot and security and OTP control (BSEC)
3.6.8
RM0442
BSEC OTP error status register x (BSEC_OTP_ERRORx)
BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to
BSEC_OTP_DATA31 (lower 1 Kbits OTP which are protected by 2:1 redundancy).
BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to
BSEC_OTP_DATA63 which are protected by 6-bit ECC.
BSEC_OTP_ERROR2 is used to report error state of BSEC_OTP_DATA64 to
BSEC_OTP_DATA95 which are protected by 6-bit ECC.
Address offset: 0x034 + 0x004 * x, (x = 0 to 2)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ERR[31:16]
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
ERR[15:0]
r
r
Bits 31:0 ERR[31:0]: error status of the correspond OTP word
0: OTP word has been read correctly
1: OTP word is erroneous, either because 2:1 redundancy has failed for words 0 to 31 or
because ECC check has failed for words 32 to 95.
3.6.9
BSEC OTP lock status register x (BSEC_OTP_WRLOCKEDx)
BSEC_OTP_WRLOCKED0 is used to report permanent write lock of BSEC_OTP_DATA0 to
BSEC_OTP_DATA31.
BSEC_OTP_WRLOCKED1 is used to report permanent write lock of BSEC_OTP_DATA32
to BSEC_OTP_DATA63.
BSEC_OTP_WRLOCKED2 is used to report permanent write lock of BSEC_OTP_DATA64
to BSEC_OTP_DATA95.
Permanent write lock requires a programming sequence to lock a word (see
section:Section 3.3.6: OTP operations on page 170).
Address offset: 0x04C + 0x004 * x, (x = 0 to 2)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WRLOCK[31:16]
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
WRLOCK[15:0]
180/3930
r
r
RM0442 Rev 7
RM0442
Boot and security and OTP control (BSEC)
Bits 31:0 WRLOCK[31:0]: permanent word lock status of the correspond OTP word
0: OTP word not locked
1: OTP word permanently locked
3.6.10
BSEC OTP sticky programming lock register x
(BSEC_OTP_SPLOCKx)
BSEC_OTP_SPLOCK0 is used to lock the programming of BSEC_OTP_DATA0 to
BSEC_OTP_DATA31 until next system-reset
BSEC_OTP_SPLOCK1 is used to lock the programming of BSEC_OTP_DATA32 to
BSEC_OTP_DATA63 until next system-reset
BSEC_OTP_SPLOCK2 is used to lock the programming of BSEC_OTP_DATA64 to
BSEC_OTP_DATA95 until next system-reset
Attempt to sticky program locked OTP word are silently ignored.
Address offset: 0x064 + 0x004 * x, (x = 0 to 2)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SPLOCK[31:16]
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rs
rs
rs
rs
rs
rs
rs
SPLOCK[15:0]
rs
rs
rs
rs
rs
rs
rs
rs
rs
Bits 31:0 SPLOCK[31:0]: lock programming for the OTP word until next power-on reset
0: OTP word not locked
1: OTP word locked for programming
RM0442 Rev 7
181/3930
189
Boot and security and OTP control (BSEC)
3.6.11
RM0442
BSEC OTP shadow write sticky lock register x
(BSEC_OTP_SWLOCKx)
BSEC_OTP_SWLOCK0 is used to prevent writing to BSEC_OTP_DATA0 to
BSEC_OTP_DATA31 until next system-reset.
BSEC_OTP_SWLOCK1 is used to prevent writing to BSEC_OTP_DATA32 to
BSEC_OTP_DATA63 until next system-reset.
BSEC_OTP_SWLOCK2 is used to prevent writing to BSEC_OTP_DATA64 to
BSEC_OTP_DATA95 until next system-reset.
Write to shadow write locked BSEC_OTP_DATA word are silently ignored.
Note:
Writing to OTP word 0 shadow is always prevented.
Address offset: 0x07C + 0x004 * x, (x = 0 to 2)
Reset value: 0x0000 0001, 0x0000 0000, 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SWLOCK[31:16]
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
SWLOCK[15:0]
rs
rs
Bits 31:0 SWLOCK[31:0]: lock the writing for the OTP shadow word until next power-on reset.
0: shadow word not locked
1: shadow word locked and cannot be written by software
Note: BSEC_OTP_SWLOCK0 bit 0 is forced to 1 by hardware, writing to this bit has no
effect.
182/3930
RM0442 Rev 7
RM0442
Boot and security and OTP control (BSEC)
3.6.12
BSEC OTP shadow read sticky lock register x
(BSEC_OTP_SRLOCKx)
BSEC_OTP_SRLOCK0 is used to prevent reloading of BSEC_OTP_DATA0 to
BSEC_OTP_DATA31 until next system-reset.
BSEC_OTP_SRLOCK1 is used to prevent reloading of BSEC_OTP_DATA32 to
BSEC_OTP_DATA63 until next system-reset.
BSEC_OTP_SRLOCK2 is used to prevent reloading of BSEC_OTP_DATA64 to
BSEC_OTP_DATA95 until next system-reset.
Setting SRLOCK bits or attempt to reload a locked OTP do not clear the corresponding
BSEC_OTP_DATAx shadow register.
Note:
BSEC_OTP_SRLOCK0 bit 0 is controlled by hardware according to fuse_ok, writing to this
bit has no effect.
Address offset: 0x094 + 0x004 * x, (x = 0 to 2)
Reset value: 0x0000 000X, 0x0000 0000, 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SRLOCK[31:16]
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
rs
SRLOCK[15:0]
rs
rs
Bits 31:0 SRLOCK[31:0]: prevent reloading of the shadow word from OTP until next power-on reset.
0: OTP word not locked
1: OTP word locked and cannot be reloaded
Note: Reloading of OTP word 0 is prevented after its initial read on a system reset.
3.6.13
BSEC JTAG input register (BSEC_JTAGIN)
Address offset: 0x0AC
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
DATA[15:0]
r
r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 DATA[15:0]: JTAG input data
16-bit copy from JTAG SoC register
RM0442 Rev 7
183/3930
189
Boot and security and OTP control (BSEC)
3.6.14
RM0442
BSEC JTAG output register (BSEC_JTAGOUT)
Address offset: 0x0B0
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
22
21
20
19
18
17
16
DATA[15:0]
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 DATA[15:0]: JTAG output data
16-bit copy to JTAG SoC register
3.6.15
BSEC scratch register (BSEC_SCRATCH)
Address offset: 0x0B4
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
DATA[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
DATA[15:0]
rw
Bits 31:0 DATA[31:0]: scratch data
This register is a general purpose register.
3.6.16
BSEC shadow register x (BSEC_OTP_DATAx)
The complete description of BSEC_OTP_DATAx register values and properties can be
found in Section 4: OTP mapping (OTP).
Several OTP directly impact BSEC behavior, such as:
•
184/3930
BSEC_OTP_DATA0[6:0] (see Table 11: OTP modes definition on page 168)
RM0442 Rev 7
RM0442
Boot and security and OTP control (BSEC)
Address offset: 0x200 + 0x004 * x, (x = 0 to 95)
Reset value: 0xXXXX XXXX
The reset value depends on the actual OTP programmed value and the OTP mode.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DATA[31:16]
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
rw
rw
rw
rw
rw
rw
rw
rw
rw
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
DATA[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 DATA[31:0]: shadow register read from OTP or written by software (OTP emulation mode)
The update of shadow registers is controlled by other registers and by OTP security mode.
3.6.17
BSEC hardware configuration register (BSEC_HWCFGR)
Address offset: 0xFF0
Reset value: 0x0000 0014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
r
r
r
ECC_USE[3:0]
r
r
r
SIZE[3:0]
r
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 ECC_USE[3:0]: protection / redundancy scheme used
0x0: No
0x1: ECC for upper OTP bits used
Others: reserved
Bits 3:0 SIZE[3:0]: OTP block size
0x2: 2 Kbits
0x4: 4 Kbits
0x8: 8 Kbits
Others: reserved
RM0442 Rev 7
185/3930
189
Boot and security and OTP control (BSEC)
3.6.18
RM0442
BSEC version register (BSEC_VERR)
Address offset: 0xFF4
Reset value: 0x0000 0011
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
r
r
r
r
r
r
21
20
19
18
17
16
MAJREV[3:0]
r
r
MINREV[3:0]
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 MAJREV[3:0]: major revision information
Bits 3:0 MINREV[3:0]: minor revision information
3.6.19
BSEC identification register (BSEC_IPIDR)
Address offset: 0xFF8
Reset value: 0x0010 0032
31
30
29
28
27
26
25
24
23
22
ID[31:16]
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
20
19
18
17
16
ID[15:0]
Bits 31:0 ID[31:0]: BSEC identification
3.6.20
BSEC size identification register (BSEC_SIDR)
Address offset: 0xFFC
Reset value: 0xA3C5 DD04
31
30
29
28
27
26
25
24
23
22
21
SID[31:16]
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
SID[15:0]
r
Bits 31:0 SID[31:0]: BSEC size identification
186/3930
RM0442 Rev 7
RM0442
3.6.21
Boot and security and OTP control (BSEC)
BSEC register map
Table 16 describes BSEC register map and reset values.
0
0
1
1
PWRUP
1
0
0
0
0
0
0
0
0
Res.
SECURE
ADDR[6:0]
Res.
0
0
FRC
PRGWDTH
TREAD
PROG
BSEC_OTP_
WRDATA
0
Res.
0x008
0
LOCK
Reset value
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BSEC_OTP_
CONTROL
Res.
0x004
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BSEC_OTP_
CONFIG
Res.
0x000
Register name
and reset value
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 16. BSEC register map and reset values
WRDATA[31:0]
BSEC_OTP_
DISTRUBED0
Reset value
0x020
0x024
0x034
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NIDEN
\DBGEN
OTP
DEVICEEN
Res.
HDPEN
ROMLOCK
BUSY
INVALID
Res.
SPIDEN
DENREG
PROGFAIL
GPLOCK
SPNIDEN
0
CP15SDISABLE[1:0]
CFGSDISABLE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DIS[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BSEC_OTP_
ERROR0
Reset value
0
0
DIS[31:0]
BSEC_OTP_
DISTURBED2
Reset value
0
0
DIS[31:0]
BSEC_OTP_
DISTURBED1
Reset value
CFGSWENABLE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
0x01C
0
0
Res.
BSEC_OTP_
DENABLE
0
0
Reset value
0x014
0
PWRON
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BSEC_OTP_LOCK
Res.
0x010
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BSEC_OTP_
STATUS
Res.
0x00C
Res.
Reset value
0
0
0
ERR[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0442 Rev 7
0
0
0
0
187/3930
189
Boot and security and OTP control (BSEC)
RM0442
Offset
Register name
and reset value
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 16. BSEC register map and reset values (continued)
BSEC_OTP_
ERROR1
ERR[31:0]
0x038
Reset value
0x03C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ERR[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
WRLOCK[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
WRLOCK[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
WRLOCK[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SPLOCK[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SPLOCK[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SPLOCK[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SWLOCK[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SWLOCK[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SWLOCK[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SRLOCK[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BSEC_OTP_
SRLOCK1
Reset value
188/3930
0
BSEC_OTP_
SRLOCK0
Reset value
0x098
0
BSEC_OTP_
SWLOCK2
Reset value
0x094
0
BSEC_OTP_
SWLOCK1
Reset value
0x084
0
BSEC_OTP_
SWLOCK0
Reset value
0x080
0
BSEC_OTP_
SPLOCK2
Reset value
0x07C
0
BSEC_OTP_
SPLOCK1
Reset value
0x06C
0
BSEC_OTP_
SPLOCK0
Reset value
0x068
0
BSEC_OTP_
WRLOCKED2
Reset value
0x064
0
BSEC_OTP_
WRLOCKED1
Reset value
0x054
0
BSEC_OTP_
WRLOCKED0
Reset value
0x050
0
BSEC_OTP_
ERROR2
Reset value
0x04C
0
0
0
0
0
SRLOCK[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0442 Rev 7
0
0
0
0
RM0442
Boot and security and OTP control (BSEC)
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BSEC_JTAGIN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SRLOCK[31:0]
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
x
x
0x37C
BSEC_
OTP_DATA95
DATA[31:0]
0
x
Res.
x
Res.
x
Res.
x
Res.
x
Res.
x
Res.
x
Res.
x
Res.
x
Res.
x
Res.
x
Res.
x
Res.
x
Res.
x
Res.
x
Res.
x
Res.
x
Res.
Res.
x
0xFFC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
ECC_USE
[3:0]
0
1
0
MAJREV
[3:0]
Res.
Res.
Res.
Res.
Res.
0
SIZE[3:0]
1
0
0
MINREV
[3:0]
0
0
0
1
0
0
0
1
ID[31:0]
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
BSEC_SIDR
Reset value
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BSEC_IPIDR
Reset value
0
0
Reset value
0xFF8
0
0
Res.
BSEC_VERR
0
0
Reset value
0xFF4
0
0
Res.
x
.
.
.
BSEC_IPHW_
CFGR
0
DATA[31:0]
.
.
.
0xFF0
0
DATA[31:0]
.
.
.
Reset value
0
Res.
0
BSEC_OTP_DATA1
Reset value
0
Res.
0x204
0
DATA[31:0]
BSEC_OTP_DATA0
Reset value
0
Res.
0x200
0
Res.
Reset value
0
0
BSEC_SCRATCH
0
DATA[15:0]
Reset value
0x0B4
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
BSEC_JTAGOUT
0
DATA[15:0]
Reset value
0x0B0
0
Res.
0x0AC
BSEC_OTP_
SRLOCK2
Res.
0x09C
Register name
and reset value
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 16. BSEC register map and reset values (continued)
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
0
0
0
0
1
0
0
SID[31:0]
1
0
1
0
0
0
1
1
1
1
0
0
0
1
0
1
1
Refer to Section 2.5 on page 153 for the register boundary addresses.
RM0442 Rev 7
189/3930
189
OTP mapping (OTP)
4
RM0442
OTP mapping (OTP)
The OTP bits are read or programmed by the Boot and Security and OTP control (BSEC).
Before being programmed the OTP bit default is ‘0’.
The STM32MP153 device has 3072 OTP (One Time Programmable) bits which can be
read-accessed in 96 words: BSEC_OTP_DATAx (x = 0 to 95):
–
Lower OTP are listed in Table 17: OTP list words 0 to 31.
–
Upper OTP are listed in Table 18: OTP list words 32 to 95.
The tables list the OTP word and bit field relevant properties using the following columns:
Name: OTP word synonym (for example OTP word0 is aka CFG0).
Description: OTP word or bit field description.
Prog: programming according to:
s: programmed by STMicroelectronics at factory whether product differentiations or
keys.
u: available to any other software executed after bootROM.
r: programmed by bootrom (for example, during SSP process)
wplock:
n: not locked.
y: permanent programming lock by factory programming.
swprlockx: sticky lock set by boot listed as s[w][p][r][c] with character w, p, r, c according to:
w: indicates write of shadow is sticky locked,
p: indicates OTP programming is sticky locked,
r: indicates OTP reloading is sticky locked,
c: indicates OTP shadow is cleared during boot.
swprlock1: sticky lock set after boot in secured-open.
swprlock2: sticky lock set after boot in secured-closed (only possible for device with secure
boot capabilities).
swprlock3: sticky lock set after boot for RMA.
190/3930
RM0442 Rev 7
RM0442
OTP mapping (OTP)
Table 17. OTP list words 0 to 31
Word
Name
Bits
Description
prog
wp
lock
swpr swpr swpr
lock1 lock2 lock3
Detail description
OTP mode encoding
0
CFG0
0 to 5
OTP mode encoding
s
6
Closed_device bit(1)
u
7 to 31
Reserved for
STMicroelectronics
s
n
sw
sw
sw
-
sw
Section 65.2: Device part number (RPN)
RPN coding
1
CFG1
0 to 7
RPN coding
8 to 31
Reserved for
STMicroelectronics
s
y
sw
sw
Rerserved for STMicroelectronics
2
CFG2
0 to 3
SSP_ATTEMPTS
r
4 to 31
Reserved for
STMicroelectronics
s
y
swprc swprc swprc
Set by bootROM during SSP
process.
-
Boot / source definition
qspi_not_default_af
0: QSPI uses default hard coded AFmux
1: QSPI uses AFmux defined in OTP
emmc_if_id
0: Source is default one: SDMMC2 with
default AFMux
1: SDMMC1. 2: SDMMC2 (uses non
default AFmux defined in OTP)
sd_if_id
0: Source is default one: SDMMC1 with
default AFMux
1: SDMMC1 (uses non default AFmux
defined in OTP)
2: SDMMC2
5
no_cpu_pll
0: PLLs for CPU/AXI are enable for cold
boot
1: PLLs for CPU/AXI are not enable for
cold boot
6
no_usb_dp_pullup
0: USB DP pull-up is set
1: USB DP pull-up is not set
7 to 14
uart_instances_disa
bled
0b00000001 reserved.
0b00000010 disable USART2.
0b00000100 disable USART3.
0b00001000 disable UART4.
0b00010000 disable UART5.
0b00100000 disable UART6.
0b01000000 disable UART7.
0b10000000 disable USART8.
15
no_data_cache
0
1 to 2
3 to 4
3
CFG3
u
n
-
sw
-
0: Data cache is used by bootrom.
1: Data cache is not used by bootrom.
RM0442 Rev 7
191/3930
201
OTP mapping (OTP)
RM0442
Table 17. OTP list words 0 to 31 (continued)
Word
Name
Bits
Description
prog
wp
lock
swpr swpr swpr
lock1 lock2 lock3
Detail description
Boot / source definition (continued)
3
CFG3
16 to 23 boot_source_disable
0b00000001 disable FMC boot source.
0b00000010 disable QSPI NOR boot
source.
0b00000100 disable eMMC boot source.
0b00001000 disable SD boot source.
0b00010000 disable UART boot source.
0b00100000 disable USB boot source.
0b01000000 disable QSPI NAND boot
source.
secondary_boot_sou
rce
0: No secondary boot source is defined
1: FMC NAND
2: QSPI NOR
3: eMMC
4: SD
5: QSPI NAND
24 to 26
27 to 29
30 to 31
u
n
-
sw
-
0: No primary boot source is defined
1: FMC NAND
2: QSPI NOR
3: eMMC
4: SD
5: QSPI NAND
primary_boot_sourc
e
0b00 HSE is autodetected.
0b01 HSE is 24 MHz.
0b10 HSE is 25 MHz.
0b11 HSE is 26 MHz.
HSE value
Boot / monotonic counter
4
CFG4
192/3930
0 to 31
Boot / monotonic
counter
u
n
-
RM0442 Rev 7
-
-
Value of monotonic counter is 31 is 2*X
where X is position of the most significant
bit at 1.
RM0442
OTP mapping (OTP)
Table 17. OTP list words 0 to 31 (continued)
Word
Name
Bits
Description
prog
wp
lock
swpr swpr swpr
lock1 lock2 lock3
Detail description
Boot / AFmux configuration 1
5
0 to 3
mode0
0: AF; no pull; low speed
1: AF; no pull; medium speed
2: AF; no pull; high speed
3: AF; pull up; low speed
4: AF; pull up; medium speed
5: AF; pull up; high speed
6: AF; pull down; low speed
7: AF; pull down; medium speed
8: AF; pull down; high speed
9: GPIO output high
10: GPIO output low
11: GPIO input
12: GPIO open drain; No pull
13: GPIO open drain; pull up
14: GPIO open drain; pull down
15: GPIO analog mode
4 to 7
afmux0
AF mux value between 0 and 15.
8 to 11
pin0
pin id between 0 and 15 for GPIOA to
GPIOJ and between 0 and 7 for GPIOK
and GPIOZ.
CFG5
u
n
-
sw
-
12 to 15
port0
0: unused (in that case, mode0, afmux0
and pin0 fields could be used as general
purpose OTP)
1: Bank A
2: Bank B
3: Bank C
4: Bank D
5: Bank E
6: Bank F
7: Bank G
8: Bank H
9: Bank I
10: Bank J
11: Bank K
12: Bank Z
Others: Invalid configuration
16 to 19
mode1
idem CFG5.mode0
20 to 23
afmux1
idem CFG5.afmux0
24 to 27
pin1
idem CFG5.pin0
28 to 31
port1
idem CFG5.port0
RM0442 Rev 7
193/3930
201
OTP mapping (OTP)
RM0442
Table 17. OTP list words 0 to 31 (continued)
Word
Name
Bits
Description
prog
wp
lock
swpr swpr swpr
lock1 lock2 lock3
Detail description
Boot / AFmux configuration 2
6
CFG6
0 to 3
mode2
idem CFG5.mode0
4 to 7
afmux2
idem CFG5.afmux0
8 to 11
pin2
idem CFG5.pin0
12 to 15
port2
16 to 19
mode3
20 to 23
afmux3
idem CFG5.afmux0
24 to 27
pin3
idem CFG5.pin0
28 to 31
port3
idem CFG5.port0
u
n
-
sw
-
idem CFG5.port0
idem CFG5.mode0
Boot / AFmux configuration 3
7
CFG7
0 to 3
mode4
idem CFG5.mode0
4 to 7
afmux4
idem CFG5.afmux0
8 to 11
pin4
idem CFG5.pin0
12 to 15
port4
16 to 19
mode5
20 to 23
afmux5
idem CFG5.afmux0
24 to 27
pin5
idem CFG5.pin0
28 to 31
port5
idem CFG5.port0
u
n
-
sw
-
idem CFG5.port0
idem CFG5.mode0
Partially reserved for STMicroelectronincs
8
CFG8
194/3930
0 to 7
Reserved for
STMicroelectronics
s
8
SSP_REQ
u
9
SSP_SUCCESS
u
10 to 31
Reserved for
STMicroelectronics
s
n
swp
swp
swp
Set by FSBL(TF-A) during SSP process.
Set by FSBL(TF-A) during SSP process.
-
RM0442 Rev 7
RM0442
OTP mapping (OTP)
Table 17. OTP list words 0 to 31 (continued)
Word
Name
Bits
Description
prog
wp
lock
swpr swpr swpr
lock1 lock2 lock3
Detail description
BootROM / configuration
9
CFG9
0
Boot_traces_disable
d
u
0: no. 1: yes
1
hse_frequency_auto
detection_disable
u
0: no. 1: yes
2
hse_bypass_detecti
on_disable
u
0: no. 1: yes
3
Reserved for
STMicroelectronics
s
-
4 to 13
not used yet
s
-
14
spinand_need_plane
_select
u
0: SPI NAND plane select not need
1: SPI NAND plane select is needed
0: ECC unset.
1: ECC 1bit (Hamming)
2: ECC 4bit (BCH4)
3: ECC 8bit (BCH8)
4: on-die ECC
15 to 17
nand_number_of_ec
c_bits
u
18
nand_bus_width
u
0: 8 bit
1: 16 bit
19 to 26
nand_nb_of_blocks
u
Number of blocks in unit of 256 blocks.
n
-
-
-
27 to 28
nand_block_size
u
Block size in number of pages:
0: 64 pages per block
1: 128 pages per block
2: 256 pages per block
29 to 30
nand_page_size
u
0: 2Kbytes
1: 4Kbytes
2: 8Kbytes
31
nand_param_stored
_in_otp
u
0: no
1: nand parameters bits 15 to 30 are used
Device configuration
10
CFG10
11
CFG11
0 to 31
for OEM device
configuration
u
n
-
-
-
-
Device configuration
0 to 31
for OEM device
configuration
u
n
-
-
-
-
Engineering purposes
12
CFG12
13
ID0
14
ID1
0 to 31
Reserved for
STMicroelectronics
s
y
-
-
-
-
Unique device ID (96-bit)
0 to 31
UID[31:0]
s
y
-
-
-
-
Unique device ID (96-bit)
0 to 31
UID[63:32]
s
y
-
RM0442 Rev 7
-
-
-
195/3930
201
OTP mapping (OTP)
RM0442
Table 17. OTP list words 0 to 31 (continued)
Word
Name
15
ID2
Bits
Description
prog
wp
lock
swpr swpr swpr
lock1 lock2 lock3
Detail description
Unique device ID (96-bit)
0 to 31
UID[95:64]
s
y
-
-
-
-
Hardware trimming / analog 1
16
HW0
0 to 5
VREFBUF trimming
VREBUF Trim
6 to 9
I/O compensation
trimming
Used for I/O calibration
10 to 11
Reserved
12 to 15
1V8 reference
trimming
16 to 21
LSI trimming
22 to 26
1V1 reference
trimming
27 to 29
PKG: factory
programmed
30 to 31
Reserved for
STMicroelectronics
1V8 Regulator Trim
s
y
swp
swp
swp
1V1 Regulator Trim
Refer to Section 65.4: Package data
register (PKG).
-
Hardware trimming / analog 2
17
HW1
196/3930
0 to 7
CSITRIM[7:0]
CSI Trim
8 to 19
HSITRIM[11:0]
HSI Trim
20 to 24
DAC1 factory
trimming
25 to 29
DAC2 factory
trimming
30 to 31
Reserved for
STMicroelectronics
DAC1 Trim
s
y
-
-
DAC2 Trim
-
RM0442 Rev 7
RM0442
OTP mapping (OTP)
Table 17. OTP list words 0 to 31 (continued)
Word
Name
Bits
Description
prog
wp
lock
swpr swpr swpr
lock1 lock2 lock3
Detail description
Hardware trimming / PKG / WDG config
18
0 to 2
Reserved for
STMicroelectronics
3
IWDG1_HW
IWDG1 start:
0: start by software
1: auto start
4
IWDG2_HW
IWDG2 start:
0: start by software
1: auto start
5
IWDG1_FZ_STOP
6
IWDG2_FZ_STOP
7
IWDG1_FZ_STAND
BY
8
IWDG2_FZ_STAND
BY
9
OTP_MCU_
SYSRST_EN
10
Reserved for
STMicroelectronics
HW2
11 to 12
s
-
IWDG1 freeze in Stop:
0: no
1: freeze in Stop
IWDG2 freeze in Stop:
0: no
1: freeze in Stop
u
IWDG1 freeze in Standby:
0: no
1: freeze in Standby
n
-
-
-
MCU allowed to generate System Reset.
s
00: BOR Disabled
01: BOR = 2.1 V
10: BOR = 2.4 V
11: BOR = 2.7 V
SELINBORH[1:0]
1: required when VDD is below 2.5 V to
allow the SYSCFG IO control register
HSLVEN_xxx bits to be taken into
account.
For more information see Section 14.3:
SYSCFG registers
SYSCFG_IOCTRLSETR and
SYSCFG_IOCTRLCLRR registers.
u
13
PRODUCT_BELOW
_2V5
14 to 31
Reserved for
STMicroelectronics
IWDG2 freeze in Standby:
0: no
1: freeze in Standby
s
-
Hardware trimming / calibration for DTS
19
HW3
0 to 15
TS1_FMT0[15:0]
s
y
-
-
-
DTS frequency measured freq at T0
16 to 31
TS1_RAMP_COEF[
15:0]
s
y
-
-
-
DTS ramp coefficient
RM0442 Rev 7
197/3930
201
OTP mapping (OTP)
RM0442
Table 17. OTP list words 0 to 31 (continued)
Word
Name
Bits
Description
prog
wp
lock
swpr swpr swpr
lock1 lock2 lock3
Detail description
Hardware trimming / calibration for VREFINT, DTS
20
0 to 6
TRIM_DTP_R[6:0]
s
y
-
-
-
DTS R Trim
7 to 8
TS1_T0[1:0]
s
y
-
-
-
DTS T0 value
9 to 15
Reserved for
STMicroelectronics
s
y
-
-
-
16 to 31 VREFINT_CAL[15:0]
s
y
-
-
-
HW4
ADC VBG measurement to correct for
VREF
Memory repair word 1
21
HW5
22
HW6
31 to 0
Reserved for
STMicroelectronics
s
y
-
-
-
-
Memory repair word 2
0 to 31
Reserved for
STMicroelectronics
s
y
-
-
-
-
Hardware trimming / calibration for analog temp sensor
23
HW7
24
PKH0
25
PKH1
26
PKH2
27
PKH3
28
PKH4
29
PKH5
30
PKH6
31
PKH7
0 to 15
TS_CAL1[15:0]
s
y
-
-
-
ADC TEMP measurement at T0
16 to 31
TS_CAL215:0]
s
y
-
-
-
ADC TEMP measurement at T1
sw
sw
-
sw
sw
-
sw
sw
-
sw
sw
-
sw
sw
-
sw
sw
-
sw
sw
-
sw
sw
-
0 to 31
Public Key Hash(2)
u/s
n/y(3)
sw
-
0 to 31
Public Key Hash
u/s
n/y(3)
sw
-
0 to 31
Public Key Hash
u/s
n/y(3)
sw
0 to 31
Public Key Hash
u/s
n/y(3)
sw
-
0 to 31
Public Key Hash
u/s
n/y(3)
sw
-
0 to 31
Public Key Hash
u/s
n/y(3)
sw
-
0 to 31
Public Key Hash
u/s
n/y(3)
sw
-
0 to 31
Public Key Hash
u/s
n/y(3)
sw
1. This bit must never be programmed to 1 on products without secure-boot option available (refer to product datasheet).
As an example, setting this bit on STM32MP15xA and STM32MP15xD products might make then permanently fail to boot.
To avoid this case, it is recommended to make the OTP Word 0 permanent write locked (see Section : OTP permanent write
lock in BSEC chapter).
2. The Public Key Hash is composed of 32 bytes: hash = byte0 byte1 byte2 ... byte31. These bytes are stored in the OTP in 8
words of 4 bytes each. The first four bytes of the hash table are stored in PKH0, the next four in PKH1, and so on. Within
each word the lowest numbered byte is stored in the most significant position, and the highest numbered byte in the least
significant position. Example: if hash = 00 01 02 03 04 05 06 07 08... then PKH0 = 0x00010203, PKH1 = 0x04050607, and
so on.
3. This word is permanent write locked on devices without secure-boot option (see datasheet).
198/3930
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RM0442
OTP mapping (OTP)
Table 18. OTP list words 32 to 95
Word
Name
Bits
Description
prog
wplock
swpr
lock1
swpr
lock2
swpr
lock3
32
XK0
0 to 31
Reserved for STMicroelectronics
s
y
swprc
swprc
swprc
33
XK1
0 to 31
Reserved for STMicroelectronics
s
y
swprc
swprc
swprc
34
XK2
0 to 31
Reserved for STMicroelectronics
s
y
swprc
swprc
swprc
35
XK3
0 to 31
Reserved for STMicroelectronics
s
y
swprc
swprc
swprc
36
XK4
0 to 31
Reserved for STMicroelectronics
s
y
swprc
swprc
swprc
37
XK5
0 to 31
Reserved for STMicroelectronics
s
y
swprc
swprc
swprc
38
XK6
0 to 31
Reserved for STMicroelectronics
s
y
swprc
swprc
swprc
39
XK7
0 to 31
Reserved for STMicroelectronics
s
y
swprc
swprc
swprc
40
XK8
swp
swp
swp
swp
swp
swp
swp
swp
swp
swp
swp
swp
swp
swp
swp
swp
swp
swp
swp
swp
swp
swp
swp
swp
swp
swp
ST Public ECDSA Chip Certificate for SSP
0 to 31
41
swp
Certificate bits(1)
s
y
swp
Certificate bits(1)
s
y
swp
Certificate bits(1)
s
y
swp
Certificate bits(1)
s
y
swp
Certificate bits(1)
s
y
swp
Certificate bits(1)
s
y
swp
Certificate bits(1)
s
y
swp
Certificate bits(1)
s
y
swp
ST Public ECDSA Chip Certificate for SSP
XK19
0 to 31
52
y
ST Public ECDSA Chip Certificate for SSP
XK18
0 to 31
51
s
ST Public ECDSA Chip Certificate for SSP
XK17
0 to 31
50
Certificate bits(1)
ST Public ECDSA Chip Certificate for SSP
XK16
0 to 31
49
swp
ST Public ECDSA Chip Certificate for SSP
XK15
0 to 31
48
y
ST Public ECDSA Chip Certificate for SSP
XK14
0 to 31
47
s
ST Public ECDSA Chip Certificate for SSP
XK13
0 to 31
46
Certificate bits(1)
ST Public ECDSA Chip Certificate for SSP
XK12
0 to 31
45
swp
ST Public ECDSA Chip Certificate for SSP
XK11
0 to 31
44
y
ST Public ECDSA Chip Certificate for SSP
XK10
0 to 31
43
s
ST Public ECDSA Chip Certificate for SSP
XK9
0 to 31
42
Certificate bits(1)
Certificate bits(1)
s
y
swp
ST Public ECDSA Chip Certificate for SSP
XK20
0 to 31
Certificate bits(1)
RM0442 Rev 7
s
y
swp
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OTP mapping (OTP)
RM0442
Table 18. OTP list words 32 to 95 (continued)
Word
Name
53
XK21
Bits
wplock
swpr
lock1
swpr
lock2
swpr
lock3
Certificate bits(1)
s
y
swp
swp
swp
swp
swp
ST Public ECDSA Chip Certificate for SSP
XK22
0 to 31
55
prog
ST Public ECDSA Chip Certificate for SSP
0 to 31
54
Description
Certificate bits(1)
s
y
swp
ST Public ECDSA Chip Certificate for SSP
XK23
0 to 31
Certificate bits(1)
s
y
swp
swp
swp
n
swrc
swrc
swrc
n
c
c
swprc
u
n
c
c
swprc
Password for RMA
56
57
XK24
0 to 14
RMA unlock password
15 to 29
RMA relock password
30 to 31
Not used
u
s
MAC address 1
XK25
0 to 31
mac[31:0]
u
MAC address 2
58
XK26
0 to 15
mac[47:32]
16 to 31
Free for user
59
XK27
-
Free for user
u
n
c
c
swprc
60
XK28
-
Free for user
u
n
c
c
swprc
61
XK29
-
Free for user
u
n
c
c
swprc
62
XK30
-
Free for user
u
n
c
c
swprc
63
XK31
-
Free for user
u
n
c
c
swprc
64
XK32
-
Free for user
u
n
c
c
swprc
65
XK33
-
Free for user
u
n
c
c
swprc
66
XK34
-
Free for user
u
n
c
c
swprc
67
XK35
-
Free for user
u
n
c
c
swprc
68
XK36
-
Free for user
u
n
c
c
swprc
69
XK37
-
Free for user
u
n
c
c
swprc
70
XK38
-
Free for user
u
n
c
c
swprc
71
XK39
-
Free for user
u
n
c
c
swprc
72
XK40
-
Free for user
u
n
c
c
swprc
73
XK41
-
Free for user
u
n
c
c
swprc
74
XK42
-
Free for user
u
n
c
c
swprc
75
XK43
-
Free for user
u
n
c
c
swprc
76
XK44
-
Free for user
u
n
c
c
swprc
77
XK45
-
Free for user
u
n
c
c
swprc
200/3930
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RM0442
OTP mapping (OTP)
Table 18. OTP list words 32 to 95 (continued)
Word
Name
Bits
Description
prog
wplock
swpr
lock1
swpr
lock2
swpr
lock3
78
XK46
-
Free for user
u
n
c
c
swprc
79
XK47
-
Free for user
u
n
c
c
swprc
80
XK48
-
Free for user
u
n
c
c
swprc
81
XK49
-
Free for user
u
n
c
c
swprc
82
XK50
-
Free for user
u
n
c
c
swprc
83
XK51
-
Free for user
u
n
c
c
swprc
84
XK52
-
Free for user
u
n
c
c
swprc
85
XK53
-
Free for user
u
n
c
c
swprc
86
XK54
-
Free for user
u
n
c
c
swprc
87
XK55
-
Free for user
u
n
c
c
swprc
88
XK56
-
Free for user
u
n
c
c
swprc
89
XK57
-
Free for user
u
n
c
c
swprc
90
XK58
-
Free for user
u
n
c
c
swprc
91
XK59
-
Free for user
u
n
c
c
swprc
92
XK60
-
Free for user
u
n
c
c
swprc
93
XK61
-
Free for user
u
n
c
c
swprc
94
XK62
-
Free for user
u
n
c
c
swprc
95
XK63
-
Free for user
u
n
c
c
swprc
1. The ST Public ECDSA Chip Certificate for SSP is composed of 64 bytes: key = byte0 byte1 byte2 ... byte63. These bytes
are stored in the OTP in 16 words of 4 bytes each. The first four bytes of the key table are stored in XK8, the next four in
XK9, and so on. Within each word the lowest numbered byte is stored in the most significant position, and the highest
numbered byte in the least significant position. Example: if key = 00 01 02 03 04 05 06 07 08 ... then XK8 = 0x00010203,
XK9 = 0x04050607, and so on.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.1
Introduction
RM0442
Portions Copyright (c) Synopsys, Inc. All rights reserved. Used with permission.
The DDRCTRL is a DDR-SDRAM controller and specific configuration of Synopsys
uMCTL2 DDR controller v3.00a.
The DDRCTRL combined with the DDRPHYC (DDR PHY with Physical Utility Block)
provides a complete memory interface solution for the DDR memory subsystem.
5.2
DDRCTRL features
•
Two 64-bit AMBA® 4 AXI4 ports interface (XPI)
•
AXI clock asynchronous to the controller
•
Supported standards:
–
JEDEC DDR3 SDRAM specification, JESD79-3E for DDR3/3L with 32-bit
interface
–
JEDEC LPDDR2 SDRAM specification, JESD209-2E for LPDDR2 with 32-bit
interface
–
JEDEC LPDDR3 SDRAM specification, JESD209-3B for LPDDR3 with 32-bit
interface
Warning:
202/3930
The STM32MP153x does not support the ODT for LPDDR3
•
64-bit with DFI 2.1 compliant interface to DDRPHYC
•
Advanced scheduler and SDRAM command generator
•
1:1 frequency ratio between the DDRC clock and the DDR PHY / external memory
clock (aka SDR mode)
•
Asynchronous clock between the AXI ports and the DDRC (the clock crossing is local
to XPI’s)
•
Programmable full data width (32-bit) or half data width (16-bit)
•
Advanced QoS support with 3 traffic class on read and 2 traffic classes on write
•
Options to avoid starvation of lower priority traffic
•
Guaranteed coherency for write-after-read (WAR) and read-after-write (RAW) on the
AXI ports
•
Programmable support for burst length options (4, 8,16)
•
Write combine to allow multiple writes to the same address to be combined into a
single write
•
Single rank configuration
•
Supports automatic SDRAM power-down entry and exit caused by a lack of transaction
arrival for programmable time
•
Supports automatic clock stop (LPDDR2/3) entry and exit caused by lack of transaction
arrival
RM0442 Rev 7
RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
•
Supports automatic low-power mode operation caused by a lack of transaction arrival
for programmable time via hardware low-power interface
•
Programmable paging policy selectable as any of the following:
•
5.3
–
Leave page open after accesses (Open page policy)
–
Close page when there are no further accesses available in the controller for that
page
–
Auto-precharge with each access, with an optimization for page-close mode which
leaves the page open after a flush for read-write and write-read collision cases
Supports the self-refresh entry and exit as follows:
–
Automatic self-refresh entry and exit caused by lack of transaction arrival for
programmable time
–
Self-refresh entry and exit under software control
•
Support for deep power-down entry and exit under software control (LPDDR2)
•
Support for explicit SDRAM mode register updates under software control
•
Flexible address mapper logic to allow application specific mapping of row, column,
bank bits
•
Programmable support for 1T or 2T timing
•
User-selectable refresh control options:
–
Controller-generated auto-refreshes at programmable average intervals
–
Ability to group up to 8 controller-generated refreshes together to be issued
consecutively (this reduces the frequency of page closings, increasing the overall
efficiency)
–
When the controller-generated refreshes are grouped, some refreshes can be
issued speculatively when the controller is idle for a programmable period of time
–
Ability to disable controller-generated auto-refreshes
–
Ability to issue a refresh through direct software request
–
User-selectable ability to perform per-bank refreshes rather than all-banks
refreshes for LPDDR2/3
DDRCTRL block diagram
A simplified DDRCTRL block diagram is shown in Figure 7.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Figure 7. DDRCTRL block diagram
DDRCTRL
DDRC
AXI
AXI
Port 0
Port interface
Command
mux
command
Scheduler
DFI
interface
PA
AXI
AXI
Port 1
Port interface
APB
Data Mux /
Reponse
Demux
Reponse
engine
data
response
Registers
MSv46533V2
5.4
DDRCTRL architecture overview
See the DDRCTRL block diagram in Figure 7.
•
The AXI Port Interface (XPI) block provides the interface to the AXI port with the AXI
bus protocol handling, data buffering and reordering for read data, data bus size / clock
domain conversion and memory burst address alignment.
•
The Port Arbiter (PA) block provides latency sensitive, priority based arbitration
between the addresses issued by the XPI’s.
•
The DDR Controller (DDRC) block contains a logical CAM (Content Addressable
Memory). This holds information on the commands, which is used by the scheduling
algorithms to optimally schedule commands to be sent to the PHY, based on priority,
bank/rank status and DDR timing constraints.
The APB register block contains the software accessible registers
•
5.4.1
•
The write data are stored until its associated command is issued to the PHY. The Write
data buffer is local to DDRC.
•
The read data are handled by the response engine in the DDRC and returned in the
order of scheduled read commands on the HIF. the read data are stored in the read reorder buffer (local to XPI) and returned in order, to the AXI ports.
AXI Port Interface (XPI)
The XPI processes the AXI information: address, burst size, burst length and burst type and
converts the AXI burst into read and write requests which are forwarded to the PA.
In the opposite direction, the XPI converts the responses from the DDRC into appropriate
AXI responses.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Read address channel features:
–
Supports any burst length for incremental bursts (<=256 byte) and burst with
length <= 16 for WRAP bursts.
–
The start address can be unaligned to the AXI width.
–
The burst size can be less than the AXI width.
–
The Read Address Queue (RAQ) is configured with dual queues (named “red” and
“blue” queues)
–
The clock crossing is performed in RAQ
–
The depth of RAQ is set to 4.
–
The generation of read request is based on AXI address and burst information and
divided into packets equal to memory burst length (BL2, BL4, BL8, BL16)
–
In case of an unaligned burst, the first read request is unaligned and the remaining
read requests are aligned.
In general, the re-alignment to a memory burst boundary potentially causes some
data beats to be discarded (affecting bandwidth) and potentially introduces
additional latency on the read data and response channel.
Write address channel features:
–
The Write Address Queue (WAQ) is used to store all the addresses for write
requests from a given port.
–
There is a single queue for all AXI IDs from a given port.
–
The write address channel behavior is similar to the read address channel.
–
The clock crossing is performed in WAQ
–
The depth of WAQ is set to 4.
Read data and response channels:
5.4.2
–
The read data and response channel has a single data storage queue (RDQ)
–
The clock crossing is performed in RDQ
–
The depth of RDQ is set to 10
–
The data from different IDs are stored in the same queue and are returned in the
order of read address acceptance.
–
A read reorder buffer is implemented in each port to reorder the read data for that
port to the same order as the order of the AXI read commands
–
The virtual channels and dynamic mapping (allow optimum reordering of read
data)
Port arbiter (PA)
The PA arbitrates command requests from the 2 AXI ports to the HIF of the DDR Controller.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
The PA is comprised of multiple tiers of arbitration stages which include:
Note:
a)
Read/write arbitration (single HIF option)
b)
2 priority level arbitration based on port aging and expired-VPR/expired-VPW
commands (timeout - priority0)
c)
2 priority level arbitration for read requests based on DDRC read priorities
(HPR/LPR-VPR)
d)
32-priority level arbitration based on internal port aging or 16-priority level
arbitration based AXI QoS inputs (programmed in AXI interconnect)
e)
Round-robin arbitration to resolve ports having the same priority after passing all
stages of arbitration.
The port aging refers to counting down the time when a port has a request, but is not
granted access to the DDRC.
The port timeout refers to when the port age becomes 0, which is also referred as the
highest priority -priority0’.
The expired-VPR refers to Variable Priority Read commands whose counter has expired.
The read/write credits refer to the DDRC ‘Credit Mechanism’ employed at the HIF interface.
5.4.3
Host Interface (HIF)
The HIF is an internal interface to the DDRCTRL (the AXI Port Interface and Port Arbiter
handle all signals on this interface). It is only described for the sake of understanding QoS
and multi-tier arbitration.
The read, write requests and write data are transferred from PA to DDRC using HIF
interface.
The requests are throttled by:
a)
A credit mechanism that ensures that the buffer space is available for any request
made to the DDRC, prior to the request being made.
b)
An independent stall mechanism that throttles requests when address collisions
take place or when entering a self-refresh via the software self-refresh.
The read data are sent back via a common response interface
Credit mechanism:
The DDRC employs a credit mechanism to ensure that buffers do not overflow. The
interface making the request to the DDRC, can only request commands for which it has
been granted credits to issue.
The credits are tracked separately for the following three command types:
- High priority read (HPR)
- Low priority read (LPR)
- Write (WR)
The interface logic includes counters to track the number of credits. The credit count
increments every time that the DDRC issues a credit.
The VPR commands are counted in the LPR credit bucket, the VPW commands are
counted in the WR credit bucket.
Read requests:
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
When the LPR or HPR credit count is greater than zero, the interface can issue read
requests to the DDRC
Write requests:
When the WR credit count is greater than zero, the interface can issue write requests to the
DDRC.
5.4.4
DDR scheduler (DDRC)
The DDRC queues commands for scheduling and the SDRAM command generation unit.
The DDRC includes 3 stores:
•
HPR and LPR stores in common read CAM
•
WR store in write CAM
Both CAMs are 16 entries, the HPR/LPR split is software programmable.
The DDRC allows the user to manage the Transaction Service Control (TSC) according to
QoS and timeouts.
5.4.5
APB Interface (APB)
There are three classes of registers in DDRCTRL:
•
Dynamic Registers
•
Quasi Dynamic Registers
•
Static Registers
The dynamic registers can be written at any time during operation.
The static registers can be written only when the controller is in reset.
The quasi dynamic registers can be written when the DDRCTRL is in reset or under specific
conditions after the reset is done. To write the quasi dynamic registers, the
DDRCTRL_SWCTL.SW_DONE bit must be set to 0 at the beginning of the programming
sequence and set back to 1 at the end. After the DDRCTRL_SWSTAT.SW_DONE_ACK
must be polled to acknowledge that the write action has been completed.
For more information about dynamic and quasi dynamic registers, refer to uMCTL2 Data
Book [1]
5.4.6
DFI Interface (DFI)
The DDRCTRL contains a DFI MC (Memory Controller) interface, which is used to connect
to a DFI compliant DDRPHYC to transfer address, control and data to the PHY.
The DFI interface is sub-divided into the following interface groups:
•
Control interface
•
Write data interface
•
Read data interface
•
Update interface
•
Status interface
•
Training interface (PHY-independent mode as supported by uMCTL2)
•
Low-power control interface
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
The DDRCTRL, including its DFI interface, runs at the single data rate (SDR) clock (referred
to as 1:1 frequency ratio mode in the DFI Specification), so all DFI command and address
signals are equal in width to the equivalent DDR SDRAM signals. The DFI data signals are
twice the width of the equivalent DDR SDRAM signals.
The DDRCTRL runs with a SDR clock and the DDRPHYC operates the SDR to DDR rate
conversion on the data buses. In 1:1 frequency ratio mode, core_ddrc_core_clk and
CK/CK# run at the same SDR clock frequency.
5.5
DDRCTRL functional description
5.5.1
Transaction service control (TSC) and quality of service (QoS)
The transaction service control allows the user to carefully manage the following:
•
Costly read/write bus turn-around
•
Priorities of read requests to generally favor high priority traffic while also preventing
starvation of low priority traffic
This functionality is implemented in a simple 2-state machine for each traffic type with
completely configurable controls. The states of the 2-state machine determine when
reads/writes are serviced and the relative priority (high priority versus low priority reads) at
any given moment.
The transactions are separated into five traffic classes: with 3 read classes and 2 write
classes:
•
Low priority reads (LPR)
•
Variable priority reads (VPR)
•
High priority reads (HPR)
•
Normal priority writes (NPW)
•
Variable priority writes (VPW)
The traffic classes are determined according to AXI QoS values (AxQOS[3:0]) set by the
SOC AXI Interconnect (AXIM) and QoS regions settings.
The HPR and VPR/LPR are stored in a common read CAM which is split according to
DDRCTRL_SCHED.lpr_num.
The VPR commands move to the expired-VPR after a timeout set by
DDRCTRL_PERFVPR1.vpr_timeout. The expired -VPR goes to highest priority (Priority0).
VPW and NPW are stored in a common write CAM; the VPW commands go to the expiredVPR after timeout set by DDRC_PERFVPW1.vpw_timeout. The expired-VPW commands
go to highest priority (Priority0).
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Following is the list of registers related to transaction service and QoS control:
5.5.2
–
DDRCTRL_SCHED: main scheduler control
–
DDRCTRL_SCHED1: page Ccose timer
–
DDRCTRL_PERFHPR1: controls HPR starvation and run_length
–
DDRCTRL_PERFHPR1: controls HPR starvation and run_length
–
DDRCTRL_PERFLPR1: controls LPR starvation and run_length
–
DDRCTRL_PCFGR_0/1: AXI port read control for port 0/1
–
DDRCTRL_PCFGW_0/1: AXI port write control for port 0/1
–
DDRCTRL_PCFRQOS0_0/1 and DDRCTRL_PCFRQOS1_0/1: AXI port read
QoS region mapping for port 0/1 and port timeouts.
–
DDRCTRL_PCFWQOS0_0/1 and DDRCTRL_PCFWQOS1_0/1: AXI port write
QoS region mapping for port 0/1 and port timeouts.
Paging policy options
Open page policy is set by DDRC_SCHED.pageclose = 0.
Any bank remains open until there is a need to close it because of a page miss or
refresh timeout.
Intelligent precharge is a mid way between open and closed page policies, set by
DDRC_SCHED.pageclose = 1 and DDRC_SCHED.pageclose_timer value to give the
user control over the time waited when there are no page hits to a bank in the CAM
before the auto-precharge or the explicit precharge is scheduled.
This timer allows the page to be kept open for a configurable number of clock cycles
after there are no commands pending in the CAM to a bank. If there are pending
commands higher up in the stream (for example XPI/PA ) to the same bank/page, it
gives a chance to be scheduled by the DDRCTRL as an open page command.
5.5.3
Power saving features
The DDRCTRL supports various methods to save power within the system using power
saving opportunities in the SDRAM, DDRPHYC and the SOC.
Precharge Power Down: (PDN)
The DDRCTRL automatically puts SDRAM in the Precharge Power Down mode under
the control of the following parameters:
Note:
–
DDRCTRL_PWRCTRL.powerdown_en: to enter PDN (PDE) after a number of idle
cycles
–
DDRCTRL_PWRTMG.powerdown_to_x32: number of idle clocks in multiple of 32
to enter PDN
–
DDRCTRL_DRAMTMG1.txp: minimum time to wait after PDN exit (PDX) to any
command (DLL stays locked during PDN)
During PDN refresh commands are performed and clocks must be maintained; the
DDRCTRL pre-charges all banks before Precharge Power Down Exit (PDE).
The DDR3 slow power down (by setting MR0[12] =1) is not supported.
Self-Refresh: (SR)
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
The SR is a significant power saving opportunity for SDRAM. Furthermore during SR, the
DLL’s in DDRPHY C can be bypassed and the DDRCTRL clocks can be stopped.
The DDRCTRL puts SDRAM in Self Refresh (SR) in the following cases:
•
•
Automatic SR when there are no read/write for a predefined time. This mode is
controlled by:
–
DDRCTRL_PWRCTRL.selfref_en: to enter SR (SRE) after a number of idle cycle
–
DDRCTRL_PWRTMG.selfref_to_x32: number of idle clocks in multiple of 32 to
enter SR.
Software controlled SR: this mode is controlled by:
–
•
DDRCTRL_PWRCTRL.selfref_sw: setting this bit is referred as software
self_refresh entry.
Hardware controlled SR: this mode is supported by:
–
The FSM external to the DDRCTRL and under the control of RCC (refer to
Section 10: Reset and clock control (RCC) for mode details). When the SoC goes
into Stop mode, the DDRCTRL can put the SDRAM into self-refresh.
Deep power down: (DPD)
Note:
DPD is applicable only to LPDDR2/3.
This power saving opportunity may be supported but does not present any significant
interest because the SDRAM content is lost during DPD, practically DPD is not different
from shutting down DDR
DDR3 DLL off mode:
The DDR3 DLL off mode may be supported at low frequencies, it requires MRS (MR1[0] =1)
to disable DLL (by default DLL are on). It should use the software clock removal sequence:
Write 0 to DDRC_PCTRLn.port_en //to block AXI port n
Poll DDRC_PSTAT.rd_port_busy = 0
Poll DDRC_PSTAT.wr_port_busy = 0
Write 1 to DDRC_PWRCTL.selref_en // move to self-refresh
Poll DDRC_PSTAT.selfref_type = 2b10
... change AXI and DDRC clocks to lower value used w/ DLL OFF
... MRS to disable DLL
Write 0 to DDRC_PWRCTL.selref_en // exit self-refresh
Poll DDRC_PSTAT.selfref_type = 2b00
Write 1 to DDRC_PCTRLn.port_en // to unlock AXI ports
DDRPHY DLL bypass mode:
It is possible to disable DDRPHYC DLL’s to save significant power at low frequencies; this
mode must be controlled by software. The software sequence transitions SDRAM to Selfrefresh during which clock frequency change is possible.
5.5.4
Address mapper
The DDRCTRL address mapper is converting the AXI port read and write request into row,
bank, column SDRAM address at XPI level.
The address mapping is very flexible and defined according to DDR_ADDRMAP1 to
DDR_ADDRMAP11 register settings.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
The usual non interleaved Row/Bank/Column (RBC) and Bank/Row/Column (BRC) can be
simply programmed according to SDRAM architecture (row/bank/column) and full or half
width interface mode.
5.5.5
DRAM timing parameters
The DDRCTRL schedule commands to SDRAM according to multiple timings constrains as
programmed in registers DDRCTRL_DRAMTMGn according to SDRAM JEDEC timing
parameters versus frequency.
The following registers are related to timings constrains
5.5.6
–
DDRCTRL_DRAMTMG0 to DDRCTRL_DRAMTMG14
–
DDRCTRL_ODTTMG
–
DDRCTRL_DFITMG0 and DDRCTRL_DFITMG1
SDRAM initialization sequence
The initialization is controlled by the DDRPHYC supporting a PUBL built-in initialization
sequence for each DDR type and triggered by PIR registers. For more information see
Section 7: DDR physical interface control (DDRPHYC).
5.5.7
Refresh controls
The refresh can be issued using the auto-refresh feature in DDRCTRL or using the direct
software request of the refresh command. DDRCTRL_RFSHCTL3.dis_auto_refresh selects
the refresh method. When this bit is set to 1, uMCTL2 uses direct software request of
refresh command. When it is set to 0, the internal auto-refresh feature is used.
Refresh using the direct software request of refresh command
Follow the steps to put the DDRCTRL in direct software request of refresh command mode:
1.
Set DDRCTRL_RFSHCTL3.dis_auto_refresh bit to 1. When the register bit set,
DDRCTRL checks for any pending refreshes. Any pending refreshes are issued right
away using the ‘critical refresh’ feature inside DDRCTRL. After these refreshes are
issued, all the refresh timers inside DDRCTRL are reset to 0. They are re-activated
only when the auto-refresh feature is enabled.
2.
The SoC core must keep track of the refresh requirements of the SDRAM.
3.
The refresh command can be issued by setting the register bits
DDRCTRL_DBGCMD.rank0_refresh to 1. When the refresh request is stored, the
corresponding register bit is automatically cleared. The SoC core can initiate a refresh
operation only if DDRCTRL_DBGSTAT.rank0_refresh_busy is low. DDRCTRL issues
refresh to the SDRAM at the earliest.
4.
Software-driven refresh commands are loaded into a 9-entry buffer, and are issued by
DDRCTRL on the DFI as soon as it is legal to do so. If the buffer saturates, the
DBGSTAT.rank0_refresh_busy remains asserted to prevent software from initiating
further refreshes.
Refresh using the auto refresh feature inside DDRCTRL
The DDRCTRL provides advanced refresh controls. Besides fully-configurable refresh
constraints (tRFC(min) and tREFI), it can also be programmed to gather refreshes to each
rank of SDRAM to reduce the bandwidth consumed by refreshes and to increase the
likelihood that refreshes can be serviced during an idle period.
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The following registers are related to refresh controls:
–
DDRCTRL_RFSHCTL0
–
DDRCTRL_RFSHCTL3
–
DDRCTRL_RFSHTMG
The purposes of refresh control are to:
•
reduce the bandwidth impact of refresh cycles
•
increase the likelihood of refreshes being serviced during idle periods
•
provide fine-gain control of the trading-off the above benefits (to gather refreshes)
versus the increased worst case latencies associated with gathering refreshes
For more information, refer to the register description; besides issuing refresh at regular
intervals according to tRFC(min) and tREFI, several optimization options are possible: Burst
refresh, Speculative refresh, and Per-bank refresh (applicable to LPDDR2/3).
5.5.8
ZQ calibration
This feature is applicable to all DDR types. The DDRCTRL can use the ZQ calibration
command to calibrate the SDRAM RON (resistor ON) and ODT (on-die termination) values
over PVT (process, voltage, temperature).
The DDRPHYC supports the RON and ODT calibration at initialization; for more information
see Section 7: DDR physical interface control (DDRPHYC).
The DDRCTRL may issue periodic calibrations which take less time at regular interval.
(ZQCS).
The DDRCTRL may also issue a long calibration (ZQCL) after self-refresh exit
The following registers are related to ZQ calibration controls:
–
DDRCTRL_ZQCTL0
–
DDRCTRL_ZQCTL1
–
DDRCTRL_ZQCTL2
–
DDRCTRL_ZQSTAT
For more information on ZQ Calibration, refer to JEDEC specifications of the corresponding
SDRAM.
5.6
DDRCTRL configuration
The DDRCTRL is a configuration of uMTCL2 with these major hardware configuration
options:
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–
DDR mode support: DDR3/LPDDR2/LPDDR3
–
Frequency ratio: 1:1
–
Arbiter: include port arbiter (PA) with 2 AXI ports
–
Partial write support
–
CAM depth:16
–
No dual HIF
–
Variable priority read and variable priority write
–
Dual read address queue per port
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7
DDRCTRL registers
The DDRCTRL is configured to support DDR3/LPDDR2/LPDDR3. In the following register
description section, ignore all references to other standards (mDDR, DDR2, DDR4,
LPDDR4) as not being applicable.
Several register values depend on DDRCTRL configuration according to:
•
Include arbiter (UMCTL2_INCL_ARB = 1)
•
Partial write support (UMTCL2__PARTIAL_WR = 1)
•
Variable priority read (UMCTL2_VPR_EN = 1)
•
Variable priority write (UMCTL2_VPW_EN = 1)
The DDRCTRL registers are accessed only by words (32-bit).
R/W access to unmapped registers causes an APB SLVERR.
Write access to read-only registers is ignored without causing an APB SLVERR.
The Programming mode tag in the bit field describes how the field can be programmed
according to:
•
Static: the bit field is written only before DDRCTRL reset is released.
•
Dynamic: the bit field may be written during run time.
•
Quasi-dynamic: the bit field may be written during run time under special conditions
and procedure (described in Section 5.4.5: APB Interface (APB)).
Quarter bus width (MSTR.data_bus_width = 10) is not supported.
For register summary see: Table 19 on page 296.
5.7.1
DDRCTRL master register 0 (DDRCTRL_MSTR)
Address offset: 0x000
30
29
28
27
26
25
24
23
22
21
20
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
EN_2T_TIMING_MODE
BURSTCHOP
Res.
Res.
Res.
Res.
Res.
LPDDR3
LPDDR2
Res.
DDR3
rw
rw
rw
rw
rw
DATA_BUS_WIDTH[1:0]
31
Res.
DLL_OFF_MODE
Reset value: 0x0004 0001
rw
rw
19
18
17
16
BURST_RDWR[3:0]
rw
Bits 31:20 Reserved, must be kept at reset value.
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Bits 19:16 BURST_RDWR[3:0]: SDRAM burst length used:
- 0001 - Burst length of 2 (only supported for mDDR)
- 0010 - Burst length of 4
- 0100 - Burst length of 8
- 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4)
All other values are reserved.
This controls the burst size used to access the SDRAM. This must match the burst length mode
register setting in the SDRAM. (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to
0x0100) The burst length of 2 is not supported with the AXI ports when
MEMC_BURST_LENGTH is 8.
The burst length of 2 is only supported when the controller is operating in 1:1 frequency mode.
For DDR3, DDR4 and LPDDR3, this must be set to 0x0100 (BL8).
For LPDDR4, this must be set to 0x1000 (BL16).
Programming mode: Static
Bit 15 DLL_OFF_MODE: Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for
low frequency operation.
Set to 0 to put DDRCTRL and DRAM in DLL-on mode for normal frequency operation.
If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), dll_off_mode
is not supported, and this bit must be set to '0'.
Programming mode: Quasi-dynamic Group 2
Bit 14 Reserved, must be kept at reset value.
Bits 13:12 DATA_BUS_WIDTH[1:0]: Selects proportion of DQ bus width that is used by the SDRAM
- 00 - Full DQ bus width to SDRAM
- 01 - Half DQ bus width to SDRAM
- 10 - Reserved
- 11 - Reserved
Programming mode: Static
Bit 11 Reserved, must be kept at reset value.
Bit 10 EN_2T_TIMING_MODE: If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In
2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus.
The chip select is asserted on the second cycle of the command
Note: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode
Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set
Note: 2T timing is not supported in DDR4 geardown mode.
Note: 2T timing is not supported in Shared-AC dual channel mode and the register value is
don't care.
Programming mode: Static
Bit 9 BURSTCHOP: When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. The burstchop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in
full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16.
The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1)
and if CRC is disabled (CRCPARCTL1.crc_enable = 0).
The BC4 (fixed) mode is not supported.
Programming mode: Static
Bits 8:4 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bit 3 LPDDR3: Selects LPDDR3 SDRAM
- 1 - LPDDR3 SDRAM device in use.
- 0 - non-LPDDR3 device in use
Present only in designs configured to support LPDDR3.
Programming mode: Static
Bit 2 LPDDR2: Selects LPDDR2 SDRAM
- 1 - LPDDR2 SDRAM device in use.
- 0 - non-LPDDR2 device in use
Present only in designs configured to support LPDDR2.
Programming mode: Static
Bit 1 Reserved, must be kept at reset value.
Bit 0 DDR3: Selects DDR3 SDRAM
- 1 - DDR3 SDRAM device in use
- 0 - non-DDR3 SDRAM device in use
Only present in designs that support DDR3.
Programming mode: Static
5.7.2
DDRCTRL operating mode status register (DDRCTRL_STAT)
Address offset: 0x004
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
r
r
OPERATING_MODE[2:0]
30
Res.
SELFREF_TYPE[1:0]
31
Res.
SELFREF_CAM_NOT_EMPTY
Reset value: 0x0000 0000
Res.
r
r
r
r
Bits 31:13 Reserved, must be kept at reset value.
Bit 12 SELFREF_CAM_NOT_EMPTY: Self refresh with CAMs not empty. Set to 1 when Self Refresh
is entered but CAMs are not drained. Cleared after exiting Self Refresh.
Programming mode: Dynamic
Bits 11:6 Reserved, must be kept at reset value.
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Bits 5:4 SELFREF_TYPE[1:0]: Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is
entered and if it was under Automatic Self Refresh control only or not.
- 00 - SDRAM is not in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is
enabled by CRCPARCTRL1.crc_parity_retry_enable, this also indicates SRE command is still
in parity error window or retry is in-progress.
- 11 - SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was
caused by Automatic Self Refresh only. If retry is enabled, this guarantees SRE command is
executed correctly without parity error.
- 10 - SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was
not caused solely under Automatic Self Refresh control. It could have been caused by
Hardware Low-power Interface and/or Software (PWRCTL.selfref_sw). If retry is enabled, this
guarantees SRE command is executed correctly without parity error.
- 01 - SDRAM is in Self Refresh, which was caused by PHY Master Request.
Programming mode: Dynamic
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 OPERATING_MODE[2:0]: Operating mode. This is 3-bits wide in configurations with
mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations.
Condition non-mDDR/LPDDR2/LPDDR3/LPDDR4 and non-DDR4 designs:
- 000 - Init
- 001 - Normal
- 010 - Power-down
- 011 - Self refresh
Condition mDDR/LPDDR2/LPDDR3 or DDR4 designs:
- 000 - Init
- 001 - Normal
- 010 - Power-down
- 011 - Self refresh
- 1XX - Deep power-down / Maximum Power Saving Mode
Condition LPDDR4 designs:
- 000 - Init
- 001 - Normal
- 010 - Power-down
- 011 - Self refresh / Self refresh power-down
Programming mode: Dynamic
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5.7.3
DDRCTRL mode register read/write control register 0
(DDRCTRL_MRCTRL0)
Address offset: 0x010
Reset value: 0x0000 0010
Mode Register Read/Write Control Register 0.
Note:
Do not enable more than one of the following fields simultaneously:
•
•
•
sw_init_int
pda_en
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MR_WR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MR_TYPE
mpr_en
rs
15
MR_ADDR[3:0]
rw
rw
rw
rw
rw
Bit 31 MR_WR: Setting this register bit to 1 triggers a mode register read or write operation. When the
MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields
of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is
recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.
Programming mode: Dynamic
Bits 30:16 Reserved, must be kept at reset value.
Bits 15:12 MR_ADDR[3:0]: Address of the mode register that is to be written to.
- 0000 - MR0
- 0001 - MR1
- 0010 - MR2
- 0011 - MR3
- 0100 - MR4
- 0101 - MR5
- 0110 - MR6
- 0111 - MR7
Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register
addressing in LPDDR2/LPDDR3/LPDDR4)
This signal is also used for writing to control words of the register chip on RDIMMs/LRDIMMs.
In that case, it corresponds to the bank address bits sent to the RDIMM/LRDIMM
In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well as
the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring
of UDIMMs/RDIMMs/LRDIMMs and the Output Inversion of RDIMMs/LRDIMMs.
Programming mode: Dynamic
Bits 11:5 Reserved, must be kept at reset value.
Bits 4:1 Reserved, must be kept at reset value.
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Bit 0 MR_TYPE: Indicates whether the mode register operation is read or write. Only used for
LPDDR2/LPDDR3/LPDDR4/DDR4.
- 0 - Write, MRCTRL register does not support MR read for LPDDR2/3
- 1 - Reserved
Programming mode: Dynamic
5.7.4
DDRCTRL mode register read/write control register 1
(DDRCTRL_MRCTRL1)
Address offset: 0x014
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
MR_DATA[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 MR_DATA[15:0]: Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4
modes.
For LPDDR2/LPDDR3/LPDDR4, MRCTRL1[15:0] are interpreted as
[15:8] MR Address
[7:0] MR data for writes, don't care for reads. This is 18-bits wide in configurations with DDR4
support and 16-bits in all other configurations.
Programming mode: Dynamic
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.5
DDRCTRL mode register read/write status register
(DDRCTRL_MRSTAT)
Address offset: 0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MR_WR_BUSY
Reset value: 0x0000 0000
r
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 MR_WR_BUSY: The SoC core may initiate a MR write operation only if this signal is low. This
signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low
when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform
MRW/MRR commands when 'MRSTAT.mr_wr_busy' is high.
- 0 - Indicates that the SoC core can initiate a mode register write operation
- 1 - Indicates that mode register write operation is in progress
Programming mode: Dynamic
5.7.6
DDRCTRL temperature derate enable register
(DDRCTRL_DERATEEN)
Address offset: 0x020
Reset value: 0x0000 0000
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
Res.
rw
rw
DERATE_ENABLE
DERATE_BYTE[3:0]
DERATE_VALUE[1:0]
31
Res.
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
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Bits 7:4 DERATE_BYTE[3:0]: Derate byte
Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
Indicates which byte of the MRR data is used for derating. The maximum valid value depends
on MEMC_DRAM_TOTAL_DATA_WIDTH.
Programming mode: Static
Bit 3 Reserved, must be kept at reset value.
Bits 2:1 DERATE_VALUE[1:0]: Derate value
- 0 - Derating uses +1.
- 1 - Derating uses +2.
Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a
core_ddrc_core_clk period.
For LPDDR3/4, if the period of core_ddrc_core_clk is less than 1.875ns, this register field
should be set to 1; otherwise it should be set to 0.
Programming mode: Quasi-dynamic Group 2 and Group 4
Bit 0 DERATE_ENABLE: Enables derating
- 0 - Timing parameter derating is disabled
- 1 - Timing parameter derating is enabled using MR4 read value.
Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
Programming mode: Dynamic
5.7.7
DDRCTRL temperature derate interval register
(DDRCTRL_DERATEINT)
Address offset: 0x024
Reset value: 0x0080 0000
31
30
29
28
27
26
25
24
23
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
rw
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
MR4_READ_INTERVAL[31:16]
MR4_READ_INTERVAL[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 MR4_READ_INTERVAL[31:0]: Interval between two MR4 reads, used to derate the timing
parameters.
Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must
not be set to zero.
Unit: DFI clock cycle.
Programming mode: Static
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5.7.8
DDRCTRL low power control register (DDRCTRL_PWRCTL)
Address offset: 0x030
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DIS_CAM_DRAIN_SELFREF
Res.
SELFREF_SW
Res.
EN_DFI_DRAM_CLK_DISABLE
DEEPPOWERDOWN_EN
POWERDOWN_EN
SELFREF_EN
Reset value: 0x0000 0000
rw
rw
rw
rw
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 DIS_CAM_DRAIN_SELFREF: Indicates whether skipping CAM draining is allowed when
entering Self-Refresh.
This register field cannot be modified while PWRCTL.selfref_sw==1.
- 0 - CAMs must be empty before entering SR
- 1 - CAMs are not emptied before entering SR (unsupported)
Note, PWRCTL.dis_cam_drain_selfref=1 is unsupported in this release.
PWRCTL.dis_cam_drain_selfref=0 is required.
Programming mode: Dynamic
Bit 6 Reserved, must be kept at reset value.
Bit 5 SELFREF_SW: A value of 1 to this register causes system to move to Self Refresh state
immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as
Software Entry/Exit to Self Refresh.
- 1 - Software Entry to Self Refresh
- 0 - Software Exit from Self Refresh
Programming mode: Dynamic
Bit 4 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Bit 3 EN_DFI_DRAM_CLK_DISABLE: Enable the assertion of dfi_dram_clk_disable whenever a
clock is not required by the SDRAM.
If set to 0, dfi_dram_clk_disable is never asserted.
Assertion of dfi_dram_clk_disable is as follows:
In DDR2/DDR3, can only be asserted in Self Refresh.
In DDR4, can be asserted in following:
- in Self Refresh.
- in Maximum Power Saving Mode
In mDDR/LPDDR2/LPDDR3, can be asserted in following:
- in Self Refresh
- in Power Down
- in Deep Power Down
- during Normal operation (Clock Stop)
In LPDDR4, can be asserted in following:
- in Self Refresh Power Down
- in Power Down
- during Normal operation (Clock Stop)
Programming mode: Dynamic
Bit 2 DEEPPOWERDOWN_EN: When this is 1, DDRCTRL puts the SDRAM into deep power-down
mode when the transaction store is empty.
This register must be reset to '0' to bring DDRCTRL out of deep power-down mode. Controller
performs automatic SDRAM initialization on deep power-down exit.
Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For nonmDDR/non-LPDDR2/non-LPDDR3, this register should not be set to 1.
For performance only
Programming mode: Dynamic
Bit 1 POWERDOWN_EN: If true then the DDRCTRL goes into power-down after a programmable
number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32).
This register bit may be re-programmed during the course of normal operation.
Programming mode: Dynamic
Bit 0 SELFREF_EN: If true then the DDRCTRL puts the SDRAM into Self Refresh after a
programmable number of cycles "maximum idle clocks before Self Refresh
(PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of
normal operation.
Programming mode: Dynamic
5.7.9
DDRCTRL low power timing register (DDRCTRL_PWRTMG)
Address offset: 0x034
Reset value: 0x0040 2010
31
30
29
28
27
26
25
24
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T_DPD_X4096[7:0]
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17
16
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SELFREF_TO_X32[7:0]
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RM0442 Rev 7
POWERDOWN_TO_X32[4:0]
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RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:16 SELFREF_TO_X32[7:0]: After this many clocks of the DDRC command channel being idle the
DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is
considered idle when there are no HIF commands outstanding. This must be enabled in the
PWRCTL.selfref_en.
Unit: Multiples of 32 DFI clocks.
For performance only.
Programming mode: Quasi-dynamic Group 4
Bits 15:8 T_DPD_X4096[7:0]: Minimum deep power-down time.
For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down
mode immediately after PWRCTL.deeppowerdown_en is de-asserted.
For LPDDR2/LPDDR3, value from the JEDEC specification is 500 us.
Unit: Multiples of 4096 DFI clocks.
Present only in designs configured to support mDDR, LPDDR2 or LPDDR3.
For performance only.
Programming mode: Quasi-dynamic Group 4
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 POWERDOWN_TO_X32[4:0]: After this many clocks of the DDRC command channel being
idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command
channel is considered idle when there are no HIF commands outstanding. This must be
enabled in the PWRCTL.powerdown_en.
Unit: Multiples of 32 DFI clocks
For performance only.
Programming mode: Quasi-dynamic Group 4
5.7.10
DDRCTRL hardware low power control register
(DDRCTRL_HWLPCTL)
Address offset: 0x038
30
29
28
Res.
Res.
Res.
27
26
25
24
23
22
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15
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13
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11
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9
8
7
6
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20
19
18
17
16
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5
4
3
2
1
0
Res.
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HW_LP_EN
31
Res.
HW_LP_EXIT_IDLE_EN
Reset value: 0x0000 0003
21
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HW_LP_IDLE_X32[11:0]
Bits 31:28 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Bits 27:16 HW_LP_IDLE_X32[11:0]: Hardware idle period. The cactive_ddrc output is driven low if the
DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM
operating_mode. The DDRC command channel is considered idle when there are no HIF
commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0.
Unit: Multiples of 32 DFI clocks.
For performance only.
Programming mode: Static
Bits 15:2 Reserved, must be kept at reset value.
Bit 1 HW_LP_EXIT_IDLE_EN: When this bit is programmed to 1 the cactive_in_ddrc pin of the
DDRC can be used to exit from the automatic clock stop, automatic power down or automatic
self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware
Low power interface and/or software (PWRCTL.selfref_sw).
Programming mode: Static
Bit 0 HW_LP_EN: Enable for hardware low power interface.
Programming mode: Quasi-dynamic Group 3
5.7.11
DDRCTRL refresh control register 0 (DDRCTRL_RFSHCTL0)
Address offset: 0x050
31
30
29
28
27
26
25
24
Res.
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Res.
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15
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11
10
9
8
Res.
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Res.
REFRESH_TO_X32[3:0]
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23
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REFRESH_MARGIN[3:0]
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4
REFRESH_BURST[4:0]
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19
18
17
16
Res.
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REFRE
SH_TO
_X32[4]
3
2
1
0
Res.
PER_BANK_REFRESH
Reset value: 0x0021 0000
Res.
Res.
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Bits 31:24 Reserved, must be kept at reset value.
Bits 23:20 REFRESH_MARGIN[3:0]: Threshold value in number of DFI clock cycles before the critical
refresh or page timer expires. A critical refresh is to be issued before this threshold is reached.
It is recommended that this not be changed from the default value, currently shown as 0x2. It
must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is
equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If
RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only),
internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in
LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is
enabled (DERATEEN.derate_enable=1).
Unit: Multiples of 32 DFI clocks.
Programming mode: Dynamic - Refresh Related
Bits 19:17 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bits 16:12 REFRESH_TO_X32[4:0]: If the refresh timer (tRFCnom, also known as tREFI) has expired at
least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative
refresh may be performed. A speculative refresh is a refresh performed at a time when refresh
would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period
of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at
least once since the last refresh, then a speculative refresh is performed. Speculative refreshes
continues successively until there are no refreshes pending or until new reads or writes are
issued to the DDRCTRL.
For performance only.
Unit: Multiples of 32 DFI clocks.
Programming mode: Dynamic - Refresh Related
Bits 11:9 Reserved, must be kept at reset value.
Bits 8:4 REFRESH_BURST[4:0]: The programmed value + 1 is the number of refresh timeouts that is
allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing
pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes.
Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page
closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower
numbers decreases the worst-case latency associated with refreshes.
- 0 - single refresh
- 1 - burst-of-2 refresh
- 7 - burst-of-8 refresh
For information on burst refresh feature refer to section 3.9 of DDR2 JEDEC specification JESD79-2F.pdf.
For DDR2/3, the refresh is always per-rank and not per-bank. The rank refresh can be
accumulated over 8*tREFI cycles using the burst refresh feature.
In DDR4 mode, according to Fine Granularity feature, 8 refreshes can be postponed in 1X
mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates,
care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not
violated due to a PHY-initiated update occurring shortly before a refresh burst was due. In this
situation, the refresh burst is delayed until the PHY-initiated update is complete.
Programming mode: dynamic - refresh related
Bit 3 Reserved, must be kept at reset value.
Bit 2 PER_BANK_REFRESH:
- 1 - Per bank refresh;
- 0 - All bank refresh.
Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all
LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in
designs configured to support LPDDR2/LPDDR3/LPDDR4
Programming mode: Static
Bits 1:0 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.12
RM0442
DDRCTRL refresh control register 3 (DDRCTRL_RFSHCTL3)
Address offset: 0x060
31
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29
28
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24
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22
21
20
19
18
17
16
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REFRESH_UPDATE_LEVEL
DIS_AUTO_REFRESH
Reset value: 0x0000 0000
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Bits 31:2 Reserved, must be kept at reset value.
Bit 1 REFRESH_UPDATE_LEVEL: Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate
that the refresh register(s) have been updated.
refresh_update_level must not be toggled when the DDRC is in reset (core_ddrc_rstn = 0).
The refresh register(s) are automatically updated when exiting reset.
Programming mode: Dynamic
Bit 0 DIS_AUTO_REFRESH: When '1', disable auto-refresh generated by the DDRCTRL. When
auto-refresh is disabled, the SoC core must generate refreshes using the registers
DBGCMD.rankn_refresh.
When dis_auto_refresh transitions from 0 to 1, any pending refreshes are immediately
scheduled by the DDRCTRL.
If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable autorefresh is not supported, and this bit must be set to '0'.
(DDR4 only) If FGR mode is enabled (RFSHCTL3.refresh_mode > 0), disable auto-refresh is
not supported, and this bit must be set to '0'.
This register field is changeable on the fly.
Programming mode: Dynamic - Refresh Related
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.13
DDRCTRL refresh timing register (DDRCTRL_RFSHTMG)
Address offset: 0x064
31
30
29
28
T_RFC_NOM_X1_SE
L
Res.
Res.
Res.
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15
14
13
12
11
10
9
8
7
6
5
LPDDR3_TREFBW_EN
Reset value: 0x0062 008C
Res.
Res.
Res.
Res.
Res.
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27
26
25
24
23
22
21
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19
18
17
16
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4
3
2
1
0
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T_RFC_NOM_X1_X32[11:0]
T_RFC_MIN[9:0]
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Bit 31 T_RFC_NOM_X1_SEL: Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32.
Programming mode: Dynamic - Refresh Related
Bits 30:28 Reserved, must be kept at reset value.
Bits 27:16 T_RFC_NOM_X1_X32[11:0]: tREFI: Average time interval between refreshes per rank
(Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR,
LPDDR2, LPDDR3 and LPDDR4).
For LPDDR2/LPDDR3/LPDDR4:
- If using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0), this register should be set to
tREFIab
- If using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should be set to
tREFIpb
When the controller is operating in 1:2 frequency ratio mode, program this to (tREFI/2), no
rounding up.
In DDR4 mode, tREFI value is different depending on the refresh mode. The user should
program the appropriate value from the spec based on the value programmed in the refresh
mode register.
Note that if RFSHTMG.t_rfc_nom_x1_sel == 1, RFSHTMG.t_rfc_nom_x1_x32 must be greater
than RFSHTMG.t_rfc_min; if RFSHTMG.t_rfc_nom_x1_sel == 0, RFSHTMG.t_rfc_nom_x1_x32
* 32 must be greater than RFSHTMG.t_rfc_min; RFSHTMG.t_rfc_nom_x1_x32 must be greater
than 0x1.
- Non-DDR4 or DDR4 Fixed 1x mode: RFSHTMG.t_rfc_nom_x1_x32 must be less than or
equal to 0xFFE.
- DDR4 Fixed 2x mode: RFSHTMG.t_rfc_nom_x1_x32 must be less than or equal to 0x7FF.
- DDR4 Fixed 4x mode: RFSHTMG.t_rfc_nom_x1_x32 must be less than or equal to 0x3FF.
Unit: Clocks or multiples of 32 clocks, depending on RFSHTMG.t_rfc_nom_x1_sel.
Programming mode: Dynamic - Refresh Related
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Bit 15 LPDDR3_TREFBW_EN: Used only when LPDDR3 memory type is connected. Should only be
changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter
(required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC
specification) or not:
- 0 - tREFBW parameter not used
- 1 - tREFBW parameter used
Programming mode: Static
Bits 14:10 Reserved, must be kept at reset value.
Bits 9:0 T_RFC_MIN[9:0]: tRFC (min): Minimum time from refresh to refresh or activate.
When the controller is operating in 1:1 mode, t_rfc_min should be set to
RoundUp(tRFCmin/tCK).
When the controller is operating in 1:2 mode, t_rfc_min should be set to
RoundUp(RoundUp(tRFCmin/tCK)/2).
In LPDDR2/LPDDR3/LPDDR4 mode:
- If using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab
- If using per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb
In DDR4 mode, the tRFCmin value in the above equations is different depending on the refresh
mode (fixed 1X,2X,4X) and the device density. The user should program the appropriate value
from the spec based on the 'refresh_mode' and the device density that is used.
Unit: Clocks.
Programming mode: Dynamic - Refresh Related
5.7.14
DDRCTRL CRC parity control register 0 (DDRCTRL_CRCPARCTL0)
Address offset: 0x0C0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
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Res.
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Res.
Res.
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11
10
9
8
7
6
5
4
3
2
1
0
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Res.
Res.
DFI_ALERT_ERR_CNT_CLR
DFI_ALERT_ERR_INT_CLR
DFI_ALERT_ERR_INT_EN
Reset value: 0x0000 0000
rc_w1
rc_w1
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Bits 31:3 Reserved, must be kept at reset value.
Bit 2 DFI_ALERT_ERR_CNT_CLR: DFI alert error count clear. Clear bit for DFI alert error counter.
Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the
clear operation is complete, the DDRCTRL automatically clears this bit.
Programming mode: Dynamic
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bit 1 DFI_ALERT_ERR_INT_CLR: Interrupt clear bit for DFI alert error. If this bit is set, the alert
error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is
complete, the DDRCTRL automatically clears this bit.
Programming mode: Dynamic
Bit 0 DFI_ALERT_ERR_INT_EN: Interrupt enable bit for DFI alert error. If this bit is set, any
parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on
CRCPARSTAT.dfi_alert_err_int.
Programming mode: Dynamic
5.7.15
DDRCTRL CRC parity status register (DDRCTRL_CRCPARSTAT)
Address offset: 0x0CC
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
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Res.
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Res.
Res.
Res.
Res.
Res.
Res.
Res.
DFI_ALERT_ERR_INT
Reset value: 0x0000 0000
15
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3
2
1
0
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DFI_ALERT_ERR_CNT[15:0]
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Bits 31:17 Reserved, must be kept at reset value.
Bit 16 DFI_ALERT_ERR_INT: DFI alert error interrupt.
If a parity/CRC error is detected on dfi_alert_n, and the interrupt is enabled by
CRCPARCTL0.dfi_alert_err_int_en, this interrupt bit is set. It remains set until cleared by
CRCPARCTL0.dfi_alert_err_int_clr
Programming mode: Static
Bits 15:0 DFI_ALERT_ERR_CNT[15:0]: DFI alert error count.
If a parity/CRC error is detected on dfi_alert_n, this counter be incremented. This is
independent of the setting of CRCPARCTL0.dfi_alert_err_int_en. It saturates at 0xFFFF, and
can be cleared by asserting CRCPARCTL0.dfi_alert_err_cnt_clr.
Programming mode: Static
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.16
RM0442
DDRCTRL SDRAM initialization register 0 (DDRCTRL_INIT0)
Address offset: 0x0D0
Reset value: 0x0002 004E
30
SKIP_DRAM_INIT[1:0]
31
29
28
27
26
Res.
Res.
Res.
Res.
11
10
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15
14
13
12
Res.
Res.
Res.
Res.
25
24
23
22
21
20
19
18
17
16
POST_CKE_X1024[9:0]
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9
8
7
6
5
4
3
2
1
0
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PRE_CKE_X1024[11:0]
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Bits 31:30 SKIP_DRAM_INIT[1:0]: If lower bit is enabled the SDRAM initialization routine is skipped. The
upper bit decides what state the controller starts up in when reset is removed
- 00 - SDRAM Initialization routine is run after power-up
- 01 - SDRAM Initialization routine is skipped after power-up. Controller starts up in Normal
Mode
- 11 - SDRAM Initialization routine is skipped after power-up. Controller starts up in Self-refresh
Mode
- 10 - Reserved.
Programming mode: Quasi-dynamic Group 2
Bits 29:26 Reserved, must be kept at reset value.
Bits 25:16 POST_CKE_X1024[9:0]: Cycles to wait after driving CKE high to start the SDRAM initialization
sequence.
Unit: 1024 DFI clock cycles.
DDR2 typically requires a 400 ns delay, requiring this value to be programmed to 2 at all clock
speeds.
LPDDR2/LPDDR3 typically requires this to be programmed for a delay of 200 us.
LPDDR4 typically requires this to be programmed for a delay of 2 us.
When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec
value divided by 2, and round it up to the next integer value.
Programming mode: Static
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 PRE_CKE_X1024[11:0]: Cycles to wait after reset before driving CKE high to start the SDRAM
initialization sequence.
Unit: 1024 DFI clock cycles.
DDR2 specifications typically require this to be programmed for a delay of >= 200 us.
LPDDR2/LPDDR3: tINIT1 of 100 ns (min)
LPDDR4: tINIT3 of 2 ms (min)
When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec
value divided by 2, and round it up to the next integer value.
For DDR3/DDR4 RDIMMs, this should include the time needed to satisfy tSTAB
Programming mode: Static
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RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.17
DDRCTRL SDRAM initialization register 1 (DDRCTRL_INIT1)
Address offset: 0x0D4
Reset value: 0x0000 0000
31
30
29
28
27
26
25
Res.
Res.
Res.
Res.
Res.
Res.
Res.
24
23
22
21
20
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rw
15
14
13
12
11
10
9
8
7
6
5
4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
19
18
17
16
rw
rw
rw
rw
3
2
1
0
DRAM_RSTN_X1024[8:0]
PRE_OCD_X32[3:0]
rw
rw
rw
rw
Bits 31:25 Reserved, must be kept at reset value.
Bits 24:16 DRAM_RSTN_X1024[8:0]: Number of cycles to assert SDRAM reset signal during init
sequence.
This is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. For use with a
DDR PHY, this should be set to a minimum of 1.
When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec
value divided by 2, and round it up to the next integer value.
Unit: 1024 DFI clock cycles.
Programming mode: Static
Bits 15:4 Reserved, must be kept at reset value.
Bits 3:0 PRE_OCD_X32[3:0]: Wait period before driving the OCD complete command to SDRAM.
Unit: Counts of a global timer that pulses every 32 DFI clock cycles.
There is no known specific requirement for this; it may be set to zero.
Programming mode: Static
5.7.18
DDRCTRL SDRAM initialization register 2 (DDRCTRL_INIT2)
Address offset: 0x0D8
Reset value: 0x0000 0D05
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
rw
rw
rw
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IDLE_AFTER_RESET_X32[7:0]
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rw
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MIN_STABLE_CLOCK_X1[3:0]
31
Res.
Bits 31:16 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Bits 15:8 IDLE_AFTER_RESET_X32[7:0]: Idle time after the reset command, tINIT4. Present only in
designs configured to support LPDDR2.
When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec
value divided by 2, and round it up to the next integer value.
Unit: 32 DFI clock cycles.
Programming mode: Static
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 MIN_STABLE_CLOCK_X1[3:0]: Time to wait after the first CKE high, tINIT2. Present only in
designs configured to support LPDDR2/LPDDR3.
LPDDR2/LPDDR3 typically requires 5 x tCK delay.
When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec
value divided by 2, and round it up to the next integer value.
Unit: DFI clock cycles.
Programming mode: Static
5.7.19
DDRCTRL SDRAM initialization register 3 (DDRCTRL_INIT3)
Address offset: 0x0DC
Reset value: 0x0000 0510
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MR[15:0]
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rw
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rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
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rw
rw
rw
rw
rw
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EMR[15:0]
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rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 MR[15:0]: DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored.
The DDRCTRL sets this bit appropriately.
DDR3/DDR4: Value loaded into MR0 register.
mDDR: Value to write to MR register.
LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 register
Programming mode: Quasi-dynamic Group 1 and Group 4
Bits 15:0 EMR[15:0]: DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this
register is ignored. The DDRCTRL sets those bits appropriately.
DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is
enabled, this bit is set appropriately by the DDRCTRL during write leveling.
mDDR: Value to write to EMR register.
LPDDR2/LPDDR3/LPDDR4 - Value to write to MR2 register
Programming mode: Quasi-dynamic Group 4
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.20
DDRCTRL SDRAM initialization register 4 (DDRCTRL_INIT4)
Address offset: 0x0E0
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
EMR2[15:0]
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rw
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rw
rw
rw
rw
rw
rw
rw
rw
rw
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rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
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rw
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rw
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18
17
16
EMR3[15:0]
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rw
Bits 31:16 EMR2[15:0]: DDR2: Value to write to EMR2 register.
DDR3/DDR4: Value to write to MR2 register
LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register
mDDR: Unused
Programming mode: Quasi-dynamic Group 4
Bits 15:0 EMR3[15:0]: DDR2: Value to write to EMR3 register.
DDR3/DDR4: Value to write to MR3 register
mDDR/LPDDR2/LPDDR3: Unused
LPDDR4: Value to write to MR13 register
Programming mode: Quasi-dynamic Group 2 and Group 4
5.7.21
DDRCTRL SDRAM initialization register 5 (DDRCTRL_INIT5)
Address offset: 0x0E4
Reset value: 0x0010 0004
31
30
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
Res.
Res.
Res.
Res.
Res.
Res.
9
8
23
22
21
20
19
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
rw
DEV_ZQINIT_X32[7:0]
MAX_AUTO_INIT_X1024[9:0]
rw
rw
rw
rw
rw
rw
rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:16 DEV_ZQINIT_X32[7:0]: ZQ initial calibration, tZQINIT. Present only in designs configured to
support DDR3 or DDR4 or LPDDR2/LPDDR3.
DDR3 typically requires 512 SDRAM clock cycles.
DDR4 requires 1024 SDRAM clock cycles.
LPDDR2/LPDDR3 requires 1 us.
When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec
value divided by 2, and round it up to the next integer value.
Unit: 32 DFI clock cycles.
Programming mode: Static
Bits 15:10 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Bits 9:0 MAX_AUTO_INIT_X1024[9:0]: Maximum duration of the auto initialization, tINIT5. Present
only in designs configured to support LPDDR2/LPDDR3.
LPDDR2/LPDDR3 typically requires 10 us.
Unit: 1024 DFI clock cycles.
Programming mode: Static
5.7.22
DDRCTRL DIMM control register (DDRCTRL_DIMMCTL)
Address offset: 0x0F0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DIMM_ADDR_MIRR_EN
DIMM_STAGGER_CS_EN
Reset value: 0x0000 0000
rw
rw
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 DIMM_ADDR_MIRR_EN: Address Mirroring Enable (for multi-rank UDIMM implementations
and multi-rank DDR4 RDIMM/LRDIMM implementations).
Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address mirroring for odd ranks,
which means that the following address, bank address and bank group bits are swapped: (A3,
A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this
bit ensures that, for mode register accesses during the automatic initialization routine, these
bits are swapped within the DDRCTRL to compensate for this UDIMM/RDIMM/LRDIMM
swapping. In addition to the automatic initialization routine, in case of DDR4
UDIMM/RDIMM/LRDIMM, they are swapped during the automatic MRS access to
enable/disable of a particular DDR4 feature.
Note: This has no effect on the address of any other memory accesses, or of software-driven
mode register accesses.
This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs.
Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0
because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1.
- 1 - For odd ranks, implement address mirroring for MRS commands to during initialization
and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM/LRDIMM
implements address mirroring)
- 0 - Do not implement address mirroring
Programming mode: Static
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bit 0 DIMM_STAGGER_CS_EN: Staggering enable for multi-rank accesses (for multi-rank UDIMM,
RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2,
LPDDR3 or LPDDR4 SDRAMs.
Note: Even if this bit is set it does not take care of software driven MR commands (via
MRCTRL0/MRCTRL1), where software is responsible to send them to separate ranks as
appropriate.
- 1 - (DDR4) Send MRS commands to each ranks separately
- 1 - (non-DDR4) Send all commands to even and odd ranks separately
- 0 - Do not stagger accesses
Programming mode: Static.
5.7.23
DDRCTRL SDRAM timing register 0 (DDRCTRL_DRAMTMG0)
Address offset: 0x100
Reset value: 0x0F10 1B0F
31
30
29
28
Res.
15
27
26
25
24
WR2PRE[6:0]
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rw
rw
rw
rw
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rw
14
13
12
11
10
9
8
Res.
T_RAS_MAX[6:0]
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rw
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rw
23
22
Res.
Res.
7
6
Res.
Res.
rw
21
20
19
18
17
16
T_FAW[5:0]
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5
4
3
2
1
0
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T_RAS_MIN[5:0]
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Bit 31 Reserved, must be kept at reset value.
Bits 30:24 WR2PRE[6:0]:
Minimum time between write and precharge to same bank.
Unit: Clocks
Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and
less for lower frequencies
where:
- WL = write latency
- BL = burst length. This must match the value programmed in the BL bit of the mode register
to the SDRAM. BST (burst terminate) is not supported at present.
- tWR = Write recovery time. This comes directly from the SDRAM specification.
Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this parameter.
When the controller is operating in 1:2 frequency ratio mode, 1T mode, divide the above value
by 2. No rounding up.
When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode,
divide the above value by 2 and round it up to the next integer value.
Note that, depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of
this parameter to compensate for the extra cycle of latency through the LRDIMM.
Programming mode: Quasi-dynamic Group 1 and Group 2 and Group 4.
Bits 23:22 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Bits 21:16 T_FAW[5:0]: tFAW Valid only when 8 or more banks(or banks x bank groups) are present.
In 8-bank design, at most 4 banks must be activated in a rolling window of tFAW cycles.
When the controller is operating in 1:2 frequency ratio mode, program this to (tFAW/2) and
round up to next integer value.
In a 4-bank design, set this register to 0x1 independent of the 1:1/1:2 frequency mode.
Unit: Clocks
Programming mode: Quasi-dynamic Group 2 and Group 4.
Bit 15 Reserved, must be kept at reset value.
Bits 14:8 T_RAS_MAX[6:0]: tRAS(max): Maximum time between activate and precharge to same bank.
This is the maximum time that a page can be kept open
Minimum value of this register is 1. Zero is invalid.
When the controller is operating in 1:2 frequency ratio mode, program this to (tRAS(max)-1)/2.
No rounding up.
Unit: Multiples of 1024 clocks.
Programming mode: Quasi-dynamic Group 2 and Group 4
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:0 T_RAS_MIN[5:0]: tRAS(min): Minimum time between activate and precharge to the same
bank.
When the controller is operating in 1:2 frequency mode, 1T mode, program this to tRAS(min)/2.
No rounding up.
When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode,
program this to (tRAS(min)/2) and round it up to the next integer value.
Unit: Clocks.
Programming mode: Quasi-dynamic Group 2 and Group 4.
5.7.24
DDRCTRL SDRAM timing register 1 (DDRCTRL_DRAMTMG1)
Address offset: 0x104
Reset value: 0x0008 0414
31
30
29
28
27
26
25
24
23
22
21
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
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15
14
13
12
11
10
9
8
7
6
5
4
3
Res.
Res.
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RD2PRE[5:0]
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rw
20
19
18
17
16
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2
1
0
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rw
T_XP[4:0]
Res.
T_RC[6:0]
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Bits 31:21 Reserved, must be kept at reset value.
Bits 20:16 T_XP[4:0]: tXP: Minimum time after power-down exit to any operation. For DDR3, this should
be programmed to tXPDLL if slow powerdown exit is selected in MR0[12].
If C/A parity for DDR4 is used, set to (tXP+PL) instead.
If LPDDR4 is selected and its spec has tCKELPD parameter, set to the larger of tXP and
tCKELPD instead.
When the controller is operating in 1:2 frequency ratio mode, program this to (tXP/2) and round
it up to the next integer value.
Units: Clocks.
Programming mode: Quasi-dynamic Group 2 and Group 4.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bits 15:14 Reserved, must be kept at reset value.
Bits 13:8 RD2PRE[5:0]: tRTP: Minimum time from read to precharge of same bank.
- DDR2: tAL + BL/2 + max(tRTP, 2) - 2
- DDR3: tAL + max (tRTP, 4)
- DDR4: Max of following two equations:
tAL + max (tRTP, 4) or,
RL + BL/2 - tRP (*).
- mDDR: BL/2
- LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4:
LPDDR2-S2: BL/2 + tRTP - 1.
LPDDR2-S4: BL/2 + max(tRTP,2) - 2.
- LPDDR3: BL/2 + max(tRTP,4) - 4
- LPDDR4: BL/2 + max(tRTP,8) - 8
(*) When both DDR4 SDRAM and ST-MRAM are used simultaneously, use SDRAM's tRP
value for calculation.
When the controller is operating in 1:2 mode, 1T mode, divide the above value by 2. No
rounding up.
When the controller is operating in 1:2 mode, 2T mode or LPDDR4 mode, divide the above
value by 2 and round it up to the next integer value.
Unit: Clocks.
Programming mode: Quasi-dynamic Group 1 and Group 2 and Group 4
Bit 7 Reserved, must be kept at reset value.
Bits 6:0 T_RC[6:0]: tRC: Minimum time between activates to same bank.
When the controller is operating in 1:2 frequency ratio mode, program this to (tRC/2) and round
up to next integer value.
Unit: Clocks.
Programming mode: Quasi-dynamic Group 2 and Group 4.
5.7.25
DDRCTRL SDRAM timing register 2 (DDRCTRL_DRAMTMG2)
Address offset: 0x108
Reset value: 0x0305 060D
31
30
Res.
Res.
15
14
Res.
Res.
29
28
27
rw
rw
rw
13
12
11
26
25
24
rw
rw
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10
9
8
WRITE_LATENCY[5:0]
RD2WR[5:0]
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rw
rw
rw
rw
23
22
Res.
Res.
7
6
Res.
Res.
rw
21
20
19
rw
rw
rw
5
4
3
18
17
16
rw
rw
rw
2
1
0
rw
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READ_LATENCY[5:0]
WR2RD[5:0]
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Bits 31:30 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Bits 29:24 WRITE_LATENCY[5:0]: Set to WL
The time from write command to write data on SDRAM interface. This must be set to WL.
For mDDR, it should normally be set to 1.
Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust the
value of WL to compensate for the extra cycle of latency through the RDIMM/LRDIMM.
When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using
the above equation by 2, and round it up to next integer.
This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as
the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those
protocols.
Unit: clocks.
Programming mode: Quasi-dynamic Group 1 and Group 2 and Group 4.
Bits 23:22 Reserved, must be kept at reset value.
Bits 21:16 READ_LATENCY[5:0]: Set to RL
The time from read command to read data on SDRAM interface. This must be set to RL.
Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust the
value of RL to compensate for the extra cycle of latency through the RDIMM/LRDIMM.
When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using
the above equation by 2, and round it up to next integer.
This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as
the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those
protocols.
Unit: clocks.
Programming mode: Quasi-dynamic Group 1 and Group 2 and Group 4.
Bits 15:14 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bits 13:8 RD2WR[5:0]:
DDR2/3/mDDR: RL + BL/2 + 2 - WL
DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL
LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL
LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE +
RD_POSTAMBLE - WL
LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE ODTLon - RU(tODTon(min)/tCK)
Minimum time from read command to write command. Include time for bus turnaround and all
per-bank, per-rank, and global constraints. Please see the relevant PHY databook for details of
what should be included here.
Unit: Clocks.
Where:
- WL = write latency
- BL = burst length. This must match the value programmed in the BL bit of the mode register
to the SDRAM
- RL = read latency = CAS latency
- WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4.
- RD_POSTAMBLE = read postamble. This is unique to LPDDR4.
For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated
tDQSCKmax should be used.
When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using
the above equation by 2, and round it up to next integer.
Note that, depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of
this parameter to compensate for the extra cycle of latency through the LRDIMM.
Programming mode: Quasi-dynamic Group 1 and Group 2 and Group 4
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:0 WR2RD[5:0]:
DDR4: CWL + PL + BL/2 + tWTR_L
LPDDR2/3/4: WL + BL/2 + tWTR + 1
Others: CWL + BL/2 + tWTR
In DDR4, minimum time from write command to read command for same bank group. In others,
minimum time from write command to read command. Includes time for bus turnaround,
recovery times, and all per-bank, per-rank, and global constraints.
Unit: Clocks.
Where:
- CWL = CAS write latency
- WL = Write latency
- PL = Parity latency
- BL = burst length. This must match the value programmed in the BL bit of the mode register
to the SDRAM
- tWTR_L = internal write to read command delay for same bank group. This comes directly
from the SDRAM specification.
- tWTR = internal write to read command delay. This comes directly from the SDRAM
specification.
Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation.
When the controller is operating in 1:2 mode, divide the value calculated using the above
equation by 2, and round it up to next integer.
Programming mode: Quasi-dynamic Group 1 and Group 2 and Group 4
RM0442 Rev 7
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.26
RM0442
DDRCTRL SDRAM timing register 3 (DDRCTRL_DRAMTMG3)
Address offset: 0x10C
Reset value: 0x0050 400C
31
30
Res.
Res.
15
14
29
28
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26
25
24
23
22
21
20
T_MRW[9:0]
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rw
rw
rw
rw
rw
rw
rw
rw
rw
13
12
11
10
9
8
7
6
5
4
Res.
Res.
rw
rw
rw
rw
T_MRD[3:0]
rw
27
rw
rw
19
18
17
Res.
Res.
T_MRD[5:4]
16
rw
rw
3
2
1
0
rw
rw
rw
rw
T_MOD[9:0]
rw
rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:20 T_MRW[9:0]: Time to wait after a mode register write or read (MRW or MRR).
Present only in designs configured to support LPDDR2, LPDDR3 or LPDDR4.
LPDDR2 typically requires value of 5.
LPDDR3 typically requires value of 10.
LPDDR4: Set this to the larger of tMRW and tMRWCKEL.
For LPDDR2, this register is used for the time from a MRW/MRR to all other commands.
When the controller is operating in 1:2 frequency ratio mode, program this to the above values
divided by 2 and round it up to the next integer value.
For LDPDR3, this register is used for the time from a MRW/MRR to a MRW/MRR.
Programming mode: Quasi-dynamic Group 2 and Group 4
Bits 19:18 Reserved, must be kept at reset value.
Bits 17:12 T_MRD[5:0]: tMRD: Cycles to wait after a mode register write or read. Depending on the
connected SDRAM, tMRD represents:
DDR2/mDDR: Time from MRS to any command
DDR3/4: Time from MRS to MRS command
LPDDR2: not used
LPDDR3/4: Time from MRS to non-MRS command.
When the controller is operating in 1:2 frequency ratio mode, program this to (tMRD/2) and
round it up to the next integer value.
If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead.
Programming mode: Quasi-dynamic Group 2 and Group 4
Bits 11:10 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bits 9:0 T_MOD[9:0]: tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode
command and following non-load mode command.
If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead.
If MPR writes for DDR4 are used, set to tMOD + AL (or tMPD_PAR + AL if C/A parity is also
used).
Set to tMOD if controller is operating in 1:1 frequency ratio mode, or tMOD/2 (rounded up to
next integer) if controller is operating in 1:2 frequency ratio mode. Note that if using
RDIMM/LRDIMM, depending on the PHY, it may be necessary to adjust the value of this
parameter to compensate for the extra cycle of latency applied to mode register writes by the
RDIMM/LRDIMM chip.
Also note that if using LRDIMM, the minimum value of this register is tMRD_L2 if controller is
operating in 1:1 frequency ratio mode, or tMRD_L2/2 (rounded up to next integer) if controller is
operating in 1:2 frequency ratio mode.
Programming mode: Quasi-dynamic Group 2 and Group 4
5.7.27
DDRCTRL SDRAM timing register 4 (DDRCTRL_DRAMTMG4)
Address offset: 0x110
Reset value: 0x0504 0405
31
30
29
Res.
Res.
Res.
28
27
26
25
24
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
T_RCD[4:0]
T_RRD[3:0]
rw
rw
rw
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
Res.
Res.
Res.
rw
19
18
17
16
T_CCD[3:0]
rw
rw
rw
rw
3
2
1
0
rw
rw
T_RP[4:0]
rw
rw
rw
Bits 31:29 Reserved, must be kept at reset value.
Bits 28:24 T_RCD[4:0]: tRCD - tAL: Minimum time from activate to read or write command to same bank.
When the controller is operating in 1:2 frequency ratio mode, program this to ((tRCD - tAL)/2)
and round it up to the next integer value.
Minimum value allowed for this register is 1, which implies minimum (tRCD - tAL) value to be 2
when the controller is operating in 1:2 frequency ratio mode.
Unit: Clocks.
Programming mode: Quasi-dynamic Group 1 and Group 2 and Group 4
Bits 23:20 Reserved, must be kept at reset value.
Bits 19:16 T_CCD[3:0]: DDR4: tCCD_L: This is the minimum time between two reads or two writes for
same bank group.
Others: tCCD: This is the minimum time between two reads or two writes.
When the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_L/2 or
tCCD/2) and round it up to the next integer value.
Unit: clocks.
Programming mode: Quasi-dynamic Group 2 and Group 4.
Bits 15:12 Reserved, must be kept at reset value.
RM0442 Rev 7
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Bits 11:8 T_RRD[3:0]: DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for
same bank group.
Others: tRRD: Minimum time between activates from bank "a" to bank "b"
When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_L/2 or
tRRD/2) and round it up to the next integer value.
Unit: Clocks.
Programming mode: Quasi-dynamic Group 2 and Group 4.
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 T_RP[4:0]: tRP: Minimum time from precharge to activate of same bank.
When the controller is operating in 1:1 frequency ratio mode, t_rp should be set to
RoundUp(tRP/tCK).
When the controller is operating in 1:2 frequency ratio mode, t_rp should be set to
RoundDown(RoundUp(tRP/tCK)/2) + 1.
When the controller is operating in 1:2 frequency ratio mode in LPDDR4, t_rp should be set
to RoundUp(RoundUp(tRP/tCK)/2).
Unit: Clocks.
Programming mode: Quasi-dynamic Group 2 and Group 4.
5.7.28
DDRCTRL SDRAM timing register 5 (DDRCTRL_DRAMTMG5)
Address offset: 0x114
Reset value: 0x0505 0403
31
30
29
28
Res.
Res.
Res.
Res.
15
14
Res.
Res.
13
12
27
26
25
24
T_CKSRX[3:0]
rw
rw
rw
rw
11
10
9
8
T_CKESR[5:0]
rw
rw
rw
rw
rw
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
Res.
Res.
Res.
rw
4
19
18
17
16
T_CKSRE[3:0]
rw
rw
rw
rw
3
2
1
0
rw
rw
T_CKE[4:0]
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:24 T_CKSRX[3:0]: This is the time before Self Refresh Exit that CK is maintained as a valid clock
before issuing SRX. Specifies the clock stable time before SRX.
Recommended settings:
- mDDR: 1
- LPDDR2: 2
- LPDDR3: 2
- LPDDR4: tCKCKEH
- DDR2: 1
- DDR3: tCKSRX
- DDR4: tCKSRX
When the controller is operating in 1:2 frequency ratio mode, program this to recommended
value divided by two and round it up to next integer.
Programming mode: Quasi-dynamic Group 2 and Group 4
Bits 23:20 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bits 19:16 T_CKSRE[3:0]: This is the time after Self Refresh Down Entry that CK is maintained as a valid
clock. Specifies the clock disable delay after SRE.
Recommended settings:
- mDDR: 0
- LPDDR2: 2
- LPDDR3: 2
- LPDDR4: tCKELCK
- DDR2: 1
- DDR3: max (10 ns, 5 tCK)
- DDR4: max (10 ns, 5 tCK) (+ PL(parity latency)(*))
(*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased by
PL.
When the controller is operating in 1:2 frequency ratio mode, program this to recommended
value divided by two and round it up to next integer.
Programming mode: Quasi-dynamic Group 2 and Group 4
Bits 15:14 Reserved, must be kept at reset value.
Bits 13:8 T_CKESR[5:0]: Minimum CKE low width for Self refresh or Self refresh power down entry to
exit timing in memory clock cycles.
Recommended settings:
- mDDR: tRFC
- LPDDR2: tCKESR
- LPDDR3: tCKESR
- LPDDR4: max(tCKE, tSR)
- DDR2: tCKE
- DDR3: tCKE + 1
- DDR4: tCKE + 1 (+ PL(parity latency)(*))
(*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased by
PL.
When the controller is operating in 1:2 frequency ratio mode, program this to recommended
value divided by two and round it up to next integer.
Programming mode: Quasi-dynamic Group 2 and Group 4
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 T_CKE[4:0]: Minimum number of cycles of CKE HIGH/LOW during power-down and self
refresh.
- LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR
- LPDDR4 mode: Set this to the larger of tCKE or tSR.
- Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value.
When the controller is operating in 1:2 frequency ratio mode, program this to (value described
above)/2 and round it up to the next integer value.
Unit: Clocks.
Programming mode: Quasi-dynamic Group 2 and Group 4
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.29
RM0442
DDRCTRL SDRAM timing register 6 (DDRCTRL_DRAMTMG6)
Address offset: 0x118
Reset value: 0x0202 0005
31
30
29
28
Res.
Res.
Res.
Res.
27
26
25
24
23
22
21
20
Res.
Res.
Res.
Res.
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
T_CKDPDE[3:0]
19
18
17
16
T_CKDPDX[3:0]
rw
rw
rw
rw
3
2
1
0
T_CKCSX[3:0]
rw
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:24 T_CKDPDE[3:0]: This is the time after Deep Power Down Entry that CK is maintained as a
valid clock. Specifies the clock disable delay after DPDE.
Recommended settings:
- mDDR: 0
- LPDDR2: 2
- LPDDR3: 2
When the controller is operating in 1:2 frequency ratio mode, program this to recommended
value divided by two and round it up to next integer.
This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices.
Programming mode: Quasi-dynamic Group 2 and Group 4
Bits 23:20 Reserved, must be kept at reset value.
Bits 19:16 T_CKDPDX[3:0]: This is the time before Deep Power Down Exit that CK is maintained as a
valid clock before issuing DPDX. Specifies the clock stable time before DPDX.
Recommended settings:
- mDDR: 1
- LPDDR2: 2
- LPDDR3: 2
When the controller is operating in 1:2 frequency ratio mode, program this to recommended
value divided by two and round it up to next integer.
This is only present for designs supporting mDDR or LPDDR2 devices.
Programming mode: Quasi-dynamic Group 2 and Group 4
Bits 15:4 Reserved, must be kept at reset value.
Bits 3:0 T_CKCSX[3:0]: This is the time before Clock Stop Exit that CK is maintained as a valid clock
before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock
Stop Exit.
Recommended settings:
- mDDR: 1
- LPDDR2: tXP + 2
- LPDDR3: tXP + 2
- LPDDR4: tXP + 2
When the controller is operating in 1:2 frequency ratio mode, program this to recommended
value divided by two and round it up to next integer.
This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
Programming mode: Quasi-dynamic Group 2 and Group 4
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.30
DDRCTRL SDRAM timing register 7 (DDRCTRL_DRAMTMG7)
Address offset: 0x11C
Reset value: 0x0000 0202
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
T_CKPDE[3:0]
rw
rw
rw
rw
T_CKPDX[3:0]
rw
rw
rw
rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:8 T_CKPDE[3:0]: This is the time after Power Down Entry that CK is maintained as a valid clock.
Specifies the clock disable delay after PDE.
Recommended settings:
- mDDR: 0
- LPDDR2: 2
- LPDDR3: 2
- LPDDR4: tCKELCK
When using DDR2/3/4 SDRAM, this register should be set to the same value as
DRAMTMG5.t_cksre.
When the controller is operating in 1:2 frequency ratio mode, program this to recommended
value divided by two and round it up to next integer.
This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
Programming mode: Quasi-dynamic Group 2 and Group 4
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 T_CKPDX[3:0]: This is the time before Power Down Exit that CK is maintained as a valid clock
before issuing PDX. Specifies the clock stable time before PDX.
Recommended settings:
- mDDR: 0
- LPDDR2: 2
- LPDDR3: 2
- LPDDR4: 2
When using DDR2/3/4 SDRAM, this register should be set to the same value as
DRAMTMG5.t_cksrx.
When the controller is operating in 1:2 frequency ratio mode, program this to recommended
value divided by two and round it up to next integer.
This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
Programming mode: Quasi-dynamic Group 2 and Group 4
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.31
RM0442
DDRCTRL SDRAM timing register 8 (DDRCTRL_DRAMTMG8)
Address offset: 0x120
Reset value: 0x0000 4405
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Res.
T_XS_DLL_X32[6:0]
rw
rw
Res.
T_XS_X32[6:0]
rw
Bits 31:15 Reserved, must be kept at reset value.
Bits 14:8 T_XS_DLL_X32[6:0]: tXSDLL: Exit Self Refresh to the commands requiring a locked DLL.
When the controller is operating in 1:2 frequency ratio mode, program this to the above value
divided by 2 and round up to next integer value.
Unit: Multiples of 32 clocks.
Note: Used only for DDR2, DDR3 and DDR4 SDRAMs.
Programming mode: Quasi-dynamic Group 2 and Group 4
Bit 7 Reserved, must be kept at reset value.
Bits 6:0 T_XS_X32[6:0]: tXS: Exit Self Refresh to commands not requiring a locked DLL.
When the controller is operating in 1:2 frequency ratio mode, program this to the above value
divided by 2 and round up to next integer value.
Unit: Multiples of 32 clocks.
Note: Used only for DDR2, DDR3 and DDR4 SDRAMs.
Programming mode: Quasi-dynamic Group 2 and Group 4
5.7.32
DDRCTRL SDRAM timing register 14 (DDRCTRL_DRAMTMG14)
Address offset: 0x138
Reset value: 0x0000 00A0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
15
14
13
12
Res.
Res.
Res.
Res.
T_XSR[11:0]
rw
rw
rw
rw
rw
rw
rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 T_XSR[11:0]: tXSR: Exit Self Refresh to any command.
When the controller is operating in 1:2 frequency ratio mode, program this to the above value
divided by 2 and round up to next integer value.
Note: Used only for mDDR/LPDDR2/LPDDR3/LPDDR4 mode.
Programming mode: Quasi-dynamic Group 2 and Group 4
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.33
DDRCTRL SDRAM timing register 15 (DDRCTRL_DRAMTMG15)
Address offset: 0x13C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
EN_DFI_LP_T_STAB
Reset value: 0x0000 0000
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
rw
rw
rw
rw
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
T_STAB_X32[7:0]
rw
rw
rw
rw
rw
Bit 31 EN_DFI_LP_T_STAB:
- 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the
clock during DFI LP to save maximum power.
- 0 - Disable using tSTAB when exiting DFI LP
Programming mode: Quasi-dynamic Group 2 and Group 4.
Bits 30:8 Reserved, must be kept at reset value.
Bits 7:0 T_STAB_X32[7:0]: tSTAB: Stabilization time.
It is required in the following two cases for DDR3/DDR4 RDIMM:
- When exiting power saving mode, if the clock was stopped, after re-enabling it the clock
must be stable for a time specified by tSTAB
- In the case of input clock frequency change (DDR4)
- After issuing control words that refers to clock timing (Specification: 6us for DDR3, 5us for
DDR4).
When the controller is operating in 1:2 frequency ratio mode, program this to recommended
value divided by two and round it up to next integer.
Unit: Multiples of 32 clock cycles.
Programming mode: Quasi-dynamic Group 2 and Group 4.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.34
RM0442
DDRCTRL ZQ control register 0 (DDRCTRL_ZQCTL0)
Address offset: 0x180
31
30
29
28
27
DIS_AUTO_ZQ
DIS_SRX_ZQCL
ZQ_RESISTOR_SHARED
Reset value: 0x0200 0040
Res.
Res.
26
25
24
23
22
21
20
19
18
17
16
T_ZQ_LONG_NOP[10:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
T_ZQ_SHORT_NOP[9:0]
rw
rw
rw
rw
rw
rw
Bit 31 DIS_AUTO_ZQ:
- 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register
DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB
module.
- 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on
ZQCTL1.t_zq_short_interval_x1024.
This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4
devices.
Programming mode: Dynamic
Bit 30 DIS_SRX_ZQCL:
- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown
exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode.
- 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown
exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode.
This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4
devices.
Programming mode: Quasi-dynamic Group 2 and Group 4.
Bit 29 ZQ_RESISTOR_SHARED:
- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ
calibration) commands are sent to one rank at a time with
tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to
different ranks do not overlap.
- 0 - ZQ resistor is not shared.
This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4
devices.
Programming mode: Static.
Bits 28:27 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bits 26:16 T_ZQ_LONG_NOP[10:0]: tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for
LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration
long)/MPC(ZQ Start) command is issued to SDRAM.
When the controller is operating in 1:2 frequency ratio mode:
DDR3/DDR4: program this to tZQoper/2 and round it up to the next integer value.
LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer value.
LPDDR4: program this to tZQCAL/2 and round it up to the next integer value.
This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4
devices.
Programming mode: Static.
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:0 T_ZQ_SHORT_NOP[9:0]: tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4:
Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ
Latch) command is issued to SDRAM.
When the controller is operating in 1:2 frequency ratio mode, program this to tZQCS/2 and
round it up to the next integer value.
This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4
devices.
Programming mode: Static.
5.7.35
DDRCTRL ZQ control register 1 (DDRCTRL_ZQCTL1)
Address offset: 0x184
Reset value: 0x0200 0100
31
Res.
15
30
29
28
27
26
Res.
14
25
24
23
22
21
20
T_ZQ_RESET_NOP[9:0]
rw
rw
rw
rw
13
12
11
10
19
18
17
16
T_ZQ_SHORT_INTERVAL_X1024[
19:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
T_ZQ_SHORT_INTERVAL_X1024[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:20 T_ZQ_RESET_NOP[9:0]: tZQReset: Number of DFI clock cycles of NOP required after a
ZQReset (ZQ calibration Reset) command is issued to SDRAM.
When the controller is operating in 1:2 frequency ratio mode, program this to tZQReset/2 and
round it up to the next integer value.
This is only present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.
Programming mode: Static.
Bits 19:0 T_ZQ_SHORT_INTERVAL_X1024[19:0]: Average interval to wait between automatically
issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to
DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices.
Meaningless, if ZQCTL0.dis_auto_zq=1.
Unit: 1024 DFI clock cycles.
This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4
devices.
Programming mode: Static.
RM0442 Rev 7
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.36
RM0442
DDRCTRL ZQ control register 2 (DDRCTRL_ZQCTL2)
Address offset: 0x188
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ZQ_RESET
Reset value: 0x0000 0000
rs
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 ZQ_RESET:
Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is
complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this
register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep
power-down operating modes.
For Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) it is scheduled after SR(except
LPDDR4) or SPRD(LPDDR4) has been exited.
For Deep power down, it is not scheduled, although ZQSTAT.zq_reset_busy is de-asserted.
This is only present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.
Programming mode: Dynamic
5.7.37
DDRCTRL ZQ status register (DDRCTRL_ZQSTAT)
Address offset: 0x18C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ZQ_RESET_BUSY
Reset value: 0x0000 0000
r
Bits 31:1 Reserved, must be kept at reset value.
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RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bit 0 ZQ_RESET_BUSY: SoC core may initiate a ZQ Reset operation only if this signal is low. This
signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low
when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over.
It is recommended not to perform ZQ Reset commands when this signal is high.
- 0 - Indicates that the SoC core can initiate a ZQ Reset operation
- 1 - Indicates that ZQ Reset operation is in progress
Programming mode: Dynamic
5.7.38
DDRCTRL DFI timing register 0 (DDRCTRL_DFITMG0)
Address offset: 0x190
Reset value: 0x0702 0002
31
30
29
Res.
Res.
Res.
15
14
Res.
Res.
13
28
27
26
25
24
DFI_T_CTRL_DELAY[4:0]
rw
rw
rw
rw
rw
12
11
10
9
8
DFI_TPHY_WRDATA[5:0]
rw
rw
rw
rw
rw
23
22
21
Res.
20
rw
rw
rw
7
6
5
4
Res.
Res.
rw
19
18
17
16
DFI_T_RDDATA_EN[6:0]
rw
rw
rw
rw
3
2
1
0
rw
rw
DFI_TPHY_WRLAT[5:0]
rw
rw
rw
rw
Bits 31:29 Reserved, must be kept at reset value.
Bits 28:24 DFI_T_CTRL_DELAY[4:0]: Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect
the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this
timing parameter should be rounded up to the next integer value. Note that if using
RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM's/LRDIMM's extra
cycle of latency in terms of DFI clock.
Programming mode: Quasi-dynamic Group 4
Bit 23 Reserved, must be kept at reset value.
Bits 22:16 DFI_T_RDDATA_EN[6:0]: Time from the assertion of a read command on the DFI interface to
the assertion of the dfi_rddata_en signal.
Refer to PHY specification for correct value.
This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using
RDIMM/LRDIMM, it may be necessary to use the adjusted value of CL in the calculation of
trddata_en. This is to compensate for the extra cycle(s) of latency through the
RDIMM/LRDIMM.
Unit: DFI clock cycles or DFI PHY clock cycles, depending on
DFITMG0.dfi_rddata_use_dfi_phy_clk.
Programming mode: Quasi-dynamic Group 1 and Group 4
Bits 15:14 Reserved, must be kept at reset value.
Bits 13:8 DFI_TPHY_WRDATA[5:0]: Specifies the number of clock cycles between when dfi_wrdata_en
is asserted to when the associated write data is driven on the dfi_wrdata signal. This
corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct
value. Note, max supported value is 8.
Unit: DFI clock cycles or DFI PHY clock cycles, depending on
DFITMG0.dfi_wrdata_use_dfi_phy_clk.
Programming mode: Quasi-dynamic Group 4
Bits 7:6 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Bits 5:0 DFI_TPHY_WRLAT[5:0]: Write latency
Number of clocks from the write command to write data enable (dfi_wrdata_en). This
corresponds to the DFI timing parameter tphy_wrlat.
Refer to PHY specification for correct value.Note that, depending on the PHY, if using
RDIMM/LRDIMM, it may be necessary to use the adjusted value of CL in the calculation of
tphy_wrlat. This is to compensate for the extra cycle(s) of latency through the
RDIMM/LRDIMM.
For LPDDR4, dfi_tphy_wrlat>60 is not supported.
Unit: DFI clock cycles or DFI PHY clock cycles, depending on
DFITMG0.dfi_wrdata_use_dfi_phy_clk.
Programming mode: Quasi-dynamic Group 1 and Group 4
5.7.39
DDRCTRL DFI timing register 1 (DDRCTRL_DFITMG1)
Address offset: 0x194
Reset value: 0x0000 0404
30
29
28
27
26
25
24
23
22
21
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
14
13
Res.
Res.
Res.
12
11
10
9
8
DFI_T_DRAM_CLK_DISABLE[4:0]
15
rw
rw
rw
rw
7
6
5
Res.
Res.
Res.
rw
20
19
18
17
16
DFI_T_WRDATA_DELAY[4:0]
rw
rw
rw
rw
rw
4
3
2
1
0
rw
rw
rw
rw
DFI_T_DRAM_CLK_ENABLE[4:0]
31
Res.
rw
Bits 31:21 Reserved, must be kept at reset value.
Bits 20:16 DFI_T_WRDATA_DELAY[4:0]: Specifies the number of DFI clock cycles between when the
dfi_wrdata_en
signal is asserted and when the corresponding write data transfer is completed on the DRAM
bus.
This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for
correct value.
For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0.
For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM).
Value to be programmed is in terms of DFI clocks, not PHY clocks.
In FREQ_RATIO=2, divide PHY's value by 2 and round up to next integer.
If using DFITMG0.dfi_wrdata_use_dfi_phy_clk=1, add 1 to the value.
Unit: Clocks
Programming mode: Quasi-dynamic Group 4
Bits 15:13 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bits 12:8 DFI_T_DRAM_CLK_DISABLE[4:0]: Specifies the number of DFI clock cycles from the
assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory
devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory
clock are not phase aligned, this timing parameter should be rounded up to the next integer
value.
Programming mode: Quasi-dynamic Group 4
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 DFI_T_DRAM_CLK_ENABLE[4:0]: Specifies the number of DFI clock cycles from the deassertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the
clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the
memory clock are not phase aligned, this timing parameter should be rounded up to the next
integer value.
Programming mode: Quasi-dynamic Group 4
5.7.40
DDRCTRL low power configuration register 0
(DDRCTRL_DFILPCFG0)
Address offset: 0x198
Res.
Res.
Res.
15
14
13
28
27
26
25
24
23
22
21
20
DFI_TLP_RESP[4:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
12
11
10
9
8
7
6
5
4
DFI_LP_WAKEUP_SR[3:0]
Res.
Res.
Res.
DFI_LP_WAKEUP_PD[3:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
19
18
17
16
Res.
Res.
Res.
DFI_LP_EN_DPD
29
DFI_LP_WAKEUP_DPD[3:0]
30
DFI_LP_EN_SR
31
3
2
1
0
Res.
Res.
Res.
DFI_LP_EN_PD
Reset value: 0x0700 0000
rw
rw
Bits 31:29 Reserved, must be kept at reset value.
Bits 28:24 DFI_TLP_RESP[4:0]: Setting in DFI clock cycles for DFI's tlp_resp time.
Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum
Power Saving modes.
DFI 2.1 specification onwards, recommends using a fixed value of 7 always.
Programming mode: Static
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Bits 23:20 DFI_LP_WAKEUP_DPD[3:0]: Value in DFI clock cycles to drive on dfi_lp_wakeup signal when
Deep Power Down mode is entered.
Determines the DFI's tlp_wakeup time:
- 0x0 - 16 cycles
- 0x1 - 32 cycles
- 0x2 - 64 cycles
- 0x3 - 128 cycles
- 0x4 - 256 cycles
- 0x5 - 512 cycles
- 0x6 - 1024 cycles
- 0x7 - 2048 cycles
- 0x8 - 4096 cycles
- 0x9 - 8192 cycles
- 0xA - 16384 cycles
- 0xB - 32768 cycles
- 0xC - 65536 cycles
- 0xD - 131072 cycles
- 0xE - 262144 cycles
- 0xF - Unlimited
This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices.
Programming mode: Static.
Bits 19:17 Reserved, must be kept at reset value.
Bit 16 DFI_LP_EN_DPD: Enables DFI Low-power interface handshaking during Deep Power Down
Entry/Exit.
- 0 - Disabled
- 1 - Enabled
This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices.
Programming mode: Static.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bits 15:12 DFI_LP_WAKEUP_SR[3:0]: Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when
Self Refresh mode is entered.
Determines the DFI's tlp_wakeup time:
- 0x0 - 16 cycles
- 0x1 - 32 cycles
- 0x2 - 64 cycles
- 0x3 - 128 cycles
- 0x4 - 256 cycles
- 0x5 - 512 cycles
- 0x6 - 1024 cycles
- 0x7 - 2048 cycles
- 0x8 - 4096 cycles
- 0x9 - 8192 cycles
- 0xA - 16384 cycles
- 0xB - 32768 cycles
- 0xC - 65536 cycles
- 0xD - 131072 cycles
- 0xE - 262144 cycles
- 0xF - Unlimited
Programming mode: Static
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 DFI_LP_EN_SR: Enables DFI Low Power interface handshaking during Self Refresh
Entry/Exit.
- 0 - Disabled
- 1 - Enabled
Programming mode: Static
Bits 7:4 DFI_LP_WAKEUP_PD[3:0]: Value in DFI clock cycles to drive on dfi_lp_wakeup signal when
Power Down mode is entered.
Determines the DFI's tlp_wakeup time:
- 0x0 - 16 cycles
- 0x1 - 32 cycles
- 0x2 - 64 cycles
- 0x3 - 128 cycles
- 0x4 - 256 cycles
- 0x5 - 512 cycles
- 0x6 - 1024 cycles
- 0x7 - 2048 cycles
- 0x8 - 4096 cycles
- 0x9 - 8192 cycles
- 0xA - 16384 cycles
- 0xB - 32768 cycles
- 0xC - 65536 cycles
- 0xD - 131072 cycles
- 0xE - 262144 cycles
- 0xF - Unlimited
Programming mode: Static
Bits 3:1 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Bit 0 DFI_LP_EN_PD: Enables DFI Low Power interface handshaking during Power Down
Entry/Exit.
- 0 - Disabled
- 1 - Enabled
Programming mode: Static
5.7.41
DDRCTRL DFI update register 0 (DDRCTRL_DFIUPD0)
Address offset: 0x1A0
31
30
29
28
27
26
DIS_AUTO_CTRLUPD
DIS_AUTO_CTRLUPD_SRX
CTRLUPD_PRE_SRX
Reset value: 0x0040 0003
Res.
Res.
Res.
rw
rw
rw
15
14
13
12
11
10
Res.
Res.
Res.
Res.
Res.
Res.
25
24
23
22
21
20
19
18
17
16
DFI_T_CTRLUP_MAX[9:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
DFI_T_CTRLUP_MIN[9:0]
rw
rw
Bit 31 DIS_AUTO_CTRLUPD: When '1', disable the automatic dfi_ctrlupd_req generation by the
DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd.
When '0', DDRCTRL issues dfi_ctrlupd_req periodically.
Programming mode: Quasi-dynamic Group 3
Bit 30 DIS_AUTO_CTRLUPD_SRX: When '1', disable the automatic dfi_ctrlupd_req generation by
the DDRCTRL at self-refresh exit.
When '0', DDRCTRL issues a dfi_ctrlupd_req before or after exiting self-refresh, depending on
DFIUPD0.ctrlupd_pre_srx.
Programming mode: Static
Bit 29 CTRLUPD_PRE_SRX: Selects dfi_ctrlupd_req requirements at SRX:
- 0 : send ctrlupd after SRX
- 1 : send ctrlupd before SRX
If DFIUPD0.dis_auto_ctrlupd_srx=1, this register has no impact, because no dfi_ctrlupd_req is
issued when SRX.
Programming mode: Static
Bits 28:26 Reserved, must be kept at reset value.
Bits 25:16 DFI_T_CTRLUP_MAX[9:0]: Specifies the maximum number of DFI clock cycles that the
dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40.
Programming mode: Static
Bits 15:10 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bits 9:0 DFI_T_CTRLUP_MIN[9:0]: Specifies the minimum number of DFI clock cycles that the
dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this
time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after
dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3.
Programming mode: Static
5.7.42
DDRCTRL DFI update register 1 (DDRCTRL_DFIUPD1)
Address offset: 0x1A4
Reset value: 0x0001 0001
31
30
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
23
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
DFI_T_CTRLUPD_INTERVAL_MIN_X1024[7:0]
DFI_T_CTRLUPD_INTERVAL_MAX_X1024[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:16 DFI_T_CTRLUPD_INTERVAL_MIN_X1024[7:0]: This is the minimum amount of time between
DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle).
Set this number higher to reduce the frequency of update requests, which can have a small
impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed
value for this field is 1.
Unit: 1024 DFI clock cycles.
Programming mode: Static.
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 DFI_T_CTRLUPD_INTERVAL_MAX_X1024[7:0]: This is the maximum amount of time
between DDRCTRL initiated DFI update requests. This timer resets with each update request;
when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is
received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI
controller update is also used to reset PHY FIFO pointers in case of data capture errors.
Updates are required to maintain calibration over PVT, but frequent updates may impact
performance. Minimum allowed value for this field is 1.
Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than
DFIUPD1.dfi_t_ctrlupd_interval_min_x1024.
Unit: 1024 DFI clock cycles.
Programming mode: Static.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.43
RM0442
DDRCTRL DFI update register 2 (DDRCTRL_DFIUPD2)
Address offset: 0x1A8
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DFI_PHYUPD_EN
Reset value: 0x8000 0000
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Bit 31 DFI_PHYUPD_EN: Enables the support for acknowledging PHY-initiated updates:
- 0 - Disabled
- 1 - Enabled
Programming mode: Static
Bits 30:0 Reserved, must be kept at reset value.
5.7.44
DDRCTRL DFI miscellaneous control register (DDRCTRL_DFIMISC)
Address offset: 0x1B0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
DFI_INIT_START
CTL_IDLE_EN
Res.
Res.
Res.
DFI_INIT_COMPLETE_EN
Reset value: 0x0000 0001
rw
rw
DFI_FREQUENCY[4:0]
rw
rw
rw
rw
rw
rw
Bits 31:13 Reserved, must be kept at reset value.
Bits 12:8 DFI_FREQUENCY[4:0]: Indicates the operating frequency of the system. The number of
supported frequencies and the mapping of signal values to clock frequencies are defined by the
PHY.
Programming mode: Quasi-dynamic Group 1
Bits 7:6 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bit 5 DFI_INIT_START: PHY init start request signal.When asserted it triggers the PHY init start
request
Programming mode: Quasi-dynamic Group 3
Bit 4 CTL_IDLE_EN: Enables support of ctl_idle signal
Programming mode: Static
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 DFI_INIT_COMPLETE_EN: PHY initialization complete enable signal.
When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisation
Programming mode: Quasi-dynamic Group 3
5.7.45
DDRCTRL DFI status register (DDRCTRL_DFISTAT)
Address offset: 0x1BC
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DFI_LP_ACK
DFI_INIT_COMPLETE
Reset value: 0x0000 0000
r
r
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 DFI_LP_ACK: Stores the value of the dfi_lp_ack input to the controller.
Programming mode: Dynamic
Bit 0 DFI_INIT_COMPLETE: The status flag register which announces when the DFI initialization
has been completed. The DFI INIT triggered by dfi_init_start signal and then the
dfi_init_complete flag is polled to know when the initialization is done.
Programming mode: Dynamic
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.46
RM0442
DDRCTRL DFI PHY master register (DDRCTRL_DFIPHYMSTR)
Address offset: 0x1C4
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DFI_PHYMSTR_EN
Reset value: 0x0000 0001
rw
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 DFI_PHYMSTR_EN: Enables the PHY Master Interface:
- 0 - Disabled
- 1 - Enabled
Programming mode: Dynamic
5.7.47
DDRCTRL address map register 1 (DDRCTRL_ADDRMAP1)
Address offset: 0x204
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
Res.
Res.
Res.
Res.
rw
rw
ADDRMAP_BANK_B1[5:0]
rw
rw
rw
rw
21
20
19
18
17
16
ADDRMAP_BANK_B2[5:0]
rw
rw
rw
rw
rw
rw
5
4
3
2
1
0
rw
rw
ADDRMAP_BANK_B0[5:0]
rw
rw
rw
rw
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:16 ADDRMAP_BANK_B2[5:0]: Selects the HIF address bit used as bank address bit 2.
Valid Range: 0 to 31, and 63
Internal Base: 4
The selected HIF address bit is determined by adding the internal base to the value of this field.
If unused, set to 63 and then bank address bit 2 is set to 0.
Programming mode: Static.
Bits 15:14 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bits 13:8 ADDRMAP_BANK_B1[5:0]: Selects the HIF address bits used as bank address bit 1.
Valid Range: 0 to 32, and 63
Internal Base: 3
The selected HIF address bit for each of the bank address bits is determined by adding the
internal base to the value of this field.
If unused, set to 63 and then bank address bit 1 is set to 0.
Programming mode: Static.
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:0 ADDRMAP_BANK_B0[5:0]: Selects the HIF address bits used as bank address bit 0.
Valid Range: 0 to 32, and 63
Internal Base: 2
The selected HIF address bit for each of the bank address bits is determined by adding the
internal base to the value of this field.
If unused, set to 63 and then bank address bit 0 is set to 0.
Programming mode: Static.
5.7.48
DDRCTRL address map register 2 (DDRCTRL_ADDRMAP2)
Address offset: 0x208
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
27
26
25
24
ADDRMAP_COL_B5[3:0]
rw
rw
rw
rw
11
10
9
8
ADDRMAP_COL_B3[3:0]
rw
rw
rw
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
Res.
Res.
Res.
Res.
rw
19
18
17
16
ADDRMAP_COL_B4[3:0]
rw
rw
rw
rw
3
2
1
0
ADDRMAP_COL_B2[3:0]
rw
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:24 ADDRMAP_COL_B5[3:0]:
- Full bus width mode: Selects the HIF address bit used as column address bit 5.
- Half bus width mode: Selects the HIF address bit used as column address bit 6.
- Quarter bus width mode: Selects the HIF address bit used as column address bit 7 .
Valid Range: 0 to 7, and 15
Internal Base: 5
The selected HIF address bit is determined by adding the internal base to the value of this field.
If unused, set to 15 and then this column address bit is set to 0.
Programming mode: Static
Bits 23:20 Reserved, must be kept at reset value.
RM0442 Rev 7
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Bits 19:16 ADDRMAP_COL_B4[3:0]:
- Full bus width mode: Selects the HIF address bit used as column address bit 4.
- Half bus width mode: Selects the HIF address bit used as column address bit 5.
- Quarter bus width mode: Selects the HIF address bit used as column address bit 6.
Valid Range: 0 to 7, and 15
Internal Base: 4
The selected HIF address bit is determined by adding the internal base to the value of this field.
If unused, set to 15 and then this column address bit is set to 0.
Programming mode: Static
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:8 ADDRMAP_COL_B3[3:0]:
- Full bus width mode: Selects the HIF address bit used as column address bit 3.
- Half bus width mode: Selects the HIF address bit used as column address bit 4.
- Quarter bus width mode: Selects the HIF address bit used as column address bit 5.
Valid Range: 0 to 7
Internal Base: 3
The selected HIF address bit is determined by adding the internal base to the value of this field.
Note, if UMCTL2_INCL_ARB=1, MEMC_BURST_LENGTH=16, Full bus width
(MSTR.data_bus_width=00) and BL16 (MSTR.burst_rdwr=1000), it is recommended to
program this to 0.
Programming mode: Static
Bits 7:4 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bits 3:0 ADDRMAP_COL_B2[3:0]:
- Full bus width mode: Selects the HIF address bit used as column address bit 2.
- Half bus width mode: Selects the HIF address bit used as column address bit 3.
- Quarter bus width mode: Selects the HIF address bit used as column address bit 4.
Valid Range: 0 to 7
Internal Base: 2
The selected HIF address bit is determined by adding the internal base to the value of this field.
Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8, it is required to program this
to 0 unless:
- in Half or Quarter bus width (MSTR.data_bus_width!=00) and
- PCCFG.bl_exp_mode==1 and either
- In DDR4 and ADDRMAP8.addrmap_bg_b0==0 or
- In LPDDR4 and ADDRMAP1.addrmap_bank_b0==0
If UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0
unless:
- in Half or Quarter bus width (MSTR.data_bus_width!=00) and
- PCCFG.bl_exp_mode==1 and
- In DDR4 and ADDRMAP8.addrmap_bg_b0==0
Otherwise, if MEMC_BURST_LENGTH=8 and Full Bus Width (MSTR.data_bus_width==00), it
is recommended to program this to 0 so that HIF[2] maps to column address bit 2.
If MEMC_BURST_LENGTH=16 and Full Bus Width (MSTR.data_bus_width==00), it is
recommended to program this to 0 so that HIF[2] maps to column address bit 2.
If MEMC_BURST_LENGTH=16 and Half Bus Width (MSTR.data_bus_width==01), it is
recommended to program this to 0 so that HIF[2] maps to column address bit 3.
Programming mode: Static
5.7.49
DDRCTRL address map register 3 (DDRCTRL_ADDRMAP3)
Address offset: 0x20C
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
28
rw
15
14
13
Res.
Res.
Res.
27
26
25
24
ADDRMAP_COL_B9[4:0]
12
rw
rw
rw
rw
11
10
9
8
ADDRMAP_COL_B7[4:0]
rw
rw
rw
rw
23
22
21
Res.
Res.
Res.
20
18
17
16
rw
rw
rw
rw
rw
3
2
1
0
7
6
5
4
Res.
Res.
Res.
Res.
rw
19
ADDRMAP_COL_B8[4:0]
ADDRMAP_COL_B6[3:0]
rw
rw
rw
rw
Bits 31:29 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Bits 28:24 ADDRMAP_COL_B9[4:0]:
- Full bus width mode: Selects the HIF address bit used as column address bit 9.
- Half bus width mode: Selects the HIF address bit used as column address bit 11 (10 in
LPDDR2/LPDDR3 mode).
- Quarter bus width mode: Selects the HIF address bit used as column address bit 13 (11 in
LPDDR2/LPDDR3 mode).
Valid Range: 0 to 7, x, and 31. x indicate a valid value in inline ECC configuration.
Internal Base: 9
The selected HIF address bit is determined by adding the internal base to the value of this field.
Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating
auto-precharge, and hence no source address bit can be mapped to column address bit 10.
In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence
column bit 10 is used.
In Inline ECC configuration (MEMC_INLINE_ECC=1) and ECC is enabled
(ECCCFG0.ecc_mode>0), the highest 3 column address bits must map to the highest 3 valid
HIF address bits.
If column bit 9 is the highest column address bit, it must map to the highest valid HIF address
bit. (x = the highest valid HIF address bit - internal base)
If column bit 9 is the second highest column address bit, it must map to the second highest
valid HIF address bit. (x = the highest valid HIF address bit - 1 - internal base)
If column bit 9 is the third highest column address bit, it must map to the third highest valid HIF
address bit. (x = the highest valid HIF address bit - 2 - internal base)
If unused, set to 31 and then this column address bit is set to 0.
Programming mode: Static.
Bits 23:21 Reserved, must be kept at reset value.
Bits 20:16 ADDRMAP_COL_B8[4:0]:
- Full bus width mode: Selects the HIF address bit used as column address bit 8.
- Half bus width mode: Selects the HIF address bit used as column address bit 9.
- Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 in
LPDDR2/LPDDR3 mode).
Valid Range: 0 to 7, x, and 31. x indicate a valid value in inline ECC configuration.
Internal Base: 8
The selected HIF address bit is determined by adding the internal base to the value of this field.
Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating
auto-precharge, and hence no source address bit can be mapped to column address bit 10.
In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence
column bit 10 is used.
In Inline ECC configuration (MEMC_INLINE_ECC=1) and ECC is enabled
(ECCCFG0.ecc_mode>0), the highest 3 column address bits must map to the highest 3 valid
HIF address bits.
If column bit 8 is the second highest column address bit, it must map to the second highest
valid HIF address bit. (x = the highest valid HIF address bit - 1 - internal base).
If column bit 8 is the third highest column address bit, it must map to the third highest valid HIF
address bit. (x = the highest valid HIF address bit - 2 - internal base).
If unused, set to 31 and then this column address bit is set to 0.
Programming mode: Static.
Bits 15:13 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bits 12:8 ADDRMAP_COL_B7[4:0]:
- Full bus width mode: Selects the HIF address bit used as column address bit 7.
- Half bus width mode: Selects the HIF address bit used as column address bit 8.
- Quarter bus width mode: Selects the HIF address bit used as column address bit 9.
Valid Range: 0 to 7, x, and 31. x indicate a valid value in inline ECC configuration.
Internal Base: 7
The selected HIF address bit is determined by adding the internal base to the value of this field.
In Inline ECC configuration (MEMC_INLINE_ECC=1) and ECC is enabled
(ECCCFG0.ecc_mode>0), the highest 3 column address bits must map to the highest 3 valid
HIF address bits.
If column bit 7 is the third highest column address bit, it must map to the third highest valid HIF
address bit. (x = the highest valid HIF address bit - 2 - internal base).
If unused, set to 31 and then this column address bit is set to 0.
Programming mode: Static.
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 ADDRMAP_COL_B6[3:0]:
- Full bus width mode: Selects the HIF address bit used as column address bit 6.
- Half bus width mode: Selects the HIF address bit used as column address bit 7.
- Quarter bus width mode: Selects the HIF address bit used as column address bit 8.
Valid Range: 0 to 7, and 15
Internal Base: 6
The selected HIF address bit is determined by adding the internal base to the value of this field.
If unused, set to 15 and then this column address bit is set to 0.
Programming mode: Static
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.50
RM0442
DDRCTRL address map register 4 (DDRCTRL_ADDRMAP4)
Address offset: 0x210
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
ADDRMAP_COL_B11[4:0]
rw
rw
rw
rw
rw
ADDRMAP_COL_B10[4:0]
rw
rw
rw
rw
rw
Bits 31:13 Reserved, must be kept at reset value.
Bits 12:8 ADDRMAP_COL_B11[4:0]:
- Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in
LPDDR2/LPDDR3 mode).
- Half bus width mode: UNUSED. See later in this description for value you need to set to
make it unused.
- Quarter bus width mode: UNUSED. See later in this description for value you need to set to
make it unused.
Valid Range: 0 to 7, x, and 31. x indicate a valid value in inline ECC configuration.
Internal Base: 11
The selected HIF address bit is determined by adding the internal base to the value of this field.
Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating
auto-precharge, and hence no source address bit can be mapped to column address bit 10.
In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence
column bit 10 is used.
In Inline ECC configuration (MEMC_INLINE_ECC=1) and ECC is enabled
(ECCCFG0.ecc_mode>0), the highest 3 column address bits must map to the highest 3 valid
HIF address bits.
If column bit 11 is the highest column address bit, it must map to the highest valid HIF address
bit. (x = the highest valid HIF address bit - internal base)
If column bit 11 is the second highest column address bit, it must map to the second highest
valid HIF address bit. (x = the highest valid HIF address bit - 1 - internal base)
If column bit 11 is the third highest column address bit, it must map to the third highest valid
HIF address bit. (x = the highest valid HIF address bit - 2 - internal base)
If unused, set to 31 and then this column address bit is set to 0.
Programming mode: Static
Bits 7:5 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bits 4:0 ADDRMAP_COL_B10[4:0]:
- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in
LPDDR2/LPDDR3 mode).
- Half bus width mode: Selects the HIF address bit used as column address bit 13 (11 in
LPDDR2/LPDDR3 mode).
- Quarter bus width mode: UNUSED. See later in this description for value you need to set to
make it unused.
Valid Range: 0 to 7, x, and 31. x indicate a valid value in inline ECC configuration.
Internal Base: 10
The selected HIF address bit is determined by adding the internal base to the value of this field.
Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating
auto-precharge, and hence no source address bit can be mapped to column address bit 10.
In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence
column bit 10 is used.
In Inline ECC configuration (MEMC_INLINE_ECC=1) and ECC is enabled
(ECCCFG0.ecc_mode>0), the highest 3 column address bits must map to the highest 3 valid
HIF address bits.
If column bit 10 is the highest column address bit, it must map to the highest valid HIF address
bit. (x = the highest valid HIF address bit - internal base)
If column bit 10 is the second highest column address bit, it must map to the second highest
valid HIF address bit. (x = the highest valid HIF address bit - 1 - internal base)
If column bit 10 is the third highest column address bit, it must map to the third highest valid
HIF address bit. (x = the highest valid HIF address bit - 2 - internal base)
If unused, set to 31 and then this column address bit is set to 0.
Programming mode: Static
5.7.51
DDRCTRL address map register 5 (DDRCTRL_ADDRMAP5)
Address offset: 0x214
Reset value: 0x0000 0000
30
29
28
27
26
25
24
23
22
21
20
Res.
Res.
Res.
Res.
ADDRMAP_ROW_B11[3:0]
Res.
Res.
Res.
Res.
15
14
13
12
7
6
5
4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
11
10
9
8
ADDRMAP_ROW_B1[3:0]
rw
rw
rw
rw
19
18
17
16
rw
3
rw
rw
rw
2
1
0
ADDRMAP_ROW_B2_10[3:0]
31
ADDRMAP_ROW_B0[3:0]
rw
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Bits 27:24 ADDRMAP_ROW_B11[3:0]: Selects the HIF address bit used as row address bit 11.
Valid Range: 0 to 11, and 15
Internal Base: 17
The selected HIF address bit is determined by adding the internal base to the value of this field.
If unused, set to 15 and then row address bit 11 is set to 0.
Programming mode: Static
Bits 23:20 Reserved, must be kept at reset value.
Bits 19:16 ADDRMAP_ROW_B2_10[3:0]: Selects the HIF address bits used as row address bits 2 to 10.
Valid Range: 0 to 11, and 15
Internal Base: 8 (for row address bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc
increasing to 16 (for row address bit 10)
The selected HIF address bit for each of the row address bits is determined by adding the
internal base to the value of this field.
When set to 15, the values of row address bits 2 to 10 are defined by registers ADDRMAP9,
ADDRMAP10, ADDRMAP11.
Programming mode: Static
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:8 ADDRMAP_ROW_B1[3:0]: Selects the HIF address bits used as row address bit 1.
Valid Range: 0 to 11
Internal Base: 7
The selected HIF address bit for each of the row address bits is determined by adding the
internal base to the value of this field.
Programming mode: Static
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 ADDRMAP_ROW_B0[3:0]: Selects the HIF address bits used as row address bit 0.
Valid Range: 0 to 11
Internal Base: 6
The selected HIF address bit for each of the row address bits is determined by adding the
internal base to the value of this field.
Programming mode: Static
5.7.52
DDRCTRL address register 6 (DDRCTRL_ADDRMAP6)
Address offset: 0x218
31
30
29
28
27
24
23
22
21
20
19
LPDDR3_6GB_12GB
Reset value: 0x0000 0000
Res.
Res.
Res.
ADDRMAP_ROW_B15[3:0]
Res.
Res.
Res.
Res.
ADDRMAP_ROW_B14[3:0]
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
Res.
Res.
Res.
Res.
ADDRMAP_ROW_B13[3:0]
Res.
Res.
Res.
Res.
rw
rw
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26
rw
25
rw
rw
RM0442 Rev 7
18
17
16
rw
rw
rw
rw
3
2
1
0
ADDRMAP_ROW_B12[3:0]
rw
rw
rw
rw
RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bit 31 LPDDR3_6GB_12GB:
Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use.
- 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]==2'b11 is
considered as invalid
- 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid
Present only in designs configured to support LPDDR3.
Programming mode: Static
Bits 30:28 Reserved, must be kept at reset value.
Bits 27:24 ADDRMAP_ROW_B15[3:0]: Selects the HIF address bit used as row address bit 15.
Valid Range: 0 to 11, and 15
Internal Base: 21
The selected HIF address bit is determined by adding the internal base to the value of this field.
If unused, set to 15 and then row address bit 15 is set to 0.
Programming mode: Static
Bits 23:20 Reserved, must be kept at reset value.
Bits 19:16 ADDRMAP_ROW_B14[3:0]: Selects the HIF address bit used as row address bit 14.
Valid Range: 0 to 11, and 15
Internal Base: 20
The selected HIF address bit is determined by adding the internal base to the value of this field.
If unused, set to 15 and then row address bit 14 is set to 0.
Programming mode: Static
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:8 ADDRMAP_ROW_B13[3:0]: Selects the HIF address bit used as row address bit 13.
Valid Range: 0 to 11, and 15
Internal Base: 19
The selected HIF address bit is determined by adding the internal base to the value of this field.
If unused, set to 15 and then row address bit 13 is set to 0.
Programming mode: Static
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 ADDRMAP_ROW_B12[3:0]: Selects the HIF address bit used as row address bit 12.
Valid Range: 0 to 11, and 15
Internal Base: 18
The selected HIF address bit is determined by adding the internal base to the value of this field.
If unused, set to 15 and then row address bit 12 is set to 0.
Programming mode: Static
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.53
RM0442
DDRCTRL address map register 9 (DDRCTRL_ADDRMAP9)
Address offset: 0x224
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
27
26
25
24
ADDRMAP_ROW_B5[3:0]
rw
rw
rw
rw
11
10
9
8
ADDRMAP_ROW_B3[3:0]
rw
rw
rw
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
Res.
Res.
Res.
Res.
rw
19
18
17
rw
rw
rw
rw
3
2
1
0
ADDRMAP_ROW_B2[3:0]
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:24 ADDRMAP_ROW_B5[3:0]: Selects the HIF address bits used as row address bit 5.
Valid Range: 0 to 11
Internal Base: 11
The selected HIF address bit for each of the row address bits is determined by adding the
internal base to the value of this field. This register field is used only when
ADDRMAP5.addrmap_row_b2_10 is set to value 15.
Programming mode: Static
Bits 23:20 Reserved, must be kept at reset value.
Bits 19:16 ADDRMAP_ROW_B4[3:0]: Selects the HIF address bits used as row address bit 4.
Valid Range: 0 to 11
Internal Base: 10
The selected HIF address bit for each of the row address bits is determined by adding the
internal base to the value of this field. This register field is used only when
ADDRMAP5.addrmap_row_b2_10 is set to value 15.
Programming mode: Static
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:8 ADDRMAP_ROW_B3[3:0]: Selects the HIF address bits used as row address bit 3.
Valid Range: 0 to 11
Internal Base: 9
The selected HIF address bit for each of the row address bits is determined by adding the
internal base to the value of this field. This register field is used only when
ADDRMAP5.addrmap_row_b2_10 is set to value 15.
Programming mode: Static
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 ADDRMAP_ROW_B2[3:0]: Selects the HIF address bits used as row address bit 2.
Valid Range: 0 to 11
Internal Base: 8
The selected HIF address bit for each of the row address bits is determined by adding the
internal base to the value of this field. This register field is used only when
ADDRMAP5.addrmap_row_b2_10 is set to value 15.
Programming mode: Static
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16
ADDRMAP_ROW_B4[3:0]
rw
RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.54
DDRCTRL address map register 10 (DDRCTRL_ADDRMAP10)
Address offset: 0x228
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
27
26
25
24
ADDRMAP_ROW_B9[3:0]
rw
rw
rw
rw
11
10
9
8
ADDRMAP_ROW_B7[3:0]
rw
rw
rw
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
Res.
Res.
Res.
Res.
rw
19
18
17
16
ADDRMAP_ROW_B8[3:0]
rw
rw
rw
rw
3
2
1
0
ADDRMAP_ROW_B6[3:0]
rw
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:24 ADDRMAP_ROW_B9[3:0]: Selects the HIF address bits used as row address bit 9.
Valid Range: 0 to 11
Internal Base: 15
The selected HIF address bit for each of the row address bits is determined by adding the
internal base to the value of this field. This register field is used only when
ADDRMAP5.addrmap_row_b2_10 is set to value 15.
Programming mode: Static
Bits 23:20 Reserved, must be kept at reset value.
Bits 19:16 ADDRMAP_ROW_B8[3:0]: Selects the HIF address bits used as row address bit 8.
Valid Range: 0 to 11
Internal Base: 14
The selected HIF address bit for each of the row address bits is determined by adding the
internal base to the value of this field. This register field is used only when
ADDRMAP5.addrmap_row_b2_10 is set to value 15.
Programming mode: Static
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:8 ADDRMAP_ROW_B7[3:0]: Selects the HIF address bits used as row address bit 7.
Valid Range: 0 to 11
Internal Base: 13
The selected HIF address bit for each of the row address bits is determined by adding the
internal base to the value of this field. This register field is used only when
ADDRMAP5.addrmap_row_b2_10 is set to value 15.
Programming mode: Static
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 ADDRMAP_ROW_B6[3:0]: Selects the HIF address bits used as row address bit 6.
Valid Range: 0 to 11
Internal Base: 12
The selected HIF address bit for each of the row address bits is determined by adding the
internal base to the value of this field. This register field is used only when
ADDRMAP5.addrmap_row_b2_10 is set to value 15.
Programming mode: Static
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.55
RM0442
DDRCTRL address map register 11 (DDRCTRL_ADDRMAP11)
Address offset: 0x22C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADDRMAP_ROW_B10[3:0]
rw
rw
rw
rw
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 ADDRMAP_ROW_B10[3:0]: Selects the HIF address bits used as row address bit 10.
Valid Range: 0 to 11
Internal Base: 16
The selected HIF address bit for each of the row address bits is determined by adding the
internal base to the value of this field. This register field is used only when
ADDRMAP5.addrmap_row_b2_10 is set to value 15.
Programming mode: Static
5.7.56
DDRCTRL ODT configuration register (DDRCTRL_ODTCFG)
Address offset: 0x240
Reset value: 0x0400 0400
31
30
29
28
Res.
Res.
Res.
Res.
27
rw
15
14
13
12
Res.
Res.
Res.
Res.
26
25
24
WR_ODT_HOLD[3:0]
11
rw
rw
rw
10
9
8
RD_ODT_HOLD[3:0]
rw
rw
rw
23
22
21
Res.
Res.
Res.
7
rw
Bits 31:28 Reserved, must be kept at reset value.
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Res.
RM0442 Rev 7
5
20
19
18
rw
rw
rw
4
3
2
RD_ODT_DELAY[4:0]
rw
rw
17
16
WR_ODT_DELAY[4:0]
rw
rw
rw
rw
rw
1
0
Res.
Res.
RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bits 27:24 WR_ODT_HOLD[3:0]:
DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2.
Recommended values:
DDR2:
- BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800), 0x7 (DDR2-1066)
- BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066)
DDR3:
- BL8: 0x6
DDR4:
- BL8: 5 + WR_PREAMBLE + CRC_MODE
WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble)
CRC_MODE = 0 (not CRC mode), 1 (CRC mode)
LPDDR3:
- BL8: 7 + RU(tODTon(max)/tCK)
Programming mode: Quasi-dynamic Group 1 and Group 4
Bits 23:21 Reserved, must be kept at reset value.
Bits 20:16 WR_ODT_DELAY[4:0]:
The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values
associated with that command. ODT setting must remain constant for the entire time that DQS
is driven by the DDRCTRL.
Recommended values:
DDR2:
- CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066)
If (CWL + AL - 3 < 0), DDRCTRL does not support ODT for write operation.
DDR3:
- 0x0
DDR4:
- DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode)
LPDDR3:
- WL - 1 - RU(tODTon(max)/tCK))
Programming mode: Quasi-dynamic Group 1 and Group 4
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:8 RD_ODT_HOLD[3:0]:
DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2.
Recommended values:
DDR2:
- BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066)
- BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066)
DDR3:
- BL8 - 0x6
DDR4:
- BL8: 5 + RD_PREAMBLE
RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble)
LPDDR3:
- BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tCK)
Programming mode: Quasi-dynamic Group 1 and Group 4
RM0442 Rev 7
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Bit 7 Reserved, must be kept at reset value.
Bits 6:2 RD_ODT_DELAY[4:0]:
The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values
associated with that command. ODT setting must remain constant for the entire time that DQS
is driven by the DDRCTRL.
Recommended values:
DDR2:
- CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066)
If (CL + AL - 4 < 0), DDRCTRL does not support ODT for read operation.
DDR3:
- CL - CWL
DDR4:
- CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL
mode)
WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble)
RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble)
If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, DDRCTRL does not support ODT
for read operation.
LPDDR3:
- RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)
Programming mode: Quasi-dynamic Group 1 and Group 4.
Bits 1:0 Reserved, must be kept at reset value.
5.7.57
DDRCTRL ODT/Rank map register (DDRCTRL_ODTMAP)
Address offset: 0x244
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RANK0_RD_ODT
Res.
Res.
Res.
RANK0_WR_ODT
Reset value: 0x0000 0011
rw
rw
Bits 31:5 Reserved, must be kept at reset value.
Bit 4 RANK0_RD_ODT: Indicates which remote ODTs must be turned on during a read from rank 0.
Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the
appropriate bit here.
Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc.
For each rank, set its bit to 1 to enable its ODT.
Programming mode: Static
Bits 3:1 Reserved, must be kept at reset value.
274/3930
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RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bit 0 RANK0_WR_ODT: Indicates which remote ODTs must be turned on during a write to rank 0.
Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the
appropriate bit here.
Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc.
For each rank, set its bit to 1 to enable its ODT.
Programming mode: Static
5.7.58
DDRCTRL scheduler control register (DDRCTRL_SCHED)
Address offset: 0x250
Reset value: 0x0000 0805
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FORCE_LOW_PRI_N
GO2CRITICAL_HYSTERESIS[7:0]
PREFER_WRITE
RDWR_IDLE_GAP[6:0]
PAGECLOSE
Res.
rw
rw
rw
LPR_NUM_ENTRIES[3:0]
rw
rw
rw
rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:24 RDWR_IDLE_GAP[6:0]: When the preferred transaction store is empty for these many clock
cycles, switch to the alternate transaction store if it is non-empty.
The read transaction store (both high and low priority) is the default preferred transaction store
and the write transaction store is the alternative store.
When prefer write over read is set this is reversed.
0x0 is a legal value for this register. When set to 0x0, the transaction store switching happens
immediately when the switching conditions become true.
FOR PERFORMANCE ONLY
Programming mode: Static
Bits 23:16 GO2CRITICAL_HYSTERESIS[7:0]: UNUSED
Programming mode: Static
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:8 LPR_NUM_ENTRIES[3:0]: Number of entries in the low priority transaction store is this value +
1.
(MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of entries available
for the high priority transaction store.
Setting this to maximum value allocates all entries to low priority transaction store.
Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high priority
transaction store.
Note: In ECC configurations, the numbers of write and low priority read credits issued is one
less than in the non-ECC case. One entry each is reserved in the write and low-priority read
CAMs for storing the RMW requests arising out of single bit error correction RMW operation.
Programming mode: Static
RM0442 Rev 7
275/3930
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 PAGECLOSE: If true, bank is kept open only while there are page hit transactions available in
the CAM to that bank. The last read or write command in the CAM with a bank and page hit is
executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and
SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be
issued in some cases where there is a mode switch between write and read or between LPR
and HPR. The Read and Write commands that are executed as part of the ECC scrub requests
are also executed without auto-precharge.
If false, the bank remains open until there is a need to close it (to open a different page, or for
page timeout or refresh timeout) - also known as open page policy. The open page policy can
be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre).
The pageclose feature provids a midway between Open and Close page policies.
For performance only.
Programming mode: Quasi-dynamic Group 3
Bit 1 PREFER_WRITE: If set then the bank selector prefers writes over reads.
FOR DEBUG ONLY.
Programming mode: Static
Bit 0 FORCE_LOW_PRI_N: Active low signal. When asserted ('0'), all incoming transactions are
forced to low priority. This implies that all high priority read (HPR) and variable priority read
commands (VPR) are treated as low priority read (LPR) commands. On the write side, all
variable priority write (VPW) commands are treated as normal priority write (NPW) commands.
Forcing the incoming transactions to low priority implicitly turns off bypass path for read
commands.
For performance only.
Programming mode: Static
5.7.59
DDRCTRL scheduler control register 1 (DDRCTRL_SCHED1)
Address offset: 0x254
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
rw
rw
rw
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PAGECLOSE_TIMER[7:0]
rw
Bits 31:8 Reserved, must be kept at reset value.
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RM0442 Rev 7
rw
rw
rw
rw
RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bits 7:0 PAGECLOSE_TIMER[7:0]: This field works in conjunction with SCHED.pageclose.
It only has meaning if SCHED.pageclose==1.
If SCHED.pageclose==1 and pageclose_timer==0, then an auto-precharge may be scheduled
for last read
or write command in the CAM with a bank and page hit.
Note, sometimes an explicit precharge is scheduled instead of the auto-precharge. See
SCHED.pageclose for details of when this may happen.
If SCHED.pageclose==1 and pageclose_timer>0, then an auto-precharge is not scheduled for
last read
or write command in the CAM with a bank and page hit.
Instead, a timer is started, with pageclose_timer as the initial value.
There is a timer on a per bank basis.
The timer decrements unless the next read or write in the CAM to a bank is a page hit.
It gets reset to pageclose_timer value if the next read or write in the CAM to a bank is a page
hit.
Once the timer has reached zero, an explicit precharge is attempted to be scheduled.
Programming mode: Static.
5.7.60
DDRCTRL high priority read CAM register 1
(DDRCTRL_PERFHPR1)
Address offset: 0x25C
Reset value: 0x0F00 0001
31
30
29
28
27
rw
rw
rw
rw
rw
15
14
13
12
11
26
25
24
rw
rw
rw
10
9
8
HPR_XACT_RUN_LENGTH[7:0]
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
HPR_MAX_STARVE[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:24 HPR_XACT_RUN_LENGTH[7:0]:
Number of transactions that are serviced once the HPR queue goes critical is the smaller of:
- (a) This number
- (b) Number of transactions available.
Unit: Transaction.
For performance only.
Programming mode: Quasi-dynamic Group 3
Bits 23:16 Reserved, must be kept at reset value.
Bits 15:0 HPR_MAX_STARVE[15:0]: Number of DFI clocks that the HPR queue can be starved before it
goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0
disables the starvation functionality; during normal operation, this function must not be disabled
as it causes excessive latencies.
For performance only.
Programming mode: Quasi-dynamic Group 3
RM0442 Rev 7
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.61
RM0442
DDRCTRL low priority read CAM register 1 (DDRCTRL_PERFLPR1)
Address offset: 0x264
Reset value: 0x0F00 007F
31
30
29
28
27
26
25
24
LPR_XACT_RUN_LENGTH[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
rw
rw
rw
rw
rw
rw
rw
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
LPR_MAX_STARVE[15:0]
rw
rw
Bits 31:24 LPR_XACT_RUN_LENGTH[7:0]:
Number of transactions that are serviced once the LPR queue goes critical is the smaller of:
- (a) This number
- (b) Number of transactions available.
Unit: Transaction.
For performance only
Programming mode: Quasi-dynamic group 3
Bits 23:16 Reserved, must be kept at reset value.
Bits 15:0 LPR_MAX_STARVE[15:0]: Number of DFI clocks that the LPR queue can be starved before it
goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0
disables the starvation functionality; during normal operation, this function must be disabled as
it causes excessive latencies.
For performance only
Programming mode: Quasi-dynamic Group 3
5.7.62
DDRCTRL write CAM register 1 (DDRCTRL_PERFWR1)
Address offset: 0x26C
Reset value: 0x0F00 007F
31
30
29
28
27
26
25
24
W_XACT_RUN_LENGTH[7:0]
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
8
W_MAX_STARVE[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:24 W_XACT_RUN_LENGTH[7:0]:
Number of transactions that are serviced once the WR queue goes critical is the smaller of:
- (a) This number
- (b) Number of transactions available.
Unit: Transaction.
For performance only.
Programming mode: Quasi-dynamic Group 3.
Bits 23:16 Reserved, must be kept at reset value.
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RM0442 Rev 7
RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bits 15:0 W_MAX_STARVE[15:0]: Number of DFI clocks that the WR queue can be starved before it
goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0
disables the starvation functionality; during normal operation, this function must not be disabled
as it causes excessive latencies.
For performance only.
Programming mode: Quasi-dynamic Group 3.
5.7.63
DDRCTRL debug register 0 (DDRCTRL_DBG0)
Address offset: 0x300
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DIS_COLLISION_PAGE_OPT
Res.
Res.
Res.
DIS_WC
Reset value: 0x0000 0000
rw
rw
Bits 31:5 Reserved, must be kept at reset value.
Bit 4 DIS_COLLISION_PAGE_OPT: When this is set to '0', auto-precharge is disabled for the
flushed command in a collision case. Collision cases are write followed by read to same
address, read followed by write to same address, or write followed by write to same address
with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits
representing critical word).
FOR DEBUG ONLY.
Programming mode: Static
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 DIS_WC: When 1, disable write combine.
FOR DEBUG ONLY
Programming mode: Static
RM0442 Rev 7
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.64
RM0442
DDRCTRL debug register 1 (DDRCTRL_DBG1)
Address offset: 0x304
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DIS_HIF
DIS_DQ
Reset value: 0x0000 0000
rw
rw
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 DIS_HIF: When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL
ignores the hif_cmd_valid and all other associated request signals.
This bit is intended to be switched on-the-fly.
Programming mode: Dynamic
Bit 0 DIS_DQ: When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is
also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM
as long as this is asserted.
This bit may be used to prevent reads or writes being issued by the DDRCTRL, which makes it
safe to modify certain register fields associated with reads and writes (see User Guide for
details). After setting this bit, it is strongly recommended to poll
DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty, before making
changes to any registers which affect reads and writes. This ensures that the relevant logic in
the DDRC is idle.
This bit is intended to be switched on-the-fly.
Programming mode: Dynamic
5.7.65
DDRCTRL CAM debug register (DDRCTRL_DBGCAM)
Address offset: 0x308
31
30
29
28
27
26
25
24
23
22
21
Res.
Res.
WR_DATA_PIPELINE_EMPTY
RD_DATA_PIPELINE_EMPTY
Res.
DBG_WR_Q_EMPTY
DBG_RD_Q_EMPTY
DBG_STALL
Reset value: 0x0000 0000
Res.
Res.
Res.
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
Res.
Res.
Res.
Res.
Res.
Res.
DBG_LPR_Q_DEPTH[4:0]
r
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r
r
r
RM0442 Rev 7
20
19
18
17
16
DBG_W_Q_DEPTH[4:0]
r
r
r
r
r
4
3
2
1
0
DBG_HPR_Q_DEPTH[4:0]
r
r
r
r
r
RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 WR_DATA_PIPELINE_EMPTY: This bit indicates that the write data pipeline on the DFI
interface is empty. This register is intended to be polled at least twice after setting
DBG1.dis_dq, to ensure that all remaining commands/data have completed.
Programming mode: Dynamic.
Bit 28 RD_DATA_PIPELINE_EMPTY: This bit indicates that the read data pipeline on the DFI
interface is empty. This register is intended to be polled at least twice after setting
DBG1.dis_dq, to ensure that all remaining commands/data have completed.
Programming mode: Dynamic.
Bit 27 Reserved, must be kept at reset value.
Bit 26 DBG_WR_Q_EMPTY: When 1, all the Write command queues and Write data buffers inside
DDRC are empty. This register is to be used for debug purpose.
An example use-case scenario: When Controller enters Self-Refresh using the Low-Power
entry sequence, Controller is expected to have executed all the commands in its queues and
the write and read data drained. Hence this register should be 1 at that time.
For debug only.
Programming mode: Dynamic.
Bit 25 DBG_RD_Q_EMPTY: When 1, all the Read command queues and Read data buffers inside
DDRC are empty. This register is to be used for debug purpose.
An example use-case scenario: When Controller enters Self-Refresh using the Low-Power
entry sequence, Controller is expected to have executed all the commands in its queues and
the write and read data drained. Hence this register should be 1 at that time.
For debug only.
Programming mode: Dynamic
Bit 24 DBG_STALL: Stall
For debug only.
Programming mode: Dynamic
Bits 23:21 Reserved, must be kept at reset value.
Bits 20:16 DBG_W_Q_DEPTH[4:0]: Write queue depth
The last entry of WR queue is reserved for ECC SCRUB operation. This entry is not included in
the calculation of the queue depth.
For debug only.
Programming mode: Dynamic
Bits 15:13 Reserved, must be kept at reset value.
Bits 12:8 DBG_LPR_Q_DEPTH[4:0]: Low priority read queue depth
The last entry of Lpr queue is reserved for ECC SCRUB operation. This entry is not included in
the calculation of the queue depth.
For debug only.
Programming mode: Dynamic
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 DBG_HPR_Q_DEPTH[4:0]: High priority read queue depth
For debug only.
Programming mode: Dynamic
RM0442 Rev 7
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.66
RM0442
DDRCTRL command debug register (DDRCTRL_DBGCMD)
Address offset: 0x30C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CTRLUPD
ZQ_CALIB_SHOR
T
Res.
Res.
Res.
RANK0_REFRESH
Reset value: 0x0000 0000
rs
rs
rs
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 CTRLUPD:
Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY.
When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation
must only be performed when DFIUPD0.dis_auto_ctrlupd=1.
Programming mode: Dynamic.
Bit 4 ZQ_CALIB_SHORT:
Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration
short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the
DDRCTRL, the bit is automatically cleared. This operation can be performed only when
ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in SelfRefresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes
or maximum power saving mode.
For self-refresh(except LPDDR4) or SR-powerdown(LPDDR4) it is scheduled after SR(except
LPDDR4) or SPRD(LPDDR4) has been exited.
For Deep power down and maximum power saving mode, it is not scheduled, although
DBGSTAT.zq_calib_short_busy is de-asserted.
Programming mode: Dynamic.
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 RANK0_REFRESH:
Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to
this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy
is cleared, the command has been stored in DDRCTRL.
For 3DS configuration, refresh is sent to rank index 0.
This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is
recommended NOT to set this register bit if in Init or Deep power-down operating modes or
Maximum Power Saving Mode.
Programming mode: Dynamic.
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RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.67
DDRCTRL status debug register (DDRCTRL_DBGSTAT)
Address offset: 0x310
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CTRLUPD_BUSY
ZQ_CALIB_SHORT_BUSY
Res.
Res.
Res.
RANK0_REFRESH_BUSY
Reset value: 0x0000 0000
r
r
r
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 CTRLUPD_BUSY: SoC core may initiate a ctrlupd operation only if this signal is low. This
signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when
the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd
operations when this signal is high.
- 0 - Indicates that the SoC core can initiate a ctrlupd operation
- 1 - Indicates that ctrlupd operation has not been initiated yet in the DDRCTRL
Programming mode: Dynamic
Bit 4 ZQ_CALIB_SHORT_BUSY: SoC core may initiate a ZQCS (ZQ calibration short) operation
only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the
ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is
recommended not to perform ZQCS operations when this signal is high.
- 0 - Indicates that the SoC core can initiate a ZQCS operation
- 1 - Indicates that ZQCS operation has not been initiated yet in the DDRCTRL
Programming mode: Dynamic
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 RANK0_REFRESH_BUSY: SoC core may initiate a rank0_refresh operation (refresh operation
to rank 0) only if this signal is low. This signal goes high in the clock after
DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in
the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is
high.
- 0 - Indicates that the SoC core can initiate a rank0_refresh operation
- 1 - Indicates that rank0_refresh operation has not been stored yet in the DDRCTRL
Programming mode: Dynamic
RM0442 Rev 7
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DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.68
RM0442
DDRCTRL software register programming control enable
(DDRCTRL_SWCTL)
Address offset: 0x320
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SW_DONE
Reset value: 0x0000 0001
rw
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 SW_DONE: Enable quasi-dynamic register programming outside reset. Program register to 0
to enable quasi-dynamic programming. Set back register to 1 once programming is done.
Programming mode: Dynamic
5.7.69
DDRCTRL software register programming control status
(DDRCTRL_SWSTAT)
Address offset: 0x324
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SW_DONE_ACK
Reset value: 0x0000 0001
r
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 SW_DONE_ACK: Register programming done. This register is the echo of SWCTL.sw_done.
Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming
sequence to ensure that the correct registers values are propagated to the destination clock
domains.
Programming mode: Static
284/3930
RM0442 Rev 7
RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.70
DDRCTRL AXI Poison configuration register
(DDRCTRL_POISONCFG)
Address offset: 0x36C
Reset value: 0x0011 0011
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RD_POISON_INTR_CLR
Res.
Res.
Res.
RD_POISON_INTR_EN
Res.
Res.
Res.
RD_POISON_SLVERR_EN
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WR_POISON_INTR_CLR
Res.
Res.
Res.
WR_POISON_INTR_EN
Res.
Res.
Res.
WR_POISON_SLVERR_EN
AXI Poison configuration register common for all AXI ports.
rc_w1
rw
rc_w1
rw
rw
rw
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 RD_POISON_INTR_CLR: Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles
for correct value to propagate to core logic and clear the interrupts.
Programming mode: Dynamic
Bits 23:21 Reserved, must be kept at reset value.
Bit 20 RD_POISON_INTR_EN: If set to 1, enables interrupts for read transaction poisoning
Programming mode: Dynamic
Bits 19:17 Reserved, must be kept at reset value.
Bit 16 RD_POISON_SLVERR_EN: If set to 1, enables SLVERR response for read transaction
poisoning
Programming mode: Dynamic
Bits 15:9 Reserved, must be kept at reset value.
Bit 8 WR_POISON_INTR_CLR: Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles
for correct value to propagate to core logic and clear the interrupts.
Programming mode: Dynamic
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 WR_POISON_INTR_EN: If set to 1, enables interrupts for write transaction poisoning
Programming mode: Dynamic
Bits 3:1 Reserved, must be kept at reset value.
RM0442 Rev 7
285/3930
312
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Bit 0 WR_POISON_SLVERR_EN: If set to 1, enables SLVERR response for write transaction
poisoning
Programming mode: Dynamic
5.7.71
DDRCTRL AXI Poison status register (DDRCTRL_POISONSTAT)
Address offset: 0x370
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RD_POISON_INTR_1
RD_POISON_INTR_0
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WR_POISON_INTR_1
WR_POISON_INTR_0
Reset value: 0x0000 0000
r
r
Bits 31:18 Reserved, must be kept at reset value.
Bit 17 RD_POISON_INTR_1: Read transaction poisoning error interrupt for port 1. This register is a
APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is
poisoned on the corresponding AXI port's read address channel. Bit 0 corresponds to Port 0,
and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB
clock.
Programming mode: Dynamic
Bit 16 RD_POISON_INTR_0: Read transaction poisoning error interrupt for port 0. This register is a
APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is
poisoned on the corresponding AXI port's read address channel. Bit 0 corresponds to Port 0,
and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB
clock.
Programming mode: Dynamic
Bits 15:2 Reserved, must be kept at reset value.
Bit 1 WR_POISON_INTR_1: Write transaction poisoning error interrupt for port 1. This register is a
APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is
poisoned on the corresponding AXI port's write address channel. Bit 0 corresponds to Port 0,
and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB
clock.
Programming mode: Dynamic
286/3930
RM0442 Rev 7
RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bit 0 WR_POISON_INTR_0: Write transaction poisoning error interrupt for port 0. This register is a
APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is
poisoned on the corresponding AXI port's write address channel. Bit 0 corresponds to Port 0,
and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB
clock.
Programming mode: Dynamic
5.7.72
DDRCTRL port status register (DDRCTRL_PSTAT)
Address offset: 0x3FC
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WR_PORT_BUSY_1
WR_PORT_BUSY_0
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RD_PORT_BUSY_1
RD_PORT_BUSY_0
Reset value: 0x0000 0000
r
r
Bits 31:18 Reserved, must be kept at reset value.
Bit 17 WR_PORT_BUSY_1: Indicates if there are outstanding writes for AXI port 1.
Programming mode: Dynamic
Bit 16 WR_PORT_BUSY_0: Indicates if there are outstanding writes for AXI port 0.
Programming mode: Dynamic
Bits 15:2 Reserved, must be kept at reset value.
Bit 1 RD_PORT_BUSY_1: Indicates if there are outstanding reads for AXI port 1.
Programming mode: Dynamic
Bit 0 RD_PORT_BUSY_0: Indicates if there are outstanding reads for AXI port 0.
Programming mode: Dynamic
RM0442 Rev 7
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312
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.73
RM0442
DDRCTRL port common configuration register (DDRCTRL_PCCFG)
Address offset: 0x400
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BL_EXP_MODE
Res.
Res.
Res.
PAGEMATCH_LIMIT
Res.
Res.
Res.
GO2CRITICAL_EN
Reset value: 0x0000 0000
rw
rw
rw
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 BL_EXP_MODE: Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI
expands every AXI burst into multiple HIF commands, using the memory burst length as a unit.
If set to 1, then XPI uses half of the memory burst length as a unit.
This applies to both reads and writes. When MSTR.data_bus_width==00, setting
bl_exp_mode to 1 has no effect.
This can be used in cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1), in
order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd_mw penalty in LPDDR4. Hence,
bl_exp_mode=1 is only recommended if DDR4 or LPDDR4.
Note that if DBICTL.dm_en=0, functionality is not supported in the following cases:
- UMCTL2_PARTIAL_WR=0
- UMCTL2_PARTIAL_WR=1, MSTR.data_bus_width=01, MEMC_BURST_LENGTH=8 and
MSTR.burst_rdwr=1000 (LPDDR4 only)
- UMCTL2_PARTIAL_WR=1, MSTR.data_bus_width=01, MEMC_BURST_LENGTH=4 and
MSTR.burst_rdwr=0100 (DDR4 only), with either MSTR.burstchop=0 or
CRCPARCTL1.crc_enable=1
Functionality is also not supported if Data Channel Interleave is enabled.
Programming mode: Static.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 PAGEMATCH_LIMIT: Page match four limit. If set to 1, limits the number of consecutive same
page DDRC transactions that can be granted by the Port Arbiter to four when Page Match
feature is enabled.
If set to 0, there is no limit imposed on number of consecutive same
page DDRC transactions.
Programming mode: Static.
Bits 3:1 Reserved, must be kept at reset value.
288/3930
RM0442 Rev 7
RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bit 0 GO2CRITICAL_EN: If set to 1 (enabled), sets co_gs_go2critical_wr and
co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input
(awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and
co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.
Programming mode: Static.
5.7.74
DDRCTRL port x configuration read register (DDRCTRL_PCFGR_x)
Address offset: 0x404 + 0xB0 * x, (x = 0 to 1)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RDWR_ORDERED_EN
Reset value: 0x0000 4000
15
14
13
12
11
10
Res.
RD_PORT_PAGEMATCH_EN
RD_PORT_URGENT_EN
RD_PORT_AGING_EN
rw
Res.
Res.
rw
rw
rw
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
RD_PORT_PRIORITY[9:0]
rw
rw
rw
rw
rw
rw
rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 RDWR_ORDERED_EN: Enables ordered read/writes. If set to 1, preserves the ordering
between read transaction and write transaction issued to the same address, on a given port. In
other words, the controller ensures that all same address read and write commands from the
application port interface are transported to the DFI interface in the order of acceptance. This
feature is useful in cases where software coherency is desired for masters issuing back-to-back
read/write transactions without waiting for write/read responses. Note that this register has an
effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter.
Programming mode: Static.
Bit 15 Reserved, must be kept at reset value.
Bit 14 RD_PORT_PAGEMATCH_EN: If set to 1, enables the Page Match feature. If enabled, once a
requesting port is granted, the port is continued to be granted if the following immediate
commands are to the same memory page (same bank and same row). See also related
PCCFG.pagematch_limit register.
Programming mode: Static
RM0442 Rev 7
289/3930
312
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Bit 13 RD_PORT_URGENT_EN: If set to 1, enables the AXI urgent sideband signal (arurgent). When
enabled and arurgent is asserted by the master, that port becomes the highest priority and
co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in
PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long
as required which is independent of address handshaking (it is not associated with any
particular command).
Programming mode: Static
Bit 12 RD_PORT_AGING_EN: If set to 1, enables aging function for the read channel of the port.
Programming mode: Static
Bits 11:10 Reserved, must be kept at reset value.
Bits 9:0 RD_PORT_PRIORITY[9:0]: Determines the initial load value of read aging counters. These
counters are parallel loaded after reset, or after each grant to the corresponding port. The
aging counters down-count every clock cycle where the port is requesting but not granted. The
higher significant 5-bits of the read aging counter sets the priority of the read channel of a given
port. Port's priority increases as the higher significant 5-bits of the counter starts to decrease.
When the aging counter becomes 0, the corresponding port channel has the highest priority
level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be
used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is
still applicable). For single port configurations, the aging counters are only used when they
timeout (become 0) to force read-write direction switching. In this case, external dynamic
priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority
levels: low priority read - LPR, high priority read - HPR) on a command by command basis.
Note: The two LSBs of this register field are tied internally to 2'b00.
Programming mode: Static
5.7.75
DDRCTRL port x configuration write register
(DDRCTRL_PCFGW_x)
Address offset: 0x408 + 0xB0 * x, (x = 0 to 1)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
WR_PORT_PAGEMATCH_EN
WR_PORT_URGENT_EN
WR_PORT_AGING_EN
Reset value: 0x0000 4000
Res.
Res.
rw
rw
rw
rw
rw
rw
WR_PORT_PRIORITY[9:0]
rw
rw
rw
Bits 31:15 Reserved, must be kept at reset value.
290/3930
RM0442 Rev 7
rw
rw
rw
rw
RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bit 14 WR_PORT_PAGEMATCH_EN: If set to 1, enables the Page Match feature. If enabled, once a
requesting port is granted, the port is continued to be granted if the following immediate
commands are to the same memory page (same bank and same row). See also related
PCCFG.pagematch_limit register.
Programming mode: Static
Bit 13 WR_PORT_URGENT_EN: If set to 1, enables the AXI urgent sideband signal (awurgent).
When enabled and awurgent is asserted by the master, that port becomes the highest priority
and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en
register.
Note that awurgent signal can be asserted anytime and as long as required which is
independent of address handshaking (it is not associated with any particular command).
Programming mode: Static
Bit 12 WR_PORT_AGING_EN: If set to 1, enables aging function for the write channel of the port.
Programming mode: Static
Bits 11:10 Reserved, must be kept at reset value.
Bits 9:0 WR_PORT_PRIORITY[9:0]: Determines the initial load value of write aging counters. These
counters are parallel loaded after reset, or after each grant to the corresponding port. The
aging counters down-count every clock cycle where the port is requesting but not granted. The
higher significant 5-bits of the write aging counter sets the initial priority of the
write
channel of a given port. Port's priority increases as the higher significant 5-bits of the counter
starts to decrease. When the aging counter becomes 0, the corresponding port channel has the
highest priority level.
For multi-port configurations, the aging counters cannot be used to set port priorities when
external dynamic priority inputs (awqos) are enabled (timeout is still applicable).
For single port configurations, the aging counters are only used when they timeout (become 0)
to force read-write direction switching.
Note: The two LSBs of this register field are tied internally to 2'b00.
Programming mode: Static
5.7.76
DDRCTRL port x control register (DDRCTRL_PCTRL_x)
Address offset: 0x490 + 0xB0 * x, (x = 0 to 1)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PORT_EN
Reset value: 0x0000 0000
rw
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 PORT_EN: Enables AXI port n.
Programming mode: Dynamic
RM0442 Rev 7
291/3930
312
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
5.7.77
RM0442
DDRCTRL port x read Q0S configuration register 0
(DDRCTRL_PCFGQOS0_x)
Address offset: 0x494 + 0xB0 * x, (x = 0 to 1)
Reset value: 0x0200 0E00
28
27
26
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
Res.
Res.
Res.
Res.
25
24
rw
rw
9
8
RQOS_MAP_LEVEL2[3:0]
rw
rw
rw
23
22
Res.
Res.
rw
rw
7
6
5
4
Res.
Res.
Res.
Res.
rw
21
20
19
18
Res.
Res.
3
2
17
16
RQOS_MAP_REGION0[1:0]
29
RQOS_MAP_REGION1[1:0]
30
RQOS_MAP_REGION2[1:0]
31
rw
rw
1
0
RQOS_MAP_LEVEL1[3:0]
rw
rw
rw
rw
Bits 31:26 Reserved, must be kept at reset value.
Bits 25:24 RQOS_MAP_REGION2[1:0]: This bitfield indicates the traffic class of region2.
For dual address queue configurations, region2 maps to the red address queue.
Valid values are 1: VPR and 2: HPR only.
When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 is set to 1
(VPR), VPR traffic is aliased to LPR traffic.
Programming mode: Quasi-dynamic Group 3
Bits 23:22 Reserved, must be kept at reset value.
Bits 21:20 RQOS_MAP_REGION1[1:0]: This bitfield indicates the traffic class of region 1.
Valid values are:
- 0 : LPR,
- 1: VPR,
- 2: HPR.
For dual address queue configurations, region1 maps to the blue address queue.
In this case, valid values are
- 0: LPR and
- 1: VPR only.
When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1
(VPR), VPR traffic is aliased to LPR traffic.
Programming mode: Quasi-dynamic Group 3
Bits 19:18 Reserved, must be kept at reset value.
292/3930
RM0442 Rev 7
RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bits 17:16 RQOS_MAP_REGION0[1:0]: This bitfield indicates the traffic class of region 0.
Valid values are:
- 0: LPR, 1: VPR, 2: HPR.
For dual address queue configurations, region 0 maps to the blue address queue.
In this case, valid values are:
- 0: LPR and 1: VPR only.
When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1
(VPR), VPR traffic is aliased to LPR traffic.
Programming mode: Quasi-dynamic Group 3
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:8 RQOS_MAP_LEVEL2[3:0]: Separation level2 indicating the end of region1 mapping; start of
region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to
arqos.
Region2 starts from (level2 + 1) up to 15.
Note that for PA, arqos values are used directly as port priorities, where the higher the value
corresponds to higher port priority.
All of the map_level* registers must be set to distinct values.
Programming mode: Quasi-dynamic Group 3
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 RQOS_MAP_LEVEL1[3:0]: Separation level1 indicating the end of region0 mapping; start of
region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ)
which corresponds to arqos.
Note that for PA, arqos values are used directly as port priorities, where the higher the value
corresponds to higher port priority.
All of the map_level* registers must be set to distinct values.
Programming mode: Quasi-dynamic Group 3
5.7.78
DDRCTRL port x read Q0S configuration register 1
(DDRCTRL_PCFGQOS1_x)
Address offset: 0x498 + 0xB0 * x, (x = 0 to 1)
Reset value: 0x0000 0000
31
30
29
28
27
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
Res.
Res.
Res.
Res.
Res.
26
25
24
23
22
21
20
19
18
17
16
RQOS_MAP_TIMEOUTR[10:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
RQOS_MAP_TIMEOUTB[10:0]
rw
rw
rw
rw
rw
rw
rw
Bits 31:27 Reserved, must be kept at reset value.
Bits 26:16 RQOS_MAP_TIMEOUTR[10:0]: Specifies the timeout value for transactions mapped to the red
address queue. With single read address queue, there is no red queue and this value has no
effect.
Programming mode: Quasi-dynamic Group 3
Bits 15:11 Reserved, must be kept at reset value.
RM0442 Rev 7
293/3930
312
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Bits 10:0 RQOS_MAP_TIMEOUTB[10:0]: Specifies the timeout value for transactions mapped to the
blue address queue.
Programming mode: Quasi-dynamic Group 3.
5.7.79
DDRCTRL port x write Q0S configuration register 0
(DDRCTRL_PCFGWQOS0_x)
Address offset: 0x49C + 0xB0 * x, (x = 0 to 1)
Reset value: 0x0000 0E00
28
27
26
Res.
Res.
Res.
Res.
Res.
Res.
24
rw
rw
9
8
15
14
13
12
11
Res.
Res.
Res.
Res.
WQOS_MAP_LEVEL2[3:0]
rw
10
25
rw
rw
23
22
Res.
Res.
21
20
rw
18
Res.
Res.
rw
7
6
5
4
Res.
Res.
Res.
Res.
rw
19
3
2
17
16
WQOS_MAP_REGION0[1:0]
29
WQOS_MAP_REGION1[1:0]
30
WQOS_MAP_REGION2[1:0]
31
rw
rw
1
0
WQOS_MAP_LEVEL1[3:0]
rw
rw
rw
rw
Bits 31:26 Reserved, must be kept at reset value.
Bits 25:24 WQOS_MAP_REGION2[1:0]: This bitfield indicates the traffic class of region 2.
Valid values are:
0: NPW, 1: VPW.
When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 2 is set to 1
(VPW), VPW traffic is aliased to NPW traffic.
Programming mode: Quasi-dynamic Group 3
Bits 23:22 Reserved, must be kept at reset value.
Bits 21:20 WQOS_MAP_REGION1[1:0]: This bitfield indicates the traffic class of region 1.
Valid values are:
0: NPW, 1: VPW.
When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 1 is set to 1
(VPW), VPW traffic is aliased to NPW traffic.
Programming mode: Quasi-dynamic Group 3
Bits 19:18 Reserved, must be kept at reset value.
Bits 17:16 WQOS_MAP_REGION0[1:0]: This bitfield indicates the traffic class of region 0.
Valid values are:
0: NPW, 1: VPW.
When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 0 is set
to 1 (VPW), VPW traffic is aliased to NPW traffic.
Programming mode: Quasi-dynamic Group 3
Bits 15:12 Reserved, must be kept at reset value.
294/3930
RM0442 Rev 7
RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Bits 11:8 WQOS_MAP_LEVEL2[3:0]: Separation level2 indicating the end of region1 mapping; start of
region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to
awqos.
Region2 starts from (level2 + 1) up to 15.
Note that for PA, awqos values are used directly as port priorities, where the higher the value
corresponds to higher port priority.
All of the map_level* registers must be set to distinct values.
Programming mode: Quasi-dynamic Group 3
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 WQOS_MAP_LEVEL1[3:0]: Separation level indicating the end of region0 mapping; start of
region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos.
Note that for PA, awqos values are used directly as port priorities, where the higher the value
corresponds to higher port priority.
All of the map_level* registers must be set to distinct values.
Programming mode: Quasi-dynamic Group 3
5.7.80
DDRCTRL port x write Q0S configuration register 1
(DDRCTRL_PCFGWQOS1_x)
Address offset: 0x4A0 + 0xB0 * x, (x = 0 to 1)
Reset value: 0x0000 0000
31
30
29
28
27
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
Res.
Res.
Res.
Res.
Res.
26
25
24
23
22
21
rw
rw
rw
rw
rw
rw
10
9
8
7
6
5
20
19
18
17
16
rw
rw
rw
rw
rw
4
3
2
1
0
rw
rw
rw
rw
WQOS_MAP_TIMEOUT2[10:0]
WQOS_MAP_TIMEOUT1[10:0]
rw
rw
rw
rw
rw
rw
rw
Bits 31:27 Reserved, must be kept at reset value.
Bits 26:16 WQOS_MAP_TIMEOUT2[10:0]: Specifies the timeout value for write transactions in region 2.
Programming mode: Quasi-dynamic Group 3.
Bits 15:11 Reserved, must be kept at reset value.
Bits 10:0 WQOS_MAP_TIMEOUT1[10:0]: Specifies the timeout value for write transactions in region 0
and 1.
Programming mode: Quasi-dynamic Group 3.
RM0442 Rev 7
295/3930
312
0x024
296/3930
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DDRCTRL_DERATEEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RM0442 Rev 7
Reset value
0 0 0 0
Reset value
MR_WR_BUSY
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MR_TYPE
Res.
Res.
Res.
OPERATING_MODE[2:0]
Res.
SELFREF_TYPE[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
SELFREF_CAM_NOT_EMPTY
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0 0
DERATE_ENABLE
Res.
Res.
Res.
Res.
Res.
Res.
0 0
DERATE_VALUE[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0 0
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MR_ADDR[3:0]
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
DDRCTRL_MRCTRL1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0 0
Res.
DDRCTRL_MRSTAT
0 1 0 0 0
DERATE_BYTE[3:0]
Res.
Res.
Res.
Reset value
Res.
Reset value
Res.
Res.
0x020
Res.
Res.
0x01C
Res.
0x018
DDRCTRL_MRCTRL0
MR_WR
0x014
Res.
Res.
0x010
Res.
0x008 0x00C
DDRCTRL_STAT
Res.
0x004
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DDRCTRL_MSTR
DDR3
Res.
LPDDR2
LPDDR3
Res.
Res.
Res.
Res.
Res.
BURSTCHOP
EN_2T_TIMING_MODE
Res.
DATA_BUS_WIDTH[1:0]
Res.
DLL_OFF_MODE
BURST_RDWR[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Register Name
Res.
0x000
Res.
Offset
Res.
5.7.81
Res.
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
DDRCTRL registers summary
Table 19. DDRCTRL register map and reset values
1
0 0 0
0
MR_DATA[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
DDRCTRL_DERATEINT
0 0 0
MR4_READ_INTERVAL[31:0]
Reset value
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x054 0x05C
Res.
RM0442 Rev 7
0 0 0 0 0
Res.
Res.
0
Res.
0 0 0 0 0 0 0 0 0 0 0 0
Res.
HW_LP_EN
HW_LP_EXIT_IDLE_EN
POWERDOWN_TO_X32[4:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DIS_CAM_DRAIN_SELFREF
Res.
SELFREF_SW
Res.
EN_DFI_DRAM_CLK_DISABLE
SELFREF_EN
POWERDOWN_EN
DEEPPOWERDOWN_EN
Res.
Res.
Res.
Res.
DDRCTRL_PWRCTL
Res.
Res.
PER_BANK_REFRESH
Res.
0x028 0x02C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register Name
Res.
Res.
Res.
Res.
0
Res.
Res.
0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0
Res.
Res.
Res.
Res.
0
Res.
REFRESH_BURST[4:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
T_DPD_X4096[7:0]
Res.
Res.
Res.
Res.
REFRESH_TO_X32[4:0]
Res.
SELFREF_TO_X32[7:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
1 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
HW_LP_IDLE_X32[11:0]
Res.
0 0 1 0
Res.
Res.
Res.
Res.
REFRESH_MARGIN[3:0]
0x03C 0x04C
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
DDRCTRL_RFSHCTL0
Res.
0x050
DDRCTRL_HWLPCTL
Res.
0x038
DDRCTRL_PWRTMG
Res.
0x034
Res.
Offset
0x030
Res.
RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Table 19. DDRCTRL register map and reset values (continued)
0 0 0 0
1 0 0 0 0
1 1
Res.
297/3930
312
0x0D0
298/3930
DDRCTRL_INIT0
Reset value
0 0
Res.
POST_CKE_X1024[9:0]
0 0 0 0 0 0 0 0 1 0
RM0442 Rev 7
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DFI_ALERT_ERR_INT
Res.
DFI_ALERT_ERR_INT_EN
DFI_ALERT_ERR_INT_CLR
DFI_ALERT_ERR_CNT_CLR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LPDDR3_TREFBW_EN
Reset value
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0 0 0 0 0 1 1 0 0 0 1 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x068 0x0BC
Res.
Res.
T_RFC_NOM_X1_X32[11:0]
Res.
Res.
DDRCTRL_CRCPARSTAT
Res.
0
Res.
T_RFC_NOM_X1_SEL
Reset value
Res.
DDRCTRL_RFSHTMG
Res.
Res.
Res.
DDRCTRL_CRCPARCTL0
Res.
DIS_AUTO_REFRESH
REFRESH_UPDATE_LEVEL
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DDRCTRL_RFSHCTL3
Res.
0x0CC
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register Name
Res.
0x0C4 0x0C8
Res.
0x0C0
Res.
0x064
Res.
0x060
Res.
Offset
SKIP_DRAM_INIT[1:0]
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Table 19. DDRCTRL register map and reset values (continued)
0 0
T_RFC_MIN[9:0]
0 0 1 0 0 0 1 1 0 0
Res.
0 0 0
DFI_ALERT_ERR_CNT[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PRE_CKE_X1024[11:0]
0 0 0 0 0 1 0 0 1 1 1 0
0x0F4 0x0FC
Res.
RM0442 Rev 7
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DIMM_STAGGER_CS_EN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DIMM_ADDR_MIRR_EN
Res.
Res.
MAX_AUTO_INIT_X1024[9:0]
Res.
Res.
Res.
Res.
Res.
Res.
DEV_ZQINIT_X32[7:0]
0 0 0 0 1 1 0 1
Res.
Res.
Res.
MIN_STABLE_CLOCK_X1[3:0]
Res.
Res.
Res.
Res.
IDLE_AFTER_RESET_X32[7:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
0x0510
EMR3[15:0]
Res.
Res.
Res.
0
EMR2[15:0]
Res.
Res.
Res.
Res.
Res.
0 0 0 1 0 0 0 0
Res.
Res.
Res.
Res.
MR[15:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
DDRCTRL_INIT4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
DDRCTRL_INIT3
Res.
Res.
Res.
DDRCTRL_DIMMCTL
Res.
DDRCTRL_INIT5
Res.
Reset value
Res.
Res.
Res.
0x0F0
Reset value
Res.
0x0E8 0x0EC
DDRCTRL_INIT2
Res.
0x0E4
Res.
0x0E0
Res.
0x0DC
Res.
0x0D8
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DDRCTRL_INIT1
PRE_OCD_X32[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DRAM_RSTN_X1024[8:0]
Res.
Res.
Res.
Res.
Res.
Res.
Register Name
Res.
0x0D4
Res.
Offset
Res.
RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Table 19. DDRCTRL register map and reset values (continued)
0 0 0 0
0 1 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0
EMR[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0
0 0
299/3930
312
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Res.
Res.
Res.
Res.
Res.
Res.
0 0 1 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0 0 0 0 1 0 1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
T_XS_X32[6:0]
Res.
T_XS_DLL_X32[6:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
T_CKPDX[3:0]
Res.
Res.
Res.
Res.
T_CKPDE[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DDRCTRL_DRAMTMG14
Reset value
T_CKCSX[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
T_CKDPDX[3:0]
Res.
Res.
Res.
T_CKSRE[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
READ_LATENCY[5:0]
Res.
Res.
Res.
Res.
Res.
0 0 0 1 1
1 0 0 0 1 0 0
Res.
300/3930
T_CKE[4:0]
0 1 0 1
Res.
0x138
T_RP[4:0]
0 0 1 0 1
0 0 0 1 0 0
Reset value
0x124 0x134
0 0 0 0 0 0 1 1 0 0
T_RRD[3:0
]
0 0 1 0
Res.
DDRCTRL_DRAMTMG8
0 0 1 1 0 1
T_MOD[9:0]
T_CKESR[5:0]
Reset value
0x120
WR2RD[5:0]
0 0 1 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DDRCTRL_DRAMTMG7
0 0 1 0
0 0 1 0 1 0 0
0 1 0 0
0 1 0 1
Res.
Reset value
0x11C
T_CKDPDE[3:0]
Res.
Res.
Res.
Res.
DDRCTRL_DRAMTMG6
0 1 0 1
T_RC[6:0]
0 0 0 1 1 0
0 1 0 0
Res.
Reset value
0x118
T_CKSRX[3:0]
Res.
Res.
Res.
0 0 1 0 1
Res.
DDRCTRL_DRAMTMG5
0x114
T_RCD[4:0]
RD2WR[5:0]
0 0 0 1 0 0
T_CCD[3:0
]
Res.
Reset value
Res.
Res.
Res.
Res.
DDRCTRL_DRAMTMG4
0x110
0 0 0 0 0 0 0 1 0 1
RD2PRE[5:0]
T_MRD[5:0]
Res.
Reset value
T_MRW[9:0]
T_RAS_MIN[5:0]
0 0 1 1 1 1
0 0 0 1 0 0
0 0 0 1 0 1
Res.
Res.
0 0 0 0 1 1
Res.
DDRCTRL_DRAMTMG3
Res.
Res.
Reset value
0x10C
WRITE_LATENCY[5:0]
0 1 0 0 0
Res.
DDRCTRL_DRAMTMG2
0x108
0 0 1 1 0 1 1
Res.
Reset value
T_XP[4:0]
T_RAS_MAX[6:0]
Res.
Res.
Res.
Res.
0 1 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DDRCTRL_DRAMTMG1
0x104
0 0 0 1 1 1 1
T_FAW[5:0]
Res.
Reset value
WR2PRE[6:0]
Res.
DDRCTRL_DRAMTMG0
0x100
Res.
Register Name
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 19. DDRCTRL register map and reset values (continued)
T_XSR[11:0]
0 0 0 0 1 0 1 0 0 0 0 0
RM0442 Rev 7
0x190
DDRCTRL_DFITMG0
Reset value
0 0 1 1 1
RM0442 Rev 7
0 0 0 0 0 1 0
0 0 0 0 0 0
DFI_TPHY_WRLAT[5:0]
Res.
Reset value
Reset value
ZQ_RESET_BUSY
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ZQ_RESET
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0 1 0 0 0 0 0 0 0 0 0
Res.
DFI_TPHY_WRDATA[5:0]
Res.
Res.
Res.
Res.
Res.
Res.
T_ZQ_RESET_NOP[9:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ZQ_RESISTOR_SHARED
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DIS_AUTO_ZQ
DIS_SRX_ZQCL
T_ZQ_LONG_NOP[10:0]
Res.
DFI_T_RDDATA_EN[6:0]
Res.
Res.
Res.
Res.
Res.
Res.
0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EN_DFI_LP_T_STAB
0
Res.
Res.
Res.
Res.
Reset value
Res.
DDRCTRL_ZQSTAT
DFI_T_CTRL_DELAY[4:0]
0x18C
DDRCTRL_ZQCTL2
Res.
Reset value
Res.
0x188
DDRCTRL_ZQCTL1
Res.
Reset value
Res.
0x184
DDRCTRL_DRAMTMG15
DDRCTRL_ZQCTL0
Res.
0x180
Res.
0x140 0x17C
Res.
0x13C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register Name
Res.
Offset
Res.
RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Table 19. DDRCTRL register map and reset values (continued)
T_STAB_X32[7:0]
0 0 0 0 0 0 0 0
T_ZQ_SHORT_NOP[9:0]
0 0 0 1 0 0 0 0 0 0
T_ZQ_SHORT_INTERVAL_X1024[19:0]
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
0
0
0 0 0 0 1 0
301/3930
312
0x1A4
302/3930
DDRCTRL_DFIUPD1
Reset value
0 0 0 0 0 0 0 1
RM0442 Rev 7
DFI_T_CTRLUPD_INTERVAL_MAX_X1024[7:0]
DFI_T_CTRLUP_MIN[9:0]
Res.
Res.
0 0 0 0 0
Res.
0 0 0 1 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
0 0 0 0 0
DFI_LP_EN_PD
Res.
Res.
0 0 1 0 0
Res.
DFI_LP_WAKEUP_PD[3:0]
DFI_LP_EN_SR
Res.
Res.
Res.
DFI_LP_WAKEUP_SR[3:0]
DFI_LP_EN_DPD
Res.
0 0 0 0 0
Res.
Res.
Res.
Res.
0 0 1 1 1 0 0 0 0
Res.
Res.
DFI_LP_WAKEUP_DPD[3:0]
DFI_TLP_RESP[4:0]
Res.
Res.
Res.
Reset value
Res.
DFI_T_CTRLUP_MAX[9:0]
Res.
Res.
Res.
0x19C
DFI_T_CTRLUPD_INTERVAL_MIN_X1024[7:0]
Res.
0 0 0
Res.
Res.
Res.
Reset value
CTRLUPD_PRE_SRX
Reset value
Res.
DDRCTRL_DFIUPD0
Res.
0x1A0
DDRCTRL_DFILPCFG0
DIS_AUTO_CTRLUPD
0x198
DIS_AUTO_CTRLUPD_SRX
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DDRCTRL_DFITMG1
DFI_T_DRAM_CLK_ENABLE[4:0]
Res.
Res.
Res.
DFI_T_DRAM_CLK_DISABLE[4:0]
Res.
Res.
Res.
DFI_T_WRDATA_DELAY[4:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Register Name
Res.
0x194
Res.
Offset
Res.
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Table 19. DDRCTRL register map and reset values (continued)
0 0 1 0 0
0
Res.
0 0 0 0 0 0 0 0 1 1
0 0 0 0 0 0 0 1
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0 0 0 0 0 0
RM0442 Rev 7
0 0 0 0 0 0
ADDRMAP_BANK_B0[5:0]
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DFI_PHYMSTR_EN Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DFI_LP_ACK
Res.
Res.
Res.
DFI_INIT_COMPLETE
Res.
Res.
0 0
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DFI_INIT_COMPLETE_EN Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CTL_IDLE_EN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DFI_INIT_START
Res.
DFI_FREQUENCY[4:0]
Res.
Res.
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
DFI_PHYUPD_EN
Res.
1
Res.
Reset value
Res.
DDRCTRL_DFIUPD2
DDRCTRL_DFIMISC
Res.
Res.
Res.
Res.
Res.
DDRCTRL_DFISTAT
Res.
Reset value
Res.
Res.
DDRCTRL_DFIPHYMSTR
Res.
Res.
Res.
Register Name
Res.
Res.
ADDRMAP_BANK_B1[5:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADDRMAP_BANK_B2[5:0]
Res.
DDRCTRL_ADDRMAP1
Res.
Res.
0x204
Res.
Res.
0x1C8 0x200
Res.
0x1C4
Res.
Res.
0x1C0
Res.
0x1BC
Res.
0x1B4 0x1B8
Res.
0x1B0
Res.
0x1AC
Res.
0x1A8
Res.
Offset
Res.
RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Table 19. DDRCTRL register map and reset values (continued)
1
0 0
1
0 0 0 0 0 0
303/3930
312
0x218
0x21C 0x220
304/3930
DDRCTRL_ADDRMAP6
Reset value
0
Res.
RM0442 Rev 7
Res.
0 0 0 0
ADDRMAP_ROW_B12[3:0]
0 0 0 0
Res.
ADDRMAP_ROW_B0[3:0]
ADDRMAP_COL_B10[4:0]
Res.
Res.
Res.
ADDRMAP_COL_B11[4:0]
0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
ADDRMAP_ROW_B1[3:0]
ADDRMAP_COL_B6[3:0]
Res.
Res.
Res.
Res.
ADDRMAP_COL_B7[4:0]
Res.
Res.
Res.
ADDRMAP_COL_B8[4:0]
0 0 0 0
Res.
Res.
Res.
Res.
Res.
ADDRMAP_ROW_B13[3:0]
0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
0 0 0 0
Res.
0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADDRMAP_COL_B9[4:0]
0 0 0 0
Res.
Res.
Res.
Res.
Res.
ADDRMAP_ROW_B2_10[3:0]
Reset value
Res.
Res.
Res.
Res.
ADDRMAP_ROW_B14[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
0 0 0 0
Res.
0 0 0 0
Res.
Res.
Res.
Res.
Res.
ADDRMAP_ROW_B11[3:0]
Res.
0 0 0 0
Res.
Res.
Res.
Res.
Res.
ADDRMAP_ROW_B15[3:0]
Res.
Res.
Res.
0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
DDRCTRL_ADDRMAP5
Res.
DDRCTRL_ADDRMAP4
Res.
0x214
DDRCTRL_ADDRMAP3
Res.
0x210
ADDRMAP_COL_B2[3:0]
Res.
Res.
Res.
Res.
ADDRMAP_COL_B3[3:0]
Res.
Res.
Res.
Res.
ADDRMAP_COL_B4[3:0]
Res.
Res.
Res.
Res.
ADDRMAP_COL_B5[3:0]
Res.
Res.
Res.
Res.
DDRCTRL_ADDRMAP2
Res.
0x20C
LPDDR3_6GB_12GB
0x208
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register Name
Res.
Offset
Res.
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Table 19. DDRCTRL register map and reset values (continued)
0 0 0 0
0 0 0 0
0 0 0 0 0
0 0 0 0
0 0 0 0
0x248 0x24C
Res.
RM0442 Rev 7
1
Res.
Res.
Res.
Res.
Res.
RANK0_WR_ODT
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0 0 0 0 0
Res.
Res.
RD_ODT_DELAY[4:0]
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
ADDRMAP_ROW_B10[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0 0 0 0
Res.
RANK0_RD_ODT
Res.
Res.
Res.
RD_ODT_HOLD[3:0]
Res.
Res.
Res.
Res.
Res.
ADDRMAP_ROW_B6[3:0]
Res.
Res.
Res.
Res.
ADDRMAP_ROW_B7[3:0]
Res.
Res.
Res.
Res.
ADDRMAP_ROW_B8[3:0]
Res.
Res.
0 0 0 0
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0 1 0 0
Res.
Res.
Res.
Res.
Res.
0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
WR_ODT_DELAY[4:0]
Res.
0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADDRMAP_ROW_B9[3:0]
Res.
Res.
0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WR_ODT_HOLD[3:0]
Res.
Res.
Res.
Res.
0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0 1 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
DDRCTRL_ODTCFG
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
DDRCTRL_ODTMAP
Res.
Res.
DDRCTRL_ADDRMAP11
Res.
0x244
Res.
0x240
Res.
Res.
0x230 0x23C
Res.
0x22C
DDRCTRL_ADDRMAP10
Res.
0x228
ADDRMAP_ROW_B2[3:0]
Res.
Res.
Res.
Res.
ADDRMAP_ROW_B3[3:0]
Res.
Res.
Res.
Res.
ADDRMAP_ROW_B4[3:0]
Res.
Res.
Res.
Res.
ADDRMAP_ROW_B5[3:0]
Res.
Res.
Res.
Res.
DDRCTRL_ADDRMAP9
Res.
0x224
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register Name
Res.
Offset
Res.
RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Table 19. DDRCTRL register map and reset values (continued)
0 0 0 0
0 0 0 0
0 0 0 0
1
305/3930
312
0x268
306/3930
Res.
RM0442 Rev 7
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PAGECLOSE_TIMER[7:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0 0 0 0 1 1 1 1
Res.
Reset value
Res.
Res.
0 0 0 0 1 1 1 1
Res.
HPR_XACT_RUN_LENGTH[7:0]
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DDRCTRL_PERFHPR1
Res.
Res.
Res.
Res.
DDRCTRL_PERFLPR1
LPR_XACT_RUN_LENGTH[7:0]
0x264
Res.
Res.
0x260
Res.
0x25C
Res.
0x258
DDRCTRL_SCHED1
Res.
Reset value
Res.
0x254
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DDRCTRL_SCHED
FORCE_LOW_PRI_N
PREFER_WRITE
PAGECLOSE
Res.
Res.
Res.
Res.
Res.
LPR_NUM_ENTRIES[3:0]
Res.
Res.
Res.
Res.
GO2CRITICAL_HYSTERESIS[7:0]
RDWR_IDLE_GAP[6:0]
Register Name
Res.
0x250
Res.
Offset
Res.
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Table 19. DDRCTRL register map and reset values (continued)
1 0 1
0 0 0 0 0 0 0 0
Res.
HPR_MAX_STARVE[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
LPR_MAX_STARVE[15:0]
0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
0x30C
DDRCTRL_DBGCMD
Reset value
RM0442 Rev 7
0 0
DIS_DQ
DIS_HIF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
RANK0_REFRESH
DBG_HPR_Q_DEPTH[4:0]
Reset value
Res.
Res.
0 0 0 0 0
Res.
Res.
Res.
Res.
DBG_LPR_Q_DEPTH[4:0]
Res.
Res.
Res.
DBG_W_Q_DEPTH[4:0]
Res.
Res.
Reset value
ZQ_CALIB_SHOR
CTRLUPD
Res.
Res.
Res.
Res.
Res.
Res.
0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DDRCTRL_DBG0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DIS_COLLISION_PAGE_OPT
Res.
Res.
Res.
DIS_WC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
W_XACT_RUN_LENGTH[7:0]
0 0 0 0 1 1 1 1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
DBG_STALL
DBG_RD_Q_EMPTY
DBG_WR_Q_EMPTY
Res.
RD_DATA_PIPELINE_EMPTY
WR_DATA_PIPELINE_EMPTY
Res.
DDRCTRL_PERFWR1
Res.
Res.
Res.
0 0
Res.
Reset value
Res.
DDRCTRL_DBGCAM
Res.
0x308
DDRCTRL_DBG1
Res.
0x304
Res.
0x300
Res.
0x270 0x2FC
Res.
0x26C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register Name
Res.
Offset
Res.
RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Table 19. DDRCTRL register map and reset values (continued)
W_MAX_STARVE[15:0]
0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
0
0 0
0 0 0 0 0
0
307/3930
312
0x374 0x3F8
308/3930
Res.
RM0442 Rev 7
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RD_POISON_INTR_CLR
Res.
Res.
Res.
RD_POISON_INTR_EN
Res.
Res.
Res.
RD_POISON_SLVERR_EN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WR_POISON_INTR_CLR
Res.
Res.
Res.
WR_POISON_INTR_EN
Res.
Res.
Res.
WR_POISON_SLVERR_EN
Reset value
1
SW_DONE_ACK
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
WR_POISON_INTR_0
WR_POISON_INTR_1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DDRCTRL_SWCTL
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SW_DONE
0 0
Res.
0 0
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
DDRCTRL_POISONCFG
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RD_POISON_INTR_0
RD_POISON_INTR_1
Res.
Res.
1
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
DDRCTRL_POISONSTAT
Res.
DDRCTRL_SWSTAT
Res.
0x370
Res.
0x36C
Res.
Res.
0x328 0x368
Res.
0x324
Res.
0x320
Res.
0x314 0x31C
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DDRCTRL_DBGSTAT
RANK0_REFRESH_BUSY
Res.
Res.
Res.
ZQ_CALIB_SHORT_BUSY
CTRLUPD_BUSY
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Register Name
Res.
0x310
Res.
Offset
Res.
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Table 19. DDRCTRL register map and reset values (continued)
0
1
1
1
0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DDRCTRL_PCTRL_0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PORT_EN
0x490
Res.
Res.
0x40C 0x48C
Res.
0x408
DDRCTRL_PCFGW_0
Reset value
RM0442 Rev 7
Reset value
1 0 0
1 0 0
WR_PORT_PRIORITY[9:0]
Res.
Res.
WR_PORT_AGING_EN
WR_PORT_URGENT_EN
0
WR_PORT_PAGEMATCH_EN
Res.
Reset value
Res.
RD_PORT_PRIORITY[9:0]
Res.
Res.
RD_PORT_AGING_EN
RD_PORT_URGENT_EN
RD_PORT_PAGEMATCH_EN
Res.
RDWR_ORDERED_EN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
0
0
GO2CRITICAL_EN
0 0
Res.
Res.
Res.
PAGEMATCH_LIMIT
Res.
Res.
Res.
BL_EXP_MODE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DDRCTRL_PCFGR_0
Res.
DDRCTRL_PCCFG
Res.
0x404
Res.
0x400
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DDRCTRL_PSTAT
RD_PORT_BUSY_0
RD_PORT_BUSY_1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WR_PORT_BUSY_0
WR_PORT_BUSY_1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Register Name
Res.
0x3FC
Res.
Offset
Res.
RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Table 19. DDRCTRL register map and reset values (continued)
0 0
0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0
309/3930
312
0x4A4 0x4B0
310/3930
Res.
RM0442 Rev 7
Res.
Res.
1 1 1 0
Res.
WQOS_MAP_TIMEOUT1[10:0]
WQOS_MAP_LEVEL1[3:0]
Res.
Res.
Res.
Res.
WQOS_MAP_LEVEL2[3:0]
RQOS_MAP_TIMEOUTB[10:0]
Res.
Res.
Res.
Res.
Res.
1 1 1 0
Res.
Res.
Res.
Res.
Res.
Res.
0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
0 0 0 0 0 0 0 0 0 0 0
Res.
0 0
Res.
Res.
Res.
Res.
Res.
WQOS_MAP_REGION0[1:0]
RQOS_MAP_TIMEOUTR[10:0]
0 0
Res.
Res.
Res.
Res.
Res.
0 0
Res.
Res.
Res.
WQOS_MAP_REGION1[1:0]
0 0
Res.
Res.
Res.
0 0
Res.
WQOS_MAP_TIMEOUT2[10:0]
Res.
Res.
WQOS_MAP_REGION2[1:0]
Res.
Res.
Res.
1 0
Res.
Res.
Res.
Reset value
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
DDRCTRL_PCFGWQOS1_0
Res.
DDRCTRL_PCFGWQOS0_0
Res.
DDRCTRL_PCFGQOS1_0
Res.
0x498
Res.
0x4A0
RQOS_MAP_LEVEL1[3:0]
Res.
Res.
Res.
Res.
RQOS_MAP_LEVEL2[3:0]
Res.
Res.
Res.
Res.
RQOS_MAP_REGION0[1:0]
Res.
Res.
RQOS_MAP_REGION1[1:0]
Res.
Res.
RQOS_MAP_REGION2[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
DDRCTRL_PCFGQOS0_0
Res.
0x494
Res.
0x49C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register Name
Res.
Offset
Res.
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Table 19. DDRCTRL register map and reset values (continued)
0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0x548
DDRCTRL_PCFGQOS1_1
Reset value
0 0 0 0 0 0 0 0 0 0 0
RM0442 Rev 7
RQOS_MAP_TIMEOUTB[10:0]
0 0
1 1 1 0
RQOS_MAP_LEVEL1[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PORT_EN
1 0 0
Res.
Res.
Res.
WR_PORT_PAGEMATCH_EN
WR_PORT_PRIORITY[9:0]
Res.
Res.
WR_PORT_AGING_EN
WR_PORT_URGENT_EN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1 0 0
RQOS_MAP_LEVEL2[3:0]
Res.
Res.
Res.
Res.
RQOS_MAP_REGION0[1:0]
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
0 0
Res.
Res.
RQOS_MAP_REGION1[1:0]
Res.
Reset value
Res.
1 0
Res.
Res.
RQOS_MAP_REGION2[1:0]
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Reset value
RQOS_MAP_TIMEOUTR[10:0]
Res.
Res.
DDRCTRL_PCFGQOS0_1
Res.
0x544
DDRCTRL_PCTRL_1
Res.
0x540
Res.
Res.
0x4BC 0x53C
DDRCTRL_PCFGW_1
Res.
0x4B8
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DDRCTRL_PCFGR_1
RD_PORT_PRIORITY[9:0]
Res.
Res.
RD_PORT_AGING_EN
RD_PORT_URGENT_EN
RD_PORT_PAGEMATCH_EN
Res.
RDWR_ORDERED_EN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Register Name
Res.
0x4B4
Res.
Offset
Res.
RM0442
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
Table 19. DDRCTRL register map and reset values (continued)
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
Reset value
0
0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
311/3930
312
DDR3/LPDDR2/LPDDR3 controller (DDRCTRL)
RM0442
Reset value
RM0442 Rev 7
WQOS_MAP_LEVEL1[3:0]
Res.
Res.
Res.
Res.
0 0 0 0 0 0 0 0 0 0 0
Refer to Section 2.5 on page 153 for the register boundary addresses.
312/3930
0 0 0 0
WQOS_MAP_TIMEOUT1[10:0]
Res.
Res.
Res.
1 1 1 0
Res.
0 0
0 0 0 0 0 0 0 0 0 0 0
WQOS_MAP_LEVEL2[3:0]
Res.
Res.
Res.
Res.
WQOS_MAP_REGION0[1:0]
Res.
Res.
Res.
Res.
WQOS_MAP_REGION2[1:0]
WQOS_MAP_REGION1[1:0]
0 0
WQOS_MAP_TIMEOUT2[10:0]
Res.
Res.
Res.
Res.
DDRCTRL_PCFGWQOS1_1
Res.
0x550
0 0
Res.
Reset value
Res.
Res.
Res.
Res.
DDRCTRL_PCFGWQOS0_1
Res.
0x54C
Register Name
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 19. DDRCTRL register map and reset values (continued)
TrustZone® address space controller for DDR (TZC)
RM0442
6
TrustZone® address space controller for DDR (TZC)
6.1
Introduction
The TZC filters read/write accesses to the DDR controller according to TrustZone access
rights, and according to Non-secure master Address ID (NSAID) on up to 9 programmable
regions.
Note:
For more information, please refer to Arm TZC-400 TRM.
6.2
TZC features
Note:
•
32-bit APB4 Interface
•
TZC configuration is supported by secure master only
•
2 filter units working concurrently
•
9 regions:
–
Region 0 is always enabled and covers the whole address range
–
Regions 1 to 8 have programmable base/end address and can be assigned one or
both filters.
•
Secure and non-secure access permissions are programmed per region
•
Non-secure accesses are filtered according to NSAID
•
Regions controlled by the same filter must not overlap
•
Failed permission checks are signaled with an AXI Bus error and/or interrupt
•
Dual read access path with:
–
Normal path supporting 256 outstanding transactions
–
Fast path with limited outstanding capabilities using FPID signals
•
Gate keeper logic to enable and disable each filter
•
Speculative access
Fast path and FPID signals are not used in STM32MP153x. Configured acceptance on
FPID is set to minimum (8).
RM0442 Rev 7
313/3930
341
TrustZone® address space controller for DDR (TZC)
6.3
RM0442
TZC block diagram
The TZC block diagram is shown in Figure 8: TZC block diagram.
Figure 8. TZC block diagram
TZC
control
tzint
registers
APB
Port0
(in)
AXI
Filter unit 0
AXI
Port0
(out)
Port1
(in)
AXI
Filter unit 1
AXI
Port1
(out)
MSv45031V1
314/3930
RM0442 Rev 7
TrustZone® address space controller for DDR (TZC)
RM0442
6.4
TZC functional description
The TZC enforces the access permissions of several regions:
•
region 0: always enabled and covers the whole 32-bit address space.
•
regions 1 to 8: are fully programmable.
Access permissions are checked against transaction security and the transaction source:
•
Transaction security is identified by AXI TrustZone protection signals: awprot[1] and
arprot[1].
•
The transaction source is identified by the Master NSAID. In the case of a permission
fail, the fail ID is reported by the AXI ID on the AXI port. The NSAID and AXI ID are
defined according to Table 26: NSAID and AXI _ID mapping.
A region must be granted secure access if required, regardless of the settings for
non-secure reads and non-secure writes. For example, when permissions are set so that a
non-secure read or non-secure write access is permitted, this does not mean that the
corresponding secure read or secure write access is also automatically granted.
Table 20. NSAID and AXI _ID mapping
Master
NSAID[3:0]
ID_WIDTH
AXI_ID[10:0]
CA7 (CPU0 and 1)
0b0000
AR:6/AW:5
11'b10XXXXXX000
CM4
0b0001
0
11'b00000000001
LTDC
0b0011
4
11'b0100XXXX101
MDMA
0b0101
1
11'b0000000X000
DMA1
0b0110
0
11'b00000000001
DMA2
0b0110
0
11'b00000000001
USBH (EHCI)
0b0111
0
11'b01000000000
USBH (OHCI)
0b0111
0
11'b01000000001
OTG
0b1000
0
11'b00000000001
SDMMC1
0b1001
0
11'b01000000011
SDMMC2
0b1001
0
11'b01000000100
SDMMC3
0b1001
0
11'b00000000001
ETH
0b1010
4
11'b0100XXXX010
DAP
0b1111
0
11'b00000000010
RM0442 Rev 7
315/3930
341
TrustZone® address space controller for DDR (TZC)
6.5
RM0442
TZC application programming examples
A simple application example is shown Figure 9: TZC example 1:
Figure 9. TZC example 1
Trustzone r/w secure
non- secure and access by all masters
region1
region0
Region0: - Always enabled
- covers the whole address range
MSv45033V1
In this example the secure world has access to whole DDR range, and all non-secure
masters have permission to access address ≥ base1.
It is programmed with:
•
region 0
–
always enabled by default
–
covers the full address range by default
–
set region0 secure r/w access permissions
–
set region0 NSAID r/w access permission
–
enable both filters on region0
REGION0_ATTRIBUTE.s_wr_en = 1
REGION0_ATTRIBUTE.s_rd_en = 1
REGION0_ID_ACCESS.nsaid_we_en = 0b00000000000
REGION0_ID_ACCESS.nsaid_re_en = 0b00000000000
REGION0_ATTRIBUTE.filter_en = 0b11
The secure world then defines the other regions (1 up to 8) and opens access to all nonsecure NSAIDs.
•
region1
–
define region1
–
region1 accessible by secure r/w
–
set region1 NSAID r/w permission for all NSAID
–
enable both filters on region1
TZC.REGION_BASE_LOW1.base_address_low = ‘base1
REGION1_TOP_LOW.top_address_low = ‘base1 + ‘size1
REGION1_ATTRIBUTE.s_wr_en = 1
REGION1_ATTRIBUTE.s_rd_en = 1
REGION1_ID_ACCESS.nsaid_we_en = 0xFFFF
REGION1_ID_ACCESS.nsaid_re_en = 0xFFFF
REGION1_ATTRIBUTE.filter_en = 0b11
316/3930
RM0442 Rev 7
TrustZone® address space controller for DDR (TZC)
RM0442
Another application example for the TZC is shown Figure 10: TZC example 2:
Figure 10. TZC example 2
Trustzone r/w secure
non- secure
access by NSAID
0,3,4,5,7,8,9,10,15
non- secure
access by all masters
region1
region2
non- secure
access by NSAID
1,6
region3
region0
Region0: - Always enabled
- covers the whole address range
MSv45032V1
In this example the secure world only has access to address ≤ base1 and non-secure
masters have selective permissions to region1 and 3; region2 is shared by all non-secure
masters.
It is programmed with:
•
region 0
–
always enabled by default
–
covers the full address range by default
–
set region0 secure r/w access permissions
–
set region0 NSAID r/w access permission
–
enable both filters on region0
REGION0_ATTRIBUTE.s_wr_en = 1
REGION0_ATTRIBUTE.s_rd_en = 1
REGION0_ID_ACCESS.nsaid_we_en = 0x0000
REGION0_ID_ACCESS.nsaid_re_en = 0x0000
REGION0_ATTRIBUTE.filter_en = 0b11
The secure world then defines several regions (1 to 3) and opens access to the non-secure
NSAID.
•
region1
–
define region1
–
region1 non accessible by secure r/w
–
set region1 NSAID r/w permission for: 0,3,4,5,7,8,9,10,15
–
enable both filters on region1
TZC.REGION_BASE_LOW1.base_address_low = ‘base1
REGION1_TOP_LOW.top_address_low = ‘base1 + ‘size1
REGION1_ATTRIBUTE.s_wr_en = 0
REGION1_ATTRIBUTE.s_rd_en = 0
REGION1_ID_ACCESS.nsaid_we_en = 0x87B9
RM0442 Rev 7
317/3930
341
TrustZone® address space controller for DDR (TZC)
RM0442
REGION1_ID_ACCESS.nsaid_re_en = 0x87B9
REGION1_ATTRIBUTE.filter_en = 0b11
•
region2
–
define region2
–
region2 non accessible by secure r/w
–
set region2 NSAID r/w permission for: 0,1,3,4,5,6,7,8,9,10,15
–
enable both filters on region2
REGION2_BASE_LOW.base_address_low = ‘base2
REGION2_TOP_LOW.top_address_low = ‘base2 + ‘size2
REGION2_ATTRIBUTE.s_wr_en = 0
REGION2_ATTRIBUTE.s_rd_en = 0
REGION2_ID_ACCESS.nsaid_we_en = 0x87FB
REGION2_ID_ACCESS.nsaid_re_en = 0x87FB
REGION2_ATTRIBUTE.filter_en = 0b11
•
region3
–
define region3
–
region3 non accessible by secure r/w
–
set region3 NSAID r/w permission for: 1,6
–
enable both filters on region3
REGION3_BASE_LOW.base_address_low = ‘base3
REGION3_TOP_LOW.top_address_low = ‘base3 + ‘size3
REGION3_ATTRIBUTE.s_wr_en = 0
REGION3_ATTRIBUTE.s_rd_en = 0
REGION3_ID_ACCESS.nsaid_we_en = 0x0042
REGION3_ID_ACCESS.nsaid_re_en = 0x0042
REGION3_ATTRIBUTE.filter_en = 0b11
Note:
All shared regions need to be distinct because regions must not overlap.
A third application example for the TZC is shown Figure 11: TZC example 3: This example
uses region0 as a blanket and secure or non-secure regions are set as holes. This
programming model is more convenient for trapping programming errors.
Figure 11. TZC example 3
No access
Secure R/W only
NonSecure R/W
(any master)
NonSecure R/W
(NSAID 1,6)
region1
region2
region3
region0
Region0: - Always enabled
- Non secure
- Covers the whole address range
MSv45034V1
In this example the secure world only has access to address ≤ base1 and non-secure
masters have selective permissions to region2 and 3.
318/3930
RM0442 Rev 7
TrustZone® address space controller for DDR (TZC)
RM0442
It is programmed with:
•
region 0
–
always enabled by default
–
covers the full address range by default
–
set region0 without secure access permissions (default)
–
set region0 without NSAID r/w access permission (default)
–
enable both filters on region0
REGION0_ATTRIBUTE.s_wr_en = 0 (default)
REGION0_ATTRIBUTE.s_rd_en = 0 (default)
REGION0_ID_ACCESS.nsaid_we_en = 0x0000 (default)
REGION0_ID_ACCESS.nsaid_re_en = 0x0000 (default)
REGION0_ATTRIBUTE.filter_en = 0b11
The secure world then defines several regions (1 to 3) and opens holes for secure and nonsecure access
•
region1
–
define region1
–
region1 accessible by secure r/w
–
set region1 no NSAID r/w permission
–
enable both filters on region1
TZC.REGION_BASE_LOW1.base_address_low = ‘base1
REGION1_TOP_LOW.top_address_low = ‘base1 + ‘size1
REGION1_ATTRIBUTE.s_wr_en = 1
REGION1_ATTRIBUTE.s_rd_en = 1
REGION1_ID_ACCESS.nsaid_we_en = 0x0000
REGION1_ID_ACCESS.nsaid_re_en = 0x0000
REGION1_ATTRIBUTE.filter_en = 0b11
•
region2
–
define region2
–
region2 non accessible by secure r/w
–
set region2 NSAID r/w permission for all NSAID
–
enable both filters on region2
REGION2_BASE_LOW.base_address_low = ‘base2
REGION2_TOP_LOW.top_address_low = ‘base2 + ‘size2
REGION2_ATTRIBUTE.s_wr_en = 0
REGION2_ATTRIBUTE.s_rd_en = 0
REGION2_ID_ACCESS.nsaid_we_en = 0xFFFF
REGION2_ID_ACCESS.nsaid_re_en = 0xFFFF
REGION2_ATTRIBUTE.filter_en = 0b11
•
region3
–
define region3
–
region3 non accessible by secure r/w
–
set region3 NSAID r/w permission for NSAID 1,6
–
enable both filters on region3
REGION3_BASE_LOW.base_address_low = ‘base3
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TrustZone® address space controller for DDR (TZC)
REGION3_TOP_LOW.top_address_low = ‘base3 + ‘size3
REGION3_ATTRIBUTE.s_wr_en = 0
REGION3_ATTRIBUTE.s_rd_en = 0
REGION3_ID_ACCESS.nsaid_we_en = 0x0042
REGION3_ID_ACCESS.nsaid_re_en = 0x0042
REGION3_ATTRIBUTE.filter_en = 0b11
6.5.1
DMA requests
Note:
TZC does not support DMA interface.
6.5.2
Interrupts
Note:
TZC is asserting interrupt: tzcint when some security checks failed.
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RM0442
TrustZone® address space controller for DDR (TZC)
RM0442
6.6
TZC registers
TZC registers are accessed only by words (32-bit).
6.6.1
TZC configuration register (TZC_BUILD_CONFIG)
Address offset: 0x000
Reset value: 0x0100 1F08
Provides information about TZC configuration.
31
30
29
28
27
26
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
Res.
Res.
25
24
NO_OF_FILTER
S[1:0]
r
r
9
8
ADDRESS_WIDTH[5:0]
r
r
r
r
r
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
4
3
2
1
0
7
6
5
Res.
Res.
Res.
r
NO_OF_REGIONS[4:0]
r
r
r
r
r
Bits 31:26 Reserved, must be kept at reset value.
Bits 25:24 NO_OF_FILTERS[1:0]: Number of filters
0x1: 2 filters
Others: Reserved
Bits 23:14 Reserved, must be kept at reset value.
Bits 13:8 ADDRESS_WIDTH[5:0]: Address width
0x1F: 32-bit address width
Others: Reserved
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 NO_OF_REGIONS[4:0]: Number fo regions
0x8: 9 regions
Others: Reserved
6.6.2
TZC action register (TZC_ACTION)
Address offset: 0x004
Reset value: 0x0000 0000
Controls interrupt and bus error response behavior when regions permission failures occur.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
REACTION_VAL
UE[1:0]
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TrustZone® address space controller for DDR (TZC)
RM0442
Bits 31:2 Reserved, must be kept at reset value.
Bits 1:0 REACTION_VALUE[1:0]: Permission failure reaction
Controls how TZC signals region permission failure.
0: set tzcint low and issue OKAY on the bus
1: set tzcint low and issue DECERR on the bus
2: set tzcint high and issue OKAY on the bus
3: set tzcint high and issue DECERR on the bus
6.6.3
TZC gate keeper register (TZC_GATE_KEEPER)
Address offset: 0x008
Reset value: 0x0000 0000
Provides control and status for the gate keeper in the implemented filter units.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
17
OPENSTAT[1:0]
r
r
1
0
OPENREQ[1:0]
rw
Bits 31:18 Reserved, must be kept at reset value.
Bits 17:16 OPENSTAT[1:0]: Gate keeper status for each filter
Bit 17 is for filter1, bit 16 is for filter0
0: filter is opened
1: filter is closed
Bits 15:2 Reserved, must be kept at reset value.
Bits 1:0 OPENREQ[1:0]: Gate keeper open request
Bit 1 is for filter1, bit 0 is for filter0.
0: request filter to open
1: request filter to close
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TrustZone® address space controller for DDR (TZC)
RM0442
6.6.4
TZC speculation control register (TZC_SPECULATION_CTRL)
Address offset: 0x00C
Reset value: 0x0000 0000
Controls read and write access speculation.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WRITE READ
SPEC_ SPEC_
DISA
DISA
BLE
BLE
rw
rw
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 WRITESPEC_DISABLE: Write access speculation disable
0: write access speculation enabled
1: write access speculation disabled
Bit 0 READSPEC_DISABLE: Read access speculation disable
0: read access speculation enabled
1: read access speculation disabled
6.6.5
TZC interrupt status register (TZC_INT_STATUS)
Address offset: 0x010
Reset value: 0x0000 0000
Contains the status of the interrupt signal, TZCINT, that reports access security violations or
region overlap errors.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OVERRUN[1:0]
r
r
17
16
OVERLAP[1:0]
r
r
1
0
STATUS[1:0]
r
r
Bits 31:18 Reserved, must be kept at reset value.
Bits 17:16 OVERLAP[1:0]: Overlap violation for each filter
Bit 17 is for filter 1, bit 16 is for filter 0.
0: interrupt is not asserted
1: interrupt asserted and waiting to be cleared
Bits 15:10 Reserved, must be kept at reset value.
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RM0442
Bits 9:8 OVERRUN[1:0]: Permission failure overrun
Two or more regions permission failures for each filter. Bit 9 is for filter 1, bit 8 is for filter 0.
0: interrupt is not asserted
1: interrupt asserted and waiting to be cleared
Bits 7:2 Reserved, must be kept at reset value.
Bits 1:0 STATUS[1:0]: Interrupt status for each filter
Bit 1 is for filter 1, bit 0 is for filter0.
0: interrupt is not asserted
1: interrupt asserted and waiting to be cleared
6.6.6
TZC interrupt clear register (TZC_INT_CLEAR)
Address offset: 0x014
Reset value: 0x0000 0000
Interrupt clear for each filter.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CLEAR[1:0]
w
w
Bits 31:2 Reserved, must be kept at reset value.
Bits 1:0 CLEAR[1:0]: Filter interrupt clear
Write “1” to clear interrupt for each filter.
bit 1: for filter 1
bit 0: for filter 0
6.6.7
TZC fail address low register x (TZC_FAIL_ADDRESS_LOWx)
Address offset: 0x020 + 0x010 * x, (x = 0 to 1)
Reset value: 0x0000 0000
Address low bits of the first failed access in the associated filter (0 to 1).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADDR_STATUS_LOW[31:16]
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
ADDR_STATUS_LOW[15:0]
r
r
r
r
r
r
r
r
r
r
Bits 31:0 ADDR_STATUS_LOW[31:0]: Fail address low bits
Low 32 address bits of the first failed access permission check in the associated filter (0 to 1).
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TrustZone® address space controller for DDR (TZC)
RM0442
6.6.8
TZC fail address high register x (TZC_FAIL_ADDRESS_HIGHx)
Address offset: 0x024 + 0x010 * x, (x = 0 to 1)
Reset value: 0x0000 0000
Address high bit of the first failed access in the associated filter (0 to 1).
Note:
Not used with 32bit address.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Bits 31:0 Reserved, must be kept at reset value.
6.6.9
TZC fail control register x (TZC_FAIL_CONTROLx)
Address offset: 0x028 + 0x010 * x, (x = 0 to 1)
Reset value: 0x0000 0000
Status information about the first access that failed a region permission check in the
associated filter (0 to 1).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
NON_
SE
CURE
PRIVI
LEGE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DIREC
TION
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
r
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 DIRECTION: Access failure direction
0: Read access failure
1: Write access failure
Bits 23:22 Reserved, must be kept at reset value.
Bit 21 NON_SECURE: Non-secure access failure
0: Secure access failure
1: Non-secure access failure
Bit 20 PRIVILEGE: Privilege access failure
0: Unprivileged access failure
1: Privileged access failure
Bits 19:0 Reserved, must be kept at reset value.
RM0442 Rev 7
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TrustZone® address space controller for DDR (TZC)
6.6.10
RM0442
TZC fail ID register x (TZC_FAIL_IDx)
Address offset: 0x02C + 0x010 * x, (x = 0 to 1)
Reset value: 0x0000 0000
Contains the master AXI ARID or AWID of the first access that failed a region permission
check in the associated filter unit. This occurs even if the ACTION register is set to not drive
the interrupt signal.
Note:
AXI ID mapping is described in Table 26: NSAID and AXI _ID mapping.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
r
r
r
r
r
r
r
r
r
r
r
21
20
19
18
17
16
ID[10:0]
Bits 31:11 Reserved, must be kept at reset value.
Bits 10:0 ID[10:0]: AXI fail ID
Return the AXI ID of the first fail.
6.6.11
TZC region 0 base address low register
(TZC_REGION_BASE_LOW0)
Address offset: 0x100
Reset value: 0x0000 0000
Base address low for region 0.
31
30
29
28
27
26
25
24
23
22
BASE_ADDRESS_LOW[19:4]
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BASE_ADDRESS_LOW[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
r
r
r
r
Bits 31:12 BASE_ADDRESS_LOW[19:0]: base address bits[31:12] for region 0
0x00000: fixed value for region 0
Others: Reserved
Bits 11:0 Reserved, must be kept at reset value.
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TrustZone® address space controller for DDR (TZC)
6.6.12
TZC region x base address high register (TZC_REGION_BASE_HIGHx)
Address offset: 0x104 + 0x20 * x, (x = 0 to 8)
Reset value: 0x0000 0000
Base address high are not used with 32-bit address.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
21
20
19
18
17
16
Bits 31:0 Reserved, must be kept at reset value.
6.6.13
TZC region 0 top address low register
(TZC_REGION_TOP_LOW0)
Address offset: 0x108
Reset value: 0xFFFF FFFF
Top address bits [31:12] for region 0.
31
30
29
28
27
26
25
24
23
22
TOP_ADDRESS_LOW[19:4]
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOP_ADDRESS_LOW[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
r
r
r
r
Bits 31:12 TOP_ADDRESS_LOW[19:0]: Top address bits [31:12] of region 0
0xFFFFF: fixed value for region 0
Others: Reserved
Bits 11:0 Reserved, must be kept at reset value.
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TrustZone® address space controller for DDR (TZC)
6.6.14
RM0442
TZC region x top address high register (TZC_REGION_TOP_HIGHx)
Address offset: 0x10C + 0x20 * x, (x= 0 to 8)
Reset value: 0x0000 0000
Top address high of region are not used with 32-bit address.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Bits 31:0 Reserved, must be kept at reset value.
6.6.15
TZC region 0 attribute register (TZC_REGION_ATTRIBUTE0)
Address offset: 0x110
Reset value: 0x0000 0003
Region 0 attributes.
31
30
S_WR_ S_RD_
EN
EN
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
0
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FILTER_EN[1:0]
r
Bit 31 S_WR_EN: Secure global write enable
0: secure write to the region are not allowed
1: permit secure write into the region
Bit 30 S_RD_EN: Secure global read enable
0: secure read to the region are not allowed
1: permit secure read into the region
Bits 29:2 Reserved, must be kept at reset value.
Bits 1:0 FILTER_EN[1:0]: Region enable for each filter
Bit 1 is for filter 1
Bit 0 is for filter 0
0: Reserved
1: enable filter for the region
Note:
328/3930
For region 0 the FILTER_EN bits are ‘1” and cannot be modified.
RM0442 Rev 7
r
TrustZone® address space controller for DDR (TZC)
RM0442
6.6.16
TZC region x ID access register (TZC_REGION_ID_ACCESSx)
Address offset: 0x114 + 0x20 * x, (x = 0 to 8)
Reset value: 0x0000 0000
Region non-secure access based on NSAID.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
NSAID_WR_EN[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
NSAID_RD_EN[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 NSAID_WR_EN[15:0]: Region write enable for each NSAID
Bit 16 is associated to NSAID = 0 .. bit 31 is associated to NSAID = 15
0: forbids write non-secure to the region for this NSAID
1: permits write non-secure to the region for this NSAID
Bits 15:0 NSAID_RD_EN[15:0]: Region read enable for each NSAID
Bit 0 is associated to NSAID = 0 ... bit 15 is associated to NSAID = 15.
0: forbids read non-secure to the region for this NSAID
1: permits read non-secure to the region for this NSAID
6.6.17
TZC region x base address low register
(TZC_REGION_BASE_LOWx)
Address offset: 0x120 + 0x20 * (x - 1), (x = 1 to 8)
Reset value: 0x0000 0000
Base address low for regions 1 to 8.
31
30
29
28
27
26
25
24
23
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
BASE_ADDRESS_LOW[3:0]
Res.
Res.
Res.
Res.
Res.
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
rw
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BASE_ADDRESS_LOW[19:4]
rw
rw
rw
rw
Bits 31:12 BASE_ADDRESS_LOW[19:0]: Base address bits[31:12] for region x
Bits 11:0 Reserved, must be kept at reset value.
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TrustZone® address space controller for DDR (TZC)
6.6.18
RM0442
TZC region x top address low register
(TZC_REGION_TOP_LOWx)
Address offset: 0x128 + 0x20 * (x - 1), (x = 1 to 8)
Reset value: 0x0000 0FFF
Top address bits [31:12] for region x.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TOP_ADDRESS_LOW[19:4]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOP_ADDRESS_LOW[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
Bits 31:12 TOP_ADDRESS_LOW[19:0]: Top address bits [31:12] of region x
Bits 11:0 Reserved, must be kept at reset value.
6.6.19
TZC region x attribute register (TZC_REGION_ATTRIBUTEx)
Address offset: 0x130 + 0x20 * (x-1), (x = 1 to 8)
Reset value: 0x0000 0000
Region x attributes.
31
30
S_WR_ S_RD_
EN
EN
rw
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
0
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FILTER_EN[1:0]
rw
Bit 31 S_WR_EN: Secure global write enable
0: secure write to the region are not allowed
1: permit secure write into the region
Bit 30 S_RD_EN: Secure global read enable
0: secure read to the region are not allowed
1: permit secure read into the region
Bits 29:2 Reserved, must be kept at reset value.
Bits 1:0 FILTER_EN[1:0]: Region enable for each filter
Bit 1 is for filter 1
Bit 0: is for filter 0
0: disable filter for the region
1: enable filter for the region
330/3930
RM0442 Rev 7
rw
TrustZone® address space controller for DDR (TZC)
RM0442
6.6.20
TZC peripheral ID 4 register (TZC_PID4)
Address offset: 0xFD0
Reset value: 0x0000 0004
Peripheral ID 4.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PER_ID_4[7:0]
r
r
r
r
r
r
r
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PER_ID_4[7:0]: Peripheral ID 4
6.6.21
TZC peripheral ID 5 register (TZC_PID5)
Address offset: 0xFD4
Reset value: 0x0000 0000
Peripheral ID 5.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
r
r
r
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PER_ID_5[7:0]
r
r
r
r
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PER_ID_5[7:0]: Peripheral ID 5
6.6.22
TZC peripheral ID 6 register (TZC_PID6)
Address offset: 0xFD8
Reset value: 0x0000 0000
Peripheral ID 6.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
r
r
r
r
r
r
PER_ID_6[7:0]
RM0442 Rev 7
r
r
331/3930
341
TrustZone® address space controller for DDR (TZC)
RM0442
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PER_ID_6[7:0]: Peripheral ID 6
6.6.23
TZC peripheral ID 7 register (TZC_PID7)
Address offset: 0xFDC
Reset value: 0x0000 0000
Peripheral ID 7.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PER_ID_7[7:0]
r
r
r
r
r
r
r
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PER_ID_7[7:0]: Peripheral ID 7
6.6.24
TZC peripheral ID 0 register (TZC_PID0)
Address offset: 0xFE0
Reset value: 0x0000 0060
Peripheral ID 0.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
r
r
r
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PER_ID_0[7:0]
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PER_ID_0[7:0]: Peripheral ID 0
332/3930
RM0442 Rev 7
r
r
r
r
TrustZone® address space controller for DDR (TZC)
RM0442
6.6.25
TZC peripheral ID 1 register (TZC_PID1)
Address offset: 0xFE4
Reset value: 0x0000 00B4
Peripheral ID 1.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PER_ID_1[7:0]
r
r
r
r
r
r
r
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PER_ID_1[7:0]: Peripheral ID 1
6.6.26
TZC peripheral ID 2 register (TZC_PID2)
Address offset: 0xFE8
Reset value: 0x0000 002B
Peripheral ID 2.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
r
r
r
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PER_ID_2[7:0]
r
r
r
r
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PER_ID_2[7:0]: Peripheral ID 2
6.6.27
TZC peripheral ID 3 register (TZC_PID3)
Address offset: 0xFEC
Reset value: 0x0000 0000
Peripheral ID 3.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
r
r
r
r
r
r
PER_ID_3[7:0]
RM0442 Rev 7
r
r
333/3930
341
TrustZone® address space controller for DDR (TZC)
RM0442
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PER_ID_3[7:0]: Peripheral ID 3
6.6.28
TZC component ID 0 register (TZC_CID0)
Address offset: 0xFF0
Reset value: 0x0000 000D
Component ID 0.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
r
r
r
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
COMP_ID_0[7:0]
r
r
r
r
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 COMP_ID_0[7:0]: Component ID 0
6.6.29
TZC component ID 1 register (TZC_CID1)
Address offset: 0xFF4
Reset value: 0x0000 00F0
Component ID 1.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
r
r
r
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
COMP_ID_1[7:0]
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 COMP_ID_1[7:0]: Component ID 0
334/3930
RM0442 Rev 7
r
r
r
r
TrustZone® address space controller for DDR (TZC)
RM0442
6.6.30
TZC component ID 2 register (TZC_CID2)
Address offset: 0xFF8
Reset value: 0x0000 0005
Component ID 2.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
r
r
r
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
COMP_ID_2[7:0]
r
r
r
r
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 COMP_ID_2[7:0]: Component ID 2
6.6.31
TZC component ID 3 register (TZC_CID3)
Address offset: 0xFFC
Reset value: 0x0000 00B1
Component ID 3.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
r
r
r
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
COMP_ID_3[7:0]
r
r
r
r
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 COMP_ID_3[7:0]: Component ID 3
RM0442 Rev 7
335/3930
341
0x014
0x018 0x01C
0x020
0x024
336/3930
TZC_INT_CLEAR
Reset value
Reset value
TZC_FAIL_
ADDRESS_HIGH0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset value
0
0
RM0442 Rev 7
0
0
0
0
0
0
0
0
0
0
0
Reserved
Res.
TZC_FAIL_
ADDRESS_LOW0
ADDR_STATUS_LOW[31:0]
0
0
0
Res.
Reset value
Reset value
OPENREQ[1:0]
Reset value
0
0
READSPEC_DISABLE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
REACTION_VALUE[1:0]
Res.
Res.
Res.
0
WRITESPEC_DISABLE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
STATUS[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
0
CLEAR[1:0]
Res.
Res.
Res.
Res.
Res.
1
Res.
1
Res.
Res.
1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OPENSTAT[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
Res.
Res.
OVERRUN[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OVERLAP[1:0]
0
Res.
Res.
Res.
Res.
Res.
0
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
TZC_INT_STATUS
Res.
TZC_
SPECULATION_
CTRL
Res.
0x00C
Res.
TZC_GATE_
KEEPER
Res.
0x008
Res.
TZC_ACTION
Res.
0x004
Res.
0x010
NO_OF_REGIONS[4:0]
Res.
Res.
Res.
ADDRESS_WIDTH[5:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
NO_OF_FILTERS[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
TZC_BUILD_
CONFIG
Res.
0x000
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register name
Offset
reset value
Res.
6.6.32
Res.
TrustZone® address space controller for DDR (TZC)
RM0442
TZC register map
Table 21. TZC register map and reset values
Register size
0
0
0
0
0
0
0
0
0
0
FAIL_ADDRESS_HIGH0[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TrustZone® address space controller for DDR (TZC)
RM0442
Table 21. TZC register map and reset values (continued)
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
BASE_ADDRESS_LOW[19:0]
Res.
Res.
Res.
0x10C
TZC_REGION_
TOP_HIGH0
0
0
0
0
0
0
0
0
0
0
0
0
0
REGION_BASE_HIGH0[31:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x110
TZC_TREGION_
ATTRIBUTE0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
Res.
1
Res.
1
Res.
1
Res.
1
Res.
1
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
S_RD_EN
0
S_WR_EN
Reset value
0
Res.
0x108
TZC_REGION_
TOP_LOW0
Reset value
0
Res.
0x104
TZC_REGION_
BASE_HIGH0
0
Res.
TZC_REGION_
BASE_LOW0
0
ID[10:0]
Res.
0x100
Res.
Res.
Res.
Reserved
Res.
Res.
Res.
Reset value
0x030 0x0FC
Res.
Res.
Res.
PRIVILEGE
Res.
0
Res.
Res.
NON_SECURE
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TZC_FAIL_ID0
Res.
0x02C
0
Res.
Reset value
DIRECTION
Res.
Res.
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
TZC_FAIL_
CONTROL0
Register size
Res.
0x028
Register name
reset value
Res.
Offset
Reset value
0
0
0
0x114
TZC_REGION_ID_
ACCESS0
1
1
1
1
1
1
1
1
1
1
1
1
NSAID_WR_EN[15:0]
0
0
0
0
0
0
0
0
0
0
0
NSAID_RD_EN[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
BASE_ADDRESS_LOW[19:0]
Res.
Res.
Res.
0x12C
TZC_REGION_
TOP_HIGH1
0
0
0
0
0
0
0
0
0
0
0
0
REGION_BASE_HIGH1[31:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TZC_REGION_
ATTRIBUTE1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
0
0
Res.
0
Res.
0
0
Res.
0
Res.
0
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
S_RD_EN
0
S_WR_EN
Reset value
0
Res.
0x128
TZC_REGION_
TOP_LOW1
Reset value
1
Res.
0x124
TZC_REGION_
BASE_HIGH1
1
Res.
TZC_REGION_
BASE_LOW1
FILTER_EN[1:0]
REGION_TOP_HIGH0[31:0]
Reserved
0x120
Reset value
0
0
TOP_ADDRESS_LOW[19:0]
0
0
REGION_TOP_HIGH1[31:0]
FILTER_EN[1:0]
Reset value
0x130
1
Res.
Reset value
0x118 0x11C
1
Res.
Reset value
TOP_ADDRESS_LOW[19:0]
0
RM0442 Rev 7
0
337/3930
341
TrustZone® address space controller for DDR (TZC)
RM0442
Table 21. TZC register map and reset values (continued)
Register size
TZC_REGION_ID_
ACCESS1
0
0
0
0
0
0
0
0
0
0
NSAID_RD_EN[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
0
Res.
BASE_ADDRESS_LOW[19:0]
Res.
Res.
Res.
0x14C
TZC_REGION_
TOP_HIGH2
0
0
0
0
0
0
0
0
0
0
0
0
REGION_BASE_HIGH2[31:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x150
TZC_REGION_
ATTRIBUTE2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
S_RD_EN
0
S_WR_EN
Reset value
0
0
Res.
0x148
TZC_REGION_
TOP_LOW2
Reset value
0
Res.
0x144
TZC_REGION_
BASE_HIGH2
0
Res.
TZC_REGION_
BASE_LOW2
0
Res.
0x140
0
Res.
Reserved
0
Res.
0x138 0x13C
NSAID_WR_EN[15:0]
0
Res.
Reset value
Res.
0x134
Register name
reset value
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Offset
Reset value
0
0
0x154
TZC_REGION_ID_
ACCESS2
0
0
0
0
0
0
0
0
0
0
0
0
0
NSAID_WR_EN[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
BASE_ADDRESS_LOW[19:0]
Res.
0x16C
TZC_REGION_
TOP_HIGH3
0
0
0
0
0
0
0
0
0
0
0
0
REGION_BASE_HIGH3[31:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x170
TZC_REGION_
ATTRIBUTE3
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
0
0
Res.
0
Res.
0
0
Res.
0
Res.
0
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
S_RD_EN
0
S_WR_EN
Reset value
0
Res.
Res.
0x168
TZC_REGION_
TOP_LOW3
Reset value
0
Res.
0x164
TZC_REGION_
BASE_HIGH3
0
Res.
TZC_REGION_
BASE_LOW3
0
NSAID_RD_EN[15:0]
Reserved
0x160
FILTER_EN[1:0]
REGION_TOP_HIGH2[31:0]
Res.
Reset value
0x158 0x15C
0
Res.
Reset value
TOP_ADDRESS_LOW[19:0]
Reset value
0
0
0x174
TZC_REGION_ID_
ACCESS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FILTER_EN[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
NSAID_RD_EN[15:0]
Res.
0
0
Res.
0
0
Res.
NSAID_WR_EN[15:0]
Reserved
Res.
TZC_REGION_
BASE_LOW4
Reset value
338/3930
REGION_TOP_HIGH3[31:0]
Res.
0x180
0
Res.
Reset value
0x178 0x17C
0
Res.
Reset value
TOP_ADDRESS_LOW[19:0]
BASE_ADDRESS_LOW[19:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0442 Rev 7
0
0
0
TrustZone® address space controller for DDR (TZC)
RM0442
Table 21. TZC register map and reset values (continued)
0x184
Register name
reset value
Register size
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Offset
TZC_REGION_
BASE_HIGH4
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x190
TZC_REGION_
ATTRIBUTE4
Res.
Res.
Res.
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
S_RD_EN
0x18C
TZC_REGION_
TOP_HIGH4
0
S_WR_EN
0x188
TZC_REGION_
TOP_LOW4
REGION_BASE_HIGH4[31:0]
0
Reset value
0
0
0x194
TZC_REGION_ID_
ACCESS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NSAID_WR_EN[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
0
Res.
0
Res.
0
Res.
BASE_ADDRESS_LOW[19:0]
Res.
Res.
Res.
0x1AC
TZC_REGION_
TOP_HIGH5
0
0
0
0
0
0
0
0
0
0
0
0
REGION_BASE_HIGH5[31:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x1B0
TZC_REGION_
ATTRIBUTE5
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
S_RD_EN
0
S_WR_EN
Reset value
0
Res.
0x1A8
TZC_REGION_
TOP_LOW5
Reset value
0
Res.
0x1A4
TZC_REGION_
BASE_HIGH5
0
Res.
TZC_REGION_
BASE_LOW5
0
NSAID_RD_EN[15:0]
0
Reserved
0x1A0
FILTER_EN[1:0]
REGION_TOP_HIGH4[31:0]
Res.
0x198 0x19C
0
Res.
Reset value
0
Res.
Reset value
TOP_ADDRESS_LOW[19:0]
Reset value
0
0
0x1B4
TZC_REGION_ID_
ACCESS5
0
0
0
0
0
0
0
0
0
0
0
0
0
NSAID_WR_EN[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
BASE_ADDRESS_LOW[19:0]
Res.
Reset value
0
Res.
Reset value
0
Res.
0x1CC
TZC_REGION_
TOP_HIGH6
Reset value
0
Res.
Res.
0x1C8
TZC_REGION_
TOP_LOW6
Reset value
0
Res.
0x1C4
TZC_REGION_
BASE_HIGH6
0
Res.
TZC_REGION_
BASE_LOW6
0
NSAID_RD_EN[15:0]
Reserved
0x1C0
FILTER_EN[1:0]
REGION_TOP_HIGH5[31:0]
Res.
Reset value
0x1B8 0x1BC
0
Res.
Reset value
TOP_ADDRESS_LOW[19:0]
0
0
0
0
0
0
0
0
0
0
0
0
REGION_BASE_HIGH6[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TOP_ADDRESS_LOW[19:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
REGION_TOP_HIGH6[31:0]
0
0
RM0442 Rev 7
0
0
0
0
0
0
339/3930
341
TrustZone® address space controller for DDR (TZC)
RM0442
Table 21. TZC register map and reset values (continued)
0
0
0
0
0
0
0
0
0
0
0
FILTER_EN[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
BASE_ADDRESS_LOW[19:0]
Res.
Res.
Res.
0x1EC
TZC_REGION_
TOP_HIGH7
0
0
0
0
0
0
0
0
0
0
0
0
REGION_BASE_HIGH7[31:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x1F0
TZC_REGION_
ATTRIBUTE7
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
S_RD_EN
0
S_WR_EN
Reset value
0
Res.
0x1E8
TZC_REGION_
TOP_LOW7
Reset value
0
Res.
0x1E4
TZC_REGION_
BASE_HIGH7
0
Res.
TZC_REGION_
BASE_LOW7
0
NSAID_RD_EN[15:0]
0
Reserved
0x1E0
Res.
Res.
Res.
Res.
Res.
NSAID_WR_EN[15:0]
0
0
Res.
0x1D8 0x1DC
Res.
0
Res.
0
Reset value
Res.
0x1D4
Res.
0
Res.
0
Res.
Reset value
TZC_REGION_ID_
ACCESS6
Res.
TZC_REGION_
ATTRIBUTE6
Res.
0x1D0
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register size
S_RD_EN
Register name
reset value
S_WR_EN
Offset
Reset value
0
0
0x1F4
TZC_REGION_ID_
ACCESS7
0
0
0
0
0
0
0
0
0
0
0
NSAID_WR_EN[15:0]
0
0
0
0
0
0
0
0
0
0
0
NSAID_RD_EN[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
BASE_ADDRESS_LOW[19:0]
Res.
Res.
Res.
0x20C
TZC_REGION_
TOP_HIGH8
0
0
0
0
0
0
0
0
0
0
0
0
REGION_BASE_HIGH8[31:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TZC_REGION_
ATTRIBUTE8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
0
0
Res.
0
Res.
0
0
Res.
0
Res.
0
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
S_RD_EN
0
S_WR_EN
Reset value
0
Res.
0x208
TZC_REGION_
TOP_LOW8
Reset value
0
Res.
0x204
TZC_REGION_
BASE_HIGH8
FILTER_EN[1:0]
REGION_TOP_HIGH7[31:0]
Res.
TZC_REGION_
BASE_LOW8
Reset value
0
0
TOP_ADDRESS_LOW[19:0]
0
0
REGION_TOP_HIGH8[31:0]
FILTER_EN[1:0]
Reset value
340/3930
0
Reserved
0x200
0x210
0
Res.
Reset value
0x1F8 0x1FC
0
Res.
Reset value
TOP_ADDRESS_LOW[19:0]
0
RM0442 Rev 7
0
0xFFC
TZC_CID3
RM0442 Rev 7
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
0
0
0
0
0
0
0
0
PER_ID_4[7:0]
NSAID_WR_EN[15:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
TZC_REGION_ID_
ACCESS8
Res.
TZC_CID2
0
Res.
0xFF8
TZC_CID1
Res.
0xFF4
TZC_CID0
Res.
0xFF0
TZC_PID3
0
Res.
0xFEC
TZC_DRASC_
PID2
0
Res.
0xFE8
TZC_PID1
Res.
0xFE4
TZC_PID0
Res.
0xFE0
TZC_PID7
Res.
0xFDC
TZC_DRASC_
PID6
Res.
0xFD8
TZC_PID5
Res.
0xFD4
TZC_PID4
Res.
0xFD0
Res.
0x218 0xFCC
0
Res.
Reset value
Res.
0x214
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register name
reset value
Res.
Offset
Res.
RM0442
TrustZone® address space controller for DDR (TZC)
Table 21. TZC register map and reset values (continued)
Register size
NSAID_RD_EN[15:0]
PER_ID_5[7:0]
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
1
0
PER_ID_6[7:0]
0
PER_ID_7[7:0]
0
PER_ID_0[7:0]
0
PER_ID_1[7:0]
1
PER_ID_2[7:0]
0
PER_ID_3[7:0]
0
0
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
0
COMP_ID_0[7:0]
1
0
1
0
0
0
0
0
1
COMP_ID_1[7:0]
0
COMP_ID_2[7:0]
1
COMP_ID_3[7:0]
1
Refer to Section 2.3 on page 101 for the register boundary addresses.
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7
RM0442
DDR physical interface control (DDRPHYC)
Portions Copyright (c) Synopsys, Inc. All rights reserved. Used with permission.
7.1
7.2
DDRPHYC features
•
32-bit DDR PHY compatible with JEDEC Standards for DDR3/3L, LPDDR2 and
LPDDR3 SDRAMs.
•
Dual width support: 16-bit (half-width with 2-byte lanes) or 32-bit (full-width with 4-byte
lanes) DDRPHYC permits operating with SDRAMs narrower than the implemented
data width.
•
Operating up to 533 MHz (1066 MT/s) with DDR3/3L.
•
Operating up to 533 MHz (1066 MT/s) with LPDDR2/3.
•
PHY Utility Block (PUBL) to support the PHY initialization, control and calibrations.
•
DFI 2.1 compliant interface to the DDRCTRL controller.
•
Programmable output and ODT impedance with dynamic PVT compensation.
•
Embedded dynamic drift detection in the PHY to facilitate dynamic drift compensation
by the controller.
•
Utilizes master and slave DLLs for a precise timing management.
•
Lane-based architecture with 4-byte lanes + 1 command/address lane.
•
Test modes supporting the IDDq and DLL characterization.
DDRPHYC block diagram
The DDRPHYC block diagram is shown in Figure 12.
The DDRPHYC is composed of:
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•
A DDRPHY physical interface which is structured into one command lane and 4-byte
lanes and used to generate signals with accurate timings at the SDRAM interface.
•
A PUBL (PHY Utility Block Logic) which is used to service the PHY and controlled via
the APB and JTAG interfaces.
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DDR physical interface control (DDRPHYC)
Figure 12. DDRPHYC block diagram
DDRPHYC
DDRPHY
Byte lane 0 PHY
MSDLL
ITM
DDRCTRL
DFI 2.1
MSDLL
Byte lane 1 PHY
ITM
JTAG
PUBL
ITM
APB
ITM
registers
MSDLL
I/O
Byte lane 2 PHY
MSDLL
APB
(PUBL control
register)
I/O
DQ[]
DQS/
DQS#
DQM
Command lane
PHY
MDLL
Connected to
SoC JTAG
chain
I/O
DQ[]
DQS/
DQS#
DQM
I/O
Byte lane 3 PHY
ITM
I/O
Ck/Ckb
Cmd/Add
DQ[]
DQS/
DQS#
DQM
DQ[]
DQS/
DQS#
DQM
MSv46541V2
7.3
DDRPHYC SDRAM interface
The DDRPHYC SDRAM interfaces are listed in Table 22.
Table 22. DDRPHYC I/O list
Pin name
DDR3/3L LPDDR2/3
Description
DDR_DQ31 to DDR_DQ24
Yes
Yes
Byte lane 3 DQ
DDR_DQS3P
Yes
Yes
Byte lane 3 DQS
DDR_DQS3N
Yes
Yes
Byte lane 3 DQS#
DDR_DQM3
Yes
Yes
Byte lane 3 DQM
DDR_DQ23 to DDR_DQ16
Yes
Yes
Byte lane 2 DQ
DDR_DQS2P
Yes
Yes
Byte lane 2 DQS
DDR_DQS2N
Yes
Yes
Byte lane 2 DQS#
DDR_DQM2
Yes
Yes
Byte lane 2 DQM
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Table 22. DDRPHYC I/O list (continued)
Pin name
DDR3/3L LPDDR2/3
Description
DDR_DQ15 to DDR_DQ8
Yes
Yes
Byte lane 1 DQ
DDR_DQS1P
Yes
Yes
Byte lane 1 DQS
DDR_DQS1N
Yes
Yes
Byte lane 1 DQS#
DDR_DQM1
Yes
Yes
Byte lane 1 DQM
DDR_DQ7 to DDR_DQ0
Yes
Yes
Byte lane 0 DQ
DDR_DQS0P
Yes
Yes
Byte lane 0 DQS
DDR_DQS0N
Yes
Yes
Byte lane 0 DQS#
DDR_DQM0
Yes
Yes
Byte lane 0 DQM
DDR_A15 to DDR_A0
Yes
Yes(1)
Row/column address / CA[] pins for
LPDDR2/3
DDR_BA2 to DDR_BA0
Yes
no
Bank address
DDR_CKE
Yes
Yes
CKE
DDR_CLKP
Yes
Yes
CK
DDR_CLKN
Yes
Yes
CK#
DDR_RASN
Yes
no
RAS#
DDR_CASN
Yes
no
CAS#
DDR_WEN
Yes
no
WE#
DDR_CSN
Yes
Yes
CS#
DDR_ODT
Yes
no
ODT
DDR_RESETN
Yes
no
RESET#
DDR_VREF1 to
DDR_VREF3
Yes
Yes(2)
Connected to Vref= VDDQ/2
DDR_ZQ
Yes
Yes
Connected to external R =240 Ω ±1%
DDR_DTO0
Test
Test
Reserved for DLL test purposes
DDR_DTO1
Test
Test
Reserved for DLL test purposes
DDR_ATO
Test
Test
Reserved for DLL test purposes
1. For LPDDR2/3: DDR_A[9:0] are used as CA[9:0] and DDR_A[15:10] are not used.
2. DDR_VREF1: command lane reference, DDR_VREF2: byte lane 3 and 1 common reference,
DDR_VREF3: byte lane 2 and 0 common reference.
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7.4
DDRPHY (DDR multiPHY IP core)
7.4.1
DDRPHY overview
The DDRPHY diagram is shown in Figure 13. It is implemented with a structured layout into
4-byte lanes and one address/command lane with:
•
MDLL and MSDLLs to provide accurate timings with 90 deg phase shifts
•
ITM: Interface timing modules, with the following types:
•
–
ITMD for DQ/DM signals,
–
ITMS for DQS/DQS# signals,
–
ITMC_D2 for address/command and CK/CK# signals.
SSTL I/O’s.
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Figure 13. DDRPHY block diagram
Byte lane 0 segment
ITMD
SSTL
I/O
DQ[] /
DQM
ITMS
SSTL
I/O
DQS/
DQS#
ITMD
SSTL
I/O
DQ[] / DQM
ITMS
SSTL
I/O
DQS/DQS#
SSTL
I/O
CK / CK#
CA[]
ITMD
SSTL
I/O
DQ[] / DQM
ITMS
SSTL
I/O
DQS/DQS#
ITMD
SSTL
I/O
DQ[] / DQM
ITMS
SSTL
I/O
DQS/DQS#
MSDLL
Byte lane 1 segment
MSDLL
Command lane segment
MDLL
ITMC_D2
Byte lane 2 segment
MSDLL
Byte lane 3 segment
MSDLL
MSv46542V2
7.4.2
Delay locked loop (DLL)
The DLLs are shown in Figure 14
The Master DLL (MDLL) uses the input (clk_in) to generate four clock outputs, each delayed
in quarter clock cycle (90º) increments. These four clock phases (clk_0, clk_90, clk_180,
clk_270) are generated with very high accuracy and low jitter across a wide range of
frequencies.
The Mast-Slave DLL (MSDLL) is composed of a MDLL and a slave delay pair.
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The slave delay pair uses a timing reference from MDLL to provide a highly accurate 90º
delay to the DQS/DQS# inputs and generate dqs_90 and dqsb_90 respectively.
DLL key features:
•
Master/Slave DLL architecture for complex timing while reducing total power
consumption with:
–
Master DLL for SDRAM command / address interface and general host timing.
–
Master-Slave DLL for SDRAM data lanes (DQ/DQS ) for write and read data
capture.
•
Operating range from 100 MHz to 533 MHz.
•
Optional: DLL bypass mode for LPDDR suitable for 10 MHz to 200 MHz and for low
speed functional and IDDQ tests.
•
Multi-phase outputs: 0deg, 90deg, 180deg 270deg.
•
Extensive DLL control for fine-tuning system timings.
•
Analog and digital DLL test outputs for device characterization.
Figure 14. MDLL block diagram
MDLL
clk_in
clk_0
clk_90
clk_180
clk270
Delay line
MSv46553V1
Figure 15. MSDLL block diagram
MSDLL
clk_in
Delay line
clk_0
clk_90
clk_180
clk270
dqs
slave delay
dqs_90
dqsb
slave delay
dqsb_90
MSv47333V1
The DLL settings are controlled by a control bus dllctrl[51:0] described in Table 23: MSDLL
control bits.
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Table 23. MSDLL control bits
Control bus
Signal name
MSDLL PUBL
register
MDLL PUBL
register
Default
Description
dllctrl[51]
lltm
DXnDLLCR[19]
N/A
0b0
Locked loopback test mode select:
0: normal, 1: Loopback
dllctrl[50]
test_hizb_a
DXnDLLCR[18]
ACDLLCR[18]
0b0
Analog test output tri-state control 0:
hiZ, 1: analog low Z
dllctrl[49:46]
sl_phase_trm[3:0]
DXnDLLCR[17:14]
N/A
0b0000
Slave phase lock trim (4 bits
encoded 18 deg step from 36 to
144deg)
dllctrl[45:44]
sl_bypass_start_up[
1:0]
DXnDLLCR[13:12]
N/A
0b00
Slave auto-startup bypass
dllctrl[43:38]
fb_trm[5:0]
DXnDLLCR[11:6]
ACDLLCR[11:6]
0b000000
Master feedback delay adjust.
fb_trm[5:3]: feed forward delay,
fb_trm[2:0]: feedback delay
dllctrl[37:32]
sl_fb_trm[5:0]
DXnDLLCR[5:0]
N/A
0b000000
Slave feedback delay adjust
(fb_trm[5:3]: ffd, fb_trm[2:0]: fbk)
dllctrl[29]
lock_det_en
DLLGCR[29]
N/A
0b0
Lock detector enable
dllctrl[28:27]
fdtrm_sl[1:0]
DLLGCR[28:27]
DLLGCR[28:27]
0b00
Slave bypass fixed delay trim
(-10%, 0, +10%, +20%)
dllctrl[26:24]
sl_bias_trm[6:4]
DLLGCR[26:24]
DLLGCR[26:24]
0b011
Slave bias generator control voltage
trim: VC
dllctrl[23]
bps200
DLLGCR[23]
DLLGCR[23]
0b0
Bypass frequency select
(0: 0-100MHz, 1:0-200MHz)
dllctrl[22:20]
sl_bias_trm[2:0]
DLLGCR[22:20]
DLLGCR[22:20]
0b111
Slave bias generator frequency trim:
Fmax
dllctrl[18:16]
bias_trm[6:4]
DLLGCR[18:16]
DLLGCR[18:16]
0b011
Master bias generator control
voltage trim: VC
{dllctrl[19],dllct
rl[15]}
fdtrm[1:0]
DLLGCR[19],DLLGC
R[15]
DLLGCR[19],D
LLGCR[15]
0b00
Master bypass fixed delay trim
(-10%, 0, +10%, +20%)
dllctrl[14:12]
bias_trm[2:0]
DLLGCR[14:12]
DLLGCR[14:12]
0b111
Master bias generator frequency
trim: Fmax
dllctrl[11]
test_ctrl_switch
DLLGCR[11]
N/A
0b0
Test control: Switch for analog and
digital. 0: master, 1: slave
dllctrl[10:9]
test_ctrl_a[1:0]
DLLGCR[10:9]
DLLGCR[10:9]
0b00
Test control: selects the analog
signal at ana test
dllctrl[8:6]
test_ctrl_d[2:0]
DLLGCR[8:6]
DLLGCR[8:6]
0b000
Test control: selects the digital
signal at dig test
dllctrl[5]
test_ctrl_en
DLLGCR[5]
DLLGCR[5]
0b0
Test control enable for analog and
digital test
dllctrl[4:2]
ipump_trm[2:0]
DLLGCR[4:2]
DLLGCR[4:2]
0b000
Charge pump current trim
(0: max current)
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7.4.3
DDR physical interface control (DDRPHYC)
Interface timing modules (ITMs)
The ITMs are used to generate signals with precise timing:
–
90deg phase delay of CK/CK# for the command / address bus
–
90deg phase delay of DQS/DQS# for write DQ/DQM byte lane outputs
–
Sampling of read DQ inputs on a 90 deg phase delay of incoming DQS/DQS#
There are three types of ITM:
•
ITMC_D2 for clock, address and command lanes.
•
ITMS for DQS/ DQS# differential strobes.
•
ITMD for DQ, DQM bytre lanes.
The ITMs are shown in Figure 16.
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Figure 16. ITMs block diagram
ITMC_D2 for CLK/CLK# and Commands
dout[1:0]
io_do
oe
from PUBL
ITMC_D2
di
io_oe To SSTL I/O
io_di
tmsel
clk_0, clk_90, clk180, clk _270
tmsel: 0: SDR, 1: DDR
From MDLL
ITMS for DQS/DQS#
dout[1:0]
oe
io_do
ITMS
di
from PUBL
io_oe To SSTL I/O
io_di
Delay trim &
drift detection
dqs_trm[2:0]: delay dqs/dqsb
in -3 to +4 fine step
dqs_drift[1:0] Phase drift info
clk0, clk90,
clk180, clk270
dqs_90,
dqsb_90
From MSDLL
ITMD for DQ
dout[1:0]
oe
from PUBL
io_do
ITMD
(Read FIFO)
di
To SSTL I/O
io_di
Delay trim
Read
valid
dq_trm[3:0]: delay increase wrt dqs/dqsb
in 0,1,2,3 fine step
io_oe
clk0, clk90,
clk180, clk270
dqs_90,
dqsb_90
From MSDLL
MS 46554V3
The ITMC-D2 does the SDR to DDR signaling conversion for LPDDR2/3 (tmsel =1).
The ITMC_D2 connections to set timings according to SDRAM type are shown in Figure 17
and Figure 18.
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Figure 17. ITMC_D2 for LPDDR2/3
DLL_CTRL[51:0]
MDLL
clk_270
clk_180
clk_90
clk_0
clk_in
tmsel = 0
ITMC_D2
I/O
CK
ITMC_D2
I/O
CK_b
ITMC_D2
I/O
CMD/
ADD
dout[1:0]
=’01'
tmsel = 0
dout[1:0]
=’10'
tmsel = 1
dout[1:0]
to CA[19:10]/CA[9:0]
MSv46556V1
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Figure 18. ITMC_D2 for DDR3/3L
DLL_CTRL[51:0]
MDLL
clk_270
clk_180
clk_90
clk_0
clk_in
tmsel = 0
ITMC_D2
I/O
CK
ITMC_D2
I/O
CK_b
ITMC_D2
I/O
CMD/
ADD
dout[1:0]
=’01'
tmsel = 0
dout[1:0]
=’10'
tmsel = 0
dout[1:0]
to same value
MSv46555V2
The ITMS are used for DQ strobes (DQS/DQS#) with:
•
SDR to DDR signaling conversion in output direction.
•
Phase select positioning
•
Fine step delay
•
Drift monitoring support
ITMS connections and timings are shown in Figure 19.
ITMD are used for data lanes (DQ[] and DQM) with:
•
SDR to DDR signaling conversion in input and output directions.
•
Sampling of incoming dq input on DQS and DQS# 90deg phases into a read FIFO
•
Fine step sampling delay.
ITMD connections and timings are shown in Figure 19.
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Figure 19. ITMS and ITMD for DQ/DQS lanes
DLL_CTRL[51:0]
clk_in
clk_0
clk_90
clk_180
clk_270
dqsb_90
dqs_90
MSDLL
phase_sel[1:0]
dqs delay
dqs_trm[2:0]
drift[1:0]
dout[1:0]
dq_trm[3:0]
din[1:0]
dout[1:0]
dq_trm[3:0]
din[1:0]
DQS
ITMS
dqs_b
dqs_trm[2:0]
drift[1:0]
I/O
delay
ITMS
I/O
DQS_b
I/O
DQ/
DQM
ITMD
Fifo
Delay
ITMD
Fifo
Delay
I/O
DQ/
DQM
Out path:
ITMD: D0 on 0deg / D1 on 180deg
ITMS: D0 on 90deg / D1 on 270deg
In path:
ITMD: D0 sampled on DQS_90/ D1
sampled on DQSb_90
MSv46557V1
7.4.4
SSTL IO’s
SSTL IO key features:
•
DDR3/DDR3L/LVCMOS operating modes
•
Compatible with JEDEC standard for DDR3/DDR3L SDRAMs
•
Programmable termination for DDR3/3L (ODT)
•
Programmable output impedance
•
PVT-compensated ODT and output impedance
•
Driver and receiver power-down control
•
Embedded boundary scan support logic
•
PAD and internal loopback modes
•
Core and I/O power down options supported
•
Retention feature maintains I/O cell state during VDD power down
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ZQ calibration cell:
The ZQ calibration cell provides independent calibration capability for the pull-up and pulldown ODT termination and for output impedances of the SSTL I/Os.
There are four sense blocks that provide independent sense capability for each impedance
element:
–
Pull-up termination impedance.
–
Pull-down termination impedance.
–
Pull-up output impedance.
–
Pull-down output impedance.
These four elements are calibrated in series using the calibration select input ZCAL[1:0].
The calibration sequence is:
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1.
Output impedance pull-down.
2.
Output impedance pull-up.
3.
On-Die termination (ODT) pull-down.
4.
ODT pull-up.
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7.5
DDR physical interface control (DDRPHYC)
PUBL
The PUBL is intended to ease the control of the PHY features. It supports the PHY
initialization, DQS gate training and programmable configuration control.
PUBL supports:
1.
DDRPHY and SDRAM initialization sequences for all types of memories: DDR3/3L,
LPDDR2 and LPDDR3.
2.
A built-in DQS gate training (DQSTRN) to assist in programming the read DQS gate
timing.
3.
A DRAM Command Unit (DCU) to assist in programming the DRAM for timing
calibration purposes.
The PUBL supports a DFI 2.1 interface with the DDRCTRL.
The PUBL includes configuration registers accessible via an APB interface. It also provides
a JTAG interface access for test purposes.
A simplified block diagram of PUBL is shown in Figure 20.
Figure 20. PUBL block diagram
APB
Configuration
Registers
JTAG
Initialization
Data Training
Command
scheduler
DFI 2.1
To PHY
DCU
To DDR_CTRL
MSv46569V2
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The following is a brief overview of the different design blocks and functionality of the PUBL:
7.5.1
•
Configuration registers: includes all registers required to configure, control, train and
self-test the PHY. The configuration block also contains registers required to initialize
the DRAM.
•
Initialization: used to automatically initialize the PHY, including locking of the DLL and
calibration of I/O impedances. The initialization block also implements built-in
initialization of all supported DRAMs.
•
Data training: used to train the PHY for optimum timing margins. This includes finding
the best positioning of the DQS gating window during reads, read valid generation and
optimizing the read data eye.
•
DRAM command unit (DCU): allows the issuing of DRAM commands through the
configuration port.
This may be used to implement software DRAM initialization. It is also used for silicon
debug and characterization of the PHY and the DDR interface.
•
Command scheduler: multiplexes commands from internal PUBL blocks and the
external memory controller and generates correct DRAM transactions in DFI 2.1
format. The commands from the external controller are passed to the DFI 2.1 block
unmodified.
•
DFI 2.1 interface: implements a DFI 2.1-compliant interface between the controller
DDRCTRL and the PHY.
PHY and SDRAM initialization
Figure 21. shows a high-level diagram of the PHY initialization sequence.
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Figure 21. DDRPHY initialization sequence
Un-initialized PHY
DLL soft reset
Impedance
Calibration
DLL lock
PHY initialization
ITM soft reset
Initialized PHY
SDRAM
initialization
DQS gate training
Triggered only after
PHY initialized
RV training
Data eye training
PHY ready
MSv46568V1
The initialization sequence has two phases. The first phase (shown in solid lines in
Figure 21) happens automatically at reset and is used as follows:
1.
Before and during configuration reset, the PHY is un-initialized and remains in this
state until the reset is de-asserted.
2.
At reset de-assertion, the PHY moves into the DLL initialization phase.
This phase may be bypassed at any time by writing a '1' to bit LOCKBYP of the DDR
PHY initialization register (DDRPHYC_PIR).
3.
In parallel to DLL initialization, the impedance calibration phase also starts at reset deassertion.
This phase can also be bypassed by writing a '1' to the ZCALBYP bit of DDR PHY
initialization register (DDRPHYC_PIR).
4.
If the PHY initialization sequence was triggered by the user, a soft reset may optionally
be selected to be issued to the ITMs.
Initialization that is automatically triggered on reset does not issue a soft reset to the
ITMs because the components have been already reset by the main reset.
5.
Once the DLL initialization and impedance calibration phases are done and after the
ITMs are reset, the PHY is initialized.
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If these phases were bypassed, it is up to the user to perform them in software or trigger
them at a later time before the PHY can be used.
The second phase of initialization starts after the PHY is initialized. Each step of this phase
is triggered by the user (APB interface) or by DDR_CTRL:
1.
The user or memory controller performs SDRAM initialization sequence (see “SDRAM
Initialization”). The DRAM mode registers and necessary timing parameters must first
be programmed into the PUBL before triggering SDRAM initialization.
2.
After the SDRAM is initialized, the user or memory controller performs, or triggers the
PUBL to perform, DQS gate training (see “Built-in DQS Gate Training” in Section 7.5.6:
DQS gate training (DQSTRN)). The SDRAM must be initialized before triggering DQS
gate training.
3.
The user or memory controller performs, or triggers the PUBL to perform, read data
valid training. PHY Initialization may be either Reset_triggered or PIR-triggered
4.
The user or memory controller performs, or triggers the PUBL to perform, read data
eye training.
Note: the current version of the PUBL does not have the read eye training designed in.
5.
The PHY is now ready for SDRAM read/write accesses.
The PUBL has a built-in SDRAM initialization routine that may be triggered by software or
DDR_CTRL by writing to the PHY initialization register (DDRPHYC_PIR).
The initialization routine built into the PUBL is generic and does not require any knowledge
of the type or configuration of external SDRAMs to be properly executed. The routine is
designed with the relevant JEDEC specifications for the fastest and slowest SDRAMs
supported by the PUBL to result in a universal initialization sequence. This generic
sequence is applicable to DDR3 and LPDDR2 and DDR SDRAMs.
It is recommended to use the built-in PUBL routine to initialize the SDRAM. However, there
may be cases such as during system debug when the built-in PUBL DRAM initialization is
not triggered and DRAM initialization is performed by software or by the controller.
In these cases the system must first wait for the PHY to initialize, i.e. DLL locked and
impedance calibration done, then it must write a '1' to the INIT bit of DDRPHYC_PIR with bit
CTLDINIT of DDRPHYC_PIR set to '1' (for controller initialization) or '0' (for software or
PUBL initialization) to inform the PUBL that DRAM initialization is done later, by software,
the controller or by re-triggering on the PUBL.
The software or controller then executes the initialization sequence by sending relevant
commands to the DRAM, respecting the various timing requirements of the initialization
sequence.
The necessary configurations of the SDRAM must first be programmed into the PUBL
before triggering SDRAM initialization.
SDRAM initialization must be triggered only after the PHY has been initialized.
All SDRAM initialization timing parameters described below are programmable in controller
clock cycles in PTR1 and PTR2 registers.
The following sections describe the built in SDRAM initialization routines for different types
of SDRAMs.
7.5.2
DDR3 initialization sequence
The initialization steps for DDR3 SDRAMs are as follows:
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1.
Optionally maintain RESET# low for a minimum of either 200 us (power-up
initialization) or 100ns (power-on initialization).
The PUBL drives RESET# low from the beginning of reset assertion and therefore this
step may be skipped if enough time may already have expired to satisfy the RESET#
low time.
2.
After RESET# is de-asserted, wait a minimum of 500 us with CKE low.
3.
Apply NOP and drive CKE high.
4.
Wait a minimum of tXPR
Caution: PUBL registers, SDRAM mode registers, and equivalent register fields inside
the memory controller must be uniformly programmed. Mismatches between the
register fields can cause transaction failures. Verify all register fields are consistently
programmed before starting any SDRAM transaction.
5.
Issue a load mode register 2 (MR2) command.
6.
Issue a load mode register 3 (MR3) command.
7.
Issue a load mode register (MR1) command (to set parameters and enable DLL).
8.
Issue a load mode register (MR0) command to set parameters and reset DLL.
9.
Issue ZQ calibration command.
10. Wait 512 SDRAM clock cycles for the DLL to lock (tDLLK) and ZQ calibration (tZQinit)
to finish.
This wait time is relative to Step 8, i.e. relative to when the DLL reset command was
issued onto the SDRAM command bus.
7.5.3
LPDDR2 initialization sequence
The initialization steps for LPDDR2 SDRAMs are as follows:
1.
Wait a minimum of 100 ns (tINIT1) with CKE driven low.
2.
Apply NOP and set CKE high.
3.
Wait a minimum of 200 us (tINIT3).
4.
Issue a RESET command.
5.
Wait a minimum of 1 us + 10 us (tINIT4 + tINIT5).
6.
Issue a ZQ calibration command.
7.
Wait a minimum of 1 us (tZQINIT).
8.
Issue a Write mode register to MR1.
9.
Issue a Write mode register to MR2
10. Issue a Write mode register to MR3
7.5.4
Initialization trigger and bypass
All initialization steps shown in Figure 21 can be triggered using the PHY initialization
register (DDRPHYC_PIR).
Writing a '1' to bit INIT of DDRPHYC_PIR register bit starts initialization, with the routines to
be run selected by the DDRPHYC_PIR register bits. If multiple routines are selected, they
are run in the order shown in Figure 21.
The completion of the routines is indicated in the PHY General Status Register
(DDRPHYC_PGSR) with the corresponding done status bits.
The DDRPHYC_PGSR.IDONE bit indicates the overall completion of the initialization
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sequence.
A status register bit is cleared (reset to '0') when the corresponding routine is re-triggered.
The de-assertion of reset automatically triggers the PUBL to perform DLL initialization with
DLL locking and impedance calibration. Once the DLL has locked and impedance
calibration has completed, the SDRAM initialization and DQS gating may be triggered or
performed by software or memory controller.
Since the PUBL allows the selection of individual routines to be run when initialization is
triggered using DDRPHYC_PIR register, the routines that automatically trigger on reset deassertion have individual bypass capability.
This means that DLL locking and/or impedance calibration may be bypassed any time by
writing a '1' to the corresponding bypass register bit in the DDRPHYC_PIR register. Once a
routine is bypassed, it is internally registered as completed and the corresponding done
status register bit is set in the PGSR register.
It is up to the user to re-trigger or perform the bypassed routines at a later time, before the
PHY can be used.
Bit INITBYP of DDRPHYC_PIR register provides the option to bypass the whole
initialization sequence
7.5.5
DATA training
After the DDRPHY and the external SDRAM have been successfully initialized, DDRPHY
may be trained for optimum operating timing margins.
This includes:
7.5.6
•
Training for DQS gating during reads (DQSTRN)
•
Training for optimal Read Valid placement (RVTRN)
DQS gate training (DQSTRN)
Built-in DQS gate training:
Note:
The built-in DQSTRN is mandatory and applicable only to DDR3/3L and may be using the
MPR register.
The PUBL has a built-in DQS gate training routine that may be triggered by software or
memory controller using the DDRPHYC_PIR register. Figure 22 shows the detailed flow of
the DQS gate training algorithm implemented in the PUB. This is followed by a description
of the main phases of the training.
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Figure 22. Buit-in DQS gate training flow
MSv46562V1
DQS gate training phases are as follows:
1.
Data Train Idle: before and during reset, the data training state machine is in the idle
state and remains in this state until the reset is de-asserted. The next configuration
register values to be used for DQS gating are also reset to zero. These are the values
that are written to DQS Gating System Latency (R0DGSL) and DQS Gating Phase
Select (R0DGPS) fields of the DDRPHYC_DXnDQSTR register before each iteration
of DQS gate training. Once reset is de-asserted, the FSM continues to remain in the
idle state until data training is triggered. The FSM also remains in the idle state if data
training is triggered with no ranks or bytes enabled. Otherwise the FSM goes to check
if the next rank or byte is enabled.
2.
Rank/byte enable check: this phase checks if the next rank/byte to be trained is
enabled, otherwise it skips the rank/byte and goes to the next rank/byte. Bytes are
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enabled/disabled using bit DXEN in DDRPHYC_DXnGCR register, and ranks are
enabled/disabled using field RANKEN in DDRPHYC_DXnGCR register.
3.
Precharge all banks: all banks are precharged before the beginning of training for each
rank and at the end of the whole training. If the precharge is at the end of the training,
the FSM goes to idle state, indicating the end of training. Otherwise it goes to prepare
the DRAM for accesses, i.e. enable the MPR register if data training using MPR is
selected, or activate the DRAM row to be used for write/read accesses.
4.
Enable MPR: issues a load mode register command to the DRAM to enable the MPR
register. This is only applicable for DDR3 DRAMs and only if the MPR bit is set in the
DTAR register.
5.
Activate: issues an activate command to the DRAM to open the bank row prior to
writing data for training. The DRAM address used for training is user programmable in
the DTAR register.
6.
Write data: issues an 8-beat write to the DRAM to load data for training. The DRAM
address and DRAM data used for training is user programmable in the DTAR,
DTDTR0, DTDTR1 registers.
7.
Write configuration register: once the data has been written to the DRAM (or MPR
register has been enabled), the FSM writes the next configuration setting for the byte to
the respective DQS gating register fields (DDRPHYC_R0DGSL and
DDRPHYC_R0DGPS).
8.
Read/collect data: this phase is executed either as a dummy read at the end of rank
training or end of whole training (to reset the drift status registers in the PHY ITMs to
the correct values), or it is executed as a normal read to evaluate if the DQS gate
configuration is valid. After a dummy read, the FSM goes on to train the next rank or if it
is the end of the whole training it goes to issue the last precharge or disable the MPR.
After a read has been issued to the DRAM the FSM waits for all read data to come
back. There is a time-out in case the read data does not come back. For a non-dummy
read, the FSM goes on to evaluate the read data for pass/fail status.
9.
Evaluate result: the read data is compared to the expected data and pass/fail status is
generated and saved. If the status is such that a fail-pass-fail region (FPPPPF) has
been found or if this is the last possible configuration (i.e. no passing region for this
byte) the midpoint of the passing region is selected and written to
(DDRPHYC_DXnDQSTR region. This signifies the end of training for the byte on the
selected rank. If this is the last byte of the rank, the FSM goes on to train the next rank,
otherwise it goes to the next byte of the rank. There is always a dummy read performed
at the end of training all bytes of the rank.
Software DQS gate training
The DQS gate training may also be executed in software using DDRCTRL and/or the PUB
DCU. Figure 23 shows the DQS gate training software algorithm. This is followed by a
description of the main phases of the training.
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Figure 23. Software DQS gate training flow
MSv46563V1
The software DQS gate training phases are as follows:
1.
Disable drift compensation by writing '0' to bit DFTCMP in DDRPHYC_DXnGCR
register.
2.
Start with rank 0, (DDRPHYC is supporting single rank only).
3.
Execute a minimum of two writes to the SDRAM. Any type of data and any SDRAM
address can be used for DQS gate training. It is however not recommended to use data
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that is all zeroes since this may mask read data comparison. The data mask must be
set to 0 to enable writing of all bytes. The number of writes must be chosen such that it
results in a minimum of eight data beats at the SDRAM. This means at least two write
commands when using SDRAM burst length of 4.
Note:
4.
Start with byte 0 (i.e. byte 0 is selected for training).
5.
Disable all the other bytes except the byte that has been selected for training. The
bytes are enabled/disabled by writing 1/0 to bit DXEN in DDRPHYC_DXnGCR register.
To avoid having to add programming and delay for a DLL re-lock when later re-enabling
a disabled byte Lane, it is recommended to also set bit PDDISDX=0 in
DDRPHYC_DXnGCR register before disabling any byte lanes. This prevents the byte
Lane's DLL from going into bypass mode when a byte Lane is disabled with bit
DXEN=0 in DDRPHYC_DXnGCR register.
6.
Start with the selected byte DQS gating system latency (RnDGSL=0 in DXnDQSTR
register).
7.
Start with the selected byte DQS gating phase select (RnDGPS=0 in DXnDQSTR
register).
8.
Write the selected DQS gating configurations (bit R0DGSL and R0DGPS in register
DXnDQSTR of the selected byte).
9.
Execute reads from the SDRAM locations previously written. The number of reads
must be equal to the number of writes used in Step 3. Compare the read data with the
expected (written) data and log the pass/fail status as a sequence or history of flags for
each trained RnDGSL/RnDGPS configuration (e.g. FFPPPPFF). A fail is either when
there is a data mis-compare or when fewer data than expected is returned.
A controller that is designed to always wait for the correct number of read data may need a
time-out in case the trained configuration results in fewer data than expected. This is not as
issue when using the PUB DCU because it does not wait for the expected number of reads;
rather the read count status indicates if fewer reads were returned.
10. Once the read data has been compared and the pass/fail status logged, issue an ITM
soft reset to clear the status of the read data logic in the PHY. This is important because
the ITM read data FIFO pointers may be in the wrong state at the end of training an
RnDGSL/RnDGPS configuration that resulted in wrong DQS gating window.
11. If two consecutive fails and some passes exist, then this is the end of the training for
this rank byte. In this case, do the following:
–
Select the middle of the passes and write the values to the corresponding fields of
DDRPHYC_DXnDQSTR register.
- If this is not the last byte, then select the next byte and go to Step 5.
- If this is the last byte but not the last rank, then select the next rank and go to
Step 3.
- If this is the last byte and the last rank, then go to Step 12 to do final clean-up
before the end of the DQS gate training.
–
If the condition of two consecutive fails and some passes does not exist, then this
signals that more RnDGSL/RnDGPS configurations need to be trained for this
rank byte. If this is the case, do the following:
- if R0DGPS is less than 3, then increment R0DGPS and go to Step 8
- if R0DGPS is equal to 3 but R0DGSL is less than 7, then increment R0DGSL
and go to Step 7
- if R0DGPS is equal to 3 and R0DGSL is equal to 7, then log an error because
this is a signal that something in the system is very wrong such that no passing
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configuration is possible for this rank byte. With such an error condition, you can
either terminate the whole training to investigate the system or you can go to train
the next byte.
12. Once the training of all ranks and all bytes is finished, issue one or more dummy reads
to the same SDRAM locations. This flushes out the DQS drift compensation logic in the
PHY and therefore avoid reporting any false drift events caused by previous DQS
gating settings.
13. Once the dummy reads have completed, re-enable drift compensation by writing 1 to
bit DFTCMP in DXnDQSTR register. This is the end of DQS gate training. Regular
memory operations can now commence.
For details of how the PUBL DCU can be used to SDRAM accesses, please refer to
Section 7.5: PUBL.
Note:
It is not necessary to issue auto-refresh commands to the SDRAM during software DQS
gate training if there is no data in the SDRAM other than the DQS gate training data. This is
because the same locations are being read over and over within a relatively short period of
time that should normally be less than the refresh timing requirement. However, if there is
other data in the SDRAM and the training is taking longer than the required refresh timing,
then refresh commands must be issued at the required intervals, interspersed relevantly
with the training commands.
Read DQS gate training with low frequency LPDDR
When using LPDDR SDRAM, the built-in read DQS gate training is accurate for standard
clock frequencies.
However, as the LPDDR tAC timing parameter becomes a smaller percentage of the clock
period, fewer read DQS gate settings work. The read DQS gating works at low frequencies
with LPDDR SDRAM, but this section provides additional guidance on how to correctly set
up read DQS gating at low frequencies with LPDDR SDRAM
For all values of tAC >= (0.25*tCK), normal training can be used. When using slower speeds
where tAC is less than 1 tCK, the number of data training passes may be less than ideal (as
low as two) but the gate position is still satisfactory, even when aligned with rising edge of
DQS. This is because there is enough margin before starting to see data fails (90 degrees of
margin and at low speed is very large number).
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The following lists the number of passing configurations for each of these settings and the
gate position:
tAC ≥ 1.0*tCK
–
Five passes, gate opening is positioned correctly 90degrees before rising edge of
DQS
tAC ≥ 0.75*tCK < 1.0*tCK
–
Four passes, gate opening is positioned correctly either aligned with rising edge of
DQS or 90 degrees before rising edge of DQS
tAC ≥ 0.5*tCK < 0.75*tCK
–
Three passes, gate opening is positioned correctly aligned with rising edge of
DQS
tAC ≥ 0.25*tCK < 0.5*tCK
–
Two passes, gate opening is positioned correctly aligned with rising edge of DQS
Note: The exception to this guidance is when tAC < 0.25*tCK. In this case, no training
should be performed and passive windowing should be used. Also, ensure the bits DGSL
and DGPS are set to zero (DGPS is 1 by default.)
7.5.7
Read valid training (RVTRN)
The PUBL has a built-in read valid training routine (RVTRN) that may be triggered by
software or the memory controller using the DDRPHYC_PIR register.
For DDR3 RVTRN is not required
For LPDDR2/3 RVTRN is normally run at the same time as DQSTRN; it is adjusting the read
valid system latency in extreme conditions with tDQSCK timings values.
7.6
PUBL timings and DFI interface
Note:
This section is intended to show signals timing at the DDRPHYC interfaces and the relation
between the signals at DFI and the SDRAM interface, with information about physical
delays which are programmed into DDRCTRL.
7.6.1
Introduction
This section describes the timing for the interface between the controller and the PHY.
The read/write timing waveforms include four groups of signals:
1.
DFI signals (dfi_*)
2.
PHY clocks (ctl_clk, clk_0,clk_90, clk_180, and clk_270)
3.
Controller-to-PHY interface signals (ctl_cmd, ctl_ds_oe, ctl_d_oe, ctl_d,ctl_qs_en,
ctl_qs_dis, and ctl_qs_phase)
4.
SDRAM signals (ck/ck_n, cmd, dqs/dqs_n, and dq).
only the important signals whose the timing needs to be controlled are shown, that are
dfi_* and SDRAM signals (DDR_*).
The PHY clock group is not shown and ctl_clk is identical to dfi_clk.
From the controller-to-PHY interface signal group, only the ctl_qs_en signal is shown with
the PHY passive DQS gating timing.
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The read/write waveforms are given for typical PHY configurations and SDRAM latencies;
the waveforms are shown for DDR3 mode.
The waveforms are mostly the same for active and the passive DQS gating, only the
passive DQS gating timing is shown with the ctl_qs_en signal.
The timing waveforms shown are for write latency (WL) of 5 and read latency (RL) of 5. The
timing of any latency, RWL, can be derived from these representative latencies by simply
shifting the timing of (ctl_ds_oe, ctl_d_oe, ctl_d, ctl_qs_en, ctl_qs_dis, and ctl_qs_phase)
relative to ctl_cmd by RWL controller clocks.
For DDR3, write latency (WL) is equal to CAS write latency (CWL) plus additive latency
(AL), and read latency (RL) is equal to CAS latency (CL) plus additive latency (AL).
7.6.2
Write timing
Figure 24 shows the write timing for DDR3 mode with WL = 5 and BL = 8
Note that dfi_clk and ctl-clk are the same clocks, only dfi_clk is shown. The only variable in
the DFI timing is the tphy_wrlat, which is the spacing between DFI write command and DFI
write data enable (dfi_wrdata_en) signal.
As shown in Table 25, this spacing is equal to WL-1. The DFI controller always drives the
write data (dfi_wrdata) one clock after it has driven the write data enable signal.
The timing of DFI write data mask (dfI_wrdata_mask) is the same as the timing of DFI write
data (dfi_wrdata) and is therefore not shown in the figure. The DFI write command (dfi_cmd)
is simply buffered to, and is therefore aligned with, the PHY controller command (ctl_cmd).
Figure 24 also shows the two PHY latency parameters for the command and data from the
controller to the SDRAM. The command latency (tCLAT) is measured from the rising edge
of the controller clock (ctl_clk) when the command is available to the PHY to the rising edge
of SDRAM clock (DDR_CLK) when the command is output. Similarly, write data latency
(tDLAT) is measured from the controller clock rising edge when data is available from the
controller to the rising edge of data strobe (DDR_DQS) on which SDRAM data is available.
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Figure 24. Write timing with WL = 5, BL = 8
Tphy_wrlat = WL-1
dfi_clk
dfi_cmd[15:0]
WR
tCLAT
dfi_wrdata_en
dfi_wrdata[15:0]
XX
D1D0
D3D2
D5D4 D7D6
XX
D0 D1 D2 D3 D4 D5 D6
D7
DDR_CLK
DDR_CMD[15:0]
tDLAT
WR
WL = 5
DDR_DQS
DDR_DQ[7:0]
Write timing: WL = 5, BL = 8
MSv46567V1
7.6.3
Read timing
Figure 25 shows the read timing for the DDR3 mode with WL = 5 and BL = 8.
Note that dfi_clk and ctl-clk are the same clocks, only dfi_clk is shown.
The only variable in the DFI timing is the trddata_en, which is the spacing between DFI read
command and DFI read data enable (dfi_rddata_en) signal. As shown in Figure 25, this
spacing is equal to RL-2.
The DFI read command (dfi_cmd) is simply buffered to, and is therefore aligned with, the
PHY controller command (ctl_cmd).
The timing shown in Figure 25 includes the timing of the read through the PHY read FIFO
back to the controller. It also shows the two PHY latency parameters for the data from the
SDRAM to the controller.
The data strobe latency (tQSLAT) is measured from the rising edge of the data strobe
(DDR_DQS) that is coincident with the first data beat to the rising edge of the controller
clock (ctl_clk same as dfi_clk) when data is sampled by the controller.
The read data latency (tQLAT) is measured from the rising edge of the data strobe
(DDR_DQS) after two data beats are available to the rising edge of the controller clock
(ctl_clk same as dfi_clk) when data is sampled by the controller.
The values of these parameters are described in Table 24. and Table 25.
Note that the read latencies have a variation of up to one controller clock cycle depending
on the alignment of the read data strobe and the controller clock. This is because of the
clock domain crossing between the read data strobe and the controller clock, which are
assumed to be completely asynchronous to each other.
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Figure 25. Read timing with WL = 5, BL = 8
Trddata_en = RL-2
dfi_clk
dfi_cmd[15:0]
RD
dfi_rddata_en
Tphy_rdlat = 7 *
dfi_rddata_valid
dfi_rddata[15:0]
XX
Q1Q0 Q3Q2 Q5Q4 Q7Q6
XX
1.25clk
DDR_CLK
tQSLAT
DDR_CMD[15:0]
RD
RL= 5
tQLAT
DDR_DQS
DDR_DQ[7:0]
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
ctl_qs_en
PHY passive DQS gating
Read timing: RL = 5, BL = 8
MSv47348V1
7.6.4
DDRPHY read/write latency
Table 24: PHY latency shows the latency of commands and data through the PHY.
Refer to Write timing on page 367 and Read timing on page 368 for definitions and
illustration of these parameters.
Table 24. PHY latency
SYMBOL
Description
Latency
Units
Note
tCLAT
Command Latency
1.25
tCLK
-
tDLAT
Write data Latency
1.25
tCLK
-
tQLAT
Read data Latency
1-2
tCLK
1
tQSLAT
Read data strobe Latency
2-3
tCLK
1
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The PHY Latency depends on the alignment of the read data strobe to the controller clock.
The PHY read latency parameter tphy_rdlat, i.e. the number of DFI clock cycles from the
assertion of dfi_rddata_en signal to the assertion of dfi_rddata_valid is defined as:
tphy_rdlat = 3 + tQSLAT + 1 + x + y
With the no-bubbles feature enabled, the latency is:
tphy_rdlat = 3 + tQSLAT + 1 + x + y + 2
With the fixed-latency feature enabled, the latency is:
tphy_rdlat = 12
Where:
x = propagation delay of the command from the PHY macro outputs to the SDRAM
y = propagation delay of the read data from the SDRAM to the PHY macro inputs
gdqs_rsl = set of DQS gating system latency values for all ranks and all byte-lanes
The term (+3) and the term (+1) of the above equations are internal DFI logic latencies.
The terms x and y include, among other things, the routing between the PHY and the I/Os,
the I/O propagation delays, package delays, board delays, and other delays associated with
the SDRAM that are not accounted for in the SDRAM read latency (RL) parameter.
The total read latency from the DFI read command to the DFI read data valid is
trddata_en + tphy_rdlat.
where trddata_en is described in Table 25.
7.6.5
DFI 2.1 overview
The DFI is an interface protocol that defines the connectivity between a DDR memory
controller (DDRCTRL) and a DDR physical interface (DDRPHY) for DDR memory devices
(here: DDR3 and LPDDR2).
The protocol defines the signals, signal relationships, and timing parameters required to
transfer control information and data to and from the DRAM devices over the DFI.
The DDRPHYC is supporting protocol version 2.1:
Interface signal groups
DFI is subdivided into the following interface groups:
•
Control interface
•
Write data interface
•
Read data interface
•
Update interface
•
Status interface
•
Training interface
•
Low power control interface
DFI timing parameters
The DFI defines several timing parameters with fixed values and specified as a number of
DFI clock cycles. Table 25 describes the DFI parameters applicable to DDRPHYC.
The DFI timings parameters are relevant for DDRCTL which needs to programmed
accordingly.
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Table 25. DFI timing parameters
Description
SDR
mode
Note
tctrl_delay
Specifies the number of DFI clock cycles after an assertion or deassertion of the
DFI control signals that the control signals at the PHY-DRAM interface reflect
the assertion or de-assertion. If the DFI clock and the memory clock are not
phase-aligned, this timing parameter should be rounded up to the next integer
value.
2
(1)
tphy_wrdata
Specifies the number of DFI clock cycles between when the dfi_wrdata_en
signal is asserted to when the associated write data is driven on the dfi_wrdata
signal.
1
-
tphy_wrlat
Specifies the number of DFI clocks between when a write command is sent on
the DFI control interface and when the dfi_wrdata_en signal is asserted
Note: In LPDDR2 mode, the following settings must be used:
WL = MR2[3:0].WL + 1 (to account for tDQSS)
WL-1
trddata_en
Specifies the time from the assertion of a read command on the DFI to the
assertion of the dfi_rddata_en signal.
Note: In LPDDR2 mode, the following settings must be used:
RL = MR2[3:0].RL + tDQSCK
RL-2
(2)(3)
tphy_rdlat
Specifies the maximum number of cycles allowed from the assertion of the
dfi_rddata_en signal to the assertion of the dfi_rddata_valid signal.
15
(5)
tdram_ck_disable
Specifies the number of clocks from the assertion of the dfi_dram_clk_disable
signal on the DFI until the clock to the DRAM memory devices, at the PHYDRAM boundary, maintains a low value
2
-
tdram_ck_enable
Specifies the number of clocks from the de-assertion of the
dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the
clock to the DRAM devices at the PHYDRAM boundary.
2
-
tphyupd_type0
Specifies the maximum number of DFI clocks that the dfi_phyupd_req signal
may remain asserted after the assertion of the dfi_phyupd_ack signal for
dfi_phyupd_type = 0.
1
(6)
tphyupd_resp
Specifies the maximum number of DFI clock cycles after the assertion of the
dfi_phyupd_req signal to the assertion of the dfi_phyupd_ack signal.
64
tphy_paritylat
Specifies the maximum number of DFI clock cycles between when the
dfi_parity_in signal is driven and when the associated dfi_parity_error is
returned.
PL+6
Name
(2)(3)
(4)
(7)
1. Actual latencies are 1.25 but rounded up to the next integer as per DFI specification.
2. For LPDDR2 device usage the WL is the SDRAM write latency (CAS write latency + additive latency + 1) to ensure that the
LPDDR2 tDQSS is accounted for. For all other DDR device usage the WL is the SDRAM write latency (CAS write latency +
additive latency ). If an external controller wants to run the PHY in loopback mode, i.e. if LBMODE is set, then tphy_wrlat
must be set to WL-2.
3. In LPDDR2 mode, WL = MR2.WL + 1 and RL = MR2.RL + tDQSCK.
4. RL is the SDRAM read latency (CAS latency + additive latency).
5. The number includes the latency through the PHY (i.e. command latency plus read latency), plus maximum possible
system latency that could be trained by the PUB.
6. This corresponds to the maximum time required for updating ITMs.
7. PL is the DIMM parity latency. it is N/A with current configuration.
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RM0442
7.7
PUBL registers
7.7.1
DDRPHYC revision ID register (DDRPHYC_RIDR)
Address offset: 0x000
Reset value: 0x0020 0200
31
30
29
28
27
26
25
24
23
UDRID[7:0]
22
21
20
19
PHYMJR[3:0]
18
17
16
PHYMDR[3:0]
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
PHYMNR[3:0]
r
r
r
PUBMJR[3:0]
r
PUBMDR[3:0]
r
r
r
PUBMNR[3:0]
r
r
r
Bits 31:24 UDRID[7:0]: User-defined rev ID
Bits 23:20 PHYMJR[3:0]: PHY maj rev
Bits 19:16 PHYMDR[3:0]: PHY moderate rev
Bits 15:12 PHYMNR[3:0]: PHY minor rev
Bits 11:8 PUBMJR[3:0]: PUB maj rev
Bits 7:4 PUBMDR[3:0]: PUB moderate rev
Bits 3:0 PUBMNR[3:0]: PUB minor rev
7.7.2
DDRPHYC PHY initialization register (DDRPHYC_PIR)
Address offset: 0x004
22
21
20
19
18
17
16
ZCALBYP
LOCKBY
P
CLRSR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DLLBYP
23
ICPC
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ZCAL
DLLSRST
24
CTLDINIT
25
DLLLOCK
26
ITMSRST
27
DRAMRST
28
DRAMINIT
29
QSTRN
30
RVTRN
31
INITBYP
Reset value: 0x0000 0000
INIT
w
w
w
w
w
w
w
w
w
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DDR physical interface control (DDRPHYC)
Bit 31
INITBYP: Initialization bypass
Bypasses or stops, if set, all initialization routines currently running, including PHY
initialization, DRAM initialization, and PHY training.
Initialization may be triggered manually using INIT and the other relevant bits of the
DDRPHYC_PIR register. This bit is self-clearing.
Bit 30
ZCALBYP: zcal bypass
Bypasses or stops, if set, impedance calibration of all ZQ control blocks that automatically
triggers after reset.
Impedance calibration may be triggered manually using INIT and ZCAL bits of the
DDRPHYC_PIR register. This bit is self-clearing.
Bit 29 LOCKBYP: DLL lock bypass
Bypasses or stops, if set, the waiting of DLLs to lock. DLL lock wait is automatically triggers
after reset.
DLL lock wait may be triggered manually using INIT and DLLLOCK bits of the
DDRPHYC_PIR register. This bit is self-clearing.
Bit 28 CLRSR: clear status register
Writing 1 to this bits does the following:
– Auto-clears itself. This means a following read to bit CLRSR returns 0
– Clears the DXnGSR0 bits for DTDONE, DTERR, DTIERR
– Clears bit DFTERR in DDRPHYC_PGSR register and bit DFTERR in
DDRPHYC_DXnGSR1 register
This bit is primarily for debug purposes and is typically not needed during normal functional
operation.
It can be used when bit IDONE=1 in PGSR register, to manually clear the PGSR status bits,
however, the PGSR status bits (except for the DFTRR and TQ bits) are automatically cleared
by starting a new init process.
The bit can also be used to manually clear the DXnGSR status bits, however, starting a new
data training process automatically clears the DXnGSR status bits.
Bits 27:19 Reserved, must be kept at reset value.
Bit 18 CTLDINIT: Controller DRAM initialization
Indicates if set that DRAM initialization is performed by the controller. Otherwise if not set it
indicates that DRAM initialization is performed using the built-in initialization sequence or
using software through the configuration port.
Bit 17 DLLBYP: DLL bypass
A setting of 1 on this bit puts all PHY DLLs in bypass mode. A bypassed DLL is also powered
down (disabled).
Bit 16 ICPC: Initialization complete pin configuration
Specifies how the DFI 2.1 initialization complete output pin should be used to indicate the
status of initialization.
0: Asserted after PHY initialization (DLL locking and impedance calibration) is complete.
1: Asserted after PHY initialization is complete and the triggered PUBL initialization (DRAM
initialization, data training, or initialization trigger with no selected initialization) is complete.
Bits 15:9 Reserved, must be kept at reset value.
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RM0442
Bit 8 RVTRN:
it is expected that RVTRN and DQSTRN are run with LPDDR2/3; RVTRN is not required for
DDR3
If RVTRN=1 and bit QSTRN=0, when bit INIT=1 (triggering the init process) the read DQS
gate training algorithm still runs (as if bit QSTRN in DDRPHYC_PIR register was actually set
to 1).
If it is necessary to run only RV training stand-alone, with no read DQS gate training, you can
prevent the read DQS gate training from running by setting bit LBGDQS=1 in
DDRPHYC_PGCR register.
Note: RV training cannot use multi-purpose register (MPR) and must use the user data
programmed in DTDR0-1.
Bit 7 QSTRN: Read DQS training
Executes a PUBL training routine to determine the optimum position of the read data DQS
strobe for maximum system timing margins.
Note: Read DQS training cannot use multi-purpose register (MPR) and must use the user data
programmed in DTDR0-1.
Bit 6 DRAMINIT: DRAM initialization
Executes the DRAM initialization sequence
Bit 5 DRAMRST: DRAM reset (DDR3 only)
Issues a reset to the DRAM (by driving the DRAM reset pin low) and wait 200us.
This can be triggered in isolation or with the full DRAM initialization (DRAMINIT). For the
latter case, the reset is issued and 200us is waited before starting the full initialization
sequence.
Bit 4 ITMSRST: ITM reset
Soft resets the interface timing modules for the data and data strobes, i.e., it asserts the ITM
soft reset (srstb) signal.
Bit 3 ZCAL: Impedance calibration (Driver and ODT)
Performs PHY impedance calibration.
Bit 2 DLLLOCK: DLL lock
Waits for the PHY DLLs to lock.
Bit 1 DLLSRST: DLL soft reset
Soft resets all PHY DLLs by driving the DLL soft reset pin.
Note: - Requires that ctl_clk be toggling for the DLL soft reset signal to be output from the DLL.
If ctl_clk (AC DLL's cclk_0) is not guaranteed to be toggling, it is recommended to use
the manual DLL soft reset bit DLLSRST of DDRPHYC_ACDLLCR, and not bit
DLLSRST of DDRPHYC_PIR.
- Ensure that the minimum requirements for DLL bypass and DLL reset are observed
while asserting this bit.
Bit 0 INIT: Initialization trigger
A write of '1' to this bit triggers the DDR system initialization, including PHY initialization,
DRAM initialization, and PHY training.
The exact initialization steps to be executes are specified in bits 1 to 6 of this register. A bit
setting of 1 means the step is executed as part of the initialization sequence, while a setting
of ‘0’ means the step is bypassed.
The initialization trigger bit is self-clearing.
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DDR physical interface control (DDRPHYC)
7.7.3
DDRPHYC PHY global control register (DDRPHYC_PGCR)
Address offset: 0x008
26
25
24
23
22
21
20
19
18
17
16
ZKSEL[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IOLB
CKDV[1:0]
DFTLMT[1:0]
ITMDMD
LBDQSS
27
DQSCFG
LBGDQS
28
DFTCMP
29
PDDISDX
30
CKINV
31
LBMODE
Reset value: 0x0184 2E04
rw
rw
rw
rw
rw
rw
rw
RFSHDT[3:0]
rw
CKEN[2:0]
rw
rw
RANKEN[3:0]
DTOSEL[3:0]
rw
rw
rw
rw
rw
rw
IODDRM[1:0]
Bit 31 LBMODE: Loop back mode
Indicates if set that the PHY/PUB is in loopback mode
Bit 30 LBGDQS: Loop back DQS gating
Selects the DQS gating mode that should be used when the PHY is in loopback mode. Valid
values are:
0: DQS gate training is triggered on the PUB
1: DQS gate is set manually using software
Bit 29 LBDQSS: Loop back DQS shift
Selects how the read DQS is shifted during loopback to ensure that the read DQS is centered
into the read data eye. Valid values are:
0: PUB sets the read DQS delay to 0; DQS is already shifted 90 degrees by write path
1: The read DQS shift is set manually through software.
Bits 28:25 RFSHDT[3:0]: Refresh during training
A non-zero value specifies that a burst of refreshes equal to the number specified in this field
should be sent to the SDRAM after training each rank except the last rank.
Bit 24 PDDISDX: Power down disabled byte
Indicates if set that the DLL and I/Os of a disabled byte should be powered down.
Bits 23:22 ZKSEL[1:0]: Impedance clock divider selection
Selects the divide ratio for the clock used by the impedance control logic. The source clock
for
the divider is the configuration port clock signal (pclk), depending on which configuration port
type used (see “Impedance Calibration” on page tbc).
Valid values are:
00: Divide by 2
01: Divide by 8
10: Divide by 32
11: Divide by 64
Bits 21:18 RANKEN[3:0]: Rank enable
Specifies the ranks that are enabled for data-training.
only Bit 0 is used and controls rank 0.
Setting the bit to ‘1’ enables the rank, and setting it to ‘0’ disables the rank.
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Bits 17:16 IODDRM[1:0]: I/O DDR mode
Selects the DDR mode for the I/Os.
Bit 15
IOLB: I/O loop back select
Selects where inside the I/O the loop-back of signals happens. Not applicable to D3A I/Os.
Valid values are:
0: Loopback is after output buffer; output enable must be asserted
1: Loopback is before output buffer; output enable is don’t care
Bit 14 CKINV: CK invert
Specifies if set that CK/CK# should be inverted. Otherwise CK/CK# toggles with normal
polarity.
Bits 13:12 CKDV[1:0]: CK disable value
Specifies the static value that should be driven on CK/CK# pair(s) when the pair(s) is
disabled. CKDV[0] specifies the value for CK and CKDV[1] specifies the value for CK#.
Bits 11:9 CKEN[2:0]: CK enable
Controls whether the CK going to the SDRAM is enabled (toggling) or
disabled (static value defined by CKDV). One bit for each of the three CK pairs.
Bits 8:5 DTOSEL[3:0]: Digital test output select
Digital Test Output Select: Selects the PHY digital test output that should be driven
onto PHY digital test output (DDR_DTO0) pin: Valid values are:
0000: DATX8 0 DLL digital test output
0001: DATX8 1 DLL digital test output
0010: DATX8 2 DLL digital test output
0011: DATX8 3 DLL digital test output
0100: DATX8 4 DLL digital test output
0101: DATX8 5 DLL digital test output
0110: DATX8 6 DLL digital test output
0111: DATX8 7 DLL digital test output
1000: DATX8 8 DLL digital test output
1001: AC DLL digital test output
Other: Reserved
Bits 4:3 DFTLMT[1:0]: DQS drift limit
Specifies the expected limit of drift on read data strobes. A drift of this value or greater is
reported as a drift error through the host port error flag. Valid values are:
00: No limit (no error reported)
01: 90° drift
10: 180° drift
11: 270° or more drift
Note: Although reported through the error flag, this is not an error requiring any action. It is
simply an indicator that the drift is greater than expected.
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DDR physical interface control (DDRPHYC)
Bit 2 DFTCMP: DQS drift compensation
Enables or disables DQS drift compensation. Valid values are:
0: Disables data strobe drift compensation
1: Enables data strobe drift compensation
By default, drift compensation is enabled.
Note: Drift compensation is not supported under any of the following situations:
- LPDDR2/3 (bit DDRMD set to LPDDR2 in DDRPHYC_DCR register)
- Burst length 2 (bit BL in DDRPHYC_MR0 register set to burst length of 2)
- Read DQS gating using passive windowing (bit DQSCFG in DDRPHYC_PGCR
register set to passive windowing)
Drift compensation must be set to disabled if any of the above are set.
Bit 1 DQSCFG: DQS gating configuration
Selects one of the two DQS gating schemes:
0: DQS gating is shut off using the rising edge of DQS_b (active windowing mode)
1: DQS gating blankets the whole burst (passive windowing mode).
Note: Passive windowing must be used for LPDDR2/3.
Bit 0 ITMDMD: ITM DDR mode
Selects whether ITMS uses DQS and DQS# or it only uses DQS.
Valid values are:
0: ITMS uses DQS and DQS#
1: ITMS uses DQS only
Note: The correct setting is always DQS and DQS#.
7.7.4
DDRPHYC PHY global status register (DDRPHYC_PGSR)
Address offset: 0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TQ
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
RVEIRR
RVERR
DFTERR
DTIERR
DTERR
DTDONE
DIDONE
ZCDDONE
DLDONE
IDONE
Reset value: 0x0000 0000
r
r
r
r
r
r
r
r
r
r
r
Bit 31 TQ: Temperature output (LPDDR only) N/A
Bits 30:10 Reserved, must be kept at reset value.
Bit 9 RVEIRR: Read valid training intermittent error
If set, indicates that there was an intermittent error during read valid training, such as a pass
was followed by a fail then followed by another pass.
Bit 8 RVERR: Read valid training error
If set, indicates that a valid read valid placement could not be found during read valid training.
Bit 7 DFTERR: DQS drift error
If set, indicates that at least one of the read data strobes has drifted by more than or equal to
the drift limit set in the PHY General Configuration Register (PGCR).
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Bit 6 DTIERR: DQS gate training intermittent error
If set, indicates that there was an intermittent error during DQS gate training, such as a pass
was followed by a fail then followed by another pass.
Bit 5 DTERR: DQS gate training error
If set, indicates that a valid DQS gating window could not be found during DQS gate training.
Bit 4 DTDONE: Data training done
Indicates, if set, that the PHY has finished doing data training.
Bit 3 DIDONE: DRAM initialization done
Indicates if set that DRAM initialization has completed.
Bit 2 ZCDDONE: zcal done
Indicates if set that impedance calibration has completed.
Bit 1 DLDONE: DLL lock done
Indicates if set that DLL locking has completed.
Bit 0 IDONE: Initialization done
Indicates if set that the DDR system initialization has completed.
This bit is set after all the selected initialization routines in DDRPHYC_PIR register have
completed.
7.7.5
DDRPHYC DDR DLL global control register (DDRPHYC_DLLGCR)
Address offset: 0x010
Reset value: 0x0373 7000
28
27
26
FDTRMSL[1:0]
25
24
23
22
SBIAS5_3[2:0]
21
20
19
SBIAS2_0[2:0]
18
17
16
MBIAS[7:4]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ATC[1:0]
rw
rw
MBIAS[3:0]
rw
rw
rw
rw
rw
TESTEN
rw
15
TESTSW
DLLRSVD2[1:0]
29
BPS200
30
LOCKDE
T
31
DTC[2:0]
rw
rw
rw
rw
IPUMP[2:0]
rw
rw
DRES[1:0]
rw
rw
rw
Bits 31:30 DLLRSVD2[1:0]:
These bit are connected to the DLL control bus and reserved for future use.
Bit 29 LOCKDET: Master lock detect enable
Note: This field is only valid for a few processes. For all other processes this field is reserved.
Bits 28:27 FDTRMSL[1:0]: Slave bypass fixed delay trim
00: Nominal delay
01: Nominal delay – 10%
10: Nominal delay + 10%
11: Nominal delay + 20%
Bits 26:24 SBIAS5_3[2:0]: Slave bias trim
Used to trim the bias for the slave DLL.
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DDR physical interface control (DDRPHYC)
Bit 23 BPS200: Bypass mode frequency range
0: 0 to 100 MHz
1: 0 to 200 MHz
Bits 22:20 SBIAS2_0[2:0]: Slave bias trim
Used to trim the bias for the slave DLL.
Bits 19:12 MBIAS[7:0]: Master bias trim
Used to trim the bias for the master DLL.
Bit 11 TESTSW: Test switch
Selects the test signals of either the master DLL, set to 0, or the slave DLL, set to 1.
Bits 10:9 ATC[1:0]: Analog test control
Selects the analog signal to be output on the DLL analog test output (DDR_ATO) when
TESTEN is high (Output is Vss when TESTEN is low).
The test output either comes from the master DLL or the slave DLL, depending on the setting
of the test switch (TESTSW).
Both master DLL and slave DLL output similar analog test signals. Valid settings for analog
test control are:
00: Replica bias output for PMOS (Vbp)
01: Replica bias output for NMOS (Vbn)
10: Filter output (Vc)
11: VDDCORE
Bits 8:6 DTC[2:0]: Digital test control
Selects the digital signal to be output on the DLL digital test output (DTO1 pin) when TESTEN
is high (Output is '0' when TESTEN is low). The DTO0 pin output masters the DLL reference
clock (clk_0).
Valid settings for master DLL (such as, when TESTSW = '0'):
- 000: 0 output clock (clk_0)
- 001: 90 output clock (clk_90)
- 010: 180 output clock (clk_180)
- 011: 270 output clock (clk_270)
- 100: 360 internal clock (clk_360_int)
- 101: Speed-up pulse (spdup)
- 110: Slow-down pulse (slwdn)
- 111: 0 MCTL logic clock (cclk_0)
Valid settings for slave DLL (such as when TESTSW = '1'):
- 000: Input DQS strobe (dqs)
- 001: Input clock reference (clk_90_in)
- 010: Internal feedback clock (clk_0_out)
- 011: 90 output DQS# strobe (dqsb_90)
- 100: 90 output DQS strobe (dqs_90)
- 101: Speed-up pulse (spdup)
- 110: Slow-down pulse (slwdn)
- 111: Auto-lock enable signal
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RM0442
Bit 5 TESTEN: Test enable
Enables digital and analog test outputs selected by DTC and ATC respectively.
Bits 4:2 IPUMP[2:0]: Charge pump current trim
000: maximum current
111: minimum current
Bits 1:0 DRES[1:0]: Trim reference current versus resistor value variation
00: Rnom
01: Rnom - 20%
1x: Rnom + 20%
Note: For a few processes this field is reserved and is not used by the DLL.
7.7.6
DDRPHYC AC DLL control register (DDRPHYC_ACDLLCR)
Address offset: 0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DLLDIS
DLLSRST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ATESTEN
Reset value: 0x4000 0000
Res.
Res.
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
15
14
13
12
rw
Res.
Res.
Res.
Res.
MFWDLY[2:0]
rw
rw
MFBDLY[2:0]
rw
rw
Bit 31 DLLDIS: DLL disable
A disabled DLL is bypassed. By default DLL is enabled.
Note: DLL bypass must only be changed when DDRPHYC clock (dphy_ker_ck) is inactive.
Bit 30 DLLSRST: DLL soft reset
Soft resets the AC DLL by driving the DLL soft reset pin.
Note: DLL reset must only be changed to 0 when DDRPHYC clock (dphy_ker_ck) is inactive.
Bits 29:19 Reserved, must be kept at reset value.
Bit 18 ATESTEN: Analog test enable
Enables the analog test signal to be output on the DLL analog test output (ATO pin). The DLL
analog test output is tri-stated when this bit is '0'.
Bits 17:12 Reserved, must be kept at reset value.
Bits 11:9 MFWDLY[2:0]: Master DLL feed-forward delay trim
Used to trim the delay in the master DLL feed-forward path:
000: minimum delay
111: maximum delay
Bits 8:6 MFBDLY[2:0]: Master DLL feed-back delay trim
Used to trim the delay in the master DLL feed-back path:
000: minimum delay
111: maximum delay
Bits 5:0 Reserved, must be kept at reset value.
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DDR physical interface control (DDRPHYC)
7.7.7
DDRPHYC PT register 0 (DDRPHYC_PTR0)
Address offset: 0x018
Reset value: 0x0022 AF9B
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TDLLLOCK
[11:10]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TITMSRST[3:0]
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
TDLLLOCK[9:0]
rw
rw
TDLLSRST[5:0]
rw
rw
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:18 TITMSRST[3:0]: ITM soft reset
Number of configuration clock cycles that the ITM soft reset pin must remain asserted when
the soft reset is applied to the ITMs.
This must correspond to a value that is equal to or more than 8 controller clock cycles.
Default value corresponds to 8 controller clock cycles.
Bits 17:6 TDLLLOCK[11:0]: DLL lock time
Number of configuration clock cycles for the DLL to stabilize and lock, i.e. number of clock
cycles from when the DLL reset pin is de-asserted to when the DLL has locked and is ready
for use.
Default value corresponds to 5.12us at 533MHz.
Bits 5:0 TDLLSRST[5:0]: DLL soft reset
Number of configuration clock cycles that the DLL soft reset pin must remain asserted when
the soft reset is triggered through the PHY initialization register (DDRPHYC_PIR).
This must correspond to a value that is equal to or more than 50ns or 8 controller clock
cycles, whichever is bigger.
Default value corresponds to 50 ns at 533 MHz.
7.7.8
DDRPHYC PT register 1 (DDRPHYC_PTR1)
Address offset: 0x01C
Reset value: 0x0604 111D
31
30
29
28
27
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
26
25
24
23
22
21
20
19
18
TDINIT1[7:0]
rw
rw
10
9
17
16
TDINIT0[18:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
TDINIT0[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
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Bits 31:27 Reserved, must be kept at reset value.
Bits 26:19 TDINIT1[7:0]: tDINIT1
DRAM initialization time corresponding to the following:
DDR3 = CKE high time to first command (tRFC +10 ns or 5 tCK, whichever value is larger)
LPDDR2 = CKE low time with power and clock stable (100 ns)
LPDDR3 = CKE low time with power and clock stable (100 ns)
Default value corresponds to DDR3 360ns at 533MHz.
Bits 18:0 TDINIT0[18:0]: tDINIT0
DRAM initialization time corresponding to the following:
DDR3 = CKE low time with power and clock stable (500 us)
LPDDR2 = CKE high time to first command (200 us)
LPDDR3 = CKE high time to first command (200us)
Default value corresponds to DDR3 500 us at 533MHz.
7.7.9
DDRPHYC PT register 2 (DDRPHYC_PTR2)
Address offset: 0x020
Reset value: 0x042D A072
31
Res.
30
Res.
15
14
29
Res.
13
28
Res.
12
27
26
25
24
23
Res.
11
22
21
20
19
18
17
TDINIT3[9:0]
rw
rw
10
9
16
TDINIT
2[16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
TDINIT2[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:27 Reserved, must be kept at reset value.
Bits 26:17 TDINIT3[9:0]: tDINIT3
DRAM initialization time corresponding to the following:
LPDDR2 = Time from ZQ initialization command to first command (1 us)
LPDDR3 = Time from ZQ initialization command to first command (1us)
Default value corresponds to the LPDDR2/3 1 us at 533MHz.
Bits 16:0 TDINIT2[16:0]: tDINIT2
DRAM initialization time corresponding to the following:
DDR3 = Reset low time (200 us on power-up or 100 ns after power-up)
LPDDR2 = Time from reset command to end of auto initialization (1 us + 10 us = 11us)
LPDDR3 = Time from reset command to end of auto initialization (11us)
Default value corresponds to DDR3 200 us at 533MHz
382/3930
RM0442 Rev 7
RM0442
DDR physical interface control (DDRPHYC)
7.7.10
DDRPHYC ACIOC register (DDRPHYC_ACIOCR)
Address offset: 0x024
28
27
26
25
24
23
22
21
20
19
18
17
16
ACSR[1:0]
RSTODT
Res.
Res.
Res.
RANKPDR
Res.
Res.
Res.
CSPDD
Res.
Res.
9
8
7
5
4
3
2
1
0
ACPDR
ACPDD
ACODT
ACOE
ACIOM
rw
rw
rw
rw
rw
RSTPDD
29
RSTPDR
31
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
Res.
RANKODT
30
RSTIOM
Reset value: 0x3040 0812
rw
CKPDR[2:0]
rw
rw
rw
CKPDD[2:0]
rw
rw
rw
6
rw
CKODT[2:0]
rw
rw
rw
rw
Bits 31:30 ACSR[1:0]: AC slew rate
Selects slew rate of the I/O for all address and command pins.
Bit 29 RSTIOM: Reset I/O mode
Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for SDRAM
Reset.
Bit 28 RSTPDR: RST pin power down receiver
Powers down, when set, the input receiver on the I/O for SDRAM RST# pin.
Bit 27 RSTPDD: RST pin power down driver
Powers down, when set, the output driver on the I/O for SDRAM RST# pin.
Bit 26 RSTODT: RST pin ODT
Enables, when set, the on-die termination on the I/O for SDRAM RST# pin.
Bits 25:23 Reserved, must be kept at reset value.
Bit 22 RANKPDR: Rank power down receiver
Powers down, when set, the input receiver on the I/O CKE, ODT, and CS# pins.
Only RANKPDR[0] is used for single rank
Bits 21:19 Reserved, must be kept at reset value.
Bit 18 CSPDD: CS power down driver
Powers down, when set, the output driver on the I/O for CS# pins.
Only PDD[0] is used for single rank.
CKE and ODT driver power down is controlled by DSGCR register.
Bits 17:15 Reserved, must be kept at reset value.
Bit 14 RANKODT: Rank ODT
Enables, when set, the on-die termination on the I/O for CKE, ODT, and CS# pins.
Bits 13:11 CKPDR[2:0]: CK pin power down receiver
Powers down, when set, the input receiver on the I/O for CK[0], CK[1], and CK[2] pins,
respectively
Bits 10:8 CKPDD[2:0]: CK pin power down driver
Powers down, when set, the output driver on the I/O for CK[0], CK[1], and CK[2] pins,
respectively.
RM0442 Rev 7
383/3930
420
DDR physical interface control (DDRPHYC)
RM0442
Bits 7:5 CKODT[2:0]: CK pin ODT
Enables, when set, the on-die termination on the I/O for CK[0], CK[1], and CK[2] pins,
respectively.
Bit 4 ACPDR: AC pins power down receivers
Powers down, when set, the input receiver on the I/O for RAS#, CAS#, WE#, BA[2:0], and
A[15:0] pins.
Bit 3 ACPDD: AC pins power down drivers
Powers down, when set, the output driver on the I/O for RAS#, CAS#, WE#, BA[2:0], and
A[15:0] pins
Bit 2 ACODT: AC pins ODT
Enables, when set, the on-die termination on the I/O for RAS#, CAS#, WE#, BA[2:0], and
A[15:0] pins
Bit 1 ACOE: AC pins output enable
Enables, when set, the output driver on the I/O for all address and command pins
Bit 0 ACIOM: AC pins I/O mode
Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for all address
and command pins,
7.7.11
DDRPHYC DXCC register (DDRPHYC_DXCCR)
Address offset: 0x028
Reset value: 0x0000 0800
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AWDT
DQSNRST
Res.
Res.
rw
rw
11
10
9
8
7
DQSNRES[3:0]
rw
rw
rw
6
5
4
DQSRES[3:0]
rw
rw
rw
rw
rw
3
2
1
0
DXODT
12
DXIOM
13
DXPDD
14
DXPDR
15
RVSEL
rw
rw
rw
rw
rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 AWDT: Active window data train
Indicates if set that data training (DQS gate training and read valid training) should be
performed with active DQS gate window.
This is just for debug purposes.
The default is to perform training with passive windowing.
Bit 15 RVSEL: ITMD read valid select
Selects the scheme used for ITMD read valid. Valid values are:
0: ITMD read valid signal is generated by delayed DFI read enable signal.
1: ITMD read valid is generated by the ITMD itself using asynchronous crossing.
Bit 14 DQSNRST: DQS reset
Indicates, if set, that the ITMS of DQS# should always be put in reset such that its output
enable is always '1' and its data output is always '0'.
This is done by driving the oe_set_b and do_rst_b pins of this ITMS to '0' in order to force the
unused DQS# PAD to a known state of '0' in applications that don't use DQS#.
384/3930
RM0442 Rev 7
RM0442
DDR physical interface control (DDRPHYC)
Bits 13:12 Reserved, must be kept at reset value.
Bits 11:8 DQSNRES[3:0]: DQS# resistor
Selects the on-die pull-up/pull-down resistor for DQS# pins. Same encoding as DQSRES.
Note: DQS# resistor must be connected for LPDDR2.
Bits 7:4 DQSRES[3:0]: DQS resistor
Selects the on-die pull-down/pull-up resistor for DQS pins.
DQSRES[3] selects pull-down (when set to 0) or pull-up (when set to 1).
DQSRES[2:0] selects the resistor value as follows:
000: Open: On-die resistor disconnected
001: 688 Ω
010: 611 Ω
011: 550 Ω
100: 500 Ω
101: 458 Ω
110: 393 Ω
111: 344 Ω
Note: DQS resistor must be connected for LPDDR2
Bit 3 DXPDR: Data power down receiver
Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of all
DATX8 macros. It also powers down the PDQSR cell of all DAXT8 macros. This bit is ORed
with the PDR and DQSRPD configuration bits of the individual DATX8
Bit 2 DXPDD: Data power down driver
Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of all
DATX8 macros. This bit is ORed with the PDD configuration bit of the individual DATX8.
Bit 1 DXIOM: Data I/O mode
Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM,
and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the IOM configuration bit of
the individual DATX8.
Bit 0 DXODT: Data on die termination
Enables, when set, the on-die termination on the I/O for DQ, DM, and DQS/DQS# pins of all
DATX8 macros. This bit is ORed with the ODT configuration bit of the individual DATX8.
7.7.12
DDRPHYC DSGC register (DDRPHYC_DSGCR)
Address offset: 0x02C
26
25
24
23
22
21
20
19
18
17
16
CKEOE
ODTOE
CKOE
TPDOE
Res.
Res.
Res.
ODTPDD
Res.
Res.
Res.
CKEPDD
7
6
5
4
3
2
1
0
LPDLLPD
LPIOPD
ZUEN
BDISEN
PUREN
rw
rw
rw
rw
rw
NL2PD
27
NL2OE
28
TPDPD
29
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
Res.
Res.
Res.
NOBUB
30
FXDLAT
31
RSTOE
Reset value: 0xFA00 001F
rw
rw
rw
DQSGE[2:0]
rw
rw
DQSGX[2:0]
rw
rw
RM0442 Rev 7
rw
rw
rw
385/3930
420
DDR physical interface control (DDRPHYC)
RM0442
Bit 31 CKEOE: CKE output enable
Sets the output driver on the I/O for SDRAM CKE pins.
Bit 30 RSTOE: RST output enable
Enables, when set, the output driver on the I/O for SDRAM RST# pin
Bit 29 ODTOE: ODT output enable
Enables, when set, the output driver on the I/O for SDRAM ODT pins.
Bit 28 CKOE: CK output enable
Enables, when set, the output driver on the I/O for SDRAM CK/CK# pins.
Bit 27 TPDOE: TPD output enable (N/A LPDDR only)
Bit 26 TPDPD: TPD power down driver (N/A LPDDR only)
Bit 25 NL2OE: Non LPDDR2 output enable
Enables, when set, the output driver on the I/O for non-LPDDR2/LPDDR3 (ODT, RAS#,
CAS#, WE#, and BA) pins.
This may be used when a chip that is designed for both LPDDR2/LPDDR3 and other DDR
modes is being used in LPDDR2/LPDDR3 mode.
For these pins, the I/O output enable signal (OE) is an AND of this bit and the respective
output enable bit in ACIOCR or DSGCR registers.
Bit 24 NL2PD: Non LPDDR2 power down
Powers down, when set, the output driver and the input receiver on the I/O for nonLPDDR2/LPDDR3 (ODT, RAS#, CAS#, WE#, and BA) pins.
This may be used when a chip that is designed for both LPDDR2/LPDDR3 and other DDR
modes is being used in LPDDR2/LPDDR3 mode.
For these pins, the I/O power down signal (PDD or PDR) is an OR of this bit and the
respective power-down bit in ACIOCR register.
Bits 23:21 Reserved, must be kept at reset value.
Bit 20 ODTPDD: ODT power down driver
Powers down, when set, the output driver on the I/O for ODT pin.
Bits 19:17 Reserved, must be kept at reset value.
Bit 16 CKEPDD: CKE power down driver
Powers down, when set, the output driver on the I/O for CKE pin.
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 FXDLAT: Fixed latency
Specified whether all reads should be returned to the controller with a fixed read latency.
Enabling fixed read latency increases the read latency. Valid values are:
0: Disable fixed read latency
1: Enable fixed read latency
Bit 11 NOBUB: No bubble
Specified whether reads should be returned to the controller with no bubbles. Enabling nobubble reads increases the read latency. Valid values are:
0: Bubbles are allowed during reads
1: Bubbles are not allowed during reads
386/3930
RM0442 Rev 7
RM0442
DDR physical interface control (DDRPHYC)
Bits 10:8 DQSGE[2:0]: DQS gate early
Specifies the number of clock cycles for which the DQS gating must be enable dearlier than
its normal position. Only applicable when using PDQSR I/O cell, passive DQS gating and no
drift compensation.
This field is recommended to be set to zero for all DDR types other than LPDDR2/LPDDR3.
For LPDDR2/LPDDR3 it should be set to (tDQSCKmax - tDQSCKmin) divide by clock period
and rounded up. tDQSCKmax and tDQSCKmin can be found in the LPDDR/LPDDR2 vendor
datasheet.
Bits 7:5 DQSGX[2:0]: DQS gate extension
Specifies the number of clock cycles for which the DQS gating must be extended beyond the
normal burst length width. Only applicable when using PDQSR I/O cell, passive DQS gating
and no drift compensation.
This field is recommended to be set to zero for all DDR types other than LPDDR2/LPDDR3.
For LPDDR2/LPDDR3 it should be set to (tDQSCKmax- tDQSCKmin) divide by clock period
and rounded up. tDQSCKmax and tDQSCKmin can be found in the LPDDR2 vendor
datasheet.
Bit 4 LPDLLPD: Low power DLL power down
Specifies if set that the PHY should respond to the DFI low power opportunity request and
power down the DLL of the PHY if the wakeup time request satisfies the DLL lock time.
For more information on requirements when enabling and disabling the DLL, refer to “bypass
mode register control”
Bit 3 LPIOPD: Low power I/O power down
Specifies if set that the PHY should respond to the DFI low power opportunity request and
power down the I/Os of the PHY.
Bit 2 ZUEN: zcal on DFI update request
Specifies if set that the PHY should perform impedance calibration (update) whenever there
is a controller initiated DFI update request. Otherwise the PHY ignores an update request
from the controller.
Bit 1 BDISEN: Byte disable enable
Specifies if set that the PHY should respond to DFI byte disable request. Otherwise the byte
disable from the DFI is ignored in which case bytes can only be disabled using the DXnGCR
register
Bit 0 PUREN: PHY update request enable
Specifies if set, that the PHY should issue PHY initiated DFI update request when there is
DQS drift of more than ¾ of a clock cycle within one continuous (back-to-back) read burst.
By default the PHY issues PHY initiated update requests and the controller should respond
otherwise the PHY may return erroneous values.
The option to disable it is provided only for silicon evaluation and testing.
RM0442 Rev 7
387/3930
420
DDR physical interface control (DDRPHYC)
7.7.13
RM0442
DDRPHYC DC register (DDRPHYC_DCR)
Address offset: 0x030
27
26
25
24
23
22
21
20
19
18
17
16
TPD
UDIMM
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
15
14
13
12
11
10
Res.
Res.
Res.
Res.
Res.
Res.
DDRTYPE[1:0]
rw
rw
rw
DDR8BNK
28
MPRDQ
29
NOSRA
30
DDR2T
31
RDIMM
Reset value: 0x0000 000B
PDQ[2:0]
rw
rw
rw
rw
DDRMD[2:0]
rw
rw
rw
Bit 31 TPD: Test power down (N/A LPDDR only)
If set it places the DRAM in deep power down mode.
Bit 30 RDIMM: Registered DIMM
Indicates if set that a registered DIMM is used. In this case, the PUBL increases the SDRAM
write and read latencies (WL/RL) by 1.
This only applies to PUBL internal SDRAM transactions. Transactions generated by the
controller must make its own adjustments to WL/RL when using a registered DIMM
Bit 29 UDIMM: Unbuffered DIMM
Indicates if set that there is address mirroring on the second rank of an un-buffered DIMM
(the rank connected to CS#[1]).
In this case, the PUBL re-scrambles the bank and address when sending mode register
commands to the second rank.
This only applies to PUBL internal SDRAM transactions. Transactions generated by the
controller must make its own adjustments when using an un-buffered DIMM. DCR[NOSRA]
must be set if address mirroring is enabled.
Bit 28 DDR2T: 2T timing
Indicates if set that 2T timing should be used by PUB internally generated SDRAM
transactions.
Bit 27 NOSRA: No simultaneous rank access
Specifies if set that simultaneous rank access on the same clock cycle is not allowed. This
means that multiple chip select signals should not be asserted at the same time. This may be
required on some DIMM systems.
Bits 26:10 Reserved, must be kept at reset value.
Bits 9:8 DDRTYPE[1:0]: DDR type (LPDDR2 S4)
Selects the DDR type for the specified LPDDR mode.
Valid values for LPDDR2 are:
00: LPDDR2-S4
01: LPDDR2-S2
Others: Reserved
388/3930
RM0442 Rev 7
RM0442
DDR physical interface control (DDRPHYC)
Bit 7 MPRDQ: MPR DQ
Specifies the value that is driven on non-primary DQ pins during MPR reads.
Valid values are:
0: Primary DQ drives out the data from MPR (0-1-0-1); non-primary DQs drive ‘0’
1: Primary DQ and non-primary DQs all drive the same data from MPR (0-1-0-1)
Bits 6:4 PDQ[2:0]: Primary DQ(DDR3 Only)
Specifies the DQ pin in a byte that is designated as a primary pin for Multi-Purpose Register
(MPR) reads. Valid values are 0 to 7 for DQ[0] to DQ[7], respectively
Bit 3 DDR8BNK: DDR 8 banks
Indicates if set that the SDRAM used has 8 banks. tRPA = tRP+1 and tFAW are used for 8bank DRAMs, other tRPA = tRP and no tFAW is used.
Note: A setting of 1 for DRAMs that have fewer than 8 banks still results in correct functionality
but less tighter DRAM command spacing for the parameters described here.
Bits 2:0 DDRMD[2:0]: SDRAM DDR mode
011: DDR3
100: LPDDR2 (Mobile DDR2)
101: LPDDR3 (Mobile DDR3)
Others: Reserved
7.7.14
DDRPHYC DTP register 0 (DDRPHYC_DTPR0)
Address offset: 0x034
Reset value: 0x3092 666E
31
30
29
TCCD
28
27
26
25
24
TRC[5:0]
23
22
21
20
19
TRRD[3:0]
18
17
16
TRAS[4:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
TRCD[3:0]
rw
TRP[3:0]
rw
TWTR[2:0]
rw
TRTP[2:0]
rw
TMRD[1:0]
rw
Bit 31 TCCD: tCCDRead to read and write to write command delay
0: BL/2 for DDR2 and 4 for DDR3
1: BL/2 + 1 for DDR2 and 5 for DDR3
Bits 30:25 TRC[5:0]: tRC
Activate to activate command delay (same bank). Valid values are 2 to 42.
Bits 24:21 TRRD[3:0]: tRRD
Activate to activate command delay (different banks). Valid values are 1 to 8.
Bits 20:16 TRAS[4:0]: tRAS
Activate to precharge command delay. Valid values are 2 to 31.
Bits 15:12 TRCD[3:0]: tRCD
Activate to read or write delay. Minimum time from when an activate command is issued to
when a read or write to the activated row can be issued. Valid values are 2 to 11.
RM0442 Rev 7
389/3930
420
DDR physical interface control (DDRPHYC)
RM0442
Bits 11:8 TRP[3:0]: tRP
Precharge command period: The minimum time between a precharge command and any
other command.
Note: Note that the controller automatically derives tRPA for 8-bank DDR2 devices by adding
1 to tRP. Valid values are 2 to 11.
Bits 7:5 TWTR[2:0]: tWTR
Internal write to read command delay. Valid values are 1 to 6.
Bits 4:2 TRTP[2:0]: tRTP
Internal read to precharge command delay. Valid values are 2 to 6. Note that even though
RTP does not apply to JEDEC DDR devices, this parameter must still be set to a minimum
value of 2 for DDR because the Controller always uses the DDR2 equation, AL + BL/2 +
max(RTP,2) – 2, to compute the read to precharge timing (which is BL/2 for JEDEC DDR).
Bits 1:0 TMRD[1:0]: tMRD
Load mode cycle time: The minimum time between a load mode register command and any
other command.
For DDR3 this is the minimum time between two load mode register commands.
For DDR3, the value used for tMRD is 4 plus the value programmed in these bits, i.e. tMRD
value for DDR3 ranges from 4 to 7.
For LPDDR3, the value used for tMRD is 8 plus the value programmed in these bits.
7.7.15
DDRPHYC DTP register 1 (DDRPHYC_DTPR1)
Address offset: 0x038
31
30
29
Res.
Res.
TDQSCKMAX[2:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
Res.
Res.
Res.
Res.
TRTOD
T
Reset value: 0x0983 0090
28
27
26
25
24
23
22
21
TMOD[1:0]
rw
rw
TDQSCKMIN[2:0]
rw
20
19
18
17
16
rw
rw
rw
rw
3
2
1
0
TRFC[7:0]
TFAW[5:0]
rw
rw
rw
rw
TRTW
rw
rw
rw
TAOND[1:0]
rw
rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:27 TDQSCKMAX[2:0]: tDQSCKmax
Maximum DQS output access time from CK/CK# (LPDDR2 only).
This value is used for implementing read-to-write spacing. Valid values are 1 to 7.
Bits 26:24 TDQSCKMIN[2:0]: tDQSCKmin
DQS output access time from CK/CK# (LPDDR2/3 only).
This value is used for computing the read latency. Valid values are 0 to 7.
This value is derived from the corresponding parameter in the SDRAM datasheet divided by
the clock cycle time without rounding up.
The fractional remainder is automatically adjusted for by data training in quarter clock cycle
units.
If data training is not performed then this fractional remainder must be converted to quarter
clock cycle units and the gating registers (DXnDQSTR) adjusted accordingly.
390/3930
RM0442 Rev 7
RM0442
DDR physical interface control (DDRPHYC)
Bits 23:16 TRFC[7:0]: tRFC
Refresh-to-Refresh: Indicates the minimum time, in clock cycles, between two refresh
commands or between a refresh and an active command. This is derived from the minimum
refresh interval from the datasheet, tRFC(min), divided by the clock cycle time.
The default number of clock cycles is for the largest JEDEC tRFC(min parameter value
supported.
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 TRTODT: tRTODT
Read to ODT delay (DDR3 only). Specifies whether ODT can be enabled immediately after
the read post-amble or one clock delay has to be added.
Valid values are:
0: ODT may be turned on immediately after read post-amble
1: ODT may not be turned on until one clock after the read post-amble
If tRTODT is set to 1, then the read-to-write latency is increased by 1 if ODT is enabled.
Bits 10:9 TMOD[1:0]: tMOD
Load mode update delay (DDR3 only). The minimum time between a load mode register
command and a non-load mode register command.
Valid values are:
00: 12
01: 13
10: 14
11: 15
Bits 8:3 TFAW[5:0]: tFAW
4-bank activate period. No more than 4-bank activate commands may be issued in a given
tFAW period. Only applies to 8-bank devices.
Valid values are 2 to 31.
Bit 2 TRTW: tRTW
Read to Write command delay.
Valid values are:
0: standard bus turn around delay
1: add 1 clock to standard bus turn around delay
This parameter allows the user to increase the delay between issuing Write commands to the
SDRAM when preceded by Read commands. This provides an option to increase bus turnaround margin for high frequency systems.
Bits 1:0 TAOND[1:0]: tAOND/tAOFD
ODT turn-on/turn-off delays (DDR2 only). The delays are in clock cycles.
Valid values are:
00: 2/2.5
01: 3/3.5
10: 4/4.5
11: 5/5.5
Most DDR2 devices utilize a fixed value of 2/2.5. For non-standard SDRAMs, the
user must ensure that the operational Write Latency is always greater than or equal
to the ODT turn-on delay. For example, a DDR2 SDRAM with CAS latency set to 3
and CAS additive latency set to 0 has a Write Latency of 2. Thus 2/2.5 can be used,
but not 3/3.5 or higher.
RM0442 Rev 7
391/3930
420
DDR physical interface control (DDRPHYC)
7.7.16
RM0442
DDRPHYC DTP register 2 (DDRPHYC_DTPR2)
Address offset: 0x03C
Reset value: 0x1001 A0C8
31
30
29
Res.
Res.
Res.
15
14
13
TCKE
[0]
28
27
26
25
24
23
22
rw
rw
20
19
18
17
16
TCKE[3:1]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
TXP[4:0]
rw
21
TDLLK[9:0]
rw
TXS[9:0]
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:29 Reserved, must be kept at reset value.
Bits 28:19 TDLLK[9:0]: tDLLK
DLL locking time. Valid values are 2 to 1023.
Bits 18:15 TCKE[3:0]: tCKE
CKE minimum pulse width. Also specifies the minimum time that the SDRAM must remain in
power down or self refresh mode. For DDR3 this parameter must be set to the value of
tCKESR which is usually bigger than the value of tCKE. Valid values are 2 to 15.
Bits 14:10 TXP[4:0]: tXP
Power down exit delay. The minimum time between a power down exit command and any
other command. This parameter must be set to the maximum of the various minimum power
down exit delay parameters specified in the SDRAM datasheet, i.e. max(tXP, tXARD,
tXARDS) for DDR2 and max(tXP, tXPDLL) for DDR3. Valid values are 2 to 31.
Bits 9:0 TXS[9:0]: tXS
Self refresh exit delay. The minimum time between a self refresh exit command and any
other command. This parameter must be set to the maximum of the various minimum self
refresh exit delay parameters specified in the SDRAM datasheet, i.e. max(tXSNR, tXSRD)
for DDR2 and max(tXS, tXSDLL) for DDR3. Valid values are 2 to 1023.
7.7.17
DDRPHYC MR0 register for DDR3 (DDRPHYC_DDR3_MR0)
Address offset: 0x040
Reset value: 0x0A52
15
14
13
RSVD[2:0]
rw
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12
11
PD
rw
rw
10
9
WR[2:0]
rw
rw
rw
8
7
DR
TM
rw
rw
RM0442 Rev 7
6
5
4
CL[3:1]
rw
rw
rw
3
2
BT
CL0
rw
rw
1
0
BL[1:0]
rw
rw
RM0442
DDR physical interface control (DDRPHYC)
Bits 15:13 RSVD[2:0]: JEDEC reserved.
Bit 12 PD: Power-down control
Controls the exit time for power-down modes. Refer to SDRAM datasheet for details on
power-down modes. Valid values are:
0: Slow exit (DLL off)
1: Fast exit (DLL on)
Bits 11:9 WR[2:0]: Write recovery
This is the value of the write recovery in clock cycles. It is calculated by dividing the data
sheet write recovery time, tWR (ns) by the data sheet clock cycle time, tCK (ns) and rounding
up a non-integer value to the next integer.
Valid values are:
001: 5
010: 6
011: 7
100: 8
101: 10
110: 12
All other settings are reserved and should not be used.
Note: tWR (ns) is the time from the first SDRAM positive clock edge after the last data-in pair
of a write command, to when a precharge of the same bank can be issued.
Bit 8 DR: DLL reset (autoclear)
Writing a ‘1’ to this bit resets the SDRAM DLL. This bit is self clearing,
i.e. it returns back to ‘0’ after the DLL reset has been issued.
Bit 7 TM: Operating mode
Selects either normal operating mode (0) or test mode (1). Test mode is reserved for the
manufacturer and should not be used.
Bit 3 BT: Burst type
Indicates whether a burst is sequential (0) or interleaved (1).
Bits 6, 5, 4, 2 CL[3:0]: CAS latency
The delay, in clock cycles, between when the SDRAM registers a read command to when
data is available.
Valid values for CL[3:0] are:
0010: 5
0100: 6
0110: 7
1000: 8
1010: 9
1100: 10
1110: 11
Others: Reserved
Bits 1:0 BL[1:0]: Burst length
Determines the maximum number of column locations that can be accessed during a given
read or write command.
Valid values for DDR3 are:
00: 8 (Fixed)
01: 4 or 8 (On the fly)
10: 4 (Fixed)
11: Reserved
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DDR physical interface control (DDRPHYC)
7.7.18
RM0442
DDRPHYC MR1 register for DDR3 (DDRPHYC_DDR3_MR1)
Address offset: 0x044
15
14
13
12
11
10
9
8
7
6
5
Res.
Res.
Res.
QOFF
TDQS
Res.
RTT2
Res.
LEVEL
Reset value: 0x0000
RTT1
DIC1
rw
rw
rw
rw
rw
rw
4
3
AL[1:0]
rw
rw
2
1
0
RTT0
DIC0
DE
rw
rw
rw
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 QOFF: Output enable/disable
0: all outputs function as normal
1: all SDRAM outputs are disabled removing output buffer current.
This feature is intended to be used for IDD characterization of read current and should not be
used in normal operation.
Bit 11 TDQS: Termination data strobe
When enabled (‘1’) TDQS provides additional termination resistance outputs that may be
useful in some system configurations. (N/A)
Bit 10 Reserved, must be kept at reset value.
Bit 8 Reserved, must be kept at reset value.
Bit 7 LEVEL: Write leveling enable (N/A)
Bits 4:3 AL[1:0]: Posted CAS Additive Latency:
Setting additive latency that allows read and write commands to be issued to the SDRAM
earlier than normal (refer to SDRAM datasheet for details). Valid values are:
00: 0 (AL disabled)
01: CL - 1
10: CL - 2
11: Reserved
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DDR physical interface control (DDRPHYC)
Bits 9, 6, 2 RTT[2:0]: On die termination
Selects the effective resistance for SDRAM on die termination.
Valid values for {RTT2,RTT1,RTT0} are:
000: ODT disabled
001: RZQ/4
010: RZQ/2
011: RZQ/6
100: RZQ/12
101: RZQ/8
Others: Reserved
Bits 5, 1 DIC[1:0]: Output driver impedance control
Controls the output drive strength.
Valid values for {DIC1,DIC0} are:
00: RZQ/6
01: RZQ/7
10: Reserved
11: Reserved
Bit 0 DE: DLL enable/disable
Enable (0) or disable (1) the DLL.
DLL must be enabled for normal operation.
7.7.19
DDRPHYC MR1 register for LPDDR2 [alternate]
(DDRPHYC_LPDDR2_MR1)
Address offset: 0x044
Reset value: 0x0000
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
NWR[2:0]
rw
rw
rw
4
3
WC
BT
rw
rw
2
1
0
BL[2:0]
rw
rw
rw
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:5 NWR[2:0]: Write recovery
001: nWR=3
100: nWR=6
110: nWR=8
111: nWR=9
Others: Reserved
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RM0442
Bit 4 WC: Wrap control
0: wrap
1: no wrap
Bit 3 BT: Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). ,
Bits 2:0 BL[2:0]: Burst length
Determines the maximum number of column locations that can be accessed during a given
read or write command. Valid values are:
010: 4
011: 8
100: 16
Others: Reserved
7.7.20
DDRPHYC MR1 register for LPDDR3 [alternate]
(DDRPHYC_LPDDR3_MR1)
Address offset: 0x044
Reset value: 0x0000
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
NWR[2:0]
rw
rw
rw
4
3
Res.
Res.
2
1
0
BL[2:0]
rw
rw
rw
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:5 NWR[2:0]: Write recovery
If nWRE (MR2 [4]) = 0:
- 001: nWR=3
- 100: nWR=6
- 110: nWR=8
- 111: nWR=9
If nWRE (MR2[4]) = 1:
- 000: nWR=10
- 001: nWR=11
- 010: nWR=12
Others: Reserved
Bits 4:3 Reserved, must be kept at reset value.
Bits 2:0 BL[2:0]: Burst length
Determines the maximum number of column locations that can be accessed during a given
read or write command.
011: 8
Others: Reserved
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DDR physical interface control (DDRPHYC)
7.7.21
DDRPHYC MR2 register for DDR3 (DDRPHYC_DDR3_MR2)
Address offset: 0x048
Reset value: 0x0000
15
14
13
12
11
10
Res.
Res.
Res.
Res.
Res.
RTTWR[1:0]
rw
9
8
7
6
Res.
SRT
ASR
rw
rw
rw
5
4
3
2
CWL[2:0]
rw
rw
1
0
PASR[2:0]
rw
rw
rw
rw
Bits 15:11 Reserved, must be kept at reset value.
Bits 10:9 RTTWR[1:0]: Dynamic ODT
Selects RTT for dynamic ODT.
00: Dynamic ODT off
01: RZQ/4
10: RZQ/2
11: Reserved
Bit 8 Reserved, must be kept at reset value.
Bit 7 SRT: Self-refresh temperature range
Selects either normal (‘0’) or extended (‘1’) operating temperature range during self-refresh.
Bit 6 ASR: Auto self-refresh
When enabled (‘1’), SDRAM automatically provides self-refresh power management
functions for all supported operating temperature values.
Otherwise the SRT bit must be programmed to indicate the temperature range.
Bits 5:3 CWL[2:0]: CAS write latency
The delay, in clock cycles, between when the SDRAM registers a write command to when
write data is available.
000: 5 (tCK = 2.5ns)
001: 6 (2.5ns > tCK = 1.875ns)
010: 7 (1.875ns > tCK = 1.5ns)
011: 8 (1.5ns > tCK = 1.25ns)
Others: Reserved
Bits 2:0 PASR[2:0]: Partial array self-refresh
Specifies that data located in areas of the array beyond the specified location are lost if self
refresh is entered.
Valid settings for 8 banks are:
000: Full Array
001: Half Array (BA[2:0] = 000, 001, 010 & 011)
010: Quarter Array (BA[2:0] = 000, 001)
011: 1/8 Array (BA[2:0] = 000)
100: 3/4 Array (BA[2:0] = 010, 011, 100, 101, 110 & 111)
101: Half Array (BA[2:0] = 100, 101, 110 & 111)
110: Quarter Array (BA[2:0] = 110 & 111)
111: 1/8 Array (BA[2:0] 111)
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7.7.22
RM0442
DDRPHYC MR2 register for LPDDR2 [alternate]
(DDRPHYC_LPDDR2_MR2)
Address offset: 0x048
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
2
1
0
RLWL[2:0]
rw
rw
rw
2
1
0
Bits 15:3 Reserved, must be kept at reset value.
Bits 2:0 RLWL[2:0]: Read and write latency
001: RL = 3 /WL = 1
010: RL = 4 / WL = 2
011: RL = 5 / WL = 2
100: RL = 6 / WL = 3
101: RL = 7 / WL = 4
110: RL = 8 / WL = 4
Others: Reserved
7.7.23
DDRPHYC MR2 register for LPDDR3 [alternate]
(DDRPHYC_LPDDR3_MR2)
Address offset: 0x048
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WR
WL
Res.
NWRE
Res.
rw
rw
rw
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 WR: New for LPDDR3 (not used by this PHY, leave at zero)
Bit 6 WL: New for LPDDR3 (not used by this PHY, leave at zero)
Bit 5 Reserved, must be kept at reset value.
Bit 4 NWRE: New for LPDDR3 (not used by this PHY, leave at zero)
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 RLWL[2:0]: Read and write latency
001: RL = 3 /WL = 1
010: RL = 4 / WL = 2
011: RL = 5 / WL = 2
100: RL = 6 / WL = 3
101: RL = 7 / WL = 4
110: RL = 8 / WL = 4
Others: Reserved
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RLWL[2:0]
rw
rw
rw
RM0442
DDR physical interface control (DDRPHYC)
7.7.24
DDRPHYC MR3 register for DDR3 (DDRPHYC_DDR3_MR3)
Address offset: 0x04C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MPR
MPRLOC[1:0]
rw
rw
rw
Bits 31:3 Reserved, must be kept at reset value.
Bit 2 MPR: Multi-purpose register enable
Enables, if set, that read data should come from the Multi-Purpose Register. Otherwise read
data come from the DRAM array.
Bits 1:0 MPRLOC[1:0]: Multi-purpose register (MPR) location
Selects MPR data location.
00: Predefined pattern for system calibration
Others: Reserved
7.7.25
DDRPHYC MR3 register for LPDDR2 [alternate]
(DDRPHYC_LPDDR2_MR3)
Address offset: 0x04C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
3
2
1
0
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DS[3:0]
rw
rw
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 DS[3:0]: Drive strength
Valid values are:
0000: Reserved
0001: 34.3 Ω typical
0010: 40 Ω typical
0011: 48 Ω typical
0100: 60 Ω typical
0101: Reserved
0110: 80 Ω typical
0111: 120 Ω typical
Others: Reserved
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DDR physical interface control (DDRPHYC)
7.7.26
RM0442
DDRPHYC MR3 register for LPDDR3 [alternate]
(DDRPHYC_LPDDR3_MR3)
Address offset: 0x04C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PDCTL[1:0]
DQ[1:0]
rw
rw
rw
rw
19
18
17
16
WROD
T
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:2 PDCTL[1:0]: Power-down control
00: ODT disabled by DRAM during power-down
01: ODT enabled by DRAM during power-down
Others: Reserved
Bits 1:0
7.7.27
DQ[1:0]: ODT on-die termination
00: Disable (default)
01: Rzq/4 (see note)
10: Rzq/2
11: Rzq/1
Note: Rzq/4 is optional for LPDDR3-1066 devices.
DDRPHYC ODTC register (DDRPHYC_ODTCR)
Address offset: 0x050
Reset value: 0x0001 0000
31
30
29
28
27
26
25
24
23
22
21
20
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
RDOD
T
rw
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 WRODT:
Specifies whether ODT should be enabled (‘1’) or disabled (‘0’) on write
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 RDODT:
Specifies whether ODT should be enabled (‘1’) or disabled (‘0’) on read
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DDR physical interface control (DDRPHYC)
7.7.28
DDRPHYC DTA register (DDRPHYC_DTAR)
Address offset: 0x054
Reset value: 0x0000 0000
30
DTMPR
31
29
28
27
26
25
24
23
DTBANK[2:0]
22
21
20
19
18
17
16
DTROW[15:4]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
DTROW[3:0]
rw
rw
rw
DTCOL[11:0]
rw
rw
Bit 31 DTMPR: Data training using MPR (DDR3 Only):
Specifies, if set, that data-training should use the SDRAM Multi-Purpose Register (MPR)
register. Otherwise data-training is performed by first writing to some locations in the SDRAM
and then reading the back.
Bits 30:28 DTBANK[2:0]: Data training bank address:
Selects the SDRAM bank address to be used during data training.
Bits 27:12 DTROW[15:0]: Data training row address:
Selects the SDRAM row address to be used during data training.
Bits 11:0 DTCOL[11:0]: Data training column address:
Selects the SDRAM column address to be used during data training.
The lower four bits of this address must always be “0000”.
7.7.29
DDRPHYC DTD register 0 (DDRPHYC_DTDR0)
Address offset: 0x058
Reset value: 0xDD22 EE11
31
30
29
28
27
26
25
24
23
22
21
DTBYTE3[7:0]
rw
rw
rw
15
14
13
rw
rw
rw
rw
rw
rw
rw
rw
12
11
10
9
8
7
6
5
DTBYTE1[7:0]
rw
rw
rw
rw
rw
20
19
18
17
16
DTBYTE2[7:0]
rw
rw
rw
rw
rw
4
3
2
1
0
rw
rw
rw
DTBYTE0[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:24 DTBYTE3[7:0]: Data training data
The first 4 bytes (e.g. shifted as Byte 0,1,2,3) of data used during data training. This same
data byte is used for each Byte Lane.
Default sequence is a walking 1 while toggling data every data cycle.
Bits 23:16 DTBYTE2[7:0]: Data Training Data
Bits 15:8 DTBYTE1[7:0]: Data Training Data
Bits 7:0 DTBYTE0[7:0]: Data Training Data
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DDR physical interface control (DDRPHYC)
7.7.30
RM0442
DDRPHYC DTD register 1 (DDRPHYC_DTDR1)
Address offset: 0x05C
Reset value: 0x7788 BB44
31
30
29
28
27
26
25
24
23
22
21
DTBYTE7[7:0]
20
19
18
17
16
DTBYTE6[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
DTBYTE5[7:0]
rw
rw
DTBYTE4[7:0]
rw
rw
Bits 31:24 DTBYTE7[7:0]: Data training data:
The second 4 bytes (e.g. shifted as Byte 4,5,6,7) of data used during data training. This same
data byte is used for each Byte Lane.
Default sequence is a walking 1 while toggling data every data cycle.
Bits 23:16 DTBYTE6[7:0]: Data Training Data
Bits 15:8 DTBYTE5[7:0]: Data Training Data
Bits 7:0 DTBYTE4[7:0]: Data Training Data
7.7.31
DDRPHYC general purpose register 0 (DDRPHYC_GPR0)
Address offset: 0x178
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
GPR0[31:16]
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
rw
rw
rw
rw
rw
rw
rw
rw
rw
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
GPR0[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 GPR0[31:0]: General purpose register 0 bits
7.7.32
DDRPHYC general purpose register 1 (DDRPHYC_GPR1)
Address offset: 0x17C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
GPR1[31:16]
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
rw
rw
rw
rw
rw
rw
rw
rw
rw
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
GPR1[15:0]
rw
402/3930
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RM0442 Rev 7
RM0442
DDR physical interface control (DDRPHYC)
Bits 31:0 GPR1[31:0]: General purpose register 1 bits
7.7.33
DDRPHYC ZQ0C register 0 (DDRPHYC_ZQ0CR0)
Address offset: 0x180
31
30
29
28
27
26
25
24
23
22
21
20
ZQPD
ZCAL
ZCALBYP
Reset value: 0x0000 014A
ZDEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
rw
rw
rw
rw
rw
rw
rw
19
18
17
16
ZDATA[19:16]
ZDATA[15:0]
rw
rw
Bit 31 ZQPD: ZCAL power down
Powers down, if set, the PZQ cell.
Bit 30 ZCAL: ZCAL trigger
Impedance Calibration Trigger: A write of '1' to this bit triggers impedance calibration to be
performed by the impedance control logic.
The impedance calibration trigger bit is self-clearing and returns back to '0' when the
calibration is complete.
Note: If ZDEN is set, then the ZCAL bit should be set to 0.
Bit 29 ZCALBYP: Impedance calibration bypass
Impedance Calibration Bypass: Disables, if set, impedance calibration of this ZQ control
block when impedance calibration is triggered globally using the ZCAL bit of DDRPHYC_PIR.
Impedance calibration of this ZQ block may be triggered manually using ZCAL.
Bit 28 ZDEN: Impedance override enable
Impedance Over-ride Enable: When this bit is set, it allows users to directly drive the
impedance control using the data programmed in the ZQDATA field. Otherwise, the control is
generated automatically by the impedance control logic.
Note: If ZDEN is set, then the ZCAL bit should be set to 0.
Bits 27:20 Reserved, must be kept at reset value.
Bits 19:0 ZDATA[19:0]: Impedance override
Impedance Over-Ride Data: Data used to directly drive the impedance control.
ZDATA field mapping for D3R I/Os is as follows:
ZDATA[27:20] is reserved and returns zeros on reads
ZDATA[19:15] is used to select the pull-up on-die termination impedance
ZDATA[14:10] is used to select the pull-down on-die termination impedance
ZDATA[9:5] is used to select the pull-up output impedance
ZDATA[4:0] is used to select the pull-down output impedance
Note: See mPHY ST40c25 Datasheet for ZDATA encoding, default value is: ODT pulpup/down set to hi-impedance and pull-up/down set to ~44.5 Ω for DDR3, 48.8 Ω for
DDR3L, 55.5 Ω for LPDDR2 typical corner 25C
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DDR physical interface control (DDRPHYC)
7.7.34
RM0442
DDRPHYC ZQ0CR1 register (DDRPHYC_ZQ0CR1)
Address offset: 0x184
Reset value: 0x7B
7
6
5
4
3
2
ZPROG[7:4]
rw
rw
1
0
rw
rw
ZPROG[3:0]
rw
rw
rw
rw
Bits 7:4 ZPROG[7:4]: Impedance divide ratio to ext R
Impedance divide ratio: selects the external resistor divide ratio to be used to set the output
impedance and the on-die termination as follows:
ZPROG[7:4] = On-die termination divide select (with RZQ = 240 Ω ±1%)
- 0x0: Reserved
- 0x1: 120 Ω
- 0x2: 96 Ω
- 0x3: 80 Ω
- 0x4: 69 Ω
- 0x5: 60 Ω
- 0x6: 52Ω
- 0x7: 46 Ω
- 0x8: 40 Ω
- 0x9: 37 Ω
- 0xA: 34 Ω
- 0xB: 32 Ω
- 0xC: 30 Ω
- 0xD: 28 Ω
- 0xE: 26.5 Ω
- 0xF: 25 Ω
Bits 3:0 ZPROG[3:0]: Impedance divide ratio to ext R
Impedance divide ratio: selects the external resistor divide ratio to be used to set the output
impedance and the on-die termination as follows:
ZPROG[3:0] = Output impedance divide select (with RZQ = 240 Ω ±1%)
- 0x0 to 0x4: Reserved
- 0x5: 80 Ω
- 0x6: 69 Ω
- 0x7: 60 Ω
- 0x8: 53 Ω
- 0x9: 48 Ω
- 0xA: 44 Ω
- 0xB: 40 Ω
- 0xC: 37 Ω
- 0xD: 34 Ω
- 0xE: 32 Ω
- 0xF: 30 Ω
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RM0442
DDR physical interface control (DDRPHYC)
7.7.35
DDRPHYC ZQ0S register 0 (DDRPHYC_ZQ0SR0)
Address offset: 0x188
31
30
29
28
27
26
25
24
23
22
21
20
ZDONE
Reset value: 0x0000 014A
ZERR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
r
r
r
r
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
r
r
r
r
r
r
r
19
18
17
16
ZCTRL[19:16]
ZCTRL[15:0]
r
r
Bit 31 ZDONE: Impedance calibration done
Indicates that impedance calibration has completed.
Bit 30 ZERR: Impedance calibration error
If set, indicates that there was an error during impedance calibration.
Bits 29:20 Reserved, must be kept at reset value.
Bits 19:0 ZCTRL[19:0]: Impedance control
Impedance Control: Current value of impedance control.
ZZCTRL field mapping for D3R I/Os is as follows:
ZCTRL[27:20] is reserved and returns zeros on reads
ZCTRL[19:15] is used to select the pull-up on-die termination impedance
ZCTRL[14:10] is used to select the pull-down on-die termination impedance
ZCTRL[9:5] is used to select the pull-up output impedance
ZCTRL[4:0] is used to select the pull-down output impedance
7.7.36
DDRPHYC ZQ0S register 1 (DDRPHYC_ZQ0SR1)
Address offset: 0x18C
Reset value: 0x00
7
6
5
OPU[1:0]
r
4
3
OPD[1:0]
r
r
2
1
ZPU[1:0]
r
r
RM0442 Rev 7
0
ZPD[1:0]
r
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r
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DDR physical interface control (DDRPHYC)
RM0442
Bits 7:6 OPU[1:0]: opu calibration status
On-Die termination (ODT) pull-up calibration status.
00: Completed with no errors
01: Overflow error
10: Underflow error
11: Calibration in progress
Bits 5:4 OPD[1:0]: opd calibration status
On-Die termination (ODT) pull-down calibration status.
00: Completed with no errors
01: Overflow error
10: Underflow error
11: Calibration in progress
Bits 3:2 ZPU[1:0]: zpu calibration status
Output impedance pull-up calibration status. Valid status encodings are:
00: Completed with no errors
01: Overflow error
10: Underflow error
11: Calibration in progress
Bits 1:0 ZPD[1:0]: zpd calibration status
Output impedance pull-down calibration status. Valid status encodings are:
00: Completed with no errors
01: Overflow error
10: Underflow error
11: Calibration in progress
7.7.37
DDRPHYC byte lane n GC register (DDRPHYC_DXnGCR)
Address offset: 0x1C0 + 0x40 * n, (n = 0 to 3)
Reset value: 0x0001 0E81
22
21
20
19
18
17
16
R0RVS
L[2]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R0RVSL[1:0]
RTTOH[1:0]
DSEN[1:0]
DQSODT
23
DQODT
24
DXIOM
25
DXPDD
26
DXPDR
27
DQSRPD
28
DQSRTT
29
DQRTT
30
RTTOAL
31
DXEN
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
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RM0442 Rev 7
RM0442
DDR physical interface control (DDRPHYC)
Bits 31:17 Reserved, must be kept at reset value.
Bits 16:14 R0RVSL[2:0]: Read valid system latency in steps
Used to specify the read valid system latency relative to the ideal placement of the ITMD read
valid signal when bit RVSEL in DDRPHYC_DXCCR register is set to 0.
Power-up default is 011 (i.e. ideal placement of the read valid signal).
The RVSL fields are initially set by the PUB during automatic read valid training but these
values can be overwritten by a direct write to this register.
Valid values are:
000: read valid system latency = ideal placement - 3
001: read valid system latency = ideal placement - 2
010: read valid system latency = ideal placement - 1
011: read valid system latency = ideal placement
100: read valid system latency = ideal placement + 1
101: read valid system latency = ideal placement + 2
110: read valid system latency = ideal placement + 3
Others: Reserved
Bit 13 RTTOAL: RTT ON additive latency
Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in
DQODT/DQSODT during read cycles.
Valid values are:
0: ODT control is set to DQSODT/DQODT almost two cycles before read data preamble
1: ODT control is set to DQSODT/DQODT almost one cycle before read data preamble
Bits 12:11 RTTOH[1:0]: RTT output hold
Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which
ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling
it (setting it to ‘0’) when using dynamic ODT control.
ODT is disabled almost RTTOH clock cycles after the read postamble
Bit 10 DQRTT: DQ dynamic RTT control
Indicates, if set, that the ODT control of DQ/DM SSTL I/Os be dynamically controlled by
setting it to the value in DQODT during reads and disabling it (setting it to ‘0’) during any
other cycle.
If this bit is not set, then the ODT control of DQ SSTL I/Os is always set to the value in
DQODT.
Since dynamic ODT is on by default, when using LPDDR2/LPDDR3 this bit must be set to 0
since LPDDR2/LPDDR3 does not require ODT to be on.`
Bit 9 DQSRTT: DQS dynamic RTT control
Indicates, if set, that the ODT control of DQS SSTL I/Os be dynamically controlled by setting
it to the value in DQSODT during reads and disabling it (setting it to ‘0’) during any other
cycle.
If this bit is not set, then the ODT control of DQS SSTL I/Os is always set to the value in
DQSODT field.
Since dynamic ODT is on by default, when using LPDDR2/LPDDR3 this bit must be set to 0
since LPDDR2/LPDDR3 does not require ODT to be on.
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DDR physical interface control (DDRPHYC)
RM0442
Bits 8:7 DSEN[1:0]: Write DQS enable
Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static
value) and whether the DQS is inverted.
DQS# is always the inversion of DQS.
These values are valid only when DQS/DQS# output enable is on, otherwise the DQS/DQS#
is tristated.
Valid settings are:
00: DQS disabled (Driven to constant 0)
01: DQS toggling with normal polarity (This should be the default setting)
10: DQS toggling with inverted polarity
11: DQS disabled (Driven to constant 1)
Bit 6 DQSRPD: DQSR power-down
Powers down, if set, the PDQSR cell.
This bit is ORed with the common PDR configuration bit
Bit 5 DXPDR: Data power-down receiver
Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of the
byte. This bit is ORed with the common PDR configuration bit
Bit 4 DXPDD: Data power-down driver
Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of the
byte. This bit is ORed with the common PDD configuration bit
Bit 3 DXIOM: Data I/O mode
Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) for the I/O for DQ, DM,
and DQS/DQS# pins of the byte.
This bit is ORed with the IOM configuration bit of the individual DATX8
Bit 2 DQODT: DQ ODT enable
Enables, when set, the on-die termination on the I/O for DQ and DM pins of the byte.
This bit is ORed with the common DATX8 ODT configuration bit
Bit 1 DQSODT: DQS ODT enable
Enables, when set, the on-die termination on the I/O for DQS/DQS# pin of the byte.
This bit is ORed with the common DATX8 ODT configuration bit
Bit 0 DXEN: DATA byte enable
Enables, if set, the DATX8 and SSTL I/Os used on the data byte.
Setting this bit to ‘0’ disables the byte, i.e. the byte SSTL I/Os are put in power-down mode
and the DLL in the DATX8 is put in bypass mode.
After changing a Byte Lane from disabled to enabled, the DLL for that Byte Lane must be
reset and re-locked.
Software can use bits DLLSRST and DLLLOCK of DDRPHYC_PIR register to accomplish
this (reset and re-locks all DLLs in the DDR PHY).
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RM0442
DDR physical interface control (DDRPHYC)
7.7.38
DDRPHYC byte lane n GS register 0 (DDRPHYC_DXnGSR0)
Address offset: 0x1C4 + 0x40 *n, (n = 0 to 3)
13
DTPASS[2:0]
r
r
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DTDONE
14
DTERR
15
DTIERR
Reset value: 0x0000
r
r
r
r
Bits 15:13 DTPASS[2:0]: DQS training pass count
The number of passing configurations during DQS gate training.
Bits 12:9 Reserved, must be kept at reset value.
Bit 8 DTIERR: DQS gate training intermittent error
If set, indicates that there was an intermittent error during DQS gate training of the byte, such
as a pass was followed by a fail then followed by another pass.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 DTERR: DQS gate training error
If set, indicates that a valid DQS gating window could not be found during DQS gate training
of the byte.
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 DTDONE: Data training done
Indicates, if set, that the byte has finished doing data training.
7.7.39
DDRPHYC byte lane n GS register 1 (DDRPHYC_DXnGSR1)
Address offset: 0x1C8 + 0x40 * n, (n = 0 to 3)
29
28
27
26
25
24
23
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
r
22
21
20
RVPASS[2:0]
DQSDFT[1:0]
r
r
19
18
17
16
Res.
Res.
Res.
RVIERR
30
3
2
1
0
Res.
Res.
Res.
DFTERR
31
RVERR
Reset value: 0x0000 0000
r
r
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:20 RVPASS[2:0]: Read valid training pass count
The number of passing configurations during read valid training.
Bits 19:17 Reserved, must be kept at reset value.
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RM0442
Bit 16 RVIERR: RV intermittent error for rank
If set, indicates that there was an intermittent error during read valid training of the byte, such
as a pass was followed by a fail then followed by another pass.
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 RVERR: RV training error
If set, indicates that a valid read valid placement could not be found during read valid training
of the byte
Bits 11:6 Reserved, must be kept at reset value.
Bits 5:4 DQSDFT[1:0]: DQS drift value
Used to report the drift on the read data strobe of the data byte.
Valid settings are:
00: No drift
01: 90° drift
10: 180° drift
11: 270° drift or more
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 DFTERR: DQS drift error
If set, indicates that the byte read data strobe has drifted by more than or equal to the drift
limit set in the PHY General Configuration Register (PGCR).
7.7.40
DDRPHYC byte lane n DLLC register (DDRPHYC_DXnDLLCR)
Address offset: 0x1CC + 0x40 * n, (n = 0 to 3)
Reset value: 0x4000 0000
27
26
25
24
23
22
21
20
19
18
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
15
14
SDPHASE[1:0]
rw
rw
13
12
11
SSTART[1:0]
rw
rw
10
9
8
MFWDLY[2:0]
rw
rw
7
6
5
MFBDLY[2:0]
rw
rw
rw
4
ATESTEN
28
SDLBMODE
29
DLLSRST
30
DLLDIS
31
rw
rw
3
2
SFWDLY[2:0]
rw
rw
rw
17
16
SDPHASE[3:2]
rw
rw
1
0
SFBDLY[2:0]
rw
rw
rw
rw
Bit 31 DLLDIS: DLL bypass
A disabled DLL is bypassed. Default ('0') is DLL enabled.
Note: DLL bypass must only be changed when DDRPHYC clock (dphy_ker_ck) is inactive.
Bit 30 DLLSRST: DLL reset
Soft resets the byte DLL by driving the DLL soft reset pin.
Note: DLL reset must only be changed to 0 when DDRPHYC clock (dphy_ker_ck) is inactive.
Bits 29:20 Reserved, must be kept at reset value.
Bit 19 SDLBMODE: Bypass slave DLL during loopback
If this bit is set, the slave DLL is put in loopback mode in which there is no 90 degrees phase
shift on read DQS/DQS#. This bit must be set when operating the byte PHYs in loopback
mode.
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RM0442
DDR physical interface control (DDRPHYC)
Bit 18 ATESTEN: Enable path to pin 'ATO'
Enables the analog test signal to be output on the DLL analog test output (DDR_ATO).
The DLL analog test output is tri-stated when this bit is '0'.
Bits 17:14 SDPHASE[3:0]: Slave DLL phase
Selects the phase difference between the input clock and
the corresponding output clock of the slave DLL. Valid settings:
0000: 90
0001: 72
0010: 54
0011: 36
0100: 108
0101: 90
0110: 72
0111: 54
1000: 126
1001: 108
1010: 90
1011: 72
1100: 144
1101: 126
1110: 108
1111: 90
Bits 13:12 SSTART[1:0]: Slave DLL autostart
Used to control how the slave DLL starts up relative to the
master DLL locking:
0X: Slave DLL automatically starts up once the master DLL has achieved lock.
10: The automatic startup of the slave DLL is disabled; the phase detector is
disabled.
11: The automatic startup of the slave DLL is disabled; the phase detector is
enabled.
Bits 11:9 MFWDLY[2:0]: Master DLL feed-forward trim
Used to trim the delay in the master DLL feedforward path:
000: minimum delay
...
111: maximum delay
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DDR physical interface control (DDRPHYC)
RM0442
Bits 8:6 MFBDLY[2:0]: Master DLL feed-back trim
Used to trim the delay in the master DLL feedback path:
000: minimum delay
...
111: maximum delay
Bits 5:3 SFWDLY[2:0]: Slave DLL feed-forward trim
Slave Feed-Forward Delay Trim: Used to trim the delay in the slave DLL feedforward path:
000: minimum delay
...
111: maximum delay
Bits 2:0 SFBDLY[2:0]: Slave DLL feed-back trim
Slave Feed-Back Delay Trim: Used to trim the delay in the slave DLL feedback path:
000: minimum delay
...
111: maximum delay
7.7.41
DDRPHYC byte lane n DQT register (DDRPHYC_DXnDQTR)
Address offset: 0x1D0 + 0x40 * n, (n = 0 to 3)
Reset value: 0xFFFF FFFF
31
30
29
28
27
DQDLY7[3:0]
26
25
24
23
DQDLY6[3:0]
22
21
20
19
DQDLY5[3:0]
18
17
16
DQDLY4[3:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
DQDLY3[3:0]
rw
rw
rw
DQDLY2[3:0]
rw
rw
DQDLY1[3:0]
rw
rw
DQDLY0[3:0]
rw
rw
rw
Bits 31:28 DQDLY7[3:0]: DQ delay for bit 7
Used to adjust the delay of the data relative to the nominal delay that is matched to the delay
of the data strobes through the slave DLL and clock tree.
The lower two bits of the DQDLY for each DQ bit controls the delay for the data clocked by
DQS, while the higher two bits control the delay for the data clocked by DQS_b.
Valid settings for each 2-bit control field are:
00: nominal delay
01: nominal delay + 1 step
10: nominal delay + 2 steps
11: nominal delay + 3 steps
Bits 27:24 DQDLY6[3:0]: DQ delay for bit 6
idem
Bits 23:20 DQDLY5[3:0]: DQ delay for bit 5
Idem
Bits 19:16 DQDLY4[3:0]: DQ delay for bit 4
Idem
Bits 15:12 DQDLY3[3:0]: DQ delay for bit 3
Idem
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DDR physical interface control (DDRPHYC)
Bits 11:8 DQDLY2[3:0]: DQ delay for bit 2
Idem
Bits 7:4 DQDLY1[3:0]: DQ delay for bit 1
Idem
Bits 3:0 DQDLY0[3:0]: DQ delay for bit 0
Idem
7.7.42
DDRPHYC byte lane n DQST register (DDRPHYC_DXnDQSTR)
Address offset: 0x1D4 + 0x40 * n, (n = 0 to 3)
Reset value: 0x3DB0 2000
31
30
Res.
Res.
29
28
27
26
25
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
Res.
Res.
R0DGPS[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMDLY[3:0]
rw
24
23
22
DQSNDLY[2:0]
21
20
19
18
17
16
Res.
Res.
Res.
Res.
4
3
2
1
0
Res.
Res.
DQSDLY[2:0]
rw
R0DGSL[2:0]
rw
rw
rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:26 DMDLY[3:0]: DM delay
Used to adjust the delay of the data relative to the nominal delay that is matched to the delay
of the data strobes through the slave DLL and clock tree.
The lower two bits of the DQDLY for each DQ bit controls the delay for the data clocked by
DQS, while the higher two bits control the delay for the data clocked by DQS_b.
Valid settings for each 2-bit control field are:
00: nominal delay
01: nominal delay + 1 step
10: nominal delay + 2 steps
11: nominal delay + 3 steps
Bits 25:23 DQSNDLY[2:0]: DQS# delay
Used to adjust the delay of the data strobes relative to the nominal delay that is matched to
the delay of the data bit through the slave DLL and clock tree.
Valid values are:
000: nominal delay - 3 steps
001: nominal delay - 2 steps
010: nominal delay - 1 step
011: nominal delay
100: nominal delay + 1 step
101: nominal delay + 2 steps
110: nominal delay + 3 steps
111: nominal delay + 4 steps
Note: - After changing this value, an ITM soft reset must be issued: bit ITMSRST=1 and bit
INIT=1 in DDRPHYC_PIR register.
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DDR physical interface control (DDRPHYC)
RM0442
Bits 22:20 DQSDLY[2:0]: DQS delay
Used to adjust the delay of the data strobes relative to the nominal delay that is matched to
the delay of the data bit through the slave DLL and clock tree.
Valid values are:
000: nominal delay - 3 steps
001: nominal delay - 2 steps
010: nominal delay - 1 step
011: nominal delay
100: nominal delay + 1 step
101: nominal delay + 2 steps
110: nominal delay + 3 steps
111: nominal delay + 4 steps
Note: - After changing this value, an ITM soft reset (bit ITMSRST=1 and bit INIT=1 in
DDRPHYC_PIR register) must be issued.
Bits 19:14 Reserved, must be kept at reset value.
Bits 13:12 R0DGPS[1:0]: Rank 0 DQS gating phase select
Selects the clock used to enable the data strobes during read so that the value of the data
strobes before and after the preamble/postamble are filtered out.
R0DGPS is initially set by the PUBL during automatic DQS data training and subsequently
updated during data strobe drift compensation. However, these values can be overwritten by
a direct write to this register, and the automatic update during DQS drift compensation can be
disabled using the PHY General Configuration Register (PGCR).
Valid values are:
00: 180 clock (clk180)
01: 270 clock (clk270)
10: 360 clock (clk0)
11: 450 clock (next clk90)
Bits 11:3 Reserved, must be kept at reset value.
Bits 2:0 R0DGSL[2:0]: Rank 0 DQS gating system latency
Used to increase the number of clock cycles needed to expect valid DDR read data by up to
five extra clock cycles.
This is used to compensate for board delays and other system delays.
Power-up default is 000 (i.e. no extra clock cycles required).
The SL fields are initially set by the PUBL during automatic DQS data training but these
values can be overwritten by a direct write to this register.
Valid values are:
000: No extra clock cycles
001: 1 extra clock cycle
010: 2 extra clock cycles
011: 3 extra clock cycles
100: 4 extra clock cycles
101: 5 extra clock cycles
Others: Reserved
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7.7.43
DDR physical interface control (DDRPHYC)
DDRPHYC register map
Register name
reset value
DFTCMP
DQSCFG
ITMDMD
DFTLMT[1:0]
CKDV[1:0]
IOLB
CKINV
DTOSEL
[3:0]
Reset value
DRES[1:0]
IPUMP[2:0]
TESTEN
DTC
[2:0]
Res.
Res.
Res.
Res.
Res.
Res.
MFBDLY[2:0]
MFWDLY[2:0]
0 0 0 0 0 0
TDLLLOCK[11:0]
TDLLSRST[5:0]
1 0 0 0 1 0 1 0 1 0 1 1 1 1 1 0 0 1 1 0 1 1
TDINIT1[7:0]
TDINIT0[18:0]
1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 1 1 0 1
TDINIT3[9:0]
TDINIT2[16:0]
0 0 1 1 0 0 0 0 0 1 0 0 0 0
RM0442 Rev 7
ACPDR
ACPDD
ACODT
ACOE
ACIOM
CKODT[2:0]
CKPDD[2:0]
CSPDD
[3:0]
CKPDR[2:0]
RANKPDR[3:0]
RSTIOM
RSTPDR
RSTPDD
RSTODT
1 0 0 0 0 1 0 1 1 0 1 1 0 1 0 0 0 0 0 0 1 1 1 0 0 1 0
ACSR[1:0]
DDRPHYC_ACIOCR
TESTSW
0
Res.
Res.
Res.
Res.
Res.
DDRPHYC_PTR2
SBIAS2_0[2:0]
0 1
Res.
Res.
Res.
Res.
Res.
DDRPHYC_PTR1
ATC
[1:0]
0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
RANKODT
DDRPHYC_PTR0
MBIAS[7:0]
TITMSRST[3:0]
DDRPHYC_ACDLLCR
BPS200
DDRPHYC_DLLGCR
0 0 0 0 0 0 0 0 0 0
SBIAS5_3[2:0]
0
Reset value
0x024
IODDRM[1:0]
LBMODE
LBGDQS
LBDQSS
Reset value
Reset value
0x020
CKEN
[2:0]
DDRPHYC_PGSR
Reset value
0x01C
RANKEN
[3:0]
0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 1 0 0
Reset value
0x018
RFSHDT
[3:0]
0 0 0 0 0 0 0 0 0
Reset value
Reset value
0x014
PDDISDX
DDRPHYC_PGCR
0 0
ZKSEL[1:0]
0 0 0 0
LOCKDET
0x010
Reset value
TQ
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RVEIRR
RVERR
DFTERR
DTIERR
DTERR
DTDONE
DIDONE
ZCDDONE
DLDONE
IDONE
0x00C
DDRPHYC_PIR
DLLRSVD2[1:0]
0x008
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
DLLDIS
DLLSRST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ATESTEN
Res.
Res.
Res.
Res.
Res.
Res.
0x004
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x000
PHYMJR PHYMDR PHYMNR PUBMJR PUBMDR PUBMNR
[3:0]
[3:0]
[3:0]
[3:0]
[3:0]
[3:0]
UDRID[7:0]
INITBYP
ZCALBYP
LCOKBYP
CLRSR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DLLBYP
ICPC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RVTRN
QSTRN
DRAMINIT
DRAMRST
ITMSRST
ZCAL
DLLLOCK
DLLSRST
INIT
DDRPHYC_RIDR
FDTRMSL[1:0]
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 26. DDRPHYC register map and reset values
0 0 0 1 0 0 0 0 0 0 1 0 0 1 0
415/3930
420
DDR physical interface control (DDRPHYC)
RM0442
Reset value
DDRPHYC_DTPR2
0x03C
DXPDR
DXPDD
DXIOM
DXODT
DQSRES[3:0]
LPDLLPD
LPIOPD
ZUEN
BDISEN
PUREN
DQSGX[2:0]
TRCD[3:0] TRP[3:0]
DDRMD[2:0]
DDR8BNK
MPRDQ
TWTR
[2:0]
TRTP
[2:0]
TMRD[1:0]
TRAS[4:0]
PDQ[2:
0]
0 0 1 0 0 1 1 0 0 0 0 0 1 1
TDLLK[9:0]
TFAW[5:0]
TAOND[1:0]
TRTW
TRFC[7:0]
TMOD[1:0]
0 0 1 1 0 0 0 0 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 1 0
0 0 0 0 1 0 0 1 0 0 0 0
TCKE[3:0]
TXP[4:0]
TXS[9:0]
RSVD
[2:0]
Reset value
Reset value
0x046 0x046
416/3930
NWR
[2:0]
WC
BT
0 0 0 0 0 0 0 0
BL[2:0]
0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
RTT0
DIC0
DE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
QOFF
TDQS
Res.
RTT2
Res.
LEVEL
RTT1
DIC1
0
AL
[1:0]
NWR
[2:0]
0 0 0
Res.
Reserved
RM0442 Rev 7
Res.
Res.
0x044
DDRPHYC_LPDDR3_
MR1
0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DDRPHYC_LPDDR2_
MR1
BL
[1:0]
0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0
Reset value
0x044
CL1
[2:0]
Res.
Reserved
DDRPHYC_DDR3_MR1
WR[2:0]
BT
CL0
DDRPHYC_DDR3_MR0
DR
TM
1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0
PD
Reset value
0x042 0x042
0x044
DQSGE[2:0]
DDRTYPE[1:0]
TRRD[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x040
TRC[5:0]
Res.
Res.
Res.
Res.
TRTODT
DDRPHYC_DTPR1
0x038
0 0 0 0 0 0 1 0 1 1
TDQSCKMIN[2:0]
Reset value
0 0 0 0 0 0 0 0 1 1 1 1 1
0 0 0 0 0
TDQSCKMAX[2:0]
DDRPHYC_DTPR0
0x034
CKEPDD
[3:0]
TPD
RDIMM
UDIMM
DDR2T
NOSRA
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
TCCD
DDRPHYC_DCR
0x030
ODTPDD
[3:0]
1 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0
Res.
Res.
Reset value
Res.
Res.
Res.
DDRPHYC_DSGCR
0x02C
0 0 0
CKOE
RSTOE
ODTOE
CKOE
TPDOE
TPDPD
NL2OE
NL2PD
Reset value
DQSNRES[3:0]
DDRPHYC_DXCCR
Res.
Res.
Res.
FXDLAT
NOBUB
0x028
Register name
reset value
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Offset
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AWDT
RVSEL
DQSNRST
Res.
Res.
Table 26. DDRPHYC register map and reset values (continued)
BL[2:0]
0 0 0
RM0442
DDR physical interface control (DDRPHYC)
0 0 0 0 0 0 0 0
0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WR
WL
Res.
NWRE
Res.
Reset value
Reset value
Reserved
DDRPHYC_DDR3_MR3
0
0x04C
0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
DDRPHYC_LPDDR2_
MR3
DDRPHYC_LPDDR3_
MR3
0x054
DDRPHYC_ODTCR
Reset value
1
Reserved
Res.
DDRPHYC_DTAR
Reset value
0x058
0x05C
0x060 0x174
0x178
0x17C
DDRPHYC_DTDR0
Reset value
DDRPHYC_DTDR1
DTBANK[2:0]
0x052 0x050
Reserved
DTMPR
0x050
0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WRODT
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RDODT
Reset value
0x04D 0x04E
DS[3:0]
0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
0x04C
0 0 0
Res.
PDCTL[1:0]
0x04C
0 0
RLWL
[2:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MPR
0x04A 0x04B
RLWL
[2:0]
MPRLOC[1:0]
0x048
DDRPHYC_LPDDR3_
MR2
PASR
[2:0]
DQ[1:0]
0x048
0 0
CWL
[2:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
DDRPHYC_LPDDR2_
MR2
Res.
SRT
ASR
DDRPHYC_DDR3_MR2
RTTWR[1:0]
0x048
Register name
reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 26. DDRPHYC register map and reset values (continued)
0
DTROW[15:0]
DTCOL[11:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DTBYTE3[7:0]
DTBYTE2[7:0]
DTBYTE1[7:0]
DTBYTE0[7:0]
1 1 0 1 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 1 0 0 0 1
DTBYTE7[7:0]
DTBYTE6[7:0]
DTBYTE5[7:0]
DTBYTE4[7:0]
Reset value
0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 0 1 0 0
Reserved
Res.
DDRPHYC_GPR0
GPR0[31:0]
Reset value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DDRPHYC_GPR1
GPR1[31:0]
Reset value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RM0442 Rev 7
417/3930
420
DDR physical interface control (DDRPHYC)
RM0442
0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0
ZPROG[7: ZPROG[3:
4]
0]
Reset value
0 1 1 1 1 0 1 1
Res.
0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0
Reset value
0 0 0 0 0 0 0 0
0x1D4
DDRPHYC_DX0DQSTR
Reset value
0x1D8 0x1FC
418/3930
DSEN[1:0]
DQRTT
DQSRTT
RTTOH[1:0]
Res.
Res.
Res.
Res.
DTIERR
Res.
Res.
Res.
DTERR
Res.
Res.
Res.
DTDONE
MFWDLY[2:0]
SSTART[1:0]
SDPHASE[3:0]
0
0 0
0
SFBDLY[2:0]
Res.
Res.
Res.
RVIERR
Res.
Res.
Res.
RVERR
Res.
Res.
Res.
Res.
Res.
Res.
RVPASS[2:0]
0 1
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DQDLY7
[3:0]
DQDLY6
[3:0]
DQDLY5
[3:0]
DQDLY4
[3:0]
DQDLY3
[3:0]
DQDLY2
[3:0]
DQDLY1
[3:0]
DQDLY0
[3:0]
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DMDLY
[3:0]
1 1 1 1 0 1 1 0 1 1
Res.
RM0442 Rev 7
1 0
R0DGSL[2:0]
Reset value
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DDRPHYC_DX0DQTR
0x1D0
0
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
DQSNDLY[2:0]
DDRPHYC_DX0DLLCR
Res.
Res.
0x1CC
0 0 0
DLLDIS
DLLSRST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SDLBMODE
ATESTEN
Reset value
DQSDLY[2:0]
DDRPHYC_DX0GSR1
0x1C8
0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
R0DGPS[1:0]
DDRPHYC_DX0GSR0
0x1C4
1 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
RTTOAL
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DDRPHYC_DX0GCR
0x1C0
R0RVSL[2:0]
Res.
Reserved
DTPASS[2:0]
0x18D 0x1BC
OPU OPD ZPU ZPD
[1:0] [1:0] [1:0] [1:0]
Res.
Res.
Res.
DFTERR
DDRPHYC_ZQ0SR1
0x18C
0 0
DQSDFT[1:0]
Reset value
ZCTRL[19:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DDRPHYC_ZQ0SR0
0x188
ZDONE
ZERR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
MFBDLY[2:0]
0x185 0x184
SFWDLY[2:0]
DDRPHYC_ZQ0CR1
0x184
ZDATA[19:0]
DQSRPD
DXPDR
DXPDD
DXIOM
DQODT
DQSODT
DXEN
Reset value
ZQPD
ZCAL
ZCALBYP
ZDEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DDRPHYC_ZQ0CR0
0x180
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Register name
reset value
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 26. DDRPHYC register map and reset values (continued)
0 0 0
0x248
DDRPHYC_DX2GSR1
Reset value
Reserved
0 0 0
RM0442 Rev 7
0
0
DQDLY2
[3:0]
DQDLY1
[3:0]
1 0
SFBDLY[2:0]
SFWDLY[2:0]
MFBDLY[2:0]
MFWDLY[2:0]
SSTART[1:0]
SDPHASE[3:0]
Res.
Res.
Res.
DFTERR
0
Res.
Res.
Res.
DFTERR
Res.
Res.
Res.
RVIERR
Res.
Res.
Res.
RVERR
Res.
Res.
Res.
Res.
Res.
Res.
RVPASS[2:0]
DQSDFT[1:0]
Res.
Res.
Res.
RVIERR
Res.
Res.
Res.
RVERR
Res.
Res.
Res.
Res.
Res.
RVPASS[2:0]
0 0
DQSDFT[1:0]
0
R0DGSL[2:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DQDLY3
[3:0]
DQSRPD
DXPDR
DXPDD
DXIOM
DQODT
DQSODT
DXEN
1 1 1 1 0 1 1 0 1 1
R0DGPS[1:0]
DQDLY4
[3:0]
DSEN[1:0]
DMDLY
[3:0]
DQDLY5
[3:0]
0
Res.
Res.
Res.
DFTERR
0x246 0x244
DDRPHYC_DX2GCR
DQDLY6
[3:0]
0
DQSDFT[1:0]
0x240
0 0 0
DQRTT
DQSRTT
Reset value
DQDLY7
[3:0]
0
RTTOH[1:0]
0x218 0x23C
DDRPHYC_DX1DQSTR
0 0 0
RTTOAL
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
R0RVSL[2:0]
0x214
DDRPHYC_DX1DQTR
0 1
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
RVIERR
Res.
Res.
Res.
RVERR
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
DQSDLY[2:0]
0x210
DDRPHYC_DX1DLLCR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
RVPASS[2:0]
0x20C
DDRPHYC_DX1GSR1
DQSNDLY[2:0]
0x208
DDRPHYC_DX1GSR0
DLLDIS
DLLSRST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SDLBMODE
ATESTEN
0x204
DQSRPD
DXPDR
DXPDD
DXIOM
DQODT
DQSODT
DXEN
DSEN[1:0]
DQRTT
DQSRTT
RTTOH[1:0]
RTTOAL
R0RVSL[2:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DDRPHYC_DX1GCR
Res.
Res.
0x200
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register name
reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Offset
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RM0442
DDR physical interface control (DDRPHYC)
Table 26. DDRPHYC register map and reset values (continued)
1 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 1
0 0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DQDLY0
[3:0]
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0
Res.
Reset value
1 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 1
Reserved
Res.
0 0
0
419/3930
420
DDR physical interface control (DDRPHYC)
RM0442
Reset value
SFBDLY[2:0]
SFWDLY[2:0]
R0DGSL[2:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DQSRPD
DXPDR
DXPDD
DXIOM
DQODT
DQSODT
DXEN
DSEN[1:0]
DQRTT
DQSRTT
DQSDFT[1:0]
Res.
Res.
Res.
DFTERR
0 0
0
SFBDLY[2:0]
SFWDLY[2:0]
MFBDLY[2:0]
MFWDLY[2:0]
SSTART[1:0]
SDPHASE[3:0]
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DQDLY7
[3:0]
DQDLY6
[3:0]
DQDLY5
[3:0]
DQDLY4
[3:0]
DQDLY3
[3:0]
DQDLY2
[3:0]
DQDLY1
[3:0]
DQDLY0
[3:0]
1 1 1 1 0 1 1 0 1 1
1 0
RM0442 Rev 7
R0DGSL[2:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMDLY
[3:0]
R0DGPS[1:0]
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Refer to Section 2.5 on page 153 for the register boundary addresses.
420/3930
MFBDLY[2:0]
MFWDLY[2:0]
SSTART[1:0]
RTTOH[1:0]
Res.
Res.
Res.
RVIERR
Res.
Res.
Res.
RVERR
Res.
Res.
Res.
Res.
Res.
Res.
DLLDIS
DLLSRST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SDLBMODE
ATESTEN
0
Res.
Res.
Res.
Res.
Res.
Res.
DDRPHYC_DX3DQSTR
0 1
DQSNDLY[2:0]
Reset value
0 0 0
Res.
Res.
DDRPHYC_DX3DQTR
RVPASS[2:0]
Res.
DDRPHYC_DX3DLLCR
0x290
0 0 0
Reserved
Reset value
0x294
1 0
1 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 1
Reset value
0x28C
DQDLY0
[3:0]
Reset value
DDRPHYC_DX3GSR1
0x288
DQDLY1
[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x286 0x284
SDPHASE[3:0]
1 1 1 1 0 1 1 0 1 1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DDRPHYC_DX3GCR
DQDLY2
[3:0]
R0DGPS[1:0]
DMDLY
[3:0]
Reserved
0x280
DQDLY3
[3:0]
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reset value
0x258 0x27C
DQDLY4
[3:0]
RTTOAL
DDRPHYC_DX2DQSTR
DQDLY5
[3:0]
DQSDLY[2:0]
0x254
DQDLY6
[3:0]
R0RVSL[2:0]
Reset value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DQDLY7
[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
DDRPHYC_DX2DQTR
0x250
0 1
DQSDLY[2:0]
Reset value
DQSNDLY[2:0]
DDRPHYC_DX2DLLCR
DLLDIS
DLLSRST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SDLBMODE
ATESTEN
0x24C
Res.
Res.
Register name
reset value
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 26. DDRPHYC register map and reset values (continued)
0 0 0
RM0442
DDR performance monitor (DDRPERFM)
8
DDR performance monitor (DDRPERFM)
8.1
Introduction
The DDRPERFM is intended to monitor DDR controller performance by counting events
from a set of signals and gathering results under software control.
The DDRPERFM can be used to feedback important statistics such as the DDR utilization,
read/write bandwidth, bank activation, idle state duration for some off-line analysis of the
DDR system performance and for optimal parameter settings to improve the DDR utilization
and for power optimization.
8.2
Features
•
One 32-bit time counter (TCNT)
•
Four 32-bit event counters (CNT0 to CNT3)
•
Selection from 4 sets of events to be monitored
•
Global Start/ Stop control
•
Individual counter enable and clear
•
Global counter start and stop triggered by software
•
Counter overflow detection with all the counters freeze and the interrupt event
generation
•
APB interface
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DDR performance monitor (DDRPERFM)
8.3
RM0442
Block diagram
Figure 26. DDRPERFM block diagram
DDRCTRL perf_monitoring and DFI signals
...
...
Signal Set Selection
ck_ddrc
Time Counter
Evt Counter0
Evt Counter7
32
APB
APB
interface
32
32
Overflow
detection
ddrperfm_it
DDRPERFM
MSv46527V1
8.4
Functional description
The DDRPERFM provides information of how efficiently the DDR controller is working by
reporting statistics according to the set of signals selected for monitoring.
Up to 4 signals from 4 sets of signals along with one permanent clock counter can be
monitored.
The counters are started and stopped by software.
All the counters stop when one counter saturates. (The quickest it can saturate is 8.05
seconds with 533 MHz DDR)
The counters may be halted without resetting them to suspend counting.
Useful composite statistics can be derived from counter values; This information can be
used by developers to tune the DDR controller settings. For example to optimize the DDR
utilization or to improve the low-power mode settings.
422/3930
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RM0442
DDR performance monitor (DDRPERFM)
Table 27. DDRPERFM signal sets
Set
CNT0
CNT1
CNT2
CNT3
0
perf_op_is_rd
perf_op_is_wr
perf_op_is_activate
ctl_idle
1
perf_hpr_req_with_no
credit
perf_lpr_req_with_noc
redit
Reserved
cactive_ddrc
2
perf_op_is_enter_pow
erdown
perf_op_is_refresh
perf_selfref_mode
dfi_lp_req
3
perf_hpr_xact_when_c perf_lpr_xact_when_c perf_wr_xact_when_c
ritical
ritical
ritical
RM0442 Rev 7
dfi_lp_req
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DDR performance monitor (DDRPERFM)
RM0442
The signals are described hereafter:
perf_op_is_rd
Asserted for every read that is issued for commands going through CAM
perf_op_is_wr
Asserted for every write that is issued for commands going through
CAM.
perf_op_is_activate
Asserted for every activate that is issued for commands going through
CAM
ctl_idle
Asserted when the controller is idle for extended periods and only when
there are no commands or data on the DFI interface.
perf_hpr_req_with_nocredit
Asserted when there is a High Priority Read (HPR) request (from XPI to
PA) not served due to no available credit.
perf_lpr_req_with_nocredit
Asserted when there is a Low Priority Read (LPR) request (from XPI to
PA) not served due to no available credit.
cactive_ddrc
DDRC Hardware Low-power clock active. Indicates that the DDRC
requires its clock signal.
perf_op_is_enter_powerdown Asserted for every entry into Power down mode
perf_op_is_refresh
Asserted for every refresh command that is issued by the controller.
perf_selfref_mode
Asserted for the entire duration for which the controller stays in SelfRefresh mode.
perf_hpr_xact_when_critical
Asserted for every High Priority Read transaction that is scheduled when
the High Priority queue is in critical state.
perf_lpr_xact_when_critical
Asserted for every Low Priority Read transaction that is scheduled when
the Low Priority queue is in critical state.
perf_wr_xact_when_critical
Asserted for every write transaction that is scheduled when the write
queue is in critical state.
dfi_lp_req
DFI low-power opportunity request. This signal is used by the controller
to inform the PHY of an opportunity to switch to a low-power mode.
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RM0442
DDR performance monitor (DDRPERFM)
8.5
Application information
8.5.1
Signal set 0: to monitor the DDR utilization
By counting the read and write commands sent to DDR over a time window, can be
monitored:
Note:
•
The read and write traffic (approximate) bandwidth.
•
The DDR utilization.
•
The DDR scheduling efficiency
The DDR efficiency is measured by the ratio of read and write count to the time where the
DDR is not idle.
Example:
read_bandwidth (Mbyte/sec)
~= 4 * BL * freq * CNT0/TCNT
write_bandwidth (Mbyte/sec) ~= 4 * BL * freq * CNT1/TCNT
DDR_utilization = (BL/2) *(CNT0 + CNT1)/TCNT
with
BL = 8
freq = 533 MHz
The ratio of activate commands to the total of read and write commands is providing
information about the bank conflict efficiency, this information can be used to select the best
memory access pattern between the bank sequential or the bank interleaved.
8.5.2
Signal set 1: to monitor the HPR and LPR stores
By counting the durations where the DDRC stores are out-of-credit to fine tune the
DDRCTRL scheduling and performance control:
•
To better balance the store split between HPR and LPR.
•
To optimize the starvation timeout.
•
To optimize run-length when the store is in critical state
•
To fine tune the page open/close policy.
These settings are controlled by DDRCTRL_SCHED, DDRCTRL_SCHED1,
DDRCTRL_HPR1, DDRCTRL_LPR1, DDRCTRL_WR1 registers.
8.5.3
Signal set 2: to monitor the refresh and self-refresh duration
The refresh commands are sent at regular intervals when the DDR is not in self-refresh.
Monitoring the PowerDown commands sent when the DDR is idle, can be used to fine tune
the low-power settings controlled by DDRCTRL_PWRCTRL and DDRCTRL_PWRTMG.
8.5.4
Signal set 3: to monitor the DDR stalling
By counting the duration where any DDRC store is in critical state, it is possible to fine tune
the DDRCTRL scheduling and performance control.
The queue goes to critical state when the starvation counters time out
These settings are controlled by DDRCTRL_PCFGR/W, DDRCTRL_PCFGQOS,
DDRCTRL_CFGWQOS registers for each port.
RM0442 Rev 7
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DDR performance monitor (DDRPERFM)
RM0442
8.6
DDRPERFM registers
8.6.1
DDRPERFM control register (DDRPERFM_CTL)
Address offset: 0x000
Reset value: 0x0000 0000
Note:
Write-only register. A read request returns all zeros.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
STOP
START
w
w
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 STOP: stop all the counters.
0: writing a ‘0’ has no effect.
1: writing a ‘1’ stops all the counters
Writing a ‘1’ when the counters are stopped (DDRPERFM_STATUS.BUSY = 0) is ignored
Bit 0 START: Start counters which are enabled, the time counter (TCNT) is always enabled.
0: writing a ‘0’ has no effect.
1: writing a ‘1’ Starts counters which are enabledW
writing a ‘1’ when the counters are running (DDRPERFM_STATUS.BUSY = 1) is ignored
Caution:
A simultaneous write of START and STOP bits at ‘1’ has an unpredictable effect.
8.6.2
DDRPERFM configurationl register (DDRPERFM_CFG)
Address offset: 0x004
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
17
rw
rw
1
0
rw
rw
EN[3:0]
Bits 31:18 Reserved, must be kept at reset value.
Bits 17:16 SEL[1:0]: select set of signals to be monitored (from 0 to 3) (see signal set description in
Table 27: DDRPERFM signal sets) and counters to be enabled
Bits 15:4 Reserved, must be kept at reset value.
Bits 3:0 EN[3:0]: enable counter x (from 0 to 3)
0: the corresponding counter is disabled and does not increment
1: the corresponding counter is enabled and incremented on event at each clock
426/3930
RM0442 Rev 7
16
SEL[1:0]
RM0442
DDR performance monitor (DDRPERFM)
Note:
The time counter (TCNT) is enabled by default.
Caution:
The DDRPERFM_CFG can be modified only when the DDRPERFM is stopped.
A write to this register is ignored when DDRPERFM_STATUS.BUSY = 1
8.6.3
DDRPERFM status register (DDRPERFM_STATUS)
Address offset: 0x008
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TOVF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BUSY
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
r
r
COVF[3:0]
r
r
r
r
Bit 31 TOVF: total counter overflow
0: no overflow
1: counter overflow
Bits 30:17 Reserved, must be kept at reset value.
Bit 16 BUSY: Busy Status
0: DDRPERFM is stopped or a counter is in overflow
1: DDRPERFM is counting (at least TCNT is counting)
Bits 15:4 Reserved, must be kept at reset value.
Bits 3:0 COVF[3:0]: Counter x Overflow (with x from 0 to 3)
0: no overflow
1: counter overflow
Note:
When any counter is in overflow, the DDRPERFM is stopped with all the counters keeping
their value, the DDRPERFM needs a restart after overflowing counter has been cleared.
The counter overflow is also visible also by reading DDRPERFM_CNTx = 0xFFFF_FFFF
8.6.4
DDRPERFM counter clear register (DDRPERFM_CCR)
Address offset: 0x00C
Note:
Write-only register. A read request returns all zeros
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TCLR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
3
2
1
0
w
15
14
13
12
11
10
9
8
7
6
5
4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CCLR[3:0]
w
RM0442 Rev 7
w
w
w
427/3930
432
DDR performance monitor (DDRPERFM)
RM0442
Bit 31 TCLR: time counter clear
0: writing a ‘0’ has no effect
1: writing a ‘1’ clears the time counter
Bits 30:4 Reserved, must be kept at reset value.
Bits 3:0 CCLR[3:0]: counter x Clear (with x from 0 to 3)
0: writing a ‘0’ has no effect
1: writing a ‘1’ clears the corresponding event counter x (with x from 0 to 3)
Note:
A write to this register is ignored when DDRPERFM_STATUS.BUSY = 1.
8.6.5
DDRPERFM interrupt enable register (DDRPERFM_IER)
Address offset: 0x010
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OVFIE
rw
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 OVFIE: overflow interrupt enable
0: overflow interrupt disabled
1: overflow interrupt enabled
8.6.6
DDRPERFM interrupt status register (DDRPERFM_ISR)
Address offset: 0x014
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OVFF
r
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 OVFF: overflow flag
This flag is set when one counter is in overflow
428/3930
RM0442 Rev 7
RM0442
DDR performance monitor (DDRPERFM)
8.6.7
DDRPERFM interrupt clear register (DDRPERFM_ICR)
Address offset: 0x018
Note:
Write-only register. A read request returns all zeros
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OVF
w
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 OVF: overflow flag
0: no action
1: clears the overflow flag
Note:
Following a counter overflow, the programming sequence must be:
1) Clear the counter(s) by writing ‘1’ to DDRPERFM_CCR appropriate bits
2) Clear the interrupt by writing ‘1’ to DDRPERFM_ICR.OVF
8.6.8
DDRPERFM time counter register (DDRPERFM_TCNT)
Address offset: 0x020
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CNT[31:16]
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
CNT[15:0]
r
r
Bits 31:0 CNT[31:0]: total time, this is number of DDR controller clocks elapsed while DDRPERFM has
been running.
Caution:
The time counter must only be read when DDRPERFM is stopped.
This register is read as zero when DDRPERFM_STATUS.BUSY=1.
RM0442 Rev 7
429/3930
432
DDR performance monitor (DDRPERFM)
8.6.9
RM0442
DDRPERFM event counter x register (DDRPERFM_CNTx)
Address offset: 0x030 + x * 0x008 (x = 0 to 3)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CNT[31:16]
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
CNT[15:0]
r
r
Bits 31:0 CNT[31:0]: event counter value.
Each counter is incrementing when the corresponding signal from the selected set is
asserted. See Table 27: DDRPERFM signal sets .
Caution:
The counters must only be read when DDRPERFM is stopped.
These registers are read as zero when DDRPERFM_STATUS.BUSY=1.
8.6.10
DDRPERFM hardware configuration register (DDRPERFM_HWCFG)
Address offset: 0x3F0
Reset value: 0x0000 0004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
NCNT[3:0]
r
r
r
r
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 NCNT[3:0]: number of counters for this configuration (4)
8.6.11
DDRPERFM version register (DDRPERFM_VER)
Address offset: 0x3F4
Reset value: 0x0000 0010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MAJREV[3:0]
r
Bits 31:8 Reserved, must be kept at reset value.
430/3930
RM0442 Rev 7
r
r
MINREV[3:0]
r
r
r
r
r
RM0442
DDR performance monitor (DDRPERFM)
Bits 7:4 MAJREV[3:0]: Major revision number.
Bits 3:0 MINREV[3:0]: Minor revision number.
8.6.12
DDRPERFM ID register (DDRPERFM_ID)
Address offset: 0x3F8
Reset value: 0x0014 0061
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ID[31:16]
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
19
18
17
16
ID[15:0]
Bits 31:0 ID[31:0]: DDRPERFM unique identification.
8.6.13
DDRPERFM magic ID register (DDRPERFM_SID)
Address offset: 0x3FC
Reset value: 0xA3C5 DD01
31
30
29
28
27
26
25
24
23
22
21
20
SID[31:16]
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
SID[15:0]
r
Bits 31:0 SID[31:0]: magic ID for automatic IP discovery.
8.6.14
DDRPERFM register map
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
COVF[3:0]
0
0
0
CCLR[3:0]
0
RM0442 Rev 7
0
EN[3:0]
0
Res.
BUS
Y
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Reset value
0
0
Res.
0
Res.
Reset value
DDRPERFM_CCR
TCLR
0x00C
DDRPERFM_STATUS
TOVF
Reset value
0x008
0
Res.
0x004
START
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Reset value
DDRPERFM_CFG
STOP
16
Res.
Res.
SEL[1:0]
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Res.
DDRPERFM_CTL
Res.
0x000
Register
Res.
Offset
Res.
Table 28. Power control register map and reset values
0
0
0
431/3930
432
Res.
Res.
432/3930
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
DDRPERFM_ID
Reset value
DDRPERFM_SID
Reset value
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
1
1
1
1
0
0
0
1
RM0442 Rev 7
Res.
Res.
CNT[31:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
Res.
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
0
0
0
0
0
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Reset value
ID[31:0]
0 0 0 0 0 0 0 0 0 0 1 1 0
SID[31:0]
0
1 1 1 0 1 1 1 0 1 0 0 0 0
0
Refer to Section 2.5 on page 153 for the register boundary addresses.
Res. Res.
0
Res.
0
Res. Res.
0
Res.
CNT[31:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res. Res.
0
Res.
0
Res.
0
Res. Res.
0
Res.
0
Res.
0
Res. Res.
0
Res.
0
Res.
0
Res. Res.
0
Res.
0
Res.
0
Res. Res.
0
Res.
0
Res.
CNT[31:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CNT[31:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res. Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res. Res.
0
Res. Res.
0
Res.
0
Res.
0
Res.
0
Res. Res.
0
Res.
0
Res.
Res.
Res.
Res.
Res.
CNT[31:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
0
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
0
Res. Res.
Res.
Res.
Res.
Res.
0
Res. Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
0
Res. Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
0
Res. Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
0
Res. Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
0
Res. Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
0
Res. Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
0
Res. Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
0
Res. Res.
Res.
Res.
Res.
0
Res.
Res.
0
Res. Res.
Res.
Res.
0
Res.
Res.
0
Res. Res.
DDRPERFM_HWCFG
Res.
Reserved
0
Res. Res.
0x04C 0x3EC
Res.
DDRPERFM_CNT3
Reset value
Res.
0x048
Res.
Reserved
Res.
0x044
Res. Res.
DDRPERFM_CNT2
Reset value
Res.
0x040
Res.
Reserved
Res.
0x03C
Res.
DDRPERFM_CNT1
Reset value
Res.
0x038
Res.
Reserved
Res.
0x034
Res.
0x030
Res. Res.
Reserved
DDRPERFM_CNT0
Reset value
Res. Res.
0x024 0x02C
Res.
DDRPERFM_TCNT
Reset value
Res.
0x020
Res.
Reserved
Res.
0x01C
Res.
0x018
Reset value
Reset value
OVFF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
OVF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DDRPERFM_ICR
Res.
0x014
DDRPERFM_ISR
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
OVFIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DDRPERFM_IER
Res.
0x010
Res. Res.
Register
Res. Res.
Offset
Res.
Res.
0x3FC
Res.
0x3F8
Res.
0x3F4
DDRPERFM_VER
Res.
0x3F0
Res.
DDR performance monitor (DDRPERFM)
RM0442
Table 28. Power control register map and reset values (continued)
0
0
0
0
NCNT[3:0]
1 0 0
MAJREV[3:0
MINREV[3:0]
]
0 0 0 1 0 0 0 0
0
0
0
1
0
0
0
1
RM0442
9
Power control (PWR)
Power control (PWR)
The power control (PWR) provides an overv">