ST STM32F446xx advanced Arm®-based 32-bit MCUs Reference Manual

ST STM32F446xx advanced Arm®-based 32-bit MCUs are designed for a wide range of applications, including motor control, power conversion, and industrial automation. This powerful device offers a unique combination of performance, flexibility and features that make it ideal for demanding embedded applications.

With its high-performance Arm® Cortex®-M4 core running at up to 180MHz, the STM32F446xx delivers exceptional processing power. It also features a rich set of peripherals, including CAN, USB, Ethernet, and a variety of timers and ADCs. This makes it easy to connect to a wide range of sensors, actuators, and other devices.

The STM32F446xx is also highly flexible, with a variety of package options and memory configurations to choose from. This makes it easy to find the perfect device for your application. And with its low power consumption and advanced power management features, the STM32F446xx is ideal for battery-powered applications.

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Document

RM0390

Reference manual

STM32F446xx advanced Arm

-based 32-bit MCUs

Introduction

This document is addressed to application developers. It provides complete information on how to use the memory and peripherals of STM32F446xx microcontrollers.

The STM32F446xx constitute a family of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics refer to the corresponding datasheets.

For information on the Arm ® Cortex

Reference Manual.

® -M4 with FPU core refer to the Cortex ® -M4 Technical

STM32F446xx microcontrollers include ST state-of-the-art patented technology .

List of tables

RM0390

STM32F446xx register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Memory mapping vs. Boot mode/physical remap in STM32F446xx. . . . . . . . . . . . . . . . . . 62

Flash module organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Number of wait states according to CPU clock (HCLK) frequency . . . . . . . . . . . . . . . . . . . 66

Program/erase parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Flash interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Option byte organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 9.

Description of the option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 10.

Access versus read protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 11.

OTP area organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 12.

Flash register map and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 13.

CRC calculation unit register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 14.

Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 96

Table 15.

Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 16.

Sleep-now entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 17.

Stop operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 18.

Stop mode entry and exit for STM32F446xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 19.

Standby mode entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 20.

PWR - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 21.

RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 22.

Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 23.

Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Table 24.

RTC_AF1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Table 25.

RTC_AF2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Table 26.

GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Table 27.

SYSCFG register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Table 28.

DMA1 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Table 29.

DMA2 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Table 30.

Source and destination address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Table 31.

Source and destination address registers in double-buffer mode (DBM = 1) . . . . . . . . . . 214

Table 32.

Packing/unpacking and endian behavior (bit PINC = MINC = 1) . . . . . . . . . . . . . . . . . . . 215

Table 33.

Restriction on NDT versus PSIZE and MSIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Table 34.

FIFO threshold configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Table 35.

Possible DMA configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Table 36.

DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Table 37.

DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Table 38.

Vector table for STM32F446xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Table 39.

External interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . . 250

Table 40.

NOR/PSRAM bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Table 41.

NOR/PSRAM External memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Table 42.

NAND memory mapping and timing registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Table 43.

NAND bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Table 44.

SDRAM bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Table 45.

SDRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Table 46.

SDRAM address mapping with 8-bit data bus width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Table 47.

SDRAM address mapping with 16-bit data bus width. . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Table 48.

Programmable NOR/PSRAM access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

36/1347

RM0390 Rev 6

RM0390 List of tables

Table 49.

Non-multiplexed I/O NOR Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Table 50.

16-bit multiplexed I/O NOR Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Table 51.

Non-multiplexed I/Os PSRAM/SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Table 52.

16-Bit multiplexed I/O PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Table 53.

NOR Flash/PSRAM: example of supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Table 54.

FMC_BCRx bitfields (mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Table 55.

FMC_BTRx bitfields (mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Table 56.

FMC_BCRx bitfields (mode A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Table 57.

FMC_BTRx bitfields (mode A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Table 58.

FMC_BWTRx bitfields (mode A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Table 59.

FMC_BCRx bitfields (mode 2/B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Table 60.

FMC_BTRx bitfields (mode 2/B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Table 61.

FMC_BWTRx bitfields (mode 2/B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Table 62.

FMC_BCRx bitfields (mode C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

Table 63.

FMC_BTRx bitfields (mode C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Table 64.

FMC_BWTRx bitfields (mode C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Table 65.

FMC_BCRx bitfields (mode D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

Table 66.

FMC_BTRx bitfields (mode D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

Table 67.

FMC_BWTRx bitfields (mode D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Table 68.

FMC_BCRx bitfields (Muxed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

Table 69.

FMC_BTRx bitfields (Muxed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Table 70.

FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . . . . . . . . . . . . . . . . . . . 284

Table 71.

FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . . . . . . . . . . . . . . . . . . . 285

Table 72.

FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . . . . . . . . . . . . . . . . . . . 286

Table 73.

FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . . . . . . . . . . . . . . . . . . . 287

Table 74.

Programmable NAND Flash access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

Table 75.

8-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

Table 76.

16-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

Table 77.

Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

Table 78.

ECC result relevant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Table 79.

SDRAM signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

Table 80.

FMC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

Table 81.

QUADSPI pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

Table 82.

QUADSPI interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

Table 83.

QUADSPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

Table 84.

ADC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

Table 85.

Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

Table 86.

Configuring the trigger polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

Table 87.

External trigger for regular channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

Table 88.

External trigger for injected channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

Table 89.

ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

Table 90.

ADC global register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

Table 91.

ADC register map and reset values for each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

Table 92.

ADC register map and reset values (common ADC registers) . . . . . . . . . . . . . . . . . . . . . 401

Table 93.

DAC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403

Table 94.

External triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

Table 95.

DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

Table 96.

DCMI input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

Table 97.

Positioning of captured data bytes in 32-bit words (8-bit width) . . . . . . . . . . . . . . . . . . . . 427

Table 98.

Positioning of captured data bytes in 32-bit words (10-bit width) . . . . . . . . . . . . . . . . . . . 427

Table 99.

Positioning of captured data bytes in 32-bit words (12-bit width) . . . . . . . . . . . . . . . . . . . 427

RM0390 Rev 6

37/1347

List of tables RM0390

Table 100. Positioning of captured data bytes in 32-bit words (14-bit width) . . . . . . . . . . . . . . . . . . . 428

Table 101. Data storage in monochrome progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . 433

Table 102. Data storage in RGB progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434

Table 103. Data storage in YCbCr progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434

Table 104. Data storage in YCbCr progressive video format - Y extraction mode . . . . . . . . . . . . . . . 435

Table 105. DCMI interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

Table 106. DCMI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

Table 107. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

Table 108. TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

Table 109. Output control bits for complementary OCx and OCxN channels

with break feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

Table 110. TIM1&TIM8 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

Table 111. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547

Table 112. TIMx internal trigger connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562

Table 113. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

Table 114. TIM2 to TIM5 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579

Table 115. TIMx internal trigger connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605

Table 116. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

Table 117. TIM9/12 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

Table 118. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623

Table 119. TIM10/11/13/14 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626

Table 120. TIM6&TIM7 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639

Table 121. Min/max IWDG timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641

Table 122. IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645

Table 123. WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652

Table 124. Effect of low power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668

Table 125. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

Table 126. RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690

Table 127. STM32F446xx FMPI2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693

Table 128. FMPI2C input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695

Table 129. FMPI2C internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695

Table 130. Comparison of analog vs. digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697

Table 131. I2C-SMBus specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

Table 132. FMPI2C configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704

Table 133. I2C-SMBus specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715

Table 134. Examples of timing settings for fI2CCLK = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725

Table 135. Examples of timings settings for fI2CCLK = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725

Table 136. SMBus timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728

Table 137. SMBus with PEC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730

Table 138. Examples of TIMEOUTA settings for various FMPI2CCLK frequencies

(max t

TIMEOUT

= 25 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731

Table 139. Examples of TIMEOUTB settings for various FMPI2CCLK frequencies. . . . . . . . . . . . . . 731

Table 140. Examples of TIMEOUTA settings for various FMPI2CCLK frequencies

(max t

IDLE

= 50 µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731

Table 141. Effect of low-power modes on the FMPI2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741

Table 142. FMPI2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742

Table 143. FMPI2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757

Table 144. Maximum DNF[3:0] value to be compliant with Thd:dat(max) . . . . . . . . . . . . . . . . . . . . . 772

Table 145. SMBus vs. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774

Table 146. I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778

Table 147. I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793

Table 148. USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796

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Table 149. Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807

Table 150. Error calculation for programmed baud rates at f

PCLK

= 8 MHz or f

PCLK

= 12 MHz, oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810

Table 151. Error calculation for programmed baud rates at f

PCLK

= 8 MHz or f

PCLK

= 12 MHz, oversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810

Table 152. Error calculation for programmed baud rates at f

PCLK

= 16 MHz or f

PCLK

= 24 MHz, oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811

Table 153. Error calculation for programmed baud rates at f

PCLK

= 16 MHz or f

PCLK

= 24 MHz, oversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812

Table 154. Error calculation for programmed baud rates at f

PCLK

= 8 MHz or f

PCLK

= 16 MHz, oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812

Table 155. Error calculation for programmed baud rates at f

PCLK

= 8 MHz or f

PCLK

= 16 MHz, oversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813

Table 156. Error calculation for programmed baud rates at f

PCLK

= 30 MHz or f

PCLK

= 60 MHz, oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814

Table 157. Error calculation for programmed baud rates at f

PCLK

= 30 MHz or f

PCLK

= 60 MHz, oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814

Table 158. Error calculation for programmed baud rates at f

PCLK

= 42 MHz or f

PCLK

= 84 Hz, oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815

Table 159. Error calculation for programmed baud rates at f

PCLK

= 42 MHz or f

PCLK

= 84 MHz, oversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816

Table 160. USART receiver tolerance when DIV fraction is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817

Table 161. USART receiver tolerance when DIV_Fraction is different from 0 . . . . . . . . . . . . . . . . . . 818

Table 162. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820

Table 163. USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834

Table 164. USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845

Table 165. STM32F446xx SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847

Table 166. SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868

Table 167. Audio-frequency precision using standard 8 MHz HSE . . . . . . . . . . . . . . . . . . . . . . . . . . 879

Table 168. I

2 S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885

Table 169. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896

Table 170. Transition sequence for preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904

Table 171. Minimum SPDIFRX_CLK frequency versus audio sampling rate . . . . . . . . . . . . . . . . . . . 914

Table 172. Bit field property versus SPDIFRX state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916

Table 173. SPDIFRX interface register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931

Table 174. SAI internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934

Table 175. SAI input/output pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934

Table 176. External synchronization selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937

Table 177. Example of possible audio frequency sampling range . . . . . . . . . . . . . . . . . . . . . . . . . . . 943

Table 178. SOPD pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949

Table 179. Parity bit calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949

Table 180. Audio sampling frequency versus symbol rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950

Table 181. SAI interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959

Table 182. SAI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985

Table 183. SDIO I/O definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990

Table 184. Command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995

Table 185. Short response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996

Table 186. Long response format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996

Table 187. Command path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996

Table 188. Data token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999

Table 189. DPSM flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000

Table 190. Transmit FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001

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Table 191. Receive FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001

Table 192. Card status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012

Table 193. SD status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015

Table 194. Speed class code field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016

Table 195. Performance move field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017

Table 196. AU_SIZE field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017

Table 197. Maximum AU size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017

Table 198. Erase size field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018

Table 199. Erase timeout field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018

Table 200. Erase offset field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018

Table 201. Block-oriented write commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021

Table 202. Block-oriented write protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022

Table 203. Erase commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022

Table 204. I/O mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022

Table 205. Lock card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023

Table 206. Application-specific commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023

Table 207. R1 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024

Table 208. R2 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024

Table 209. R3 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025

Table 210. R4 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025

Table 211. R4b response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025

Table 212. R5 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026

Table 213. R6 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027

Table 214. Response type and SDIO_RESPx registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033

Table 215. SDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044

Table 216. Transmit mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060

Table 217. Receive mailbox mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060

Table 218. bxCAN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086

Table 219. OTG_HS speeds supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091

Table 220. OTG_FS speeds supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091

Table 221. OTG_FS/OTG_HS implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094

Table 222. OTG_FS input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096

Table 223. OTG_HS input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096

Table 224. OTG_FS/OTG_HS input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097

Table 225. Compatibility of STM32 low power modes with the OTG . . . . . . . . . . . . . . . . . . . . . . . . 1110

Table 226. Core global control and status registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1118

Table 227. Host-mode control and status registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119

Table 228. Device-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121

Table 229. Data FIFO (DFIFO) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1124

Table 230. Power and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1124

Table 231. TRDT values (FS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134

Table 232. TRDT values (HS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134

Table 233. Minimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175

Table 234. OTG_FS/OTG_HS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1205

Table 235. HDMI pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284

Table 236. Error handling timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1290

Table 237. TXERR timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291

Table 238. HDMI-CEC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1292

Table 239. HDMI-CEC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1300

Table 240. SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1304

Table 241. Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1304

Table 242. JTAG debug port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1308

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Table 243. 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . 1310

Table 244. Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1311

Table 245. ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1311

Table 246. DATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1311

Table 247. SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1312

Table 248. Cortex

® -M4 with FPU AHB-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1314

Table 249. Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1315

Table 250. Main ITM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1318

Table 251. Main ETM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1320

Table 252. Asynchronous TRACE pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1328

Table 253. Synchronous TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1328

Table 254. Flexible TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1329

Table 255. Important TPIU registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1332

Table 256. DBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1333

Table 257. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1337

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List of figures

List of figures

RM0390

Figure 1.

System architecture for STM32F446xx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 2.

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 3.

Flash memory interface connection inside system architecture . . . . . . . . . . . . . . . . . . . . . 64

Figure 4.

Sequential 32-bit instruction execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 5.

RDP levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 6.

PCROP levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 7.

CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 8.

Power supply overview for STM32F446xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 9.

Backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 10.

Power-on reset/power-down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 11.

BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 12.

PVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 13.

Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 14.

Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 15.

HSE/ LSE clock sources (hardware configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 16.

Frequency measurement with TIM5 in Input capture mode . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 17.

Frequency measurement with TIM11 in Input capture mode . . . . . . . . . . . . . . . . . . . . . . 126

Figure 18.

Basic structure of a 5 V tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Figure 19.

Selecting an alternate function on STM32F446xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Figure 20.

Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Figure 21.

Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Figure 22.

Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Figure 23.

High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Figure 24.

DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Figure 25.

Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Figure 26.

Peripheral-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 27.

Memory-to-peripheral mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Figure 28.

Memory-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Figure 29.

FIFO structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Figure 30.

External interrupt/event controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Figure 31.

External interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Figure 32.

FMC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Figure 33.

FMC memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Figure 34.

Mode 1 read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Figure 35.

Mode 1 write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Figure 36.

Mode A read access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Figure 37.

Mode A write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Figure 38.

Mode 2 and mode B read access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Figure 39.

Mode 2 write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Figure 40.

Mode B write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Figure 41.

Mode C read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Figure 42.

Mode C write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

Figure 43.

Mode D read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Figure 44.

Mode D write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Figure 45.

Muxed read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Figure 46.

Muxed write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

Figure 47.

Asynchronous wait during a read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

Figure 48.

Asynchronous wait during a write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

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Figure 49.

Wait configuration waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

Figure 50.

Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . . . . . . . . 284

Figure 51.

Synchronous multiplexed write mode waveforms - PSRAM (CRAM). . . . . . . . . . . . . . . . 286

Figure 52.

NAND Flash controller waveforms for common memory access . . . . . . . . . . . . . . . . . . . 298

Figure 53.

Access to non ‘CE don’t care’ NAND-Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Figure 54.

Burst write SDRAM access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

Figure 55.

Burst read SDRAM access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

Figure 56.

Logic diagram of Read access with RBURST bit set (CAS=1, RPIPE=0) . . . . . . . . . . . . 311

Figure 57.

Read access crossing row boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Figure 58.

Write access crossing row boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Figure 59.

Self-refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

Figure 60.

Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

Figure 61.

QUADSPI block diagram when dual-flash mode is disabled . . . . . . . . . . . . . . . . . . . . . . 326

Figure 62.

QUADSPI block diagram when dual-flash mode is enabled . . . . . . . . . . . . . . . . . . . . . . 327

Figure 63.

An example of a read command in quad mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

Figure 64.

An example of a DDR command in quad mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

Figure 65.

nCS when CKMODE = 0 (T = CLK period). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

Figure 66.

nCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . 339

Figure 67.

nCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . 340

Figure 68.

nCS when CKMODE = 1 with an abort (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . . 340

Figure 69.

Single ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

Figure 70.

ADC1 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

Figure 71.

ADC2 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

Figure 72.

ADC3 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

Figure 73.

Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

Figure 74.

Analog watchdog’s guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

Figure 75.

Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

Figure 76.

Right alignment of 12-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

Figure 77.

Left alignment of 12-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

Figure 78.

Left alignment of 6-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

Figure 79.

Multi ADC block diagram (1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

Figure 80.

Injected simultaneous mode on 4 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . . 375

Figure 81.

Injected simultaneous mode on 4 channels: triple ADC mode . . . . . . . . . . . . . . . . . . . . . 375

Figure 82.

Regular simultaneous mode on 16 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . 376

Figure 83.

Regular simultaneous mode on 16 channels: triple ADC mode . . . . . . . . . . . . . . . . . . . . 376

Figure 84.

Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode. . . . . . 377

Figure 85.

Interleaved mode on 1 channel in continuous conversion mode: triple ADC mode . . . . . 378

Figure 86.

Alternate trigger: injected group of each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

Figure 87.

Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . . . . . . . . . 379

Figure 88.

Alternate trigger: injected group of each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

Figure 89.

Alternate + regular simultaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

Figure 90.

Case of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

Figure 91.

Temperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 382

Figure 92.

DAC channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403

Figure 93.

DAC output buffer connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404

Figure 94.

Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

Figure 95.

Data registers in dual DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

Figure 96.

Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 406

Figure 97.

DAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408

Figure 98.

DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . . 408

Figure 99.

DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409

Figure 100. DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 409

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Figure 101. DCMI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

Figure 102. Top-level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

Figure 103. DCMI signal waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

Figure 104. Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

Figure 105. Frame capture waveforms in snapshot mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

Figure 106. Frame capture waveforms in continuous grab mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

Figure 107. Coordinates and size of the window after cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

Figure 108. Data capture waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

Figure 109. Pixel raster scan order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

Figure 110. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

Figure 111. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 451

Figure 112. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 451

Figure 113. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452

Figure 114. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

Figure 115. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

Figure 116. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

Figure 117. Counter timing diagram, update event when ARPE=0

(TIMx_ARR not preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

Figure 118. Counter timing diagram, update event when ARPE=1

(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

Figure 119. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

Figure 120. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

Figure 121. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

Figure 122. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

Figure 123. Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . . 458

Figure 124. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 459

Figure 125. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

Figure 126. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 460

Figure 127. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

Figure 128. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 461

Figure 129. Counter timing diagram, update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 461

Figure 130. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 463

Figure 131. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 464

Figure 132. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465

Figure 133. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

Figure 134. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

Figure 135. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467

Figure 136. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 468

Figure 137. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

Figure 138. Output stage of capture/compare channel (channels 1 to 3) . . . . . . . . . . . . . . . . . . . . . . 469

Figure 139. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 469

Figure 140. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

Figure 141. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

Figure 142. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

Figure 143. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

Figure 144. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

Figure 145. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 477

Figure 146. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 477

Figure 147. Output behavior in response to a break.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480

Figure 148. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481

Figure 149. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

Figure 150. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

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Figure 151. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 486

Figure 152. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 486

Figure 153. Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

Figure 154. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

Figure 155. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

Figure 156. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

Figure 157. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 492

Figure 158. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521

Figure 159. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 522

Figure 160. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 523

Figure 161. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524

Figure 162. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524

Figure 163. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524

Figure 164. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525

Figure 165. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 525

Figure 166. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 526

Figure 167. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527

Figure 168. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527

Figure 169. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527

Figure 170. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

Figure 171. Counter timing diagram, Update event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

Figure 172. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 529

Figure 173. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530

Figure 174. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 530

Figure 175. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530

Figure 176. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 531

Figure 177. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 531

Figure 178. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 532

Figure 179. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

Figure 180. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

Figure 181. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

Figure 182. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

Figure 183. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 536

Figure 184. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

Figure 185. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 537

Figure 186. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

Figure 187. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

Figure 188. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

Figure 189. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

Figure 190. Example of one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544

Figure 191. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546

Figure 192. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 548

Figure 193. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 548

Figure 194. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549

Figure 195. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550

Figure 196. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

Figure 197. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 552

Figure 198. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

Figure 199. Gating timer 2 with OC1REF of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553

Figure 200. Gating timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

Figure 201. Triggering timer 2 with update of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555

Figure 202. Triggering timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

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Figure 203. Triggering timer 1 and 2 with timer 1 TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

Figure 204. General-purpose timer block diagram (TIM9 and TIM12) . . . . . . . . . . . . . . . . . . . . . . . . 582

Figure 205. General-purpose timer block diagram (TIM10/11/13/14) . . . . . . . . . . . . . . . . . . . . . . . . . 583

Figure 206. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 585

Figure 207. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 585

Figure 208. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586

Figure 209. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

Figure 210. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

Figure 211. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

Figure 212. Counter timing diagram, update event when ARPE=0

(TIMx_ARR not preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

Figure 213. Counter timing diagram, update event when ARPE=1

(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

Figure 214. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 589

Figure 215. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

Figure 216. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

Figure 217. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 591

Figure 218. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592

Figure 219. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 592

Figure 220. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594

Figure 221. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

Figure 222. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

Figure 223. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598

Figure 224. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600

Figure 225. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601

Figure 226. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601

Figure 227. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628

Figure 228. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 630

Figure 229. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 630

Figure 230. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631

Figure 231. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632

Figure 232. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632

Figure 233. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632

Figure 234. Counter timing diagram, update event when ARPE = 0

(TIMx_ARR not preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633

Figure 235. Counter timing diagram, update event when ARPE=1

(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633

Figure 236. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 634

Figure 237. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641

Figure 238. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

Figure 239. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648

Figure 240. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654

Figure 241. FMPI2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694

Figure 242. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696

Figure 243. Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698

Figure 244. FMPI2C initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701

Figure 245. Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702

Figure 246. Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

Figure 247. Slave initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

Figure 248. Transfer sequence flowchart for FMPI2C slave transmitter,

NOSTRETCH= 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708

Figure 249. Transfer sequence flowchart for FMPI2C slave transmitter,

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NOSTRETCH= 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709

Figure 250. Transfer bus diagrams for FMPI2C slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710

Figure 251. Transfer sequence flowchart for slave receiver with NOSTRETCH=0 . . . . . . . . . . . . . . 711

Figure 252. Transfer sequence flowchart for slave receiver with NOSTRETCH=1 . . . . . . . . . . . . . . 712

Figure 253. Transfer bus diagrams for FMPI2C slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712

Figure 254. Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714

Figure 255. Master initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716

Figure 256. 10-bit address read access with HEAD10R=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716

Figure 257. 10-bit address read access with HEAD10R=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717

Figure 258. Transfer sequence flowchart for FMPI2C master transmitter for N ≤ 255 bytes. . . . . . . . . 718

Figure 259. Transfer sequence flowchart for FMPI2C master transmitter for N>255 bytes. . . . . . . . . 719

Figure 260. Transfer bus diagrams for FMPI2C master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . 720

Figure 261. Transfer sequence flowchart for FMPI2C master receiver for N ≤ 255 bytes . . . . . . . . . . 722

Figure 262. Transfer sequence flowchart for FMPI2C master receiver for N >255 bytes . . . . . . . . . . 723

Figure 263. Transfer bus diagrams for FMPI2C master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724

Figure 264. Timeout intervals for t

LOW:SEXT

, t

LOW:MEXT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728

Figure 265. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . . 732

Figure 266. Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . . . . . . . . . . . . . . . . . . 733

Figure 267. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC . . . . . . . . . . . . . 734

Figure 268. Bus transfer diagrams for SMBus slave receiver (SBC=1). . . . . . . . . . . . . . . . . . . . . . . . 735

Figure 269. Bus transfer diagrams for SMBus master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736

Figure 270. Bus transfer diagrams for SMBus master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738

Figure 271. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761

Figure 272. I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762

Figure 273. Transfer sequence diagram for slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764

Figure 274. Transfer sequence diagram for slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765

Figure 275. Transfer sequence diagram for master transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768

Figure 276. Transfer sequence diagram for master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770

Figure 277. I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779

Figure 278. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798

Figure 279. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799

Figure 280. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801

Figure 281. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802

Figure 282. Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803

Figure 283. Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806

Figure 284. Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807

Figure 285. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819

Figure 286. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819

Figure 287. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . . 822

Figure 288. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 823

Figure 289. USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824

Figure 290. USART data clock timing diagram (M=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824

Figure 291. USART data clock timing diagram (M=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825

Figure 292. RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825

Figure 293. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826

Figure 294. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827

Figure 295. IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829

Figure 296. IrDA data modulation (3/16) -Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829

Figure 297. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831

Figure 298. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832

Figure 299. Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832

Figure 300. RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833

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Figure 301. CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833

Figure 302. USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835

Figure 303. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848

Figure 304. Full-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849

Figure 305. Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850

Figure 306. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851

Figure 307. Master and three independent slaves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852

Figure 308. Multi-master application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853

Figure 309. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854

Figure 310. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856

Figure 311. TXE/RXNE/BSY behavior in master / full-duplex mode (BIDIMODE=0,

RXONLY=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859

Figure 312. TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0,

RXONLY=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860

Figure 313. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862

Figure 314. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863

Figure 315. TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866

Figure 316. I

2 S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869

Figure 317. Full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871

Figure 318. I

Figure 319. I

S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0). . . . . . . . . . . . . . . . . 872

S Philips standard waveforms (24-bit frame with CPOL = 0) . . . . . . . . . . . . . . . . . . . . . 872

Figure 320. Transmitting 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873

Figure 321. Receiving 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873

Figure 322. I

2 S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . . . . . . 873

Figure 323. Example of 16-bit data frame extended to 32-bit channel frame . . . . . . . . . . . . . . . . . . . 874

Figure 324. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . . . . . . . . . . . . . . . 874

Figure 325. MSB justified 24-bit frame length with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874

Figure 326. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 875

Figure 327. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . 875

Figure 328. LSB justified 24-bit frame length with CPOL = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875

Figure 329. Operations required to transmit 0x3478AE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876

Figure 330. Operations required to receive 0x3478AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876

Figure 331. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 876

Figure 332. Example of 16-bit data frame extended to 32-bit channel frame . . . . . . . . . . . . . . . . . . . 877

Figure 333. PCM standard waveforms (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877

Figure 334. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . . . . . . . . . . . . . . 877

Figure 335. Audio sampling frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878

Figure 336. I

2 S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878

Figure 337. SPDIFRX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898

Figure 338. S/PDIF sub-frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899

Figure 339. S/PDIF block format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899

Figure 340. S/PDIF Preambles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900

Figure 341. Channel coding example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900

Figure 342. SPDIFRX decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902

Figure 343. Noise filtering and edge detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902

Figure 344. Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904

Figure 345. Synchronization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906

Figure 346. Synchronization process scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907

Figure 347. SPDIFRX States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908

Figure 348. SPDIFRX_FMTx_DR register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910

Figure 349. Channel/user data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911

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Figure 350. S/PDIF overrun error when RXSTEO = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913

Figure 351. S/PDIF overrun error when RXSTEO = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914

Figure 352. SPDIFRX interface interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915

Figure 353. SAI functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933

Figure 354. Audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937

Figure 355. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . . . . . . . . 939

Figure 356. FS role is start of frame (FSDEF = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940

Figure 357. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . . . . . . . . . . . . . . . . . . . . . . 941

Figure 358. First bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941

Figure 359. Audio block clock generator overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942

Figure 360. AC’97 audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946

Figure 361. Example of typical AC’97 configuration on devices featuring at least

2 embedded SAIs (three external AC’97 decoders) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947

Figure 362. SPDIF format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948

Figure 363. SAI_xDR register ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949

Figure 364. Data companding hardware in an audio block in the SAI . . . . . . . . . . . . . . . . . . . . . . . . . 953

Figure 365. Tristate strategy on SD output line on an inactive slot . . . . . . . . . . . . . . . . . . . . . . . . . . . 954

Figure 366. Tristate on output data line in a protocol like I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955

Figure 367. Overrun detection error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956

Figure 368. FIFO underrun event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956

Figure 369. “No response” and “no data” operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988

Figure 370. (Multiple) block read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988

Figure 371. (Multiple) block write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988

Figure 372. Sequential read operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989

Figure 373. Sequential write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989

Figure 374. SDIO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989

Figure 375. SDIO adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991

Figure 376. Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992

Figure 377. SDIO_CK clock dephasing (BYPASS = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992

Figure 378. SDIO adapter command path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993

Figure 379. Command path state machine (SDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994

Figure 380. SDIO command transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995

Figure 381. Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997

Figure 382. Data path state machine (DPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998

Figure 383. CAN network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047

Figure 384. Dual-CAN block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048

Figure 385. bxCAN operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050

Figure 386. bxCAN in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051

Figure 387. bxCAN in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051

Figure 388. bxCAN in combined mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052

Figure 389. Transmit mailbox states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054

Figure 390. Receive FIFO states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055

Figure 391. Filter bank scale configuration - Register organization . . . . . . . . . . . . . . . . . . . . . . . . . . 1057

Figure 392. Example of filter numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058

Figure 393. Filtering mechanism example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059

Figure 394. CAN error state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061

Figure 395. Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063

Figure 396. CAN frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064

Figure 397. Event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065

Figure 398. CAN mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077

Figure 399. OTG_FS full-speed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095

Figure 400. OTG_HS high-speed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096

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Figure 401. OTG_FS/OTG_HS A-B device connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099

Figure 402. OTG_FS/OTG_HS peripheral-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101

Figure 403. OTG_FS/OTG_HS host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105

Figure 404. SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . . . . . . . . . . . . 1109

Figure 405. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111

Figure 406. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . 1112

Figure 407. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . . 1113

Figure 408. Interrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117

Figure 409. Transmit FIFO write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223

Figure 410. Receive FIFO read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224

Figure 411. Normal bulk/control OUT/SETUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226

Figure 412. Bulk/control IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1230

Figure 413. Normal interrupt OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233

Figure 414. Normal interrupt IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1238

Figure 415. Isochronous OUT transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240

Figure 416. Isochronous IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243

Figure 417. Normal bulk/control OUT/SETUP transactions - DMA . . . . . . . . . . . . . . . . . . . . . . . . . . 1245

Figure 418. Normal bulk/control IN transaction - DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1247

Figure 419. Normal interrupt OUT transactions - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1248

Figure 420. Normal interrupt IN transactions - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249

Figure 421. Normal isochronous OUT transaction - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250

Figure 422. Normal isochronous IN transactions - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251

Figure 423. Receive FIFO packet read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257

Figure 424. Processing a SETUP packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259

Figure 425. Bulk OUT transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266

Figure 426. TRDT max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1276

Figure 427. A-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277

Figure 428. B-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1278

Figure 429. A-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279

Figure 430. B-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1281

Figure 431. HDMI-CEC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284

Figure 432. Message structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1285

Figure 433. Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1285

Figure 434. Bit timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286

Figure 435. Signal free time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286

Figure 436. Arbitration phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287

Figure 437. SFT of three nominal bit periods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287

Figure 438. Error bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1288

Figure 439. Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289

Figure 440. TXERR detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291

Figure 441. Block diagram of STM32 MCU and Cortex ®

-M4 with FPU-level debug support . . . . . . 1301

Figure 442. SWJ debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303

Figure 443. JTAG TAP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1306

Figure 444. TPIU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1327

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The STM32F446xx devices have an Arm

® (a)

Cortex

-M4 with FPU core.

1.2 List of abbreviations for registers

The following abbreviations (b) are used in register descriptions: read-only (r) write-only (w) read/write (rw) read/clear write0 (rc_w0) read/clear write1 (rc_w1) read/clear write (rc_w) read/clear by read (rc_r) read/set by read (rs_r)

Software can read and write to this bit.

Software can only read this bit.

Software can only write to this bit. Reading this bit returns the reset value.

Software can read as well as clear this bit by writing 0. Writing 1 has no effect on the bit value.

Software can read as well as clear this bit by writing 1. Writing 0 has no effect on the bit value.

Software can read as well as clear this bit by writing to the register. The value written to this bit is not important.

Software can read this bit. Reading this bit automatically clears it to 0.

Writing this bit has no effect on the bit value.

Software can read this bit. Reading this bit automatically sets it to 1.

Writing this bit has no effect on the bit value.

read/set (rs) read/write once (rwo)

Software can read as well as set this bit. Writing 0 has no effect on the bit value.

Software can only write once to this bit and can also read it at any time.

Only a reset can return the bit to its reset value.

The software can toggle this bit by writing 1. Writing 0 has no effect.

toggle (t) read-only write trigger (rt_w1) Software can read this bit. Writing 1 triggers an event but has no effect on the bit value.

Reserved (Res.) Reserved bit, must be kept at reset value.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

b. This is an exhaustive list of all abbreviations applicable to STMicroelectronics microcontrollers, some of them may not be used in the current document.

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1.3 Glossary

This section gives a brief definition of acronyms and abbreviations used in this document:

 The CPU core integrates two debug ports:

– JTAG debug port ( JTAG-DP ) provides a 5-pin standard interface based on the

Joint Test Action Group (JTAG) protocol.

– SWD debug port ( SWD-DP ) provides a 2-pin (clock and data) interface based on the Serial Wire Debug (SWD) protocol.

For both the JTAG and SWD protocols, refer to the Cortex

-M4 with FPU

Technical Reference Manual.

 Word : data of 32-bit length.

 Half-word : data of 16-bit length.

 Byte : data of 8-bit length.

 Double word : data of 64-bit length.

 IAP (in-application programming) : IAP is the ability to re-program the Flash memory of a microcontroller while the user program is running.

 ICP (in-circuit programming) : ICP is the ability to program the Flash memory of a microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the device is mounted on the user application board.

 I-Code : this bus connects the Instruction bus of the CPU core to the Flash instruction

 interface. Prefetch is performed on this bus.

 D-Code : this bus connects the D-Code bus (literal load and debug access) of the CPU

 to the Flash data interface.

 Option bytes : product configuration bits stored in the Flash memory.

 OBL : option byte loader.

 AHB : advanced high-performance bus.

 CPU : refers to the Cortex

-M4 with FPUcore.

For availability of peripherals and their number across all sales types, refer to the particular device datasheet.

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2 Memory and bus architecture

Memory and bus architecture

In STM32F446xx, the main system consists of 32-bit multilayer AHB bus matrix that interconnects:

 Seven masters:

– Cortex

-M4 with FPU core I-bus, D-bus and S-bus

– DMA1 memory bus

– DMA2 memory bus

– DMA2 peripheral bus

– USB OTG HS DMA bus

 Seven slaves:

– Internal Flash memory ICode bus

– Internal Flash memory DCode bus

– Main internal SRAM1 (112 KB)

– Auxiliary internal SRAM2 (16 KB)

– AHB1 peripherals including AHB to APB bridges and APB peripherals

– AHB2 peripherals

– FMC / QUADSPI

The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even when several high-speed peripherals work simultaneously. This architecture is shown in

Figure 1 .

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Memory and bus architecture

ARM

Cortex-M4

Figure 1. System architecture for STM32F446xx devices

DMA1

DMA2

USB OTG

RM0390

ICODE

DCODE

Flash memory

SRAM1

112 Kbyte

SRAM2

16 Kbyte

AHB1 peripherals

AHB2 peripherals

FMC MemCtl/

QuadSPI

APB1

APB2

Bus matrix-S

MSv36042V1

2.1.1 I-bus

This bus connects the Instruction bus of the Cortex ® -M4 with FPU core to the BusMatrix.

This bus is used by the core to fetch instructions. The target of this bus is a memory containing code (internal Flash memory/SRAM or external memories through the FMC).

2.1.2 D-bus

This bus connects the databus of the Cortex ® -M4 with FPU to the BusMatrix. This bus is used by the core for literal load and debug access. The target of this bus is a memory containing code or data (internal Flash memory or external memories through the FMC).

2.1.3 S-bus

This bus connects the system bus of the Cortex ® -M4 with FPU core to a BusMatrix. This bus is used to access data located in a peripheral or in SRAM. Instructions may also be fetch on this bus (less efficient than ICode). The targets of this bus are the internal SRAM,

SRAM2, the AHB1 peripherals including the APB peripherals, the AHB2 peripherals and the external memories through the FMC and QUADSPI.

2.1.4 DMA memory bus

This bus connects the DMA memory bus master interface to the BusMatrix. It is used by the

DMA to perform transfer to/from memories. The targets of this bus are data memories:

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2.1.5

internal Flash, internal SRAMs (SRAM1, SRAM2) and external memories through the FMC and QUADSPI.

DMA peripheral bus

This bus connects the DMA peripheral master bus interface to the BusMatrix. This bus is used by the DMA to access AHB peripherals or to perform memory-to-memory transfers.

The targets of this bus are the AHB and APB peripherals plus data memories: internal

Flash, internal SRAMs (SRAM1, SRAM2) and external memories through the FMC and the

QUADSPI.

2.1.6 USB OTG HS DMA bus

This bus connects the USB OTG HS DMA master interface to the BusMatrix. This bus is used by the USB OTG DMA to load/store data to a memory. The targets of this bus are data memories: internal SRAMs (SRAM1, SRAM2), internal Flash memory, and external memories through the FMC and QUADSPI.

2.1.7 BusMatrix

The BusMatrix manages the access arbitration between masters. The arbitration uses a round-robin algorithm.

Note:

The two AHB/APB bridges, APB1 and APB2, provide full synchronous connections between the AHB and the two APB buses, allowing flexible selection of the peripheral frequency.

Refer to the device datasheets for more details on APB1 and APB2 maximum frequencies, and to

Table 1

for the address mapping of AHB and APB peripherals.

After each device reset, all peripheral clocks are disabled (except for the SRAM and Flash memory interface). Before using a peripheral you have to enable its clock in the

RCC_AHBxENR or RCC_APBxENR register.

When a 16- or an 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

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2.2.1 Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear

4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.

The addressable memory space is divided into eight main blocks, of 512 Mbytes each.

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2.2.2 Memory map and register boundary addresses

Figure 2. Memory map

Reserved

Cortex-M4 internal peripherals

0xE010 0000 - 0xFFFF FFFF

0xE000 0000 - 0xE00F FFFF

AHB3

Reserved

0x6000 0000 - 0xDFFF FFFF

0x5006 0C00 - 0x5FFF FFFF

0x5006 0BFF

AHB2

0xFFFF FFFF 512-Mbyte

Block 7

Cortex-M4

Internal peripherals

0xE000 0000

0xDFFF FFFF

512-Mbyte

Block 6

FMC

0xD000 0000

0xCFFF FFFF

512-Mbyte

Block 5

FMC/QuadSPI

0xA000 0000

0x9FFF FFFF

512-Mbyte

Block 4

FMC bank 3 and QuadSPI

0x8000 0000

0x7FFF FFFF

512-Mbyte

Block 3

FMC bank 1

0x6000 0000

0x5FFF FFFF

512-Mbyte

Block 2

Peripherals

0x4000 0000

0x3FFF FFFF

512-Mbyte

Block 1

SRAM

0x2000 0000

0x1FFF FFFF

512-Mbyte

Block 0

SRAM

0x0000 0000

Reserved

AHB1

Reserved

APB2

0x5000 0000

0x4008 0000 - 0x4FFF FFFF

0x4007 FFFF

0x4002 0000

0x4001 6C00 - 0x4001 FFFF

0x4001 6BFF

Reserved

SRAM (16 KB aliased

By bit-banding

SRAM (112 KB aliased

By bit-banding

Reserved

Option Bytes

Reserved

System memory

Reserved

Option bytes

Reserved

Flash memory

Reserved

Aliased to Flash, system memory or SRAM depending on the BOOT pins

0x2003 0000 - 0x3FFF FFFF

0x2002 0000 - 0x2002 FFFF

0x2001 C000 - 0x2001 FFFF

0x2000 0000 - 0x2001 BFFF

0x1FFF C008 - 0x1FFF FFFF

0x1FFF C000 - 0x1FFF C00F

0x1FFF 7A10 - 0x1FFF 7FFF

0x1FFF 0000 - 0x1FFF 7A0F

0x1FFE C008 - 0x1FFE FFFF

0x1FFE C000 - 0x1FFE C00F

0x1001 0000 - 0x1FFE BFFF

0x1000 0000 - 0x1000 FFFF

0x0820 0000 - 0x0FFF FFFF

0x0800 0000 - 0x081F FFFF

0x0020 0000 - 0x07FF FFFF

0x0000 0000 - 0x001F FFFF

Reserved

APB1

0x4001 0000

0x4000 8000 - 0x4000 FFFF

0x4000 7FFF

0x4000 0000

MS33841V1

All the memory map areas that are not allocated to on-chip memories and peripherals are considered “Reserved”. For the detailed mapping of available memory and register areas, refer to the following table.

The following table gives the boundary addresses of the peripherals available in the devices.

Boundary address

Table 1. STM32F446xx register boundary addresses

Peripheral Bus Register map

0xA000 0000 - 0xA000 0FFF FMC control register AHB3

Section 11.8.6: FMC register map on page 323

0xA000 1000 - 0xA000 1FFF QUADSPI register AHB3

Section 12.5.14: QUADSPI register map on page 354

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Table 1. STM32F446xx register boundary addresses (continued)

Boundary address Peripheral Bus Register map

0x5005 0000 - 0x5005 03FF

0x5000 0000 - 0x5003 FFFF

0x4004 0000 - 0x4007 FFFF

DCMI

USB OTG FS

USB OTG HS

AHB2

Section 15.5.12: DCMI register map on page 447

AHB2

Section 31.15.64: OTG_FS/OTG_HS register map on page 1205

0x4002 6400 - 0x4002 67FF

0x4002 6000 - 0x4002 63FF

0x4002 4000 - 0x4002 4FFF

0x4002 3C00 - 0x4002 3FFF

0x4002 3800 - 0x4002 3BFF

0x4002 3000 - 0x4002 33FF

0x4002 1C00 - 0x4002 1FFF

0x4002 1800 - 0x4002 1BFF

0x4002 1400 - 0x4002 17FF

0x4002 1000 - 0x4002 13FF

0x4002 0C00 - 0x4002 0FFF

0x4002 0800 - 0x4002 0BFF

0x4002 0400 - 0x4002 07FF

0x4002 0000 - 0x4002 03FF

0x4001 5C00 - 0x4001 5FFF

0x4001 5800 - 0x4001 5BFF

0x4001 4800 - 0x4001 4BFF

0x4001 4400 - 0x4001 47FF

0x4001 4000 - 0x4001 43FF

0x4001 3C00 - 0x4001 3FFF

DMA2

DMA1

BKPSRAM

Flash interface register

RCC

CRC

GPIOH

GPIOG

GPIOF

GPIOE

GPIOD

GPIOC

GPIOB

GPIOA

SAI2

SAI1

TIM11

TIM10

TIM9

EXTI

AHB1

APB2

Section 9.5.11: DMA register map on page 235

Section 3.8: Flash interface registers on page 80

Section 6.3.28: RCC register map on page 172

Section 4.4.4: CRC register map on page 91

Section 7.4.11: GPIO register map on page 193

Section 28.5.18: SAI register map on page 985

0x4001 3800 - 0x4001 3BFF SYSCFG

0x4001 3400 - 0x4001 37FF

0x4001 3000 - 0x4001 33FF

SPI4

SPI1

0x4001 2C00 - 0x4001 2FFF SDMMC

0x4001 2000 - 0x4001 23FF ADC1 - ADC2 - ADC3

0x4001 1400 - 0x4001 17FF USART6

0x4001 1000 - 0x4001 13FF

0x4001 0400 - 0x4001 07FF

0x4001 0000 - 0x4001 03FF

USART1

TIM8

TIM1

Section 18.5.12: TIM10/11/13/14 register map on page 626

APB2

Section 10.3.7: EXTI register map on page 250

Section 8.2.9: SYSCFG register maps on page 202

APB2

Section 26.7.10: SPI register map on page 896

Section 29.8.16: SDIO register map on page 1044

Section 13.14: ADC register map on page 399

APB2

Section 25.6.8: USART register map on page 845

Section 16.4.21: TIM1&TIM8 register map on page 518

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Table 1. STM32F446xx register boundary addresses (continued)

Boundary address Peripheral Bus Register map

0x4000 7400 - 0x4000 77FF

0x4000 7000 - 0x4000 73FF

0x4000 6C00 - 0x4000 6FFF

DAC

PWR

HDMI-CEC

Section 14.5.15: DAC register map on page 423

Section 5.5: PWR register map on page 115

Section 32.7.7: HDMI-CEC register map on page 1300

0x4000 6800 - 0x4000 6BFF

0x4000 6400 - 0x4000 67FF

0x4000 5C00 - 0x4000 5FFF

0x4000 5800 - 0x4000 5BFF

0x4000 5400 - 0x4000 57FF

0x4000 5000 - 0x4000 53FF

0x4000 4C00 - 0x4000 4FFF

0x4000 4800 - 0x4000 4BFF

0x4000 4400 - 0x4000 47FF

CAN2

CAN1

I2C3

I2C2

I2C1

UART5

UART4

USART3

USART2

Section 30.9.5: bxCAN register map on page 1086

Section 24.6.11: I2C register map on page 793

Section 25.6.8: USART register map on page 845

0x4000 4000 - 0x4000 43FF SPDIF-RX

0x4000 3C00 - 0x4000 3FFF

0x4000 3800 - 0x4000 3BFF

0x4000 3000 - 0x4000 33FF

SPI3 / I2S3

SPI2 / I2S2

IWDG

0x4000 2C00 - 0x4000 2FFF WWDG

0x4000 2800 - 0x4000 2BFF RTC & BKP Registers

0x4000 2000 - 0x4000 23FF TIM14

0x4000 1C00 - 0x4000 1FFF

0x4000 1800 - 0x4000 1BFF

0x4000 1400 - 0x4000 17FF

TIM13

TIM12

TIM7

0x4000 1000 - 0x4000 13FF

0x4000 0C00 - 0x4000 0FFF

0x4000 0800 - 0x4000 0BFF

0x4000 0400 - 0x4000 07FF

0x4000 0000 - 0x4000 03FF

TIM6

TIM5

TIM4

TIM3

TIM2

APB1

Section 27.5.10: SPDIFRX interface register map on page 931

Section 26.7.10: SPI register map on page 896

Section 20.4.5: IWDG register map on page 645

Section 21.6.4: WWDG register map on page 652

Section 22.6.21: RTC register map on page 690

Section 18.5.12: TIM10/11/13/14 register map on page 626

Section 19.4.9: TIM6&TIM7 register map on page 639

Section 17.4.21: TIMx register map on page 579

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The STM32F446xx feature 4 Kbytes of backup SRAM (see

Section 5.1.2: Battery backup domain

) plus 128 Kbytes of system SRAM.

The embedded SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits).

Read and write operations are performed at CPU speed with 0 wait state. The embedded

SRAM is divided into up to two blocks:

 SRAM1 and SRAM2 mapped at address 0x2000 0000 and accessible by all AHB masters.

The AHB masters support concurrent SRAM accesses (from the USB OTG HS): for instance, the USB OTG HS can read/write from/to SRAM2 while the CPU is reading/writing from/to SRAM1.

The CPU can access the SRAM1 and SRAM2 through the System bus or through the

I-Code/D-Code buses when boot from SRAM is selected or when physical remap is selected (

Section 8.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP)

in the

SYSCFG controller). To get the maximum performance on SRAM execution, physical remap should be selected (boot or software selection).

The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. It accelerates code execution with a system of instruction prefetch and cache lines.

The Flash memory is organized as follows:

 A main memory block divided into sectors.

 System memory from which the device boots in System memory boot mode

 512 OTP (one-time programmable) bytes for user data.

 Option bytes to configure read and write protection, BOR level, watchdog software/hardware and reset when the device is in Standby or Stop mode.

Refer to Section 3: Embedded Flash memory interface for more details.

The Cortex ® -M4 with FPU memory map includes two bit-band regions. These regions map each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region.

In the STM32F446xx devices both the peripheral registers and the SRAM are mapped to a bit-band region, so that single bit-band write and read operations are allowed. The operations are only available for Cortex ® -M4 with FPU accesses, and not from other bus masters (e.g. DMA).

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A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region. The mapping formula is: bit_word_addr = bit_band_base + ( byte_offset x 32) + ( bit_number × 4) where:

– bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit

– bit_band_base is the starting address of the alias region

– byte_offset is the number of the byte in the bit-band region that contains the targeted bit

– bit_number is the bit position (0-7) of the targeted bit

Example

The following example shows how to map bit 2 of the byte located at SRAM address

0x20000300 to the alias region:

0x22006008 = 0x22000000 + (0x300*32) + (2*4)

Writing to address 0x22006008 has the same effect as a read-modify-write operation on bit

2 of the byte at SRAM address 0x20000300.

Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM address 0x20000300 (0x01: bit set; 0x00: bit reset).

For more information on bit-banding, refer to the Cortex

-M4 with FPU programming manual (see

Embedded bootloader

The embedded bootloader mode is used to reprogram the Flash memory using one of the following serial interfaces:

 USART

 CAN2

 I2C

 SPI

 USB OTG FS in Device mode (DFU: device firmware upgrade).

The USART peripherals operate at the internal 16 MHz oscillator (HSI) frequency, while the

CAN and USB OTG FS require an external clock (HSE) multiple of 1 MHz (ranging from 4 to

26 MHz).

The embedded bootloader code is located in system memory. It is programmed by ST during production. For additional information, refer to application note AN2606.

Physical remap in STM32F446xx

Once the boot pins are selected, the application software can modify the memory accessible in the code area (in this way the code can be executed through the ICode bus in

place of the System bus). This modification is performed by programming the Section 8.2.1:

SYSCFG memory remap register (SYSCFG_MEMRMP)

in the SYSCFG controller.

The following memories can thus be remapped:

 Main Flash memory

 System memory

 Embedded SRAM1 (112 KB)

 FMC bank 1 (NOR/PSRAM 1 and 2)

 FMC SDRAM bank 1

Table 3. Memory mapping vs. Boot mode/physical remap in STM32F446xx

Addresses

Boot/Remap in main Flash memory

Boot/Remap in embedded SRAM

Boot/Remap in

System memory

Remap in FMC

0x2001 C000 - 0x2001 FFFF

0x2000 0000 - 0x2001 BFFF

0x1FFF 0000 - 0x1FFF 77FF

0x0810 0000 - 0x0FFF FFFF

0x0800 0000 - 0x081F FFFF

SRAM2 (16 KB)

SRAM1 (112 KB)

System memory

Reserved

Flash memory

SRAM2 (16 KB) SRAM2 (16 KB) SRAM2 (16 KB)

SRAM1 (112 KB) SRAM1 (112 KB) SRAM1 (112 KB)

System memory System memory

Reserved Reserved

Flash memory Flash memory

System memory

Reserved

Flash memory

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Table 3. Memory mapping vs. Boot mode/physical remap in STM32F446xx (continued)

Addresses

Boot/Remap in main Flash memory

Boot/Remap in embedded SRAM

Boot/Remap in

System memory

Remap in FMC

0x0400 0000 - 0x07FF FFFF

0x0000 0000 -

0x001F FFFF

(1)(2)

Reserved

Flash (512 KB)

Aliased

Reserved

SRAM1 (112 KB)

Aliased

Reserved

System memory

(30 KB) Aliased

FMC bank 1

NOR/PSRAM 2

(128 MB Aliased)

FMC bank 1

NOR/PSRAM 1

(128 MB Aliased) or FMC SDRAM bank 1 (128 MB

Aliased)

1. When the FMC is remapped at address 0x0000 0000, only the first two regions of bank 1 memory controller (bank 1

NOR/PSRAM 1 and NOR/PSRAM 2) or SDRAM bank 1 can be remapped. In remap mode, the CPU can access the external memory via ICode bus instead of System bus which boosts up the performance.

2. Even when aliased in the boot memory space, the related memory is still accessible at its original memory space.

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Embedded Flash memory interface

3 Embedded Flash memory interface

RM0390

3.1 Introduction

The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms.

The Flash memory interface accelerates code execution with a system of instruction prefetch and cache lines.

 Flash memory read operations

 Flash memory program/erase operations

 Read / write protections

 Prefetch on I-Code

 64 cache lines of 128 bits on I-Code

 8 cache lines of 128 bits on D-Code

Figure 3 shows the Flash memory interface connection inside the system architecture.

Figure 3. Flash memory interface connection inside system architecture

Cortex-M4 with FPU

I-Code bus

Cortex core

D-code bus

I -Code

D-Code

S bus

DMA1

DMA2

AHB

32-bit instruction bus

Flash interface

Flash memory bus

128 bits

Flash memory

AHB

32-bit data bus

FLITF registers

AHB

32-bit system bus

AHB periph1

SRAM and

External memories

AHB periph2

USB HS

Access to instruction in Flash memory

Access to data and literal pool in Flash memory

FLITF register access

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3.3

Embedded Flash memory interface

Embedded Flash memory

The Flash memory has the following main features:

 Capacity up to 512 KBytes

 128 bits wide data read

 Byte, half-word, word and double word write

 Sector and mass erase

 Memory organization

The Flash memory is organized as follows:

– A main memory block divided into 4 sectors of 16 KBytes, 1 sector of 64 KBytes, and 3 sectors of 128 Kbytes

– System memory from which the device boots in System memory boot mode

– 512 OTP (one-time programmable) bytes for user data

The OTP area contains 16 additional bytes used to lock the corresponding OTP data block.

– Option bytes to configure read and write protection, BOR level, watchdog software/hardware and reset when the device is in Standby or Stop mode.

 Low-power modes (for details refer to the Power control (PWR) section of the reference manual)

Block

Table 4. Flash module organization

Name

Main memory

Sector 0

Sector 1

Sector 2

Sector 3

Sector 4

Sector 5

Sector 6

Sector 7

System memory

OTP area

Option bytes

Block base addresses

0x0800 0000 - 0x0800 3FFF

0x0800 4000 - 0x0800 7FFF

0x0800 8000 - 0x0800 BFFF

0x0800 C000 - 0x0800 FFFF

0x0801 0000 - 0x0801 FFFF

0x0802 0000 - 0x0803 FFFF

0x0804 0000 - 0x0805 FFFF

0x0806 0000 - 0x0807 FFFF

0x1FFF 0000 - 0x1FFF 77FF

0x1FFF 7800 - 0x1FFF 7A0F

0x1FFF C000 - 0x1FFF C00F

Size

16 Kbytes

64 Kbytes

128 Kbytes

30 Kbytes

528 bytes

16 bytes

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3.4.1

Note:

Relation between CPU clock frequency and Flash memory read time

To correctly read data from Flash memory, the number of wait states (LATENCY) must be correctly programmed in the Flash access control register (FLASH_ACR) according to the frequency of the CPU clock (HCLK) and the supply voltage of the device.

The prefetch buffer must be disabled when the supply voltage is below 2.1 V. The correspondence between wait states and CPU clock frequency is given in

Table 5

On STM32F446xx devices:

- when VOS[1:0] = '0x01', the maximum value of f

HCLK

is 120 MHz.

- when VOS[1:0] = '0x10', the maximum value of f

HCLK

168 MHz by activating the over-drive mode.

is 144 MHz. It can be extended to

- when VOS[1:0] = '0x11, the maximum value of f

HCLK

is 168 MHz. It can be extended to

180 MHz by activating the over-drive mode. The over-drive mode is not available when V

DD ranges from 1.8 to 2.1 V (refer to

Section 5.1.3: Voltage regulator

for details on how to activate the over-drive mode).

Table 5. Number of wait states according to CPU clock (HCLK) frequency

HCLK (MHz)

Wait states (WS)

(LATENCY)

Voltage range

2.7 V - 3.6 V

Voltage range

2.4 V - 2.7 V

Voltage range

2.1 V - 2.4 V

Voltage range

1.8 V - 2.1 V

Prefetch OFF

0 WS (1 CPU cycle)

1 WS (2 CPU cycles)

2 WS (3 CPU cycles)

3 WS (4 CPU cycles)

4 WS (5 CPU cycles)

5 WS (6 CPU cycles)

6 WS (7 CPU cycles)

7 WS (8 CPU cycles)

8 WS (9 CPU cycles)

0 < HCLK ≤ 30

30 < HCLK ≤ 60

60 < HCLK ≤ 90

90 < HCLK ≤ 120

0 <HCLK ≤

24 < HCLK

48 < HCLK

72 < HCLK

≤

0 <HCLK ≤

22 < HCLK

44 < HCLK

66 < HCLK

≤

120 < HCLK ≤ 150 96 < HCLK ≤ 120 88 < HCLK ≤ 110

150 < HCLK ≤ 180 120 < HCLK ≤ 144 110 < HCLK ≤ 132

144 < HCLK ≤ 168 132 < HCLK ≤ 154

168 <HCLK ≤ 180 154 <HCLK ≤ 176

176 <HCLK ≤ 180

0 < HCLK ≤ 20

20 < HCLK ≤ 40

40 < HCLK ≤ 60

60 < HCLK ≤ 80

80 < HCLK ≤ 100

100 < HCLK ≤ 120

120 < HCLK ≤ 140

140 < HCLK ≤ 160

160 < HCLK ≤ 168

After reset, the CPU clock frequency is 16 MHz and 0 wait state (WS) is configured in the

FLASH_ACR register.

It is highly recommended to use the following software sequences to tune the number of wait states needed to access the Flash memory with the CPU frequency.

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Note:

Embedded Flash memory interface

Increasing the CPU frequency

Program the new number of wait states to the LATENCY bits in the FLASH_ACR register

2. Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register

3. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register

4. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR

5. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are taken into account by reading the clock source status (SWS bits) or/and the AHB prescaler value (HPRE bits), respectively, in the RCC_CFGR register.

Decreasing the CPU frequency

Modify the CPU clock source by writing the SW bits in the RCC_CFGR register

2. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR

3. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are taken into account by reading the clock source status (SWS bits) or/and the AHB prescaler value (HPRE bits), respectively, in the RCC_CFGR register

4. Program the new number of wait states to the LATENCY bits in FLASH_ACR

5. Check that the new number of wait states is used to access the Flash memory by reading the FLASH_ACR register

A change in CPU clock configuration or wait state (WS) configuration may not be effective straight away. To make sure that the current CPU clock frequency is the one you have configured, you can check the AHB prescaler factor and clock source status values. To make sure that the number of WS you have programmed is effective, you can read the

FLASH_ACR register.

The proprietary Adaptive real-time (ART) memory accelerator is optimized for STM32 industry-standard ARM

Cortex

-M4 with FPU processors. It balances the inherent performance advantage of the ARM

Cortex

-M4 with FPU over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher operating frequencies.

To release the processor full performance, the accelerator implements an instruction prefetch queue and branch cache which increases program execution speed from the 128bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the

ART accelerator is equivalent to 0 wait state program execution from Flash memory at a

CPU frequency up to 180 MHz.

Instruction prefetch

Each Flash memory read operation provides 128 bits from either four instructions of 32 bits or 8 instructions of 16 bits according to the program launched. So, in case of sequential code, at least four CPU cycles are needed to execute the previous read instruction line.

Prefetch on the I-Code bus can be used to read the next sequential instruction line from the

Flash memory while the current instruction line is being requested by the CPU. Prefetch is enabled by setting the PRFTEN bit in the FLASH_ACR register. This feature is useful if at least one wait state is needed to access the Flash memory.

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Figure 4 shows the execution of sequential 32-bit instructions with and without prefetch

when 3 WSs are needed to access the Flash memory.

Figure 4. Sequential 32-bit instruction execution

WAIT

2 ins 1 fetch

F D E

1 1 1

F D E

2 2 2

@ F D E

3 3 3 3

@ F D E

4 4 4 4

WAIT

6 ins 2 fetch ins 3 fetch ins 4 fetch

Without prefetch ins 5 fetch

F D E

5 5 5

F D E

6 6 6

@ F D

7 7 7

@ F

8 8 ins 6 fetch ins 7 fetch ins 8 fetch

Read ins 1, 2, 3, 4 Gives ins 1, 2, 3, 4 Read ins 5, 6, 7, 8 Gives ins 5, 6, 7, 8

Wait data

F D E

1 1 1

F D E

2 2 2

@ F D

3 3 3

@ F

4 4

D E

4 4

F D E

5 5 5

@ F D E

6 6 6

@ F D

7 7 7

@ F

8 8 ins 1 fetch ins 2 fetch ins 3 ins 4 ins 5 fetch fetch fetch ins 6 ins 7 fetch fetch ins 8 fetch

Read ins 1, 2, 3, 4 Gives ins 1, 2, 3, 4 Gives ins 5, 6, 7, 8

Read ins 5, 6, 7, 8 Read ins 9, 10, ...

With prefetch

Cortex-M4 pipeline

@ F D E

AHB protocol

@ : address requested

F: Fetch stage

D: Decode stage

E: Execute stage

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When the code is not sequential (branch), the instruction may not be present in the currently used instruction line or in the prefetched instruction line. In this case (miss), the penalty in terms of number of cycles is at least equal to the number of wait states.

Instruction cache memory

To limit the time lost due to jumps, it is possible to retain 64 lines of 128 bits in an instruction cache memory. This feature can be enabled by setting the instruction cache enable (ICEN) bit in the FLASH_ACR register. Each time a miss occurs (requested data not present in the currently used instruction line, in the prefetched instruction line or in the instruction cache memory), the line read is copied into the instruction cache memory. If some data contained in the instruction cache memory are requested by the CPU, they are provided without inserting any delay. Once all the instruction cache memory lines have been filled, the LRU

(least recently used) policy is used to determine the line to replace in the instruction memory cache. This feature is particularly useful in case of code containing loops.

Data management

Literal pools are fetched from Flash memory through the D-Code bus during the execution stage of the CPU pipeline. The CPU pipeline is consequently stalled until the requested literal pool is provided. To limit the time lost due to literal pools, accesses through the AHB databus D-Code have priority over accesses through the AHB instruction bus I-Code.

If some literal pools are frequently used, the data cache memory can be enabled by setting the data cache enable (DCEN) bit in the FLASH_ACR register. This feature works like the instruction cache memory, but the retained data size is limited to 8 rows of 128 bits.

Data in user configuration sector are not cacheable.

3.5

3.5.1

Erase and program operations

For any Flash memory program operation (erase or program), the CPU clock frequency

(HCLK) must be at least 1 MHz. The contents of the Flash memory are not guaranteed if a device reset occurs during a Flash memory operation.

Any attempt to read the Flash memory on STM32F4xx while it is being written or erased, causes the bus to stall. Read operations are processed correctly once the program operation has completed. This means that code or data fetches cannot be performed while a write/erase operation is ongoing.

Unlocking the Flash control register

After reset, write is not allowed in the Flash control register (FLASH_CR) to protect the

Flash memory against possible unwanted operations due, for example, to electric disturbances. The following sequence is used to unlock this register:

Write KEY1 = 0x45670123 in the Flash key register (FLASH_KEYR)

2. Write KEY2 = 0xCDEF89AB in the Flash key register (FLASH_KEYR)

Any wrong sequence will return a bus error and lock up the FLASH_CR register until the next reset.

The FLASH_CR register can be locked again by software by setting the LOCK bit in the

FLASH_CR register.

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The FLASH_CR register is not accessible in write mode when the BSY bit in the FLASH_ register is set. Any attempt to write to it with the BSY bit set will cause the AHB bus to stall until the BSY bit is cleared.

The maximum parallelism size is configured through the PSIZE field in the FLASH_CR register. It represents the number of bytes to be programmed each time a write operation occurs to the Flash memory. PSIZE is limited by the supply voltage and by whether the external V

supply is used or not. It must therefore be correctly configured in the

FLASH_CR register before any programming/erasing operation.

A Flash memory erase operation can only be performed by sector or for the whole Flash memory (mass erase). The erase time depends on PSIZE programmed value. For more details on the erase time, refer to the electrical characteristics section of the device datasheet.

Table 6 provides the correct PSIZE values.

Voltage range

Maximum parallelism size

PSIZE(1:0)

Table 6. Program/erase parallelism

2.7 to 3.6 V, with external V

PP x64

2.7 to 3.6 V 2.4 to 2.7 V 2.1 to 2.4 V 1.7 to 2.1 V x32 x16 x8

11 10 01 00

Note: Any program or erase operation started with inconsistent program parallelism/voltage range settings may lead to unpredicted results. Even if a subsequent read operation indicates that the logical value was effectively written to the memory, this value may be not retained.

To use V

, an external high-voltage supply (between 8 and 9 V) must be applied to the V

PP pad. The external supply must be able to sustain this voltage range even if the DC consumption exceeds 10 mA. It is advised to limit the use of V

PP the factory line. The V

Flash memory might be damaged.

to initial programming on

supply must not be applied for more than an hour, otherwise the

3.5.3 Erase

The Flash memory erase operation can be performed at sector level or on the whole Flash memory (mass erase). Mass erase does not affect the OTP sector or the configuration sector.

Sector Erase

To erase a sector, follow the procedure below:

Check that no Flash memory operation is ongoing by checking the BSY bit in the

FLASH_SR register

2. Set the SER bit and select the sector out of the 7 sectors in the main memory block you wish to erase (SNB) in the FLASH_CR register

3. Set the STRT bit in the FLASH_CR register

4. Wait for the BSY bit to be cleared.

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Note:

Mass Erase

To perform Mass Erase, the following sequence is recommended:

Check that no Flash memory operation is ongoing by checking the BSY bit in the

FLASH_SR register

2. Set the MER bit in the FLASH_CR register

3. Set the STRT bit in the FLASH_CR register

4. Wait for the BSY bit to be cleared.

If MER and SER bits are both set in the FLASH_CR register, mass erase is performed.

If both MER and SER bits are reset and the STRT bit is set, an unpredictable behavior may occur without generating any error flag. This condition should be forbidden.

3.5.4 Programming

Note:

Standard programming

The Flash memory programming sequence is as follows:

Check that no main Flash memory operation is ongoing by checking the BSY bit in the

FLASH_SR register.

2. Set the PG bit in the FLASH_CR register

3. Perform the data write operation(s) to the desired memory address (inside main memory block or OTP area):

– Byte access in case of x8 parallelism

– Half-word access in case of x16 parallelism

– Word access in case of x32 parallelism

– Double word access in case of x64 parallelism

4. Wait for the BSY bit to be cleared.

Successive write operations are possible without the need of an erase operation when changing bits from ‘1’ to ‘0’. Writing ‘1’ requires a Flash memory erase operation.

If an erase and a program operation are requested simultaneously, the erase operation is performed first.

Programming errors

It is not allowed to program data to the Flash memory that would cross the 128-bit row boundary. In such a case, the write operation is not performed and a program alignment error flag (PGAERR) is set in the FLASH_SR register.

The write access type (byte, half-word, word or double word) must correspond to the type of parallelism chosen (x8, x16, x32 or x64). If not, the write operation is not performed and a program parallelism error flag (PGPERR) is set in the FLASH_SR register.

If the standard programming sequence is not respected (for example, if there is an attempt to write to a Flash memory address when the PG bit is not set), the operation is aborted and a program sequence error flag (PGSERR) is set in the FLASH_SR register.

Programming and caches

If a Flash memory write access concerns some data in the data cache, the Flash write access modifies the data in the Flash memory and the data in the cache.

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If an erase operation in Flash memory also concerns data in the data or instruction cache, you have to make sure that these data are rewritten before they are accessed during code execution. If this cannot be done safely, it is recommended to flush the caches by setting the

DCRST and ICRST bits in the FLASH_CR register.

The I/D cache should be flushed only when it is disabled (I/DCEN = 0).

3.5.5 Interrupts

Note:

Setting the end of operation interrupt enable bit (EOPIE) in the FLASH_CR register enables interrupt generation when an erase or program operation ends, that is when the busy bit

(BSY) in the FLASH_SR register is cleared (operation completed, correctly or not). In this case, the end of operation (EOP) bit in the FLASH_SR register is set.

If an error occurs during a program, an erase, or a read operation request, one of the following error flags is set in the FLASH_SR register:

 PGAERR, PGPERR, PGSERR (Program error flags)

 WRPERR (Protection error flag)

In this case, if the error interrupt enable bit (ERRIE) is set in the FLASH_SR register, an interrupt is generated and the operation error bit (OPERR) is set in the FLASH_SR register.

If several successive errors are detected (for example, in case of DMA transfer to the Flash memory), the error flags cannot be cleared until the end of the successive write requests.

Interrupt event

End of operation

Write protection error

Programming error

Table 7. Flash interrupt request

Event flag

EOP

WRPERR

PGAERR, PGPERR, PGSERR

Enable control bit

EOPIE

ERRIE

The option bytes are configured by the end user depending on the application requirements.

Table 8 shows the organization of these bytes inside the user configuration sector.

Address

0x1FFF C000

0x1FFF C008

Table 8. Option byte organization

[63:16] [15:0]

Reserved

ROP & user option bytes ( RDP & USER )

Write protection nWRP bits for sectors 0 to 7

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Table 9. Description of the option bytes

Option bytes (word, address 0x1FFF C000)

RDP: Read protection option byte.

The read protection is used to protect the software code stored in Flash memory.

Bits 15:8

0xAA: Level 0, no protection

0xCC: Level 2, chip protection (debug and boot from RAM features disabled)

Others: Level 1, read protection of memories (debug features limited)

USER: User option byte

This byte is used to configure the following features:

Select the watchdog event: Hardware or software

Reset event when entering the Stop mode

Reset event when entering the Standby mode

Bit 7

Bit 6

Bit 5

Bit 4

Bits 3:2

Bits 1:0

Bit 15

Bits 14:8 nRST_STDBY

0: Reset generated when entering the Standby mode

1: No reset generated nRST_STOP

0: Reset generated when entering the Stop mode

1: No reset generated

WDG_SW

0: Hardware watchdog

1: Software watchdog

0x0: Not used. Do not change the default value of this bit which is “0” out of fab.

BOR_LEV: BOR reset Level

These bits contain the supply level threshold that activates/releases the reset.

They can be written to program a new BOR level value into Flash memory.

00: BOR Level 3 (VBOR3), brownout threshold level 3

01: BOR Level 2 (VBOR2), brownout threshold level 2

10: BOR Level 1 (VBOR1), brownout threshold level 1

11: BOR off, POR/PDR reset threshold level is applied

For full details on BOR characteristics, refer to the Electrical characteristics section of the product datasheet.

0x1: Not used

Option bytes (word, address 0x1FFF C008)

SPRMOD: Selection of Protection Mode of nWPRi bits

0: nWPRi bits used for sector i write protection (Default)

1: nWPRi bits used for sector i PCROP protection (Sector)

Reserved

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Table 9. Description of the option bytes (continued) nWRP : Flash memory write protection option bytes

Sectors 0 to 7 can be write protected.

Bits 7:0 nWRPi

If SPRMOD is reset (default value) :

0: Write protection active on sector i.

1: Write protection not active on sector i.

If SPRMOD is set (active):

0: PCROP protection not active on sector i.

1: PCROP protection active on sector i.

3.6.2

Note:

RM0390

Programming user option bytes

To run any operation on this sector, the option lock bit (OPTLOCK) in the Flash option control register (FLASH_OPTCR) must be cleared. To be allowed to clear this bit, you have to perform the following sequence:

Write OPTKEY1 = 0x0819 2A3B in the Flash option key register (FLASH_OPTKEYR)

2. Write OPTKEY2 = 0x4C5D 6E7F in the Flash option key register (FLASH_OPTKEYR)

The user option bytes can be protected against unwanted erase/program operations by setting the OPTLOCK bit by software.

Modifying user option bytes

To modify the user option value, follow the sequence below:

Check that no Flash memory operation is ongoing by checking the BSY bit in the

FLASH_SR register

2. Write the desired option value in the FLASH_OPTCR register.

3. Set the option start bit (OPTSTRT) in the FLASH_OPTCR register

4. Wait for the BSY bit to be cleared.

The value of an option is automatically modified by first erasing the user configuration sector and then programming all the option bytes with the values contained in the FLASH_OPTCR register.

The user area in the Flash memory can be protected against read operations by an entrusted code. Three read protection levels are defined:

 Level 0: no read protection

When the read protection level is set to Level 0 by writing 0xAA into the read protection option byte (RDP), all read/write operations (if no write protection is set) from/to the

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Flash memory are possible in all boot configurations (Flash user boot, debug or boot from RAM).

 Level 1: read protection enabled

It is the default read protection level after option byte erase. The read protection Level

1 is activated by writing any value (except for 0xAA and 0xCC used to set Level 0 and

Level 2, respectively) into the RDP option byte. When the read protection Level 1 is set:

– No access (read, erase, program) to Flash memory can be performed while the debug feature is connected or while booting from RAM or system memory bootloader. A bus error is generated in case of read request.

– When booting from Flash memory, accesses (read, erase, program) to Flash memory from user code are allowed.

When Level 1 is active, programming the protection option byte (RDP) to Level 0 causes the Flash memory to be mass-erased. As a result the user code area is cleared before the read protection is removed. The mass erase only erases the user code area.

The other option bytes including write protections remain unchanged from before the mass-erase operation. The OTP area is not affected by mass erase and remains unchanged. Mass erase is performed only when Level 1 is active and Level 0 requested. When the protection level is increased (0->1, 1->2, 0->2) there is no mass erase.

 Level 2: debug/chip read protection disabled

The read protection Level 2 is activated by writing 0xCC to the RDP option byte. When the read protection Level 2 is set:

– All protections provided by Level 1 are active.

– Booting from RAM or system memory bootloader is no more allowed.

– JTAG, SWV (single-wire viewer), ETM, and boundary scan are disabled.

– User option bytes can no longer be changed.

– When booting from Flash memory, accesses (read, erase and program) to Flash memory from user code are allowed.

Memory read protection Level 2 is an irreversible operation. When Level 2 is activated, the level of protection cannot be decreased to Level 0 or Level 1.

The JTAG port is permanently disabled when Level 2 is active (acting as a JTAG fuse). As a consequence, boundary scan cannot be performed. STMicroelectronics is not able to perform analysis on defective parts on which the Level 2 protection has been set.

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Memory area

Table 10. Access versus read protection level

Protection

Level

Debug features, Boot from RAM or from System memory bootloader

Booting from Flash memory

Read Write Erase Read Write Erase

Main Flash Memory

Option Bytes

OTP

Level 1

Level 2

Level 1

Level 2

Level 1

Level 2

YES

(1)

YES

1. The main Flash memory is only erased when the RDP changes from level 1 to 0. The OTP area remains unchanged.

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Figure 5 shows how to go from one RDP level to another.

Figure 5. RDP levels

RDP /= AAh & /= CCh

Others options modified

Write options including

RDP = CCh

D e

P v

= e l

C h

Options write (RDP level increase) includes

- Options erase

- New options program

Options write (RDP level decrease) includes

- Mass erase

- Options erase

- New options program

Level 1

RDP /= AAh

RDP /= CCh default

Write optionsincluding

RDP /= CCh & /= AAh

L e v e l 0

R D P = A A h

Write options including

RDP = CCh

Write options including

RDP = AAh

Others option(s) modified

Options write (RDP level identical) includes

- Options erase

- New options program ai16045

Note:

Up to 7 user sectors in Flash memory can be protected against unwanted write operations due to loss of program counter contexts. When the non-write protection nWRPi bit (0 ≤ i ≤ 7) in the FLASH_OPTCR or FLASH_OPTCR1 registers is low, the corresponding sector cannot be erased or programmed. Consequently, a mass erase cannot be performed if one of the sectors is write-protected.

If an erase/program operation to a write-protected part of the Flash memory is attempted

(sector protected by write protection bit, OTP part locked or part of the Flash memory that can never be written like the ICP), the write protection error flag (WRPERR) is set in the

FLASH_SR register.

When the memory read protection level is selected (RDP level = 1), it is not possible to program or erase Flash memory sector i if the CPU debug features are connected (JTAG or single wire) or boot code is being executed from RAM, even if nWRPi = 1.

Write protection error flag

If an erase/program operation to a write protected area of the Flash memory is performed, the Write Protection Error flag (WRPERR) is set in the FLASH_SR register.

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If an erase operation is requested, the WRPERR bit is set when:

 Mass, bank, sector erase are configured (MER and SER = 1)

 A sector erase is requested and the Sector Number SNB field is not valid

 A mass erase is requested while at least one of the user sector is write protected by option bit (MER = 1 and nWRPi = 0 with 0 ≤ i ≤ 117 bits in the FLASH_OPTCRx register

 A sector erase is requested on a write protected sector. (SER = 1, SNB = i and nWRPi = 0 with 0 ≤ i ≤ 117 bits in the FLASH_OPTCRx register)

 The Flash memory is readout protected and an intrusion is detected.

If a program operation is requested, the WRPERR bit is set when:

 A write operation is performed on system memory or on the reserved part of the user specific sector.

 A write operation is performed to the user configuration sector

 A write operation is performed on a sector write protected by option bit.

 A write operation is requested on an OTP area which is already locked

 The Flash memory is read protected and an intrusion is detected.

Proprietary code readout protection (PCROP)

Flash memory user sectors (0 to 7) can be protected against D-bus read accesses by using the proprietary readout protection (PCROP).

The PCROP protection is selected as follows, through the SPRMOD option bit in the

FLASH_CR register:

 SPRMOD = 0: nWRPi control the write protection of respective user sectors

 SPRMOD = 1: nWRPi control the read and write protection (PCROP) of respective user sectors.

When a sector is readout protected (PCROP mode activated), it can only be accessed for code fetch through ICODE Bus on Flash interface:

 Any read access performed through the D-bus triggers a RDERR flag error.

 Any program/erase operation on a PCROPed sector triggers a WRPERR flag error.

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Figure 6. PCROP levels

Write options

SPMOD = active and valid nWRPi*

Write options

SPMOD = active and valid nWRPi*

Level 1

RDP /= 0xAA

RDP /= 0xCC default Write options

SPMOD = active and valid nWRPi*

No restriction on

Write options

Level 2

RDP = 0xCC

Write options

SPMOD = active and valid nWRPi*

Level 0

RDP = 0xAA

Write options

SPMOD = active and valid nWRPi* User option sector erase

Program new options

Global mass erase

User option section erase

Program new options

* Valid nWRPi means that none of the nWRP bits set can be reset (transition from 1 to 0)

MS30467V1

The deactivation of the SPRMOD and/or the unprotection of PCROPed user sectors can only occur when, at the same time, the RDP level changes from 1 to 0. If this condition is not respected, the user option byte modification is canceled and the write error WRPERR flag is set. The modification of the users option bytes (BOR_LEV, RST_STDBY, ..) is allowed since none of the active nWRPi bits is reset and SPRMOD is kept active.

The active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).

If SPRMOD = 1 and nWRPi =1, then user sector i of bank 1, respectively bank 2 is read/write protected (PCROP).

Table 11 shows the organization of the one-time programmable (OTP) part of the OTP area.

Block

[128:96]

OTP0

OTP1

Table 11. OTP area organization

[95:64] [63:32] [31:0]

OTP0

OTP1

OTP0

OTP1

OTP0

OTP1

Address byte 0

0x1FFF 7800

0x1FFF 7810

0x1FFF 7820

0x1FFF 7830

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Block

Lock block

Table 11. OTP area organization (continued)

[128:96] [95:64] [63:32] [31:0]

OTP15

LOCKB15 ...

LOCKB12

OTP15

LOCKB11 ...

LOCKB8

OTP15

LOCKB7 ...

LOCKB4

OTP15

LOCKB3 ...

LOCKB0

Address byte 0

0x1FFF 79E0

0x1FFF 79F0

0x1FFF 7A00

The OTP area is divided into 16 OTP data blocks of 32 bytes and one lock OTP block of 16 bytes. The OTP data and lock blocks cannot be erased. The lock block contains 16 bytes

LOCKBi (0 ≤ i ≤ 15) to lock the corresponding OTP data block (blocks 0 to 15). Each OTP data block can be programmed until the value 0x00 is programmed in the corresponding

OTP lock byte. The lock bytes must only contain 0x00 and 0xFF values, otherwise the OTP bytes might not be taken into account correctly.

The Flash access control register is used to enable/disable the acceleration features and control the Flash memory access time according to CPU frequency.

Address offset: 0x00

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

31 30

Res.

2 1

LATENCY rw rw

0 rw

15 14

Res.

13 12 11 10 9 8 7

Res.

DCRST ICRST DCEN ICEN PRFTEN Res.

rw w rw rw rw

Res.

Bits 31:13 Reserved, must be kept cleared.

Bit 12 DCRST: Data cache reset

0: Data cache is not reset

1: Data cache is reset

This bit can be written only when the D cache is disabled.

Bit 11 ICRST: Instruction cache reset

0: Instruction cache is not reset

1: Instruction cache is reset

This bit can be written only when the I cache is disabled.

Bit 10 DCEN: Data cache enable

0: Data cache is disabled

1: Data cache is enabled

Res.

3 rw

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3.8.2

31 w

15 w

Flash key register (FLASH_KEYR)

The Flash key register is used to allow access to the Flash control register and so, to allow program and erase operations.

Address offset: 0x04

Reset value: 0x0000 0000

Access: no wait state, word access

30 29 28 27 26 25 22 21 20 19 18 17 16 w

14 w w

13 w w

12 w w

11 w w

10 w w

9 w

24 23

KEY[31:16] w

8 w

7 w

KEY[15:0] w w

6 w w

5 w w

4 w w

3 w w

2 w w

1 w w

0 w

Bits 31:0 FKEYR : FPEC key

The following values must be programmed consecutively to unlock the FLASH_CR register and allow programming/erasing it: a) KEY1 0x45670123 b) KEY2 0xCDEF89AB

3.8.3

Bit 9 ICEN: Instruction cache enable

0: Instruction cache is disabled

1: Instruction cache is enabled

Bit 8 PRFTEN: Prefetch enable

0: Prefetch is disabled

1: Prefetch is enabled

Bits 7:4 Reserved, must be kept cleared.

Bits 3:0 LATENCY: Latency

These bits represent the ratio of the CPU clock period to the Flash memory access time.

0000: Zero wait state

0001: One wait state

0010: Two wait states

1110: Fourteen wait states

1111: Fifteen wait states

Flash option key register (FLASH_OPTKEYR)

The Flash option key register is used to allow program and erase operations in the user configuration sector.

Address offset: 0x08

Reset value: 0x0000 0000

Access: no wait state, word access

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31 w

15 w

30 29 w

14 w w

28 w

27 w

26 w

25 w

24 23

OPTKEYR[31:16 w w

8 7

OPTKEYR[15:0] w w

22 w

6 w

21 w

20 w

19 w

18 w

17 w

16 w w w w w w w w w w

Bits 31:0 OPTKEYR : Option byte key

The following values must be programmed consecutively to unlock the FLASH_OPTCR register and allow programming it: a) OPTKEY1 = 0x08192A3B b) OPTKEY2 = 0x4C5D6E7F w w

3.8.4 Flash status register (FLASH_SR)

The Flash status register gives information on ongoing program and erase operations.

Address offset: 0x0C

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25

Res.

15 14 13 12 11 10 9 8 7 6 5 4 3

Res.

RDERR PGSERR PGPERR PGAERR WRPERR Res.

rw rc_w1 rc_w1 rc_w1 rc_w1

Res.

BSY r

2 1 0

Res.

OPERR EOP rc_w1 rc_w1

Bits 31:17 Reserved, must be kept cleared.

Bit 16 BSY: Busy

This bit indicates that a Flash memory operation is in progress. It is set at the beginning of a

Flash memory operation and cleared when the operation finishes or an error occurs.

0: no Flash memory operation ongoing

1: Flash memory operation ongoing

Bits 15:9 Reserved, must be kept cleared.

Bit 8 RDERR: Read Protection Error (pcrop)

Set by hardware when an address to be read through the Dbus belongs to a read protected part of the flash.

Reset by writing 1.

Bit 7 PGSERR: Programming sequence error

Set by hardware when a write access to the Flash memory is performed by the code while the control register has not been correctly configured.

Cleared by writing 1.

Bit 6 PGPERR: Programming parallelism error

Set by hardware when the size of the access (byte, half-word, word, double word) during the program sequence does not correspond to the parallelism configuration PSIZE (x8, x16, x32, x64).

Cleared by writing 1.

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Bit 5 PGAERR: Programming alignment error

Set by hardware when the data to program cannot be contained in the same 128-bit Flash memory row.

Cleared by writing 1.

Bit 4 WRPERR: Write protection error

Set by hardware when an address to be erased/programmed belongs to a write-protected part of the Flash memory.

Cleared by writing 1.

Bits 3:2 Reserved, must be kept cleared.

Bit 1 OPERR: Operation error

Set by hardware when a Flash operation (programming / erase /read) request is detected and can not be run because of parallelism, alignment, or write protection error. This bit is set only if error interrupts are enabled (ERRIE = 1).

Bit 0 EOP: End of operation

Set by hardware when one or more Flash memory operations (program/erase) has/have completed successfully. It is set only if the end of operation interrupts are enabled (EOPIE =

1).

Cleared by writing a 1.

3.8.5 Flash control register (FLASH_CR)

The Flash control register is used to configure and start Flash memory operations.

Address offset: 0x10

Reset value: 0x8000 0000

Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access.

31 30

LOCK Res.

Res.

26 25 24

Res.

ERRIE EOPIE rw rw

Res.

PSIZE[1:0] rw

8 rw

Res.

6 rw

Res.

SNB[3:0]

4 rw rw

Res.

3 rw

Res.

MER rw

Res.

SER rw

Bit 31 LOCK: Lock

Write to 1 only. When it is set, this bit indicates that the FLASH_CR register is locked. It is cleared by hardware after detecting the unlock sequence.

In the event of an unsuccessful unlock operation, this bit remains set until the next reset.

Bits 30:26 Reserved, must be kept cleared.

Bit 25 ERRIE: Error interrupt enable

This bit enables the interrupt generation when the OPERR bit in the FLASH_SR register is set to 1.

0: Error interrupt generation disabled

1: Error interrupt generation enabled

STRT rs

PG rw

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Bit 24 EOPIE: End of operation interrupt enable

This bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes to 1.

0: Interrupt generation disabled

1: Interrupt generation enabled

Bits 23:17 Reserved, must be kept cleared.

Bit 16 STRT: Start

This bit triggers an erase operation when set. It is set only by software and cleared when the

BSY bit is cleared.

Bits 15:10 Reserved, must be kept cleared.

Bits 9:8 PSIZE: Program size

These bits select the program parallelism.

00 program x8

01 program x16

10 program x32

11 program x64

Bit 7 Reserved, must be kept cleared.

Bits 6:3 SNB: Sector number

These bits select the sector to erase.

0000 sector 0

0001 sector 1

...

0101 sector 5

0110 sector 6

0111 sector 7

1000 not allowed

...

1011 not allowed

1100 user specific sector

1101 user configuration sector

1110 not allowed

1111 not allowed

Bit 2 MER: Mass Erase

Erase activated for all user sectors.

Bit 1 SER: Sector Erase

Sector Erase activated.

Bit 0 PG: Programming

Flash programming activated.

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RM0390 Embedded Flash memory interface

The FLASH_OPTCR register is used to modify the user option bytes.

Address offset: 0x14

Reset value: 0x0FFF AAED. The option bits are loaded with values from Flash memory at reset release.

Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access.

31 30

SPRMOD Res.

29 28 27 26 25 24

Res.

15 14 13 12 11 10 9 8 rw rw rw

RDP[7:0] rw rw rw rw rw

23 22 21 rw

7 nRST_

STDBY rw rw

6 nRST_

STOP rw rw

WDG_S

W rw

20 19 nWRP[7:0] rw

Res.

18 rw

3 rw

BOR_LEV rw rw

17 16 rw

OPTST

RT rs rw

OPTLO

CK rs

Bit 31 SPRMOD: Selection of Protection Mode of nWPRi bits

0: PCROP disabled, nWPRi bits used for Write Protection on sector i

1: PCROP enabled, nWPRi bits used for PCROP Protection on sector i

Bits 30:24 Reserved, must be kept cleared.

Bits 23:16 nWRP[7:0]: Not write protect

These bits contain the value of the write-protection option bytes of sectors after reset. They can be written to program a new write protect value into Flash memory.

0: Write protection active on selected sector

1: Write protection not active on selected sector

These bits contain the value of the write-protection and read-protection (PCROP) option bytes for sectors 0 to 7 after reset. They can be written to program a new write-protect or

PCROP value into Flash memory.

If SPRMOD is reset:

0: Write protection active on sector i

1: Write protection not active on sector i

If SPRMOD is set:

0: PCROP protection not active on sector i

1: PCROP protection active on sector i

Bits 15:8 RDP: Read protect

These bits contain the value of the read-protection option level after reset. They can be written to program a new read protection value into Flash memory.

0xAA: Level 0, read protection not active

0xCC: Level 2, chip read protection active

Others: Level 1, read protection of memories active

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Bits 7:5 USER: User option bytes

These bits contain the value of the user option byte after reset. They can be written to program a new user option byte value into Flash memory.

Bit 7: nRST_STDBY

Bit 6: nRST_STOP

Bit 5: WDG_SW

Note: When changing the WDG mode from hardware to software or from software to hardware, a system reset is required to make the change effective.

Bit 4 Reserved, must be kept cleared. Always read as “0”.

Bits 3:2 BOR_LEV: BOR reset Level

These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level. By default, BOR is off. When the supply voltage (V

DD drops below the selected BOR level, a device reset is generated.

)

00: BOR Level 3 (VBOR3), brownout threshold level 3

01: BOR Level 2 (VBOR2), brownout threshold level 2

10: BOR Level 1 (VBOR1), brownout threshold level 1

11: BOR off, POR/PDR reset threshold level is applied

Note: For full details about BOR characteristics, refer to the “Electrical characteristics” section in the device datasheet.

Bit 1 OPTSTRT: Option start

This bit triggers a user option operation when set. It is set only by software and cleared when the BSY bit is cleared.

Bit 0 OPTLOCK: Option lock

Write to 1 only. When this bit is set, it indicates that the FLASH_OPTCR register is locked.

This bit is cleared by hardware after detecting the unlock sequence.

In the event of an unsuccessful unlock operation, this bit remains set until the next reset.

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3.8.7

Embedded Flash memory interface

Flash interface register map

Table 12. Flash register map and reset value

Offset Register

FLASH_ACR LATENCY

0x00

0x04

0x08

Reset value 0 0 0 0 0 0 0 0 0

FLASH_KEYR

Reset value

FLASH_

OPTKEYR

Reset value

KEY[31:16] KEY[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OPTKEYR[31:16] OPTKEYR[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASH_SR

0x0C

Reset value 0 0 0 0 0 0 0 0

FLASH_CR SNB[3:0]

0x10

Reset value 1 0 0 0 0 0 0 0 0 0 0 0 0

0x14

FLASH_OPTCR

Reset value 0 nWRP[7:0] RDP[7:0]

1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 1

Refer to Section 2.2 on page 56 for the register boundary addresses.

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CRC calculation unit

4 CRC calculation unit

RM0390

4.2

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a way of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location.

CRC main features

 Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7

– X

+ X

+ X +1

 Single input/output 32-bit data register

 CRC computation done in four AHB clock cycles (HCLK)

 General-purpose 8-bit register (can be used for temporary storage)

The block diagram is shown in

Figure 7 .

Figure 7. CRC calculation unit block diagram

AHB bus

32-bit (read access)

Data register (output)

4.3

CRC computation (polynomial: 0x4C11DB7)

32-bit (write access)

Data register (input) ai14968

CRC functional description

The CRC calculation unit mainly consists of a single 32-bit data register, which:

 is used as an input register to enter new data in the CRC calculator (when writing into the register)

 holds the result of the previous CRC calculation (when reading the register)

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RM0390 CRC calculation unit

Each write operation into the data register creates a combination of the previous CRC value and the new one (CRC computation is done on the whole 32-bit data word, and not byte per byte).

The write operation is stalled until the end of the CRC computation, thus allowing back-toback write accesses or consecutive write and read accesses.

The CRC calculator can be reset to 0xFFFF FFFF with the RESET control bit in the

CRC_CR register. This operation does not affect the contents of the CRC_IDR register.

The CRC calculation unit contains two data registers and a control register.

The peripheral

The CRC registers have to be accessed by words (32 bits).

Address offset: 0x00

Reset value: 0xFFFF FFFF

31 rw

15 rw

30 rw

29 rw

28 rw

27 rw

26 rw

25 rw

24 23

DR [31:16] rw rw

DR [15:0]

7 rw rw

22 rw

21 rw

20 rw

19 rw

3 rw rw rw rw rw rw rw rw rw rw

Bits 31:0 Data register bits

Used as an input register when writing new data into the CRC calculator.

Holds the previous CRC calculation result when it is read.

18 rw

2 rw

17 16 rw

1 rw rw

0 rw

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4.4.2

Res.

Independent data register (CRC_IDR)

Address offset: 0x04

Res.

Reset value: 0x0000 0000

Res.

7 rw

6 rw

5 rw

4 3 rw

IDR[7:0] rw

2 rw

1 rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 General-purpose 8-bit data register bits

Can be used as a temporary storage location for one byte.

This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register.

0 rw

4.4.3

Res.

Control register (CRC_CR)

Res.

Address offset: 0x08

Reset value: 0x0000 0000

Res.

1 0

Res.

RESET w

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 RESET bit

Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF.

This bit can only be set, it is automatically cleared by hardware.

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RM0390 CRC calculation unit

4.4.4 CRC register map

Table 13. CRC calculation unit register map and reset values

Offset Register

Data register

0xFFFF FFFF

0x00

0x04

0x08

CRC_DR

Reset value

CRC_IDR

Reset value

CRC_CR

Reset value

Independent data register

0x0000

Refer to Section 2.2 on page 56 for the register boundary addresses.

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Power controller (PWR)

5 Power controller (PWR)

RM0390

Note:

The device requires a 1.8 to 3.6 V operating voltage supply (V

). An embedded linear voltage regulator is used to supply the internal 1.2 V digital power.

The real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP SRAM) can be powered from the V

BAT

voltage when the main V

supply is powered off.

Depending on the operating power supply range, some peripheral may be used with limited functionality and performance. For more details refer to section “General operating conditions” in STM32F446xx datasheet.

Figure 8. Power supply overview for STM32F446xx

BAT

1.65 to 3.6V

Power switch

Backup circuitry

(OSC32K,RTC,

Wakeup logic

Backup registers, backup RAM)

OUT

Logic

GPIOs

12 × 100 nF

+ 1 × 4.7 μF

2 × 2.2 μF

CAP_1

CAP_2

1/2/...11/12

DDUSB

(2)

BYPASS_REG

DDUSB

(2)

100 nF

+ 1 μF

100 nF

+ 1 μF

100 nF

+ 1 μF

REF

PDR_ON

DDA

REF+

REF-

SSA

Voltage regulator

OTG

PHY

Reset controller

ADC

Analog:

RCs,

PLL,..

Kernel logic

(CPU, digital

& RAM)

Flash memory

MSv33072V1

1. V

DDA

and V

SSA must be connected to V

and V

, respectively.

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RM0390 Power controller (PWR)

5.1.1 Independent converter supply and reference voltage

To improve conversion accuracy, the ADC has an independent power supply which can be separately filtered and shielded from noise on the PCB.

 The ADC voltage supply input is available on a separate V

DDA

pin.

 An isolated supply ground connection is provided on pin V

SSA

 To ensure a better accuracy of low voltage inputs, the user can connect a separate external reference voltage ADC input on V

REF to V

DDA

. The voltage on V

REF

ranges from 1.8 V

Backup domain description

To retain the content of the RTC backup registers, backup SRAM, and supply the RTC when

DD is turned off, V

BAT pin can be connected to an optional standby voltage supplied by a battery or by another source.

To allow the RTC to operate even when the main digital supply (V

DD pin powers the following blocks:

) is turned off, the V

BAT

 The RTC

 The LSE oscillator

 The backup SRAM when the low-power backup regulator is enabled

 PC13 to PC15 I/Os

The switch to the V

BAT block.

supply is controlled by the power-down reset embedded in the Reset

Warning: During t

RSTTEMPO

(temporization at V connected to V

BAT

During the startup phase, if V

startup) or after a PDR is detected, the power switch between V

BAT and V

remains

is established in less than

(refer to the datasheet for the value of t t

RSTTEMPO and V

> V

BAT through an internal diode connected between V

DD power switch (V

BAT

If the power supply/battery connected to the V

BAT

RSTTEMPO

+ 0.6 V, a current may be injected into V

BAT

and the

)

pin cannot support this current injection, it is strongly recommended to connect an external low-drop diode between this power supply and the V

BAT

pin.

If no external battery is used in the application, it is recommended to connect the V

BAT

with a 100 nF external decoupling ceramic capacitor in parallel.

pin to

When the backup domain is supplied by V

DD following functions are available:

(analog switch connected to V

), the

 PC14 and PC15 can be used as either GPIO or LSE pins

 PC13 can be used as a GPIOas the RTC_AF1 pin (refer to

Table 24: RTC_AF1 pin

for more details about this pin configuration)

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Note:

RM0390

Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of

GPIOs PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED).

When the backup domain is supplied by V

BAT

(analog switch connected to V

is not present), the following functions are available:

BAT

because

 PC14 and PC15 can be used as LSE pins only

 PC13 can be used as the RTC_AF1 pin (refer to

Table 24: RTC_AF1 pin for more

details about this pin configuration).

Backup domain access

After reset, the backup domain (RTC registers, RTC backup register and backup SRAM) is protected against possible unwanted write accesses. To enable access to the backup domain, proceed as follows:

 Access to the RTC and RTC backup registers

Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR

register (see Section 6.3.13: RCC APB1 peripheral clock enable register

(RCC_APB1ENR) )

2. Set the DBP bit in the Section 5.4.1: PWR power control register (PWR_CR)

and

PWR power control register (PWR_CR)

to enable access to the backup domain

3. Select the RTC clock source: see Section 6.2.8: RTC/AWU clock

4. Enable the RTC clock by programming the RTCEN [15] bit in the

Section 6.3.20: RCC

Backup domain control register (RCC_BDCR)

 Access to the backup SRAM

Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR

register (see Section 6.3.13

2. Set the DBP bit in the PWR power control register (PWR_CR)

to enable access to the backup domain

3. Enable the backup SRAM clock by setting BKPSRAMEN bit in the

RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) .

RTC and RTC backup registers

The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a timeof-day clock/calendar, two programmable alarm interrupts, and a periodic programmable wakeup flag with interrupt capability. The RTC contains 20 backup data registers (80 bytes) which are reset when a tamper detection event occurs. For more details refer to .

Backup SRAM

The backup domain includes 4 Kbytes of backup SRAM addressed in 32-bit, 16-bit or 8-bit mode. Its content is retained even in Standby or V

BAT

mode when the low-power backup regulator is enabled. It can be considered as an internal EEPROM when V present.

BAT

is always

When the backup domain is supplied by V

SRAM is powered from V

(analog switch connected to V

DD which replaces the V

BAT

), the backup

power supply to save battery life.

When the backup domain is supplied by V

BAT

(analog switch connected to V

BAT

because

is not present), the backup SRAM is powered by a dedicated low-power regulator. This

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RM0390 Power controller (PWR) regulator can be ON or OFF depending whether the application needs the backup SRAM function in Standby and V

BAT

modes or not. The power-down of this regulator is controlled by a dedicated bit, the BRE control bit of the PWR_CSR register.

The backup SRAM is not mass erased by a tamper event.

When the Flash is read out protected, the backup SRAM is also read protected to prevent confidential data (such as cryptographic private key) from being accessed. When the protection level change from level 1 to level 0 is requested, the backup SRAM content is erased. Refer to the description of Read protection (RDP) option byte.

Figure 9. Backup domain

Voltage regulator

3.3 -> 1.2 V

1.2 V domain

Backup SRAM interface

Power switch LP voltage regulator

3.3 -> 1.2 V

Backup SRAM

1.2 V

RTC LSE 32.768 Hz

Backup domain

MS30430V1

An embedded linear voltage regulator supplies all the digital circuitries except for the backup domain and the Standby circuitry. The regulator output voltage is around 1.2 V.

This voltage regulator requires two external capacitors to be connected to two dedicated pins, V

CAP_1

or V package.

DD and V

CAP_2 available in all packages. Specific pins must be connected either to

to activate or deactivate the voltage regulator. These pins depend on the

When activated by software, the voltage regulator is always enabled after Reset. It works in three different modes depending on the application modes (Run, Stop, or Standby mode).

 In Run mode , the main regulator supplies full power to the 1.2 V domain (core, memories and digital peripherals). In this mode, the regulator output voltage (around

1.2 V) can be scaled by software to different voltage values (scale 1, scale 2, and scale

3 can be configured through VOS[1:0] bits of the PWR_CR register). The scale can be modified only when the PLL is OFF and the HSI or HSE clock source is selected as system clock source. The new value programmed is active only when the PLL is ON.

When the PLL is OFF, the voltage scale 3 is automatically selected.

The voltage scaling allows optimizing the power consumption when the device is clocked below the maximum system frequency. After exit from Stop mode, the voltage

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Power controller (PWR)

Note:

RM0390

scale 3 is automatically selected.(see Section 5.4.1: PWR power control register

(PWR_CR) .

2 operating modes are available:

– Normal mode : The CPU and core logic operate at maximum frequency at a given voltage scaling (scale 1, scale 2 or scale 3)

– Over-drive mode : This mode allows the CPU and the core logic to operate at a higher frequency than the normal mode for the voltage scaling scale 1 and scale

 In Stop mode : the main regulator or low-power regulator supplies a low-power voltage to the 1.2V domain, thus preserving the content of registers and internal SRAM.

The voltage regulator can be put either in main regulator mode (MR) or in low-power mode (LPR). Both modes can be configured by software as follows:

– Normal mode : the 1.2 V domain is preserved in nominal leakage mode. It is the default mode when the main regulator (MR) or the low-power regulator (LPR) is enabled.

– Low voltage mode.

– Under-drive mode : the 1.2 V domain is preserved in reduced leakage mode. This mode is only available when the main regulator or the low-power regulator is in low voltage mode (see

Table 14

).

 In Standby mode : the regulator is powered down. The content of the registers and

SRAM are lost except for the Standby circuitry and the backup domain.

Over-drive and under-drive mode are not available when the regulator is bypassed.

For more details, refer to the voltage regulator section in the STM32F446xx datasheet.

Table 14. Voltage regulator configuration mode versus device operating mode (1)

Voltage regulator configuration

Run mode Sleep mode Stop mode Standby mode

Normal mode

Low-voltage mode

Over-drive mode

(2)

Under-drive mode

Power-down mode

1. ‘-’ means that the corresponding configuration is not available.

2. The over-drive mode is not available when V

= 1.8 to 2.1 V.

MR or LPR

Yes

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Note:

Power controller (PWR)

Entering Over-drive mode

It is recommended to enter Over-drive mode when the application is not running critical tasks and when the system clock source is either HSI or HSE. To optimize the configuration time, enable the Over-drive mode during the PLL lock phase.

To enter Over-drive mode, follow the sequence below:

Select HSI or HSE as system clock.

3. Set ODEN bit of PWR_CR register to enable the Over-drive mode and wait for the

ODRDY flag to be set in the PWR_CSR register.

4. Set the ODSW bit in the PWR_CR register to switch the voltage regulator from Normal mode to Over-drive mode. The System will be stalled during the switch but the PLL clock system will be still running during locking phase.

5. Wait for the ODSWRDY flag in the PWR_CSR to be set.

6. Select the required Flash latency as well as AHB and APB prescalers.

7. Wait for PLL lock.

8. Switch the system clock to the PLL.

9. Enable the peripherals that are not generated by the System PLL (I2S clock, SAI1 and

SAI2 clocks, USB_48MHz clock....).

The PLLI2S and PLLSAI can be configured at the same time as the system PLL.

During the Over-drive switch activation, no peripheral clocks should be enabled. The peripheral clocks must be enabled once the Over-drive mode is activated.

Entering Stop mode disables the Over-drive mode, as well as the PLL. The application software has to configure again the Over-drive mode and the PLL after exiting from Stop mode.

Exiting from Over-drive mode

It is recommended to exit from Over-drive mode when the application is not running critical tasks and when the system clock source is either HSI or HSE.There are two sequences that allow exiting from over-drive mode:

 By resetting simultaneously the ODEN and ODSW bits bit in the PWR_CR register

(sequence 1)

 By resetting first the ODSW bit to switch the voltage regulator to Normal mode and then resetting the ODEN bit to disable the Over-drive mode (sequence 2).

Example of sequence 1:

Select HSI or HSE as system clock source.

2. Disable the peripheral clocks that are not generated by the System PLL (I2S clock,

SAI1 and SAI2 clocks, USB_48MHz clock,....)

3. Reset simultaneously the ODEN and the ODSW bits in the PWR_CR register to switch back the voltage regulator to Normal mode and disable the Over-drive mode.

4. Wait for the ODWRDY flag of PWR_CSR to be reset.

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Note:

RM0390

Example of sequence 2:

Select HSI or HSE as system clock source.

2. Disable the peripheral clocks that are not generated by the System PLL (I2S clock,

SAI1 and SAI2 clocks, USB_48MHz clock,....).

3. Reset the ODSW bit in the PWR_CR register to switch back the voltage regulator to

Normal mode. The system clock is stalled during voltage switching.

4. Wait for the ODWRDY flag of PWR_CSR to be reset.

5. Reset the ODEN bit in the PWR_CR register to disable the Over-drive mode.

During step 3, the ODEN bit remains set and the Over-drive mode is still enabled but not active (ODSW bit is reset). If the ODEN bit is reset instead, the Over-drive mode is disabled and the voltage regulator is switched back to the initial voltage.

The device has an integrated POR/PDR circuitry that allows proper operation starting from 1.8 V.

The device remains in Reset mode when V

POR/PDR

DDA is below a specified threshold,

, without the need for an external reset circuit. For more details concerning the power on/power-down reset threshold, refer to the electrical characteristics of the datasheet.

Figure 10. Power-on reset/power-down reset waveform

VDD/VDDA

PDR

40 mV hysteresis

PDR

Temporization tRSTTEMPO

Reset

MS30431V1

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RM0390 Power controller (PWR)

Note:

During power on, the Brownout reset (BOR) keeps the device under reset until the supply voltage reaches the specified V

BOR threshold.

BOR

is configured through device option bytes. By default, BOR is off. 3 programmable

threshold levels can be selected:

 BOR Level 3 (VBOR3). Brownout threshold level 3.

 BOR Level 2 (VBOR2). Brownout threshold level 2.

 BOR Level 1 (VBOR1). Brownout threshold level 1.

For full details about BOR characteristics, refer to the "Electrical characteristics" section in the device datasheet.

When the supply voltage (V

DD generated.

) drops below the selected V

BOR

threshold, a device reset is

The BOR can be disabled by programming the device option bytes. In this case, the power-on and power-down is then monitored by the POR/ PDR (see

Section 5.2.1: Poweron reset (POR) / power-down reset (PDR) ).

The BOR threshold hysteresis is ~100 mV (between the rising and the falling edge of the supply voltage).

Figure 11. BOR thresholds

VDD/VDDA

BOR threshold 100 mV hysteresis

5.2.3

Reset

MS30433V1

Programmable voltage detector (PVD)

You can use the PVD to monitor the V

power supply by comparing it to a threshold selected by the PLS[2:0] bits in the

Section 5.4.1: PWR power control register (PWR_CR)

The PVD is enabled by setting the PVDE bit.

A PVDO flag is available, in the

Section 5.4.2: PWR power control/status register

(PWR_CSR) , to indicate if V

is higher or lower than the PVD threshold. This event is

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Power controller (PWR) RM0390 internally connected to the EXTI line16 and can generate an interrupt if enabled through the

EXTI registers. The PVD output interrupt can be generated when V

DD threshold and/or when V

drops below the PVD

rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration. As an example the service routine could perform emergency shutdown tasks.

Figure 12. PVD thresholds

VDD

PVD threshold 100 mV hysteresis

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PVD output

MS30432V2

By default, the microcontroller is in Run mode after a system or a power-on reset. In Run mode the CPU is clocked by HCLK and the program code is executed. Several low-power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode that gives the best compromise between low-power consumption, short startup time and available wakeup sources.

The devices feature three low-power modes:

 Sleep mode (Cortex ® -M4 with FPU core stopped, peripherals kept running)

 Stop mode (all clocks are stopped)

 Standby mode (1.2 V domain powered off)

In addition, the power consumption in Run mode can be reduce by one of the following means:

 Slowing down the system clocks

 Gating the clocks to the APBx and AHBx peripherals when they are unused.

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Mode name Entry

Table 15. Low-power mode summary

Wakeup

Effect on 1.2 V domain clocks

Effect on

domain clocks

Voltage regulator

Sleep

(Sleep now or Sleep-onexit)

Stop

Standby

WFI or Return from ISR

WFE

Any interrupt

Wakeup event

CPU CLK OFF no effect on other clocks or analog clock sources

PDDS and LPDS bits +

SLEEPDEEP bit

+ WFI or Return from ISR or WFE

Any EXTI line (configured in the EXTI registers, internal and external lines)

PDDS bit +

SLEEPDEEP bit

+ WFI or Return from ISR or WFE

WKUP pin rising edge,

RTC alarm (Alarm A or

Alarm B), RTC Wakeup event, RTC tamper events, RTC time stamp event, external reset in

NRST pin, IWDG reset

All 1.2 V domain clocks OFF

None ON

HSI and

HSE oscillators

OFF

ON or in low- power mode (depends on

PWR power control register (PWR_CR)

OFF

5.3.2

In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down peripherals before entering Sleep mode.

For more details refer to Section 6.3.3: RCC clock configuration register (RCC_CFGR)

Peripheral clock gating

In Run mode, the HCLKx and PCLKx for individual peripherals and memories can be stopped at any time to reduce power consumption.

To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.

Peripheral clock gating for STM32F446xx is controlled by the AHB1 peripheral clock enable register (RCC_AHB1ENR), AHB2 peripheral by the clock enable register

(RCC_AHB2ENR), AHB3 by the peripheral clock enable register (RCC_AHB3ENR) (see

Section 6.3.10: RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) ,

Section 6.3.11: RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) and

Section 6.3.12: RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) ,

respectively).

Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting the corresponding bit in RCC_AHBxLPENR and RCC_APBxLPENR registers.

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5.3.3 Low power mode

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Entering low power mode

Low power modes are entered by the MCU executing the WFI (Wait For Interrupt), or WFE

(Wait For Event) instructions, or when the SLEEPONEXIT bit in the Cortex ® -M4 System

Control register is set on Return from ISR.

Exiting low power mode

From Sleep and Stop modes the MCU exits low power mode depending on the way the mode was entered:

 If the WFI instruction or Return from ISR was used to enter the low power mode, any peripheral interrupt acknowledged by the NVIC can wake up the device

 If the WFE instruction was used to enter the low power mode, the MCU exits the mode as soon as an event occurs. The wakeup event can by generated either by:

– NVIC IRQ interrupt

- When SEVEONPEND=0 in the Cortex ® -M4 System Control register.

By enabling an interrupt in the peripheral control register and in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.

Only NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.

- When SEVEONPEND=1 in the Cortex

-M4 System Control register.

By enabling an interrupt in the peripheral control register and optionally in the

NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and

(when enabled) the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.

All NVIC interrupts will wakeup the MCU, even the disabled ones.

Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the

MCU.

- Event

Configuring a EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bits corresponding to the event line is not set.

It may be necessary to clear the interrupt flag in the peripheral.

From Standby and Shutdown modes the MCU exits Low power mode through an external reset (NRST pin), an IWDG reset, a rising edge on one of the enabled WKUPx pins or a

RTC event (see

Figure 240: RTC block diagram ).

Entering Sleep mode

The Sleep mode is entered according to

Entering low power mode

, when the SLEEPDEEP bit in the Cortex ® -M4 System Control register is cleared.

Refer to Table 16

for details on how to enter the Sleep mode.

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Exiting Sleep mode

The Sleep mode is exited according to

Exiting low power mode

Refer to Table 16

for details on how to exit the Sleep mode.

Sleep-now mode

Mode entry

Mode exit

Wakeup latency

Table 16. Sleep-now entry and exit

Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP = 0

Refer to the Cortex

-M4 with FPU System Control register.

On Return from ISR while:

– SLEEPDEEP = 0 and

– SLEEPONEXIT = 1

Refer to the Cortex

-M4 with FPU System Control register.

If WFI or Return from ISR was used for entry:

– Interrupt: refer to Table 38: Vector table for STM32F446xx

If WFE was used for entry and SEVONPEND = 0

– Wakeup event: refer to Section 10.2.3: Wakeup event management

If WFE was used for entry and SEVONPEND = 1

– Interrupt event when disabled in NVIC: refer to

Table 38: Vector table for

STM32F446xx

– Wakeup event: refer to Section 10.2.3: Wakeup event management

None

The Stop mode is based on the Cortex

-M4 with FPU deepsleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or lowpower mode. In Stop mode, all clocks in the 1.2 V domain are stopped, the PLLs, the HSI and the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved.

In Stop mode, the power consumption can be further reduced by using additional settings in the PWR_CR register. However this will induce an additional startup delay when waking up

from Stop mode (see Table 17

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Voltage regulator mode

Table 17. Stop operating modes

UDEN[1:0] bits

MRUDS bit

LPUDS bit

LPDS bit

FPDS bit

STOP MR

(Main regulator)

- 0 - 0

Wakeup latency

0 HSI RC startup time

Normal mode

Underdrive mode

STOP MR- FPD

STOP LP

STOP LP-FPD

STOP UMR-FPD

STOP ULP-FPD

HSI RC startup time +

Flash wakeup time from power-down mode

HSI RC startup time +

Regulator wakeup time from

LP mode

HSI RC startup time +

Flash wakeup time from power-down mode +

Regulator wakeup time from

LP mode

HSI RC startup time +

Flash wakeup time from power-down mode +

Main regulator wakeup time from under-drive mode +

Core logic to nominal mode

HSI RC startup time +

Flash wakeup time from power-down mode +

Regulator wakeup time from

LP under-drive mode +

Core logic to nominal mode

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Entering Stop mode

The Stop mode is entered according to Entering low power mode , when the SLEEPDEEP

bit in Cortex

-M4 System Control register is set.

Refer to Table 18

for details on how to enter the Stop mode.

When the microcontroller enters in Stop mode, the voltage scale 3 is automatically selected.

To further reduce power consumption in Stop mode, the internal voltage regulator can be put in low-power or low voltage mode. This is configured by the LPDS, MRUDS, LPUDS and

UDEN bits of the

PWR power control register (PWR_CR)

Stop mode can be entered from Run mode and Low power run mode.

If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory access is finished.

If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB access is finished.

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If the Over-drive mode was enabled before entering Stop mode, it is automatically disabled during when the Stop mode is activated.

In Stop mode, the following features can be selected by programming individual control bits:

 Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. See

Section 20.3: IWDG functional description



Real-time clock (RTC): this is configured by the RTCEN bit in the RCC Backup domain control register (RCC_BDCR)



Internal RC oscillator (LSI RC): this is configured by the LSION bit in the RCC clock control & status register (RCC_CSR) .

 External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the

RCC Backup domain control register (RCC_BDCR) .

The ADC or DAC can also consume power during the Stop mode, unless they are disabled before entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit in the DAC_CR register must both be written to 0.

Before entering Stop mode, it is recommended to enable the clock security system (CSS) feature to prevent external oscillator (HSE) failure from impacting the internal MCU behavior.

Exiting Stop mode

The Stop mode is exited according to

Exiting low power mode .

Refer to Table 18

for more details on how to exit Stop mode.

When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock.

If the Under-drive mode was enabled, it is automatically disabled after exiting Stop mode.

When the voltage regulator operates in low-power or low voltage mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator

ON during Stop mode, the consumption is higher although the startup time is reduced.

When the voltage regulator operates in Under-drive mode, an additional startup delay is induced when waking up from Stop mode.

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Stop mode

Table 18. Stop mode entry and exit for STM32F446xx

Description

Mode entry

Mode exit

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– Set SLEEPDEEP bit in Cortex

-M4 with FPU System Control register

– Clear PDDS bit in Power Control register (PWR_CR)

– Select the voltage regulator mode by configuring LPDS, MRUDS, LPUDS and

UDEN bits

in PWR_CR (see Table 17: Stop operating modes ).

On Return from ISR while:

– SLEEPDEEP bit is set in Cortex

-M4 with FPU System Control register

– SLEEPONEXIT = 1

– LPMS = “000” in PWR_C1: volatage regulator in main regulator mode

– LPMS = “001” in PWR_C1: volatage regulator in low power regulator mode

Note: To enter the Stop mode, all EXTI Line pending bits in

Pending register

(EXTI_PR)

, all peripheral interrupts pending bits, the RTC Alarms (Alarm A and

Alarm B), RTC wakeup, RTC tamper, and RTC time stamp flags, must be reset.

Otherwise, the Stop mode entry procedure is ignored and program execution continues.

If WFI or Return from ISTR was used for entry:

All EXTI lines configured in Interrupt mode (the corresponding EXTI Interrupt

vector must be enabled in the NVIC). Refer to Table 38: Vector table for

STM32F446xx .

If WFE was used for entry and SEVONPEND = 0:

All EXTI Lines configured in event mode. Refer to Section 10.2.3: Wakeup event management

If WFE was used for entry and SEVONPEND = 1:

Any EXTI line configured in Interrupt mode (even if the corresponding EXTI

Interrupt vector is disabled in the NVIC). The interrupt source can be external

interrupts or peripherals with wakeup capability. Refer to Table 38: Vector table for STM32F446xx .

Wakeup event: refer to

Section 10.2.3: Wakeup event management

Wakeup latency Refer to

Table 17: Stop operating modes

The Standby mode allows to achieve the lowest power consumption. It is based on the

Cortex ® -M4 with FPU deepsleep mode, with the voltage regulator disabled. The 1.2 V domain is consequently powered off. The PLLs, the HSI oscillator and the HSE oscillator are also switched off. SRAM and register contents are lost except for registers in the backup domain (RTC registers, RTC backup register and backup SRAM), and Standby circuitry (see

Figure 8 ).

Entering Standby mode

The Standby mode is entered according to

Entering low power mode , when the

SLEEPDEEP bit in the Cortex ® -M4 with FPU System Control register is set.

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Refer to Table 19

for more details on how to enter Standby mode.

In Standby mode, the following features can be selected by programming individual control bits:

 Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a reset. See

Section 20.3: IWDG functional description

 Real-time clock (RTC): this is configured by the RTCEN bit in the backup domain control register (RCC_BDCR)

 Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status register (RCC_CSR).

 External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the backup domain control register (RCC_BDCR)

Exiting Standby mode

The microcontroller exits Standby mode according to Exiting low power mode

. The SBF

status flag in the PWR power control/status register (PWR_CSR) indicates that the MCU was in Standby mode. All registers are reset after wakeup from standby except for PWR power control/status register (PWR_CSR)

Refer to Table 19

for more details on how to exit Standby mode.

Standby mode

Table 19. Standby mode entry and exit

Description

Mode entry

Mode exit

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP is set in Cortex

-M4 with FPU with FPU System Control register

– PDDS bit is set in Power Control register (PWR_CR)

– no interrupt (for WFI or event (for WFE) is pending

– WUF bit is cleared in Power Control/Status register (PWR_CR)

– the RTC flag corresponding to the chosen wakeup source (RTC Alarm A,

RTC Alarm B, RTC wakeup, Tamper or Timestamp flags) is cleared

On Return from ISR while:

– SLEEPDEEP bit is set in Cortex

-M4 with FPU with FPU System Control register and

– SLEEPONEXIT = 1 and

– PDDS bit is set in Power Control register (PWR_CR) and

– no interrupt is pending and

– WUF bit is cleared in Power Control/Status register (PWR_SR) and

– the RTC flag corresponding to the chosen wakeup source (RTC Alarm A,

RTC Alarm B, RTC wakeup, Tamper or Timestamp flags) is cleared

WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.

Wakeup latency Reset phase.

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5.3.7

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I/O states in Standby mode

In Standby mode, all I/O pins are high impedance except for:

 Reset pad (still available)

 RTC_AF1 pin (PC13) if configured for tamper, time stamp, RTC Alarm out, or RTC clock calibration out

 WKUP pin (PA0), if enabled

Debug mode

By default, the debug connection is lost if the application puts the MCU in Stop or Standby mode while the debug features are used. This is due to the fact that the Cortex

-M4 with

FPU core is no longer clocked.

However, by setting some configuration bits in the DBGMCU_CR register, the software can be debugged even when using the low-power modes extensively. For more details, refer to

Section 33.16.1: Debug support for low-power modes

Programming the RTC alternate functions to wake up the device from the Stop and Standby modes

The MCU can be woken up from a low-power mode by an RTC alternate function.

The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), RTC wakeup, RTC tamper event detection and RTC time stamp event detection.

These RTC alternate functions can wake up the system from the Stop and Standby lowpower modes.

The system can also wake up from low-power modes without depending on an external interrupt (Auto-wakeup mode), by using the RTC alarm or the RTC wakeup events.

The RTC provides a programmable time base for waking up from the Stop or Standby mode at regular intervals.

For this purpose, two of the three alternate RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the

RCC Backup domain control register

(RCC_BDCR)

 Low-power 32.768 kHz external crystal oscillator (LSE OSC)

This clock source provides a precise time base with a very low-power consumption

(additional consumption of less than 1 µA under typical conditions)

 Low-power internal RC oscillator (LSI RC)

This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This internal RC oscillator is designed to use minimum power.

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RTC alternate functions to wake up the device from the Stop mode

 To wake up the device from the Stop mode with an RTC alarm event, it is necessary to: a) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt or Event modes) b) Enable the RTC Alarm Interrupt in the RTC_CR register c) Configure the RTC to generate the RTC alarm

 To wake up the device from the Stop mode with an RTC tamper or time stamp event, it is necessary to: a) Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt or Event modes) b) Enable the RTC time stamp Interrupt in the RTC_CR register or the RTC tamper interrupt in the RTC_TAFCR register c) Configure the RTC to detect the tamper or time stamp event

 To wake up the device from the Stop mode with an RTC wakeup event, it is necessary to: a) Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt or Event modes) b) Enable the RTC wakeup interrupt in the RTC_CR register c) Configure the RTC to generate the RTC Wakeup event

RTC alternate functions to wake up the device from the Standby mode

 To wake up the device from the Standby mode with an RTC alarm event, it is necessary to: a) Enable the RTC alarm interrupt in the RTC_CR register b) Configure the RTC to generate the RTC alarm

 To wake up the device from the Standby mode with an RTC tamper or time stamp event, it is necessary to: a) Enable the RTC time stamp interrupt in the RTC_CR register or the RTC tamper interrupt in the RTC_TAFCR register b) Configure the RTC to detect the tamper or time stamp event

 To wake up the device from the Standby mode with an RTC wakeup event, it is necessary to: a) Enable the RTC wakeup interrupt in the RTC_CR register b) Configure the RTC to generate the RTC wakeup event

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Safe RTC alternate function wakeup flag clearing sequence

If the selected RTC alternate function is set before the PWR wakeup flag (WUTF) is cleared, it will not be detected on the next event as detection is made once on the rising edge.

To avoid bouncing on the pins onto which the RTC alternate functions are mapped, and exit correctly from the Stop and Standby modes, it is recommended to follow the sequence below before entering the Standby mode:

 When using RTC alarm to wake up the device from the low-power modes: a) Disable the RTC alarm interrupt (ALRAIE or ALRBIE bits in the RTC_CR register) b) Clear the RTC alarm (ALRAF/ALRBF) flag c) Clear the PWR Wakeup (WUF) flag d) Enable the RTC alarm interrupt e) Re-enter the low-power mode

 When using RTC wakeup to wake up the device from the low-power modes: a) Disable the RTC Wakeup interrupt (WUTIE bit in the RTC_CR register) b) Clear the RTC Wakeup (WUTF) flag c) Clear the PWR Wakeup (WUF) flag d) Enable the RTC Wakeup interrupt e) Re-enter the low-power mode

 When using RTC tamper to wake up the device from the low-power modes: a) Disable the RTC tamper interrupt (TAMPIE bit in the RTC_TAFCR register) b) Clear the Tamper (TAMP1F/TSF) flag c) Clear the PWR Wakeup (WUF) flag d) Enable the RTC tamper interrupt e) Re-enter the low-power mode

 When using RTC time stamp to wake up the device from the low-power modes: a) Disable the RTC time stamp interrupt (TSIE bit in RTC_CR) b) Clear the RTC time stamp (TSF) flag c) Clear the PWR Wakeup (WUF) flag d) Enable the RTC TimeStamp interrupt e) Re-enter the low-power mode

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5.4.1 PWR power control register (PWR_CR)

Address offset: 0x00

Reset value: 0x0000 C000 (reset by wakeup from Standby mode)

Res.

VOS[1:0] rw rw

Res.

24 23 22 21 20

Res.

FISSR FMSSR

8 7 6 rw

5 rw

4 13 12 11 10 9

ADCDC1 Res.

MRUDS LPUDS FPDS DBP rw rw rw rw rw rw

PLS[2:0] rw rw

PVDE rw

19 rw

CSBF rc_w1

UDEN[1:0] rw

CWUF rc_w1

17 16

ODSWEN ODEN rw

1 rw

PDDS rw

LPDS rw

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 FISSR : Flash Interface Stop while System Run

0: Flash interface clock run (Default value)

1: Flash Interface clock off.

Note: This bit could not be set while executing with the Flash itself. It should be done with a specific routine executed from RAM.

Bit 20 FMSSR : Flash Memory Stop while System Run

0: Flash standard mode (Default value)

1: Flash forced to be in STOP or Deep Power Down mode (depending of FPDS value bit) by hardware.

Note: This bit could not be set while executing with the Flash itself. It should be done with a specific routine executed from RAM

Bits 19:18 UDEN[1:0] : Under-drive enable in stop mode

These bits are set by software. They allow to achieve a lower power consumption in Stop mode but with a longer wakeup time.

When set, the digital area has less leakage consumption when the device enters Stop mode.

00: Under-drive disable

01: Reserved

10: Reserved

11:Under-drive enable

Bit 17 ODSWEN : Over-drive switching enabled.

This bit is set by software. It is cleared automatically by hardware after exiting from Stop mode or when the ODEN bit is reset. When set, It is used to switch to Over-drive mode.

To set or reset the ODSWEN bit, the HSI or HSE must be selected as system clock.

The ODSWEN bit must only be set when the ODRDY flag is set to switch to Over-drive mode.

0: Over-drive switching disabled

1: Over-drive switching enable d

Note: On any over-drive switch (enabled or disabled), the system clock will be stalled during the internal voltage set up.

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Bit 16 ODEN : Over-drive enable

This bit is set by software. It is cleared automatically by hardware after exiting from Stop mode. It is used to enabled the Over-drive mode in order to reach a higher frequency.

To set or reset the ODEN bit, the HSI or HSE must be selected as system clock. When the

ODEN bit is set, the application must first wait for the Over-drive ready flag (ODRDY) to be set before setting the ODSWEN bit.

0: Over-drive disabled

1: Over-drive enabled

Bits 15:14 VOS[1:0] : Regulator voltage scaling output selection

These bits control the main internal voltage regulator output voltage to achieve a trade-off between performance and power consumption when the device does not operate at the maximum frequency (refer to the STM32F446xx datasheet for more details).

These bits can be modified only when the PLL is OFF. The new value programmed is active only when the PLL is ON. When the PLL is OFF, the voltage scale 3 is automatically selected.

00: Reserved (Scale 3 mode selected)

01: Scale 3 mode

10: Scale 2 mode

11: Scale 1 mode (reset value)

Bit 13 ADCDC1 :

0: No effect.

1: Refer to AN4073 for details on how to use this bit.

Note: This bit can only be set when operating at supply voltage range 2.7 to 3.6V and when the Prefetch is OFF.

Bit 12 Reserved, must be kept at reset value.

Bit 11 MRUDS : Main regulator in deepsleep under-drive mode

This bit is set and cleared by software.

0: Main regulator ON when the device is in Stop mode

1: Main Regulator in under-drive mode and Flash memory in power-down when the device is in Stop under-drive mode.

Bit 10 LPUDS : Low-power regulator in deepsleep under-drive mode

This bit is set and cleared by software.

0: Low-power regulator ON if LPDS bit is set when the device is in Stop mode

1: Low-power regulator in under-drive mode if LPDS bit is set and Flash memory in powerdown when the device is in Stop under-drive mode.

Bit 9 FPDS : Flash power-down in Stop mode

When set, the Flash memory enters power-down mode when the device enters Stop mode.

This allows to achieve a lower consumption in stop mode but a longer restart time.

0: Flash memory not in power-down when the device is in Stop mode

1: Flash memory in power-down when the device is in Stop mode

Bit 8 DBP : Disable backup domain write protection

In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), and the BRE bit of the PWR_CSR register, are protected against parasitic write access. This bit must be set to enable write access to these registers.

0: Access to RTC and RTC Backup registers and backup SRAM disabled

1: Access to RTC and RTC Backup registers and backup SRAM enabled

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Bits 7:5 PLS[2:0]: PVD level selection

These bits are written by software to select the voltage threshold detected by the Power

Voltage Detector

000: 2.0 V

001: 2.1 V

010: 2.3 V

011: 2.5 V

100: 2.6 V

101: 2.7 V

110: 2.8 V

111: 2.9 V

Note: Refer to the electrical characteristics of the datasheet for more details.

Bit 4 PVDE: Power voltage detector enable

This bit is set and cleared by software.

0: PVD disabled

1: PVD enabled

Bit 3 CSBF : Clear standby flag

This bit is always read as 0.

0: No effect

1: Clear the SBF Standby Flag (write).

Bit 2 CWUF: Clear wakeup flag

This bit is always read as 0.

0: No effect

1: Clear the WUF Wakeup Flag after 2 System clock cycles

Bit 1 PDDS : Power-down deepsleep

This bit is set and cleared by software. It works together with the LPDS bit.

0: Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the

LPDS bit.

1: Enter Standby mode when the CPU enters deepsleep.

Bit 0 LPDS: Low-power deepsleep

This bit is set and cleared by software. It works together with the PDDS bit.

0:Main voltage regulator ON during Stop mode

1: Low-power voltage regulator ON during Stop mode

5.4.2 PWR power control/status register (PWR_CSR)

Address offset: 0x04

Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)

Additional APB cycles are needed to read this register versus a standard APB read.

Res.

29 28 27 26

Res.

14 13 12 11 10

Res.

VOSRDY Res.

Res.

22 21 20

Res.

9 8 7 6 5 4

BRE EWUP1 EWUP2 Res.

Res.

rw rw rw

19 18 17 16

UDRDY[1:0] ODSWRDY ODRDY rc_w1 rc_w1 r r

3 2

BRR PVDO r r

SBF r

WUF r

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Bits 31:20 Reserved, must be kept at reset value.

Bits 19:18 UDRDY[1:0] : Under-drive ready flag

These bits are set by hardware when MCU entered stop Under-drive mode and exited.

When the under-drive mode is enabled, these bits are not set as long as the MCU has not entered stop mode yet. They are cleared by programming them to 1.

00: Under-drive is disabled

01: Reserved

10: Reserved

11:Under-drive mode is activated in Stop mode.

Bit 17 ODSWRDY : Over-drive mode switching ready

0: Over-drive mode is not active.

1: Over-drive mode is active on digital area on 1.2 V domain

Bit 16 ODRDY : Over-drive mode ready

0: Over-drive mode not ready.

1: Over-drive mode ready

Bit 14 VOSRDY : Regulator voltage scaling output selection ready bit

0: Not ready

1: Ready

Bits 13:10 Reserved, must be kept at reset value.

Bit 9 BRE : Backup regulator enable

When set, the Backup regulator (used to maintain backup SRAM content in Standby and

BAT

modes) is enabled. If BRE is reset, the backup regulator is switched off. The backup

SRAM can still be used but its content will be lost in the Standby and V

BAT

modes. Once set, the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that the data written into the RAM will be maintained in the Standby and V

BAT

0: Backup regulator disabled

modes.

1: Backup regulator enabled

Note: This bit is not reset when the device wakes up from Standby mode, by a system reset, or by a power reset.

Bit 8 EWUP1 : Enable WKUP1 pin

This bit is set and cleared by software.

0: WKUP1 pin is used for general purpose I/O. An event on the WKUP1 pin does not wakeup the device from Standby mode.

1: WKUP1 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP1 pin wakes-up the system from Standby mode).

Note: This bit is reset by a system reset.

Bit 7 EWUP2: Enable WKUP2 pin

This bit is set and cleared by software

0: WKUP2 pin is used for general purpose I/O. An event on the WKUP2 pin does not wakeup the device from Standby mode.

1: WKUP2 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP2 pin wakes-up the system from Standby mode).

Note: This bit is reset by a system reset.

Bits 7:4 Reserved, must be kept at reset value.

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RM0390 Power controller (PWR)

Bit 3 BRR : Backup regulator ready

Set by hardware to indicate that the Backup Regulator is ready.

0: Backup Regulator not ready

1: Backup Regulator ready

Note: This bit is not reset when the device wakes up from Standby mode or by a system reset or power reset.

Bit 2 PVDO: PVD output

This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.

0: V

1: V

is higher than the PVD threshold selected with the PLS[2:0] bits.

is lower than the PVD threshold selected with the PLS[2:0] bits.

Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after

Standby or reset until the PVDE bit is set.

Bit 1 SBF: Standby flag

This bit is set by hardware and cleared only by a POR/PDR (power-on reset/power-down

reset) or by setting the CSBF bit in the PWR power control register (PWR_CR)

0: Device has not been in Standby mode

1: Device has been in Standby mode

Bit 0 WUF: Wakeup flag

This bit is set by hardware and cleared either by a system reset or by setting the CWUF bit in the PWR_CR register.

0: No wakeup event occurred

1: A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or

Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup).

Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the

EWUP bit) when the WKUP pin level is already high.

5.5 PWR register map

The following table summarizes the PWR registers.

Table 20. PWR - register map and reset values

Offset Register

0x000

PWR_CR

Reset value 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0

0x004

PWR_CSR

Reset value 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 56 for the register boundary addresses.

0 0 0 0

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6 Reset and clock control (RCC)

RM0390

6.1 Reset

There are three types of reset, defined as system Reset, power Reset and backup domain

Reset.

A system reset sets all registers to their reset values except the reset flags in the clock

controller CSR register and the registers in the Backup domain (see Figure 13 ).

A system reset is generated when one of the following events occurs:

A low level on the NRST pin (external reset)

2. Window watchdog end of count condition (WWDG reset)

3. Independent watchdog end of count condition (IWDG reset)

4. A software reset (SW reset) (see Software reset )

5. Low-power management reset (see Low-power management reset )

Software reset

The reset source can be identified by checking the reset flags in the RCC clock control & status register (RCC_CSR) .

The SYSRESETREQ bit in Cortex

-M4 with FPU Application Interrupt and Reset Control

-M4 with

FPU technical reference manual for more details.

Low-power management reset

There are two ways of generating a low-power management reset:

Reset generated when entering the Standby mode:

This type of reset is enabled by resetting the nRST_STDBY bit in the user option bytes.

In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering the Standby mode.

2. Reset when entering the Stop mode:

This type of reset is enabled by resetting the nRST_STOP bit in the user option bytes.

In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering the Stop mode.

For further information on the user option bytes, refer to Section 3: Embedded Flash memory interface .

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A power reset is generated when one of the following events occurs:

Power-on/power-down reset (POR/PDR reset) or brownout (BOR) reset

2. When exiting the Standby mode

A power reset sets all registers to their reset values except the Backup domain (see

Figure 13

)

RM0390 Rev 6

RM0390 Reset and clock control (RCC)

These sources act on the NRST pin and it is always kept low during the delay phase. The

RESET service routine vector is fixed at address 0x0000_0004 in the memory map.

The system reset signal provided to the device is output on the NRST pin. The pulse generator guarantees a minimum reset pulse duration of 20 µs for each internal reset source. In case of an external reset, the reset pulse is generated while the NRST pin is asserted low.

Figure 13. Simplified diagram of the reset circuit

DDA

External reset

NRST

Filter

System reset

Pulse generator

(min 20 μs)

WWDG reset

IWDG reset

Power reset

Software reset

Low-power management reset

The Backup domain has two specific resets that affect only the Backup domain (see

Figure 13

ai16095c

The backup domain reset sets all RTC registers and the RCC_BDCR register to their reset values. The BKPSRAM is not affected by this reset. The only way of resetting the

BKPSRAM is through the Flash interface by requesting a protection level change from 1 to

A backup domain reset is generated when one of the following events occurs:

Software reset, triggered by setting the BDRST bit in the RCC Backup domain control register (RCC_BDCR)

2. V

or V

BAT

power on, if both supplies have previously been powered off.

6.2 Clocks

Three different clock sources can be used to drive the system clock (SYSCLK):

 HSI oscillator clock

 HSE oscillator clock

 Two main PLL (PLL) clocks

The devices have the two following secondary clock sources:

 32 kHz low-speed internal RC (LSI RC) which drives the independent watchdog and, optionally, the RTC used for Auto-wakeup from the Stop/Standby mode.

 32.768 kHz low-speed external crystal (LSE crystal) which optionally drives the RTC clock (RTCCLK)

Each clock source can be switched on or off independently when it is not used, to optimize power consumption.

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LSI RC

32 kHz

OSC32_IN

OSC32_OUT

LES OSC

32.768 kHz

LSI

LSE

Figure 14. Clock tree

Enable watchdog

IWDGCLK

RTC / AWU enable

RTC / AWU clock

HSI

SYSCLK

PCLK1

LSE

HSI / 488

MCO2

/ 1 → 5

MCO1

/ 1 → 5

SYSCLK

PLLI2S

/ 2 → 31

Peripheral clock enable

Clock enable

1 not (sleep or deepsleep) not deepsleep

OSC_IN

OSC_OUT

PLL

PLLSAI

PLLI2S

/ P

/ Q

/ R

/ P

/ Q

/ R

/ P

/ Q

/ R

I2S_CKIN

USB2.0 PHY

24 → 60 MHz

4-25 MHz

HSE OSC

HSE

16 MHz

HSI RC

PLLCLK

PLLQ

PLLR

/ M1

/ M3

PLLSAIP

PLLSAIQ

DIV

PLLI2SP

PLLI2SR

/ M2

DIV

HSI

PLLI2S_SAICLK

HSE

HSI

PLLCLK

PLLR

System clock

SYSCLK

PLL48CLK

AHB

PRESC

/ 1,2,..512

Peripheral clock enable clock enable

/ 8

APB1

PRESC

/ 1,2,4,8,16

Peripheral clock enable

Peripheral clock enable if (APB1 presc = 1) x1 else x2

APB2

PRESC

/ 1,2,4,8,16

Peripheral clock enable if (APB2 presc = 1) x1 else x2

Peripheral clock enable

PLLI2S_SAICLK

Clock enable

I2S1 clocks

I2S_CKIN

Clock enable

I2S2 clocks

Clock enable

PLLI2SP

Clock enable

OTG_HS_SCL

RM0390

FMPI2C1 clock

HDMI-CEC clock

SDIO clock

Power ctrl clock

CPU clock

FCLK Cortex free-running clock

AHB peripheral clocks

SysTick clock

APB1 peripheral clocks

APB1 timer clocks

APB2 peripheral clocks

APB2 timer clocks

USB 48 MHz clock

SAI2 clock

SAI1 clock

SPDIFRX-IN clock

USBHS

ULPI clock

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1. For full details about the internal and external clock source characteristics, refer to the Electrical characteristics section in the device datasheet.

2. When TIMPRE bit of the RCC_DCKCFGR register is reset, if APBx prescaler is 1, then TIMxCLK = PCLKx,

RM0390 Rev 6

RM0390 Reset and clock control (RCC) otherwise TIMxCLK = 2x PCLKx.

3. When TIMPRE bit in the RCC_DCKCFGR register is set, if APBx prescaler is 1,2 or 4, then TIMxCLK =

HCLK, otherwise TIMxCLK = 4x PCLKx.

The clock controller provides a high degree of flexibility to the application in the choice of the external crystal or the oscillator to run the core and peripherals at the highest frequency and, guarantee the appropriate frequency for peripherals that need a specific clock like USB

OTG FS and HS, I2S, SAI, and SDIO.

Several prescalers are used to configure the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB domain is

180 MHz. The maximum allowed frequency of the high-speed APB2 domain is 90 MHz. The maximum allowed frequency of the low-speed APB1 domain is 45 MHz

All peripheral clocks are derived from the system clock (SYSCLK) except for:

 The USB OTG FS clock (48 MHz), which is coming from a specific output of the PLL

(PLLP) or PLLSAI (PLLSAIP)

 The SDIO clock (48 MHz) which is coming from a specific output of the PLL48CLK

(PLLQ, PLLSAIP), or System Clock.

 I2S1/2 clocks

To achieve high-quality audio performance and for a better configuration flexibility, the

I2S1 clock and I2S2 clock (which are respectively clocks for I2Ss mapped on APB1 and APB2) can be derived from four sources: specific main PLL output, a specific

PLLI2S output, from an external clock mapped on the I2S_CKIN pin or from HSI/HSE

 SAIs clock

The SAI1/SAI2 clocks are generated from a specific PLL (Main PLL, PLLSAI, or

PLLI2S), from an external clock mapped on the I2S_CKIN pin or from HSI/HSE clock.

The PLLSAI can be used as clock source for SAI1 peripheral in case the PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or

11.2896 MHz), and the application requires both frequencies at the same time.

 The USB OTG HS (60 MHz) clock which is provided from the external PHY.

 SPDIF-Rx clock

The SPDIF-Rx clock is generated from a specific output of PLLI2S or from a specific output of main PLL.

 HDMI-CEC clock which is generated from LSE or HSI divided by 488.

 FMPI2C1 clock which can also be generated from HSI, SYSCLK or APB1 clock.

The timer clock frequencies are automatically set by hardware. There are two cases depending on the value of TIMPRE bit in RCC_CFGR register:

 If TIMPRE bit in RCC_DKCFGR register is reset:

If the APB prescaler is configured to a division factor of 1, the timer clock frequencies

(TIMxCLK) are set to PCLKx. Otherwise, the timer clock frequencies are twice the frequency of the APB domain to which the timers are connected: TIMxCLK = 2xPCLKx.

 If TIMPRE bit in RCC_DKCFGR register is set:

If the APB prescaler is configured to a division factor of 1, 2 or 4, the timer clock frequencies (TIMxCLK) are set to HCLK. Otherwise, the timer clock frequencies is four times the frequency of the APB domain to which the timers are connected: TIMxCLK =

4xPCLKx.

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The RCC feeds the external clock of the Cortex System Timer (SysTick) with the AHB clock

(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock

(HCLK), configurable in the SysTick control and status register.

FCLK acts as Cortex ® -M4 with FPU free-running clock. For more details, refer to the

Cortex ® -M4 with FPU technical reference manual.

The high speed external clock signal (HSE) can be generated from two possible clock sources:

 HSE external crystal/ceramic resonator

 HSE external user clock

The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

Figure 15. HSE/ LSE clock sources (hardware configuration)

External clock

OSC_OUT

(HI-Z)

External source

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OSC_IN OSC_OUT

Crystal/ceramic resonators

Load capacitors

External source (HSE bypass)

In this mode, an external clock source must be provided. You select this mode by setting the

HSEBYP and HSEON bits in the

RCC clock control register (RCC_CR)

. The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC_IN pin while the

OSC_OUT pin should be left HI-Z. See

Figure 15

External crystal/ceramic resonator (HSE crystal)

The HSE has the advantage of producing a very accurate rate on the main clock.

The associated hardware configuration is shown in

Figure 15

. Refer to the electrical characteristics section of the datasheet for more details.

The HSERDY flag in the

RCC clock control register (RCC_CR)

indicates if the high-speed external oscillator is stable or not. At startup, the clock is not released until this bit is set by

RM0390 Rev 6

RM0390 Reset and clock control (RCC) hardware. An interrupt can be generated if enabled in the

RCC clock interrupt register

(RCC_CIR) .

The HSE Crystal can be switched on and off using the HSEON bit in the RCC clock control register (RCC_CR) .

The HSI clock signal is generated from an internal 16 MHz RC oscillator and can be used directly as a system clock, or used as PLL input.

The HSI RC oscillator has the advantage of providing a clock source at low cost (no external components). It also has a faster startup time than the HSE crystal oscillator however, even with calibration the frequency is less accurate than an external crystal oscillator or ceramic resonator.

Calibration

RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T

= 25 °C.

After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the

RCC clock control register (RCC_CR) .

If the application is subject to voltage or temperature variations this may affect the RC oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]

bits in the RCC clock control register (RCC_CR) .

The HSIRDY flag in the

RCC clock control register (RCC_CR)

indicates if the HSI RC is stable or not. At startup, the HSI RC output clock is not released until this bit is set by hardware.

The HSI RC can be switched on and off using the HSION bit in the

RCC clock control register (RCC_CR) .

The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal oscillator fails. Refer to

Section 6.2.7: Clock security system (CSS) on page 123

The STM32F446xx devices feature three PLLs:

 A main PLL (PLL) clocked by the HSE or HSI oscillator and featuring three different output clocks:

– The first output is used to generate the high speed system clock (up to 180 MHz)

– The second output can be used to generate the clock for the USB OTG FS

(48 MHz) or the SDIO ( ≤ 48 MHz).

– The third output can be used to generate the clock for I2S1 and I2S2 clocks,

SPDIF-Rx clock or the high speed system clock.

 Two dedicated PLLs (PLLI2S and PLLSAI) used to generate an accurate clock to achieve high-quality audio performance on the I2S and SAIs interfaces. PLLSAI and

PLLI2S are also used to generate SPDIF-Rx clock or the 48 MHz clock for USB OTG

FS and SDIO.

Since the main-PLL configuration parameters cannot be changed once PLL is enabled, it is recommended to configure PLL before enabling it (selection of the HSI or HSE oscillator as

PLL clock source, and configuration of division factors M, N, P, R and Q).

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The PLLI2S and PLLSAI use the same input clock as PLL (PLLSRC bit is common to both

PLLs). However, the PLLI2S and PLLSAI have dedicated enable/disable and division factors (M, N, P, R and R) configuration bits. Once the PLLI2S and PLLSAI are enabled, the configuration parameters cannot be changed.

The three PLLs are disabled by hardware when entering Stop and Standby modes, or when

an HSE failure occurs when HSE or PLL (clocked by HSE) are used as system clock. RCC

PLL configuration register (RCC_PLLCFGR) ,

RCC clock configuration register

(RCC_CFGR)

, and

RCC dedicated clock configuration register (RCC_DCKCFGR) can be

used to configure PLL, PLLI2S, and PLLSAI.

The LSE clock is generated from a 32.768 kHz low-speed external crystal or ceramic resonator. It has the advantage providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions.

The LSE oscillator is switched on and off using the LSEON bit in

RCC Backup domain control register (RCC_BDCR) .

The LSERDY flag in the RCC Backup domain control register (RCC_BDCR)

indicates if the

LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the

RCC clock interrupt register (RCC_CIR) .

External source (LSE bypass)

In this mode, an external clock source must be provided. It must have a frequency up to

1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the RCC Backup domain control register (RCC_BDCR) . The external clock signal (square, sinus or triangle)

with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be

left HI-Z. See Figure 15 .

6.2.6

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The LSI RC acts as an low-power clock source that can be kept running in Stop and

Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The clock frequency is around 32 kHz. For more details, refer to the electrical characteristics section of the datasheets.

The LSI RC can be switched on and off using the LSION bit in the

RCC clock control & status register (RCC_CSR) .

The LSIRDY flag in the

RCC clock control & status register (RCC_CSR) indicates if the low-

speed internal oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the

RCC clock interrupt register

(RCC_CIR) .

System clock (SYSCLK) selection

After a system reset, the HSI oscillator is selected as the system clock. When a clock source is used directly or through PLL as the system clock, it is not possible to stop it.

A switch from one clock source to another occurs only if the target clock source is ready

(clock stable after startup delay or PLL locked). If a clock source that is not yet ready is selected, the switch occurs when the clock source is ready. Status bits in the

RCC clock

RM0390 Rev 6

RM0390

6.2.7

Note:

Reset and clock control (RCC)

control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently

used as the system clock.

Clock security system (CSS)

The clock security system can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.

If a failure is detected on the HSE clock, this oscillator is automatically disabled, a clock failure event is sent to the break inputs of advanced-control timers TIM1 and TIM8, and an interrupt is generated to inform the software about the failure (clock security system interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the

Cortex

-M4 with FPU NMI (non-maskable interrupt) exception vector.

When the CSS is enabled, if the HSE clock happens to fail, the CSS generates an interrupt, which causes the automatic generation of an NMI. The NMI is executed indefinitely unless the CSS interrupt pending bit is cleared. As a consequence, the application has to clear the

CSS interrupt in the NMI ISR by setting the CSSC bit in the Clock interrupt register

(RCC_CIR).

If the HSE oscillator is used directly or indirectly as the system clock (indirectly meaning that it is directly used as PLL input clock, and that PLL clock is the system clock) and a failure is detected, then the system clock switches to the HSI oscillator and the HSE oscillator is disabled.

If the HSE oscillator clock was the clock source of PLL used as the system clock when the failure occurred, PLL is also disabled. In this case, if the PLLI2S was enabled, it is also disabled when the HSE fails.

Once the RTCCLK clock source has been selected, the only possible way of modifying the selection is to reset the power domain.

The RTCCLK clock source can be either the HSE 1 MHz (HSE divided by a programmable prescaler), the LSE or the LSI clock. This is selected by programming the RTCSEL[1:0] bits in the

RCC Backup domain control register (RCC_BDCR)

and the RTCPRE[4:0] bits in

RCC clock configuration register (RCC_CFGR) . This selection cannot be modified without

resetting the Backup domain.

If the LSE is selected as the RTC clock, the RTC will work normally if the backup or the system supply disappears. If the LSI is selected as the AWU clock, the AWU state is not guaranteed if the system supply disappears. If the HSE oscillator divided by a value between 2 and 31 is used as the RTC clock, the RTC state is not guaranteed if the backup or the system supply disappears.

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Note:

RM0390

The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. As a consequence:

 If LSE is selected as the RTC clock:

– The RTC continues to work even if the V

BAT

supply is maintained.

supply is switched off, provided the

 If LSI is selected as the Auto-wakeup unit (AWU) clock:

– The AWU state is not guaranteed if the V

supply is powered off. Refer to

Section 6.2.5: LSI clock on page 122 for more details on LSI calibration.

 If the HSE clock is used as the RTC clock:

– The RTC state is not guaranteed if the V

supply is powered off or if the internal voltage regulator is powered off (removing power from the 1.2 V domain).

To read the RTC calendar register when the APB1 clock frequency is less than seven times the RTC clock frequency (f

APB1

< 7xf

RTCLCK

), the software must read the calendar time and date registers twice. The data are correct if the second read access to RTC_TR gives the same result than the first one. Otherwise a third read access must be performed.

If the independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG.

Two microcontroller clock output (MCO) pins are available:

 MCO1

You can output four different clock sources onto the MCO1 pin (PA8) using the configurable prescaler (from 1 to 5):

– HSI clock

– LSE clock

– HSE clock

– PLL clock

The desired clock source is selected using the MCO1PRE[2:0] and MCO1[1:0] bits in the

RCC clock configuration register (RCC_CFGR)

 MCO2

You can output four different clock sources onto the MCO2 pin (PC9) using the configurable prescaler (from 1 to 5):

– HSE clock

– PLL clock

– System clock (SYSCLK)

– PLLI2S clock

The desired clock source is selected using the MCO2PRE[2:0] and MCO2 bits in the

RCC clock configuration register (RCC_CFGR)

For the different MCO pins, the corresponding GPIO port has to be programmed in alternate function mode.

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RM0390 Reset and clock control (RCC)

The selected clock to output onto MCO must not exceed 100 MHz (the maximum I/O speed).

It is possible to indirectly measure the frequencies of all on-board clock source generators by means of the input capture of TIM5 channel4 and TIM11 channel1 as shown in

Figure 16

and Figure 17

Internal/external clock measurement using TIM5 channel4

TIM5 has an input multiplexer which allows choosing whether the input capture is triggered by the I/O or by an internal clock. This selection is performed through the TI4_RMP [1:0] bits in the TIM5_OR register.

The primary purpose of having the LSE connected to the channel4 input capture is to be able to precisely measure the HSI (this requires to have the HSI used as the system clock source). The number of HSI clock counts between consecutive edges of the LSE signal provides a measurement of the internal clock period. Taking advantage of the high precision of LSE crystals (typically a few tens of ppm) we can determine the internal clock frequency with the same resolution, and trim the source to compensate for manufacturing-process and/or temperature- and voltage-related frequency deviations.

The HSI oscillator has dedicated, user-accessible calibration bits for this purpose.

The basic concept consists in providing a relative measurement (e.g. HSI/LSE ratio): the precision is therefore tightly linked to the ratio between the two clock sources. The greater the ratio, the better the measurement.

It is also possible to measure the LSI frequency: this is useful for applications that do not have a crystal. The ultralow-power LSI oscillator has a large manufacturing process deviation: by measuring it versus the HSI clock source, it is possible to determine its frequency with the precision of the HSI. The measured value can be used to have more accurate RTC time base timeouts (when LSI is used as the RTC clock source) and/or an

IWDG timeout with an acceptable accuracy.

Use the following procedure to measure the LSI frequency:

Enable the TIM5 timer and configure channel4 in Input capture mode.

2. This bit is set the TI4_RMP bits in the TIM5_OR register to 0x01 to connect the LSI clock internally to TIM5 channel4 input capture for calibration purposes.

3. Measure the LSI clock frequency using the TIM5 capture/compare 4 event or interrupt.

4. Use the measured LSI frequency to update the prescaler of the RTC depending on the desired time base and/or to compute the IWDG timeout.

Figure 16. Frequency measurement with TIM5 in Input capture mode

TIM5

TI4_RMP[1:0]

GPIO

RTC_WakeUp_IT

LSE

LSI

TI4 ai17741d

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Internal/external clock measurement using TIM11 channel1

TIM11 has an input multiplexer which allows choosing whether the input capture is triggered by the I/O, by SPDIF-Rx Frame Synch or by an internal clock. This selection is performed through TI1_RMP [1:0] bits in the TIM11_OR register. The HSE_RTC clock (HSE divided by a programmable prescaler) is connected to channel 1 input capture to have a rough indication of the external crystal frequency. This requires that the HSI is the system clock source. This can be useful for instance to ensure compliance with the IEC 60730/IEC 61335 standards which require to be able to determine harmonic or subharmonic frequencies (–

50/+100% deviations).

Figure 17. Frequency measurement with TIM11 in Input capture mode

TIM11

TI1_RMP[1:0]

GPIO

HSE_RTC(1 MHz)

SPDIFRX_FRAME_SYNC

TI1

MS37331V1

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RM0390 Reset and clock control (RCC)

Refer to Section 1.2: List of abbreviations for registers

for a list of abbreviations used in register descriptions.

Res.

15 r

Address offset: 0x00

Reset value: 0x0000 XX83 where X is undefined.

Access: no wait state, word, half-word and byte access

Res.

29 28

PLLSAI

RDY r

PLLSAI

ON rw

13 12

PLLI2S

RDY r

PLLI2S

ON rw

HSICAL[7:0] r r r r r

PLL

RDY r

9 r

PLL

ON rw

8 r

Res.

7 rw

Res.

6 5

HSITRIM[4:0]

4 rw rw rw

CSS

ON rw

3 rw

HSE

BYP rw

Res.

HSE

RDY r

HSI

RDY r

Bits 31:28 Reserved, must be kept at reset value.

Bit 29 PLLSAIRDY : PLLSAI clock ready flag

Set by hardware to indicate that the PLLSAI is locked.

0: PLLSAI unlocked

1: PLLSAI locked

Bit 28 PLLSAION : PLLSAI enable

Set and cleared by software to enable PLLSAI.

Cleared by hardware when entering Stop or Standby mode.

0: PLLSAI OFF

1: PLLSAI ON

Bit 27 PLLI2SRDY : PLLI2S clock ready flag

Set by hardware to indicate that the PLLI2S is locked.

0: PLLI2S unlocked

1: PLLI2S locked

Bit 26 PLLI2SON : PLLI2S enable

Set and cleared by software to enable PLLI2S.

Cleared by hardware when entering Stop or Standby mode.

0: PLLI2S OFF

1: PLLI2S ON

Bit 25 PLLRDY : Main PLL (PLL) clock ready flag

Set by hardware to indicate that PLL is locked.

0: PLL unlocked

1: PLL locked

Bit 24 PLLON : Main PLL (PLL) enable

Set and cleared by software to enable PLL.

Cleared by hardware when entering Stop or Standby mode. This bit cannot be reset if PLL clock is used as the system clock.

0: PLL OFF

1: PLL ON

HSE

ON rw

HSI

ON rw

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Bits 23:20 Reserved, must be kept at reset value.

Bit 19 CSSON : Clock security system enable

Set and cleared by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if an oscillator failure is detected.

0: Clock security system OFF (Clock detector OFF)

1: Clock security system ON (Clock detector ON if HSE oscillator is stable, OFF if not)

Bit 18 HSEBYP : HSE clock bypass

Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit, to be used by the device.

The HSEBYP bit can be written only if the HSE oscillator is disabled.

0: HSE oscillator not bypassed

1: HSE oscillator bypassed with an external clock

Bit 17 HSERDY : HSE clock ready flag

Set by hardware to indicate that the HSE oscillator is stable. After the HSEON bit is cleared,

HSERDY goes low after 6 HSE oscillator clock cycles.

0: HSE oscillator not ready

1: HSE oscillator ready

Bit 16 HSEON : HSE clock enable

Set and cleared by software.

Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.

0: HSE oscillator OFF

1: HSE oscillator ON

Bits 15:8 HSICAL[7:0] : Internal high-speed clock calibration

These bits are initialized automatically at startup.

Bits 7:3 HSITRIM[4:0] : Internal high-speed clock trimming

These bits provide an additional user-programmable trimming value that is added to the

HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the internal HSI RC.

Bit 2 Reserved, must be kept at reset value.

Bit 1 HSIRDY : Internal high-speed clock ready flag

Set by hardware to indicate that the HSI oscillator is stable. After the HSION bit is cleared,

HSIRDY goes low after 6 HSI clock cycles.

0: HSI oscillator not ready

1: HSI oscillator ready

Bit 0 HSION : Internal high-speed clock enable

Set and cleared by software.

Set by hardware to force the HSI oscillator ON when leaving the Stop or Standby mode or in case of a failure of the HSE oscillator used directly or indirectly as the system clock. This bit cannot be cleared if the HSI is used directly or indirectly as the system clock.

0: HSI oscillator OFF

1: HSI oscillator ON

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RM0390 Rev 6

RM0390 Reset and clock control (RCC)

6.3.2 RCC configuration register (RCC_PLLCFGR)

Address offset: 0x04

Reset value: 0x2400 3010

Access: no wait state, word, half-word and byte access.

This register is used to configure the PLL clock outputs according to the formulas:

 f

(VCO clock)

= f

(PLL clock input)

× (PLLN / PLLM)

 f

(PLL general clock output)

= f

(VCO clock)

/ PLLP

 f

(USB OTG FS, SDIO)

= f

(VCO clock)

/ PLLQ

Res.

30 rw

PLLR[2:0] rw

28 rw

12 rw rw rw

27 rw

11 rw

PLLN[8:0]

PLLQ[3:0] rw rw

9 rw rw

24 rw

8 rw

23 22 21

Res.

PLLSRC Res.

7 6 5 rw rw rw

Res.

4 rw

Res.

3 2

PLLM[5:0] rw rw

17 16

PLLP[1:0] rw rw

1 0 rw rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:28 PLLR[2:0]: Main PLL division factor for I2Ss, SAIs, SYSTEM and SPDIF-Rx clocks

Set and cleared by software to control the frequency of the clock. These bits should be written only if PLL is disabled.

Clock frequency = VCO frequency / PLLR with 2 ≤ PLLR ≤ 7

000: PLLR = 0, wrong configuration

001: PLLR = 1, wrong configuration

010: PLLR = 2

011: PLLR = 3

...

111: PLLR = 7

Bits 27:24 PLLQ[3:0]: Main PLL (PLL) division factor for USB OTG FS, SDIOclocks

Set and cleared by software to control the frequency of USB OTG FS clock and the

SDIOclock. These bits should be written only if PLL is disabled.

Caution: The USB OTG FS requires a 48 MHz clock to work correctly. The SDIOneeds a frequency lower than or equal to 48 MHz to work correctly.

USB OTG FS clock frequency = VCO frequency / PLLQ with 2 ≤ PLLQ ≤ 15

0000: PLLQ = 0, wrong configuration

0001: PLLQ = 1, wrong configuration

0010: PLLQ = 2

0011: PLLQ = 3

0100: PLLQ = 4

...

1111: PLLQ = 15

Bit 23 Reserved, must be kept at reset value.

Bit 22 PLLSRC: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source

Set and cleared by software to select PLL and PLLI2S clock source. This bit can be written only when PLL and PLLI2S are disabled.

0: HSI clock selected as PLL and PLLI2S clock entry

1: HSE oscillator clock selected as PLL and PLLI2S clock entry

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Bits 21:18 Reserved, must be kept at reset value.

Bits 17:16 PLLP[1:0]: Main PLL (PLL) division factor for main system clock

Set and cleared by software to control the frequency of the general PLL output clock. These bits can be written only if PLL is disabled.

Caution: The software has to set these bits correctly not to exceed 180 MHz on this domain.

PLL output clock frequency = VCO frequency / PLLP with PLLP = 2, 4, 6, or 8

00: PLLP = 2

01: PLLP = 4

10: PLLP = 6

11: PLLP = 8

Bits 14:6 PLLN[8:0]: Main PLL (PLL) multiplication factor for VCO

Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when PLL is disabled. Only half-word and word accesses are allowed to write these bits.

Caution: The software has to set these bits correctly to ensure that the VCO output frequency is between 100 and 432 MHz.

VCO output frequency = VCO input frequency × PLLN with 50 ≤ PLLN ≤ 432

000000000: PLLN = 0, wrong configuration

000000001: PLLN = 1, wrong configuration ...

000110010: PLLN = 50

...

001100011: PLLN = 99

001100100: PLLN = 100

...

110110000: PLLN = 432

110110001: PLLN = 433, wrong configuration ...

111111111: PLLN = 511, wrong configuration

Note: Between 50 and 99 multiplication factors are possible for VCO input frequency higher than 1 MHz. However care must be taken to fulfill the minimum VCO output frequency as specified above.

Bits 5:0 PLLM[5:0]: Division factor for the main PLL (PLL) input clock

Set and cleared by software to divide the PLL input clock before the VCO. These bits can be written only when the PLL is disabled.

Caution: The software has to set these bits correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit

PLL jitter.

VCO input frequency = PLL input clock frequency / PLLM with 2 ≤ PLLM ≤ 63

000000: PLLM = 0, wrong configuration

000001: PLLM = 1, wrong configuration

000010: PLLM = 2

000011: PLLM = 3

000100: PLLM = 4

...

111110: PLLM = 62

111111: PLLM = 63

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RM0390 Rev 6

RM0390 Reset and clock control (RCC)

Address offset: 0x08

Reset value: 0x0000 0000

Access: 0 ≤ wait state ≤ 2, word, half-word and byte access

1 or 2 wait states inserted only if the access occurs during a clock source switch.

31 30

MCO2[1:0] rw

15 14 rw

PPRE2[2:0] rw

29 28

MCO2 PRE[2:0]

27 rw

13 rw

12 rw

11 rw rw

PPRE1[2:0] rw

26 25

MCO1 PRE[2:0]

24 rw

10 rw

9 rw

Res.

7 rw

MCO1

21 rw

6 5

HPRE[3:0] rw rw

20 rw

4 rw

19 18

RTCPRE[4:0]

17 rw

3 rw

2 rw

1 r

SWS[1:0] r

16 rw

0 rw

SW[1:0} rw

Bits 31:30 MCO2[1:0]: Microcontroller clock output 2

Set and cleared by software. Clock source selection may generate glitches on MCO2. It is highly recommended to configure these bits only after reset before enabling the external oscillators and the PLLs.

00: System clock (SYSCLK) selected

01: PLLI2S clock selected

10: HSE oscillator clock selected

11: PLL clock selected

Bits 27:29 MCO2PRE: MCO2 prescaler

Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset before enabling the external oscillators and the PLLs.

0xx: no division

100: division by 2

101: division by 3

110: division by 4

111: division by 5

Bits 24:26 MCO1PRE: MCO1 prescaler

Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset before enabling the external oscillators and the PLL.

0xx: no division

100: division by 2

101: division by 3

110: division by 4

111: division by 5

Bit 23 Reserved, must be kept at reset value.

Bits 22:21 MCO1: Microcontroller clock output 1

Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset before enabling the external oscillators and PLL.

00: HSI clock selected

01: LSE oscillator selected

10: HSE oscillator clock selected

11: PLL clock selected

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Bits 20:16 RTCPRE: HSE division factor for RTC clock

Set and cleared by software to divide the HSE clock input clock to generate a 1 MHz clock for RTC.

Caution: The software has to set these bits correctly to ensure that the clock supplied to the

RTC is 1 MHz. These bits must be configured if needed before selecting the RTC clock source.

00000: no clock

00001: no clock

00010: HSE/2

00011: HSE/3

00100: HSE/4

...

11110: HSE/30

11111: HSE/31

Bits 15:13 PPRE2: APB high-speed prescaler (APB2)

Set and cleared by software to control APB high-speed clock division factor.

Caution: The software has to set these bits correctly not to exceed 90 MHz on this domain.

The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after

PPRE2 write.

0xx: AHB clock not divided

100: AHB clock divided by 2

101: AHB clock divided by 4

110: AHB clock divided by 8

111: AHB clock divided by 16

Bits 12:10 PPRE1: APB Low speed prescaler (APB1)

Set and cleared by software to control APB low-speed clock division factor.

Caution: The software has to set these bits correctly not to exceed 45 MHz on this domain.

The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after

PPRE1 write.

0xx: AHB clock not divided

100: AHB clock divided by 2

101: AHB clock divided by 4

110: AHB clock divided by 8

111: AHB clock divided by 16

Bits 9:8 Reserved, must be kept at reset value.

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RM0390 Rev 6

RM0390 Reset and clock control (RCC)

Bits 7:4 HPRE: AHB prescaler

Set and cleared by software to control AHB clock division factor.

Caution: The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after

HPRE write.

Caution: The AHB clock frequency must be at least 25 MHz when the Ethernet is used.

0xxx: system clock not divided

1000: system clock divided by 2

1001: system clock divided by 4

1010: system clock divided by 8

1011: system clock divided by 16

1100: system clock divided by 64

1101: system clock divided by 128

1110: system clock divided by 256

1111: system clock divided by 512

Bits 3:2 SWS[1:0]: System clock switch status

Set and cleared by hardware to indicate which clock source is used as the system clock.

00: HSI oscillator used as the system clock

01: HSE oscillator used as the system clock

10: PLL used as the system clock

11: PLL_R used as the system clock

Bits 1:0 SW[1:0]: System clock switch

Set and cleared by software to select the system clock source.

Set by hardware to force the HSI selection when leaving the Stop or Standby mode or in case of failure of the HSE oscillator used directly or indirectly as the system clock.

00: HSI oscillator selected as system clock

01: HSE oscillator selected as system clock

10: PLL_P selected as system clock

11: PLL_R selected as system clock

Address offset: 0x0C

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Res.

PLLSAI

RDYIE rw

13 12

PLLI2S

RDYIE rw

PLL

RDYIE rw

HSE

RDYIE rw

HSI

RDYIE rw

Res.

LSE

RDYIE rw

LSI

RDYIE rw

Res.

CSSC w

CSSF r

PLLSAI

RDYC w

PLLSAI

RDYF r

PLLI2S

RDYC w

PLLI2S

RDYF r

PLL

RDYC w

PLL

RDYF r

HSE

RDYC w

HSE

RDYF r

HSI

RDYC w

HSI

RDYF r

LSE

RDYC w

LSE

RDYF r

LSI

RDYC w

LSI

RDYF r

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Bits 31:24 Reserved, must be kept at reset value.

Bit 23 CSSC: Clock security system interrupt clear

This bit is set by software to clear the CSSF flag.

0: No effect

1: Clear CSSF flag

Bit 22 PLLSAIRDYC : PLLSAI Ready Interrupt Clear

This bit is set by software to clear PLLSAIRDYF flag. It is reset by hardware when the

PLLSAIRDYF is cleared.

0: PLLSAIRDYF not cleared

1: PLLSAIRDYF cleared

Bit 21 PLLI2SRDYC: PLLI2S ready interrupt clear

This bit is set by software to clear the PLLI2SRDYF flag.

0: No effect

1: PLLI2SRDYF cleared

Bit 20 PLLRDYC: Main PLL(PLL) ready interrupt clear

This bit is set by software to clear the PLLRDYF flag.

0: No effect

1: PLLRDYF cleared

Bit 19 HSERDYC: HSE ready interrupt clear

This bit is set by software to clear the HSERDYF flag.

0: No effect

1: HSERDYF cleared

Bit 18 HSIRDYC: HSI ready interrupt clear

This bit is set software to clear the HSIRDYF flag.

0: No effect

1: HSIRDYF cleared

Bit 17 LSERDYC: LSE ready interrupt clear

This bit is set by software to clear the LSERDYF flag.

0: No effect

1: LSERDYF cleared

Bit 16 LSIRDYC: LSI ready interrupt clear

This bit is set by software to clear the LSIRDYF flag.

0: No effect

1: LSIRDYF cleared

Bit 15 Reserved, must be kept at reset value.

Bit 14 PLLSAIRDYIE : PLLSAI Ready Interrupt Enable

This bit is set and reset by software to enable/disable interrupt caused by PLLSAI lock.

0: PLLSAI lock interrupt disabled

1: PLLSAI lock interrupt enabled

Bit 13 PLLI2SRDYIE: PLLI2S ready interrupt enable

This bit is set and cleared by software to enable/disable interrupt caused by PLLI2S lock.

0: PLLI2S lock interrupt disabled

1: PLLI2S lock interrupt enabled

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RM0390 Rev 6

RM0390 Reset and clock control (RCC)

Bit 12 PLLRDYIE: Main PLL (PLL) ready interrupt enable

This bit is set and cleared by software to enable/disable interrupt caused by PLL lock.

0: PLL lock interrupt disabled

1: PLL lock interrupt enabled

Bit 11 HSERDYIE: HSE ready interrupt enable

This bit is set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization.

0: HSE ready interrupt disabled

1: HSE ready interrupt enabled

Bit 10 HSIRDYIE: HSI ready interrupt enable

This bit is set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization.

0: HSI ready interrupt disabled

1: HSI ready interrupt enabled

Bit 9 LSERDYIE: LSE ready interrupt enable

This bit is set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization.

0: LSE ready interrupt disabled

1: LSE ready interrupt enabled

Bit 8 LSIRDYIE: LSI ready interrupt enable

This bit is set and cleared by software to enable/disable interrupt caused by LSI oscillator stabilization.

0: LSI ready interrupt disabled

1: LSI ready interrupt enabled

Bit 7 CSSF: Clock security system interrupt flag

This bit is set by hardware when a failure is detected in the HSE oscillator.

It is cleared by software by setting the CSSC bit.

0: No clock security interrupt caused by HSE clock failure

1: Clock security interrupt caused by HSE clock failure

Bit 6 PLLSAIRDYF : PLLSAI Ready Interrupt flag

This bit is set by hardware when the PLLSAI is locked and PLLSAIRDYDIE is set.

It is cleared by software by setting the PLLSAIRDYC bit.

0: No clock ready interrupt caused by PLLSAI lock

1: Clock ready interrupt caused by PLLSAI lock

Bit 5 PLLI2SRDYF: PLLI2S ready interrupt flag

This bit is set by hardware when the PLLI2S is locked and PLLI2SRDYDIE is set.

It is cleared by software by setting the PLLRI2SDYC bit.

0: No clock ready interrupt caused by PLLI2S lock

1: Clock ready interrupt caused by PLLI2S lock

Bit 4 PLLRDYF: Main PLL (PLL) ready interrupt flag

This bit is set by hardware when PLL is locked and PLLRDYDIE is set.

It is cleared by software setting the PLLRDYC bit.

0: No clock ready interrupt caused by PLL lock

1: Clock ready interrupt caused by PLL lock

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Bit 3 HSERDYF: HSE ready interrupt flag

This bit is set by hardware when External High Speed clock becomes stable and

HSERDYDIE is set.

It is cleared by software by setting the HSERDYC bit.

0: No clock ready interrupt caused by the HSE oscillator

1: Clock ready interrupt caused by the HSE oscillator

Bit 2 HSIRDYF: HSI ready interrupt flag

This bit is set by hardware when the Internal High Speed clock becomes stable and

HSIRDYDIE is set.

It is cleared by software by setting the HSIRDYC bit.

0: No clock ready interrupt caused by the HSI oscillator

1: Clock ready interrupt caused by the HSI oscillator

Bit 1 LSERDYF: LSE ready interrupt flag

This bit is set by hardware when the External Low Speed clock becomes stable and

LSERDYDIE is set.

It is cleared by software by setting the LSERDYC bit.

0: No clock ready interrupt caused by the LSE oscillator

1: Clock ready interrupt caused by the LSE oscillator

Bit 0 LSIRDYF: LSI ready interrupt flag

This bit is set by hardware when the internal low speed clock becomes stable and

LSIRDYDIE is set.

It is cleared by software by setting the LSIRDYC bit.

0: No clock ready interrupt caused by the LSI oscillator

1: Clock ready interrupt caused by the LSI oscillator

Address offset: 0x10

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

Res.

OTGHS

RST rw

Res.

CRC

RST rw

Res.

Res

Res.

GPIOH

RST rw

DMA2

RST rw

GPIOG

RST rw

DMA1

RST rw

GPIOF

RST rw

Res.

GPIOE

RST rw

Res.

GPIOD

RST rw

GPIOC

RST rw

GPIOB

RST rw

GPIOA

RST rw

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 OTGHSRST: USB OTG HS module reset

This bit is set and cleared by software.

0: does not reset the USB OTG HS module

1: resets the USB OTG HS module

Bits 28:23 Reserved, must be kept at reset value.

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RM0390 Rev 6

RM0390

Bit 22 DMA2RST: DMA2 reset

This bit is set and cleared by software.

0: does not reset DMA2

1: resets DMA2

Bit 21 DMA1RST: DMA2 reset

This bit is set and cleared by software.

0: does not reset DMA2

1: resets DMA2

Bits 20:13 Reserved, must be kept at reset value.

Bit 12 CRCRST: CRC reset

This bit is set and cleared by software.

0: does not reset CRC

1: resets CRC

Bits 11:8 Reserved, must be kept at reset value.

Bit 7 GPIOHRST: IO port H reset

This bit is set and cleared by software.

0: does not reset IO port H

1: resets IO port H

Bit 6 GPIOGRST: IO port G reset

This bit is set and cleared by software.

0: does not reset IO port G

1: resets IO port G

Bit 5 GPIOFRST: IO port F reset

This bit is set and cleared by software.

0: does not reset IO port F

1: resets IO port F

Bit 4 GPIOERST: IO port E reset

This bit is set and cleared by software.

0: does not reset IO port E

1: resets IO port E

Bit 3 GPIODRST: IO port D reset

This bit is set and cleared by software.

0: does not reset IO port D

1: resets IO port D

Bit 2 GPIOCRST: IO port C reset

This bit is set and cleared by software.

0: does not reset IO port C

1: resets IO port C

Bit 1 GPIOBRST: IO port B reset

This bit is set and cleared by software.

0: does not reset IO port B

1:resets IO port B

Bit 0 GPIOARST: IO port A reset

This bit is set and cleared by software.

0: does not reset IO port A

1: resets IO port A

RM0390 Rev 6

Reset and clock control (RCC)

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Reset and clock control (RCC) RM0390

Res.

Address offset: 0x14

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Res.

OTGFS

RST rw

Res.

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 OTGFSRST: USB OTG FS module reset

Set and cleared by software.

0: does not reset the USB OTG FS module

1: resets the USB OTG FS module

Bits 6:1 Reserved, must be kept at reset value.

Bit 0 DCMIRST: Camera interface reset

Set and cleared by software.

0: does not reset the Camera interface

1: resets the Camera interface

Res.

DCMI

RST rw

Res.

Address offset: 0x18

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

Res.

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 QSPIRST : QUADSPI module reset

Set and reset by software

0: does not reset QUADSPI module

1: resets QUADSPI module

Res.

2 1 0

Res.

QSPIRST FMCRST rw rw

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RM0390 Rev 6

RM0390 Reset and clock control (RCC)

Bit 0 FMCRST: Flexible memory controller module reset

Set and cleared by software.

0: does not reset the FMC module

1: resets the FMC module

6.3.8

Res.

SPI3

RST rw

RCC APB1 peripheral reset register (RCC_APB1RSTR)

Address offset: 0x20

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

Res.

SPI2

RST

DAC

RST rw

Res.

PWR

RST rw

Res.

27 26

CECRS

T rw

CAN2

RST

10 11

WWDG

RST rw

Res.

25 24

CAN1

RST rw

FMPI2C1

RST rw

Res.

TIM14

RST rw

I2C3

RST rw

TIM13

RST rw

I2C2

RST rw

TIM12

RST rw

I2C1

RST rw

TIM7

RST rw

20 19 18 17 16

UART5

RST

UART4

RST

UART3

RST

UART2

RST

SPDIFRX

RST rw rw rw rw rw

TIM6

RST rw

TIM5

RST rw

TIM4

RST rw

TIM3

RST rw

TIM2

RST rw

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 DACRST: DAC reset

Set and cleared by software.

0: does not reset the DAC interface

1: resets the DAC interface

Bit 28 PWRRST: Power interface reset

Set and cleared by software.

0: does not reset the power interface

1: resets the power interface

Bit 27 CECRST: CEC reset

Set and cleared by software.

0: does not reset CEC

1: resets CEC

Bit 26 CAN2RST: CAN2 reset

Set and cleared by software.

0: does not reset CAN2

1: resets CAN2

Bit 25 CAN1RST: CAN1 reset

Set and cleared by software.

0: does not reset CAN1

1: resets CAN1

Bit 24 IFMPI2C1RST: FMPI2C1 reset

Set and cleared by software

0: does not reset FMPI2C1

1: resets FMPI2C1

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Bit 23 I2C3RST: I2C3 reset

Set and cleared by software.

0: does not reset I2C3

1: resets I2C3

Bit 22 I2C2RST: I2C2 reset

Set and cleared by software.

0: does not reset I2C2

1: resets I2C2

Bit 21 I2C1RST: I2C1 reset

Set and cleared by software.

0: does not reset I2C1

1: resets I2C1

Bit 20 UART5RST: UART5 reset

Set and cleared by software.

0: does not reset UART5

1: resets UART5

Bit 19 UART4RST: USART4 reset

Set and cleared by software.

0: does not reset UART4

1: resets UART4

Bit 18 USART3RST: USART3 reset

Set and cleared by software.

0: does not reset USART3

1: resets USART3

Bit 17 USART2RST: USART2 reset

Set and cleared by software.

0: does not reset USART2

1: resets USART2

Bit 16 SPDIFRXRST: SPDIF-Rx reset

Set and cleared by software.

0: does not reset SPDIF-Rx

1: resets SPDIF-Rx

Bit 15 SPI3RST: SPI3 reset

Set and cleared by software.

0: does not reset SPI3

1: resets SPI3

Bit 14 SPI2RST: SPI2 reset

Set and cleared by software.

0: does not reset SPI2

1: resets SPI2

Bits 13:12 Reserved, must be kept at reset value.

Bit 11 WWDGRST: Window watchdog reset

Set and cleared by software.

0: does not reset the window watchdog

1: resets the window watchdog

Bits 10:9 Reserved, must be kept at reset value.

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Bit 8 TIM14RST: TIM14 reset

Set and cleared by software.

0: does not reset TIM14

1: resets TIM14

Bit 7 TIM13RST: TIM13 reset

Set and cleared by software.

0: does not reset TIM13

1: resets TIM13

Bit 6 TIM12RST: TIM12 reset

Set and cleared by software.

0: does not reset TIM12

1: resets TIM12

Bit 5 TIM7RST: TIM7 reset

Set and cleared by software.

0: does not reset TIM7

1: resets TIM7

Bit 4 TIM6RST: TIM6 reset

Set and cleared by software.

0: does not reset TIM6

1: resets TIM6

Bit 3 TIM5RST: TIM5 reset

Set and cleared by software.

0: does not reset TIM5

1: resets TIM5

Bit 2 TIM4RST: TIM4 reset

Set and cleared by software.

0: does not reset TIM4

1: resets TIM4

Bit 1 TIM3RST: TIM3 reset

Set and cleared by software.

0: does not reset TIM3

1: resets TIM3

Bit 0 TIM2RST: TIM2 reset

Set and cleared by software.

0: does not reset TIM2

1: resets TIM2

Reset and clock control (RCC)

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6.3.9 RCC APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x24

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

Res.

SYSCFG

RST rw

SPI4

RST rw

Res.

SPI1

RST rw

SDIO

RST rw

Res.

ADC

RST rw

SAI2

RST rw

Res

SAI1

RST rw

Res

Res.

USART6

RST rw

USART1

RST rw

Res.

TIM11

RST rw

Res.

TIM10

RST rw

TIM8

RST rw

TIM9

RST rw

TIM1

RST rw

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 SAI2RST : SAI2 reset

This bit is set and reset by software.

0: does not reset SAI2

1: resets SAI2

Bit 22 SAI1RST : SAI1 reset

This bit is set and reset by software.

0: does not reset SAI1

1: resets SAI1

Bits 21:19 Reserved, must be kept at reset value.

Bit 18 TIM11RST: TIM11 reset

This bit is set and cleared by software.

0: does not reset TIM11

1: resets TIM14

Bit 17 TIM10RST: TIM10 reset

This bit is set and cleared by software.

0: does not reset TIM10

1: resets TIM10

Bit 16 TIM9RST: TIM9 reset

This bit is set and cleared by software.

0: does not reset TIM9

1: resets TIM9

Bit 15 Reserved, must be kept at reset value.

Bit 14 SYSCFGRST: System configuration controller reset

This bit is set and cleared by software.

0: does not reset the System configuration controller

1: resets the System configuration controller

Bit 13 SPI4RST : SPI4 reset

This bit is set and cleared by software.

0: does not reset SPI4

1: resets SPI4

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Bit 12 SPI1RST: SPI1 reset

This bit is set and cleared by software.

0: does not reset SPI1

1: resets SPI1

Bit 11 SDIORST: SDIO reset

This bit is set and cleared by software.

0: does not reset the SDIO module

1: resets the SDIO module

Bits 10:9 Reserved, must be kept at reset value.

Bit 8 ADCRST: ADC interface reset (common to all ADCs)

This bit is set and cleared by software.

0: does not reset the ADC interface

1: resets the ADC interface

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 USART6RST: USART6 reset

This bit is set and cleared by software.

0: does not reset USART6

1: resets USART6

Bit 4 USART1RST: USART1 reset

This bit is set and cleared by software.

0: does not reset USART1

1: resets USART1

Bits 3:2 Reserved, must be kept at reset value.

Bit 1 TIM8RST: TIM8 reset

This bit is set and cleared by software.

0: does not reset TIM8

1: resets TIM8

Bit 0 TIM1RST: TIM1 reset

This bit is set and cleared by software.

0: does not reset TIM1

1: resets TIM1

Reset and clock control (RCC)

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6.3.10 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)

Address offset: 0x30

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

Res.

OTGHS

ULPIEN

OTGHS

EN rw

14 rw

Res.

CRC

EN rw

Res.

GPIOH

EN rw

DMA2

EN rw

GPIOG

EN rw

DMA1

EN rw

GPIOF

EN rw

Res.

GPIOE

EN rw

GPIOD

EN rw

BKP

SRAMEN rw

GPIOC

EN rw

Res.

GPIOB

EN rw

Res.

GPIOA

EN rw

Bit 31 Reserved, must be kept at reset value.

Bit 30 OTGHSULPIEN: USB OTG HSULPI clock enable

This bit is set and cleared by software.

0: USB OTG HS ULPI clock disabled

1: USB OTG HS ULPI clock enabled

Bit 29 OTGHSEN: USB OTG HS clock enable

This bit is set and cleared by software.

0: USB OTG HS clock disabled

1: USB OTG HS clock enabled

Bits 28:23 Reserved, must be kept at reset value.

Bit 22 DMA2EN: DMA2 clock enable

This bit is set and cleared by software.

0: DMA2 clock disabled

1: DMA2 clock enabled

Bit 21 DMA1EN: DMA1 clock enable

This bit is set and cleared by software.

0: DMA1 clock disabled

1: DMA1 clock enabled

Bits 20:19 Reserved, must be kept at reset value.

Bit 18 BKPSRAMEN: Backup SRAM interface clock enable

This bit is set and cleared by software.

0: Backup SRAM interface clock disabled

1: Backup SRAM interface clock enabled

Bits 17:13 Reserved, must be kept at reset value.

Bit 12 CRCEN: CRC clock enable

This bit is set and cleared by software.

0: CRC clock disabled

1: CRC clock enabled

Bits 11:8 Reserved, must be kept at reset value.

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RM0390 Reset and clock control (RCC)

Bit 7 GPIOHEN: IO port H clock enable

This bit is set and cleared by software.

0: IO port H clock disabled

1: IO port H clock enabled

Bit 6 GPIOGEN: IO port G clock enable

This bit is set and cleared by software.

0: IO port G clock disabled

1: IO port G clock enabled

Bit 5 GPIOFEN: IO port F clock enable

This bit is set and cleared by software.

0: IO port F clock disabled

1: IO port F clock enabled

Bit 4 GPIOEEN: IO port E clock enable

This bit is set and cleared by software.

0: IO port E clock disabled

1: IO port E clock enabled

Bit 3 GPIODEN: IO port D clock enable

This bit is set and cleared by software.

0: IO port D clock disabled

1: IO port D clock enabled

Bit 2 GPIOCEN: IO port C clock enable

This bit is set and cleared by software.

0: IO port C clock disabled

1: IO port C clock enabled

Bit 1 GPIOBEN: IO port B clock enable

This bit is set and cleared by software.

0: IO port B clock disabled

1: IO port B clock enabled

Bit 0 GPIOAEN: IO port A clock enable

This bit is set and cleared by software.

0: IO port A clock disabled

1: IO port A clock enabled

6.3.11 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)

Address offset: 0x34

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

31 30 29 28 27 26 25 24

Res.

19 18 17

Res.

15 14 13 12 11 10 9 8 7

Res.

OTGFSEN rw

Res.

3 2 1 0

Res.

DCMIEN rw

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Bits 31:8 Reserved, must be kept at reset value.

Bit 7 OTGFSEN: USB OTG FS clock enable

This bit is set and cleared by software.

0: USB OTG FS clock disabled

1: USB OTG FS clock enabled

Bits 6:1 Reserved, must be kept at reset value.

Bit 0 DCMIEN: Camera interface enable

This bit is set and cleared by software.

0: Camera interface clock disabled

1: Camera interface clock enabled

6.3.12 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR)

Address offset: 0x38

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

Res.

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 QSPIEN: QUADSPI memory controller module clock enable

This bit is set and cleared by software.

0: QUADSPI module clock disabled

1: QUADSPI module clock enabled

Bit 0 FMCEN: Flexible memory controller module clock enable

This bit is set and cleared by software.

0: FMC module clock disabled

1: FMC module clock enabled

Res.

2 1 0

Res.

QSPIEN FMCEN rw rw

6.3.13 RCC APB1 peripheral clock enable register (RCC_APB1ENR)

Address offset: 0x40

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

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RM0390 Reset and clock control (RCC)

Res.

SPI3

EN rw

Res.

SPI2

EN rw

DAC

EN rw

Res.

PWR

EN rw

Res.

CEC

EN rw

WWDG

EN rw

CAN2

EN rw

Res.

25 24

CAN1

EN rw

FMPI2C1

EN rw

Res.

TIM14

EN rw

I2C3

EN rw

TIM13

EN rw

I2C2

EN rw

TIM12

EN rw

I2C1

EN rw

TIM7

EN rw

UART5

EN rw

TIM6

EN rw

UART4

EN rw

TIM5

EN rw

USART3

EN rw

TIM4

EN rw

USART2

EN rw

TIM3

EN rw

SPDIFRX

EN rw

TIM2

EN rw

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 DACEN: DAC interface clock enable

This bit is set and cleared by software.

0: DAC interface clock disabled

1: DAC interface clock enable

Bit 28 PWREN: Power interface clock enable

This bit is set and cleared by software.

0: Power interface clock disabled

1: Power interface clock enable

Bit 27 CECEN: CEC interface clock enable

This bit is set and cleared by software.

0: CEC interface clock disabled

1: CEC interface clock enabled

Bit 26 CAN2EN: CAN 2 clock enable

This bit is set and cleared by software.

0: CAN 2 clock disabled

1: CAN 2 clock enabled

Bit 25 CAN1EN: CAN 1 clock enable

This bit is set and cleared by software.

0: CAN 1 clock disabled

1: CAN 1 clock enabled

Bit 24 FMPI2C1EN: FMPI2C1 clock enable

This bit is set and cleared by software.

0: FMPI2C1 clock disabled

1: FMPI2C1 clock enabled

Bit 23 I2C3EN: I2C3 clock enable

This bit is set and cleared by software.

0: I2C3 clock disabled

1: I2C3 clock enabled

Bit 22 I2C2EN: I2C2 clock enable

This bit is set and cleared by software.

0: I2C2 clock disabled

1: I2C2 clock enabled

Bit 21 I2C1EN: I2C1 clock enable

This bit is set and cleared by software.

0: I2C1 clock disabled

1: I2C1 clock enabled

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Reset and clock control (RCC)

Bit 20 UART5EN: UART5 clock enable

This bit is set and cleared by software.

0: UART5 clock disabled

1: UART5 clock enabled

Bit 19 UART4EN: UART4 clock enable

This bit is set and cleared by software.

0: UART4 clock disabled

1: UART4 clock enabled

Bit 18 USART3EN: USART3 clock enable

This bit is set and cleared by software.

0: USART3 clock disabled

1: USART3 clock enabled

Bit 17 USART2EN: USART2 clock enable

This bit is set and cleared by software.

0: USART2 clock disabled

1: USART2 clock enabled

Bit 16 SPDIFRXEN: SPDIF-Rx clock enable

This bit is set and cleared by software.

0: SPDIF-Rx clock disabled

1: SPDIF-Rx clock enabled

Bit 15 SPI3EN: SPI3 clock enable

This bit is set and cleared by software.

0: SPI3 clock disabled

1: SPI3 clock enabled

Bit 14 SPI2EN: SPI2 clock enable

This bit is set and cleared by software.

0: SPI2 clock disabled

1: SPI2 clock enabled

Bits 13:12 Reserved, must be kept at reset value.

Bit 11 WWDGEN: Window watchdog clock enable

This bit is set and cleared by software.

0: Window watchdog clock disabled

1: Window watchdog clock enabled

Bits 10:9 Reserved, must be kept at reset value.

Bit 8 TIM14EN: TIM14 clock enable

This bit is set and cleared by software.

0: TIM14 clock disabled

1: TIM14 clock enabled

Bit 7 TIM13EN: TIM13 clock enable

This bit is set and cleared by software.

0: TIM13 clock disabled

1: TIM13 clock enabled

Bit 6 TIM12EN: TIM12 clock enable

This bit is set and cleared by software.

0: TIM12 clock disabled

1: TIM12 clock enabled

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RM0390

RM0390 Reset and clock control (RCC)

Bit 5 TIM7EN: TIM7 clock enable

This bit is set and cleared by software.

0: TIM7 clock disabled

1: TIM7 clock enabled

Bit 4 TIM6EN: TIM6 clock enable

This bit is set and cleared by software.

0: TIM6 clock disabled

1: TIM6 clock enabled

Bit 3 TIM5EN: TIM5 clock enable

This bit is set and cleared by software.

0: TIM5 clock disabled

1: TIM5 clock enabled

Bit 2 TIM4EN: TIM4 clock enable

This bit is set and cleared by software.

0: TIM4 clock disabled

1: TIM4 clock enabled

Bit 1 TIM3EN: TIM3 clock enable

This bit is set and cleared by software.

0: TIM3 clock disabled

1: TIM3 clock enabled

Bit 0 TIM2EN: TIM2 clock enable

This bit is set and cleared by software.

0: TIM2 clock disabled

1: TIM2 clock enabled

6.3.14 RCC APB2 peripheral clock enable register (RCC_APB2ENR)

Address offset: 0x44

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

Res.

SYSCFG

EN rw

SPI4

EN rw

Res.

SPI1

EN rw

Res.

SDIO

EN rw

ADC3

EN rw

ADC2

EN rw

ADC1

EN rw

SAI2

EN rw

Res.

SAI1

EN rw

Res.

USART6

EN rw

USART1

EN rw

Res.

TIM11

EN rw

Res.

TIM10

EN rw

TIM8

EN rw

TIM9

EN rw

TIM1

EN rw

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Reset and clock control (RCC)

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 SAI2EN: SAI2 clock enable

This bit is set and cleared by software.

0: SAI2 clock disabled

1: SAI2 clock enabled

Bit 22 SAI1EN: SAI1 clock enable

This bit is set and cleared by software.

0: SAI1 clock disabled

1: SAI1 clock enabled

Bits 21:19 Reserved, must be kept at reset value.

Bit 18 TIM11EN: TIM11 clock enable

This bit is set and cleared by software.

0: TIM11 clock disabled

1: TIM11 clock enabled

Bit 17 TIM10EN: TIM10 clock enable

This bit is set and cleared by software.

0: TIM10 clock disabled

1: TIM10 clock enabled

Bit 16 TIM9EN: TIM9 clock enable

This bit is set and cleared by software.

0: TIM9 clock disabled

1: TIM9 clock enabled

Bit 15 Reserved, must be kept at reset value.

Bit 14 SYSCFGEN: System configuration controller clock enable

This bit is set and cleared by software.

0: System configuration controller clock disabled

1: System configuration controller clock enabled

Bit 13 SPI4EN: SPI4 clock enable

This bit is set and cleared by software.

0: SPI4 clock disabled

1: SPI4 clock enabled

Bit 12 SPI1EN: SPI1 clock enable

This bit is set and cleared by software.

0: SPI1 clock disabled

1: SPI1 clock enabled

Bit 11 SDIOEN: SDIO clock enable

This bit is set and cleared by software.

0: SDIO module clock disabled

1: SDIO module clock enabled

Bit 10 ADC3EN: ADC3 clock enable

This bit is set and cleared by software.

0: ADC3 clock disabled

1: ADC3 clock enabled

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RM0390

RM0390 Reset and clock control (RCC)

Bit 9 ADC2EN: ADC2 clock enable

This bit is set and cleared by software.

0: ADC2 clock disabled

1: ADC2 clock enabled

Bit 8 ADC1EN: ADC1 clock enable

This bit is set and cleared by software.

0: ADC1 clock disabled

1: ADC1 clock enabled

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 USART6EN: USART6 clock enable

This bit is set and cleared by software.

0: USART6 clock disabled

1: USART6 clock enabled

Bit 4 USART1EN: USART1 clock enable

This bit is set and cleared by software.

0: USART1 clock disabled

1: USART1 clock enabled

Bits 3:2 Reserved, must be kept at reset value.

Bit 1 TIM8EN: TIM8 clock enable

This bit is set and cleared by software.

0: TIM8 clock disabled

1: TIM8 clock enabled

Bit 0 TIM1EN: TIM1 clock enable

This bit is set and cleared by software.

0: TIM1 clock disabled

1: TIM1 clock enabled

6.3.15 RCC AHB1 peripheral clock enable in low power mode register

(RCC_AHB1LPENR)

Address offset: 0x50

Reset value: 0x6067 90FF

Access: no wait state, word, half-word and byte access.

Res.

FLITF

LPEN rw

OTGHS

ULPI

LPEN rw

OTGHS

LPEN rw

Res.

CRC

LPEN rw

Res.

DMA2

LPEN

DMA1

LPEN

GPIOH

LPEN rw rw

6 rw

GPIOG

LPEN rw

GPIOF

LPEN rw

Res.

GPIOE

LPEN rw

GPIOD

LPEN rw

BKP

SRAM

LPEN rw

GPIOC

LPEN rw

SRAM2

LPEN

SRAM1

LPEN rw

GPIOB

LPEN rw

16 rw

GPIOA

LPEN rw

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Reset and clock control (RCC)

Bit 31 Reserved, must be kept at reset value.

Bit 30 OTGHSULPILPEN: USB OTG HS ULPI clock enable during Sleep mode

This bit is set and cleared by software.

0: USB OTG HS ULPI clock disabled during Sleep mode

1: USB OTG HS ULPI clock enabled during Sleep mode

Bit 29 OTGHSLPEN: USB OTG HS clock enable during Sleep mode

This bit is set and cleared by software.

0: USB OTG HS clock disabled during Sleep mode

1: USB OTG HS clock enabled during Sleep mode

Bits 28:23 Reserved, must be kept at reset value.

Bit 22 DMA2LPEN: DMA2 clock enable during Sleep mode

This bit is set and cleared by software.

0: DMA2 clock disabled during Sleep mode

1: DMA2 clock enabled during Sleep mode

Bit 21 DMA1LPEN: DMA1 clock enable during Sleep mode

This bit is set and cleared by software.

0: DMA1 clock disabled during Sleep mode

1: DMA1 clock enabled during Sleep mode

Bits 20:19 Reserved, must be kept at reset value.

Bit 18 BKPSRAMLPEN: Backup SRAM interface clock enable during Sleep mode

This bit is set and cleared by software.

0: Backup SRAM interface clock disabled during Sleep mode

1: Backup SRAM interface clock enabled during Sleep mode

Bit 17 SRAM2LPEN: SRAM2 interface clock enable during Sleep mode

This bit is set and cleared by software.

0: SRAM2 interface clock disabled during Sleep mode

1: SRAM2 interface clock enabled during Sleep mode

Bit 16 SRAM1LPEN: SRAM1 interface clock enable during Sleep mode

This bit is set and cleared by software.

0: SRAM1 interface clock disabled during Sleep mode

1: SRAM1 interface clock enabled during Sleep mode

Bit 15 FLITFLPEN: Flash interface clock enable during Sleep mode

This bit is set and cleared by software.

0: Flash interface clock disabled during Sleep mode

1: Flash interface clock enabled during Sleep mode

Bits 14:13 Reserved, must be kept at reset value.

Bit 12 CRCLPEN: CRC clock enable during Sleep mode

This bit is set and cleared by software.

0: CRC clock disabled during Sleep mode

1: CRC clock enabled during Sleep mode

Bits 11:8 Reserved, must be kept at reset value.

Bit 7 GPIOHLPEN: IO port H clock enable during Sleep mode

This bit is set and cleared by software.

0: IO port H clock disabled during Sleep mode

1: IO port H clock enabled during Sleep mode

RM0390

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RM0390 Reset and clock control (RCC)

Bit 6 GPIOGLPEN: IO port G clock enable during Sleep mode

This bit is set and cleared by software.

0: IO port G clock disabled during Sleep mode

1: IO port G clock enabled during Sleep mode

Bit 5 GPIOFLPEN: IO port F clock enable during Sleep mode

This bit is set and cleared by software.

0: IO port F clock disabled during Sleep mode

1: IO port F clock enabled during Sleep mode

Bit 4 GPIOELPEN: IO port E clock enable during Sleep mode

Set and cleared by software.

0: IO port E clock disabled during Sleep mode

1: IO port E clock enabled during Sleep mode

Bit 3 GPIODLPEN: IO port D clock enable during Sleep mode

This bit is set and cleared by software.

0: IO port D clock disabled during Sleep mode

1: IO port D clock enabled during Sleep mode

Bit 2 GPIOCLPEN: IO port C clock enable during Sleep mode

This bit is set and cleared by software.

0: IO port C clock disabled during Sleep mode

1: IO port C clock enabled during Sleep mode

Bit 1 GPIOBLPEN: IO port B clock enable during Sleep mode

This bit is set and cleared by software.

0: IO port B clock disabled during Sleep mode

1: IO port B clock enabled during Sleep mode

Bit 0 GPIOALPEN: IO port A clock enable during sleep mode

This bit is set and cleared by software.

0: IO port A clock disabled during Sleep mode

1: IO port A clock enabled during Sleep mode

6.3.16 RCC AHB2 peripheral clock enable in low power mode register

(RCC_AHB2LPENR)

Address offset: 0x54

Reset value: 0x0000 0081

Access: no wait state, word, half-word and byte access.

Res.

OTGFS

LPEN rw

Res.

DCMI

LPEN rw

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Bits 31:8 Reserved, must be kept at reset value.

Bit 7 OTGFSLPEN: USB OTG FS clock enable during Sleep mode

This bit is set and cleared by software.

0: USB OTG FS clock disabled during Sleep mode

1: USB OTG FS clock enabled during Sleep mode

Bits 6:1 Reserved, must be kept at reset value.

Bit 0 DCMILPEN: Camera interface enable during Sleep mode

This bit is set and cleared by software.

0: Camera interface clock disabled during Sleep mode

1: Camera interface clock enabled during Sleep mode

6.3.17 RCC AHB3 peripheral clock enable in low power mode register

(RCC_AHB3LPENR)

Address offset: 0x58

Reset value: 0x0000 0003

Access: no wait state, word, half-word and byte access.

Res.

QSPI

LPEN rw

FMC

LPEN rw

Bits 31:2Reserved, must be kept at reset value.

Bit 1 QSPILPEN: QUADSPI memory controller module clock enable during Sleep mode

This bit is set and cleared by software.

0: QUADSPI module clock disabled during Sleep mode

1: QUADSPI module clock enabled during Sleep mode

Bit 0 FMCLPEN: Flexible memory controller module clock enable during Sleep mode

This bit is set and cleared by software.

0: FMC module clock disabled during Sleep mode

1: FMC module clock enabled during Sleep mode

6.3.18 RCC APB1 peripheral clock enable in low power mode register

(RCC_APB1LPENR)

Address offset: 0x60

Reset value: 0x3FFF C9FF

Access: no wait state, word, half-word and byte access.

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RM0390 Reset and clock control (RCC)

Res.

SPI3

LPEN rw

Res.

SPI2

LPEN rw

DAC

LPEN rw

Res.

PWR

LPEN rw

Res.

CECLP

EN rw

WWDG

LPEN rw

CAN2

LPEN rw

Res.

CAN1

LPEN rw

Res.

FMPI2C1

LPEN rw

TIM14

LPEN rw

I2C3

LPEN rw

TIM13

LPEN rw

I2C2

LPEN rw

TIM12

LPEN rw

I2C1

LPEN rw

TIM7

LPEN rw

UART5

LPEN rw

TIM6

LPEN rw

UART4

LPEN rw

TIM5

LPEN rw

USART3

LPEN rw

USART2

LPEN rw

TIM4

LPEN rw

TIM3

LPEN rw

SPDIFRX

LPEN rw

TIM2

LPEN rw

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 DACLPEN: DAC interface clock enable during Sleep mode

This bit is set and cleared by software.

0: DAC interface clock disabled during Sleep mode

1: DAC interface clock enabled during Sleep mode

Bit 28 PWRLPEN: Power interface clock enable during Sleep mode

This bit is set and cleared by software.

0: Power interface clock disabled during Sleep mode

1: Power interface clock enabled during Sleep mode

Bit 27 CECLPEN: CEC clock enable during Sleep mode

This bit is set and cleared by software.

0: CEC clock disabled during Sleep mode

1: CEC clock enabled during Sleep mode

Bit 26 CAN2LPEN: CAN 2 clock enable during Sleep mode

This bit is set and cleared by software.

0: CAN 2 clock disabled during sleep mode

1: CAN 2 clock enabled during sleep mode

Bit 25 CAN1LPEN: CAN 1 clock enable during Sleep mode

This bit is set and cleared by software.

0: CAN 1 clock disabled during Sleep mode

1: CAN 1 clock enabled during Sleep mode

Bit 24 FMPI2C1LPEN: FMPI2C1 clock enable during Sleep mode

This bit is set and cleared by software.

0: FMPI2C1 clock disabled during Sleep mode

1: FMPI2C1 clock enabled during Sleep mode

Bit 23 I2C3LPEN: I2C3 clock enable during Sleep mode

This bit is set and cleared by software.

0: I2C3 clock disabled during Sleep mode

1: I2C3 clock enabled during Sleep mode

Bit 22 I2C2LPEN: I2C2 clock enable during Sleep mode

This bit is set and cleared by software.

0: I2C2 clock disabled during Sleep mode

1: I2C2 clock enabled during Sleep mode

Bit 21 I2C1LPEN: I2C1 clock enable during Sleep mode

This bit is set and cleared by software.

0: I2C1 clock disabled during Sleep mode

1: I2C1 clock enabled during Sleep mode

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Reset and clock control (RCC)

Bit 20 UART5LPEN: UART5 clock enable during Sleep mode

This bit is set and cleared by software.

0: UART5 clock disabled during Sleep mode

1: UART5 clock enabled during Sleep mode

Bit 19 UART4LPEN: UART4 clock enable during Sleep mode

This bit is set and cleared by software.

0: UART4 clock disabled during Sleep mode

1: UART4 clock enabled during Sleep mode

Bit 18 USART3LPEN: USART3 clock enable during Sleep mode

This bit is set and cleared by software.

0: USART3 clock disabled during Sleep mode

1: USART3 clock enabled during Sleep mode

Bit 17 USART2LPEN: USART2 clock enable during Sleep mode

This bit is set and cleared by software.

0: USART2 clock disabled during Sleep mode

1: USART2 clock enabled during Sleep mode

Bit 16 SPDIFLPEN: SPDIF-Rx clock enable during Sleep mode

This bit is set and cleared by software.

0: SPDIF-Rx clock disabled during Sleep mode

1: SPDIF-Rx clock enabled during Sleep mode

Bit 15 SPI3LPEN: SPI3 clock enable during Sleep mode

This bit is set and cleared by software.

0: SPI3 clock disabled during Sleep mode

1: SPI3 clock enabled during Sleep mode

Bit 14 SPI2LPEN: SPI2 clock enable during Sleep mode

This bit is set and cleared by software.

0: SPI2 clock disabled during Sleep mode

1: SPI2 clock enabled during Sleep mode

Bits 13:12 Reserved, must be kept at reset value.

Bit 11 WWDGLPEN: Window watchdog clock enable during Sleep mode

This bit is set and cleared by software.

0: Window watchdog clock disabled during sleep mode

1: Window watchdog clock enabled during sleep mode

Bits 10:9 Reserved, must be kept at reset value.

Bit 8 TIM14LPEN: TIM14 clock enable during Sleep mode

This bit is set and cleared by software.

0: TIM14 clock disabled during Sleep mode

1: TIM14 clock enabled during Sleep mode

Bit 7 TIM13LPEN: TIM13 clock enable during Sleep mode

This bit is set and cleared by software.

0: TIM13 clock disabled during Sleep mode

1: TIM13 clock enabled during Sleep mode

Bit 6 TIM12LPEN: TIM12 clock enable during Sleep mode

This bit is set and cleared by software.

0: TIM12 clock disabled during Sleep mode

1: TIM12 clock enabled during Sleep mode

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Bit 5 TIM7LPEN: TIM7 clock enable during Sleep mode

This bit is set and cleared by software.

0: TIM7 clock disabled during Sleep mode

1: TIM7 clock enabled during Sleep mode

Bit 4 TIM6LPEN: TIM6 clock enable during Sleep mode

This bit is set and cleared by software.

0: TIM6 clock disabled during Sleep mode

1: TIM6 clock enabled during Sleep mode

Bit 3 TIM5LPEN: TIM5 clock enable during Sleep mode

This bit is set and cleared by software.

0: TIM5 clock disabled during Sleep mode

1: TIM5 clock enabled during Sleep mode

Bit 2 TIM4LPEN: TIM4 clock enable during Sleep mode

This bit is set and cleared by software.

0: TIM4 clock disabled during Sleep mode

1: TIM4 clock enabled during Sleep mode

Bit 1 TIM3LPEN: TIM3 clock enable during Sleep mode

This bit is set and cleared by software.

0: TIM3 clock disabled during Sleep mode

1: TIM3 clock enabled during Sleep mode

Bit 0 TIM2LPEN: TIM2 clock enable during Sleep mode

This bit is set and cleared by software.

0: TIM2 clock disabled during Sleep mode

1: TIM2 clock enabled during Sleep mode

Reset and clock control (RCC)

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6.3.19 RCC APB2 peripheral clock enabled in low power mode register

(RCC_APB2LPENR)

Address offset: 0x64

Reset value: 0x0x00C7 7F33

Access: no wait state, word, half-word and byte access.

Res.

SYSCFG

LPEN rw

SPI4

LPEN rw

SPI1

LPEN rw

SDIO

LPEN rw

Res.

ADC3

LPEN rw

ADC2

LPEN rw

Res.

ADC1

LPEN rw

SAI2

LPEN rw

Res.

SAI1

LPEN rw

Res.

USART6

LPEN rw

USART1

LPEN rw

Res.

TIM11

LPEN rw

Res.

TIM10

LPEN rw

TIM8

LPEN rw

TIM9

LPEN rw

TIM1

LPEN rw

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 SAI2LPEN: SAI2 clock enable during Sleep mode

This bit is set and cleared by software.

0: SAI2 clock disabled during Sleep mode

1: SAI2 clock enabled during Sleep mode

Bit 22 SAI1LPEN: SAI1 clock enable during Sleep mode

This bit is set and cleared by software.

0: SAI1 clock disabled during Sleep mode

1: SAI1 clock enabled during Sleep mode

Bits 21:19 Reserved, must be kept at reset value.

Bit 18 TIM11LPEN: TIM11 clock enable during Sleep mode

This bit is set and cleared by software.

0: TIM11 clock disabled during Sleep mode

1: TIM11 clock enabled during Sleep mode

Bit 17 TIM10LPEN: TIM10 clock enable during Sleep mode

This bit is set and cleared by software.

0: TIM10 clock disabled during Sleep mode

1: TIM10 clock enabled during Sleep mode

Bit 16 TIM9LPEN: TIM9 clock enable during sleep mode

This bit is set and cleared by software.

0: TIM9 clock disabled during Sleep mode

1: TIM9 clock enabled during Sleep mode

Bit 15 Reserved, must be kept at reset value.

Bit 14 SYSCFGLPEN: System configuration controller clock enable during Sleep mode

This bit is set and cleared by software.

0: System configuration controller clock disabled during Sleep mode

1: System configuration controller clock enabled during Sleep mode

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Bit 13 SPI4LPEN: SPI4 clock enable during Sleep mode

This bit is set and cleared by software.

0: SPI4 clock disabled during Sleep mode

1: SPI4 clock enabled during Sleep mode

Bit 12 SPI1LPEN: SPI1 clock enable during Sleep mode

This bit is set and cleared by software.

0: SPI1 clock disabled during Sleep mode

1: SPI1 clock enabled during Sleep mode

Bit 11 SDIOLPEN: SDIO clock enable during Sleep mode

This bit is set and cleared by software.

0: SDIO module clock disabled during Sleep mode

1: SDIO module clock enabled during Sleep mode

Bit 10 ADC3LPEN: ADC 3 clock enable during Sleep mode

This bit is set and cleared by software.

0: ADC 3 clock disabled during Sleep mode

1: ADC 3 clock disabled during Sleep mode

Bit 9 ADC2LPEN: ADC2 clock enable during Sleep mode

This bit is set and cleared by software.

0: ADC2 clock disabled during Sleep mode

1: ADC2 clock disabled during Sleep mode

Bit 8 ADC1LPEN: ADC1 clock enable during Sleep mode

This bit is set and cleared by software.

0: ADC1 clock disabled during Sleep mode

1: ADC1 clock disabled during Sleep mode

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 USART6LPEN: USART6 clock enable during Sleep mode

This bit is set and cleared by software.

0: USART6 clock disabled during Sleep mode

1: USART6 clock enabled during Sleep mode

Bit 4 USART1LPEN: USART1 clock enable during Sleep mode

This bit is set and cleared by software.

0: USART1 clock disabled during Sleep mode

1: USART1 clock enabled during Sleep mode

Bits 3:2 Reserved, must be kept at reset value.

Bit 1 TIM8LPEN: TIM8 clock enable during Sleep mode

This bit is set and cleared by software.

0: TIM8 clock disabled during Sleep mode

1: TIM8 clock enabled during Sleep mode

Bit 0 TIM1LPEN: TIM1 clock enable during Sleep mode

This bit is set and cleared by software.

0: TIM1 clock disabled during Sleep mode

1: TIM1 clock enabled during Sleep mode

Reset and clock control (RCC)

Address offset: 0x70

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Reset value: 0x0000 0000, reset by Backup domain reset.

Access: 0 ≤ wait state ≤ 3, word, half-word and byte access

Wait states are inserted in case of successive accesses to this register.

The LSEON, LSEBYP, RTCSEL and RTCEN bits in the RCC Backup domain control register (RCC_BDCR)

are in the Backup domain. As a result, after Reset, these bits are

write-protected and the DBP bit in the PWR power control register (PWR_CR) has to be set

before these can be modified. Refer to

Section 6.1.1: System reset on page 116 for further

information. These bits are only reset after a Backup domain Reset (see Section 6.1.3:

Backup domain reset ). Any internal or external Reset will not have any effect on these bits.

Res.

15 14

RTCEN Res.

Res.

9 8

RTCSEL[1:0] rw rw

Res.

BDRST rw

4 3 2 1 0

Res.

LSEMOD LSEBYP LSERDY LSEON rw rw r rw

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 BDRST: Backup domain software reset

This bit is set and cleared by software.

0: Reset not activated

1: Resets the entire Backup domain

Note: The BKPSRAM is not affected by this reset, the only way of resetting the BKPSRAM is through the Flash interface when a protection level change from level 1 to level 0 is requested.

Bit 15 RTCEN: RTC clock enable

This bit is set and cleared by software.

0: RTC clock disabled

1: RTC clock enabled

Bits 14:10 Reserved, must be kept at reset value.

Bits 9:8 RTCSEL[1:0]: RTC clock source selection

These bits are set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit can be used to reset them.

00: No clock

01: LSE oscillator clock used as the RTC clock

10: LSI oscillator clock used as the RTC clock

11: HSE oscillator clock divided by a programmable prescaler (selection through the

RTCPRE[4:0] bits in the RCC clock configuration register (RCC_CFGR)) used as the RTC clock

Bits 7:4 Reserved, must be kept at reset value.

Bit 3 LSEMOD: External low-speed oscillator mode

This bit is set and cleared by software to select the low speed oscillator crystal mode. Two power modes are available. This bit can be written only when the LSE clock is disabled.

0: LSE oscillator "low power" mode selection

1: LSE oscillator "high drive" mode selection

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Bit 2 LSEBYP: External low-speed oscillator bypass

This bit is set and cleared by software to bypass the oscillator. This bit can be written only when the LSE clock is disabled.

0: LSE oscillator not bypassed

1: LSE oscillator bypassed

Bit 1 LSERDY: External low-speed oscillator ready

This bit is set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles.

0: LSE clock not ready

1: LSE clock ready

Bit 0 LSEON: External low-speed oscillator enable

This bit is set and cleared by software.

0: LSE clock OFF

1: LSE clock ON

6.3.21 RCC clock control & status register (RCC_CSR)

Address offset: 0x74

Reset value: 0x0E00 0000, reset by system reset, except reset flags by power reset only.

Access: 0 ≤ wait state ≤ 3, word, half-word and byte access

Wait states are inserted in case of successive accesses to this register.

LPWR

RSTF rw

Res.

WWDG

RSTF

IWDG

RSTF rw

Res.

SFT

RSTF rw

Res.

POR

RSTF rw

Res.

RSTF rw

Res.

BOR

RSTF rw

Res.

24 23

RMVF Res.

Res.

2 1 0

Res.

LSIRDY LSION r rw

Bit 31 LPWRRSTF: Low-power reset flag

This bit is set by hardware when a Low-power management reset occurs.

Cleared by writing to the RMVF bit.

0: No Low-power management reset occurred

1: Low-power management reset occurred

For further information on Low-power management reset, refer to Low-power management reset .

Bit 30 WWDGRSTF: Window watchdog reset flag

This bit is set by hardware when a window watchdog reset occurs.

Cleared by writing to the RMVF bit.

0: No window watchdog reset occurred

1: Window watchdog reset occurred

Bit 29 IWDGRSTF: Independent watchdog reset flag

This bit is set by hardware when an independent watchdog reset from V

Cleared by writing to the RMVF bit.

domain occurs.

0: No watchdog reset occurred

1: Watchdog reset occurred

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Bit 28 SFTRSTF: Software reset flag

This bit is set by hardware when a software reset occurs.

Cleared by writing to the RMVF bit.

0: No software reset occurred

1: Software reset occurred

Bit 27 PORRSTF: POR/PDR reset flag

This bit is set by hardware when a POR/PDR reset occurs.

Cleared by writing to the RMVF bit.

0: No POR/PDR reset occurred

1: POR/PDR reset occurred

Bit 26 PINRSTF: PIN reset flag

This bit is set by hardware when a reset from the NRST pin occurs.

Cleared by writing to the RMVF bit.

0: No reset from NRST pin occurred

1: Reset from NRST pin occurred

Bit 25 BORRSTF: BOR reset flag

Cleared by software by writing the RMVF bit.

This bit is set by hardware when a POR/PDR or BOR reset occurs.

0: No POR/PDR or BOR reset occurred

1: POR/PDR or BOR reset occurred

Bit 24 RMVF: Remove reset flag

This bit is set by software to clear the reset flags.

0: No effect

1: Clear the reset flags

Bits 23:2 Reserved, must be kept at reset value.

Bit 1 LSIRDY: Internal low-speed oscillator ready

This bit is set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after 3 LSI clock cycles.

0: LSI RC oscillator not ready

1: LSI RC oscillator ready

Bit 0 LSION: Internal low-speed oscillator enable

This bit is set and cleared by software.

0: LSI RC oscillator OFF

1: LSI RC oscillator ON

6.3.22 RCC spread spectrum clock generation register (RCC_SSCGR)

Note:

Address offset: 0x80

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

The spread spectrum clock generation is available only for the main PLL.

The RCC_SSCGR register must be written either before the main PLL is enabled or after the main PLL disabled.

For full details about PLL spread spectrum clock generation (SSCG) characteristics, refer to the “Electrical characteristics” section in your device datasheet.

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31 30

INCSTEP

SSCGEN SPREADSEL Res.

rw rw

15 13 rw rw rw

Res.

12 rw

27 rw

11 rw

26 rw

10 rw

25 rw

9 rw

8 rw

23 rw

7 rw

MODPER

INCSTEP rw rw

5 rw rw

20 rw

4 rw

19 rw

3 rw

18 rw

2 rw

17 rw

1 rw

Bit 31 SSCGEN: Spread spectrum modulation enable

This bit is set and cleared by software.

0: Spread spectrum modulation DISABLE. (To write after clearing CR[24]=PLLON bit)

1: Spread spectrum modulation ENABLE. (To write before setting CR[24]=PLLON bit)

Bit 30 SPREADSEL: Spread Select

This bit is set and cleared by software.

To write before to set CR[24]=PLLON bit.

0: Center spread

1: Down spread

Bits 29:28 Reserved, must be kept at reset value.

Bits 27:13 INCSTEP: Incrementation step

These bits are set and cleared by software. To write before setting CR[24]=PLLON bit.

Configuration input for modulation profile amplitude.

Bits 12:0 MODPER: Modulation period

These bits are set and cleared by software. To write before setting CR[24]=PLLON bit.

Configuration input for modulation profile period.

16 rw

0 rw

Res.

Address offset: 0x84

Reset value: 0x2400 3010

Access: no wait state, word, half-word and byte access.

This register is used to configure the PLLI2S clock outputs according to the formulas: f

(VCO clock)

= f

(PLLI2S clock input)

× (PLLI2SN / PLLI2SM) f

(PLL I2S clock output)

= f

(VCO clock)

/ PLLI2SR f

(PLL SPDIFRX clock output)

= f

(VCO clock)

/ PLLI2SP

30 29

PLLI2SR[2:0]

28 rw

14 rw

13 rw

12 rw rw

27 rw

26 25

PLLI2SQ[3:0] rw

10 rw

9 rw

PLLI2SN[8:0] rw rw

24 rw

8 rw

Res.

7 rw

Res.

6 rw

Res.

5 rw

Res.

4 rw

Res.

3 2

PLLI2SM[5:0] rw rw

17 16

PLLI2SP[1:0] rw

1 rw

0 rw rw

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Bit 31 Reserved, must be kept at reset value.

Bits 30:28 PLLI2SR[2:0]: PLLI2S division factor for I2S clocks

These bits are set and cleared by software to control the I2S clock frequency. These bits should be written only if the PLLI2S is disabled. The factor must be chosen in accordance with the prescaler values inside the I2S peripherals, to reach 0.3% error when using standard crystals and 0% error with audio crystals. For more information about I2S clock

frequency and precision, refer to Section 26.6.4: Clock generator in the I2S chapter.

Caution: The I2Ss requires a frequency lower than or equal to 192 MHz to work correctly.

I2S clock frequency = VCO frequency / PLLR with 2 ≤ PLLR ≤ 7

000: PLLR = 0, wrong configuration

001: PLLR = 1, wrong configuration

010: PLLR = 2

...

111: PLLR = 7

Bits 27:24 PLLI2SQ[3:0] : PLLI2S division factor for SAI1 clock

These bits are set and cleared by software to control the SAI1 clock frequency.

They should be written when the PLLI2S is disabled.

SAI1 clock frequency = VCO frequency / PLLI2SQ with 2 ≤ PLLI2SIQ ≤ 15

0000: PLLI2SQ = 0, wrong configuration

0001: PLLI2SQ = 1, wrong configuration

0010: PLLI2SQ = 2

0011: PLLI2SQ = 3

0100: PLLI2SQ = 4

0101: PLLI2SQ = 5

...

1111: PLLI2SQ = 15

Bits 23:18 Reserved, must be kept at reset value.

Bits 17:16 PLLI2SP[1:0]: PLLI2S division factor for SPDIF-Rx clock

These bits are set and cleared by software to control the SPDIF-Rx clock frequency.

They should be written when the PLLI2S is disabled.

Caution: The software has to set these bits correctly to ensure that the output frequency doesn’t exceed 120 MHz on this output.

PLL output clock frequency = VCO frequency / PLLI2SP with PLLI2SIP = 2, 4, 6 or 8

00: PLLI2SP =2

01: PLLI2SP = 4

10: PLLI2SP = 6

11: PLLI2SP = 8

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Bit 15 Reserved, must be kept at reset value.

Bits 14:6 PLLI2SN[8:0]: PLLI2S multiplication factor for VCO

These bits are set and cleared by software to control the multiplication factor of the VCO.

These bits can be written only when the PLLI2S is disabled. Only half-word and word accesses are allowed to write these bits.

Caution: The software has to set these bits correctly to ensure that the VCO output frequency is between 100 and 432 MHz.

VCO output frequency = VCO input frequency × PLLI2SN with 50 ≤ PLLI2SN ≤ 432

000000000: PLLI2SN = 0, wrong configuration

000000001: PLLI2SN = 1, wrong configuration ...

001100010: PLLI2SN = 50

...

001100011: PLLI2SN = 99

001100100: PLLI2SN = 100

001100101: PLLI2SN = 101

001100110: PLLI2SN = 102

...

110110000: PLLI2SN = 432

110110000: PLLI2SN = 433, wrong configuration ...

111111111: PLLI2SN = 511, wrong configuration

Note: Between 50 and 99 multiplication factors are possible for VCO input frequency higher than 1 MHz. However care must be taken to fulfill the minimum VCO output frequency as specified above.

Bits 5:0 PLLI2SM[5:0]: Division factor for audio PLL (PLLI2S) input clock

Set and cleared by software to divide PLLI2S input clock before the VCO.

These bits can be written only when PLLI2S is disabled.

Caution: The software has to set these bits correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.

VCO input frequency = PLL input clock frequency / PLLI2S with 2 ≤ PLLI2SM ≤ 63

000000: PLLI2SM = 0, wrong configuration

000001: PLLI2SM = 1, wrong configuration

000010: PLLI2SM = 2

000011: PLLI2SM = 3

000100: PLLI2SM = 4

...

111110: PLLI2SM = 62

111111: PLLI2SM = 63

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Res.

14 rw

Address offset: 0x88

Reset value: 0x0400 3010

Access: no wait state, word, half-word and byte access.

This register is used to configure the PLLSAI clock outputs according to the formulas:

 f

(VCO clock)

= f

(PLLSAI clock input)

× (PLLSAIN / PLLM)

 f

(PLL SAI 48MHz clock output)

= f

(VCO clock)

/ PLLSAIP

 f

(PLL SAI1 clock output)

= f

(VCO clock)

/ PLLSAIQ

Res.

13 rw

Res.

12 rw

27 rw

PLLSAIN[8:0]

PLLSAIQ[3:0] rw rw

9 rw rw rw

24 rw

8 rw

Res.

7 rw

Res.

6 rw

Res.

5 rw

Res.

4 rw

Res.

3 2

PLLSAIM[5:0] rw rw

17 16

PLLSAIP[1:0] rw rw

1 0 rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:24 PLLSAIQ: PLLSAI division factor for SAIs clock

Set and reset by software to control the frequency of SAIs clock.

These bits should be written when the PLLSAI is disabled.

SAI1 clock frequency = VCO frequency / PLLSAIQ with 2 ≤ PLLSAIQ ≤ 15

0000: PLLSAIQ = 0, wrong configuration

0001: PLLSAIQ = 1, wrong configuration

...

0010: PLLSAIQ = 2

0011: PLLSAIQ = 3

0100: PLLSAIQ = 4

0101: PLLSAIQ = 5

...

1111: PLLSAIQ = 15

Bits 23:18 Reserved, must be kept at reset value.

Bits 17:16 PLLSAIP: PLLSAI division factor for 48 MHz clock

These bits are set and cleared by software to control the output clock frequency.

They should be written when the PLLSAI is disabled.

Caution: The software has to set these bits correctly to ensure that the output frequency not exceed 120 MHz on this output

PLL output clock frequency = VCO frequency / PLLSAIP with PLLSAIP = 2, 4, 6 or 8

00: PLLSAIP =2

01: PLLSAIP = 4

10: PLLSAIP = 6

11: PLLSAIP = 8

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Bit 15 Reserved, must be kept at reset value.

Bits 14:6 PLLSAIN: PLLSAI division factor for VCO

Set and reset by software to control the multiplication factor of the VCO. These bits should be written when the PLLSAI is disabled. Only half-word and word accesses are allowed to write these bits.

Caution: The software has to set these bits correctly to ensure that the VCO output frequency is between 100 and 432 MHz.

VCO output frequency = VCO input frequency x PLLSAIN with 50 ≤ PLLSAIN ≤ 432

000000000: PLLSAIN = 0, wrong configuration

000000001: PLLSAIN = 1, wrong configuration ...

001100010: PLLSAIN = 50

...

001100011: PLLSAIN = 99

001100100: PLLSAIN = 100

001100101: PLLSAIN = 101

001100110: PLLSAIN = 102

...

110110000: PLLSAIN = 432

110110000: PLLSAIN = 433, wrong configuration ...

111111111: PLLSAIN = 511, wrong configuration

Note: Between 50 and 99 multiplication factors are possible for VCO input frequency higher than 1 MHz. However care must be taken to fulfill the minimum VCO output frequency as specified above.

Bits 5:0 PLLSAIM: Division factor for audio PLLSAI input clock

Set and cleared by software to divide PLLSAI input clock before the VCO.

These bits can be written only when PLLSAI is disabled.

Caution: The software has to set these bits correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit

PLL jitter.

VCO input frequency = PLL input clock frequency / PLLSAI with 2 <= PLLSAIM <= 63

000000: PLLSAIM = 0, wrong configuration

000001: PLLSAIM = 1, wrong configuration

000010: PLLSAIM = 2

000011: PLLSAIM = 3

000100: PLLSAIM = 4

...

111110: PLLSAIM = 62

111111: PLLSAIM = 63

Address offset: 0x8C

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

This register allows to configure the timer clock prescalers and the PLLSAI and PLLI2S output clock dividers for SAIs peripherals according to the following formula: f

(PLLSAIDIVQ clock output)

= f

(PLLSAI_Q)

/ PLLSAIDIVQ f(

PLLI2SDIVQ clock output)

= f

(PLLI2S_Q)

/ PLLI2SDIVQ

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Res.

28 27

I2S2SRC rw rw

12 11 rw rw

26 25

I2S1SRC rw rw

PLLSAIDIVQ

9 rw rw

TIMPRE rw

23 22

SAI2SRC rw rw

Res.

SAI1SRC rw rw

4 rw

Res.

3 rw

PLLIS2DIVQ rw

1 rw

Res.

0 rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:27 I2S2SRC: I2S APB2 clock source selection

Set and reset by software to control the frequency of the APB2 I2S clock.

These bits should be written when the PLL, PLLSAI and PLLI2S are disabled.

00: I2S2 clock frequency = f

(PLLI2S_R)

01: I2S2 clock frequency = I2S_CKIN Alternate function input frequency

10: I2S2 clock frequency = f

(PLL_R)

11: I2S2 clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22])

Bits 26:25 I2S1SRC: I2S APB1 clock source selection

Set and reset by software to control the frequency of the APB1 I2S clock.

These bits should be written when the PLL, PLLSAI and PLLI2S are disabled.

00: I2S1 clock frequency = f

(PLLI2S_R)

01: I2S1 clock frequency = I2S_CKIN Alternate function input frequency

10: I2S1 clock frequency = f

(PLL_R)

11: I2S1 clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22])

Bit 24 TIMPRE : Timers clocks prescalers selection

This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domain.

0: If the APB prescaler (PPRE1, PPRE2 in the RCC_CFGR register) is configured to a division factor of 1, TIMxCLK = PCLKx. Otherwise, the timer clock frequencies are set to twice to the frequency of the APB domain to which the timers are connected:

TIMxCLK = 2xPCLKx.

1:If the APB prescaler (PPRE1, PPRE2 in the RCC_CFGR register) is configured to a division factor of 1, 2 or 4, TIMxCLK = HCLK. Otherwise, the timer clock frequencies are set to four times to the frequency of the APB domain to which the timers are connected:

TIMxCLK = 4xPCLKx.

Bits 23:22 SAI2SRC : SAI2 clock source selection

These bits are set and cleared by software to control the SAI2 clock frequency.

They should be written when the PLL, PLLSAI and PLLI2S are disabled.

00: SAI2 clock frequency = f

(PLLSAI_Q)

01: SAI2 clock frequency = f

(PLLI2S_Q)

10: SAI2 clock frequency = f

(PLL_R)

/ PLLSAIDIVQ

/ PLLI2SDIVQ

11: SAI2 clock frequency = HSI/HSE depends on PLLSRC (PLLCFGR[22])

Bits 21:20 SAI1SRC : SAI1 clock source selection

These bits are set and cleared by software to control the SAI1 clock frequency.

They should be written when the PLLSAI and PLLI2S are disabled.

00: SAI1 clock frequency = f

(PLLSAI_Q)

01: SAI1 clock frequency = f

(PLLI2S_Q)

10: SAI1 clock frequency = f

(PLL_R)

/ PLLSAIDIVQ

/ PLLI2SDIVQ

11: I2S_CKIN Alternate function input frequency

Bits 19:13 Reserved, must be kept at reset value.

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RM0390 Rev 6

RM0390 Reset and clock control (RCC)

Bits 12:8 PLLSAIDIVQ[4:0] : PLLSAI division factor for SAIs clock

These bits are set and reset by software to control the SAIs clock frequency.

They should be written only if PLLSAI is disabled.

SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ with 1 ≤ PLLSAIDIVQ ≤ 31

00000: PLLSAIDIVQ = /1

00001: PLLSAIDIVQ = /2

00010: PLLSAIDIVQ = /3

00011: PLLSAIDIVQ = /4

00100: PLLSAIDIVQ = /5

...

11111: PLLSAIDIVQ = /32

Bits 7:5 Reserved, must be kept at reset value.

Bits 4:0 PLLI2SDIVQ[4:0] : PLLI2S division factor for SAIs clock

These bits are set and reset by software to control the SAIs clock frequency.

They should be written only if PLLI2S is disabled.

SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ with 1 ≤ PLLI2SDIVQ ≤ 31

00000: PLLI2SDIVQ = /1

00001: PLLI2SDIVQ = /2

00010: PLLI2SDIVQ = /3

00011: PLLI2SDIVQ = /4

00100: PLLI2SDIVQ = /5

...

11111: PLLI2SDIVQ = /32

Address offset: 0x90

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

This register allows to enable or disable the clock gating for the specified IPs.

31 30 29 28 27 26 25 24 23

Res.

15 14 13 12 11 10 9 8 7

Res.

RCC

_CKEN

FLITF

_CKEN

SRAM

_CKEN

SPARE

_CKEN rw rw rw rw

CM4DBG

_CKEN rw

AHB2APB2

_CKEN rw

AHB2APB1

_CKEN rw

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 RCC_CKEN: RCC clock enable

0: the clock gating is enabled

1: the clock gating is disabled, the clock is always enabled.

Bit 5 FLITF_CKEN: Flash Interface clock enable

0: the clock gating is enabled

1: the clock gating is disabled, the clock is always enabled.

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Reset and clock control (RCC)

Bit 4

SRAM_CKEN: SRQAM controller clock enable

0: the clock gating is enabled

1: the clock gating is disabled, the clock is always enabled.

Bit 3

SPARE_CKEN: Spare clock enable

0: the clock gating is enabled

1: the clock gating is disabled, the clock is always enabled.

Bit 2 CM4DBG_CKEN: Cortex M4 ETM clock enable

0: the clock gating is enabled

1: the clock gating is disabled, the clock is always enabled.

Bit 1 AHB2APB2_CKEN: AHB to APB2 Bridge clock enable

0: the clock gating is enabled

1: the clock gating is disabled, the clock is always enabled.

Bit 0 AHB2APB1_CKEN: AHB to APB1 Bridge clock enable

0: the clock gating is enabled

1: the clock gating is disabled, the clock is always enabled.

RM0390

Address offset: 0x94

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

This register allows to enable or disable the clock gating for the specified IPs.

Res.

SPDIFRX

SEL rw

Res.

SDIO

SEL rw

Res.

CK48M

SEL rw

Res.

CEC

SEL rw

Res.

23 22

FMPI2C1SEL

[1:0] rw rw

Res.

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 SPDIFRXSEL: SPDIF-Rx clock selection

1: f

(PLLI2S_P)

0: f

(PLL_R)

Bit 28 SDIOSEL: SDIO clock selection

1: Clock System

0: Clock 48 MHz

Bit 27 CK48MSEL: SDIO/USBFS/HS clock selection

1: f

(PLLSAI_P)

0: f

(PLL_Q)

Bit 26 CECSEL: HDMI CEC clock source selection

1: LSE

0: HSI/488

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RM0390 Rev 6

RM0390 Reset and clock control (RCC)

Bits 25:24 Reserved, must be kept at reset value.

Bits 23:22 FMPI2C1SEL[1:0]: I2C4 kernel clock source selection

00: APB clock selected as FMPI2C1 clock

01: System clock selected as FMPI2C1 clock

10: HSI clock selected as FMPI2C1 clock

11: APB clock selected as FMPI2C1 clock (same as “00”)

Bits 21:0 Reserved, must be kept at reset value.

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0x0C

RCC_CIR

Reset value

0x10

RCC_AHB1

RSTR

Reset value

0x14

RCC_AHB2

RSTR

Reset value

0x18

RCC_AHB3

RSTR

0x1C

Reset value

Reserved

Reset value

0x20

RCC_APB1

RSTR

Reset value

Reset and clock control (RCC)

6.3.28 RCC register map

Table 21 gives the register map and reset values.

Table 21. RCC register map and reset values

Addr. offset

Register name

RM0390

RCC_CR

0x00

Reset value

RCC_PLL

CFGR

0 0 0 0 0 0

PLLR

[2:0]

PLLQ[3:0]

0x04

0x08

Reset value 0 1 0 0 1 0 0

RCC_CFGR

MCO

[1:0]

MCO2

PRE

[2:0]

MCO1

PRE

[2:0]

Reset value 0 0 0 0 0 0 0 0

HSICAL[7:0] HSITRIM[4:0]

0 0 0 0 x x x x x x x x 1 0 0 0 0

PLLP

[1:0]

PLLN[8:0] PLLM[5:0]

1 1

0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0

MCO

[1:0]

RTCPRE[4:0]

PPRE2

[2:0]

PPRE1

[2:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0

HPRE[3:0]

0 0 0

SWS

[1:0]

0 0

[1:0]

0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0

0 0 0 0 0 0 0 0 0

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RM0390 Rev 6

RM0390 Reset and clock control (RCC)

Table 21. RCC register map and reset values (continued)

Addr. offset

Register name

0x24

RCC_APB2

RSTR

0x28

0x2C

Reset value

Reserved

Reset value

Reserved

Reset value

0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x30

RCC_

AHB1ENR

Reset value

RCC_

AHB2ENR

0x34

0x38

0x3C

Reset value

RCC_

AHB3ENR

Reset value

Reserved

Reset value

0x40

RCC_

APB1ENR

Reset value

RCC_

APB2ENR

0x44

0x48

0x4C

Reset value

Reserved

Reset value

Reserved

Reset value

0 0

0 0 0 0 0 0 0

0 0 0

0 0

0 0 0

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Table 21. RCC register map and reset values (continued)

Addr. offset

Register name

RM0390

0x50

RCC_AHB1

LPENR

Reset value

0x54

RCC_AHB2

LPENR

Reset value

0x58

RCC_AHB3

LPENR

0x5C

Reset value

Reserved

Reset value

1 1

0x60

RCC_APB1

LPENR

Reset value

0x64

RCC_APB2

LPENR

0x68

0x6C

Reset value

Reserved

Reset value

Reserved

Reset value

0x70

RCC_BDCR

Reset value

1 1 1 1 1 1

0x74

RCC_CSR

Reset value 0 0 0 0 1 1 1 0

1 1 1

1 1

1 1 1

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RM0390 Rev 6

RM0390 Reset and clock control (RCC)

Table 21. RCC register map and reset values (continued)

Addr. offset

Register name

Reserved

0x78

Reset value

0x7C

Reserved

Reset value

RCC_SS

CGR

INCSTEP MODPER

0x80

0x84

Reset value

RCC_PLLI2

SCFGR

Reset value

0 0

PLLI2SR

[2:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PLLI2SQ

[3:0]

PLLI

2SP

[1:0]

PLLI2SN[8:0] PLLI2SM[5:0]

0 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0

0x88

RCC_PLL

SAI

CFGR

Reset value

PLLSAIR

[2:0]

0 0 0

PLLSAIQ

[3:0]

1 0 0 0 0 0 1 1

PLLSAIN[8:0]

0 0 0 0 0 0 0

PLLSAIM[5:0]

1 0 0 0 0

0x8C

RCC_DCK

CFGR

Reset value 0 0 0 0 0 0 0 0 0

PLLSAIDIVQ

[4:0]

0 0 0 0 0

PLLI2SDIVQ

[4:0]

0 0 0 0 0

0x90

RCC_CK

GATENR

Reset value

0x94

RCC_DCK

CFGR2

Reset value

FMP

I2C1

SEL

[1:0]

0 0 0 0 0 0

Refer to Section 2.2 on page 56 for the register boundary addresses.

0 0 0 0 0 0 0

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General-purpose I/Os (GPIO)

7 General-purpose I/Os (GPIO)

RM0390

7.2

7.3

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Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER,

GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers

(GPIOx_IDR and GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection register (GPIOx_AFRH and GPIOx_AFRL).

GPIO main features

 Up to 16 I/Os under control

 Output states: push-pull or open drain + pull-up/down

 Output data from output data register (GPIOx_ODR) or peripheral (alternate function output)

 Speed selection for each I/O

 Input states: floating, pull-up/down, analog

 Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)

 Bit set and reset register (GPIOx_BSRR) for bitwise write access to GPIOx_ODR

 Locking mechanism (GPIOx_LCKR) provided to freeze the I/O configuration

 Analog function

 Alternate function input/output selection registers (at most 16 AFs per I/O)

 Fast toggle capable of changing every two clock cycles

 Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several peripheral functions

GPIO functional description

Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in several modes:

 Input floating

 Input pull-up

 Input-pull-down

 Analog

 Output open-drain with pull-up or pull-down capability

 Output push-pull with pull-up or pull-down capability

 Alternate function push-pull with pull-up or pull-down capability

 Alternate function open-drain with pull-up or pull-down capability

Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR register is to allow atomic read/modify accesses to any of the GPIO registers. In this way, there is no risk of an IRQ occurring between the read and the modify access.

RM0390 Rev 6

RM0390 General-purpose I/Os (GPIO)

Figure 18 shows the basic structure of a 5 V tolerant I/O port bit, Table 22

gives the possible port bit configurations.

Figure 18. Basic structure of a 5 V tolerant I/O port bit

To on-chip peripheral

Analog

Alternate function input on/off

Read

DD_FT

(1)

TTL Schmitt

trigger

Input driver on/off

Pull up

Protection diode

I/O pin Write

Output driver

Output control

P-MOS on/off

Pull down

Protection diode

Read/write

N-MOS

From on-chip peripheral Alternate function output

Push-pull, open-drain or disabled

Analog ai15939b

1. V

DD_FT is a potential specific to 5 V tolerant I/Os and different from V

Table 22. Port bit configuration table (1)

MODER(i)[1:0] OTYPER(i) OSPEEDR(i)[B:A] PUPDR(i)[1:0]

SPEED[B:A]

I/O configuration

GP output

PP + PU

PP + PD

Reserved

GP output OD

GP output

OD + PU

OD + PD

Reserved (GP output OD)

AF PP

PP + PU

PP + PD

Reserved

OD + PU

OD + PD

Reserved

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Table 22. Port bit configuration table (1) (continued)

MODER(i)[1:0] OTYPER(i) OSPEEDR(i)[B:A] PUPDR(i)[1:0] I/O configuration

11 x x x x x x x x x x x x x x x x x x x x x x x x

Input

Input / output

Floating

Reserved

Reserved (input floating)

Analog

1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate function.

During and just after reset, the alternate functions are not active and the I/O ports are configured in input floating mode.

The debug pins are in AF pull-up/pull-down after reset:

 PA15: JTDI in pull-up

 PA14: JTCK/SWCLK in pull-down

 PA13: JTMS/SWDAT in pull-up

 PB4: NJTRST in pull-up

 PB3: JTDO in floating state

When the pin is configured as output, the value written to the output data register

(GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull mode or open-drain mode (only the N-MOS is activated when 0 is output).

The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB1 clock cycle.

All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not depending on the value in the GPIOx_PUPDR register.

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The microcontroller I/O pins are connected to onboard peripherals/modules through a multiplexer that allows only one peripheral’s alternate function (AF) connected to an I/O pin at a time. In this way, there can be no conflict between peripherals sharing the same I/O pin.

Each I/O pin has a multiplexer with sixteen alternate function inputs (AF0 to AF15) that can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15) registers:

 After reset all I/Os are connected to the system’s alternate function 0 (AF0)

 The peripherals’ alternate functions are mapped from AF1 to AF13

 Cortex

-M4 with FPU EVENTOUT is mapped on AF15

This structure is shown in Figure 19 .

RM0390 Rev 6

RM0390

Note:

General-purpose I/Os (GPIO)

In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped onto different I/O pins to optimize the number of peripherals available in smaller packages.

To use an I/O in a given configuration, proceed as follows:

 System function

Connect the I/O to AF0 and configure it depending on the function used:

– JTAG/SWD, after each device reset these pins are assigned as dedicated pins immediately usable by the debugger host (not controlled by the GPIO controller)

– RTC_REFIN: this pin should be configured in Input floating mode

– MCO1 and MCO2: these pins have to be configured in alternate function mode.

You can disable some or all of the JTAG/SWD pins and so release the associated pins for

GPIO usage.

For more details refer to Section 6.2.10: Clock-out capability

Table 23. Flexible SWJ-DP pin assignment

SWJ I/O pin assigned

Available debug ports PA13 /

JTMS/

SWDIO

PA14 /

JTCK/

SWCLK

PA15 /

JTDI

PB3 /

JTDO

X Full SWJ (JTAG-DP + SW-DP) - Reset state

Full SWJ (JTAG-DP + SW-DP) but without

NJTRST

JTAG-DP Disabled and SW-DP Enabled

JTAG-DP Disabled and SW-DP Disabled

X X

Released

PB4/

NJTRST

 GPIO

Configure the desired I/O as output or input in the GPIOx_MODER register.

 Peripheral alternate function

For the ADC and DAC, configure the desired I/O as analog in the GPIOx_MODER register.

For other peripherals:

– Configure the desired I/O as an alternate function in the GPIOx_MODER register

– Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,

GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively

– Connect the I/O to the desired AFx in the GPIOx_AFRL or GPIOx_AFRH register

 EVENTOUT

Configure the I/O pin used to output the Cortex ® -M4 with FPU EVENTOUT signal by connecting it to AF15

EVENTOUT is not mapped onto the following I/O pins: PC13, PC14, PC15, PH0 and PH1.

Refer to the “Alternate function mapping” table in the datasheets for the detailed mapping of the system and peripherals’ alternate function I/O pins.

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General-purpose I/Os (GPIO)

Figure 19. Selecting an alternate function on STM32F446xx

For pins 0 to 7, the GPIOx_AFRL[31:0] register selects the dedicated alternate function

AF0 (system)

AF1 (TIM1/TIM2)

AF2 (TIM3..5)

AF3 (TIM8..11, CEC)

AF4 (I2C1..4, CEC)

AF5 (SPI1/2/3/4)

AF6 (SPI2/3/4, SAI1)

AF7 (SPI2/3, USART1..3, UART5, SPDIF-IN)

AF8 (SPI2/3, USART1..3, UART5, SPDIF-IN)

AF9 (CAN1/2, TIM12..14, QUADSPI)

AF10 (SAI2, QUADSPI, OTG_HS, OTG_FS)

AF11

AF12 (FMC, SDIO, OTG_HS

(1)

)

AF13 (DCMI)

AF14

AF15 (EVENTOUT)

Pin x (x = 0..7)

RM0390

AFRL[31:0]

For pins 8 to 15, the GPIOx_AFRH[31:0] register selects the dedicated alternate function

AF0 (system)

AF1 (TIM1/TIM2)

AF2 (TIM3..5)

AF3 (TIM8..11, CEC)

AF4 (I2C1..4, CEC)

AF5 (SPI1/2/3/4)

AF6 (SPI2/3/4, SAI1)

AF7 (SPI2/3, USART1..3, UART5, SPDIF-IN)

AF8 (SPI2/3, USART1..3, UART5, SPDIF-IN)

AF9 (CAN1/2, TIM12..14, QUADSPI)

AF10 (SAI2, QUADSPI, OTG_HS, OTG_FS)

AF11

AF12 (FMC, SDIO, OTG_HS

(1)

)

AF13 (DCMI)

AF14

AF15 (EVENTOUT)

Pin x (x = 8..15)

7.3.3

AFRH[31:0]

MS35850V1

1. Configured in FS.

I/O port control registers

Each of the GPIOs has four 32-bit memory-mapped control registers (GPIOx_MODER,

GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The

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RM0390 Rev 6

RM0390

7.3.4

7.3.5

General-purpose I/Os (GPIO)

GPIOx_MODER register is used to select the I/O direction (input, output, AF, analog). The

GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (pushpull or open-drain) and speed (the I/O speed pins are directly connected to the corresponding GPIOx_OSPEEDR register bits whatever the I/O direction). The

GPIOx_PUPDR register is used to select the pull-up/pull-down whatever the I/O direction.

I/O port data registers

Each GPIO has two 16-bit memory-mapped data registers: input and output data registers

(GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write accessible. The data input through the I/O are stored into the input data register

(GPIOx_IDR), a read-only register.

See

Section 7.4.5: GPIO port input data register (GPIOx_IDR) (x = A..H)

and Section 7.4.6:

GPIO port output data register (GPIOx_ODR) (x = A..H) for the register descriptions.

I/O data bitwise handling

The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset register has twice the size of GPIOx_ODR.

To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BSRR(i) and

BSRR(i+SIZE). When written to 1, bit BSRR(i) sets the corresponding ODR(i) bit. When written to 1, bit BSRR(i+SIZE) resets the ODR(i) corresponding bit.

Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in

GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set action takes priority.

Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a

“one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always be accessed directly. The GPIOx_BSRR register provides a way of performing atomic bitwise handling.

There is no need for the software to disable interrupts when programming the GPIOx_ODR at bit level: it is possible to modify one or more bits in a single atomic AHB1 write access.

It is possible to freeze the GPIO control registers by applying a specific write sequence to the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER,

GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.

To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must be the same). When the LOCK sequence has been applied to a port bit, the value of the port bit can no longer be modified until the next reset. Each GPIOx_LCKR bit freezes the corresponding bit in the control registers (GPIOx_MODER, GPIOx_OTYPER,

GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH).

The LOCK sequence (refer to

Section 7.4.8: GPIO port configuration lock register

(GPIOx_LCKR) (x = A..H) ) can only be performed using a word (32-bit long) access to the

GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same time as the [15:0] bits.

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General-purpose I/Os (GPIO) RM0390

For more details refer to LCKR register description in Section 7.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A..H) .

Note:

7.3.8

Two registers are provided to select one out of the sixteen alternate function inputs/outputs available for each I/O. With these registers, you can connect an alternate function to some other pin as required by your application.

This means that a number of possible peripheral functions are multiplexed on each GPIO using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can thus select any one of the possible functions for each I/O. The AF selection signal being common to the alternate function input and alternate function output, a single channel is selected for the alternate function input/output of one I/O.

To know which functions are multiplexed on each GPIO pin, refer to the datasheets.

The application is allowed to select one of the possible peripheral functions for each I/O at a time.

External interrupt/wakeup lines

All ports have external interrupt capability. To use external interrupt lines, the port must be configured in input mode, refer to

Section 10.2: External interrupt/event controller (EXTI)

and Section 10.2.3: Wakeup event management .

When the I/O port is programmed as Input:

 the output buffer is disabled

 the Schmitt trigger input is activated

 the pull-up and pull-down resistors are activated depending on the value in the

GPIOx_PUPDR register

 The data present on the I/O pin are sampled into the input data register every AHB1 clock cycle

 A read access to the input data register provides the I/O State

Figure 20

shows the input configuration of the I/O port bit.

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RM0390 Rev 6

RM0390 General-purpose I/Os (GPIO)

Figure 20. Input floating/pull up/pull down configurations

Read

Write

Read/write on input driver output driver

TTL Schmitt

trigger

VDD on/off

VDD pull up protection diode

I/O pin on/off pull down

VSS

VSS protection diode ai15940b

When the I/O port is programmed as output:

 The output buffer is enabled:

– Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated)

– Push-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register activates the P-MOS

 The Schmitt trigger input is activated

 The weak pull-up and pull-down resistors are activated or not depending on the value in the GPIOx_PUPDR register

 The data present on the I/O pin are sampled into the input data register every AHB1 clock cycle

 A read access to the input data register gets the I/O state

 A read access to the output data register gets the last written value

Figure 21

shows the output configuration of the I/O port bit.

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General-purpose I/Os (GPIO) RM0390

Figure 21. Output configuration on

Read

Write

Read/write

Input driver

Output driver

TTL Schmitt

trigger

Output control

P-MOS

N-MOS

Push-pull or

Open-drain

DD on/off

DD protection diode pull up

I/O pin on/off

SS pull down

SS protection diode ai15941b

7.3.11 Alternate function configuration

When the I/O port is programmed as alternate function:

 The output buffer can be configured as open-drain or push-pull

 The output buffer is driven by the signal coming from the peripheral (transmitter enable and data)

 The Schmitt trigger input is activated

 The weak pull-up and pull-down resistors are activated or not depending on the value in the GPIOx_PUPDR register

 The data present on the I/O pin are sampled into the input data register every AHB1 clock cycle

 A read access to the input data register gets the I/O state

Figure 22

shows the Alternate function configuration of the I/O port bit.

Figure 22. Alternate function configuration

To on-chip peripheral

Alternate function input

Read on

Write

Read/write

From on-chip peripheral

Alternate function output

TTL Schmitt

trigger

Input driver

Output driver

Output control

P-MOS

N-MOS push-pull or open-drain

DD on/off

Pull up protection diode

I/O pin on/off

Pull down

SS V

SS protection diode ai15942b

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RM0390 General-purpose I/Os (GPIO)

Note:

When the I/O port is programmed as analog configuration:

 The output buffer is disabled

 The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).

 The weak pull-up and pull-down resistors are disabled

 Read access to the input data register gets the value “0”

In the analog configuration, the I/O pins cannot be 5 Volt tolerant.

Figure 23

shows the high-impedance, analog-input configuration of the I/O port bit.

Figure 23. High impedance-analog configuration

To on-chip peripheral

Read

Analog

Write

Input driver off

TTL Schmitt

trigger

DD protection diode

I/O pin

SS protection diode

Read/write

From on-chip peripheral

Analog ai15943

7.3.13 Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins

Note:

The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general-purpose

PC14 and PC15 I/Os, respectively, when the LSE oscillator is off. The PC14 and PC15 I/Os are only configured as LSE oscillator pins OSC32_IN and OSC32_OUT when the LSE oscillator is ON. This is done by setting the LSEON bit in the RCC_BDCR register. The LSE has priority over the GPIO function.

The PC14/PC15 GPIO functionality is lost when the 1.2 V domain is powered off (by the device entering the standby mode) or when the backup domain is supplied by V more supplied). In this case the I/Os are set in analog input mode.

BAT

7.3.14 Using the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins

The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1

I/Os, respectively, when the HSE oscillator is OFF. (after reset, the HSE oscillator is off). The

PH0/PH1 I/Os are only configured as OSC_IN/OSC_OUT HSE oscillator pins when the

HSE oscillator is ON. This is done by setting the HSEON bit in the RCC_CR register. The

HSE has priority over the GPIO function.

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General-purpose I/Os (GPIO) RM0390

7.3.15 Selection of RTC additional_AF1 and RTC_AF2 alternate functions

The STM32F446xx feature two GPIO pins RTC_AF1 and RTC_AF2 that can be used for the detection of a tamper or time stamp event, or RTC_ALARM, or RTC_CALIB RTC outputs.

 The RTC_AF1 (PC13) can be used for the following purposes:

RTC_ALARM output: this output can be RTC Alarm A, RTC Alarm B or RTC Wakeup depending on the OSEL[1:0] bits in the RTC_CR register

 RTC_CALIB output: this feature is enabled by setting the COE[23] in the RTC_CR register

 RTC_TAMP1: tamper event detection

 RTC_TS: time stamp event detection

The RTC_AF2 (PA0) can be used for the following purposes:

 RTC_TAMP1: tamper event detection

 RTC_TAMP2: tamper event detection

 RTC_TS: time stamp event detection

The selection of the corresponding pin is performed through the RTC_TAFCR register as follows:

 TAMP1INSEL is used to select which pin is used as the RTC_TAMP1 tamper input

 TSINSEL is used to select which pin is used as the RTC_TS time stamp input

 ALARMOUTTYPE is used to select whether the RTC_ALARM is output in push-pull or open-drain mode

The output mechanism follows the priority order listed in

Table 24

and Table 25

Table 24. RTC_AF1 pin

(1)

Pin configuration and function

RTC_ALARM enabled

RTC_CALIB enabled

Tamper enabled

Time stamp enabled

TAMP1INSEL

TAMPER1 pin selection

TSINSEL

TIMESTAMP pin selection

ALARMOUTTYPE

RTC_ALARM configuration

Alarm out output OD

Alarm out output PP

Calibration out output PP

TAMPER1 input floating

TIMESTAMP and

TAMPER1 input floating

TIMESTAMP input floating

Standard

GPIO

1. OD: open drain; PP: push-pull.

Don’t care

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RM0390 General-purpose I/Os (GPIO)

Pin configuration and function

TAMPER1 input floating

TIMESTAMP and TAMPER1 input floating

TIMESTAMP input floating

Standard GPIO

Table 25. RTC_AF2 pin

Tamper enabled

Time stamp enabled

TAMP1INSEL

TAMPER1 pin selection

TSINSEL

TIMESTAMP pin selection

ALARMOUTTYPE

RTC_ALARM configuration

1 0 1 Don’t care Don’t care

Don’t care

This section gives a detailed description of the GPIO registers.

For a summary of register bits, register address offsets and reset values, refer to Table 26

The GPIO registers can be accessed by byte (8 bits), half-words (16 bits) or words (32 bits).

7.4.1 GPIO port mode register (GPIOx_MODER) (x = A..H)

Address offset: 0x00

Reset values:

 0xA800 0000 for port A

 0x0000 0280 for port B

 0x0000 0000 for other ports

31 30 29 28 27 26 25 24

MODER15[1:0] MODER14[1:0] MODER13[1:0] MODER12[1:0] rw

15 rw

14 rw

13 rw

12 rw

11 rw

10 rw

9 rw

MODER7[1:0] rw rw

MODER6[1:0] rw rw

MODER5[1:0] rw rw

MODER4[1:0] rw rw

23 22

MODER11[1:0] rw

7 rw

MODER3[1:0] rw rw

21 20

MODER10[1:0] rw

5 rw

MODER2[1:0] rw rw

Bits 2y:2y+1 MODERy[1:0]: Port x configuration bits (y = 0..15)

These bits are written by software to configure the I/O direction mode.

00: Input (reset state)

01: General purpose output mode

10: Alternate function mode

11: Analog mode

19 18

MODER9[1:0] rw

3 rw

MODER1[1:0] rw rw

17 16

MODER8[1:0] rw

1 rw

MODER0[1:0] rw rw

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General-purpose I/Os (GPIO) RM0390

7.4.2

Res.

GPIO port output type register (GPIOx_OTYPER) (x = A..H)

Address offset: 0x04

Reset value: 0x0000 0000

Res.

15 14 13 12 11 10

OT15 OT14 OT13 OT12 OT11 OT10 rw rw rw rw rw rw

OT9 rw

OT8 rw

OT7 rw

OT6 rw

OT5 rw

OT4 rw

OT3 rw

OT2 rw

OT1 rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OTy : Port x configuration bits (y = 0..15)

These bits are written by software to configure the output type of the I/O port.

0: Output push-pull (reset state)

1: Output open-drain

OT0 rw

7.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..H)

Address offset: 0x08

Reset values:

 0x0000 00C0 for port B

 0x0000 0000 for other ports

31 30

OSPEEDR15

[1:0] rw rw

15 14

OSPEEDR7

[1:0] rw rw

29 28

OSPEEDR14

[1:0] rw rw

13 12

OSPEEDR6

[1:0] rw rw

27 26

OSPEEDR13

[1:0] rw rw

11 10

OSPEEDR5

[1:0] rw rw

25 24

OSPEEDR12

[1:0] rw rw

9 8

OSPEEDR4

[1:0] rw rw

23 22

OSPEEDR11

[1:0] rw rw

7 6

OSPEEDR3[

1:0] rw rw

21 20

OSPEEDR10

[1:0] rw rw

5 4

OSPEEDR2

[1:0] rw rw

19 18

OSPEEDR9

[1:0] rw rw

3 2

OSPEEDR1

[1:0] rw rw

17 16

OSPEEDR8

[1:0] rw rw

1 0

OSPEEDR0

1:0] rw rw

Bits 2y:2y+1 OSPEEDRy[1:0]: Port x configuration bits (y = 0..15)

These bits are written by software to configure the I/O output speed.

00: Low speed

01: Medium speed

10: Fast speed

11: High speed

Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V range and external load.

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RM0390 General-purpose I/Os (GPIO)

7.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..H)

Address offset: 0x0C

Reset values:

 0x6400 0000 for port A

 0x0000 0100 for port B

 0x0000 0000 for other ports

31 30 29 28 27 26 25 24

PUPDR15[1:0] PUPDR14[1:0] PUPDR13[1:0] PUPDR12[1:0] rw rw rw rw rw rw rw rw

15 14

PUPDR7[1:0] rw rw

13 12

PUPDR6[1:0] rw rw

PUPDR5[1:0] rw

10 rw

9 rw

PUPDR4[1:0] rw

23 22

PUPDR11[1:0] rw rw

7 6

PUPDR3[1:0] rw rw

21 20

PUPDR10[1:0] rw rw

5 4

PUPDR2[1:0] rw rw

19 18

PUPDR9[1:0] rw rw

3 2

PUPDR1[1:0] rw rw

Bits 2y:2y+1 PUPDRy[1:0]: Port x configuration bits (y = 0..15)

These bits are written by software to configure the I/O pull-up or pull-down

00: No pull-up, pull-down

01: Pull-up

10: Pull-down

11: Reserved

17 16

PUPDR8[1:0] rw rw

1 0

PUPDR0[1:0] rw rw

7.4.5

Res.

GPIO port input data register (GPIOx_IDR) (x = A..H)

Address offset: 0x10

Reset value: 0x0000 XXXX (where X means undefined)

Res.

15 14 13 12 11 10 9

IDR15 IDR14 IDR13 IDR12 IDR11 IDR10 IDR9 r r r r r r r

IDR8 r

IDR7 r

IDR6 r

IDR5 r

IDR4 r

IDR3 r

IDR2 r

IDR1 r

IDR0 r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 IDRy : Port input data (y = 0..15)

These bits are read-only and can be accessed in word mode only. They contain the input value of the corresponding I/O port.

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General-purpose I/Os (GPIO) RM0390

7.4.6

Res.

GPIO port output data register (GPIOx_ODR) (x = A..H)

Address offset: 0x14

Reset value: 0x0000 0000

Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ODR15 ODR14 ODR13 ODR12 ODR11 ODR10 ODR9 ODR8 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 ODRy : Port output data (y = 0..15)

These bits can be read and written by software.

Note: For atomic bit set/reset, the ODR bits can be individually set and reset by writing to the

GPIOx_BSRR register (x = A..H).

7.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..H)

Address offset: 0x18

Reset value: 0x0000 0000

BR15 w

BS15 w

BR14 w

BS14 w

BR13 w

BS13 w

BR12 w

BS12 w

BR11 w

BS11 w

BR10 w

BS10 w

BR9 w

BS9 w

BR8 w

BS8 w

BR7 w

BS7 w

BR6 w

BS6 w

BR5 w

BS5 w

BR4 w

BS4 w

BR3 w

BS3 w

BR2 w

BS2 w

BR1 w

BS1 w

Bits 31:16 BRy: Port x reset bit y (y = 0..15)

These bits are write-only and can be accessed in word, half-word or byte mode. A read to these bits returns the value 0x0000.

0: No action on the corresponding ODRx bit

1: Resets the corresponding ODRx bit

Note: If both BSx and BRx are set, BSx has priority.

Bits 15:0 BSy: Port x set bit y (y= 0..15)

These bits are write-only and can be accessed in word, half-word or byte mode. A read to these bits returns the value 0x0000.

0: No action on the corresponding ODRx bit

1: Sets the corresponding ODRx bit

BR0 w

BS0 w

7.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A..H)

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the

GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the

LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next reset.

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RM0390 General-purpose I/Os (GPIO)

Note:

Res.

LCK

K15 rw

A specific write sequence is used to write to the GPIOx_LCKR register. Only word access

(32-bit long) is allowed during this write sequence.

Each lock bit freezes a specific configuration register (control and alternate function registers).

Address offset: 0x1C

Reset value: 0x0000 0000

Access: 32-bit word only, read/write register

Res.

LCK

K14 rw

LCK

K13 rw

Res.

LCK

K12 rw

Res.

LCK

K11 rw

Res.

LCK

K10 rw

Res.

LCK

K9 rw

Res.

LCK

K8 rw

Res.

LCK

K7 rw

Res.

LCK

K6 rw

Res.

LCK

K5 rw

Res.

LCK

K4 rw

Res.

LCK

K3 rw

Res.

LCK

K2 rw

Res.

LCK

K1 rw

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 LCKK[16]: Lock key

This bit can be read any time. It can only be modified using the lock key write sequence.

0: Port configuration lock key not active

1: Port configuration lock key active. The GPIOx_LCKR register is locked until an MCU reset occurs.

LCK

K16 rw

LCK

K0 rw

LOCK key write sequence:

WR LCKR[16] = ‘1’ + LCKR[15:0]

WR LCKR[16] = ‘0’ + LCKR[15:0]

WR LCKR[16] = ‘1’ + LCKR[15:0]

RD LCKR

RD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active)

Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.

Any error in the lock sequence aborts the lock.

After the first lock sequence on any bit of the port, any read access on the LCKK bit will return ‘1’ until the next CPU reset.

Bits 15:0 LCKy: Port x lock bit y (y= 0..15)

These bits are read/write but can only be written when the LCKK bit is ‘0.

0: Port configuration not locked

1: Port configuration locked

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General-purpose I/Os (GPIO)

7.4.9

31 rw

15 rw

GPIO alternate function low register (GPIOx_AFRL) (x = A..H)

Address offset: 0x20

Reset value: 0x0000 0000

30 29

AFRL7[3:0] rw

14 rw

AFRL3[3:0] rw rw

28 rw

12 rw

27 rw

11 rw

26 25

AFRL6[3:0] rw

10 rw

AFRL2[3:0] rw rw

24 rw

8 rw

23 rw

7 rw

22 21

AFRL5[3:0] rw

6 rw

AFRL1[3:0] rw rw

20 rw

4 rw

19 rw

3 rw

Bits 31:0 AFRLy: Alternate function selection for port x bit y (y = 0..7)

These bits are written by software to configure alternate function I/Os

AFRLy selection:

0000: AF0

0001: AF1

0010: AF2

0011: AF3

0100: AF4

0101: AF5

0110: AF6

0111: AF7

1000: AF8

1001: AF9

1010: AF10

1011: AF11

1100: AF12

1101: AF13

1110: AF14

1111: AF15

18 17

AFRL4[3:0] rw

2 rw

AFRL0[3:0] rw rw

RM0390

16 rw

0 rw

31 rw

15 rw

Address offset: 0x24

Reset value: 0x0000 0000

30 29

AFRH15[3:0] rw

14 rw

AFRH11[3:0] rw rw

28 rw

12 rw

27 rw

11 rw

26 25

AFRH14[3:0] rw

10 rw

AFRH10[3:0] rw rw

24 rw

8 rw

23 rw

7 rw

22 21

AFRH13[3:0] rw

6 rw

AFRH9[3:0] rw rw

20 rw

4 rw

19 rw

3 rw

Bits 31:0 AFRHy: Alternate function selection for port x bit y (y = 8..15)

These bits are written by software to configure alternate function I/Os

AFRHy selection:

0000: AF0

0001: AF1

0010: AF2

0011: AF3

0100: AF4

0101: AF5

0110: AF6

0111: AF7

1000: AF8

1001: AF9

1010: AF10

1011: AF11

1100: AF12

1101: AF13

1110: AF14

1111: AF15

18 17

AFRH12[3:0] rw

2 rw

AFRH8[3:0] rw rw

16 rw

0 rw

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RM0390 General-purpose I/Os (GPIO)

7.4.11 GPIO register map

The following table gives the GPIO register map and the reset values.

Table 26. GPIO register map and reset values

Offset Register

0x00

GPIOA_

MODER

Reset value 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOB_

MODER

0x00

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0

0x00

GPIOx_MODER

(where x = C..H)

0x04

Reset value

GPIOx_

OTYPER

(where x = A..H)

Reset value

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x08

GPIOx_

OSPEEDER

(where x = A..H except B)

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x08

GPIOB_

OSPEEDER

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0

0x0C

GPIOA_PUPDR

Reset value 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0C

GPIOB_PUPDR

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

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General-purpose I/Os (GPIO)

Table 26. GPIO register map and reset values (continued)

Offset Register

RM0390

0x0C

GPIOx_PUPDR

(where x = C..H)

0x10

0x14

0x18

0x1C

0x20

0x24

Reset value

GPIOx_IDR

(where x = A..H)

Reset value

GPIOx_ODR

(where x = A..H)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x x x

Reset value

GPIOx_BSRR

(where x = A..H)

Reset value

GPIOx_LCKR

(where x = A..H)

Reset value

GPIOx_AFRL

(where x = A..H)

Reset value

GPIOx_AFRH

(where x = A..H)

Reset value

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AFRL7[3:0] AFRL6[3:0] AFRL5[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AFRL4[3:0] AFRL3[3:0] AFRL2[3:0] AFRL1[3:0] AFRL0[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AFRH15[3:0

]

AFRH14[3:0

]

AFRH13[3:0

]

AFRH12[3:0

]

AFRH11[3:0

]

AFRH10[3:0

]

AFRH9[3:0] AFRH8[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 56 for the register boundary addresses.

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RM0390

8

System configuration controller (SYSCFG)

System configuration controller (SYSCFG)

The system configuration controller is mainly used to remap the memory accessible in the code area and to manage the external interrupt line connection to the GPIOs.

8.1 I/O compensation cell

By default the I/O compensation cell is not used. However when the I/O output buffer speed is configured in 50 MHz or 100 MHz mode, it is recommended to use the compensation cell for slew rate control on I/O t f(IO)out supply.

)/t r(IO)out

commutation to reduce the I/O noise on power

When the compensation cell is enabled, a READY flag is set to indicate that the compensation cell is ready and can be used. The I/O compensation cell can be used only when the supply voltage ranges from 2.4 to 3.6 V.

8.2.1

Note:

SYSCFG memory remap register (SYSCFG_MEMRMP)

This register is used for specific configurations on memory remap:

 Three bits are used to configure the type of memory accessible at address

0x0000 0000. These bits are used to select the physical remap by software and so, bypass the BOOT pins.

 After reset these bits take the value selected by the BOOT pins. When booting from main Flash memory with BOOT pins set to 10 [(BOOT1,BOOT0) = (1,0)] this register takes the value 0x00.

 Other bits are used to swap FMC SDRAM Bank 1/2 with FMC Bank 3/4.

There are two possible FMC remap at address 0x0000 0000:

 FMC Bank 1 (NOR/PSRAM 1 and 2) remap:

Only the first two regions of Bank 1 memory controller (Bank1 NOR/PSRAM 1 and

NOR/PSRAM 2) can be remapped.

 FMC SDRAM Bank 1 remap.

In remap mode at address 0x0000 0000, the CPU can access the external memory via

ICode bus instead of System bus which boosts up the performance.

Address offset: 0x00

Reset value: 0x0000 000X (X is the memory mode selected by the BOOT pins)

Booting from NOR Flash memory or SDRAM is not allowed. The regions can only be mapped at 0x0000 0000 through software remap.

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202

System configuration controller (SYSCFG) RM0390

Res.

)

Res.

11 10

SWP_FMC rw rw

Res.

2 1

MEM_MODE[2:0]

0 rw rw rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:10 SWP_FMC : FMC memory mapping swap

Set and cleared by software. These bits are used to swap the FMC SDRAM

Banks 1/2 from address 0xC000 0000 and 0xD000 0000 to address 0x6000

0000 and 0x7000 0000 to enable the code execution from SDRAM Banks without a physical remapping at 0x0000 0000 address. NOR/PSRAM Bank, which is by default mapped at 0x6000 0000, is remapped at 0xC000 0000 when

SDRAM bank1 is mapped at 0x6000 0000.

00: No FMC memory mapping swap

01: SDRAM banks mapping are swapped. SDRAM Bank 1 and 2 are mapped at

0x6000 0000 and 0x7000 0000 address, respectively. NOR/PSRAM Bank is mapped at 0xC000 0000.

10: Reserved

11: Reserved

Bits 9:3 Reserved, must be kept at reset value.

Bits 2:0 MEM_MODE: Memory mapping selection

Set and cleared by software. This bit controls the memory internal mapping at address 0x0000 0000. After reset these bits take the value selected by the Boot pins (except for FMC).

000: Main Flash memory mapped at 0x0000 0000

001: System Flash memory mapped at 0x0000 0000

010: FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000

011: Embedded SRAM (SRAM1) mapped at 0x0000 0000

100: FMC/SDRAM Bank 1 mapped at 0x0000 0000

Other configurations are reserved

Note: Refer to Section 2.2.2: Memory map and register boundary addresses

for details about the memory mapping at address 0x0000 0000.

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RM0390 System configuration controller (SYSCFG)

8.2.2

Res.

SYSCFG peripheral mode configuration register (SYSCFG_PMC)

Address offset: 0x04

Reset value: 0x0000 0000

Res.

18 rw

Res.

ADCxDC2 rw

Res.

16 rw

Res.

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:16 ADCxDC2 :

0: No effect.

1: Refer to AN4073 on how to use this bit.

Note: These bits can be set only if the following conditions are met:

- ADC clock higher or equal to 30 MHz.

- Only one ADCxDC2 bit must be selected if ADC conversions do not start at the same time and the sampling times differ.

- These bits must not be set when the ADCDC1 bit is set in PWR_CR register.

Bits 15:0 Reserved, must be kept at reset value.

8.2.3

Res.

SYSCFG external interrupt configuration register 1

(SYSCFG_EXTICR1)

Address offset: 0x08

Reset value: 0x0000 0000

Res.

15 rw

14 13

EXTI3[3:0] rw rw

12 rw

11 rw

10 9

EXTI2[3:0] rw rw

8 rw

7 rw

6 5

EXTI1[3:0] rw rw

4 rw

3 rw

2 1

EXTI0[3:0] rw rw

0 rw

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Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 0 to 3)

These bits are written by software to select the source input for the EXTIx external interrupt.

Note: 0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0101: PF[x] pin

0110: PG[x] pin

0111: PH[x] pin

8.2.4

Res.

SYSCFG external interrupt configuration register 2

(SYSCFG_EXTICR2)

Address offset: 0x0C

Reset value: 0x0000 0000

Res.

15 rw

14 13

EXTI7[3:0] rw rw

12 rw

11 rw

10 9

EXTI6[3:0] rw rw

8 rw

7 rw

6 5

EXTI5[3:0] rw rw

4 rw

3 rw

2 1

EXTI4[3:0] rw rw

0 rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 4 to 7)

Note: These bits are written by software to select the source input for the EXTIx external interrupt.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0101: PF[x] pin

0110: PG[x] pin

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8.2.5

Res.

SYSCFG external interrupt configuration register 3

(SYSCFG_EXTICR3)

Address offset: 0x10

Reset value: 0x0000 0000

Res.

15 rw

14 13

EXTI11[3:0] rw rw

12 rw

11 rw

10 9

EXTI10[3:0] rw rw

8 rw

7 rw

6 5

EXTI9[3:0] rw rw

4 rw

3 rw

2 1

EXTI8[3:0] rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 8 to 11)

These bits are written by software to select the source input for the EXTIx external interrupt.

Note: 0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0101: PF[x] pin

0110: PG[x] pin

0 rw

8.2.6

Res.

SYSCFG external interrupt configuration register 4

(SYSCFG_EXTICR4)

Address offset: 0x14

Reset value: 0x0000 0000

Res.

15 rw

14 13

EXTI15[3:0] rw rw

12 rw

11 rw

10 9

EXTI14[3:0] rw rw

8 rw

7 rw

6 5

EXTI13[3:0] rw rw

4 rw

3 rw

2 1

EXTI12[3:0] rw rw

0 rw

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Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 12 to 15)

These bits are written by software to select the source input for the EXTIx external interrupt.

Note: 0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0101: PF[x] pin

0110: PG[x] pin

8.2.7

Res.

Compensation cell control register (SYSCFG_CMPCR)

Address offset: 0x20

Reset value: 0x0000 0000

Res.

8 9

Res.

READY r

Res.

1 0

Res.

CMP_PD rw

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 READY: Compensation cell ready flag

0: I/O compensation cell not ready

1: O compensation cell ready

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 CMP_PD: Compensation cell power-down

0: I/O compensation cell power-down mode

1: I/O compensation cell enabled

Address offset: 0x2C

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18

Res.

15 14 13 12 11 10 9 r

8 7 6 5 4 3 2

Res.

1 0

Res.

FMPI2C1_SDA FMPI2C1_SCL rw rw

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Bits 31:2 Reserved, must be kept at reset value.

Bit 1 FMPI2C1_SDA

Set and cleared by software. When set it forces FM+ drive capability on

FMPI2C1_SDA pin selected through GPIO port mode register and GPIO alternate function selection bits

Bit 0 FMPI2C1_SCL

Set and cleared by software. When set it forces FM+ drive capability on

FMPI2C1_SCL pin selected through GPIO port mode register and GPIO alternate function selection bits

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System configuration controller (SYSCFG)

8.2.9 SYSCFG register maps

The following table summarizes the SYSCFG register map and the reset values.

Table 27. SYSCFG register map and reset values

RM0390

Offset Register

0x00

SYSCFG_

MEMRMP

Reset value

0x04

SYSCFG_PMC

Reset value

0x08

SYSCFG_EXTICR1

Reset value

0x0C

SYSCFG_EXTICR2

Reset value

0x10

SYSCFG_EXTICR3

Reset value

0x14

SYSCFG_EXTICR4

Reset value

0x20

SYSCFG_CMPCR

Reset value

0 0

MEM_

MODE x x x

0 0 0

EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x2C

SYSCFG_CFGR

Reset value

Refer to Section 2.2 on page 56 for the register boundary addresses.

0 0

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9

Direct memory access controller (DMA)

Direct memory access controller (DMA)

9.2

Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory and between memory and memory. Data can be quickly moved by

DMA without any CPU action. This keeps CPU resources free for other operations.

The DMA controller combines a powerful dual AHB master bus architecture with independent FIFO to optimize the bandwidth of the system, based on a complex bus matrix architecture.

The two DMA controllers (DMA1, DMA2) have 8 streams each, dedicated to managing memory access requests from one or more peripherals.

Each stream can have up to 8 channels (requests) in total.

Each DMA controller has an arbiter for handling the priority between DMA requests.

DMA main features

The main DMA features are:

 Dual AHB master bus architecture, one dedicated to memory accesses and one dedicated to peripheral accesses

 AHB slave programming interface supporting only 32-bit accesses

 8 streams for each DMA controller, up to 8 channels (requests) per stream

 Four-word depth 32 first-in, first-out memory buffers (FIFOs) per stream, that can be used in FIFO mode or direct mode:

– FIFO mode: with threshold level software selectable between 1/4, 1/2 or 3/4 of the

FIFO size

– Direct mode: each DMA request immediately initiates a transfer from/to the memory. When it is configured in direct mode (FIFO disabled), to transfer data in memory-to-peripheral mode, the DMA preloads only one data from the memory to the internal FIFO to ensure an immediate data transfer as soon as a DMA request is triggered by a peripheral.

 Each stream can be configured to be:

– a regular channel that supports peripheral-to-memory, memory-to-peripheral and memory-to-memory transfers

– a double buffer channel that also supports double buffering on the memory side

 Priorities between DMA stream requests are software-programmable (four levels consisting of very high, high, medium, low) or hardware in case of equality (for example, request 0 has priority over request 1)

 Each stream also supports software trigger for memory-to-memory transfers (only available for the DMA2 controller)

 Each stream request can be selected among up to 8 possible channel requests. This selection is software-configurable and allows several peripherals to initiate DMA requests

 The number of data items to be transferred can be managed either by the DMA controller or by the peripheral:

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– DMA flow controller: the number of data items to be transferred is softwareprogrammable from 1 to 65535

– Peripheral flow controller: the number of data items to be transferred is unknown and controlled by the source or the destination peripheral that signals the end of the transfer by hardware

 Independent source and destination transfer width (byte, half-word, word): when the data widths of the source and destination are not equal, the DMA automatically packs/unpacks the necessary transfers to optimize the bandwidth. This feature is only available in FIFO mode

 Incrementing or non-incrementing addressing for source and destination

 Supports incremental burst transfers of 4, 8 or 16 beats. The size of the burst is software-configurable, usually equal to half the FIFO size of the peripheral

 Each stream supports circular buffer management

 5 event flags (DMA half transfer, DMA transfer complete, DMA transfer error, DMA

FIFO error, direct mode error) logically ORed together in a single interrupt request for each stream

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9.3 DMA functional description

Direct memory access controller (DMA)

The figure below shows the block diagram of a DMA.

Figure 24. DMA block diagram

DMA controller

REQ_STR0_CH0

REQ_STR0_CH1

REQ_STR0_CH7

REQ_STR1_CH0

REQ_STR1_CH1

REQ_STR1_CH7

REQ_STREAM0

REQ_STREAM1

REQ_STREAM2

REQ_STREAM3

REQ_STREAM4

REQ_STREAM5

REQ_STREAM6

REQ_STREAM7

Arbiter

REQ_STR7_CH0

REQ_STR7_CH1

REQ_STR7_CH7

Channel selection

Memory port

Peripheral port

AHB slave programming interface

Programming port ai15945b

The DMA controller performs direct memory transfer: as an AHB master, the DMA controller can take the control of the AHB bus matrix to initiate AHB transactions.

The DMA controller carries out the following transactions:

 peripheral-to-memory

 memory-to-peripheral

 memory-to-memory

The DMA controller provides two AHB master ports: the AHB memory port, intended to be connected to memories and the AHB peripheral port, intended to be connected to peripherals. However, to allow memory-to-memory transfers, the AHB peripheral port must also have access to the memories.

The AHB slave port is used to program the DMA controller (it supports only 32-bit accesses).

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A DMA transaction consists of a sequence of a given number of data transfers. The number of data items to be transferred and their width (8-bit, 16-bit or 32-bit) are softwareprogrammable.

Each DMA transfer consists of three operations:

 a loading from the peripheral data register or a location in memory, addressed through the DMA_SxPAR or DMA_SxM0AR register

 a storage of the data loaded to the peripheral data register or a location in memory addressed through the DMA_SxPAR or DMA_SxM0AR register

 a post-decrement of the DMA_SxNDTR register, containing the number of transactions that still have to be performed

After an event, the peripheral sends a request signal to the DMA controller. The DMA controller serves the request depending on the channel priorities. As soon as the DMA controller accesses the peripheral, an Acknowledge signal is sent to the peripheral by the

DMA controller. The peripheral releases its request as soon as it gets the Acknowledge signal from the DMA controller. Once the request has been deasserted by the peripheral, the DMA controller releases the Acknowledge signal. If there are more requests, the peripheral can initiate the next transaction.

Each stream is associated with a DMA request that can be selected out of 8 possible channel requests. The selection is controlled by the CHSEL[2:0] bits in the DMA_SxCR register.

Caution: A same peripheral request can be assigned to two different channels only if the application ensures that these channels are not requested to be served at the same time. In other words, if two different channels receive a same asserted peripheral request at the same time, an unpredictable DMA hardware behavior occurs.

Figure 25. Channel selection

REQ_STRx_CH7

REQ_STRx_CH6

REQ_STRx_CH5

REQ_STRx_CH4

REQ_STRx_CH3

REQ_STRx_CH2

REQ_STRx_CH1

REQ_STRx_CH0

REQ_STREAMx

DMA_SxCR

3 1 2 7 25

CHSEL[2:0]

0 ai15947b

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The 8 requests from the peripherals (such as TIM, ADC, SPI, I2C) are independently connected to each channel and their connection depends on the product implementation.

Table 28 and Table 29

give examples of DMA request mappings.

Table 28. DMA1 request mapping

Peripheral requests

Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

SPI3_RX

I2C1_RX

TIM4_CH1

UART5_RX

TIM5_CH3

TIM5_UP

SPDIFRX_DT

I2C3_RX

TIM2_UP

TIM2_CH3

USART3_RX

SPI3_RX

TIM7_UP

FMPI2C1_RX

I2C3_RX

UART4_RX

TIM3_CH4

TIM3_UP

TIM5_CH4

TIM5_TRIG

TIM6_UP

TIM5_CH1

I2C2_RX

SPI2_RX

TIM4_CH2

USART3_TX

TIM5_CH4

TIM5_TRIG

I2C2_RX

SPI2_TX

TIM7_UP

I2C3_TX

UART4_TX

TIM3_CH1

TIM3_TRIG

TIM5_CH2

USART3_TX

SPI3_TX

I2C1_RX

FMPI2C1_TX

SPDIFRX_CS

I2C1_TX

TIM4_UP

SPI3_TX

I2C1_TX

TIM4_CH3

TIM2_CH1

TIM2_CH2

TIM2_CH4

TIM2_UP

TIM2_CH4

USART2_RX USART2_TX UART5_TX

TIM3_CH2

DAC1

TIM5_UP

DAC2

TIM3_CH3

I2C2_TX

Peripheral requests

Stream 0 Stream 1

Table 29. DMA2 request mapping

Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

ADC1

ADC3

SPI1_RX

SPI4_RX

TIM1_TRIG

SAI1_A

DCMI

ADC3

SPI4_TX

USART6_RX

TIM1_CH1

TIM8_CH1

TIM8_CH2

TIM8_CH3

ADC2

SPI1_RX

USART1_RX

USART6_RX

TIM1_CH2

SAI1_A

ADC2

SPI1_TX

SDIO

SPI4_RX

TIM1_CH1

ADC1

SAI1_B

SAI2_A

SPI4_TX

TIM1_CH4

TIM1_TRIG

TIM1_COM

SAI1_B

SPI1_TX

USART1_RX

TIM1_CH1

TIM1_CH2

TIM1_CH3

SAI2_B

DCMI

SAI2_B

SDIO

QUADSPI

USART1_TX

USART6_TX USART6_TX

TIM1_UP TIM1_CH3 -

Channel 7 TIM8_UP TIM8_CH1 TIM8_CH2 TIM8_CH3 -

TIM8_CH4

TIM8_TRIG

TIM8_COM

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9.3.5 Arbiter

An arbiter manages the 8 DMA stream requests based on their priority for each of the two

AHB master ports (memory and peripheral ports) and launches the peripheral/memory access sequences.

Priorities are managed in two stages:

 Software: each stream priority can be configured in the DMA_SxCR register. There are four levels:

– Very high priority

– High priority

– Medium priority

– Low priority

 Hardware: If two requests have the same software priority level, the stream with the lower number takes priority over the stream with the higher number. For example, stream 2 takes priority over stream 4.

Each of the eight DMA controller streams provides a unidirectional transfer link between a source and a destination.

Each stream can be configured to perform:

 Regular type transactions: memory-to-peripherals, peripherals-to-memory or memoryto-memory transfers

 Double-buffer type transactions: double buffer transfers using two memory pointers for the memory (while the DMA is reading/writing from/to a buffer, the application can write/read to/from the other buffer).

The amount of data to be transferred (up to 65535) is programmable and related to the source width of the peripheral that requests the DMA transfer connected to the peripheral

AHB port. The register that contains the amount of data items to be transferred is decremented after each transaction.

Both source and destination transfers can address peripherals and memories in the entire

4-Gbyte area, at addresses comprised between 0x0000 0000 and 0xFFFF FFFF.

The direction is configured using the DIR[1:0] bits in the DMA_SxCR register and offers three possibilities: memory-to-peripheral, peripheral-to-memory or memory-to-memory transfers.

The table below describes the corresponding source and destination addresses.

Bits DIR[1:0] of the

DMA_SxCR register

Table 30. Source and destination address

Direction Source address

Peripheral-to-memory

Memory-to-peripheral

DMA_SxPAR

DMA_SxM0AR

Destination address

DMA_SxM0AR

DMA_SxPAR

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Table 30. Source and destination address (continued)

Bits DIR[1:0] of the

DMA_SxCR register

Direction Source address Destination address

Memory-to-memory

Reserved

DMA_SxPAR

DMA_SxM0AR

When the data width (programmed in the PSIZE or MSIZE bits in the DMA_SxCR register) is a half-word or a word, respectively, the peripheral or memory address written into the

DMA_SxPAR or DMA_SxM0AR/M1AR registers has to be aligned on a word or half-word address boundary, respectively.

Peripheral-to-memory mode

Figure 26

describes this mode.

When this mode is enabled (by setting the bit EN in the DMA_SxCR register), each time a peripheral request occurs, the stream initiates a transfer from the source to fill the FIFO.

When the threshold level of the FIFO is reached, the contents of the FIFO are drained and stored into the destination.

The transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral requests the end of transfers (in case of a peripheral flow controller) or when the EN bit in the DMA_SxCR register is cleared by software.

In direct mode (when the DMDIS value in the DMA_SxFCR register is 0), the threshold level of the FIFO is not used: after each single data transfer from the peripheral to the FIFO, the corresponding data are immediately drained and stored into the destination.

The stream has access to the AHB source or destination port only if the arbitration of the corresponding stream is won. This arbitration is performed using the priority defined for each stream using the PL[1:0] bits in the DMA_SxCR register.

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DMA controller

Figure 26. Peripheral-to-memory mode

DMA_SxM0AR

DMA_SxM1AR

(1)

AHB memory port

Memory bus

Memory destination

RM0390

REQ_STREAMx

Arbiter

FIFO level FIFO

AHB peripheral port

Peripheral bus peripheral source

DMA_SxPAR

Peripheral DMA request ai15948

1. For double-buffer mode.

Memory-to-peripheral mode

Figure 27

describes this mode.

When this mode is enabled (by setting the EN bit in the DMA_SxCR register), the stream immediately initiates transfers from the source to entirely fill the FIFO.

Each time a peripheral request occurs, the contents of the FIFO are drained and stored into the destination. When the level of the FIFO is lower than or equal to the predefined threshold level, the FIFO is fully reloaded with data from the memory.

In direct mode (when the DMDIS value in the DMA_SxFCR register is 0), the threshold level of the FIFO is not used. Once the stream is enabled, the DMA preloads the first data to transfer into an internal FIFO. As soon as the peripheral requests a data transfer, the DMA transfers the preloaded value into the configured destination. It then reloads again the empty internal FIFO with the next data to be transfer. The preloaded data size corresponds to the value of the PSIZE bitfield in the DMA_SxCR register.

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DMA controller

Figure 27. Memory-to-peripheral mode

DMA_SxM0AR

DMA_SxM1AR

(1)

Memory bus

AHB memory port

Memory source

REQ_STREAMx

Arbiter

FIFO level FIFO

Note:

AHB peripheral port

Peripheral bus

Peripheral destination

DMA_SxPAR

Peripheral DMA request ai15949

1. For double-buffer mode.

Memory-to-memory mode

The DMA channels can also work without being triggered by a request from a peripheral.

This is the memory-to-memory mode, described in Figure 28 .

When the stream is enabled by setting the Enable bit (EN) in the DMA_SxCR register, the stream immediately starts to fill the FIFO up to the threshold level. When the threshold level is reached, the FIFO contents are drained and stored into the destination.

The transfer stops once the DMA_SxNDTR register reaches zero or when the EN bit in the

DMA_SxCR register is cleared by software.

When memory-to-memory mode is used, the circular and direct modes are not allowed.

Only the DMA2 controller is able to perform memory-to-memory transfers.

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Direct memory access controller (DMA)

DMA controller

Figure 28. Memory-to-memory mode

DMA_SxM0AR

DMA_SxM1AR

(1)

AHB memory port

RM0390

Memory bus

Memory 2 destination

Stream enable

Arbiter level FIFO

AHB peripheral port

DMA_SxPAR

Peripheral bus

Memory 1 source ai15950

1. For double-buffer mode.

Peripheral and memory pointers can optionally be automatically post-incremented or kept constant after each transfer depending on the PINC and MINC bits in the DMA_SxCR register.

Disabling the increment mode is useful when the peripheral source or destination data is accessed through a single register.

If the increment mode is enabled, the address of the next transfer is the address of the previous one incremented by 1 (for bytes), 2 (for half-words) or 4 (for words) depending on the data width programmed in the PSIZE or MSIZE bits in the DMA_SxCR register.

In order to optimize the packing operation, it is possible to fix the increment offset size for the peripheral address whatever the size of the data transferred on the AHB peripheral port.

The PINCOS bit in the DMA_SxCR register is used to align the increment offset size with the data size on the peripheral AHB port, or on a 32-bit address (the address is then incremented by 4). The PINCOS bit has an impact on the AHB peripheral port only.

If the PINCOS bit is set, the address of the following transfer is the address of the previous one incremented by 4 (automatically aligned on a 32-bit address), whatever the PSIZE value. The AHB memory port, however, is not impacted by this operation.

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Note:

The circular mode is available to handle circular buffers and continuous data flows (e.g.

ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_SxCR register.

When the circular mode is activated, the number of data items to be transferred is automatically reloaded with the initial value programmed during the stream configuration phase, and the DMA requests continue to be served.

In the circular mode, it is mandatory to respect the following rule in case of a burst mode configured for memory:

DMA_SxNDTR = Multiple of ((Mburst beat) × (Msize)/(Psize)), where:

– (Mburst beat) = 4, 8 or 16 (depending on the MBURST bits in the DMA_SxCR register)

– ((Msize)/(Psize)) = 1, 2, 4, 1/2 or 1/4 (Msize and Psize represent the MSIZE and

PSIZE bits in the DMA_SxCR register. They are byte dependent)

– DMA_SxNDTR = Number of data items to transfer on the AHB peripheral port

For example: Mburst beat = 8 (INCR8), MSIZE = 00 (byte) and PSIZE = 01 (half-word), in this case: DMA_SxNDTR must be a multiple of (8 × 1/2 = 4).

If this formula is not respected, the DMA behavior and data integrity are not guaranteed.

NDTR must also be a multiple of the Peripheral burst size multiplied by the peripheral data size, otherwise this could result in a bad DMA behavior.

Note:

This mode is available for all the DMA1 and DMA2 streams.

The double-buffer mode is enabled by setting the DBM bit in the DMA_SxCR register.

A double-buffer stream works as a regular (single buffer) stream with the difference that it has two memory pointers. When the double-buffer mode is enabled, the circular mode is automatically enabled (CIRC bit in DMA_SxCR is not relevant) and at each end of transaction, the memory pointers are swapped.

In this mode, the DMA controller swaps from one memory target to another at each end of transaction. This allows the software to process one memory area while the second memory area is being filled/used by the DMA transfer. The double-buffer stream can work in both directions (the memory can be either the source or the destination) as described in

Table 31: Source and destination address registers in double-buffer mode (DBM = 1) .

In double-buffer mode, it is possible to update the base address for the AHB memory port on-the-fly ( DMA_SxM0AR or DMA_SxM1AR ) when the stream is enabled, by respecting the following conditions:

 When the CT bit is 0 in the DMA_SxCR register, the DMA_SxM1AR register can be written. Attempting to write to this register while CT = 1 sets an error flag (TEIF) and the stream is automatically disabled.

 When the CT bit is 1 in the DMA_SxCR register, the DMA_SxM0AR register can be written. Attempting to write to this register while CT = 0, sets an error flag (TEIF) and the stream is automatically disabled.

To avoid any error condition, it is advised to change the base address as soon as the TCIF flag is asserted because, at this point, the targeted memory must have changed from

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Direct memory access controller (DMA) RM0390 memory 0 to 1 (or from 1 to 0) depending on the value of CT in the DMA_SxCR register in accordance with one of the two above conditions.

For all the other modes (except the double-buffer mode), the memory address registers are write-protected as soon as the stream is enabled.

Table 31. Source and destination address registers in double-buffer mode (DBM = 1)

Bits DIR[1:0] of the

DMA_SxCR register

Direction Source address Destination address

Peripheral-to-memory

Reserved

DMA_SxPAR

Memory-to-peripheral DMA_SxM0AR / DMA_SxM1AR

Not allowed

(1)

DMA_SxM0AR / DMA_SxM1AR

DMA_SxPAR

1. When the double-buffer mode is enabled, the circular mode is automatically enabled. Since the memory-to-memory mode is not compatible with the circular mode, when the double-buffer mode is enabled, it is not allowed to configure the memory-to-memory mode.

9.3.11 Programmable data width, packing/unpacking, endianness

The number of data items to be transferred has to be programmed into DMA_SxNDTR

(number of data items to transfer bit, NDT) before enabling the stream (except when the flow controller is the peripheral, PFCTRL bit in DMA_SxCR is set).

When using the internal FIFO, the data widths of the source and destination data are programmable through the PSIZE and MSIZE bits in the DMA_SxCR register (can be 8-,

16- or 32-bit).

When PSIZE and MSIZE are not equal:

 The data width of the number of data items to transfer, configured in the DMA_SxNDTR register is equal to the width of the peripheral bus (configured by the PSIZE bits in the

DMA_SxCR register). For instance, in case of peripheral-to-memory, memory-toperipheral or memory-to-memory transfers and if the PSIZE[1:0] bits are configured for half-word, the number of bytes to be transferred is equal to 2 × NDT.

 The DMA controller only copes with little-endian addressing for both source and destination. This is described in

Table 32: Packing/unpacking and endian behavior (bit

PINC = MINC = 1)

This packing/unpacking procedure may present a risk of data corruption when the operation is interrupted before the data are completely packed/unpacked. So, to ensure data coherence, the stream may be configured to generate burst transfers: in this case, each group of transfers belonging to a burst are indivisible (refer to

Section 9.3.12: Single and burst transfers ).

In direct mode (DMDIS = 0 in the DMA_SxFCR register), the packing/unpacking of data is not possible. In this case, it is not allowed to have different source and destination transfer data widths: both are equal and defined by the PSIZE bits in the DMA_SxCR register.

MSIZE bits are not relevant.

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Table 32. Packing/unpacking and endian behavior (bit PINC = MINC = 1)

AHB memory port width

AHB peripheral port width

Number of data items to transfer

(NDT)

Memory transfer number

Memory port address / byte lane

Peripheral transfer number

Peripheral port address / byte lane

PINCOS = 1 PINCOS = 0

0x0 / B0[7:0]

0x1 / B1[7:0]

0x2 / B2[7:0]

0x3 / B3[7:0]

0x0 / B0[7:0]

0x1 / B1[7:0]

0x2 / B2[7:0]

0x3 / B3[7:0]

0x0 / B0[7:0]

0x1 / B1[7:0]

0x2 / B2[7:0]

0x3 / B3[7:0]

0x0 / B1|B0[15:0]

0x2 / B3|B2[15:0]

0x0 / B0[7:0]

0x4 / B1[7:0]

0x8 / B2[7:0]

0xC / B3[7:0]

0x0 / B1|B0[15:0]

0x4 / B3|B2[15:0]

0x0 /

B3|B2|B1|B0[31:0]

0x0 / B0[7:0]

0x1 / B1[7:0]

0x2 / B2[7:0]

0x3 / B3[7:0]

0x0 / B1|B0[15:0]

0x2 / B3|B2[15:0]

0x0 /

B3|B2|B1|B0[31:0]

1 -

0x0 / B1|B0[15:0]

0x2 / B1|B0[15:0]

0x0 / B1|B0[15:0]

0x2 / B3|B2[15:0]

0x0 / B3|B2|B1|B0[31:0]

0x0 /B3|B2|B1|B0[31:0]

0x0 /B3|B2|B1|B0 [31:0]

0x0 / B0[7:0]

0x4 / B1[7:0]

0x8 / B2[7:0]

0xC / B3[7:0]

0x0 / B1|B0[15:0]

0x4 / B3|B2[15:0]

0x0 /

B3|B2|B1|B0[31:0]

0x0 / B0[7:0]

0x4 / B1[7:0]

0x8 / B2[7:0]

0xC / B3[7:0]

0x0 / B1|B0[15:0]

0x4 / B3|B2[15:0]

0x0 /

B3|B2|B1|B0 [31:0]

0x0 / B0[7:0]

0x1 / B1[7:0]

0x2 / B2[7:0]

0x3 / B3[7:0]

0x0 / B1|B0[15:0]

0x2 / B3|B2[15:0]

0x0 /

B3|B2|B1|B0[31:0]

0x0 / B0[7:0]

0x1 / B1[7:0]

0x2 / B2[7:0]

0x3 / B3[7:0]

0x0 / B1|B0[15:0]

0x2 / B3|B2[15:0]

0x0 /

B3|B2|B1|B0[31:0]

Note: Peripheral port may be the source or the destination (it can also be the memory source in the case of memory-to-memory transfer).

PSIZE, MSIZE and NDT[15:0] must be configured so as to ensure that the last transfer is not incomplete. This can occur when the data width of the peripheral port (PSIZE bits) is lower than the data width of the memory port (MSIZE bits). This constraint is summarized in the table below.

Table 33. Restriction on NDT versus PSIZE and MSIZE

PSIZE[1:0] of DMA_SxCR MSIZE[1:0] of DMA_SxCR NDT[15:0] of DMA_SxNDTR

00 (8-bit)

01 (16-bit)

10 (32-bit)

Must be a multiple of 2.

Must be a multiple of 4.

Must be a multiple of 2.

The DMA controller can generate single transfers or incremental burst transfers of 4, 8 or

16 beats.

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The size of the burst is configured by software independently for the two AHB ports by using the MBURST[1:0] and PBURST[1:0] bits in the DMA_SxCR register.

The burst size indicates the number of beats in the burst, not the number of bytes transferred.

To ensure data coherence, each group of transfers that form a burst are indivisible: AHB transfers are locked and the arbiter of the AHB bus matrix does not degrant the DMA master during the sequence of the burst transfer.

Depending on the single or burst configuration, each DMA request initiates a different number of transfers on the AHB peripheral port:

 When the AHB peripheral port is configured for single transfers, each DMA request generates a data transfer of a byte, half-word or word depending on the PSIZE[1:0] bits in the DMA_SxCR register

 When the AHB peripheral port is configured for burst transfers, each DMA request generates 4,8 or 16 beats of byte, half word or word transfers depending on the

PBURST[1:0] and PSIZE[1:0] bits in the DMA_SxCR register.

The same as above has to be considered for the AHB memory port considering the

MBURST and MSIZE bits.

In direct mode, the stream can only generate single transfers and the MBURST[1:0] and

PBURST[1:0] bits are forced by hardware.

The address pointers (DMA_SxPAR or DMA_SxM0AR registers) must be chosen so as to ensure that all transfers within a burst block are aligned on the address boundary equal to the size of the transfer.

The burst configuration has to be selected in order to respect the AHB protocol, where bursts must not cross the 1 Kbyte address boundary because the minimum address space that can be allocated to a single slave is 1 Kbyte. This means that the 1-Kbyte address boundary must not be crossed by a burst block transfer, otherwise an AHB error is generated, that is not reported by the DMA registers.

9.3.13 FIFO

FIFO structure

The FIFO is used to temporarily store data coming from the source before transmitting them to the destination.

Each stream has an independent 4-word FIFO and the threshold level is softwareconfigurable between 1/4, 1/2, 3/4 or full.

To enable the use of the FIFO threshold level, the direct mode must be disabled by setting the DMDIS bit in the DMA_SxFCR register.

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The structure of the FIFO differs depending on the source and destination data widths, and is described in the figure below.

Figure 29. FIFO structure

4 words

Empty byte lane 3

Source: byte byte lane 2

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 byte lane 1

B15

B14

B13

1/4 byte lane 0

B12

B 11

B10

1/2

3/4

Full

Destination: word

W3, W2, W1, W0

4 words

Empty byte lane 3

Source: byte byte lane 2

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 byte lane 1

B15

B14

B13

1/4

B 11

B10

1/2

B5 byte lane 0

B12

3/4

Full

Destination: half-word

H7, H6, H5, H4, H3, H2, H1, H0

4 words

Source: half-word

H7 H6 H5 H4 H3 H2 H1 H0

Empty byte lane 3

H7 byte lane 2 byte lane 1 byte lane 0

1/4

1/2

3/4

Full

Destination: word

W3, W2, W1, W0

4-words

Source: half-word

H7 H6 H5 H4 H3 H2 H1 H0

Empty byte lane 3 B15

1/4 byte lane 2

H7 byte lane 1

B14

B13 byte lane 0

B12

B 11

B10

1/2

3/4

Full

Destination: byte

B15 B14 B13 B12 B11 B10 B9 B8

B7 B6 B5 B4 B3 B2 B1 B0 ai15951

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FIFO threshold and burst configuration

Caution is required when choosing the FIFO threshold (bits FTH[1:0] of the DMA_SxFCR register) and the size of the memory burst (MBURST[1:0] of the DMA_SxCR register): The content pointed by the FIFO threshold must exactly match an integer number of memory burst transfers. If this is not in the case, a FIFO error (flag FEIFx of the DMA_HISR or

DMA_LISR register) is generated when the stream is enabled, then the stream is automatically disabled. The allowed and forbidden configurations are described in the table below. The forbidden configurations are highlighted in gray in the table.

MSIZE

Byte

Half-word

Word

FIFO level

Table 34. FIFO threshold configurations

MBURST = INCR4 MBURST = INCR8

1/2

3/4

Full

1/4

1/2

1/4

1/2

3/4

Full

1/4

3/4

Full

1 burst of 4 beats

2 bursts of 4 beats

3 bursts of 4 beats

4 bursts of 4 beats

Forbidden

1 burst of 4 beats

Forbidden

2 bursts of 4 beats

Forbidden

1 burst of 4 beats

Forbidden

1 burst of 8 beats

Forbidden

2 bursts of 8 beats

Forbidden

1 burst of 8 beats

Forbidden

MBURST = INCR16

Forbidden

1 burst of 16 beats

Forbidden

In all cases, the burst size multiplied by the data size must not exceed the FIFO size (data size can be: 1 (byte), 2 (half-word) or 4 (word)).

Incomplete burst transfer at the end of a DMA transfer may happen if one of the following conditions occurs:

 For the AHB peripheral port configuration: the total number of data items (set in the

DMA_SxNDTR register) is not a multiple of the burst size multiplied by the data size.

 For the AHB memory port configuration: the number of remaining data items in the

FIFO to be transferred to the memory is not a multiple of the burst size multiplied by the data size.

In such cases, the remaining data to be transferred is managed in single mode by the DMA, even if a burst transaction is requested during the DMA stream configuration.

When burst transfers are requested on the peripheral AHB port and the FIFO is used

(DMDIS = 1 in the DMA_SxCR register), it is mandatory to respect the following rule to avoid permanent underrun or overrun conditions, depending on the DMA stream direction:

If (PBURST × PSIZE) = FIFO_SIZE (4 words), FIFO_Threshold = 3/4 is forbidden with

PSIZE = 1, 2 or 4 and PBURST = 4, 8 or 16.

This rule ensures that enough FIFO space at a time is free to serve the request from the peripheral.

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FIFO flush

The FIFO can be flushed when the stream is disabled by resetting the EN bit in the

DMA_SxCR register and when the stream is configured to manage peripheral-to-memory or memory-to-memory transfers. If some data are still present in the FIFO when the stream is disabled, the DMA controller continues transferring the remaining data to the destination

(even though stream is effectively disabled). When this flush is completed, the transfer complete status bit (TCIFx) in the DMA_LISR or DMA_HISR register is set.

The remaining data counter DMA_SxNDTR keeps the value in this case to indicate how many data items are currently available in the destination memory.

Note that during the FIFO flush operation, if the number of remaining data items in the FIFO to be transferred to memory (in bytes) is less than the memory data width (for example 2 bytes in FIFO while MSIZE is configured to word), data is sent with the data width set in the

MSIZE bit in the DMA_SxCR register. This means that memory is written with an undesired value. The software may read the DMA_SxNDTR register to determine the memory area that contains the good data (start address and last address).

If the number of remaining data items in the FIFO is lower than a burst size (if the MBURST bits in DMA_SxCR register are set to configure the stream to manage burst on the AHB memory port), single transactions are generated to complete the FIFO flush.

Direct mode

By default, the FIFO operates in direct mode (DMDIS bit in the DMA_SxFCR is reset) and the FIFO threshold level is not used. This mode is useful when the system requires an immediate and single transfer to or from the memory after each DMA request.

When the DMA is configured in direct mode (FIFO disabled), to transfer data in memory-toperipheral mode, the DMA preloads one data from the memory to the internal FIFO to ensure an immediate data transfer as soon as a DMA request is triggered by a peripheral.

To avoid saturating the FIFO, it is recommended to configure the corresponding stream with a high priority.

This mode is restricted to transfers where:

 the source and destination transfer widths are equal and both defined by the

PSIZE[1:0] bits in DMA_SxCR (MSIZE[1:0] bits are not relevant)

 burst transfers are not possible (PBURST[1:0] and MBURST[1:0] bits in DMA_SxCR are don’t care)

Direct mode must not be used when implementing memory-to-memory transfers.

Different events can generate an end of transfer by setting the TCIFx bit in the DMA_LISR or DMA_HISR status register:

 In DMA flow controller mode:

– The DMA_SxNDTR counter has reached zero in the memory-to-peripheral mode.

– The stream is disabled before the end of transfer (by clearing the EN bit in the

DMA_SxCR register) and (when transfers are peripheral-to-memory or memory-

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 In Peripheral flow controller mode:

– The last external burst or single request has been generated from the peripheral and (when the DMA is operating in peripheral-to-memory mode) the remaining data have been transferred from the FIFO into the memory

– The stream is disabled by software, and (when the DMA is operating in peripheralto-memory mode) the remaining data have been transferred from the FIFO into the memory

The transfer completion is dependent on the remaining data in FIFO to be transferred into memory only in the case of peripheral-to-memory mode. This condition is not applicable in memory-to-peripheral mode.

If the stream is configured in non-circular mode, after the end of the transfer (that is when the number of data to be transferred reaches zero), the DMA is stopped (EN bit in

DMA_SxCR register is cleared by Hardware) and no DMA request is served unless the software reprograms the stream and re-enables it (by setting the EN bit in the DMA_SxCR register).

Note:

At any time, a DMA transfer can be suspended to be restarted later on or to be definitively disabled before the end of the DMA transfer.

There are two cases:

 The stream disables the transfer with no later-on restart from the point where it was stopped. There is no particular action to do, except to clear the EN bit in the

DMA_SxCR register to disable the stream. The stream may take time to be disabled

(ongoing transfer is completed first). The transfer complete interrupt flag (TCIF in the

DMA_LISR or DMA_HISR register) is set in order to indicate the end of transfer. The value of the EN bit in DMA_SxCR is now 0 to confirm the stream interruption. The

DMA_SxNDTR register contains the number of remaining data items at the moment when the stream was stopped so that the software can determine how many data items have been transferred before the stream was interrupted.

 The stream suspends the transfer before the number of remaining data items to be transferred in the DMA_SxNDTR register reaches 0. The aim is to restart the transfer later by re-enabling the stream. In order to restart from the point where the transfer was stopped, the software has to read the DMA_SxNDTR register after disabling the stream by writing the EN bit in DMA_SxCR register (and then checking that it is at 0) to know the number of data items already collected. Then:

– The peripheral and/or memory addresses have to be updated in order to adjust the address pointers

– The SxNDTR register has to be updated with the remaining number of data items to be transferred (the value read when the stream was disabled)

– The stream may then be re-enabled to restart the transfer from the point it was stopped

A transfer complete interrupt flag (TCIF in DMA_LISR or DMA_HISR) is set to indicate the end of transfer due to the stream interruption.

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Note:

The entity that controls the number of data to be transferred is known as the flow controller.

This flow controller is configured independently for each stream using the PFCTRL bit in the

DMA_SxCR register.

The flow controller can be:

 The DMA controller: in this case, the number of data items to be transferred is programmed by software into the DMA_SxNDTR register before the DMA stream is enabled.

 The peripheral source or destination: this is the case when the number of data items to be transferred is unknown. The peripheral indicates by hardware to the DMA controller when the last data are being transferred. This feature is only supported for peripherals that are able to signal the end of the transfer, that is: SDIO.

When the peripheral flow controller is used for a given stream, the value written into the

DMA_SxNDTR has no effect on the DMA transfer. Actually, whatever the value written, it is forced by hardware to 0xFFFF as soon as the stream is enabled, to respect the following schemes:

 Anticipated stream interruption: EN bit in DMA_SxCR register is reset to 0 by the software to stop the stream before the last data hardware signal (single or burst) is sent by the peripheral. In such a case, the stream is switched off and the FIFO flush is triggered in the case of a peripheral-to-memory DMA transfer. The TCIFx flag of the corresponding stream is set in the status register to indicate the DMA completion. To know the number of data items transferred during the DMA transfer, read the

DMA_SxNDTR register and apply the following formula:

– Number_of_data_transferred = 0xFFFF – DMA_SxNDTR

 Normal stream interruption due to the reception of a last data hardware signal: the stream is automatically interrupted when the peripheral requests the last transfer

(single or burst) and when this transfer is complete. the TCIFx flag of the corresponding stream is set in the status register to indicate the DMA transfer completion. To know the number of data items transferred, read the DMA_SxNDTR register and apply the same formula as above.

 The DMA_SxNDTR register reaches 0: the TCIFx flag of the corresponding stream is set in the status register to indicate the forced DMA transfer completion. The stream is automatically switched off even though the last data hardware signal (single or burst) has not been yet asserted. The already transferred data is not lost. This means that a maximum of 65535 data items can be managed by the DMA in a single transaction, even in peripheral flow control mode.

When configured in memory-to-memory mode, the DMA is always the flow controller and the PFCTRL bit is forced to 0 by hardware.

The circular mode is forbidden in the peripheral flow controller mode.

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9.3.17 Summary of the possible DMA configurations

The table below summarizes the different possible DMA configurations. The forbidden configurations are highlighted in gray in the table.

Peripheral-tomemory

Memory-toperipheral

Memory-tomemory

DMA transfer mode

Source

AHB peripheral port

AHB memory port

Table 35. Possible DMA configurations

Destination

Flow controller

Circular mode

Transfer type

AHB peripheral port

AHB memory port

DMA

Peripheral Forbidden

DMA

Possible

Peripheral Forbidden

DMA only Forbidden single burst single burst single burst single burst single burst

Direct mode

Possible

Forbidden

Possible

Forbidden

Possible

Forbidden

Possible

Forbidden

Double- buffer mode

Possible

Forbidden

Possible

Forbidden

Forbidden Forbidden

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The following sequence must be followed to configure a DMA stream x (where x is the stream number):

If the stream is enabled, disable it by resetting the EN bit in the DMA_SxCR register, then read this bit in order to confirm that there is no ongoing stream operation. Writing this bit to 0 is not immediately effective since it is actually written to 0 once all the current transfers are finished. When the EN bit is read as 0, this means that the stream is ready to be configured. It is therefore necessary to wait for the EN bit to be cleared before starting any stream configuration. All the stream dedicated bits set in the status register (DMA_LISR and DMA_HISR) from the previous data block DMA transfer must be cleared before the stream can be re-enabled.

2. Set the peripheral port register address in the DMA_SxPAR register. The data is moved from/ to this address to/ from the peripheral port after the peripheral event.

3. Set the memory address in the DMA_SxMA0R register (and in the DMA_SxMA1R register in the case of a double-buffer mode). The data is written to or read from this memory after the peripheral event.

4. Configure the total number of data items to be transferred in the DMA_SxNDTR register. After each peripheral event or each beat of the burst, this value is decremented.

5. Select the DMA channel (request) using CHSEL[2:0] in the DMA_SxCR register.

6. If the peripheral is intended to be the flow controller and if it supports this feature, set the PFCTRL bit in the DMA_SxCR register.

7. Configure the stream priority using the PL[1:0] bits in the DMA_SxCR register.

8. Configure the FIFO usage (enable or disable, threshold in transmission and reception)

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9. Configure the data transfer direction, peripheral and memory incremented/fixed mode, single or burst transactions, peripheral and memory data widths, circular mode, double-buffer mode and interrupts after half and/or full transfer, and/or errors in the

DMA_SxCR register.

10. Activate the stream by setting the EN bit in the DMA_SxCR register.

As soon as the stream is enabled, it can serve any DMA request from the peripheral connected to the stream.

Once half the data have been transferred on the AHB destination port, the half-transfer flag

(HTIF) is set and an interrupt is generated if the half-transfer interrupt enable bit (HTIE) is set. At the end of the transfer, the transfer complete flag (TCIF) is set and an interrupt is generated if the transfer complete interrupt enable bit (TCIE) is set.

Warning: To switch off a peripheral connected to a DMA stream request, it is mandatory to, first, switch off the DMA stream to which the peripheral is connected, then to wait for EN bit = 0.

Only then can the peripheral be safely disabled.

The DMA controller can detect the following errors:

 Transfer error : the transfer error interrupt flag (TEIFx) is set when:

– a bus error occurs during a DMA read or a write access

– a write access is requested by software on a memory address register in double-buffer mode whereas the stream is enabled and the current target memory is the one impacted by the write into the memory address register (refer to

Section 9.3.10: Double-buffer mode

)

 FIFO error : the FIFO error interrupt flag (FEIFx) is set if:

– a FIFO underrun condition is detected

– a FIFO overrun condition is detected (no detection in memory-to-memory mode because requests and transfers are internally managed by the DMA)

– the stream is enabled while the FIFO threshold level is not compatible with the size of the memory burst (refer to

Table 34: FIFO threshold configurations

)

 Direct mode error : the direct mode error interrupt flag (DMEIFx) can only be set in the peripheral-to-memory mode while operating in direct mode and when the MINC bit in the DMA_SxCR register is cleared. This flag is set when a DMA request occurs while the previous data have not yet been fully transferred into the memory (because the memory bus was not granted). In this case, the flag indicates that two data items were be transferred successively to the same destination address, which could be an issue if the destination is not able to manage this situation

In direct mode, the FIFO error flag can also be set under the following conditions:

 In the peripheral-to-memory mode, the FIFO can be saturated (overrun) if the memory bus is not granted for several peripheral requests.

 In the memory-to-peripheral mode, an underrun condition may occur if the memory bus has not been granted before a peripheral request occurs.

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If the TEIFx or the FEIFx flag is set due to incompatibility between burst size and FIFO threshold level, the faulty stream is automatically disabled through a hardware clear of its

EN bit in the corresponding stream configuration register (DMA_SxCR).

If the DMEIFx or the FEIFx flag is set due to an overrun or underrun condition, the faulty stream is not automatically disabled and it is up to the software to disable or not the stream by resetting the EN bit in the DMA_SxCR register. This is because there is no data loss when this kind of errors occur.

When the stream's error interrupt flag (TEIF, FEIF, DMEIF) in the DMA_LISR or DMA_HISR register is set, an interrupt is generated if the corresponding interrupt enable bit (TEIE,

FEIE, DMIE) in the DMA_SxCR or DMA_SxFCR register is set.

When a FIFO overrun or underrun condition occurs, the data is not lost because the peripheral request is not acknowledged by the stream until the overrun or underrun condition is cleared. If this acknowledge takes too much time, the peripheral itself may detect an overrun or underrun condition of its internal buffer and data might be lost.

Note:

For each DMA stream, an interrupt can be produced on the following events:

 Half-transfer reached

 Transfer complete

 Transfer error

 FIFO error (overrun, underrun or FIFO level error)

 Direct mode error

Separate interrupt enable control bits are available for flexibility as shown in the table below.

Interrupt event

Half-transfer

Transfer complete

Transfer error

FIFO overrun/underrun

Direct mode error

Table 36. DMA interrupt requests

Event flag

HTIF

TCIF

TEIF

FEIF

DMEIF

Enable control bit

HTIE

TCIE

TEIE

FEIE

DMEIE

Before setting an enable control bit EN = 1, the corresponding event flag must be cleared, otherwise an interrupt is immediately generated.

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The DMA registers have to be accessed by words (32 bits).

9.5.1 DMA low interrupt status register (DMA_LISR)

Address offset: 0x000

Reset value: 0x0000 0000

Res.

29 28 27 26 25 24 23 22 21

Res.

TCIF3 HTIF3 TEIF3 DMEIF3 Res.

FEIF3 TCIF2 r r r r r r

13 12 11 10 9 8 7 6 5

Res.

TCIF1 HTIF1 TEIF1 DMEIF1 Res.

FEIF1 TCIF0 r r r r r r

20 19 18 17

HTIF2 TEIF2 DMEIF2 Res.

r r r

4 3 2 1

HTIF0 TEIF0 DMEIF0 Res.

r r r

FEIF2 r

FEIF0 r

Bits 31:28, 15:12 Reserved, must be kept at reset value.

Bits 27, 21, 11, 5 TCIF[3:0] : stream x transfer complete interrupt flag (x = 3 to 0)

This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the

DMA_LIFCR register.

0: no transfer complete event on stream x

1: a transfer complete event occurred on stream x

Bits 26, 20, 10, 4 HTIF[3:0] : stream x half transfer interrupt flag (x = 3 to 0)

This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the

DMA_LIFCR register.

0: no half transfer event on stream x

1: a half transfer event occurred on stream x

Bits 25, 19, 9, 3 TEIF[3:0] : stream x transfer error interrupt flag (x = 3 to 0)

This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the

DMA_LIFCR register.

0: no transfer error on stream x

1: a transfer error occurred on stream x

Bits 24, 18, 8, 2 DMEIF[3:0] : stream x direct mode error interrupt flag (x = 3 to 0)

This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the

DMA_LIFCR register.

0: No direct mode error on stream x

1: a direct mode error occurred on stream x

Bits 23, 17, 7, 1 Reserved, must be kept at reset value.

Bits 22, 16, 6, 0 FEIF[3:0] : stream x FIFO error interrupt flag (x = 3 to 0)

This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the

DMA_LIFCR register.

0: no FIFO error event on stream x

1: a FIFO error event occurred on stream x

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9.5.2 DMA high interrupt status register (DMA_HISR)

Address offset: 0x004

Reset value: 0x0000 0000

Res.

30 29

Res.

14 13

Res.

28 27 26 25 24 23 22 21 20 19 18 17

Res.

TCIF7 HTIF7 TEIF7 DMEIF7 Res.

FEIF7 TCIF6 HTIF6 TEIF6 DMEIF6 Res.

12 r

11 r

10 r

9 r

8 7 r

6 r

5 r

4 r

3 r

2 1

Res.

TCIF5 HTIF5 TEIF5 DMEIF5 Res.

FEIF5 TCIF4 HTIF4 TEIF4 DMEIF4 Res.

r r r r r r r r r

FEIF6 r

FEIF4 r

Bits 31:28, 15:12 Reserved, must be kept at reset value.

Bits 27, 21, 11, 5 TCIF[7:4] : stream x transfer complete interrupt flag (x = 7 to 4)

This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the

DMA_HIFCR register.

0: no transfer complete event on stream x

1: a transfer complete event occurred on stream x

Bits 26, 20, 10, 4 HTIF[7:4] : stream x half transfer interrupt flag (x = 7 to 4)

This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the

DMA_HIFCR register.

0: no half transfer event on stream x

1: a half transfer event occurred on stream x

Bits 25, 19, 9, 3 TEIF[7:4] : stream x transfer error interrupt flag (x = 7 to 4)

This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the

DMA_HIFCR register.

0: no transfer error on stream x

1: a transfer error occurred on stream x

Bits 24, 18, 8, 2 DMEIF[7:4] : stream x direct mode error interrupt flag (x = 7 to 4)

This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the

DMA_HIFCR register.

0: no direct mode error on stream x

1: a direct mode error occurred on stream x

Bits 23, 17, 7, 1 Reserved, must be kept at reset value.

Bits 22, 16, 6, 0 FEIF[7:4] : stream x FIFO error interrupt flag (x = 7 to 4)

This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the

DMA_HIFCR register.

0: no FIFO error event on stream x

1: a FIFO error event occurred on stream x

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9.5.3 DMA low interrupt flag clear register (DMA_LIFCR)

Address offset: 0x008

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res.

CTCIF3 CHTIF3 CTEIF3 CDMEIF3 Res.

CFEIF3 CTCIF2 CHTIF2 CTEIF2 CDMEIF2 Res.

CFEIF2

15 14 13 12 w

11 w

10 w

9 w

8 7 w

6 w

5 w

4 w

3 w

2 1 w

Res.

CTCIF1 CHTIF1 CTEIF1 CDMEIF1 Res.

CFEIF1 CTCIF0 CHTIF0 CTEIF0 CDMEIF0 Res.

CFEIF0 w w w w w w w w w w

Bits 31:28, 15:12 Reserved, must be kept at reset value.

Bits 27, 21, 11, 5 CTCIF[3:0] : stream x clear transfer complete interrupt flag (x = 3 to 0)

Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_LISR register.

Bits 26, 20, 10, 4 CHTIF[3:0] : stream x clear half transfer interrupt flag (x = 3 to 0)

Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_LISR register

Bits 25, 19, 9, 3 CTEIF[3:0] : Stream x clear transfer error interrupt flag (x = 3 to 0)

Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_LISR register.

Bits 24, 18, 8, 2 CDMEIF[3:0] : stream x clear direct mode error interrupt flag (x = 3 to 0)

Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_LISR register.

Bits 23, 17, 7, 1 Reserved, must be kept at reset value.

Bits 22, 16, 6, 0 CFEIF[3:0] : stream x clear FIFO error interrupt flag (x = 3 to 0)

Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_LISR register.

9.5.4 DMA high interrupt flag clear register (DMA_HIFCR)

Address offset: 0x00C

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24

Res. Res. Res. Res.

CTCIF7 CHTIF7 CTEIF7 CDMEIF7 w w w w

15 14 13 12 11 10 9 8

Res. Res. Res. Res.

CTCIF5 CHTIF5 CTEIF5 CDMEIF5 w w w w

23 22 21 20 19 18

Res.

CFEIF7 CTCIF6 CHTIF6 CTEIF6 CDMEIF6 w w w w w

7 6 5 4 3 2

Res.

CFEIF5 CTCIF4 CHTIF4 CTEIF4 CDMEIF4 w w w w w

Bits 31:28, 15:12 Reserved, must be kept at reset value.

Bits 27, 21, 11, 5 CTCIF[7:4] : stream x clear transfer complete interrupt flag (x = 7 to 4)

Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_HISR register.

Bits 26, 20, 10, 4 CHTIF[7:4] : stream x clear half transfer interrupt flag (x = 7 to 4)

Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_HISR register.

Bits 25, 19, 9, 3 CTEIF[7:4] : stream x clear transfer error interrupt flag (x = 7 to 4)

Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_HISR register.

Res.

CFEIF6 w

CFEIF4 w

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Bits 24, 18, 8, 2 CDMEIF[7:4] : stream x clear direct mode error interrupt flag (x = 7 to 4)

Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register.

Bits 23, 17, 7, 1 Reserved, must be kept at reset value.

Bits 22, 16, 6, 0 CFEIF[7:4] : stream x clear FIFO error interrupt flag (x = 7 to 4)

Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register.

9.5.5 DMA stream x configuration register (DMA_SxCR)

This register is used to configure the concerned stream.

Address offset: 0x010 + 0x018 * x, (x = 0 to 7)

Reset value: 0x0000 0000

Res.

PINCOS rw

30 29

Res.

14 rw

MSIZE[1:0] rw

Res.

27 rw

12 11

PSIZE[1:0] rw rw

CHSEL[2:0] rw

25 rw

MINC rw

PINC rw

24 23

MBURST [1:0] rw rw

CIRC rw

DIR[1:0] rw

6 rw

22 21

PBURST[1:0] rw rw

PFCTRL rw

Res.

TCIE rw

CT rw

HTIE rw

DBM rw

TEIE rw

17 16 rw

PL[1:0] rw

DMEIE rw

EN rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:25 CHSEL[2:0] : channel selection

These bits are set and cleared by software.

000: channel 0 selected

001: channel 1 selected

010: channel 2 selected

011: channel 3 selected

100: channel 4 selected

101: channel 5 selected

110: channel 6 selected

111: channel 7 selected

These bits are protected and can be written only if EN is 0.

Bits 24:23 MBURST[1:0] : memory burst transfer configuration

These bits are set and cleared by software.

00: single transfer

01: INCR4 (incremental burst of 4 beats)

10: INCR8 (incremental burst of 8 beats)

11: INCR16 (incremental burst of 16 beats)

These bits are protected and can be written only if EN = 0.

In direct mode, these bits are forced to 0x0 by hardware as soon as bit EN = 1.

Bits 22:21 PBURST[1:0] : peripheral burst transfer configuration

These bits are set and cleared by software.

00: single transfer

01: INCR4 (incremental burst of 4 beats)

10: INCR8 (incremental burst of 8 beats)

11: INCR16 (incremental burst of 16 beats)

These bits are protected and can be written only if EN = 0.

In direct mode, these bits are forced to 0x0 by hardware.

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RM0390 Direct memory access controller (DMA)

Bit 20 Reserved, must be kept at reset value.

Bit 19 CT : current target (only in double-buffer mode)

This bit is set and cleared by hardware. It can also be written by software.

0: current target memory is Memory 0 (addressed by the DMA_SxM0AR pointer)

1: current target memory is Memory 1 (addressed by the DMA_SxM1AR pointer)

This bit can be written only if EN = 0 to indicate the target memory area of the first transfer.

Once the stream is enabled, this bit operates as a status flag indicating which memory area is the current target.

Bit 18 DBM : double-buffer mode

This bit is set and cleared by software.

0: no buffer switching at the end of transfer

1: memory target switched at the end of the DMA transfer

This bit is protected and can be written only if EN = 0.

Bits 17:16 PL[1:0] : priority level

These bits are set and cleared by software.

00: low

01: medium

10: high

11: very high

These bits are protected and can be written only if EN = 0.

Bit 15 PINCOS : peripheral increment offset size

This bit is set and cleared by software

0: The offset size for the peripheral address calculation is linked to the PSIZE

1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment).

This bit has no meaning if bit PINC = 0.

This bit is protected and can be written only if EN = 0.

This bit is forced low by hardware when the stream is enabled (EN = 1) if the direct mode is selected or if PBURST are different from 00.

Bits 14:13 MSIZE[1:0] : memory data size

These bits are set and cleared by software.

00: byte (8-bit)

01: half-word (16-bit)

10: word (32-bit)

11: reserved

These bits are protected and can be written only if EN = 0.

In direct mode, MSIZE is forced by hardware to the same value as PSIZE as soon as

EN = 1.

Bits 12:11 PSIZE[1:0] : peripheral data size

These bits are set and cleared by software.

00: byte (8-bit)

01: half-word (16-bit)

10: word (32-bit)

11: reserved

These bits are protected and can be written only if EN = 0.

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Bit 10 MINC : memory increment mode

This bit is set and cleared by software.

0: memory address pointer is fixed

1: memory address pointer is incremented after each data transfer (increment is done according to MSIZE)

This bit is protected and can be written only if EN = 0.

Bit 9 PINC : peripheral increment mode

This bit is set and cleared by software.

0: peripheral address pointer fixed

1: peripheral address pointer incremented after each data transfer (increment done according to PSIZE)

This bit is protected and can be written only if EN = 0.

Bit 8 CIRC : circular mode

This bit is set and cleared by software and can be cleared by hardware.

0: circular mode disabled

1: circular mode enabled

When the peripheral is the flow controller (bit PFCTRL = 1) and the stream is enabled

(EN = 1), then this bit is automatically forced by hardware to 0.

It is automatically forced by hardware to 1 if the DBM bit is set, as soon as the stream is enabled (EN = 1).

Bits 7:6 DIR[1:0] : data transfer direction

These bits are set and cleared by software.

00: peripheral-to-memory

01: memory-to-peripheral

10: memory-to-memory

11: reserved

These bits are protected and can be written only if EN = 0.

Bit 5 PFCTRL : peripheral flow controller

This bit is set and cleared by software.

0: DMA is the flow controller.

1: The peripheral is the flow controller.

This bit is protected and can be written only if EN = 0.

When the memory-to-memory mode is selected (bits DIR[1:0]=10), then this bit is automatically forced to 0 by hardware.

Bit 4 TCIE : transfer complete interrupt enable

This bit is set and cleared by software.

0: TC interrupt disabled

1: TC interrupt enabled

Bit 3 HTIE : half transfer interrupt enable

This bit is set and cleared by software.

0: HT interrupt disabled

1: HT interrupt enabled

Bit 2 TEIE : transfer error interrupt enable

This bit is set and cleared by software.

0: TE interrupt disabled

1: TE interrupt enabled

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RM0390 Direct memory access controller (DMA)

Bit 1 DMEIE : direct mode error interrupt enable

This bit is set and cleared by software.

0: DME interrupt disabled

1: DME interrupt enabled

Bit 0 EN : stream enable / flag stream ready when read low

This bit is set and cleared by software.

0: stream disabled

1: stream enabled

This bit may be cleared by hardware:

– on a DMA end of transfer (stream ready to be configured)

– if a transfer error occurs on the AHB master buses

– when the FIFO threshold on memory AHB port is not compatible with the size of the burst

When this bit is read as 0, the software is allowed to program the configuration and FIFO bits registers. It is forbidden to write these registers when the EN bit is read as 1.

Note: Before setting EN bit to 1 to start a new transfer, the event flags corresponding to the stream in DMA_LISR or DMA_HISR register must be cleared.

9.5.6

Res.

DMA stream x number of data register (DMA_SxNDTR)

Address offset: 0x014 + 0x018 * x, (x = 0 to 7)

Reset value: 0x0000 0000

Res.

15 rw

14 rw

13 rw

12 rw

11 rw

10 rw

9 rw

8 7

NDT[15:0] rw rw

6 rw

5 rw

4 rw

3 rw

2 rw

1 rw

0 rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 NDT[15:0] : number of data items to transfer (0 up to 65535)

This register can be written only when the stream is disabled. When the stream is enabled, this register is read-only, indicating the remaining data items to be transmitted. This register decrements after each DMA transfer.

Once the transfer is completed, this register can either stay at zero (when the stream is in normal mode) or be reloaded automatically with the previously programmed value in the following cases:

– when the stream is configured in circular mode.

– when the stream is enabled again by setting EN bit to 1.

If the value of this register is zero, no transaction can be served even if the stream is enabled.

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9.5.7

31 rw

15 rw

DMA stream x peripheral address register (DMA_SxPAR)

Address offset: 0x018 + 0x018 * x, (x = 0 to 7)

Reset value: 0x0000 0000

30 29 rw

14 rw

28 rw

27 rw

26 rw

25 rw

24 23

PAR[31:16] rw

8 rw

PAR[15:0] rw rw

22 rw

21 rw

20 rw

19 rw

18 rw

17 rw

1 rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 PAR[31:0] : peripheral address

Base address of the peripheral data register from/to which the data is read/written.

These bits are write-protected and can be written only when bit EN = 0 in DMA_SxCR.

16 rw

0 rw

9.5.8

31 rw

15 rw

DMA stream x memory 0 address register

(DMA_SxM0AR)

Address offset: 0x01C + 0x018 * x, (x = 0 to 7)

Reset value: 0x0000 0000

30 29 rw

14 rw

28 rw

27 rw

26 rw

25 rw

24 23

M0A[31:16] rw rw

8 7

M0A[15:0] rw rw

22 rw

21 rw

20 rw

19 rw

18 rw

17 rw

1 rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 M0A[31:0] : memory 0 address

Base address of memory area 0 from/to which the data is read/written.

These bits are write-protected. They can be written only if:

– the stream is disabled (EN = 0 in DMA_SxCR) or

– the stream is enabled (EN = 1 in DMA_SxCR) and CT = 1 in DMA_SxCR (in double-buffer mode).

16 rw

0 rw

9.5.9

31 rw

15 rw

DMA stream x memory 1 address register

(DMA_SxM1AR)

Address offset: 0x020 + 0x018 * x, (x = 0 to 7)

Reset value: 0x0000 0000

30 29 28 27 26 25 22 rw

14 rw rw

13 rw rw

12 rw rw

11 rw rw

10 rw rw

9 rw

24 23

M1A[31:16] rw rw

8 7

M1A[15:0] rw rw rw

6 rw

21 rw

5 rw

20 rw

4 rw

19 rw

3 rw

18 rw

2 rw

17 rw

1 rw

16 rw

0 rw

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RM0390 Direct memory access controller (DMA)

Bits 31:0 M1A[31:0] : memory 1 address (used in case of double-buffer mode)

Base address of memory area 1 from/to which the data is read/written.

This register is used only for the double-buffer mode.

These bits are write-protected. They can be written only if:

– the stream is disabled (EN = 0 in DMA_SxCR) or

– the stream is enabled (EN = 1 in DMA_SxCR) and bit CT = 0 in DMA_SxCR .

Address offset: 0x024 + 0x018 * x, (x = 0 to 7)

Reset value: 0x0000 0021

Res.

28 27

Res.

12 11

Res.

FEIE rw

Res.

5 r

FS[2:0] r

3 2

DMDIS rw

1 0 rw

FTH[1:0] rw r

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 FEIE : FIFO error interrupt enable

This bit is set and cleared by software.

0: FE interrupt disabled

1: FE interrupt enabled

Bit 6 Reserved, must be kept at reset value.

Bits 5:3 FS[2:0] : FIFO status

These bits are read-only.

000: 0 < fifo_level < 1/4

001: 1/4 ≤ fifo_level < 1/2

010: 1/2 ≤ fifo_level < 3/4

011: 3/4 ≤ fifo_level < full

100: FIFO is empty

101: FIFO is full others: no meaning

These bits are not relevant in the direct mode (DMDIS = 0).

Bit 2 DMDIS : direct mode disable

This bit is set and cleared by software. It can be set by hardware.

0: direct mode enabled

1: direct mode disabled

This bit is protected and can be written only if EN = 0.

This bit is set by hardware if the memory-to-memory mode is selected (DIR bit in

DMA_SxCR are 10) and the EN = 1 in DMA_SxCR because the direct mode is not allowed in the memory-to-memory configuration.

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Direct memory access controller (DMA)

Bits 1:0 FTH[1:0] : FIFO threshold selection

These bits are set and cleared by software.

00: 1/4 full FIFO

01: 1/2 full FIFO

10: 3/4 full FIFO

11: full FIFO

These bits are not used in the direct mode when the DMIS = 0.

These bits are protected and can be written only if EN = 0.

RM0390

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RM0390 Direct memory access controller (DMA)

Offset Register name

0x000

0x004

DMA_LISR

Reset value

DMA_HISR

Reset value

0x008

DMA_LIFCR

Reset value

0x00C

DMA_HIFCR

Reset value

Table 37. DMA register map and reset values

0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x010

DMA_S0CR

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x014

DMA_S0NDTR

Reset value

0x018

DMA_S0PAR

Reset value

NDT[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x01C

DMA_S0M0AR

Reset value

M0A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M1A[31:0]

0x020

DMA_S0M1AR

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x024

DMA_S0FCR

Reset value 0

FS[2:0]

1 0 0 0 0 1

DMA_S1CR

0x008

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x02C

DMA_S1NDTR

0x030

Reset value

DMA_S1PAR

Reset value

NDT[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Table 37. DMA register map and reset values (continued)

Offset Register name

0x034

DMA_S1M0AR

Reset value

M0A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M1A[31:0]

0x038

DMA_S1M1AR

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x03C

DMA_S1FCR

Reset value 0

FS[2:0]

1 0 0 0 0 1

DMA_S2CR

0x040

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x044

DMA_S2NDTR

0x048

Reset value

DMA_S2PAR

Reset value

NDT[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x04C

DMA_S2M0AR

Reset value

M0A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x050

DMA_S2M1AR

Reset value

M1A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x054

DMA_S2FCR

Reset value 0

FS[2:0]

1 0 0 0 0 1

DMA_S3CR

0x058

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x05C

DMA_S3NDTR

0x060

Reset value

DMA_S3PAR

Reset value

NDT[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x064

DMA_S3M0AR

Reset value

M0A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x068

DMA_S3M1AR

Reset value

M1A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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RM0390

Offset Register name

Direct memory access controller (DMA)

Table 37. DMA register map and reset values (continued)

0x06C

DMA_S3FCR

Reset value 0

FS[2:0]

1 0 0 0 0 1

0x070

DMA_S4CR

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x074

DMA_S4NDTR

Reset value

DMA_S4PAR

0x078

0x07C

Reset value

DMA_S4M0AR

Reset value

0x080

DMA_S4M1AR

Reset value

PA[31:0]

0 0 0 0 0

NDT[15:0]

0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M0A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M1A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x084

DMA_S4FCR

Reset value 0

FS[2:0]

1 0 0 0 0 1

0x088

DMA_S5CR

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x08C

DMA_S5NDTR

Reset value

DMA_S5PAR

0x090

0x094

Reset value

DMA_S5M0AR

Reset value

0x098

DMA_S5M1AR

Reset value

PA[31:0]

0 0 0 0 0

NDT[15:0]

0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M0A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M1A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x09C

DMA_S5FCR

Reset value 0

FS[2:0]

1 0 0 0 0 1

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Table 37. DMA register map and reset values (continued)

Offset Register name

RM0390

DMA_S6CR

0x0A0

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0A4

DMA_S6NDTR

0x0A8

Reset value

DMA_S6PAR

Reset value

NDT[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0AC

DMA_S6M0AR

Reset value

M0A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M1A[31:0]

0x0B0

DMA_S6M1AR

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0B4

DMA_S6FCR

Reset value 0

FS[2:0]

1 0 0 0 0 1

DMA_S7CR

0x0B8

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0BC

DMA_S7NDTR

0x0C0

Reset value

DMA_S7PAR

Reset value

NDT[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0C4

DMA_S7M0AR

Reset value

M0A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0C8

DMA_S7M1AR

Reset value

M1A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0CC

DMA_S7FCR

Reset value 0

FS[2:0]

1 0 0 0 0 1

Refer to Section 2.2

for the register boundary addresses.

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10 Interrupts and events

10.1 Nested vectored interrupt controller (NVIC)

Interrupts and events

The nested vector interrupt controller NVIC includes the following features:

 96 maskable interrupt channels (not including the 16 interrupt lines of Cortex ® -M4 with

FPU)

 16 programmable priority levels (4 bits of interrupt priority are used)

 low-latency exception and interrupt handling

 power management control

 implementation of system control registers

The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts.

All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to programming manual PM0214.

The SysTick calibration value is fixed to 18750, which gives a reference time base of 1 ms with the SysTick clock set to 18.75 MHz (HCLK/8, with HCLK set to 150 MHz).

10.1.3 Interrupt and exception vectors

See

Table 38 for the vector table.

The external interrupt/event controller consists of up to 23 edge detectors for generating event/interrupt requests. Each input line can be independently configured to select the type

(interrupt or event) and the corresponding trigger event (rising or falling or both). Each line can also masked independently. A pending register maintains the status line of the interrupt requests.

Table 38. Vector table for STM32F446xx

Type of priority

Acronym Description Address

-3

-2

-1

fixed fixed fixed

0 settable

Reset

NMI

HardFault

MemManage

Reserved 0x0000 0000

Reset 0x0000 0004

Non maskable interrupt, Clock Security System 0x0000 0008

All class of fault 0x0000 000C

Memory management 0x0000 0010

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Type of priority

1 settable

2 settable

3 settable

4 settable

5 settable

6 settable

7 settable

8 settable

9 settable

10 settable

11 settable

12 settable

13 settable

14 settable

16 settable settable

10 17 settable

11 18 settable

12 19 settable

13 20 settable

14 21 settable

15 22 settable

16 23 settable

17 24 settable

18 25 settable

19 26 settable

20 27 settable

21 28 settable

22 29 settable

23 30 settable

Table 38. Vector table for STM32F446xx (continued)

Acronym Description

BusFault

UsageFault

SVCall

Debug Monitor

PendSV

Systick

WWDG

PVD

TAMP_STAMP

RTC_WKUP

FLASH

RCC

EXTI0

EXTI1

EXTI2

EXTI3

EXTI4

DMA1_Stream0

DMA1_Stream1

DMA1_Stream2

DMA1_Stream3

DMA1_Stream4

DMA1_Stream5

DMA1_Stream6

ADC

CAN1_TX

CAN1_RX0

CAN1_RX1

CAN1_SCE

EXTI9_5

Address

Pre-fetch fault, memory access fault

Undefined instruction or illegal state

Reserved

System Service call via SWI instruction

Debug Monitor

Reserved

Pendable request for system service

System tick timer

Window Watchdog interrupt

PVD through EXTI line detection interrupt

Tamper and TimeStamp interrupts through the EXTI line

0x0000 0014

0x0000 0018

0x0000 001C -

0x0000 002B

0x0000 002C

0x0000 0030

0x0000 0034

0x0000 0038

0x0000 003C

0x0000 0040

0x0000 0044

0x0000 0048

RTC Wakeup interrupt through the EXTI line 0x0000 004C

Flash global interrupt 0x0000 0050

RCC global interrupt 0x0000 0054

EXTI Line0 interrupt

EXTI Line1 interrupt

EXTI Line2 interrupt

EXTI Line3 interrupt

EXTI Line4 interrupt

0x0000 0058

0x0000 005C

0x0000 0060

0x0000 0064

0x0000 0068

DMA1 Stream0 global interrupt

DMA1 Stream1 global interrupt

DMA1 Stream2 global interrupt

DMA1 Stream3 global interrupt

DMA1 Stream4 global interrupt

DMA1 Stream5 global interrupt

0x0000 006C

0x0000 0070

0x0000 0074

0x0000 0078

0x0000 007C

0x0000 0080

DMA1 Stream6 global interrupt

ADC1, ADC2 and ADC3 global interrupts

CAN1 TX interrupts

CAN1 RX0 interrupts

CAN1 RX1 interrupt

CAN1 SCE interrupt

EXTI Line[9:5] interrupts

0x0000 0084

0x0000 0088

0x0000 008C

0x0000 0090

0x0000 0094

0x0000 0098

0x0000 009C

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Table 38. Vector table for STM32F446xx (continued)

Type of priority

Acronym Description Address

26 33 settable TIM1_TRG_COM_TIM11

28 35 settable

29 36 settable

31 38 settable

32 39 settable

34 41 settable

35 42 settable

37 44 settable

38 45 settable

39 46 settable

47 settable settable settable settable settable

TIM1_CC

TIM2

TIM3

TIM4

I2C1_EV

I2C1_ER

I2C2_EV

I2C2_ER

SPI1

SPI2

USART1

USART2

USART3

EXTI15_10

45 52 settable TIM8_TRG_COM_TIM14

57 settable settable settable settable settable settable settable

47 54 settable

48 55 settable

49 56 settable settable

51 58 settable

52 59 settable

TIM1_BRK_TIM9

TIM1_UP_TIM10

RTC_Alarm

OTG_FS WKUP

TIM8_BRK_TIM12

TIM8_UP_TIM13

TIM8_CC

DMA1_Stream7

FMC

SDIO

TIM5

SPI3

UART4

TIM1 Break interrupt and TIM9 global interrupt

TIM1 Update interrupt and TIM10 global interrupt

TIM1 Trigger and Commutation interrupts and TIM11 global interrupt

TIM1 Capture compare interrupt

TIM2 global interrupt

TIM3 global interrupt

TIM4 global interrupt

C1 event interrupt

C1 error interrupt

C2 event interrupt

C2 error interrupt

SPI1 global interrupt

SPI2 global interrupt

USART1 global interrupt

USART2 global interrupt

USART3 global interrupt

EXTI Line[15:10] interrupts

RTC Alarms (A and B) through EXTI line interrupt

0x0000 00A0

0x0000 00A4

0x0000 00A8

0x0000 00AC

0x0000 00B0

0x0000 00B4

0x0000 00B8

0x0000 00BC

0x0000 00C0

0x0000 00C4

0x0000 00C8

0x0000 00CC

0x0000 00D0

0x0000 00D4

0x0000 00D8

0x0000 00DC

0x0000 00E0

0x0000 00E4

USB On-The-Go FS Wakeup through EXTI line interrupt

0x0000 00E8

TIM8 break interrupt and TIM12 global interrupt 0x0000 00EC

TIM8 Update interrupt and TIM13 global interrupt

0x0000 00F0

TIM8 Trigger and Commutation interrupts and TIM14 global interrupt

TIM8 Capture compare interrupt

DMA1 Stream7 global interrupt

FMC global interrupt

SDIO global interrupt

TIM5 global interrupt

SPI3 global interrupt

UART4 global interrupt

0x0000 00F4

0x0000 00F8

0x0000 00FC

0x0000 0100

0x0000 0104

0x0000 0108

0x0000 010C

0x0000 0110

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Table 38. Vector table for STM32F446xx (continued)

Type of priority

53 60 settable

54 61 settable

55 62 settable

56 63 settable

57 64 settable

58 65 settable

59 66 settable

60 67 settable

61 68 -

62 69 -

63 70 settable

64 71 settable

65 72 settable

66 73 settable

67 74 settable

68 75 settable

69 76 settable

70 77 settable

71 78 settable

72 79 settable

73 80 settable

74 81 settable

Acronym

UART5

TIM6_DAC

TIM7

DMA2_Stream0

DMA2_Stream1

DMA2_Stream2

DMA2_Stream3

DMA2_Stream4

CAN2_TX

CAN2_RX0

CAN2_RX1

CAN2_SCE

OTG_FS

DMA2_Stream5

DMA2_Stream6

DMA2_Stream7

USART6

I2C3_EV

I2C3_ER

OTG_HS_EP1_OUT

75 82 settable

76 83 settable

77 84 settable

78 85 settable

79 86

80 87

81 88 settable

82 89

83 90 -

OTG_HS_EP1_IN

OTG_HS_WKUP

OTG_HS

DCMI

FPU

Description

UART5 global interrupt

TIM6 global interrupt,

DAC1 and DAC2 underrun error interrupts

TIM7 global interrupt

DMA2 Stream0 global interrupt

DMA2 Stream1 global interrupt

DMA2 Stream2 global interrupt

DMA2 Stream3 global interrupt

DMA2 Stream4 global interrupt

Reserved

CAN2 TX interrupts

CAN2 RX0 interrupts

CAN2 RX1 interrupt

CAN2 SCE interrupt

USB On The Go FS global interrupt

DMA2 Stream5 global interrupt

DMA2 Stream6 global interrupt

DMA2 Stream7 global interrupt

USART6 global interrupt

I 2 C3 event interrupt

C3 error interrupt

USB On The Go HS End Point 1 Out global interrupt

USB On The Go HS End Point 1 In global interrupt

USB On The Go HS Wakeup through EXTI interrupt

USB On The Go HS global interrupt

DCMI global interrupt

Reserved

FPU global interrupt

Reserved

RM0390

Address

0x0000 0114

0x0000 0118

0x0000 011C

0x0000 0120

0x0000 0124

0x0000 0128

0x0000 012C

0x0000 0130

0x0000 0134

0x0000 0138

0x0000 013C

0x0000 0140

0x0000 0144

0x0000 0148

0x0000 014C

0x0000 0150

0x0000 0154

0x0000 0158

0x0000 015C

0x0000 0160

0x0000 0164

0x0000 0168

0x0000 016C

0x0000 0170

0x0000 0174

0x0000 0178

0x0000 017C

0x0000 0180

0x0000 0184

0x0000 0188

0x0000 018C

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Type of priority

84 91 settable

85 92

86 93

87 94 settable

88 95

89 96

90 97

91 98 settable

92 99 settable

93 100 settable

94 101 settable

95 102 settable

96 103 settable

Table 38. Vector table for STM32F446xx (continued)

Acronym Description

SPI4

SAI1

SAI2

QuadSPI

HDMI-CEC

SPDIF-Rx

FMPI2C1

FMPI2C1 error

SPI 4 global interrupt

Reserved

SAI1 global interrupt

Reserved

SAI2 global interrupt

QuadSPI global interrupt

HDMI-CEC global interrupt

SPDIF-Rx global interrupt

FMPI2C1 event interrupt

FMPI2C1 error interrupt

Interrupts and events

Address

0x0000 0190

0x0000 0194

0x0000 0198

0x0000 019C

0x0000 01A0

0x0000 01A4

0x0000 01A8

0x0000 01AC

0x0000 01B0

0x0000 01B4

0x0000 01B8

0x0000 01BC

0x0000 01C0

10.2.1 EXTI main features

The main features of the EXTI controller are the following:

 independent trigger and mask on each interrupt/event line

 dedicated status bit for each interrupt line

 generation of up to 23 software event/interrupt requests

 detection of external signals with a pulse width lower than the APB2 clock period. Refer to the electrical characteristics section of the STM32F446xx datasheets for details on this parameter.

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Figure 30

shows the block diagram.

Figure 30. External interrupt/event controller block diagram

AMBA APB bus

PCLK2 Peripheral interface

23 23 23 23 23

To NVIC interrupt controller

Pending request register

Interrupt mask register

Software interrupt event register

Rising trigger selection register

Falling trigger selection register

23 23

Pulse generator 23 23

Edge detect circuit

Event mask register

Input line

MS32662V1

The STM32F446xx microcontrollers are able to handle external or internal events in order to wake up the core (WFE). The wakeup event can be generated either by:

 enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex ® -M4 with FPU System Control register. When the

MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC

IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.

 or configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC

IRQ channel pending bit as the pending bit corresponding to the event line is not set.

To use an external line as a wakeup event, refer to

Section 10.2.4

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To generate the interrupt, the interrupt line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register.

When the selected edge occurs on the external interrupt line, an interrupt request is

RM0390 Rev 6

RM0390 Interrupts and events generated. The pending bit corresponding to the interrupt line is also set. This request is reset by writing a ‘1’ in the pending register.

To generate the event, the event line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a ‘1’ to the corresponding bit in the event mask register. When the selected edge occurs on the event line, an event pulse is generated. The pending bit corresponding to the event line is not set.

An interrupt/event request can also be generated by software by writing a ‘1’ in the software interrupt/event register.

Hardware interrupt selection

To configure the 23 lines as interrupt sources, use the following procedure:

 Configure the mask bits of the 23 interrupt lines (EXTI_IMR)

 Configure the Trigger selection bits of the interrupt lines (EXTI_RTSR and EXTI_FTSR)

 Configure the enable and mask bits that control the NVIC IRQ channel mapped to the external interrupt controller (EXTI) so that an interrupt coming from one of the 23 lines can be correctly acknowledged.

Hardware event selection

To configure the 23 lines as event sources, use the following procedure:

 Configure the mask bits of the 23 event lines (EXTI_EMR)

 Configure the Trigger selection bits of the event lines (EXTI_RTSR and EXTI_FTSR)

Software interrupt/event selection

The 23 lines can be configured as software interrupt/event lines. The following is the procedure to generate a software interrupt.

 Configure the mask bits of the 23 interrupt/event lines (EXTI_IMR, EXTI_EMR)

 Set the required bit in the software interrupt register (EXTI_SWIER)

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Up to 114 GPIOs are connected to the 16 external interrupt/event lines in the following manner:

Figure 31. External interrupt/event GPIO mapping

EXTI0[3:0] bits in the SYSCFG_EXTICR1 register

PA0

PB0

PC0

PD0

PE0

PF0

PG0

PH0

EXTI0

EXTI1[3:0] bits in the SYSCFG_EXTICR1 register

PA1

PB1

PC1

PD1

PE1

PF1

PG1

PH1

EXTI1

EXTI15[3:0] bits in the SYSCFG_EXTICR4 register

PA15

PB15

PC15

PD15

PE15

PF15

PG15

EXTI15

MS35851V1

The seven other EXTI lines are connected as follows:

 EXTI line 16 is connected to the PVD output

 EXTI line 17 is connected to the RTC Alarm event

 EXTI line 18 is connected to the USB OTG FS Wakeup event

 EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event

 EXTI line 21 is connected to the RTC Tamper and TimeStamp events

 EXTI line 22 is connected to the RTC Wakeup event

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10.3

EXTI

registers

Refer to Section 1.2 on page 51 for a list of abbreviations used in register descriptions.

10.3.1 Interrupt mask register (EXTI_IMR)

Address offset: 0x00

Reset value: 0x0000 0000

Res.

15 14 13 12 11 10

MR15 MR14 MR13 MR12 MR11 MR10 rw rw rw rw rw rw

Res.

MR9 rw

Res.

MR8 rw

23 22 21 20 19 18 17 16

Res.

MR22 MR21 MR20 MR19 MR18 MR17 MR16 rw rw rw rw rw rw rw

MR7 rw

MR6 rw

MR5 rw

MR4 rw

MR3 rw

MR2 rw

MR1 rw

MR0 rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 MRx: Interrupt mask on line x

0: Interrupt request from line x is masked

1: Interrupt request from line x is not masked

Res.

Address offset: 0x04

Reset value: 0x0000 0000

Res.

15 14 13 12 11 10

MR15 MR14 MR13 MR12 MR11 MR10 rw rw rw rw rw rw

MR9 rw

Res.

MR8 rw

23 22 21 20 19 18 17 16

Res.

MR22 MR21 MR20 MR19 MR18 MR17 MR16

7 rw

6 rw

5 rw

4 rw

3 rw

2 rw

1 rw

MR7 rw

MR6 rw

MR5 rw

MR4 rw

MR3 rw

MR2 rw

MR1 rw

MR0 rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 MRx: Event mask on line x

0: Event request from line x is masked

1: Event request from line x is not masked

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Res.

Note:

Address offset: 0x08

Reset value: 0x0000 0000

Res.

15 14 13 12 11 10

TR15 TR14 TR13 TR12 TR11 TR10 rw rw rw rw rw rw

Res.

TR9 rw

Res.

TR8 rw

Res.

TR7 rw

22 21 20

TR22 TR21 TR20 rw

6 rw

5 rw

TR6 rw

TR5 rw

TR4 rw

Res.

TR3 rw

TR18 rw

TR2 rw

TR17 rw

TR1 rw

TR16 rw

TR0 rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:20 TRx: Rising trigger event configuration bit of line x

0: Rising trigger disabled (for Event and Interrupt) for input line

1: Rising trigger enabled (for Event and Interrupt) for input line

Bit 19 Reserved, must be kept at reset value.

Bits 18:0 TRx: Rising trigger event configuration bit of line x

0: Rising trigger disabled (for Event and Interrupt) for input line

1: Rising trigger enabled (for Event and Interrupt) for input line

The external wakeup lines are edge triggered, no glitch must be generated on these lines.

If a rising edge occurs on the external interrupt line while writing to the EXTI_RTSR register, the pending bit is be set.

Rising and falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition.

Address offset: 0x0C

Reset value: 0x0000 0000

Res.

15 14 13 12 11 10

TR15 TR14 TR13 TR12 TR11 TR10 rw rw rw rw rw rw

Res.

TR9 rw

Res.

TR8 rw

Res.

TR7 rw

22 21 20

TR22 TR21 TR20 rw rw rw

TR6 rw

TR5 rw

TR4 rw

Res.

TR3 rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:20 TRx: Falling trigger event configuration bit of line x

0: Falling trigger disabled (for Event and Interrupt) for input line

1: Falling trigger enabled (for Event and Interrupt) for input line.

Bit 19 Reserved, must be kept at reset value.

Bits 18:0 TRx: Falling trigger event configuration bit of line x

0: Falling trigger disabled (for Event and Interrupt) for input line

1: Falling trigger enabled (for Event and Interrupt) for input line.

TR18 rw

TR2 rw

TR17 rw

TR1 rw

TR16 rw

TR0 rw

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Interrupts and events

The external wakeup lines are edge triggered, no glitch must be generated on these lines.

If a falling edge occurs on the external interrupt line while writing to the EXTI_FTSR register, the pending bit is not set.

Rising and falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition.

Address offset: 0x10

Reset value: 0x0000 0000

Res.

SWIER

15 rw

SWIER

14 rw

SWIER

13 rw

SWIER

12 rw

SWIER

11 rw

SWIER

10 rw

SWIER

9 rw

Res.

SWIER

8 rw

Res.

SWIER

7 rw

SWIER

22 rw

SWIER

21 rw

SWIER

6 rw

SWIER

5 rw

SWIER

20 rw

SWIER

4 rw

SWIER

19 rw

SWIER

18 rw

SWIER

3 rw

SWIER

2 rw

SWIER

17 rw

SWIER

1 rw

SWIER

16 rw

SWIER

0 rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 SWIERx: Software Interrupt on line x

If interrupt are enabled on line x in the EXTI_IMR register, writing '1' to SWIERx bit when it is set at '0' sets the corresponding pending bit in the EXTI_PR register, thus resulting in an interrupt request generation.

This bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to the bit).

10.3.6 Pending register (EXTI_PR)

Address offset: 0x14

Reset value: undefined

Res.

22 21 20 19 18

PR22 PR21 PR20 PR19 PR18

PR17

PR16 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7

PR15 PR14 PR13 PR12 PR11 PR10 PR9 PR8 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 PRx: Pending bit on line x

0: No trigger request occurred

1: selected trigger request occurred

This bit is set when the selected edge event arrives on the external interrupt line.

This bit is cleared by programming it to ‘1’.

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10.3.7 EXTI register map

Table 39 gives the EXTI register map and the reset values.

Table 39. External interrupt/event controller register map and reset values

RM0390

Offset Register

0x00

0x04

0x08

0x0C

0x10

0x14

EXTI_IMR

Reset value

EXTI_EMR

Reset value

EXTI_RTSR

Reset value

EXTI_FTSR

Reset value

EXTI_SWIER

Reset value

EXTI_PR

Reset value

MR[22:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MR[22:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TR[22:0] TR[22:0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TR[22:0]

0 0 0

TR[22:0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SWIER[22:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PR[22:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 56 for the register boundary addresses.

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11

Flexible memory controller (FMC)

Flexible memory controller (FMC)

11.1 Introduction

The flexible memory controller (FMC) includes three memory controllers:

 The NOR/PSRAM memory controller

 The NAND memory controller

 The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller

11.2 FMC main features

The FMC functional block makes the interface with: synchronous and asynchronous static memories, SDRAM memories, and NAND Flash memory. Its main purposes are:

 to translate AHB transactions into the appropriate external device protocol

 to meet the access time requirements of the external memory devices

All external memories share the addresses, data and control signals with the controller.

Each external device is accessed by means of a unique chip select. The FMC performs only one access at a time to an external device.

The main features of the FMC controller are the following:

 Interface with static-memory mapped devices including:

– Static random access memory (SRAM)

– NOR Flash memory/OneNAND Flash memory

– PSRAM (4 memory banks)

– NAND Flash memory with ECC hardware to check up to 8 Kbytes of data

 Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories

 Interface with parallel LCD modules, supporting Intel 8080 and Motorola 6800 modes.

 Burst mode support for faster access to synchronous devices such as NOR Flash memory, PSRAM and SDRAM)

 Programmable continuous clock output for asynchronous and synchronous accesses

 8-,16-bit wide data bus

 Independent chip select control for each memory bank

 Independent configuration for each memory bank

 Write enable and byte lane select outputs for use with PSRAM, SRAM and SDRAM devices

 External asynchronous wait control

 Write FIFO with 16 x32-bit depth

 Cacheable Read FIFO with 6 x32-bit depth (6 x14-bit address tag) for SDRAM controller.

The Write FIFO is common to all memory controllers and consists of:

 a Write Data FIFO which stores the AHB data to be written to the memory (up to 32 bits) plus one bit for the AHB transfer (burst or not sequential mode)

 a Write Address FIFO which stores the AHB address (up to 28 bits) plus the AHB data size (up to 2 bits). When operating in burst mode, only the start address is stored

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Flexible memory controller (FMC) RM0390 except when crossing a page boundary (for PSRAM and SDRAM). In this case, the

AHB burst is broken into two FIFO entries.

The Write FIFO can be disabled by setting the WFDIS bit in the FMC_BCR1 register.

At startup the FMC pins must be configured by the user application. The FMC I/O pins which are not used by the application can be used for other purposes.

The FMC registers that define the external device type and associated characteristics are usually set at boot time and do not change until the next reset or power-up. However, the settings can be changed at any time.

11.3 FMC block diagram

The FMC consists of the following main blocks:

 The AHB interface (including the FMC configuration registers)

 The NOR Flash/PSRAM/SRAM controller

 The SDRAM controller

 The external device interface

The block diagram is shown in the figure below.

Figure 32. FMC block diagram

FMC interrupts to NVIC

From clock controller

HCLK

NOR/PSRAM memory controller

Configuration registers

NAND memory controller

SDRAM controller

FMC_NL (or NADV)

FMC_CLK

NOR/PSRAM signals

FMC_NBL[1:0]

NOR / PSRAM / SRAM shared signals

FMC_A[25:0]

FMC_D[15:0]

Shared signals

FMC_NE[4:1]

FMC_NOE

FMC_NWE

FMC_NWAIT

FMC_NCE

FMC_INT

NOR / PSRAM / SRAM shared signals

NAND signals

FMC_SDCLK

FMC_SDNWE

FMC_SDCKE[1:0]

FMC_SDNE[1:0]

FMC_NRAS

FMC_NCAS

SDRAM signals

MS34471V3

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The AHB slave interface allows internal CPUs and other bus master peripherals to access the external memories.

AHB transactions are translated into the external device protocol. In particular, if the selected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split into consecutive 16- or 8-bit accesses. The FMC chip select (FMC_NEx) does not toggle between the consecutive accesses except in case of Access mode D when the Extended mode is enabled.

The FMC generates an AHB error in the following conditions:

 When reading or writing to an FMC bank (Bank 1 to 4) which is not enabled.

 When reading or writing to the NOR Flash bank while the FACCEN bit is reset in the

FMC_BCRx register.

 When writing to a write protected SDRAM bank (WP bit set in the SDRAM_SDCRx register).

 When the SDRAM address range is violated (access to reserved address range)

The effect of an AHB error depends on the AHB master which has attempted the R/W access:

 If the access has been attempted by the Cortex ® -M4 with FPU CPU, a hard fault interrupt is generated.

 If the access has been performed by a DMA controller, a DMA transfer error is generated and the corresponding DMA channel is automatically disabled.

The AHB clock (HCLK) is the reference clock for the FMC.

General transaction rules

The requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the accessed external device has a fixed data width. This may lead to inconsistent transfers.

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Therefore, some simple transaction rules must be followed:

 AHB transaction size and memory data size are equal

There is no issue in this case.

 AHB transaction size is greater than the memory size:

In this case, the FMC splits the AHB transaction into smaller consecutive memory accesses to meet the external data width. The FMC chip select (FMC_NEx) does not toggle between the consecutive accesses.

 AHB transaction size is smaller than the memory size:

The transfer may or not be consistent depending on the type of external device:

– Accesses to devices that have the byte select feature (SRAM, ROM, PSRAM,

SDRAM)

In this case, the FMC allows read/write transactions and accesses the right data through its byte lanes NBL[1:0].

Bytes to be written are addressed by NBL[1:0].

All memory bytes are read (NBL[1:0] are driven low during read transaction) and the useless ones are discarded.

– Accesses to devices that do not have the byte select feature (NOR and NAND

Flash memories)

This situation occurs when a byte access is requested to a 16-bit wide Flash memory. Since the device cannot be accessed in Byte mode (only 16-bit words can be read/written from/to the Flash memory), Write transactions and Read transactions are allowed (the controller reads the entire 16-bit memory word and uses only the required byte).

Wrap support for NOR Flash/PSRAM and SDRAM

Wrap burst mode for synchronous memories is not supported. The memories must be configured in Linear burst mode of undefined length.

Configuration registers

The FMC can be configured through a set of registers. Refer to Section 11.6.6

, for a detailed

description of the NOR Flash/PSRAM controller registers. Refer to Section 11.7.7

, for a

detailed description of the NAND Flash registers and to

Section 11.8.5

for a detailed

description of the SDRAM controller registers.

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11.5 External device address mapping

From the FMC point of view, the external memory is divided into fixed-size banks of

256 Mbytes each (see

Figure 33 ):

 Bank 1 used to address up to 4 NOR Flash memory or PSRAM devices. This bank is split into 4 NOR/PSRAM subbanks with 4 dedicated chip selects, as follows:

– Bank 1 - NOR/PSRAM 1

– Bank 1 - NOR/PSRAM 2

– Bank 1 - NOR/PSRAM 3

– Bank 1 - NOR/PSRAM 4

 Bank 3 used to address NAND Flash memory devices.The MPU memory attribute for this space must be reconfigured by software to Device.

 Bank 4 and 5 used to address SDRAM devices (1 device per bank).

For each bank the type of memory to be used can be configured by the user application through the Configuration register.

Figure 33. FMC memory banks

Address

0x6000 0000

Bank

Bank 1

4 x 64 MB

Supported memory type

NOR/PSRAM/

SRAM

0x6FFF FFFF

0x7000 0000

Bank 2

Not used

0x7FFF FFFF

0x8000 0000

Bank 3

4 x 64 MB

NAND Flash memory

0x8FFF FFFF

0x9000 0000

Bank 4

Not used

0x9FFF FFFF

0xC000 0000

SDRAM Bank 1

4 x 64 MB

0xCFFF FFFF

0xD000 0000

SDRAM

SDRAM Bank 2

4 x 64 MB

0xDFFF FFFF

MSv30444V5

HADDR[27:26] bits are used to select one of the four memory banks as shown in

Table 40 .

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Table 40. NOR/PSRAM bank selection

HADDR[27:26]

(1)

Selected bank

Bank 1 - NOR/PSRAM 1

Bank 1 - NOR/PSRAM 2

Bank 1 - NOR/PSRAM 3

Bank 1 - NOR/PSRAM 4

1. HADDR are internal AHB address lines that are translated to external memory.

The HADDR[25:0] bits contain the external memory address. Since HADDR is a byte address whereas the memory is addressed at word level, the address actually issued to the memory varies according to the memory data width, as shown in the following table.

Memory width

(1)

Table 41. NOR/PSRAM External memory address

Data address issued to the memory Maximum memory capacity (bits)

8-bit

16-bit

HADDR[25:0]

HADDR[25:1] >> 1

64 Mbytes x 8 = 512 Mbit

64 Mbytes/2 x 16 = 512 Mbit

1. In case of a 16-bit external memory width, the FMC internally uses HADDR[25:1] to generate the address for external memory FMC_A[24:0].

Whatever the external memory width, FMC_A[0] should be connected to external memory address A[0].

The NAND bank is divided into memory areas as indicated in Table 42

Table 42. NAND memory mapping and timing registers

Start address End address FMC bank Memory space Timing register

0x8800 0000 0x8BFF FFFF

0x8000 0000 0x83FF FFFF

Bank 3 - NAND Flash

Attribute

Common

FMC_PATT (0x8C)

FMC_PMEM (0x88)

For NAND Flash memory, the common and attribute memory spaces are subdivided into three sections (see in

Table 43 below) located in the lower 256 Kbytes:

 Data section (first 64 Kbytes in the common/attribute memory space)

 Command section (second 64 Kbytes in the common / attribute memory space)

 Address section (next 128 Kbytes in the common / attribute memory space)

Section name

Address section

Command section

Data section

Table 43. NAND bank selection

HADDR[17:16]

Address range

0x020000-0x03FFFF

0x010000-0x01FFFF

0x000000-0x0FFFF

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The application software uses the 3 sections to access the NAND Flash memory:

 To sending a command to NAND Flash memory , the software must write the command value to any memory location in the command section.

 To specify the NAND Flash address that must be read or written , the software must write the address value to any memory location in the address section. Since an address can be 4 or 5 bytes long (depending on the actual memory size), several consecutive write operations to the address section are required to specify the full address.

 To read or write data, the software reads or writes the data from/to any memory location in the data section.

Since the NAND Flash memory automatically increments addresses, there is no need to increment the address of the data section to access consecutive memory locations.

11.5.3 SDRAM address mapping

The HADDR[28] bit (internal AHB address line 28) is used to select one of the two memory

banks as indicated in Table 44

HADDR[28]

Table 44. SDRAM bank selection

Selected bank Control register

SDRAM Bank1

SDRAM Bank2

FMC_SDCR1

FMC_SDCR2

Timing register

FMC_SDTR1

FMC_SDTR2

The following table shows SDRAM mapping for a 13-bit row, a 11-bit column and a 4 internal bank configuration.

Table 45. SDRAM address mapping

Memory width

(1)

Internal bank Row address

Column address

(2)

Maximum memory capacity

(Mbytes)

8-bit

16-bit

HADDR[25:24]

HADDR[26:25]

HADDR[23:11]

HADDR[24:12]

HADDR[10:0]

HADDR[11:1]

64 Mbytes:

4 x 8K x 2K

128 Mbytes:

4 x 8K x 2K x 2

1. When interfacing with a 16-bit memory, the FMC internally uses the HADDR[11:1] internal AHB address lines to generate the external address. Whatever the memory width, FMC_A[0] has to be connected to the external memory address A[0].

2. The AutoPrecharge is not supported. FMC_A[10] must be connected to the external memory address

A[10] but it will be always driven ‘low’.

The HADDR[27:0] bits are translated to external SDRAM address depending on the

SDRAM controller configuration:

 Data size:8 or 16 bits

 Row size:11, 12 or 13 bits

 Column size: 8, 9, 10 or 11 bits

 Number of internal banks: two or four internal banks

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The following tables show the SDRAM address mapping versus the SDRAM controller configuration.

Table 46. SDRAM address mapping with 8-bit data bus width (1)(2)

HADDR(AHB Internal Address Lines)

Row size configuration

27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

11-bit row size configuration

12-bit row size configuration

13-bit row size configuration

Res.

Bank

[1:0]

Bank

[1:0]

Bank

[1:0]

Bank

[1:0]

Res.

Bank

[1:0]

Bank

[1:0]

Res.

Bank

[1:0]

Bank

[1:0]

Bank

[1:0]

Res.

Bank

[1:0]

Bank

[1:0]

Bank

[1:0]

Row[10:0]

Row[11:0]

Row[12:0]

Row[10:0]

Row[12:0]

Column[7:0]

Column[8:0]

Column[9:0]

Column[10:0]

Column[7:0]

Column[8:0]

Column[9:0]

Column[10:0]

Column[7:0]

Column[8:0]

Column[9:0]

Column[10:0]

1. BANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be set to ‘0’.

2. Access to Reserved (Res.) address range generates an AHB error.

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Row size

Configuration

Table 47. SDRAM address mapping with 16-bit data bus width (1)(2)

HADDR(AHB address Lines)

11-bit row size configuration

12-bit row size configuration

13-bit row size configuration

Res.

Bank

[1:0]

Res.

[1:0]

Bank

Res.

Bank

[1:0]

Res.

[1:0]

Res.

Bank

[1:0]

Bank

Res.

Bank

[1:0]

Res.

[1:0]

Bank

Res.

[1:0]

Res.

Bank

[1:0]

Res.

[1:0]

Bank

Res.

[1:0]

Bank s.

[1:0]

Row[10:0]

Row[11:0]

Row[10:0]

Row[12:0]

Row[11:0]

Row[12:0]

Row[10:0]

Row[12:0]

Column[7:0]

Column[8:0]

Column[9:0]

Column[10:0]

Column[7:0]

Column[8:0]

Column[9:0]

Column[10:0]

Column[7:0]

Column[8:0]

Column[9:0]

Column[10:0]

1. BANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be set to ‘0’.

2. Access to Reserved space (Res.) generates an AHB error.

3. BM0: is the byte mask for 16-bit access.

BM0

(3)

BM0

11.6 NOR Flash/PSRAM controller

The FMC generates the appropriate signal timings to drive the following types of memories:

 Asynchronous SRAM and ROM

– 8 bits

– 16 bits

 PSRAM (CellularRAM™)

– Asynchronous mode

– Burst mode for synchronous accesses

– Multiplexed or non-multiplexed

 NOR Flash memory

– Asynchronous mode

– Burst mode for synchronous accesses

– Multiplexed or non-multiplexed

The FMC outputs a unique chip select signal, NE[4:1], per bank. All the other signals

(addresses, data and control) are shared.

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The FMC supports a wide range of devices through a programmable timings among which:

 Programmable wait states (up to 15)

 Programmable bus turnaround cycles (up to 15)

 Programmable output enable and write enable delays (up to 15)

 Independent read and write timings and protocol to support the widest variety of memories and timings

 Programmable continuous clock (FMC_CLK) output.

The FMC Clock (FMC_CLK) is a submultiple of the HCLK clock. It can be delivered to the selected external device either during synchronous accesses only or during asynchronous and synchronous accesses depending on the CCKEN bit configuration in the FMC_BCR1 register:

 If the CCLKEN bit is reset, the FMC generates the clock (CLK) only during synchronous accesses (Read/write transactions).

 If the CCLKEN bit is set, the FMC generates a continuous clock during asynchronous and synchronous accesses. To generate the FMC_CLK continuous clock, Bank 1 must

be configured in Synchronous mode (see Section 11.6.6: NOR/PSRAM controller registers

). Since the same clock is used for all synchronous memories, when a continuous output clock is generated and synchronous accesses are performed, the

AHB data size has to be the same as the memory data width (MWID) otherwise the

FMC_CLK frequency is changed depending on AHB data transaction (refer to

Section 11.6.5: Synchronous transactions

for FMC_CLK divider ratio formula).

The size of each bank is fixed and equal to 64 Mbytes. Each bank is configured through dedicated registers (see

Section 11.6.6: NOR/PSRAM controller registers

The programmable memory parameters include access times (see

Table 48 ) and support

for wait management (for PSRAM and NOR Flash accessed in Burst mode).

Table 48. Programmable NOR/PSRAM access parameters

Address setup

Address hold

Data setup

Bust turn

Clock divide ratio

Data latency

Duration of the address setup phase

Duration of the address hold phase

Duration of the data setup phase

Duration of the bus turnaround phase

Asynchronous

Asynchronous, muxed I/Os

Asynchronous

AHB clock cycle

(HCLK)

AHB clock cycle

(HCLK)

AHB clock cycle

(HCLK)

Asynchronous and synchronous read

/ write

AHB clock cycle

(HCLK)

Number of AHB clock cycles

(HCLK) to build one memory clock cycle (CLK)

Number of clock cycles to issue to the memory before the first data of the burst

Synchronous

AHB clock cycle

(HCLK)

Memory clock cycle (CLK)

256

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11.6.1 External memory interface signals

Note:

Table 49 , Table 50 and

Table 51 list the signals that are typically used to interface with NOR

Flash memory, SRAM and PSRAM.

The prefix “N” identifies the signals that are active low.

NOR Flash memory, non-multiplexed I/Os

Table 49. Non-multiplexed I/O NOR Flash memory

FMC signal name I/O Function

CLK O Clock (for synchronous access)

D[15:0]

NE[x]

NOE

NWE

NL(=NADV)

NWAIT

I/O

Bidirectional data bus

Chip select, x = 1..4

Latch enable (this signal is called address valid, NADV, by some NOR Flash devices)

NOR Flash wait input signal to the FMC

The maximum capacity is 512 Mbits (26 address lines).

NOR Flash memory, 16-bit multiplexed I/Os

Table 50. 16-bit multiplexed I/O NOR Flash memory

FMC signal name I/O Function

CLK O

A[25:16] O

Clock (for synchronous access)

A[15:0] and data D[15:0] are multiplexed on the databus)

Chip select, x = 1..4

NE[x]

NOE

NWE

NL(=NADV)

NWAIT

Latch enable (this signal is called address valid, NADV, by some NOR

Flash devices)

NOR Flash wait input signal to the FMC

The maximum capacity is 512 Mbits.

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PSRAM/SRAM, non-multiplexed I/Os

Table 51. Non-multiplexed I/Os PSRAM/SRAM

FMC signal name I/O Function

CLK O Clock (only for PSRAM synchronous access)

A[25:0] O

D[15:0]

NE[x]

NOE

I/O Data bidirectional bus

O Chip select, x = 1..4 (called NCE by PSRAM (CellularRAM™ i.e. CRAM))

NWE

NL(= NADV)

NWAIT

NBL[1:0]

Address valid only for PSRAM input (memory signal name: NADV)

PSRAM wait input signal to the FMC

O Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable)

The maximum capacity is 512 Mbits.

PSRAM, 16-bit multiplexed I/Os

FMC signal name I/O

Table 52. 16-Bit multiplexed I/O PSRAM

Function

CLK O

A[25:16] O

Clock (for synchronous access)

AD[15:0] I/O

NE[x]

16-bit multiplexed, bidirectional address/data bus (the 16-bit address

A[15:0] and data D[15:0] are multiplexed on the databus)

O Chip select, x = 1..4 (called NCE by PSRAM (CellularRAM™ i.e. CRAM))

NOE

NWE

NL(= NADV)

NWAIT

NBL[1:0]

Address valid PSRAM input (memory signal name: NADV)

PSRAM wait input signal to the FMC

O Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable)

The maximum capacity is 512 Mbits (26 address lines).

Table 53 below shows an example of the supported devices, access modes and

transactions when the memory data bus is 16-bit wide for NOR Flash memory, PSRAM and

SRAM. The transactions not allowed (or not supported) by the FMC are shown in gray in this example.

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Device

Table 53. NOR Flash/PSRAM: example of supported memories and transactions

Mode R/W

AHB data size

Memory data size

Allowed/ not allowed

Comments

Asynchronous R 8 16 Y

Asynchronous W 8 16 N

Asynchronous R 16 16 Y

Asynchronous W 16 16 Y

NOR Flash

(muxed I/Os and nonmuxed

I/Os)

Asynchronous R 32

Asynchronous W 32

Asynchronous page

Synchronous R

Y Split into 2 FMC accesses

Split into 2 FMC accesses

Mode is not supported

Synchronous R 16

Synchronous R 32

Asynchronous R 8 16 Y

PSRAM

(multiplexed

I/Os and nonmultiplexed

I/Os)

SRAM and

ROM

Asynchronous W 8

Asynchronous

Asynchronous R

Asynchronous W

Asynchronous page

Synchronous R

R 16 16

W 16 16

Use

Y Split into 2 FMC accesses

Mode is not supported

Synchronous R 16

Synchronous R 32

Synchronous W 8

Synchronous W 16/32

Asynchronous R

Asynchronous W

Asynchronous R

Asynchronous W

8 / 16

Use of byte lanes NBL[1:0]

Split into 2 FMC accesses

Use of byte lanes NBL[1:0]

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11.6.3 General timing rules

Signals synchronization

 All controller output signals change on the rising edge of the internal clock (HCLK)

 In Synchronous mode (read or write), all output signals change on the rising edge of

HCLK. Whatever the CLKDIV value, all outputs change as follows:

– NOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the falling edge of FMC_CLK clock.

– NOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising edge of FMC_CLK clock.

11.6.4 NOR Flash/PSRAM controller asynchronous transactions

Asynchronous static memories (NOR Flash, PSRAM, SRAM)

 Signals are synchronized by the internal clock HCLK. This clock is not issued to the memory

 The FMC always samples the data before de-asserting the NOE signal. This guarantees that the memory data hold timing constraint is met (minimum Chip Enable high to data transition is usually 0 ns)

 If the Extended mode is enabled (EXTMOD bit is set in the FMC_BCRx register), up to four extended modes (A, B, C and D) are available. It is possible to mix A, B, C and D modes for read and write operations. For example, read operation can be performed in mode A and write in mode B.

 If the Extended mode is disabled (EXTMOD bit is reset in the FMC_BCRx register), the

FMC can operate in mode 1 or mode 2 as follows:

– Mode 1 is the default mode when SRAM/PSRAM memory type is selected (MTYP

= 0x0 or 0x01 in the FMC_BCRx register)

– Mode 2 is the default mode when NOR memory type is selected (MTYP = 0x10 in the FMC_BCRx register).

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Mode 1 - SRAM/PSRAM (CRAM)

The next figures show the read and write transactions for the supported modes followed by the required configuration of FMC_BCRx, and FMC_BTRx/FMC_BWTRx registers.

Figure 34. Mode 1 read access waveforms

Memory transaction

A[25:0]

NBL[1:0]

NEx

NOE

NWE

High

D[15:0]

ADDSET

HCLK cycles data driven by memory

DATAST

HCLK cycles

MS34477V1

Figure 35. Mode 1 write access waveforms

Memory transaction

A[25:0]

NBL[1:0]

NEx

NOE

NWE

1HCLK

D[15:0]

ADDSET

HCLK cycles data driven by FMC

(DATAST + 1)

HCLK cycles

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The one HCLK cycle at the end of the write transaction helps guarantee the address and data hold time after the NWE rising edge. Due to the presence of this HCLK cycle, the

DATAST value must be greater than zero (DATAST > 0).

Bit number

Table 54. FMC_BCRx bitfields (mode 1)

Bit name Value to set

31:22

18:16

Reserved

WFDIS

0x000

As needed

CCLKEN As needed

CBURSTRW 0x0 (no effect in Asynchronous mode)

CPSIZE 0x0 (no effect in Asynchronous mode)

ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.

EXTMOD

WAITEN

WREN

0x0

0x0 (no effect in Asynchronous mode)

As needed

Reserved

WAITPOL

8 BURSTEN

7 Reserved

6 FACCEN

0x0

Meaningful only if bit 15 is 1

0x0

0x1

5:4 MWID

3:2 MTYP

1 MUXE

As needed, exclude 0x2 (NOR Flash memory)

0x0

Bit number

31:30

29:28

27:24

23:20

19:16

15:8

7:4

3:0

Bit name

Table 55. FMC_BTRx bitfields (mode 1)

Value to set

Reserved

ACCMOD

DATLAT

0x0

Don’t care

CLKDIV Don’t care

BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).

DATAST

ADDHLD

ADDSET

Duration of the second access phase (DATAST+1 HCLK cycles for write accesses, DATAST HCLK cycles for read accesses).

Don’t care

Duration of the first access phase (ADDSET HCLK cycles).

Minimum value for ADDSET is 0.

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Mode A - SRAM/PSRAM (CRAM) OE toggling

Figure 36. Mode A read access waveforms

Memory transaction

A[25:0]

NBL[1:0]

NEx

NOE

NWE

High

D[15:0]

ADDSET

HCLK cycles data driven by memory

DATAST

HCLK cycles

MS34479V1

1. NBL[1:0] are driven low during the read access

Figure 37. Mode A write access waveforms

Memory transaction

A[25:0]

NBL[1:0]

NEx

NOE

NWE

1HCLK

D[15:0]

ADDSET

HCLK cycles data driven by FMC

(DATAST + 1)

HCLK cycles

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The differences compared with Mode 1 are the toggling of NOE and the independent read and write timings.

Bit number

Table 56. FMC_BCRx bitfields (mode A)

Bit name Value to set

31:22

18:16

14 EXTMOD

13 WAITEN

CPSIZE 0x0 (no effect in Asynchronous mode)

ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.

WREN

0x1

0x0 (no effect in Asynchronous mode)

As needed

Reserved

WFDIS

0x000

As needed

CCLKEN As needed

CBURSTRW 0x0 (no effect in Asynchronous mode)

WAITCFG

Reserved

WAITPOL

8 BURSTEN

7 Reserved

6 FACCEN

Don’t care

0x0

Meaningful only if bit 15 is 1

0x0

0x1

3:2 MTYP

1 MUXEN

0 MBKEN

As needed, exclude 0x2 (NOR Flash memory)

0x0

0x1

Bit number Bit name

Table 57. FMC_BTRx bitfields (mode A)

Value to set

31:30

29:28

27:24

23:20

19:16

15:8

7:4

3:0

Reserved 0x0

ACCMOD 0x0

DATLAT Don’t care

CLKDIV Don’t care

BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).

DATAST

Duration of the second access phase (DATAST HCLK cycles) for read accesses.

ADDHLD Don’t care

ADDSET

Duration of the first access phase (ADDSET HCLK cycles) for read accesses.

Minimum value for ADDSET is 0.

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Bit number Bit name

Table 58. FMC_BWTRx bitfields (mode A)

Value to set

31:30

29:28

27:24

23:20

19:16

15:8

7:4

3:0

Reserved 0x0

ACCMOD 0x0

DATLAT

CLKDIV

Don’t care

BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).

DATAST

Duration of the second access phase (DATAST HCLK cycles) for write accesses.

ADDHLD Don’t care

ADDSET

Duration of the first access phase (ADDSET HCLK cycles) for write accesses.

Minimum value for ADDSET is 0.

Mode 2/B - NOR Flash

Figure 38. Mode 2 and mode B read access waveforms

Memory transaction

A[25:0]

NADV

NEx

NOE

NWE

High

D[15:0]

ADDSET

HCLK cycles data driven by memory

DATAST

HCLK cycles

MS34481V2

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Figure 39. Mode 2 write access waveforms

Memory transaction

A[25:0]

NADV

NEx

NOE

NWE

1HCLK

RM0390

A[25:0]

NADV

NEx

NOE

NWE

D[15:0]

ADDSET

HCLK cycles data driven by FMC

(DATAST + 1)

HCLK cycles

Figure 40. Mode B write access waveforms

Memory transaction

1HCLK

MS34482V2

D[15:0]

ADDSET

HCLK cycles data driven by FMC

(DATAST + 1)

HCLK cycles

MS34483V1

The differences with mode 1 are the toggling of NWE and the independent read and write timings when extended mode is set (mode B).

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Bit number

Table 59. FMC_BCRx bitfields (mode 2/B)

Bit name Value to set

31:22

18:16

Reserved

WFDIS

0x000

As needed

CCLKEN As needed

CBURSTRW 0x0 (no effect in Asynchronous mode)

CPSIZE 0x0 (no effect in Asynchronous mode)

ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.

EXTMOD

WAITEN

0x1 for mode B, 0x0 for mode 2

0x0 (no effect in Asynchronous mode)

WREN

WAITCFG

Reserved

9 WAITPOL

8 BURSTEN

7 Reserved

6 FACCEN

As needed

Don’t care

0x0

Meaningful only if bit 15 is 1

0x0

0x1

3:2 MTYP

1 MUXEN

0 MBKEN

0x2 (NOR Flash memory)

0x0

0x1

Bit number

31:30

29:28

27:24

23:20

19:16

15:8

7:4

3:0

Table 60. FMC_BTRx bitfields (mode 2/B)

Bit name Value to set

Reserved 0x0

ACCMOD 0x1 if Extended mode is set

DATLAT

CLKDIV

Don’t care

BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).

DATAST

ADDHLD

ADDSET

Duration of the access second phase (DATAST HCLK cycles) for read accesses.

Don’t care

Duration of the access first phase (ADDSET HCLK cycles) for read accesses. Minimum value for ADDSET is 0.

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Bit number

31:30

29:28

27:24

23:20

19:16

15:8

7:4

3:0

Table 61. FMC_BWTRx bitfields (mode 2/B)

Bit name Value to set

Reserved 0x0

ACCMOD 0x1 if Extended mode is set

DATLAT

CLKDIV

Don’t care

BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).

DATAST

ADDHLD

Duration of the access second phase (DATAST HCLK cycles) for write accesses.

Don’t care

ADDSET

Duration of the access first phase (ADDSET HCLK cycles) for write accesses. Minimum value for ADDSET is 0.

Note: The FMC_BWTRx register is valid only if the Extended mode is set (mode B), otherwise its content is don’t care.

Mode C - NOR Flash - OE toggling

Figure 41. Mode C read access waveforms

Memory transaction

A[25:0]

NADV

NEx

NOE

NWE

High

D[15:0]

ADDSET

HCLK cycles data driven by memory

DATAST

HCLK cycles

MS34484V1

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Figure 42. Mode C write access waveforms

Memory transaction

A[25:0]

NADV

NEx

NOE

NWE

1HCLK

D[15:0] data driven by FMC

ADDSET

HCLK cycles

(DATAST + 1)

HCLK cycles

MSv40166V1

The differences compared with mode 1 are the toggling of NOE and the independent read and write timings.

Bit number

Table 62. FMC_BCRx bitfields (mode C)

Bit name Value to set

31:22

Reserved

WFDIS

CCLKEN

0x000

As needed

18:16

CBURSTRW 0x0 (no effect in Asynchronous mode)

CPSIZE 0x0 (no effect in Asynchronous mode)

15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.

14 EXTMOD 0x1

WAITEN

WREN

WAITCFG

Reserved

0x0 (no effect in Asynchronous mode)

As needed

Don’t care

0x0

9 WAITPOL Meaningful only if bit 15 is 1

8 BURSTEN 0x0

7 Reserved

6 FACCEN

0x1

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Bit number

Table 62. FMC_BCRx bitfields (mode C) (continued)

Bit name

3:2 MTYP

1 MUXEN

0 MBKEN

0x02 (NOR Flash memory)

0x0

0x1

Value to set

RM0390

Bit number

31:30

29:28

27:24

23:20

19:16

15:8

7:4

3:0

Table 63. FMC_BTRx bitfields (mode C)

Bit name Value to set

Reserved

ACCMOD

DATLAT

0x0

0x2

0x0

CLKDIV 0x0

BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).

DATAST

ADDHLD

ADDSET

Duration of the second access phase (DATAST HCLK cycles) for read accesses.

Don’t care

Duration of the first access phase (ADDSET HCLK cycles) for read accesses. Minimum value for ADDSET is 0.

Bit number

31:30

29:28

27:24

23:20

19:16

15:8

7:4

3:0

Table 64. FMC_BWTRx bitfields (mode C)

Bit name Value to set

Reserved 0x0

ACCMOD 0x2

DATLAT

CLKDIV

Don’t care

BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).

DATAST

ADDHLD

ADDSET

Duration of the second access phase (DATAST HCLK cycles) for write accesses.

Don’t care

Duration of the first access phase (ADDSET HCLK cycles) for write accesses. Minimum value for ADDSET is 0.

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Mode D - asynchronous access with extended address

Figure 43. Mode D read access waveforms

Memory transaction

A[25:0]

NADV

NEx

NOE

NWE

High

D[15:0]

ADDSET

HCLK cycles

ADDHLD

HCLK cycles data driven by memory

DATAST

HCLK cycles

Figure 44. Mode D write access waveforms

Memory transaction

A[25:0]

NADV

MS34486V1

NEx

NOE

NWE

1HCLK

D[15:0]

ADDSET

HCLK cycles

ADDHLD

HCLK cycles data driven by FMC

(DATAST+ 1)

HCLK cycles

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The differences with mode 1 are the toggling of NOE that goes on toggling after NADV changes and the independent read and write timings.

Bit number

Table 65. FMC_BCRx bitfields (mode D)

Bit name Value to set

31:22

18:16

Reserved

WFDIS

0x000

As needed

CCLKEN As needed

CBURSTRW 0x0 (no effect in Asynchronous mode)

CPSIZE 0x0 (no effect in Asynchronous mode)

ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.

EXTMOD

WAITEN

WREN

0x1

0x0 (no effect in Asynchronous mode)

As needed

WAITCFG

Reserved

WAITPOL

BURSTEN

Reserved

FACCEN

Don’t care

0x0

Meaningful only if bit 15 is 1

0x0

0x1

Set according to memory support

As needed 5:4 MWID

3:2 MTYP

1 MUXEN

0 MBKEN

0x0

0x1

Bit number

31:30

29:28

27:24

23:20

19:16

15:8

7:4

3:0

Bit name

Table 66. FMC_BTRx bitfields (mode D)

Value to set

Reserved 0x0

ACCMOD 0x3

DATLAT Don’t care

CLKDIV Don’t care

BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).

DATAST

ADDHLD

ADDSET

Duration of the second access phase (DATAST HCLK cycles) for read accesses.

Duration of the middle phase of the read access (ADDHLD HCLK cycles)

Duration of the first access phase (ADDSET HCLK cycles) for read accesses. Minimum value for ADDSET is 1.

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Bit number

31:30

29:28

27:24

23:20

19:16

15:8

7:4

3:0

Table 67. FMC_BWTRx bitfields (mode D)

Bit name Value to set

Reserved

ACCMOD

DATLAT

CLKDIV

0x0

0x3

Don’t care

BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).

DATAST

Duration of the second access phase (DATAST + 1 HCLK cycles) for write accesses.

ADDHLD

ADDSET

Duration of the middle phase of the write access (ADDHLD HCLK cycles)

Duration of the first access phase (ADDSET HCLK cycles) for write accesses. Minimum value for ADDSET is 1.

Muxed mode - multiplexed asynchronous access to NOR Flash memory

Figure 45. Muxed read access waveforms

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Figure 46. Muxed write access waveforms

Memory transaction

A[25:16]

RM0390

NADV

NEx

NOE

NWE

1HCLK

AD[15:0] Lower address data driven by FMC

ADDSET

HCLK cycles

ADDHLD

HCLK cycles

(DATAST + 1)

HCLK cycles

MS39905V2

The difference with mode D is the drive of the lower address byte(s) on the data bus.

Bit number

Table 68. FMC_BCRx bitfields (Muxed mode)

Bit name Value to set

31:22

Reserved

WFDIS

CCLKEN

0x000

As needed

18:16

CBURSTRW

CPSIZE

0x0 (no effect in Asynchronous mode)

15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.

14 EXTMOD 0x0

WAITEN

WREN

WAITCFG

Reserved

9 WAITPOL

8 BURSTEN

7 Reserved

6 FACCEN

0x0 (no effect in Asynchronous mode)

As needed

Don’t care

0x0

Meaningful only if bit 15 is 1

0x0

0x1

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Bit number

Table 68. FMC_BCRx bitfields (Muxed mode) (continued)

Bit name

3:2 MTYP

1 MUXEN

0 MBKEN

Value to set

0x2 (NOR Flash memory) or 0x1(PSRAM)

0x1

Bit number

31:30

29:28

27:24

23:20

19:16

15:8

7:4

3:0

Table 69. FMC_BTRx bitfields (Muxed mode)

Bit name Value to set

Reserved 0x0

ACCMOD 0x0

DATLAT Don’t care

CLKDIV Don’t care

BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).

DATAST

ADDHLD

ADDSET

Duration of the second access phase (DATAST HCLK cycles for read accesses and DATAST+1 HCLK cycles for write accesses).

Duration of the middle phase of the access (ADDHLD HCLK cycles).

Duration of the first access phase (ADDSET HCLK cycles). Minimum value for ADDSET is 1.

WAIT management in asynchronous accesses

If the asynchronous memory asserts the WAIT signal to indicate that it is not yet ready to accept or to provide data, the ASYNCWAIT bit has to be set in FMC_BCRx register.

If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access phase (Data setup phase), programmed by the DATAST bits, is extended until WAIT becomes inactive. Unlike the data setup phase, the first access phases (Address setup and

Address hold phases), programmed by the ADDSET and ADDHLD bits, are not WAIT sensitive and so they are not prolonged.

The data setup phase must be programmed so that WAIT can be detected 4 HCLK cycles before the end of the memory transaction. The following cases must be considered:

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The memory asserts the WAIT signal aligned to NOE/NWE which toggles:

DATAST   4 HCLK  + max_wait_assertion_time

2. The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling): if then:

DATAST   4 HCLK  +

 max_wait_assertion_time

–

address_phase

–

hold_phase

 otherwise where max_wait_assertion_time is the maximum time taken by the memory to assert the WAIT signal once NEx/NOE/NWE is low.

Figure 47

and Figure 48

show the number of HCLK clock cycles that are added to the memory access phase after WAIT is released by the asynchronous memory (independently of the above cases).

Figure 47. Asynchronous wait during a read access waveforms

Memory transaction

A[25:0] address phase data setup phase

NEx don’t care NWAIT

NOE don’t care

D[15:0] data driven by memory

4HCLK

MS30463V2

1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register.

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A[25:0]

Flexible memory controller (FMC)

Figure 48. Asynchronous wait during a write access waveforms

Memory transaction address phase data setup phase

NEx

NWAIT don’t care don’t care

1HCLK

NWE

D[15:0] data driven by FMC

3HCLK

1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register.

MSv40168V1

The memory clock, FMC_CLK, is a submultiple of HCLK. It depends on the value of

CLKDIV and the MWID/ AHB data size, following the formula given below:

FMC_CLK divider ratio = ( ,   )

Whatever MWID size: 16 or 8-bit, the FMC_CLK divider ratio is always defined by the programmed CLKDIV value.

Example:

 If CLKDIV=1, MWID = 16 bits, AHB data size=8 bits, FMC_CLK=HCLK/2.

NOR Flash memories specify a minimum time from NADV assertion to CLK high. To meet this constraint, the FMC does not issue the clock to the memory during the first internal clock cycle of the synchronous access (before NADV assertion). This guarantees that the rising edge of the memory clock occurs in the middle of the NADV low pulse.

Data latency versus NOR memory latency

The data latency is the number of cycles to wait before sampling the data. The DATLAT value must be consistent with the latency value specified in the NOR Flash configuration register. The FMC does not include the clock cycle when NADV is low in the data latency count.

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Caution: Some NOR Flash memories include the NADV Low cycle in the data latency count, so that the exact relation between the NOR Flash latency and the FMC DATLAT parameter can be either:

 NOR Flash latency = (DATLAT + 2) CLK clock cycles

 or NOR Flash latency = (DATLAT + 3) CLK clock cycles

Some recent memories assert NWAIT during the latency phase. In such cases DATLAT can be set to its minimum value. As a result, the FMC samples the data and waits long enough to evaluate if the data are valid. Thus the FMC detects when the memory exits latency and real data are processed.

Other memories do not assert NWAIT during latency. In this case the latency must be set correctly for both the FMC and the memory, otherwise invalid data are mistaken for good data, or valid data are lost in the initial phase of the memory access.

Single-burst transfer

When the selected bank is configured in Burst mode for synchronous accesses, if for example an AHB single-burst transaction is requested on 16-bit memories, the FMC performs a burst transaction of length 1 (if the AHB transfer is 16 bits), or length 2 (if the

AHB transfer is 32 bits) and de-assert the chip select signal when the last data is strobed.

Such transfers are not the most efficient in terms of cycles compared to asynchronous read operations. Nevertheless, a random asynchronous access would first require to re-program the memory access mode, which would altogether last longer.

Cross boundary page for CellularRAM™ 1.5

CellularRAM™ 1.5 does not allow burst access to cross the page boundary. The FMC controller allows to split automatically the burst access when the memory page size is reached by configuring the CPSIZE bits in the FMC_BCR1 register following the memory page size.

Wait management

For synchronous NOR Flash memories, NWAIT is evaluated after the programmed latency period, which corresponds to (DATLAT+2) CLK clock cycles.

If NWAIT is active (low level when WAITPOL = 0, high level when WAITPOL = 1), wait states are inserted until NWAIT is inactive (high level when WAITPOL = 0, low level when

WAITPOL = 1).

When NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1) or on the next clock edge (bit WAITCFG = 0).

During wait-state insertion via the NWAIT signal, the controller continues to send clock pulses to the memory, keeping the chip select and output enable signals valid. It does not consider the data as valid.

In Burst mode, there are two timing configurations for the NOR Flash NWAIT signal:

 The Flash memory asserts the NWAIT signal one data cycle before the wait state

(default after reset).

 The Flash memory asserts the NWAIT signal during the wait state

The FMC supports both NOR Flash wait state configurations, for each chip select, thanks to the WAITCFG bit in the FMC_BCRx registers (x = 0..3).

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Figure 49. Wait configuration waveforms

Memory transaction = burst of 4 half words

HCLK

CLK

A[25:16]

NADV

NWAIT

(WAITCFG = 0)

NWAIT

(WAITCFG = 1)

A/D[15:0] addr[25:16] addr[15:0] data inserted wait state data data ai15798c

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Figure 50. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM)

Memory transaction = burst of 4 half words

HCLK

CLK

A[25:16] addr[25:16]

NEx

NOE

NWE

High

NADV

NWAIT

(WAITCFG=

A/D[15:0]

Addr[15:0]

(DATLAT + 2)

CLK cycles data inserted wait state data data data

1 clock cycle

Data strobes Data strobes ai17723f

1. Byte lane outputs (NBL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, they are held low.

Table 70. FMC_BCRx bitfields (Synchronous multiplexed read mode)

Bit number Bit name Value to set

31:22

Reserved

WFDIS

0x000

As needed

CCLKEN As needed

CBURSTRW No effect on synchronous read

18:16

CPSIZE 0x0 (no effect in Asynchronous mode)

ASYNCWAIT 0x0

14 EXTMOD

WAITEN

WREN

0x0

To be set to 1 if the memory supports this feature, to be kept at 0 otherwise

No effect on synchronous read

WAITCFG To be set according to memory

Reserved 0x0

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Table 70. FMC_BCRx bitfields (Synchronous multiplexed read mode) (continued)

Bit number Bit name Value to set

9 WAITPOL To be set according to memory

8 BURSTEN 0x1

7 Reserved

6 FACCEN

0x1

Set according to memory support (NOR Flash memory)

3-2 MTYP

1 MUXEN

0 MBKEN 0x1

Table 71. FMC_BTRx bitfields (Synchronous multiplexed read mode)

Bit number Bit name Value to set

31:30

29:28

27-24

23-20

19-16

15-8

7-4

3-0

Reserved

ACCMOD

DATLAT

0x0

Data latency

CLKDIV

0x0 to get CLK = HCLK (Not supported)

0x1 to get CLK = 2 × HCLK

BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).

DATAST

ADDHLD

ADDSET

Don’t care

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Figure 51. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)

Memory transaction = burst of 2 half words

HCLK

RM0390

CLK

A[25:16]

NEx

NOE

Hi-Z addr[25:16]

NWE

NADV

NWAIT

(WAITCFG = 0)

A/D[15:0]

Addr[15:0]

(DATLAT + 2)

CLK cycles data inserted wait state data

1 clock 1 clock ai14731f

1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.

2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.

Table 72. FMC_BCRx bitfields (Synchronous multiplexed write mode)

Bit number Bit name Value to set

31:22

Reserved 0x000

WFDIS As needed

CCLKEN As needed

18:16

15 ASYNCWAIT 0x0

14 EXTMOD 0x0

CBURSTRW 0x1

CPSIZE As needed (0x1 for CRAM 1.5)

WAITEN

To be set to 1 if the memory supports this feature, to be kept at 0 otherwise.

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Table 72. FMC_BCRx bitfields (Synchronous multiplexed write mode) (continued)

Bit number Bit name Value to set

WREN 0x1

WAITCFG 0x0

Reserved 0x0

WAITPOL to be set according to memory

8 BURSTEN no effect on synchronous write

7 Reserved 0x1

6 FACCEN Set according to memory support

3-2 MTYP

1 MUXEN

0 MBKEN

0x1

Table 73. FMC_BTRx bitfields (Synchronous multiplexed write mode)

Bit number Bit name Value to set

31-30

29:28

27-24

23-20

19-16

15-8

7-4

3-0

Reserved 0x0

ACCMOD 0x0

DATLAT Data latency

CLKDIV

0x0 to get CLK = HCLK (not supported)

0x1 to get CLK = 2 × HCLK

BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).

DATAST

ADDHLD

ADDSET

Don’t care

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SRAM/NOR-Flash chip-select control register for bank x

(FMC_BCRx) (x = 1 to 4)

Address offset: 8 * (x – 1), (x = 1 to 4)

Reset value: Bank 1: 0x0000 30DB

Reset value: Bank 2: 0x0000 30D2

Reset value: Bank 3: 0x0000 30D2

Reset value: Bank 4: 0x0000 30D2

This register contains the control information of each memory bank, used for SRAMs,

PSRAM and NOR Flash memories.

Res.

ASYNC

WAIT rw

EXT

MOD rw

WAIT

EN rw

WREN rw

WAIT

CFG rw

Res.

WAIT

POL rw

BURST

EN rw

Res.

22 21

Res.

WFDIS rw

CCLK

EN rw

4 6

FACC

EN rw

MWID[1:0] rw rw

CBURST

RW rw

3 rw

18 rw

MTYP[1:0]

2 rw

CPSIZE[2:0] rw

MUX

EN rw

16 rw

MBK

EN rw

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 WFDIS: Write FIFO disable

This bit disables the Write FIFO used by the FMC controller.

0: Write FIFO enabled (Default after reset)

1: Write FIFO disabled

Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the

FMC_BCR1 register.

Bit 20 CCLKEN: Continuous clock enable

This bit enables the FMC_CLK clock output to external memory devices.

0: The FMC_CLK is only generated during the synchronous memory access (read/write transaction). The FMC_CLK clock ratio is specified by the programmed CLKDIV value in the

FMC_BCRx register (default after reset).

1: The FMC_CLK is generated continuously during asynchronous and synchronous access. The

FMC_CLK clock is activated when the CCLKEN is set.

Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the

FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the

FMC_CLK continuous clock.

Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care.

Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the

FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.)

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Bit 19 CBURSTRW: Write burst enable

For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register.

0: Write operations are always performed in Asynchronous mode.

1: Write operations are performed in Synchronous mode.

Bits 18:16 CPSIZE[2:0] : CRAM page size

These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size).

000: No burst split when crossing page boundary (default after reset)

001: 128 bytes

010: 256 bytes

011: 512 bytes

100: 1024 bytes

Others: reserved

Bit 15 ASYNCWAIT : Wait signal during asynchronous transfers

This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol.

0: NWAIT signal is not taken in to account when running an asynchronous protocol (default after reset).

1: NWAIT signal is taken in to account when running an asynchronous protocol.

Bit 14 EXTMOD: Extended mode enable

This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations.

0: values inside FMC_BWTR register are not taken into account (default after reset)

1: values inside FMC_BWTR register are taken into account

Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows:

– Mode 1 is the default mode when the SRAM/PSRAM memory type is selected

(MTYP = 0x0 or 0x01)

– Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).

Bit 13 WAITEN: Wait enable bit

This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in

Synchronous mode.

0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after the programmed Flash latency period).

1: NWAIT signal is enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset).

Bit 12 WREN: Write enable bit

This bit indicates whether write operations are enabled/disabled in the bank by the FMC.

0: Write operations are disabled in the bank by the FMC, an AHB error is reported.

1: Write operations are enabled for the bank by the FMC (default after reset).

Bit 11 WAITCFG: Wait timing configuration

The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if

NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:

0: NWAIT signal is active one data cycle before wait state (default after reset).

1: NWAIT signal is active during wait state (not used for PSRAM).

Bit 10 Reserved, must be kept at reset value.

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Bit 9 WAITPOL: Wait signal polarity bit

Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode.

0: NWAIT active low (default after reset)

1: NWAIT active high

Bit 8 BURSTEN: Burst enable bit

This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode.

0: Burst mode disabled (default after reset). Read accesses are performed in Asynchronous mode.

1: Burst mode enable. Read accesses are performed in Synchronous mode.

Bit 7 Reserved, must be kept at reset value.

Bit 6 FACCEN: Flash access enable

Enables NOR Flash memory access operations.

0: Corresponding NOR Flash memory access is disabled.

1: Corresponding NOR Flash memory access is enabled (default after reset).

Bits 5:4 MWID[1:0]: Memory data bus width

Defines the external memory device width, valid for all type of memories.

00: 8 bits

01: 16 bits (default after reset)

10: reserved

11: reserved

Bits 3:2 MTYP[1:0]: Memory type

Defines the type of external memory attached to the corresponding memory bank.

00: SRAM (default after reset for Bank 2...4)

01: PSRAM (CRAM)

10: NOR Flash/OneNAND Flash (default after reset for Bank 1)

11: reserved

Bit 1 MUXEN: Address/data multiplexing enable bit

When this bit is set, the address and data values are multiplexed on the data bus, valid only with

NOR and PSRAM memories:

0: Address/data non multiplexed

1: Address/data multiplexed on databus (default after reset)

Bit 0 MBKEN: Memory bank enable bit

Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus.

0: Corresponding memory bank is disabled.

1: Corresponding memory bank is enabled.

SRAM/NOR-Flash chip-select timing register for bank x (FMC_BTRx)

Address offset: 0x04 + 8 * (x – 1), (x = 1 to 4)

Reset value: 0x0FFF FFFF

This register contains the control information of each memory bank, used for SRAMs,

PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to

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Res.

15 rw configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).

Res.

14 rw

29 28

ACCMOD[1:0] rw

13 rw rw

27 rw

12 11

DATAST[7:0] rw rw

26 25

DATLAT[3:0] rw

10 rw

9 rw rw

24 rw

8 rw

23 rw

7 rw

22 21

CLKDIV[3:0] rw rw

6 5

ADDHLD[3:0] rw rw

20 rw

4 rw

19 rw

3 rw

18 17

BUSTURN[3:0] rw rw

2 1

ADDSET[3:0] rw rw

16 rw

0 rw

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 ACCMOD[1:0]: Access mode

Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.

00: Access mode A

01: Access mode B

10: Access mode C

11: Access mode D

Bits 27:24 DATLAT[3:0]: (see note below bit descriptions): Data latency for synchronous memory

For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits set), defines the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data:

This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods.

For asynchronous access, this value is don't care.

0000: Data latency of 2 CLK clock cycles for first burst access

1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)

Bits 23:20 CLKDIV[3:0]: Clock divide ratio (for FMC_CLK signal)

Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles:

0000: Reserved

0001: FMC_CLK period = 2 × HCLK periods

0010: FMC_CLK period = 3 × HCLK periods

1111: FMC_CLK period = 16 × HCLK periods (default value after reset)

In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care.

Note: Refer to

Section 11.6.5: Synchronous transactions for FMC_CLK divider ratio formula)

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Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration

These bits are written by software to add a delay at the end of a write-to-read (and read-towrite) transaction. This delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (tEHQZ). The programmed bus turnaround delay is inserted between an asynchronous read (muxed or mode D) or write transaction and any other asynchronous /synchronous read or write to or from a static bank. The bank can be the same or different in case of read, in case of write the bank can be different except for muxed or mode D.

In some cases, whatever the programmed BUSTURN values, the bus turnaround delay is fixed as follows:

• The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D.

• There is a bus turnaround delay of 1 HCLK clock cycle between:

–Two consecutive asynchronous read transfers to the same static memory bank except for muxed mode and mode D.

–An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except for muxed mode and mode D.

–An asynchronous (modes 1, 2, A, B or C) read and a read from another static bank.

• There is a bus turnaround delay of 2 HCLK clock cycle between:

–Two consecutive synchronous writes (burst or single) to the same bank.

–A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or different for the case of read.

–Two consecutive synchronous reads (burst or single) followed by any synchronous/asynchronous read or write from/to another static memory bank.

• There is a bus turnaround delay of 3 HCLK clock cycle between:

–Two consecutive synchronous writes (burst or single) to different static bank.

–A synchronous write (burst or single) access and a synchronous read from the same or a different bank.

0000: BUSTURN phase duration = 0 HCLK clock cycle added

...

1111: BUSTURN phase duration = 15 x HCLK clock cycles added (default value after reset)

Bits 15:8 DATAST[7:0]: Data-phase duration

These bits are written by software to define the duration of the data phase (refer to Figure 34

to Figure 46

), used in asynchronous accesses:

0000 0000: Reserved

0000 0001: DATAST phase duration = 1 × HCLK clock cycles

0000 0010: DATAST phase duration = 2 × HCLK clock cycles

...

1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)

For each memory type and access mode data-phase duration, refer to the respective figure

(

Figure 34 to

Figure 46

Example: Mode 1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK clock cycles.

Note: In synchronous accesses, this value is don’t care.

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Note:

Bits 7:4 ADDHLD[3:0]: Address-hold phase duration

These bits are written by software to define the duration of the address hold phase (refer to

Figure 34

Figure 46 ), used in mode D or multiplexed accesses:

0000: Reserved

0001: ADDHLD phase duration =1 × HCLK clock cycle

0010: ADDHLD phase duration = 2 × HCLK clock cycle

...

1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)

For each access mode address-hold phase duration, refer to the respective figure (

Figure 34

to Figure 46

Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration.

Bits 3:0 ADDSET[3:0]: Address setup phase duration

These bits are written by software to define the duration of the address setup phase (refer to

Figure 34

Figure 46 ), used in SRAMs, ROMs, asynchronous NOR Flash and PSRAM:

0000: ADDSET phase duration = 0 × HCLK clock cycle

...

1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)

For each access mode address setup phase duration, refer to the respective figure

(

Figure 34 to

Figure 46

Note: In synchronous accesses, this value is don’t care.

In Muxed mode or mode D, the minimum value for ADDSET is 1.

In mode 1 and PSRAM memory, the minimum value for ADDSET is 1.

PSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these memories issue the NWAIT signal during the whole latency phase to prolong the latency as needed.

With PSRAMs (CRAMs) the filled DATLAT must be set to 0, so that the FMC exits its latency phase soon and starts sampling NWAIT from memory, then starts to read or write when the memory is ready.

This method can be used also with the latest generation of synchronous Flash memories that issue the NWAIT signal, unlike older Flash memories (check the datasheet of the specific Flash memory being used).

SRAM/NOR-Flash write timing registers x (FMC_BWTRx)

Address offset: 0x104 + 8 * (x – 1), (x = 1 to 4)

Reset value: 0x0FFF FFFF

This register contains the control information of each memory bank. It is used for SRAMs,

PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Res.

14 rw

29 28

ACCMOD[1:0] rw

13 rw rw

Res.

12 11

DATAST[7:0] rw rw

Res.

8 rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Res.

7 rw

Res.

6 5

ADDHLD[3:0] rw rw

Res.

4 rw

19 rw

3 rw

18 17

BUSTURN[3:0] rw rw

2 1

ADDSET[3:0] rw rw

16 rw

0 rw

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Bits 29:28 ACCMOD[1:0]: Access mode.

Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.

00: Access mode A

01: Access mode B

10: Access mode C

11: Access mode D

Bits 27:20 Reserved, must be kept at reset value.

Bits 19:16 BUSTURN[3:0] : Bus turnaround phase duration

The programmed bus turnaround delay is inserted between an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. The bank can be the same or different in case of read, in case of write the bank can be different expect for muxed or mode D.

In some cases, whatever the programmed BUSTURN values, the bus turnaround delay is fixed as follows:

• The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed and D modes.

• There is a bus turnaround delay of 2 HCLK clock cycle between:

–Two consecutive synchronous writes (burst or single) to the same bank.

–A synchronous write (burst or single) transfer and an asynchronous write or read transfer to or from static memory bank.

• There is a bus turnaround delay of 3 HCLK clock cycle between:

–Two consecutive synchronous writes (burst or single) to different static bank.

–A synchronous write (burst or single) transfer and a synchronous read from the same or a different bank.

0000: BUSTURN phase duration = 0 HCLK clock cycle added

...

1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)

Bits 15:8 DATAST[7:0]: Data-phase duration.

These bits are written by software to define the duration of the data phase (refer to

Figure 34

Figure 46

), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:

0000 0000: Reserved

0000 0001: DATAST phase duration = 1 × HCLK clock cycles

0000 0010: DATAST phase duration = 2 × HCLK clock cycles

...

1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)

Bits 7:4 ADDHLD[3:0]: Address-hold phase duration.

These bits are written by software to define the duration of the address hold phase (refer to

Figure 43

to Figure 46

), used in asynchronous multiplexed accesses:

0000: Reserved

0001: ADDHLD phase duration = 1 × HCLK clock cycle

0010: ADDHLD phase duration = 2 × HCLK clock cycle

...

1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)

Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always

1 Flash clock period duration.

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Bits 3:0 ADDSET[3:0]: Address setup phase duration.

These bits are written by software to define the duration of the address setup phase in HCLK cycles

(refer to Figure 34

to Figure 46

), used in asynchronous accesses:

0000: ADDSET phase duration = 0 × HCLK clock cycle

...

1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)

Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1.

11.7 NAND Flash controller

The FMC generates the appropriate signal timings to drive the following types of device:

 8- and 16-bit NAND Flash memories

The NAND bank is configured through dedicated registers ( Section 11.7.7

). The programmable memory parameters include access timings (shown in

Table 74

) and ECC configuration.

Parameter

Table 74. Programmable NAND Flash access parameters

Function Access mode Unit

Memory setup time

Memory wait

Number of clock cycles (HCLK) required to set up the address before the command assertion

Minimum duration (in HCLK clock cycles) of the command assertion

Memory hold

Memory databus high-Z

Number of clock cycles (HCLK) during which the address must be held (as well as the data if a write access is performed) after the command de-assertion

Number of clock cycles (HCLK) during which the data bus is kept in high-Z state after a write access has started

Read/Write

Write

AHB clock cycle

(HCLK)

AHB clock cycle

(HCLK)

AHB clock cycle

(HCLK)

AHB clock cycle

(HCLK)

Min. Max.

1 255

2 255

1 254

1 255

11.7.1 External memory interface signals

Note:

The following tables list the signals that are typically used to interface NAND Flash memory.

The prefix “N” identifies the signals which are active low.

8-bit NAND Flash memory

FMC signal name

A[17]

A[16]

I/O

Table 75. 8-bit NAND Flash

Function

O NAND Flash address latch enable (ALE) signal

O NAND Flash command latch enable (CLE) signal

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FMC signal name

NCE

NOE(= NRE)

NWE

NWAIT/INT

Table 75. 8-bit NAND Flash (continued)

I/O Function

8-bit bidirectional address/data bus

O Chip select

O Output enable (memory signal name: read enable, NRE)

I NAND Flash ready/busy input signal to the FMC

Theoretically, there is no capacity limitation as the FMC can manage as many address cycles as needed.

16-bit NAND Flash memory

FMC signal name

A[17]

A[16]

I/O

Table 76. 16-bit NAND Flash

Function

O NAND Flash address latch enable (ALE) signal

O NAND Flash command latch enable (CLE) signal

NCE

NOE(= NRE)

NWE

NWAIT/INT

O Chip select

O Output enable (memory signal name: read enable, NRE)

I NAND Flash ready/busy input signal to the FMC

Theoretically, there is no capacity limitation as the FMC can manage as many address cycles as needed.

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Table 77 shows the supported devices, access modes and transactions. Transactions not

allowed (or not supported) by the NAND Flash controller are shown in gray.

Device

Table 77. Supported memories and transactions

Memory data size

Allowed/ not allowed

Comments

Asynchronous R 8 8 Y

Asynchronous W 8 8 Y

NAND 8-bit

Asynchronous R

Asynchronous W

Split into 2 FMC accesses

Asynchronous R

Asynchronous W

Asynchronous R 8 16 Y

Asynchronous W 8 16 N

Split into 4 FMC accesses

NAND 16-bit

Asynchronous R 16 16 Y

Asynchronous W 16 16 Y

Asynchronous R

Asynchronous W

Split into 2 FMC accesses

The NAND Flash memory bank is managed through a set of registers:

 Control register: FMC_PCR

 Interrupt status register: FMC_SR

 ECC register: FMC_ECCR

 Timing register for Common memory space: FMC_PMEM

 Timing register for Attribute memory space: FMC_PATT

Each timing configuration register contains three parameters used to define number of

HCLK cycles for the three phases of any NAND Flash access, plus one parameter that defines the timing for starting driving the data bus when a write access is performed.

Figure 52

shows the timing parameter definitions for common memory accesses, knowing that Attribute memory space access timings are similar.

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Figure 52. NAND Flash controller waveforms for common memory access

HCLK

A[25:0]

NCEx

NREG,

NIOW,

NIOR

NWE,

NOE (1)

High write_data read_data

MEMxSET

+ 1

MEMxHIZ + 1

MEMxWAIT + 1

Valid

MEMxHOLD

MS33733V3

1. NOE remains high (inactive) during write accesses. NWE remains high (inactive) during read accesses.

2. For write access, the hold phase delay is (MEMHOLD) HCLK cycles and for read access is

(MEMHOLD + 2) HCLK cycles.

The command latch enable (CLE) and address latch enable (ALE) signals of the NAND

Flash memory device are driven by address signals from the FMC controller. This means that to send a command or an address to the NAND Flash memory, the CPU has to perform a write to a specific address in its memory space.

A typical page read operation from the NAND Flash device requires the following steps:

Program and enable the corresponding memory bank by configuring the FMC_PCR

and FMC_PMEM (and for some devices, FMC_PATT, see Section 11.7.5: NAND Flash prewait functionality

) registers according to the characteristics of the NAND Flash memory (PWID bits for the data bus width of the NAND Flash, PTYP = 1, PWAITEN =

0 or 1 as needed, see Section 11.5.2: NAND Flash memory address mapping for timing

configuration).

2. The CPU performs a byte write to the common memory space, with data byte equal to one Flash command byte (for example 0x00 for Samsung NAND Flash devices). The

LE input of the NAND Flash memory is active during the write strobe (low pulse on

NWE), thus the written byte is interpreted as a command by the NAND Flash memory.

Once the command is latched by the memory device, it does not need to be written again for the following page read operations.

3. The CPU can send the start address (STARTAD) for a read operation by writing four bytes (or three for smaller capacity devices), STARTAD[7:0], STARTAD[16:9],

STARTAD[24:17] and finally STARTAD[25] (for 64 Mb x 8 bit NAND Flash memories) in the common memory or attribute space. The ALE input of the NAND Flash device is active during the write strobe (low pulse on NWE), thus the written bytes are interpreted as the start address for read operations. Using the attribute memory space makes it possible to use a different timing configuration of the FMC, which can be used

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details in Section 11.7.5: NAND Flash prewait functionality

4. The controller waits for the NAND Flash memory to be ready (R/NB signal high), before starting a new access to the same or another memory bank. While waiting, the controller holds the NCE signal active (low).

5. The CPU can then perform byte read operations from the common memory space to read the NAND Flash page (data field + Spare field) byte by byte.

6. The next NAND Flash page can be read without any CPU command or address write operation. This can be done in three different ways:

– by simply performing the operation described in step 5

– a new random address can be accessed by restarting the operation at step 3

– a new command can be sent to the NAND Flash device by restarting at step 2

Some NAND Flash devices require that, after writing the last part of the address, the controller waits for the R/NB signal to go low. (see

Figure 53

Figure 53. Access to non ‘CE don’t care’ NAND-Flash

1. CPU wrote byte 0x00 at address 0x7001 0000.

2. CPU wrote byte A7~A0 at address 0x7002 0000.

3. CPU wrote byte A16~A9 at address 0x7002 0000.

4. CPU wrote byte A24~A17 at address 0x7002 0000.

5. CPU wrote byte A25 at address 0x7802 0000: FMC performs a write access using FMC_PATT timing definition, where ATTHOLD ≥ 7 (providing that (7+1) × HCLK = 112 ns > t max). This guarantees that

NCE remains low until R/NB goes low and high again (only requested for NAND Flash memories where

NCE is not don’t care).

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When this functionality is required, it can be ensured by programming the MEMHOLD value to meet the t

timing. However any CPU read access to the NAND Flash memory has a hold delay of (MEMHOLD + 2) HCLK cycles and CPU write access has a hold delay of

(MEMHOLD) HCLK cycles inserted between the rising edge of the NWE signal and the next access.

To cope with this timing constraint, the attribute memory space can be used by programming its timing register with an ATTHOLD value that meets the t

timing, and by keeping the MEMHOLD value at its minimum value. The CPU must then use the common memory space for all NAND Flash read and write accesses, except when writing the last address byte to the NAND Flash device, where the CPU must write to the attribute memory space.

in NAND Flash memory

The FMC NAND Card controller includes two error correction code computation hardware blocks, one per memory bank. They reduce the host CPU workload when processing the

ECC by software.

These two ECC blocks are identical and associated with Bank 2 and Bank 3. As a consequence, no hardware ECC computation is available for memories connected to

Bank 4.

The ECC algorithm implemented in the FMC can perform 1-bit error correction and 2-bit error detection per 256, 512, 1 024, 2 048, 4 096 or 8 192 bytes read or written from/to the

NAND Flash memory. It is based on the Hamming coding algorithm and consists in calculating the row and column parity.

The ECC modules monitor the NAND Flash data bus and read/write signals (NCE and

NWE) each time the NAND Flash memory bank is active.

The ECC operates as follows:

 When accessing NAND Flash memory bank 2 or bank 3, the data present on the

D[15:0] bus is latched and used for ECC computation.

 When accessing any other address in NAND Flash memory, the ECC logic is idle, and does not perform any operation. As a result, write operations to define commands or addresses to the NAND Flash memory are not taken into account for ECC computation.

Once the desired number of bytes has been read/written from/to the NAND Flash memory by the host CPU, the FMC_ECCR registers must be read to retrieve the computed value.

Once read, they should be cleared by resetting the ECCEN bit to ‘0’. To compute a new data block, the ECCEN bit must be set to one in the FMC_PCR registers.

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To perform an ECC computation:

Enable the ECCEN bit in the FMC_PCR register.

2. Write data to the NAND Flash memory page. While the NAND page is written, the ECC block computes the ECC value.

3. Read the ECC value available in the FMC_ECCR register and store it in a variable.

4. Clear the ECCEN bit and then enable it in the FMC_PCR register before reading back the written data from the NAND page. While the NAND page is read, the ECC block computes the ECC value.

5. Read the new ECC value available in the FMC_ECCR register.

6. If the two ECC values are the same, no correction is required, otherwise there is an

ECC error and the software correction routine returns information on whether the error can be corrected or not.

Res.

NAND Flash control registers (FMC_PCR)

Address offset: 0x80

Reset value: 0x0000 0018

Res.

15 rw

TAR[2:0] rw

13 rw

12 rw

11 10

TCLR[3:0] rw rw

9 rw

Res.

7 6

Res.

ECCEN rw

Res.

PWID[1:0] rw

4 rw

19 18

ECCPS[2:0]

17 16

TAR3 rw rw rw rw

3 2 1 0

PTYP PBKEN PWAITEN Res.

rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:17 ECCPS[2:0]: ECC page size

Defines the page size for the extended ECC:

000: 256 bytes

001: 512 bytes

010: 1024 bytes

011: 2048 bytes

100: 4096 bytes

101: 8192 bytes

Bits 16:13 TAR[3:0]: ALE to RE delay

Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).

Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period

0000: 1 HCLK cycle (default)

1111: 16 HCLK cycles

Note: SET is MEMSET or ATTSET according to the addressed space.

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Bits 12:9 TCLR[3:0]: CLE to RE delay

Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).

Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period

0000: 1 HCLK cycle (default)

1111: 16 HCLK cycles

Note: SET is MEMSET or ATTSET according to the addressed space.

Bits 8:7 Reserved, must be kept at reset value.

Bit 6 ECCEN: ECC computation logic enable bit

0: ECC logic is disabled and reset (default after reset),

1: ECC logic is enabled.

Bits 5:4 PWID[1:0]: Data bus width

Defines the external memory device width.

00: 8 bits

01: 16 bits (default after reset).

10: reserved.

11: reserved.

Bit 3 PTYP: Memory type

Defines the type of device attached to the corresponding memory bank:

0: Reserved, must be kept at reset value

1: NAND Flash (default after reset)

Bit 2 PBKEN: NAND Flash memory bank enable bit

Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus

0: Corresponding memory bank is disabled (default after reset)

1: Corresponding memory bank is enabled

Bit 1 PWAITEN: Wait feature enable bit

Enables the Wait feature for the NAND Flash memory bank:

0: disabled

1: enabled

Bit 0 Reserved, must be kept at reset value.

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Res.

FIFO status and interrupt register (FMC_SR)

Address offset: 0x84

Reset value: 0x0000 0040

This register contains information about the FIFO status and interrupt. The FMC features a

FIFO that is used when writing to memories to transfer up to 16 words of data from the AHB.

This is used to quickly write to the FIFO and free the AHB for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.

The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.

Res.

7 6 5

Res.

FEMPT IFEN r rw

ILEN rw

IREN rw

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 FEMPT: FIFO empty

Read-only bit that provides the status of the FIFO

0: FIFO not empty

1: FIFO empty

Bit 5 IFEN: Interrupt falling edge detection enable bit

0: Interrupt falling edge detection request disabled

1: Interrupt falling edge detection request enabled

Bit 4 ILEN: Interrupt high-level detection enable bit

0: Interrupt high-level detection request disabled

1: Interrupt high-level detection request enabled

Bit 3 IREN: Interrupt rising edge detection enable bit

0: Interrupt rising edge detection request disabled

1: Interrupt rising edge detection request enabled

Bit 2 IFS: Interrupt falling edge status

The flag is set by hardware and reset by software.

0: No interrupt falling edge occurred

1: Interrupt falling edge occurred

Note: If this bit is written by software to 1 it is set.

Bit 1 ILS: Interrupt high-level status

The flag is set by hardware and reset by software.

0: No Interrupt high-level occurred

1: Interrupt high-level occurred

IFS rw

ILS rw

IRS rw

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31 rw

15 rw

Bit 0 IRS: Interrupt rising edge status

The flag is set by hardware and reset by software.

0: No interrupt rising edge occurred

1: Interrupt rising edge occurred

Note: If this bit is written by software to 1 it is set.

Common memory space timing register (FMC_PMEM)

Address offset: Address: 0x88

Reset value: 0xFCFC FCFC

The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the

NAND Flash for command, address write access and data read/write access.

30 29 rw

14 rw rw

13 rw

28 27

MEMHIZ[7:0] rw rw

12 11

MEMWAIT[7:0] rw rw

26 rw

10 rw

25 rw

9 rw

24 rw

8 rw

23 rw

7 rw

22 rw

6 rw

21 rw

5 rw

20 19

MEMHOLD[7:0] rw rw

4 3

MEMSET[7:0] rw rw

18 rw

2 rw

17 rw

1 rw

16 rw

0 rw

Bits 31:24 MEMHIZ[7:0]: Common memory x data bus Hi-Z time

Defines the number of HCLK clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space on socket. This is only valid for write transactions:

0000 0000: 1 HCLK cycle

1111 1110: 255 HCLK cycles

1111 1111: reserved.

Bits 23:16 MEMHOLD[7:0]: Common memory hold time

Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for read access during which the address is held (and data for write accesses) after the command is deasserted (NWE, NOE), for NAND Flash read or write access to common memory space on socket x:

0000 0000: reserved.

0000 0001: 1 HCLK cycle for write access / 3 HCLK cycles for read access

1111 1110: 254 HCLK cycles for write access / 256 HCLK cycles for read access

1111 1111: reserved.

Bits 15:8 MEMWAIT[7:0]: Common memory wait time

Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,

NOE), for NAND Flash read or write access to common memory space on socket. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of HCLK:

0000 0000: reserved

0000 0001: 2HCLK cycles (+ wait cycle introduced by deasserting NWAIT)

1111 1110: 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)

1111 1111: reserved.

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31 rw

15 rw

Bits 7:0 MEMSET[7:0]: Common memory x setup time

Defines the number of HCLK (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space on socket x:

0000 0000: 1 HCLK cycle

1111 1110: 255 HCLK cycles

1111 1111: reserved

Attribute memory space timing register (FMC_PATT)

Address offset: 0x8C

Reset value: 0xFCFC FCFC

The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for

Ready/Busy management, refer to Section 11.7.5: NAND Flash prewait functionality ).

30 29 rw

14 rw rw

13 rw

28 27

ATTHIZ[7:0] rw

12 rw

ATTWAIT[7:0] rw rw

26 rw

10 rw

25 rw

9 rw

24 rw

8 rw

23 rw

7 rw

22 rw

6 rw

21 rw

5 rw

20 19

ATTHOLD[7:0] rw

4 rw

ATTSET[7:0] rw rw

18 rw

2 rw

17 rw

1 rw

16 rw

0 rw

Bits 31:24 ATTHIZ[7:0]: Attribute memory data bus Hi-Z time

Defines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction:

0000 0000: 0 HCLK cycle

1111 1110: 255 HCLK cycles

1111 1111: reserved.

Bits 23:16 ATTHOLD[7:0]: Attribute memory hold time

Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for read access during which the address is held (and data for write access) after the command deassertion (NWE, NOE), for NAND Flash read or write access to attribute memory space on socket:

0000 0000: reserved

0000 0001: 1 HCLK cycle for write access / 3 HCLK cycles for read access

1111 1110: 254 HCLK cycles for write access / 256 HCLK cycles for read access

1111 1111: reserved.

Bits 15:8 ATTWAIT[7:0]: Attribute memory wait time

Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,

NOE), for NAND Flash read or write access to attribute memory space on socket x. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of HCLK:

0000 0000: reserved

0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)

1111 1110: 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)

1111 1111: reserved.

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31 r

15 r

Bits 7:0 ATTSET[7:0]: Attribute memory setup time

Defines the number of HCLK (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space on socket:

0000 0000: 1 HCLK cycle

1111 1110: 255 HCLK cycles

1111 1111: reserved.

ECC result registers (FMC_ECCR)

Address offset: 0x94

Reset value: 0x0000 0000

This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads the data from a

NAND Flash memory page at the correct address (refer to

Section 11.7.6: Computation of the error correction code (ECC) in NAND Flash memory ), the data read/written from/to the

NAND Flash memory are processed automatically by the ECC computation module. When

X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.

30 29 r

14 r r

28 r

27 r

26 r

25 r

24 23

ECC[31:16] r r

8 7

ECC[15:0] r r

22 r

21 r

20 r

19 r

18 r

17 r

16 r

Bits 31:0 ECC[31:0]: ECC result

This field contains the value computed by the ECC computation logic.

Table 78

describes the contents of these bitfields.

r r r r r r r r r r r r

ECCPS[2:0]

000

001

010

011

100

101

Table 78. ECC result relevant bits

Page size in bytes

256

512

1024

2048

4096

8192

ECC bits

ECC[21:0]

ECC[23:0]

ECC[25:0]

ECC[27:0]

ECC[29:0]

ECC[31:0]

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11.8.1 SDRAM controller main features

The main features of the SDRAM controller are the following:

 Two SDRAM banks with independent configuration

 8-bit, 16-bit data bus width

 13-bits Address Row, 11-bits Address Column, 4 internal banks: 4x16Mx16bit

(128 MB), 4x16Mx8bit (64 MB)

 Word, half-word, byte access

 SDRAM clock can be HCLK/2 or HCLK/3

 Automatic row and bank boundary management

 Multibank ping-pong access

 Programmable timing parameters

 Automatic Refresh operation with programmable Refresh rate

 Self-refresh mode

 Power-down mode

 SDRAM power-up initialization by software

 CAS latency of 1,2,3

 Cacheable Read FIFO with depth of 6 lines x32-bit (6 x14-bit address tag)

At startup, the SDRAM I/O pins used to interface the FMC SDRAM controller with the external SDRAM devices must configured by the user application. The SDRAM controller

I/O pins which are not used by the application, can be used for other purposes.

SDRAM signal

Table 79. SDRAM signals

Description Alternate function

SDCLK

SDCKE[1:0]

SDNE[1:0]

A[12:0]

D[15:0]

BA[1:0]

NRAS

NCAS

SDNWE

NBL[1:0]

I/O

I/O type

SDRAM clock

SDCKE0: SDRAM Bank 1 Clock Enable

SDCKE1: SDRAM Bank 2 Clock Enable

SDNE0: SDRAM Bank 1 Chip Enable

SDNE1: SDRAM Bank 2 Chip Enable

Address

Bidirectional data bus

Bank Address

Row Address Strobe

Column Address Strobe

Write Enable

Output Byte Mask for write accesses

(memory signal name: DQM[1:0]

FMC_A[12:0]

FMC_D[15:0]

FMC_A[15:14]

FMC_NBL[1:0]

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All SDRAM controller outputs (signals, address and data) change on the falling edge of the memory clock (FMC_SDCLK).

SDRAM initialization

The initialization sequence is managed by software. If the two banks are used, the initialization sequence must be generated simultaneously to Bank 1and Bank 2 by setting the Target Bank bits CTB1 and CTB2 in the FMC_SDCMR register:

Program the memory device features into the FMC_SDCRx register. The SDRAM clock frequency, RBURST and RPIPE must be programmed in the FMC_SDCR1 register.

2. Program the memory device timing into the FMC_SDTRx register. The TRP and TRC timings must be programmed in the FMC_SDTR1 register.

3. Set MODE bits to ‘001’ and configure the Target Bank bits (CTB1 and/or CTB2) in the

FMC_SDCMR register to start delivering the clock to the memory (SDCKE is driven high).

4. Wait during the prescribed delay period. Typical delay is around 100 μ s (refer to the

SDRAM datasheet for the required delay after power-up).

5. Set MODE bits to ‘010’ and configure the Target Bank bits (CTB1 and/or CTB2) in the

FMC_SDCMR register to issue a “Precharge All” command.

6. Set MODE bits to ‘011’, and configure the Target Bank bits (CTB1 and/or CTB2) as well as the number of consecutive Auto-refresh commands (NRFS) in the FMC_SDCMR register. Refer to the SDRAM datasheet for the number of Auto-refresh commands that should be issued. Typical number is 8.

7. Configure the MRD field according to the SDRAM device, set the MODE bits to '100', and configure the Target Bank bits (CTB1 and/or CTB2) in the FMC_SDCMR register to issue a "Load Mode Register" command in order to program the SDRAM device.

In particular: a) the CAS latency must be selected following configured value in FMC_SDCR1/2 registers b) the Burst Length (BL) of 1 must be selected by configuring the M[2:0] bits to 000 in the mode register. Refer to SDRAM device datasheet.

If the Mode Register is not the same for both SDRAM banks, this step has to be repeated twice, once for each bank, and the Target Bank bits set accordingly.

8. Program the refresh rate in the FMC_SDRTR register

The refresh rate corresponds to the delay between refresh cycles. Its value must be adapted to SDRAM devices.

9. For mobile SDRAM devices, to program the extended mode register it should be done once the SDRAM device is initialized: First, a dummy read access should be performed while BA1=1 and BA=0 (refer to SDRAM address mapping section for BA[1:0] address mapping) in order to select the extended mode register instead of the load mode register and then program the needed value.

At this stage the SDRAM device is ready to accept commands. If a system reset occurs during an ongoing SDRAM access, the data bus might still be driven by the SDRAM device.

Therefor the SDRAM device must be first reinitialized after reset before issuing any new access by the NOR Flash/PSRAM/SRAM or NAND Flash controller.

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Note:

Flexible memory controller (FMC)

If two SDRAM devices are connected to the FMC, all the accesses performed at the same time to both devices by the Command Mode register (Load Mode Register command) are issued using the timing parameters configured for SDRAM Bank 1 (TMRD andTRAS timings) in the FMC_SDTR1 register.

SDRAM controller write cycle

The SDRAM controller accepts single and burst write requests and translates them into single memory accesses. In both cases, the SDRAM controller keeps track of the active row for each bank to be able to perform consecutive write accesses to different banks (Multibank ping-pong access).

Before performing any write access, the SDRAM bank write protection must be disabled by clearing the WP bit in the FMC_SDCRx register.

Figure 54. Burst write SDRAM access waveforms

TRCD = 3

SDNE

SDCLK

A[12:0]

NRAS

NCAS

SDNWE

DATA[15:0]

Row n Cola Colb Colc Cold Cole Colf Cog Colh Coli Colj Colk Coll

Dna Dnb Dnc Dnd Dne Dnf Dng Dnh Dni Dnj Dnk Dnl

MS34488V3

The SDRAM controller always checks the next access.

 If the next access is in the same row or in another active row, the write operation is carried out,

 if the next access targets another row (not active), the SDRAM controller generates a precharge command, activates the new row and initiates a write command.

SDRAM controller read cycle

The SDRAM controller accepts single and burst read requests and translates them into single memory accesses. In both cases, the SDRAM controller keeps track of the active row in each bank to be able to perform consecutive read accesses in different banks (Multibank ping-pong access).

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Figure 55. Burst read SDRAM access

TRCD = 3 CAS latency = 2

SDNE

SDCLK

A[12:0]

NRAS

Row n Cola Colb Colc Cold Cole Colf

NCAS

NWE

DATA[15:0] Dna Dnb Dnc Dnd Dne Dnf

The FMC SDRAM controller features a Cacheable read FIFO (6 lines x 32 bits). It is used to store data read in advance during the CAS latency period and the RPIPE delay following the below formula. The RBURST bit must be set in the FMC_SDCR1 register to anticipate the next read access.

Number for anticipated data = CAS latency + 1 + (RPIPE delay)/2

MS34489V2

Examples:

 CAS latency = 3, RPIPE delay = 0: Four data (not committed) are stored in the FIFO.

 CAS latency = 3, RPIPE delay = 2: Five data (not committed) are stored in the FIFO.

The read FIFO features a 14-bit address tag to each line to identify its content: 11 bits for the column address, 2 bits to select the internal bank and the active row, and 1 bit to select the

SDRAM device

When the end of the row is reached in advance during an AHB burst read, the data read in advance (not committed) are not stored in the read FIFO. For single read access, data are correctly stored in the FIFO.

Each time a read request occurs, the SDRAM controller checks:

 If the address matches one of the address tags, data are directly read from the FIFO and the corresponding address tag/ line content is cleared and the remaining data in the FIFO are compacted to avoid empty lines.

 Otherwise, a new read command is issued to the memory and the FIFO is updated with new data. If the FIFO is full, the older data are lost.

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Figure 56. Logic diagram of Read access with RBURST bit set (CAS=1, RPIPE=0)

1st Read access: Requested data is not in the FIFO

AXI Master

FMC SDRAM Controller read request@0x00

Data 1

SDRAM

Device

(CAS = 1)

6 lines FIFO

@0x04

@0x08

Data 2

Data 3

...

Add. Tag read FIFO

Data stored in FIFO in advance during the CAS latency period

2nd Read access : Requested data was previously stored in the FIFO

Address matches with one of the address tags

AXI Master

FMC SDRAM Controller read request@0x04

Data 2

SDRAM

Device

(CAS = 1)

6 lines FIFO

@0x04 Data 2

@0x08

...

Data 3

...

Add. Tag read FIFO

Data read from FIFO

MS30445V2

During a write access or a Precharge command, the read FIFO is flushed and ready to be filled with new data.

After the first read request, if the current access was not performed to a row boundary, the

SDRAM controller anticipates the next read access during the CAS latency period and the

RPIPE delay (if configured). This is done by incrementing the memory address. The following condition must be met:

 RBURST control bit should be set to ‘1’ in the FMC_SDCR1 register.

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The address management depends on the next AHB request:

 Next AHB request is sequential (AHB Burst)

In this case, the SDRAM controller increments the address.

 Next AHB request is not sequential

– If the new read request targets the same row or another active row, the new address is passed to the memory and the master is stalled for the CAS latency period, waiting for the new data from memory.

– If the new read request does not target an active row, the SDRAM controller generates a Precharge command, activates the new row, and initiates a read command.

If the RURST is reset, the read FIFO is not used.

Row and bank boundary management

When a read or write access crosses a row boundary, if the next read or write access is sequential and the current access was performed to a row boundary, the SDRAM controller executes the following operations:

Precharge of the active row,

2. Activation of the new row

3. Start of a read/write command.

At a row boundary, the automatic activation of the next row is supported for all columns and data bus width configurations.

If necessary, the SDRAM controller inserts additional clock cycles between the following commands:

 Between Precharge and Active commands to match TRP parameter (only if the next access is in a different row in the same bank),

 Between Active and Read commands to match the TRCD parameter.

These parameters are defined into the FMC_SDTRx register.

Refer to Figure 54

and Figure 55

for read and burst write access crossing a row boundary.

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Figure 57. Read access crossing row boundary

TRP = 3 TRCD = 3 CAS latency = 2

SDNE

SDCLK

A[12:0]

NRAS

NCAS

NWE

Data[15:0]

SDNE

SDCLK

A[12:0]

Row n

Col a

NRAS

NCAS

NWE

Data[15:0]

Row n +1 Col a Col b

Dna

Precharge Activate Row Read Command

Figure 58. Write access crossing row boundary

Dn+1 a

MS34490V1

TRP = 3 TRCD = 3

Cna Colb Row n+1 Cola Colb

Dna Dnb

Precharge

Dn+1a Dn+1b

Activate Row Write command

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If the next access is sequential and the current access crosses a bank boundary, the

SDRAM controller activates the first row in the next bank and initiates a new read/write command. Two cases are possible:

 If the current bank is not the last one, the active row in the new bank must be precharged.At a bank boundary, the automatic activation of the next row is supported for all rows/columns and data bus width configuration.

 If the current bank is the last one and the selected SDRAM device is connected to

Bank 1, the automatic activation of the next row in device connected to SDRAM Bank2 is not supported. A PALL software command must be issused on Bank1 before any any access on Bank2.

SDRAM controller refresh cycle

The Auto-refresh command is used to refresh the SDRAM device content. The SDRAM controller periodically issues auto-refresh commands. An internal counter is loaded with the

COUNT value in the register FMC_SDRTR. This value defines the number of memory clock cycles between the refresh cycles (refresh rate). When this counter reaches zero, an internal pulse is generated.

If a memory access is ongoing, the auto-refresh request is delayed. However, if the memory access and the auto-refresh requests are generated simultaneously, the auto-refresh request takes precedence.

If the memory access occurs during an auto-refresh operation, the request is buffered and processed when the auto-refresh is complete.

If a new auto-refresh request occurs while the previous one was not served, the RE

(Refresh Error) bit is set in the Status register. An Interrupt is generated if it has been enabled (REIE = ‘1’).

If SDRAM lines are not in idle state (not all row are closed), the SDRAM controller generates a PALL (Precharge ALL) command before the auto-refresh.

If the Auto-refresh command is generated by the FMC_SDCMR Command Mode register

(Mode bits = ‘011’), a PALL command (Mode bits =’ 010’) must be issued first.

Two low-power modes are available:

 Self-refresh mode

The auto-refresh cycles are performed by the SDRAM device itself to retain data without external clocking.

 Power-down mode

The auto-refresh cycles are performed by the SDRAM controller.

Self-refresh mode

This mode is selected by setting the MODE bits to ‘101’ and by configuring the Target Bank bits (CTB1 and/or CTB2) in the FMC_SDCMR register.

The SDRAM clock stops running after a TRAS delay and the internal refresh timer stops counting only if one of the following conditions is met:

 A Self-refresh command is issued to both devices

 One of the devices is not activated (SDRAM bank is not initialized).

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Before entering Self-Refresh mode, the SDRAM controller automatically issues a PALL command.

If the Write data FIFO is not empty, all data are sent to the memory before activating the

Self-refresh mode and the BUSY status flag remains set.

In Self-refresh mode, all SDRAM device inputs become don’t care except for SDCKE which remains low.

The SDRAM device must remain in Self-refresh mode for a minimum period of time of

TRAS and can remain in Self-refresh mode for an indefinite period beyond that. To guarantee this minimum period, the BUSY status flag remains high after the Self-refresh activation during a TRAS delay.

As soon as an SDRAM device is selected, the SDRAM controller generates a sequence of commands to exit from Self-refresh mode. After the memory access, the selected device remains in Normal mode.

To exit from Self-refresh, the MODE bits must be set to ‘000’ (Normal mode) and the Target

Bank bits (CTB1 and/or CTB2) must be configured in the FMC_SDCMR register.

T0 T1

Figure 59. Self-refresh mode

Tn+1 T0+1 T0+2

SDCLK tRAS(min)

SDCKE

COMMAND

PRECHARGE

DOM/

DOML/DOMU

A0- A9

A11, A12

A10 ALL

BANKS

Data[15:0] Hi-Z

Precharge all active banks

NOP

AUTO

REFRESH

NOP or COMMAND

INHERIT

AUTO

REFRESH tRP tXSR

Enter Self-refresh mode

Exit Self-refresh mode

(restart refresh timebase)

CLK stable prior to existing

Self-refresh mode

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Power-down mode

This mode is selected by setting the MODE bits to ‘110’ and by configuring the Target Bank bits (CTB1 and/or CTB2) in the FMC_SDCMR register.

Figure 60. Power-down mode

SDCLK

SDCKE

COMMAND

NOP NOP ACTIVE

All banks idle

Enter Power-down

Input buffers gated off

Exit Power-down tRCD tRAS tRC

MS30451V1

If the Write data FIFO is not empty, all data are sent to the memory before activating the

Power-down mode.

As soon as an SDRAM device is selected, the SDRAM controller exits from the Power-down mode. After the memory access, the selected SDRAM device remains in Normal mode.

During Power-down mode, all SDRAM device input and output buffers are deactivated except for the SDCKE which remains low.

The SDRAM device cannot remain in Power-down mode longer than the refresh period and cannot perform the Auto-refresh cycles by itself. Therefore, the SDRAM controller carries out the refresh operation by executing the operations below:

Exit from Power-down mode and drive the SDCKE high

2. Generate the PALL command only if a row was active during Power-down mode

3. Generate the auto-refresh command

4. Drive SDCKE low again to return to Power-down mode.

To exit from Power-down mode, the MODE bits must be set to ‘000’ (Normal mode) and the

Target Bank bits (CTB1 and/or CTB2) must be configured in the FMC_SDCMR register.

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Address offset: 0x140+ 4* (x – 1), x = 1,2

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Reset value: 0x0000 02D0

This register contains the control parameters for each SDRAM memory bank

Res.

14 13

RPIPE[1:0] rw rw

RBURST rw

SDCLK

10 rw rw

WP rw

CAS

7 rw rw

NB rw

5 4 rw

MWID rw

3 rw

NR rw

1 rw

0 rw

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:13 RPIPE[1:0]: Read pipe

These bits define the delay, in KCK_FMC clock cycles, for reading data after CAS latency.

00: No KCK_FMC clock cycle delay

01: One KCK_FMC clock cycle delay

10: Two KCK_FMC clock cycle delay

11: reserved.

Note: The corresponding bits in the FMC_SDCR2 register is read only.

Bit 12 RBURST: Burst read

This bit enables Burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO.

0: single read requests are not managed as bursts

1: single read requests are always managed as bursts

Note: The corresponding bit in the FMC_SDCR2 register is don’t care.

Bits 11:10 SDCLK[1:0]: SDRAM clock configuration

These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized.

00: SDCLK clock disabled

01: reserved

10: SDCLK period = 2 x HCLK periods

11: SDCLK period = 3 x HCLK periods

Note: The corresponding bits in the FMC_SDCR2 register are don’t care.

Bit 9 WP: Write protection

This bit enables write mode access to the SDRAM bank.

0: Write accesses allowed

1: Write accesses ignored

Bits 8:7 CAS[1:0]: CAS Latency

This bits sets the SDRAM CAS latency in number of memory clock cycles

00: reserved.

01: 1 cycle

10: 2 cycles

11: 3 cycles

Bit 6 NB: Number of internal banks

This bit sets the number of internal banks.

0: Two internal Banks

1: Four internal Banks

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Note:

Bits 5:4 MWID[1:0]: Memory data bus width.

These bits define the memory device width.

00: 8 bits

01: 16 bits

10: reserved

11: reserved.

Bits 3:2 NR[1:0]: Number of row address bits

These bits define the number of bits of a row address.

00: 11 bit

01: 12 bits

10: 13 bits

11: reserved.

Bits 1:0 NC[1:0]: Number of column address bits

These bits define the number of bits of a column address.

00: 8 bits

01: 9 bits

10: 10 bits

11: 11 bits.

Before modifying the RBURST or RPIPE settings or disabling the SDCLK clock, the user must first send a PALL command to make sure ongoing operations are complete.

SDRAM Timing registers 1,2 (FMC_SDTR1,2)

Address offset: 0x148 + 4 * (x – 1), x = 1,2

Reset value: 0x0FFF FFFF

This register contains the timing parameters of each SDRAM bank

Res.

15 rw

Res.

TRC

13 rw rw

Res.

12 rw

27 rw

11 rw

TRCD

25 rw rw

TRAS

9 rw rw

24 rw

8 rw

23 rw

7 rw

22 21

TRP rw

TXSR rw

5 rw rw

20 rw

4 rw

19 rw

3 rw

18 17

TWR rw

TMRD rw

1 rw rw

16 rw

0 rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:24 TRCD[3:0]: Row to column delay

These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles.

0000: 1 cycle.

0001: 2 cycles

....

1111: 16 cycles

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Bits 23:20 TRP[3:0]: Row precharge delay

These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two

SDRAM devices are used, the TRP must be programmed with the timing of the slowest device.

0000: 1 cycle

0001: 2 cycles

....

1111: 16 cycles

Note: The corresponding bits in the FMC_SDTR2 register are don’t care.

Bits 19:16 TWR[3:0]: Recovery delay

These bits define the delay between a Write and a Precharge command in number of memory clock cycles.

0000: 1 cycle

0001: 2 cycles

....

1111: 16 cycles

Note: TWR must be programmed to match the write recovery time (t

WR datasheet, and to guarantee that:

) defined in the SDRAM

TWR ≥ TRAS - TRCD and TWR ≥ TRC - TRCD - TRP

Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be programmed to 0x1.

If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TWR timing corresponding to the slowest SDRAM device.

If only one SDRAM device is used, the TWR timing must be kept at reset value (0xF) for the not used bank.

Bits 15:12 TRC[3:0]: Row cycle delay

These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device.

0000: 1 cycle

0001: 2 cycles

....

1111: 16 cycles

Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM device datasheet.

Note: The corresponding bits in the FMC_SDTR2 register are don’t care.

Bits 11:8 TRAS[3:0]: Self refresh time

These bits define the minimum Self-refresh period in number of memory clock cycles.

0000: 1 cycle

0001: 2 cycles

....

1111: 16 cycles

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Note:

Bits 7:4 TXSR[3:0]: Exit Self-refresh delay

These bits define the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles.

0000: 1 cycle

0001: 2 cycles

....

1111: 16 cycles

Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TXSR timing corresponding to the slowest SDRAM device.

Bits 3:0 TMRD[3:0]: Load Mode Register to Active

These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles.

0000: 1 cycle

0001: 2 cycles

....

1111: 16 cycles

If two SDRAM devices are connected, all the accesses performed simultaneously to both devices by the Command Mode register (Load Mode Register command) are issued using the timing parameters configured for Bank 1 (TMRD and TRAS timings) in the FMC_SDTR1 register.

The TRP and TRC timings are only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP and TRC timings must be programmed with the timings of the slowest device.

SDRAM Command Mode register (FMC_SDCMR)

Address offset: 0x150

Reset value: 0x0000 0000

This register contains the command issued when the SDRAM device is accessed. This register is used to initialize the SDRAM device, and to activate the Self-refresh and the

Power-down modes. As soon as the MODE field is written, the command will be issued only to one or to both SDRAM banks according to CTB1 and CTB2 command bits. This register is the same for both SDRAM banks.

Res.

15 rw

Res.

14 rw

13 rw

Res.

MRD rw

Res.

11 rw

Res.

10 rw

Res.

9 rw

Res.

8 rw

Res.

7 6 rw

NRFS rw

21 rw

5 rw

20 19 18

MRD rw rw

4 3

CTB1 CTB2 rw rw rw

2 rw

17 rw

MODE rw

16 rw

0 rw

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:9 MRD[12:0]: Mode Register definition

This 13-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using the Load Mode Register command.

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Bits 8:5 NRFS[3:0]: Number of Auto-refresh

These bits define the number of consecutive Auto-refresh commands issued when MODE = ‘011’.

0000: 1 Auto-refresh cycle

0001: 2 Auto-refresh cycles

....

1110: 15 Auto-refresh cycles

1111: 16 Auto-refresh cycles

Bit 4 CTB1: Command Target Bank 1

This bit indicates whether the command will be issued to SDRAM Bank 1 or not.

0: Command not issued to SDRAM Bank 1

1: Command issued to SDRAM Bank 1

Bit 3 CTB2: Command Target Bank 2

This bit indicates whether the command will be issued to SDRAM Bank 2 or not.

0: Command not issued to SDRAM Bank 2

1: Command issued to SDRAM Bank 2

Bits 2:0 MODE[2:0]: Command mode

These bits define the command issued to the SDRAM device.

000: Normal Mode

001: Clock Configuration Enable

010: PALL (“All Bank Precharge”) command

011: Auto-refresh command

100: Load Mode Register

101: Self-refresh command

110: Power-down command

111: Reserved

Note: When a command is issued, at least one Command Target Bank bit ( CTB1 or CTB2) must be set otherwise the command will be ignored.

Note: If two SDRAM banks are used, the Auto-refresh and PALL command must be issued simultaneously to the two devices with CTB1 and CTB2 bits set otherwise the command will be ignored.

Note: If only one SDRAM bank is used and a command is issued with it’s associated CTB bit set, the other CTB bit of the the unused bank must be kept to 0.

SDRAM Refresh Timer register (FMC_SDRTR)

Address offset:0x154

Reset value: 0x0000 0000

This register sets the refresh rate in number of SDCLK clock cycles between the refresh cycles by configuring the Refresh Timer Count value.

Refresh rate =    SDRAM clock frequency

 – 20 COUNT = 

Example

Refresh rate =  where 64 ms is the SDRAM refresh period.

 = 7.81

 s

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Res.

7.81

 s 60MHz = 468.6

The refresh rate must be increased by 20 SDRAM clock cycles (as in the above example) to obtain a safe margin if an internal refresh request occurs when a read request has been accepted. It corresponds to a COUNT value of ‘0000111000000’ (448).

This 13-bit field is loaded into a timer which is decremented using the SDRAM clock. This timer generates a refresh pulse when zero is reached. The COUNT value must be set at least to 41 SDRAM clock cycles.

As soon as the FMC_SDRTR register is programmed, the timer starts counting. If the value programmed in the register is ’0’, no refresh is carried out. This register must not be reprogrammed after the initialization procedure to avoid modifying the refresh rate.

Each time a refresh pulse is generated, this 13-bit COUNT field is reloaded into the counter.

If a memory access is in progress, the Auto-refresh request is delayed. However, if the memory access and Auto-refresh requests are generated simultaneously, the Auto-refresh takes precedence. If the memory access occurs during a refresh operation, the request is buffered to be processed when the refresh is complete.

This register is common to SDRAM bank 1 and bank 2.

Res.

REIE rw

13 rw

12 rw

11 rw

10 rw

9 rw

8 rw

COUNT rw

6 rw

5 rw

4 rw

3 rw

2 rw

1 rw

CRE w

Bits 31: 15 Reserved, must be kept at reset value.

Bit 14 REIE: RES Interrupt Enable

0: Interrupt is disabled

1: An Interrupt is generated if RE = 1

Bits 13:1 COUNT[12:0]: Refresh Timer Count

This 13-bit field defines the refresh rate of the SDRAM device. It is expressed in number of memory clock cycles. It must be set at least to 41 SDRAM clock cycles (0x29).

Refresh rate = (COUNT + 1) x SDRAM frequency clock

COUNT = (SDRAM refresh period / Number of rows) - 20

Bit 0 CRE: Clear Refresh error flag

This bit is used to clear the Refresh Error Flag (RE) in the Status Register.

0: no effect

1: Refresh Error flag is cleared

Note: The programmed COUNT value must not be equal to the sum of the following timings:

TWR+TRP+TRC+TRCD+4 memory clock cycles.

SDRAM Status register (FMC_SDSR)

Address offset: 0x158

Reset value: 0x0000 0000

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Res.

BUSY r

11.8.6 FMC register map

Table 80. FMC register map and reset values

Offset Register

MODES2

3 r r

MODES1

1 r r

Bits 31:5 Reserved, must be kept at reset value.

Bit 5 BUSY: Busy status

This bit defines the status of the SDRAM controller after a Command Mode request

0: SDRAM Controller is ready to accept a new request

1; SDRAM Controller is not ready to accept a new request

Bits 4:3 MODES2[1:0]: Status Mode for Bank 2

This bit defines the Status Mode of SDRAM Bank 2.

00: Normal Mode

01: Self-refresh mode

10: Power-down mode

Bits 2:1 MODES1[1:0]: Status Mode for Bank 1

This bit defines the Status Mode of SDRAM Bank 1.

00: Normal Mode

01: Self-refresh mode

10: Power-down mode

Bit 0 RE: Refresh error flag

0: No refresh error has been detected

1: A refresh error has been detected

An interrupt is generated if REIE = 1 and RE = 1

RE r

0x00

FMC_BCR1

Reset value

0x08

FMC_BCR2

Reset value

0x10

FMC_BCR3

Reset value

CPSIZE

[2:0]

0 0 0 0 0 0 0 0 1 1 0

CPSIZE

[2:0]

0 0 0 0 0 0 1 1 0

CPSIZE

[2:0]

0 0 0 0 0 0 1 1 0

0 0

MWID

[1:0]

MTYP

[1:0]

1 0 1 1 0 1 1

MWID

[1:0]

MTYP

[1:0]

1 0 1 0 0 1 0

MWID

[1:0]

MTYP

[1:0]

1 0 1 0 0 1 0

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0x18

FMC_BCR4

Reset value

0x04

FMC_BTR1

Reset value

0x0C

FMC_BTR2

Reset value

0x14

FMC_BTR3

Reset value

0x1C

FMC_BTR4

Reset value

0x104

FMC_BWTR1

Reset value

0x10C

FMC_BWTR2

Reset value

0x114

FMC_BWTR3

Reset value

0x11C

FMC_BWTR4

0x80

0x84

Reset value

FMC_PCR

Reset value

FMC_SR

Reset value

Flexible memory controller (FMC)

Table 80. FMC register map and reset values (continued)

Offset Register

RM0390

CPSIZE

[2:0]

0 0 0 0 0 0 1 1 0

DATLAT[3:0] CLKDIV[3:0]

BUSTURN[3:0

]

DATAST[7:0]

0 0 1

MWID

[1:0]

0 1

MTYP

[1:0]

0 0 1 0

ADDHLD[3:0] ADDSET[3:0]

0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

DATLAT[3:0] CLKDIV[3:0]

BUSTURN[3:0

]

DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]

0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

DATLAT[3:0] CLKDIV[3:0]

BUSTURN[3:0

]

DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]

0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

DATLAT[3:0] CLKDIV[3:0]

BUSTURN[3:0

]

DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]

0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

BUSTURN[3:0

]

DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]

0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

BUSTURN[3:0

]

DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

BUSTURN

[3:0]

DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]

0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

BUSTURN

[3:0]

DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

ECCPS

[2:0]

TAR[3:0] TCLR[3:0]

0 0 0 0 0 0 0 0 0 0 0 0

PWID

[1:0]

0 1 1 0 0

1 0 0 0 0 0 0

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Table 80. FMC register map and reset values (continued)

Offset Register

0x88

0x8C

0x94

0x140

0x144

0x148

0x14C

0x150

0x154

FMC_PMEM MEMHIZx[7:0] MEMHOLDx[7:0] MEMWAITx[7:0] MEMSETx[7:0]

Reset value 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0

FMC_PATT ATTHIZ[7:0] ATTHOLD[7:0] ATTWAIT[7:0] ATTSET[7:0]

Reset value 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0

FMC_ECCR ECCx[31:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FMC_SDCR1

RPIPE

[1:0]

SDCLK

[1:0]

CAS

[1:0]

MWID

[1:0]

Reset value

FMC_SDCR2

Reset value

FMC_SDTR1

Reset value

FMC_SDTR2

Reset value

FMC_SDCMR

Reset value

FMC_SDRTR

Reset value

0 0 0 1 1 0 1 0 0 1 0 0 0 0 0

SDCLK

[1:0]

CAS

[1:0]

MWID

[1:0]

TRCD[3:0] TRP[3:0] TWR[3:0] TRC[3:0]

0 1 1 0 1 0 0 1 0 0 0 0 0

TRAS[3:0] TXSR[3:0] TMRD[3:0]

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

TRCD[3:0] TRP[3:0] TWR[3:0] TRC[3:0] TRAS[3:0] TXSR[3:0] TMRD[3:0]

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

MRD[12:0] NRFS[3:0] MODE[2:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

COUNT[12:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x158

FMC_SDSR

Reset value 0 0 0 0 0

Refer to Section 2.2 on page 56 for the register boundary addresses.

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Quad-SPI interface (QUADSPI)

12 Quad-SPI interface (QUADSPI)

RM0390

12.1 Introduction

The QUADSPI is a specialized communication interface targeting single, dual or quad SPI

Flash memories. It can operate in any of the three following modes:

 indirect mode: all the operations are performed using the QUADSPI registers

 status polling mode: the external Flash memory status register is periodically read and an interrupt can be generated in case of flag setting

 memory-mapped mode: the external Flash memory is mapped to the device address space and is seen by the system as if it was an internal memory

Both throughput and capacity can be increased two-fold using dual-flash mode, where two

Quad-SPI Flash memories are accessed simultaneously.

12.2 QUADSPI main features

 Three functional modes: indirect, status-polling, and memory-mapped

 Dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two

Flash memories in parallel.

 SDR and DDR support

 Fully programmable opcode for both indirect and memory mapped mode

 Fully programmable frame format for both indirect and memory mapped mode

 Integrated FIFO for reception and transmission

 8, 16, and 32-bit data accesses are allowed

 DMA channel for indirect mode operations

 Interrupt generation on FIFO threshold, timeout, operation complete, and access error

12.3 QUADSPI functional description

12.3.1 QUADSPI block diagram

AHB

Figure 61. QUADSPI block diagram when dual-flash mode is disabled

QUADSPI

Registers / control

Clock management

FIFO Shift register

CLK

BK1_IO0/SO

BK1_IO1/SI

BK1_IO2

BK1_IO3

BK1_nCS

SPI FLASH

CLK

Q0/SI

Q1/SO

Q2/WP

Q3/HOLD

MS35315V1

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AHB

Figure 62. QUADSPI block diagram when dual-flash mode is enabled

QUADSPI

Registers / control

Clock management

FIFO

CLK

BK1_IO0/SO

BK1_IO1/SI

BK1_IO2

BK1_IO3

BK1_nCS

SPI FLASH 1

CLK

Q0/SI

Q1/SO

Q2/WP

Q3/HOLD

Shift register

BK2_IO0/SO

BK2_IO1/SI

BK2_IO2

BK2_IO3

BK2_nCS

SPI FLASH 2

CLK

Q0/SI

Q1/SO

Q2/WP

Q3/HOLD

MS35316V1

Table 81 lists the QUADSPI pins, six for interfacing with a single Flash memory, or 10 to 11

for interfacing with two Flash memories (FLASH 1 and FLASH 2) in dual-flash mode.

Signal name

CLK

BK1_IO0/SO

BK1_IO1/SI

BK1_IO2

BK1_IO3

BK2_IO0/SO

BK2_IO1/SI

BK2_IO2

BK2_IO3

BK1_nCS

BK2_nCS

Table 81. QUADSPI pins

Signal type

Digital output

Digital input/output

Digital output

Description

Clock to FLASH 1 and FLASH 2

Bidirectional IO in dual/quad modes or serial output in single mode, for FLASH 1

Bidirectional IO in dual/quad modes or serial input in single mode, for FLASH 1

Bidirectional IO in quad mode, for FLASH 1

Bidirectional IO in dual/quad modes or serial output in single mode, for FLASH 2

Bidirectional IO in dual/quad modes or serial input in single mode, for FLASH 2

Bidirectional IO in quad mode, for FLASH 2

Chip select (active low) for FLASH 1. Can also be used for FLASH 2 if QUADSPI is always used in dual-flash mode.

Chip select (active low) for FLASH 2. Can also be used for FLASH 1 if QUADSPI is always used in dual-flash mode.

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12.3.3 QUADSPI command sequence

The QUADSPI communicates with the Flash memory using commands. Each command can include 5 phases: instruction, address, alternate byte, dummy, data. Any of these phases can be configured to be skipped, but at least one of the instruction, address, alternate byte, or data phase must be present.

nCS falls before the start of each command and rises again after each command finishes.

Figure 63. An example of a read command in quad mode

Instruction Address Alt.

Dummy Data nCS

SCLK

IO0

IO1

IO2

IO3

7 6 5 4 3 2 1 0 4

6 2

7 3

A23-16

6 2

7 3

A15-8

6 2

A7-0

6 2

M7-0

IO switch from output to input

6 2

7 3

Byte 1

6 2

7 3

Byte 2

MS35317V1

Instruction phase

During this phase, an 8-bit instruction, configured in INSTRUCTION field of

QUADSPI_CCR[7:0] register, is sent to the Flash memory, specifying the type of operation to be performed.

Though most Flash memories can receive instructions only one bit at a time from the

IO0/SO signal (single SPI mode), the instruction phase can optionally send 2 bits at a time

(over IO0/IO1 in dual SPI mode) or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI mode). This can be configured using the IMODE[1:0] field of QUADSPI_CCR[9:8] register.

When IMODE = 00, the instruction phase is skipped, and the command sequence starts with the address phase, if present.

Address phase

In the address phase, 1-4 bytes are sent to the Flash memory to indicate the address of the operation. The number of address bytes to be sent is configured in the ADSIZE[1:0] field of

QUADSPI_CCR[13:12] register. In indirect and automatic-polling modes, the address bytes to be sent are specified in the ADDRESS[31:0] field of QUADSPI_AR register, while in memory-mapped mode the address is given directly via the AHB (from the Cortex ® or from a DMA).

The address phase can send 1 bit at a time (over SO in single SPI mode), 2 bits at a time

(over IO0/IO1 in dual SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI mode). This can be configured using the ADMODE[1:0] field of QUADSPI_CCR[11:10] register.

When ADMODE = 00, the address phase is skipped, and the command sequence proceeds directly to the next phase, if any.

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RM0390 Quad-SPI interface (QUADSPI)

Alternate-bytes phase

In the alternate-bytes phase, 1-4 bytes are sent to the Flash memory, generally to control the mode of operation. The number of alternate bytes to be sent is configured in the

ABSIZE[1:0] field of QUADSPI_CCR[17:16] register. The bytes to be sent are specified in the QUADSPI_ABR register.

The alternate-bytes phase can send 1 bit at a time (over SO in single SPI mode), 2 bits at a time (over IO0/IO1 in dual SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI mode). This can be configured using the ABMODE[1:0] field of QUADSPI_CCR[15:14] register.

When ABMODE = 00, the alternate-bytes phase is skipped, and the command sequence proceeds directly to the next phase, if any.

There may be times when only a single nibble needs to be sent during the alternate-byte phase rather than a full byte, such as when dual-mode is used and only two cycles are used for the alternate bytes. In this case, firmware can use quad-mode (ABMODE = 11) and send a byte with bits 7 and 3 of ALTERNATE set to ‘1’ (keeping the IO3 line high), and bits 6 and

2 set to ‘0’ (keeping the IO2 line low). In this case the upper two bits of the nibble to be sent are placed in bits 4:3 of ALTERNATE while the lower two bits are placed in bits 1 and 0. For example, if the nibble 2 (0010) is to be sent over IO0/IO1, then ALTERNATE should be set to 0x8A (1000_1010).

Dummy-cycles phase

In the dummy-cycles phase, 1-31 cycles are given without any data being sent or received, in order to allow the Flash memory the time to prepare for the data phase when higher clock frequencies are used. The number of cycles given during this phase is specified in the

DCYC[4:0] field of QUADSPI_CCR[22:18] register. In both SDR and DDR modes, the duration is specified as a number of full CLK cycles.

When DCYC is zero, the dummy-cycles phase is skipped, and the command sequence proceeds directly to the data phase, if present.

The operating mode of the dummy-cycles phase is determined by DMODE.

In order to assure enough “turn-around” time for changing the data signals from output mode to input mode, there must be at least one dummy cycle when using dual or quad mode to receive data from the Flash memory.

Data phase

During the data phase, any number of bytes can be sent to, or received from the Flash memory.

In indirect and automatic-polling modes, the number of bytes to be sent/received is specified in the QUADSPI_DLR register.

In indirect write mode the data to be sent to the Flash memory must be written to the

QUADSPI_DR register, while in indirect read mode the data received from the Flash memory is obtained by reading from the QUADSPI_DR register.

In memory-mapped mode, the data which is read is sent back directly over the AHB to the

Cortex or to a DMA.

The data phase can send/receive 1 bit at a time (over SO/SI in single SPI mode), 2 bits at a time (over IO0/IO1 in dual SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI

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Quad-SPI interface (QUADSPI) RM0390 mode). This can be configured using the ABMODE[1:0] field of QUADSPI_CCR[15:14] register.

When DMODE = 00, the data phase is skipped, and the command sequence finishes immediately by raising nCS. This configuration must only be used in only indirect write mode.

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Single SPI mode

Legacy SPI mode allows just a single bit to be sent/received serially. In this mode, data is sent to the Flash memory over the SO signal (whose I/O shared with IO0). Data received from the Flash memory arrives via SI (whose I/O shared with IO1).

The different phases can each be configured separately to use this single bit mode by setting the IMODE/ADMODE/ABMODE/DMODE fields (in QUADSPI_CCR) to 01.

In each phase which is configured in single mode:

 IO0 (SO) is in output mode

 IO1 (SI) is in input mode (high impedance)

 IO2 is in output mode and forced to ‘0’

 IO3 is in output mode and forced to ‘1’ (to deactivate the “hold” function)

This is the case even for the dummy phase if DMODE = 01.

Dual SPI mode

In dual SPI mode, two bits are sent/received simultaneously over the IO0/IO1 signals.

The different phases can each be configured separately to use dual SPI mode by setting the

IMODE/ADMODE/ABMODE/DMODE fields of QUADSPI_CCR register to 10.

In each phase which is configured in dual mode:

 IO0/IO1 are at high-impedance (input) during the data phase for read operations, and outputs in all other cases

 IO2 is in output mode and forced to ‘0’

 IO3 is in output mode and forced to ‘1’

In the dummy phase when DMODE = 01, IO0/IO1 are always high-impedance.

Quad SPI mode

In quad SPI mode, four bits are sent/received simultaneously over the IO0/IO1/IO2/IO3 signals.

The different phases can each be configured separately to use quad SPI mode by setting the IMODE/ADMODE/ABMODE/DMODE fields of QUADSPI_CCR register to 11.

In each phase which is configured in quad mode, IO0/IO1/IO2/IO3 are all are at highimpedance (input) during the data phase for read operations, and outputs in all other cases.

In the dummy phase when DMODE = 11, IO0/IO1/IO2/IO3 are all high-impedance.

IO2 and IO3 are used only in Quad SPI mode. If none of the phases are configured to use

Quad SPI mode, then the pins corresponding to IO2 and IO3 can be used for other functions even while QUADSPI is active.

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RM0390 Quad-SPI interface (QUADSPI)

SDR mode

By default, the DDRM bit (QUADSPI_CCR[31]) is 0 and the QUADSPI operates in single data rate (SDR) mode.

In SDR mode, when the QUADSPI is driving the IO0/SO, IO1, IO2, IO3 signals, these signals transition only with the falling edge of CLK.

When receiving data in SDR mode, the QUADSPI assumes that the Flash memories also send the data using CLK’s falling edge. By default (when SSHIFT = 0), the signals are sampled using the following (rising) edge of CLK.

DDR mode

When the DDRM bit (QUADSPI_CCR[31]) is set to 1, the QUADSPI operates in double data rate (DDR) mode.

In DDR mode, when the QUADSPI is driving the IO0/SO, IO1, IO2, IO3 signals in the address/alternate-byte/data phases, a bit is sent on each of the falling and rising edges of

CLK.

The instruction phase is not affected by DDRM. The instruction is always sent using CLK’s falling edge.

When receiving data in DDR mode, the QUADSPI assumes that the Flash memories also send the data using both rising and falling CLK edges. When DDRM = 1, firmware must clear SSHIFT bit (bit 4 of QUADSPI_CR). Thus, the signals are sampled one half of a CLK cycle later (on the following, opposite edge).

Figure 64. An example of a DDR command in quad mode

Instruction Address Alt.

Dummy Data nCS

SCLK

IO0

IO1

IO2

IO3

7 6 5 4 3 2 1 0 4 0

5 4

4 0

5 4

4 0

5 4

4 0

5 4

4 0 4 0

5 4 5 4

6 2 6 2 6 2 6 2 6 2 6 2

7 3 7 3 7 3 7 3

A23-16A15-8 A7-0 M7-0

IO switch from output to input

7 3 7 3

Byte1 Byte2

MS35318V1

Dual-flash mode

When the DFM bit (bit 6 of QUADSPI_CR) is 1, the QUADSPI is in dual-flash mode, where two external quad SPI Flash memories (FLASH 1 and FLASH 2) are used in order to send/receive 8 bits (or 16 bits in DDR mode) every cycle, effectively doubling the throughput as well as the capacity.

Each of the Flash memories use the same CLK and optionally the same nCS signals, but each have separate IO0, IO1, IO2, and IO3 signals.

Dual-flash mode can be used in conjunction with single-bit, dual-bit, and quad-bit modes, as well as with either SDR or DDR mode.

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The Flash memory size, as specified in FSIZE[4:0] (QUADSPI_DCR[20:16]), should reflect the total Flash memory capacity, which is double the size of one individual component.

If address X is even, then the byte which the QUADSPI gives for address X is the byte at the address X/2 of FLASH 1, and the byte which the QUADSPI gives for address X+1 is the byte at the address X/2 of FLASH 2. In other words, bytes at even addresses are all stored in FLASH 1 and bytes at odd addresses are all stored in FLASH 2.

When reading the Flash memories status registers in dual-flash mode, twice as many bytes should be read compared to doing the same read in single-flash mode. This means that if each Flash memory gives 8 valid bits after the instruction for fetching the status register, then the QUADSPI must be configured with a data length of 2 bytes (16 bits), and the

QUADSPI receives one byte from each Flash memory. If each Flash memory gives a status of 16 bits, then the QUADSPI must be configured to read 4 bytes to get all the status bits of both Flash memories in dual-flash mode. The least-significant byte of the result (in the data register) is the least-significant byte of FLASH 1 status register, while the next byte is the least-significant byte of FLASH 2 status register. Then, the third byte of the data register is

FLASH 1 second byte, while the forth byte is FLASH 2 second byte (in the case that the

Flash memories have 16-bit status registers).

An even number of bytes must always be accessed in dual-flash mode. For this reason, bit

0 of the data length field (QUADSPI_DLR[0]) is stuck at 1 when DRM = 1.

In dual-flash mode, the behavior of FLASH 1 interface signals are basically the same as in normal mode. FLASH 2 interface signals have exactly the same waveforms as FLASH 1 during the instruction, address, alternate-byte, and dummy-cycles phases. In other words, each Flash memory always receives the same instruction and the same address. Then, during the data phase, the BK1_IOx and BK2_IOx buses are both transferring data in parallel, but the data that are sent to (or received from) FLASH 1 are distinct from those of

FLASH 2.

12.3.5 QUADSPI indirect mode

When in indirect mode, commands are started by writing to QUADSPI registers and data is transferred by writing or reading the data register, in the same way as for other communication peripherals.

When FMODE = 00 (QUADSPI_CCR[27:26]), the QUADSPI is in indirect write mode, where bytes are sent to the Flash memory during the data phase. Data are provided by writing to the data register (QUADSPI_DR).

When FMODE = 01, the QUADSPI is in indirect read mode, where bytes are received from the Flash memory during the data phase. Data are recovered by reading QUADSPI_DR.

The number of bytes to be read/written is specified in the data length register

(QUADSPI_DLR). If QUADSPI_DLR = 0xFFFF_FFFF (all 1’s), then the data length is considered undefined and the QUADSPI simply continues to transfer data until the end of

Flash memory (as defined by FSIZE) is reached. If no bytes are to be transferred, DMODE

(QUADSPI_CCR[25:24]) should be set to 00.

If QUADSPI_DLR = 0xFFFF_FFFF and FSIZE = 0x1F (max value indicating a 4GB Flash memory), then in this special case the transfers continue indefinitely, stopping only after an abort request or after the QUADSPI is disabled. After the last memory address is read (at address 0xFFFF_FFFF), reading continues with address = 0x0000_0000.

When the programmed number of bytes to be transmitted or received is reached, TCF is set and an interrupt is generated if TCIE = 1. In the case of undefined number of data, the TCF

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RM0390 Rev 6

RM0390 Quad-SPI interface (QUADSPI) is set when the limit of the external SPI memory is reached according to the Flash memory size defined in the QUADSPI_CR.

Triggering the start of a command

Essentially, a command starts as soon as firmware gives the last information that is necessary for this command. Depending on the QUADSPI configuration, there are three different ways to trigger the start of a command in indirect mode. The commands starts immediately after:

a write is performed to INSTRUCTION[7:0] (QUADSPI_CCR), if no address is necessary (when ADMODE = 00) and if no data needs to be provided by the firmware

(when FMODE = 01 or DMODE = 00)

2. a write is performed to ADDRESS[31:0] (QUADSPI_AR), if an address is necessary

(when ADMODE != 00) and if no data needs to be provided by the firmware (when

FMODE = 01 or DMODE = 00)

3. a write is performed to DATA[31:0] (QUADSPI_DR), if an address is necessary (when

ADMODE != 00) and if data needs to be provided by the firmware (when FMODE = 00 and DMODE != 00)

Writes to the alternate byte register (QUADSPI_ABR) never trigger the communication start.

If alternate bytes are required, they must be programmed before.

As soon as a command is started, the BUSY bit (bit 5 of QUADSPI_SR) is automatically set.

FIFO and data management

In indirect mode, data go through a 32-byte FIFO which is internal to the QUADSPI.

FLEVEL[5:0] (QUADSPI_SR[13:8]) indicates how many bytes are currently being held in the FIFO.

In indirect write mode (FMODE = 00), firmware adds data to the FIFO when it writes

QUADSPI_DR. Word writes add 4 bytes to the FIFO, halfword writes add 2 bytes, and byte writes add only 1 byte. If firmware adds too many bytes to the FIFO (more than is indicated by DL[31:0]), the extra bytes are flushed from the FIFO at the end of the write operation

(when TCF is set).

Byte/halfword accesses to QUADSPI_DR must be done only to the least significant byte/halfword of the 32-bit register.

FTHRES[3:0] is used to define a FIFO threshold. When the threshold is reached, the FTF

(FIFO threshold flag) is set. In indirect read mode, FTF is set when the number of valid bytes to be read from the FIFO is above the threshold. FTF is also set if there are data in the

FIFO after the last byte is read from the Flash memory, regardless of the FTHRES setting.

In indirect write mode, FTF is set when the number of empty bytes in the FIFO is above the threshold.

If FTIE = 1, there is an interrupt when FTF is set. If DMAEN = 1, a DMA transfer is initiated when FTF is set. FTF is cleared by HW as soon as the threshold condition is no longer true

(after enough data is transferred by the CPU or DMA).

In indirect read mode when the FIFO becomes full, the QUADSPI temporarily stops reading bytes from the Flash memory to avoid an overrun. Note that the reading of the Flash memory does not restart until 4 bytes become vacant in the FIFO (when FLEVEL ≤ 11).

Thus, when FTHRES ≥ 13, the application must take care to read enough bytes to assure that the QUADSPI starts retrieving data from the Flash memory again. Otherwise, the FTF flag stays at '0' as long as 11 < FLEVEL < FTHRES.

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12.3.6 QUADSPI status flag polling mode

In automatic-polling mode, the QUADSPI periodically starts a command to read a defined number of status bytes (up to 4). The received bytes can be masked to isolate some status bits and an interrupt can be generated when the selected bits have a defined value.

The accesses to the Flash memory begin in the same way as in indirect read mode: if no address is required (AMODE = 00), accesses begin as soon as the QUADSPI_CCR is written. Otherwise, if an address is required, the first access begins when QUADSPI_AR is written. BUSY goes high at this point and stays high even between the periodic accesses.

The contents of MASK[31:0] (QUADSPI_PSMAR) are used to mask the data from the Flash memory in automatic-polling mode. If the MASK[n] = 0, then bit n of the result is masked and not considered. If MASK[n] = 1, and the content of bit[n] is the same as MATCH[n]

(QUADSPI_PSMAR), then there is a match for bit n.

If the polling match mode bit (PMM, bit 23 of QUADSPI_CR) is 0, then “AND” match mode is activated. This means status match flag (SMF) is set only when there is a match on all of the unmasked bits.

If PMM = 1, then “OR” match mode is activated. This means SMF is set if there is a match on any of the unmasked bits.

An interrupt is called when SMF is set if SMIE = 1.

If the automatic-polling-mode-stop (APMS) bit is set, operation stops and BUSY goes to 0 as soon as a match is detected. Otherwise, BUSY stays at ‘1’ and the periodic accesses continue until there is an abort or the QUADSPI is disabled (EN = 0).

The data register (QUADSPI_DR) contains the latest received status bytes (the FIFO is deactivated). The content of the data register is not affected by the masking used in the matching logic. The FTF status bit is set as soon as a new reading of the status is complete, and FTF is cleared as soon as the data is read.

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When configured in memory-mapped mode, the external SPI device is seen as an internal memory.

It is forbidden to access QUADSPI Flash bank area before having properly configured and enabled the QUADSPI peripheral.

No more than 256MB can addressed even if the Flash memory capacity is larger.

If an access is made to an address outside of the range defined by FSIZE but still within the

256MB range, then a bus error is given. The effect of this error depends on the bus master that attempted the access:

 If it is the Cortex

CPU, bus fault exception is generated when enabled (or a hard fault exception when bus fault is disabled)

 If it is a DMA, a DMA transfer error is generated and the corresponding DMA channel is automatically disabled.

Byte, halfword, and word access types are all supported.

Support for execute in place (XIP) operation is implemented, where the QUADSPI anticipates the next access and load in advance the byte at the following address. If the subsequent access is indeed made at a continuous address, the access is completed faster since the value is already prefetched.

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RM0390 Quad-SPI interface (QUADSPI)

By default, the QUADSPI never stops its prefetch operation, keeping the previous read operation active with nCS maintained low, even if no access to the Flash memory occurs for a long time. Since Flash memories tend to consume more when nCS is held low, the application might want to activate the timeout counter (TCEN = 1, bit 3 of QUADSPI_CR) so that nCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have elapsed without any access since when the FIFO becomes full with prefetch data.

BUSY goes high as soon as the first memory-mapped access occurs. Because of the prefetch operations, BUSY does not fall until there is a timeout, there is an abort, or the peripheral is disabled.

12.3.8 QUADSPI Flash memory configuration

The device configuration register (QUADSPI_DCR) can be used to specify the characteristics of the external SPI Flash memory.

The FSIZE[4:0] field defines the size of external memory using the following formula:

Number of bytes in Flash memory = 2 [FSIZE+1]

FSIZE+1 is effectively the number of address bits required to address the Flash memory.

The Flash memory capacity can be up to 4GB (addressed using 32 bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256MB.

If DFM = 1, FSIZE indicates the total capacity of the two Flash memories together.

When the QUADSPI executes two commands, one immediately after the other, it raises the chip select signal (nCS) high between the two commands for only one CLK cycle by default.

If the Flash memory requires more time between commands, the chip select high time

(CSHT) field can be used to specify the minimum number of CLK cycles (up to 8) that nCS must remain high.

The clock mode (CKMODE) bit indicates the CLK signal logic level in between commands

(when nCS = 1).

12.3.9 QUADSPI delayed data sampling

By default, the QUADSPI samples the data driven by the Flash memory one half of a CLK cycle after the Flash memory drives the signal.

In case of external signal delays, it may be beneficial to sample the data later. Using the

SSHIFT bit (bit 4 of QUADSPI_CR), the sampling of the data can be shifted by half of a CLK cycle.

Clock shifting is not supported in DDR mode: the SSHIFT bit must be clear when DDRM bit is set.

The QUADSPI configuration is done in two phases:

 QUADSPI IP configuration

 QUADSPI Flash memory configuration

Once configured and enabled, the QUADSPI can be used in one of its three operating modes: indirect mode, status-polling mode, or memory-mapped mode.

QUADSPI configuration

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The QUADSPI is configured using the QUADSPI_CR. The user shall configure the clock prescaler division factor and the sample shifting settings for the incoming data.

DDR mode can be set through the DDRM bit. When setting QUADSPI interface in DDR mode, the internal divider of kernel clock must be set with a division ratio of 2 or more. Once enabled, the address and the alternate bytes are sent on both clock edges and the data are sent/received on both clock edges. Regardless of the DDRM bit setting, instructions are always sent in SDR mode.

The DMA requests are enabled setting the DMAEN bit. In case of interrupt usage, their respective enable bit can be also set during this phase.

FIFO level for either DMA request generation or interrupt generation is programmed in the

FTHRES bits.

If timeout counter is needed, the TCEN bit can be set and the timeout value programmed in the QUADSPI_LPTR register.

Dual-flash mode can be activated by setting DFM to 1.

QUADSPI Flash memory configuration

The parameters related to the targeted external Flash memory are configured through the

QUADSPI_DCR register.The user shall program the Flash memory size in the FSIZE bits, the Chip Select minimum high time in the CSHT bits, and the functional mode (Mode 0 or

Mode 3) in the MODE bit.

The operating mode is selected using FMODE[1:0] (QUADSPI_CCR[27:26]).

Indirect mode procedure

When FMODE is programmed to 00, indirect write mode is selected and data can be sent to the Flash memory. With FMODE = 01, indirect read mode is selected where data can be read from the Flash memory.

When the QUADSPI is used in indirect mode, the frames are constructed in the following way:

Specify a number of data bytes to read or write in the QUADSPI_DLR.

2. Specify the frame format, mode and instruction code in the QUADSPI_CCR.

3. Specify optional alternate byte to be sent right after the address phase in the

QUADSPI_ABR.

4. Specify the operating mode in the QUADSPI_CR. If FMODE = 00 (indirect write mode) and DMAEN = 1, then QUADSPI_AR should be specified before QUADSPI_CR, because otherwise QUADSPI_DR might be written by the DMA before QUADSPI_AR is updated (if the DMA controller has already been enabled)

5. Specify the targeted address in the QUADSPI_AR.

6. Read/Write the data from/to the FIFO through the QUADSPI_DR.

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RM0390 Quad-SPI interface (QUADSPI)

When writing the control register (QUADSPI_CR) the user specifies the following settings:

 The enable bit (EN) set to ‘1’

 The DMA enable bit (DMAEN) for transferring data to/from RAM

 Timeout counter enable bit (TCEN)

 Sample shift setting (SSHIFT)

 FIFO threshold level (FTRHES) to indicate when the FTF flag should be set

 Interrupt enables

 Automatic polling mode parameters: match mode and stop mode (valid when

FMODE = 11)

 Clock prescaler

When writing the communication configuration register (QUADSPI_CCR) the user specifies the following parameters:

 The instruction byte through the INSTRUCTION bits

 The way the instruction has to be sent through the IMODE bits (1/2/4 lines)

 The way the address has to be sent through the ADMODE bits (None/1/2/4 lines)

 The address size (8/16/24/32-bit) through the ADSIZE bits

 The way the alternate bytes have to be sent through the ABMODE (None/1/2/4 lines)

 The alternate bytes number (1/2/3/4) through the ABSIZE bits

 The presence or not of dummy bytes through the DBMODE bit

 The number of dummy bytes through the DCYC bits

 The way the data have to be sent/received (None/1/2/4 lines) through the DMODE bits

If neither the address register (QUADSPI_AR) nor the data register (QUADSPI_DR) need to be updated for a particular command, then the command sequence starts as soon as

QUADSPI_CCR is written. This is the case when both ADMODE and DMODE are 00, or if just ADMODE = 00 when in indirect read mode (FMODE = 01).

When an address is required (ADMODE is not 00) and the data register does not need to be written (when FMODE = 01 or DMODE = 00), the command sequence starts as soon as the address is updated with a write to QUADSPI_AR.

In case of data transmission (FMODE = 00 and DMODE! = 00), the communication start is triggered by a write in the FIFO through QUADSPI_DR.

Status flag polling mode

The status flag polling mode is enabled setting the FMODE field (QUADSPI_CCR[27:26]) to

10. In this mode, the programmed frame is sent and the data retrieved periodically.

The maximum amount of data read in each frame is 4 bytes. If more data is requested in

QUADSPI_DLR, it is ignored and only 4 bytes are read.

The periodicity is specified in the QUADSPI_PISR register.

Once the status data is retrieved, it can internally be processed i order to:

 set the status match flag and generate an interrupt if enabled

 stop automatically the periodic retrieving of the status bytes

The received value can be masked with the value stored in the QUADSPI_PSMKR and

ORed or ANDed with the value stored in the QUADSPI_PSMAR.

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In case of match, the status match flag is set and an interrupt is generated if enabled, and the QUADSPI can be automatically stopped if the AMPS bit is set.

In any case, the latest retrieved value is available in the QUADSPI_DR.

Memory-mapped mode

In memory-mapped mode, the external Flash memory is seen as internal memory but with some latency during accesses. Only read operations are allowed to the external Flash memory in this mode.

Memory-mapped mode is entered by setting the FMODE to 11 in the QUADSPI_CCR register.

The programmed instruction and frame is sent when a master is accessing the memory mapped space.

The FIFO is used as a prefetch buffer to anticipate linear reads. Any access to

QUADSPI_DR in this mode returns zero.

The data length register (QUADSPI_DLR) has no meaning in memory-mapped mode.

12.3.12 Sending the instruction only once

Some Flash memories (e.g. Winbound) might provide a mode where an instruction must be sent only with the first command sequence, while subsequent commands start directly with the address. One can take advantage of such a feature using the SIOO bit

(QUADSPI_CCR[28]).

SIOO is valid for all functional modes (indirect, automatic polling, and memory-mapped). If the SIOO bit is set, the instruction is sent only for the first command following a write to

QUADSPI_CCR. Subsequent command sequences skip the instruction phase, until there is a write to QUADSPI_CCR.

SIOO has no effect when IMODE = 00 (no instruction).

An error can be generated in the following case:

 In indirect mode or status flag polling mode when a wrong address is programmed in the QUADSPI_AR (according to the Flash memory size defined by FSIZE[4:0] in the

QUADSPI_DCR): this sets the TEF and an interrupt is generated if enabled.

 Also in indirect mode, if the address plus the data length exceeds the Flash memory size, TEF is set as soon as the access is triggered.

 In memory-mapped mode, when an out of range access is done by a master or when the QUADSPI is disabled: this generates a bus error as a response to the faulty bus master request.

 When a master is accessing the memory mapped space while the memory mapped mode is disabled: this generates a bus error as a response to the faulty bus master request.

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Once the QUADSPI starts an operation with the Flash memory, the BUSY bit is automatically set in the QUADSPI_SR.

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RM0390

Note:

Quad-SPI interface (QUADSPI)

In indirect mode, the BUSY bit is reset once the QUADSPI has completed the requested command sequence and the FIFO is empty.

In automatic-polling mode, BUSY goes low only after the last periodic access is complete, due to a match when APMS = 1, or due to an abort.

After the first access in memory-mapped mode, BUSY goes low only on a timeout event or on an abort.

Any operation can be aborted by setting the ABORT bit in the QUADSPI_CR. Once the abort is completed, the BUSY bit and the ABORT bit are automatically reset, and the FIFO is flushed.

Some Flash memories might misbehave if a write operation to a status registers is aborted.

By default, nCS is high, deselecting the external Flash memory. nCS falls before an operation begins and rises as soon as it finishes.

When CKMODE = 0 (“mode0”, where CLK stays low when no operation is in progress) nCS falls one CLK cycle before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation final rising CLK edge, as shown in

Figure 65

Figure 65. nCS when CKMODE = 0 (T = CLK period)

T T nCS

SCLK

MS35319V1

When CKMODE=1 (“mode3”, where CLK goes high when no operation is in progress) and

DDRM=0 (SDR mode), nCS still falls one CLK cycle before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation final rising CLK edge, as shown in

Figure 66

Figure 66. nCS when CKMODE = 1 in SDR mode (T = CLK period)

T T nCS

SCLK

MS35320V1

When CKMODE = 1 (“mode3”) and DDRM = 1 (DDR mode), nCS falls one CLK cycle before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation

final active rising CLK edge, as shown in Figure 67 . Because DDR operations must finish

with a falling edge, CLK is low when nCS rises, and CLK rises back up one half of a CLK cycle afterwards.

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Figure 67. nCS when CKMODE = 1 in DDR mode (T = CLK period)

T T T/2 nCS

SCLK

MS35321V1

When the FIFO stays full in a read operation or if the FIFO stays empty in a write operation, the operation stalls and CLK stays low until firmware services the FIFO. If an abort occurs when an operation is stalled, nCS rises just after the abort is requested and then CLK rises

one half of a CLK cycle later, as shown in Figure 68 .

Figure 68. nCS when CKMODE = 1 with an abort (T = CLK period)

T Clock stalled T/2 nCS

SCLK

Abort

MS35322V1

When not in dual-flash mode (DFM = 0) and FSEL = 0 (default value), only FLASH 1 is accessed and thus BK2_nCS stays high, if FSEL = 1, only FLASH 2 is accessed and

BK1_nCS stays high. In dual-flash mode, BK2_nCS behaves exactly the same as

BK1_nCS. Thus, if there is a FLASH 2 and if the application is dual-flash mode only, then

BK1_nCS signal can be used for FLASH 2 as well, and the pin devoted to BK2_nCS can be used for other functions.

An interrupt can be produced on the following events:

 Timeout

 Status match

 FIFO threshold

 Transfer complete

 Transfer error

Separate interrupt enable bits are available for flexibility.

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RM0390 Quad-SPI interface (QUADSPI)

Interrupt event

Timeout

Status match

FIFO threshold

Transfer complete

Transfer error

Table 82. QUADSPI interrupt requests

Event flag Enable control bit

TOF

SMF

FTF

TCF

TEF

TOIE

SMIE

FTIE

TCIE

TEIE

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Address offset: 0x0000

Reset value: 0x0000 0000

31 rw

Res.

30 rw

Res.

29 rw

Res.

28 27

PRESCALER[7:0]

26 rw

12 rw

11 rw

10 rw rw

25 rw

FTHRES[4:0] rw rw

24 rw

23 22

PMM APMS rw

7 rw

FSEL DFM rw rw

Res.

TOIE

SMIE

FTIE

TCIE

5 rw

4 rw

3 rw

2 rw

Res.

SSHIFT TCEN DMAEN ABORT rw rw rw rw

TEIE rw

EN rw rw

Bits 31:24 PRESCALER[7:0] : Clock prescaler

This field defines the scaler factor for generating CLK based on the AHB clock

(value+1).

0: F

CLK

= F

AHB

, AHB clock used directly as QUADSPI CLK (prescaler bypassed)

1: F

CLK

= F

AHB

2: F

CLK

= F

AHB

...

255: F

CLK

= F

AHB

/256

For odd clock division factors, CLK’s duty cycle is not 50%. The clock signal remains low one cycle longer than it stays high.

This field can be modified only when BUSY = 0.

When setting QUADSPI interface in DDR mode, the prescaler must be set with a division ratio of 2 or more.

Bit 23 PMM : Polling match mode

This bit indicates which method should be used for determining a “match” during automatic polling mode.

0: AND match mode. SMF is set if all the unmasked bits received from the Flash memory match the corresponding bits in the match register.

1: OR match mode. SMF is set if any one of the unmasked bits received from the Flash memory matches its corresponding bit in the match register.

This bit can be modified only when BUSY = 0.

Bit 22 APMS : Automatic poll mode stop

This bit determines if automatic polling is stopped after a match.

0: Automatic polling mode is stopped only by abort or by disabling the QUADSPI.

1: Automatic polling mode stops as soon as there is a match.

This bit can be modified only when BUSY = 0.

Bit 21 Reserved, must be kept at reset value.

Bit 20 TOIE : TimeOut interrupt enable

This bit enables the TimeOut interrupt.

0: Interrupt disable

1: Interrupt enabled

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Bit 19 SMIE : Status match interrupt enable

This bit enables the status match interrupt.

0: Interrupt disable

1: Interrupt enabled

Bit 18 FTIE : FIFO threshold interrupt enable

This bit enables the FIFO threshold interrupt.

0: Interrupt disabled

1: Interrupt enabled

Bit 17 TCIE : Transfer complete interrupt enable

This bit enables the transfer complete interrupt.

0: Interrupt disabled

1: Interrupt enabled

Bit 16 TEIE : Transfer error interrupt enable

This bit enables the transfer error interrupt.

0: Interrupt disable

1: Interrupt enabled

Bits 15:13 Reserved, must be kept at reset value.

Bits 12:8 FTHRES[4:0] FIFO threshold level

Defines, in indirect mode, the threshold number of bytes in the FIFO that causes the

FIFO threshold flag (bit FTF in register QUADSPI_SR) to be set.

0: In indirect write mode (FMODE = 00) FTF is set if there are 1 or more free bytes location left in the FIFO or indirect read mode (FMODE = 01) FTF is set if there are 1 or more valid bytes that can be read from the FIFO

1: In indirect write mode (FMODE = 00) FTF is set if there are 2 or more free bytes location left in the FIFO or indirect read mode (FMODE = 01) FTF is set if there are 2 or more valid bytes that can be read from the FIFO

...

31: In indirect write mode (FMODE = 00) FTF is set if there are 32 free bytes location left in the FIFO or indirect read mode (FMODE = 01) FTF is set if there are 32 valid bytes that can be read from the FIFO

If DMAEN = 1, then the DMA controller for the corresponding channel must be disabled before changing the FTHRES value.

Bit 7 FSEL : Flash memory selection

This bit selects the Flash memory to be addressed in single flash mode (when DFM =

0).

0: FLASH 1 selected

1: FLASH 2 selected

This bit can be modified only when BUSY = 0.

This bit is ignored when DFM = 1.

Bit 6 DFM : Dual-flash mode

This bit activates dual-flash mode, where two external Flash memories are used simultaneously to double throughput and capacity.

0: Dual-flash mode disabled

1: Dual-flash mode enabled

This bit can be modified only when BUSY = 0.

Bit 5 Reserved, must be kept at reset value.

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Bit 4 SSHIFT : Sample shift

By default, the QUADSPI samples data 1/2 of a CLK cycle after the data is driven by the

Flash memory. This bit allows the data to be sampled later in order to account for external signal delays.

0: No shift

1: 1/2 cycle shift

Firmware must assure that SSHIFT = 0 when in DDR mode (when DDRM = 1).

This field can be modified only when BUSY = 0.

Bit 3 TCEN : Timeout counter enable

This bit is valid only when memory-mapped mode (FMODE = 11) is selected. Activating this bit causes the chip select (nCS) to be released (and thus reduces consumption) if there has not been an access after a certain amount of time, where this time is defined by TIMEOUT[15:0] (QUADSPI_LPTR).

Enable the timeout counter.

QUADSPI_CR) so that nCS is released after a period of TIMEOUT[15:0]

(QUADSPI_LPTR) cycles have elapsed without an access since when the FIFO becomes full with prefetch data.

0: Timeout counter is disabled, and thus the chip select (nCS) remains active indefinitely after an access in memory-mapped mode.

1: Timeout counter is enabled, and thus the chip select is released in memory-mapped mode after TIMEOUT[15:0] cycles of Flash memory inactivity.

This bit can be modified only when BUSY = 0.

Bit 2 DMAEN : DMA enable

In indirect mode, DMA can be used to input or output data via the QUADSPI_DR register. DMA transfers are initiated when the FIFO threshold flag, FTF, is set.

0: DMA is disabled for indirect mode

1: DMA is enabled for indirect mode

Bit 1 ABORT : Abort request

This bit aborts the on-going command sequence. It is automatically reset once the abort is complete.

This bit stops the current transfer.

In polling mode or memory-mapped mode, this bit also reset the APM bit or the DM bit.

0: No abort requested

1: Abort requested

Bit 0 EN : Enable

Enable the QUADSPI.

0: QUADSPI is disabled

1: QUADSPI is enabled

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12.5.2 QUADSPI device configuration register (QUADSPI_DCR)

Address offset: 0x0004

Reset value: 0x0000 0000

Res.

29 28 27

Res.

13 12 11

Res.

10 rw

9 8

CSHT[2:0] rw rw

Res.

19 rw

Res.

FSIZE[4:0] rw

Res.

17 rw

Res.

16 rw

MODE rw

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:16 FSIZE[4:0] : Flash memory size

This field defines the size of external memory using the following formula:

Number of bytes in Flash memory = 2

[FSIZE+1]

FSIZE+1 is effectively the number of address bits required to address the Flash memory. The Flash memory capacity can be up to 4GB (addressed using 32 bits) in indirect mode, but the addressable space in memory-mapped mode is limited to

256MB.

If DFM = 1, FSIZE indicates the total capacity of the two Flash memories together.

This field can be modified only when BUSY = 0.

Bits 15:11 Reserved, must be kept at reset value.

Bits 10:8 CSHT[2:0] : Chip select high time

CSHT+1 defines the minimum number of CLK cycles which the chip select (nCS) must remain high between commands issued to the Flash memory.

0: nCS stays high for at least 1 cycle between Flash memory commands

1: nCS stays high for at least 2 cycles between Flash memory commands

...

7: nCS stays high for at least 8 cycles between Flash memory commands

This field can be modified only when BUSY = 0.

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 CKMODE : Mode 0 / mode 3

This bit indicates the level that CLK takes between commands (when nCS = 1).

0: CLK must stay low while nCS is high (chip select released). This is referred to as mode 0.

1: CLK must stay high while nCS is high (chip select released). This is referred to as mode 3.

This field can be modified only when BUSY = 0.

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Address offset: 0x0008

Reset value: 0x0000 0000

Res.

29 28 27

Res.

13 r

12 11 10 r

FLEVEL[5:0] r

9 r

8 7

Res.

BUSY r

TOF r

SMF r

FTF r

TCF r

TEF r r r

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:8 FLEVEL[5:0] : FIFO level

This field gives the number of valid bytes which are being held in the FIFO. FLEVEL = 0 when the FIFO is empty, and 32 when it is full. In memory-mapped mode and in automatic status polling mode, FLEVEL is zero.

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 BUSY : Busy

This bit is set when an operation is on going. This bit clears automatically when the operation with the Flash memory is finished and the FIFO is empty.

Bit 4 TOF : Timeout flag

This bit is set when timeout occurs. It is cleared by writing 1 to CTOF.

Bit 3 SMF : Status match flag

This bit is set in automatic polling mode when the unmasked received data matches the corresponding bits in the match register (QUADSPI_PSMAR). It is cleared by writing 1 to CSMF.

Bit 2 FTF : FIFO threshold flag

In indirect mode, this bit is set when the FIFO threshold is reached, or if there is any data left in the FIFO after reads from the Flash memory are complete. It is cleared automatically as soon as threshold condition is no longer true.

In automatic polling mode this bit is set every time the status register is read, and the bit is cleared when the data register is read.

Bit 1 TCF : Transfer complete flag

This bit is set in indirect mode when the programmed number of data is transferred or in any mode when the transfer is aborted.It is cleared by writing 1 to CTCF.

Bit 0 TEF : Transfer error flag

This bit is set in indirect mode when an invalid address is being accessed in indirect mode. It is cleared by writing 1 to CTEF.

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12.5.4 QUADSPI flag clear register (QUADSPI_FCR)

Address offset: 0x000C

Reset value: 0x0000 0000

Res.

29 28 27

Res.

13 12 11

Res.

4 3

CTOF CSMF w w

Res.

1 0

CTCF CTEF w w

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 CTOF : Clear timeout flag

Writing 1 clears the TOF flag in the QUADSPI_SR register

Bit 3 CSMF : Clear status match flag

Writing 1 clears the SMF flag in the QUADSPI_SR register

Bit 2 Reserved, must be kept at reset value.

Bit 1 CTCF : Clear transfer complete flag

Writing 1 clears the TCF flag in the QUADSPI_SR register

Bit 0 CTEF : Clear transfer error flag

Writing 1 clears the TEF flag in the QUADSPI_SR register

12.5.5 QUADSPI data length register (QUADSPI_DLR)

Address offset: 0x0010

Reset value: 0x0000 0000

31 30 29 28 27 26 25 22 21 rw

15 rw rw

14 rw rw

13 rw rw

12 rw rw

11 rw rw

10 rw rw

9 rw

24 23

DL[31:16] rw

8 rw

DL[15:0] rw rw rw

6 rw rw

5 rw

20 rw

4 rw

19 rw

3 rw

18 rw

2 rw

17 rw

1 rw

16 rw

0 rw

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Bits 31:0 DL[31:0] : Data length

Number of data to be retrieved (value+1) in indirect and status-polling modes. A value no greater than 3 (indicating 4 bytes) should be used for status-polling mode.

All 1s in indirect mode means undefined length, where QUADSPI continues until the end of memory, as defined by FSIZE.

0x0000_0000: 1 byte is to be transferred

0x0000_0001: 2 bytes are to be transferred

0x0000_0002: 3 bytes are to be transferred

0x0000_0003: 4 bytes are to be transferred

...

0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred

0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred

0xFFFF_FFFF: undefined length -- all bytes until the end of Flash memory (as defined by FSIZE) are to be transferred. Continue reading indefinitely if FSIZE = 0x1F.

DL[0] is stuck at ‘1’ in dual-flash mode (DFM = 1) even when ‘0’ is written to this bit, thus assuring that each access transfers an even number of bytes.

This field has no effect when in memory-mapped mode (FMODE = 10).

This field can be written only when BUSY = 0.

12.5.6 QUADSPI communication configuration register (QUADSPI_CCR)

Address offset: 0x0014

Reset value: 0x0000 0000

31 30 29 28

DDRM DHHC Res.

SIOO rw

15 rw

ABMODE[1:0] rw rw

13 rw

ADSIZE[1:0] rw rw

27 26

FMODE[1:0] rw

11 rw

ADMODE[1:0] rw rw

25 24

DMODE[1:0] rw

9 rw

IMODE[1:0] rw rw

Res.

7 rw

22 rw

6 rw

21 rw

5 rw

DCYC[4:0]

19 18 rw

4 rw

INSTRUCTION[7:0] rw rw rw

2 rw

17 16

ABSIZE[1:0] rw

1 rw

0 rw rw

Bit 31 DDRM : Double data rate mode

This bit sets the DDR mode for the address, alternate byte and data phase:

0: DDR Mode disabled

1: DDR Mode enabled

This field can be written only when BUSY = 0.

Bit 30 DHHC : DDR hold

Delay the data output by 1/4 of the QUADSPI output clock cycle in DDR mode:

0: Delay the data output using analog delay

1: Delay the data output by 1/4 of a QUADSPI output clock cycle.

This feature is only active in DDR mode.

This field can be written only when BUSY = 0.

Note: PRESCALER>0 is mandatory when DHHC=1.

Bit 29 Reserved, must be kept at reset value.

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Bit 28 SIOO : Send instruction only once mode

See

Section 12.3.12: Sending the instruction only once on page 338

. This bit has no effect when IMODE = 00.

0: Send instruction on every transaction

1: Send instruction only for the first command

This field can be written only when BUSY = 0.

Bits 27:26 FMODE[1:0] : Functional mode

This field defines the QUADSPI functional mode of operation.

00: Indirect write mode

01: Indirect read mode

10: Automatic polling mode

11: Memory-mapped mode

If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE value.

This field can be written only when BUSY = 0.

Bits 25:24 DMODE[1:0] : Data mode

This field defines the data phase’s mode of operation:

00: No data

01: Data on a single line

10: Data on two lines

11: Data on four lines

This field also determines the dummy phase mode of operation.

This field can be written only when BUSY = 0.

Bit 23 Reserved, must be kept at reset value.

Bits 22:18 DCYC[4:0] : Number of dummy cycles

This field defines the duration of the dummy phase. In both SDR and DDR modes, it specifies a number of CLK cycles (0-31).

This field can be written only when BUSY = 0.

Bits 17:16 ABSIZE[1:0] : Alternate bytes size

This bit defines alternate bytes size:

00: 8-bit alternate byte

01: 16-bit alternate bytes

10: 24-bit alternate bytes

11: 32-bit alternate bytes

This field can be written only when BUSY = 0.

Bits 15:14 ABMODE[1:0] : Alternate bytes mode

This field defines the alternate-bytes phase mode of operation:

00: No alternate bytes

01: Alternate bytes on a single line

10: Alternate bytes on two lines

11: Alternate bytes on four lines

This field can be written only when BUSY = 0.

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Bits 13:12 ADSIZE[1:0] : Address size

This bit defines address size:

00: 8-bit address

01: 16-bit address

10: 24-bit address

11: 32-bit address

This field can be written only when BUSY = 0.

Bits 11:10 ADMODE[1:0] : Address mode

This field defines the address phase mode of operation:

00: No address

01: Address on a single line

10: Address on two lines

11: Address on four lines

This field can be written only when BUSY = 0.

Bits 9:8 IMODE[1:0] : Instruction mode

This field defines the instruction phase mode of operation:

00: No instruction

01: Instruction on a single line

10: Instruction on two lines

11: Instruction on four lines

This field can be written only when BUSY = 0.

Bits 7:0 INSTRUCTION[7:0] : Instruction

Instruction to be send to the external SPI device.

This field can be written only when BUSY = 0.

RM0390

31 rw

15 rw

Address offset: 0x0018

Reset value: 0x0000 0000

30 29 28 27 26 25 rw

14 rw rw

13 rw

12 rw

11 rw

10 rw

24 23

ADDRESS[31:16]

22 rw

8 rw

7 rw

ADDRESS[15:0] rw rw rw

21 rw

20 rw

19 rw

18 rw

17 rw

16 rw

0 rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 ADDRESS[31:0] : Address

Address to be send to the external Flash memory

Writes to this field are ignored when BUSY = 1 or when FMODE = 11 (memory-mapped mode).

In dual flash mode, ADDRESS[0] is automatically stuck to ‘0’ as the address should always be even

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12.5.8 QUADSPI alternate bytes registers (QUADSPI_ABR)

Address offset: 0x001C

Reset value: 0x0000 0000

31 30 29 28 27 26 25 21 20 rw

15 rw rw

14 rw rw

13 rw rw

12 rw rw

11 rw rw

10 rw rw

9 rw

24 23

ALTERNATE[31:16]

22 rw

8 rw

7 rw

ALTERNATE[15:0] rw rw rw rw

5 rw rw

4 rw

19 rw

3 rw

18 rw

2 rw

17 rw

1 rw

16 rw

0 rw

Bits 31:0 ALTERNATE[31:0] : Alternate Bytes

Optional data to be send to the external SPI device right after the address.

This field can be written only when BUSY = 0.

12.5.9 QUADSPI data register (QUADSPI_DR)

Address offset: 0x0020

Reset value: 0x0000 0000

31 30 29 28 27 26 25 rw

15 rw rw

14 rw rw

13 rw rw

12 rw rw

11 rw rw

10 rw rw

9 rw

24 23

DATA[31:16] rw

8 rw

DATA[15:0] rw rw

22 rw

6 rw

21 rw

5 rw

20 rw

4 rw

19 rw

3 rw

18 rw

2 rw

17 rw

1 rw

16 rw

0 rw

Bits 31:0 DATA[31:0] : Data

Data to be sent/received to/from the external SPI device.

In indirect write mode, data written to this register is stored on the FIFO before it is sent to the Flash memory during the data phase. If the FIFO is too full, a write operation is stalled until the FIFO has enough space to accept the amount of data being written.

In indirect read mode, reading this register gives (via the FIFO) the data which was received from the Flash memory. If the FIFO does not have as many bytes as requested by the read operation and if BUSY=1, the read operation is stalled until enough data is present or until the transfer is complete, whichever happens first.

In automatic polling mode, this register contains the last data read from the Flash memory (without masking).

Word, halfword, and byte accesses to this register are supported. In indirect write mode, a byte write adds 1 byte to the FIFO, a halfword write 2, and a word write 4. Similarly, in indirect read mode, a byte read removes 1 byte from the FIFO, a halfword read 2, and a word read 4. Accesses in indirect mode must be aligned to the bottom of this register: a byte read must read DATA[7:0] and a halfword read must read DATA[15:0].

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31 rw

15 rw

Address offset: 0x0024

Reset value: 0x0000 0000

30 29 28 27 26 25 rw

14 rw rw

13 rw

12 rw

11 rw

10 rw

24 23

MASK[31:16] rw

8 rw

7 rw

MASK[15:0] rw

22 rw

6 rw

21 rw

20 rw

19 rw

18 rw

17 rw

16 rw

0 rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MASK[31:0] : Status mask

Mask to be applied to the status bytes received in polling mode.

For bit n:

0: Bit n of the data received in automatic polling mode is masked and its value is not considered in the matching logic

1: Bit n of the data received in automatic polling mode is unmasked and its value is considered in the matching logic

This field can be written only when BUSY = 0.

31 rw

15 rw

Address offset: 0x0028

Reset value: 0x0000 0000

30 29 28 27 26 25 rw

14 rw rw

13 rw

12 rw

11 rw

10 rw

24 23

MATCH[31:16]

22 rw

8 rw rw

MATCH[15:0] rw rw

6 rw

21 rw

20 rw

19 rw

18 rw

2 rw rw rw rw rw rw rw rw rw

Bits 31:0 MATCH[31:0] : Status match

Value to be compared with the masked status register to get a match.

This field can be written only when BUSY = 0.

17 16 rw

1 rw

0 rw rw

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12.5.12 QUADSPI polling interval register (QUADSPI_PIR)

Address offset: 0x002C

Reset value: 0x0000 0000

Res.

30 29

Res.

28 27

Res.

15 rw

14 rw

13 12 11 10 9 8 7

INTERVAL[15:0]

6 rw rw rw

5 4 3 2 rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 INTERVAL[15:0] : Polling interval

Number of CLK cycles between to read during automatic polling phases.

This field can be written only when BUSY = 0.

1 rw

0 rw

Address offset: 0x0030

Reset value: 0x0000 0000

Res.

30 29

Res.

28 27

Res.

15 rw

14 rw

13 12 11 10 9 8 7

TIMEOUT[15:0]

6 rw rw rw

5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 TIMEOUT[15:0] : Timeout period

After each access in memory-mapped mode, the QUADSPI prefetches the subsequent bytes and holds these bytes in the FIFO. This field indicates how many CLK cycles the

QUADSPI waits after the FIFO becomes full until it raises nCS, putting the Flash memory in a lower-consumption state.

This field can be written only when BUSY = 0.

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12.5.14 QUADSPI register map

Offset

Register name

Table 83. QUADSPI register map and reset values

0x0000

QUADSPI_CR

Reset value

PRESCALER[7:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FTHRES

[4:0]

0 0 0 0 0 0 0 0 0 0 0 0

0x0004

QUADSPI_DCR

Reset value

0x0008

QUADSPI_SR

Reset value

FSIZE[4:0]

0 0 0 0 0

CSHT

0 0 0

FLEVEL[5:0]

0 0 0 0 0 0 0 0 0 0 0 0

0x000C

QUADSPI_FCR

0x0010

Reset value

QUADSPI_DLR

Reset value

0 0 0 0

DL[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0014

QUADSPI_CCR DCYC[4:0] INSTRUCTION[7:0]

0x0018

0x001C

0x0020

0x0024

0x0028

Reset value

QUADSPI_AR

Reset value

QUADSPI_ABR

Reset value

QUADSPI_DR

Reset value

QUADSPI_

PSMKR

Reset value

QUADSPI_

PSMAR

Reset value

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADDRESS[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ALTERNATE[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DATA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MASK[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MATCH[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

QUADSPI_PIR INTERVAL[15:0]

0x002C

0x0030

Reset value

QUADSPI_

LPTR

Reset value

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMEOUT[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 56 for the register boundary addresses.

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13

Analog-to-digital converter (ADC)

Analog-to-digital converter (ADC)

The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19 multiplexed channels allowing it to measure signals from 16 external sources, two internal sources, and the V

BAT

channel. The A/D conversion of the channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored into a left- or right-aligned 16-bit data register.

The analog watchdog feature allows the application to detect if the input voltage goes beyond the user-defined, higher or lower thresholds.

13.2 ADC main features

Note:

 12-bit, 10-bit, 8-bit or 6-bit configurable resolution

 Interrupt generation at the end of conversion, end of injected conversion, and in case of analog watchdog or overrun events

 Single and continuous conversion modes

 Scan mode for automatic conversion of channel 0 to channel ‘n’

 Data alignment with in-built data coherency

 Channel-wise programmable sampling time

 External trigger option with configurable polarity for both regular and injected conversions

 Discontinuous mode

 Dual/Triple mode (on devices with 2 ADCs or more)

 Configurable DMA data storage in Dual/Triple ADC mode

 Configurable delay between conversions in Dual/Triple interleaved mode

 ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at slower speed

 ADC input range: V

REF –

≤ V

REF+

 DMA request generation during regular channel conversion

Figure 69

shows the block diagram of the ADC.

REF–

, if available (depending on package), must be tied to V

SSA

13.3 ADC functional description

Figure 69

shows a single ADC block diagram and

Table 84 gives the ADC pin description.

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Figure 69. Single ADC block diagram

DMA overrun

Flags

Interrupt enable bits

OVR OVRIE

End of conversion

End of injected conversion

EOC

JEOC

EOCIE

JEOCIE

Analog watchdog event

AWD AWDIE

Analog watchdog

Compare result

Higher threshold (12 bits)

Lower threshold (12 bits)

ADC Interrupt to NVIC

V REF+

V REF-

V DDA

V SSA

ADCx_IN0

ADCx_IN1

GPIO ports

ADCx_IN15

Temp. sensor

VREFINT

VBAT

Analog mux up to 4 up to 16

Injected data registers

(4 x 16 bits)

Regular data register

(16 bits)

DMA request

Injected

channels

Regular

channels

Analog to digital converter

ADCCLK

JEXTSEL[3:0] bits

TIM1_CH4

TIM1_TRGO

TIM2_CH1

TIM2_TRGO

TIM3_CH2

TIM3_CH4

TIM4_CH1

TIM4_CH2

TIM4_CH3

TIM4_TRGO

TIM5_CH4

TIM5_TRGO

TIM8_CH2

TIM8_CH3

TIM8_CH4

JEXTEN

[1:0] bits

Start trigger

(injected group)

From ADC prescaler

EXTSEL[3:0] bits

EXTEN

[1:0] bits

Start trigger

(regular group)

TIM1_CH1

TIM1_CH2

TIM1_CH3

TIM2_CH2

TIM2_CH3

TIM2_CH4

TIM2_TRGO

TIM3_CH1

TIM3_TRGO

TIM4_CH4

TIM5_CH1

TIM5_CH2

TIM5_CH3

TIM8_CH1

TIM8_TRGO

EXTI_15

EXTI_11 ai16046

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REF+

DDA

Name Signal type

Table 84. ADC pins

Input, analog reference positive

Input, analog supply

REF–

SSA

Input, analog reference negative

Input, analog supply ground

ADCx_IN[15:0] Analog input signals

Remarks

The higher/positive reference voltage for the ADC,

1.8 V ≤ V

REF+

≤ V

DDA

Analog power supply equal to V

2.4 V ≤ V

DDA

1.8 V ≤ V

DDA

≤ V

and

(3.6 V) for full speed

(3.6 V) for reduced speed

The lower/negative reference voltage for the ADC,

REF–

= V

SSA

Ground for analog power supply equal to V

16 analog input channels

The ADC is powered on by setting the ADON bit in the ADC_CR2 register. When the ADON bit is set for the first time, it wakes up the ADC from the Power-down mode.

The conversion starts when either the SWSTART or the JSWSTART bit is set.

The user can stop conversion and put the ADC in power down mode by clearing the ADON bit. In this mode the ADC consumes almost no power (only a few µA).

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13.3.2 ADC1/2 and ADC3 connectivity

ADC1, ADC2 and ADC3 are tightly coupled and share some external channels as described in

Figure 70

, Figure 71

and Figure 72

Figure 70. ADC1 connectivity

ADC123_IN0

ADC123_IN1

ADC123_IN2

ADC123_IN3

ADC12_IN4

ADC12_IN5

ADC12_IN6

ADC12_IN7

ADC12_IN8

ADC12_IN9

ADC123_IN10

ADC123_IN11

ADC123_IN12

ADC123_IN13

ADC12_IN14

ADC12_IN15

[8]

[9]

[10]

[11]

[12]

[13]

[14]

[15]

N.C.

[16]

[17]

REFINT

[18]

VBAT/4 or V

SENSE

[3]

[4]

[5]

[6]

[7]

ADC1

[0]

[1]

[2]

Channel selection

REF+

SAR

ADC1

REF-

MSv35937V1

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ADC123_IN0

ADC123_IN1

ADC123_IN2

ADC123_IN3

ADC12_IN4

ADC12_IN5

ADC12_IN6

ADC12_IN7

ADC12_IN8

ADC12_IN9

ADC123_IN10

ADC123_IN11

ADC123_IN12

ADC123_IN13

ADC12_IN14

ADC12_IN15

Analog-to-digital converter (ADC)

Figure 71. ADC2 connectivity

[11]

[12]

[13]

[14]

[15]

N.C.

[16]

[17]

N.C.

[18]

N.C.

[3]

[4]

[5]

[6]

ADC2

[0]

[1]

[2]

[7]

[8]

[9]

[10]

Channel selection

REF+

SAR

ADC2

REF-

MSv35938V1

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ADC123_IN0

ADC123_IN1

ADC123_IN2

ADC123_IN3

ADC3_IN4

ADC3_IN5

ADC3_IN6

ADC3_IN7

ADC3_IN8

ADC3_IN9

ADC123_IN10

ADC123_IN11

ADC123_IN12

ADC123_IN13

ADC3_IN14

ADC3_IN15

RM0390

Figure 72. ADC3 connectivity

ADC3

[0]

[1]

[2]

[3]

[4]

[5]

[14]

[15]

N.C.

[16]

[17]

N.C.

[18]

N.C.

[6]

[7]

[8]

[9]

[10]

[11]

[12]

[13]

Channel selection

REF+

SAR

ADC3

REF-

MSv35939V1

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The ADC features two clock schemes:

 Clock for the analog circuitry: ADCCLK, common to all ADCs

This clock is generated from the APB2 clock divided by a programmable prescaler that allows the ADC to work at f

PCLK2 maximum value of ADCCLK.

/2, /4, /6 or /8. Refer to the datasheets for the

 Clock for the digital interface (used for registers read/write access)

This clock is equal to the APB2 clock. The digital interface clock can be enabled/disabled individually for each ADC through the RCC APB2 peripheral clock enable register (RCC_APB2ENR).

Note:

There are 16 multiplexed channels. It is possible to organize the conversions in two groups: regular and injected. A group consists of a sequence of conversions that can be done on any channel and in any order. For instance, it is possible to implement the conversion sequence in the following order: ADC_IN3, ADC_IN8, ADC_IN2, ADC_IN2, ADC_IN0,

ADC_IN2, ADC_IN2, ADC_IN15.

 A regular group is composed of up to 16 conversions. The regular channels and their order in the conversion sequence must be selected in the ADC_SQRx registers. The total number of conversions in the regular group must be written in the L[3:0] bits in the

ADC_SQR1 register.

 An injected group is composed of up to 4 conversions. The injected channels and their order in the conversion sequence must be selected in the ADC_JSQR register.

The total number of conversions in the injected group must be written in the L[1:0] bits in the ADC_JSQR register.

If the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current conversion is reset and a new start pulse is sent to the ADC to convert the newly chosen group.

Temperature sensor, V

REFINT

and V

BAT

internal channels

 The temperature sensor is internally connected to ADC1_IN18 channel which is shared with VBAT. Only one conversion, temperature sensor or VBAT, must be selected at a time. When the temperature sensor and VBAT conversion are set simultaneously, only the VBAT conversion is performed.

The internal reference voltage VREFINT is connected to ADC1_IN17.

The V

BAT channel is connected to ADC1_IN18 channel. It can also be converted as an injected or regular channel.

The temperature sensor, V

REFINT

ADC1 peripheral.

and the V

BAT channel are available only on the master

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13.3.5 Single conversion mode

In Single conversion mode the ADC does one conversion. This mode is started with the

CONT bit at 0 by either:

 setting the SWSTART bit in the ADC_CR2 register (for a regular channel only)

 setting the JSWSTART bit (for an injected channel)

 external trigger (for a regular or injected channel)

Once the conversion of the selected channel is complete:

 If a regular channel was converted:

– The converted data are stored into the 16-bit ADC_DR register

– The EOC (end of conversion) flag is set

– An interrupt is generated if the EOCIE bit is set

 If an injected channel was converted:

– The converted data are stored into the 16-bit ADC_JDR1 register

– The JEOC (end of conversion injected) flag is set

– An interrupt is generated if the JEOCIE bit is set

Then the ADC stops.

13.3.6 Continuous conversion mode

Note:

In continuous conversion mode, the ADC starts a new conversion as soon as it finishes one.

This mode is started with the CONT bit at 1 either by external trigger or by setting the

SWSTART bit in the ADC_CR2 register (for regular channels only).

After each conversion:

 If a regular group of channels was converted:

– The last converted data are stored into the 16-bit ADC_DR register

– The EOC (end of conversion) flag is set

– An interrupt is generated if the EOCIE bit is set

Injected channels cannot be converted continuously. The only exception is when an injected channel is configured to be converted automatically after regular channels in continuous mode (using JAUTO bit), refer to Auto-injection section)

.

As shown in

Figure 73

, the ADC needs a stabilization time of t

STAB

before it starts converting accurately. After the start of the ADC conversion and after 15 clock cycles, the

EOC flag is set and the 16-bit ADC data register contains the result of the conversion.

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Figure 73. Timing diagram

Analog-to-digital converter (ADC)

ADC_CLK

ADON

SWSTART/

JSWSTART

ADC

EOC tSTAB

Start 1st conversion

ADC conversion

Conversion time

(total conv. time)

Start next conversion

Next ADC conversion

Software clears the EOC bit ai16047b

The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is below a lower threshold or above a higher threshold. These thresholds are programmed in the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can be enabled by using the AWDIE bit in the ADC_CR1 register.

The threshold value is independent of the alignment selected by the ALIGN bit in the

ADC_CR2 register. The analog voltage is compared to the lower and higher thresholds before alignment.

Table 85 shows how the ADC_CR1 register should be configured to enable the analog

watchdog on one or more channels.

Figure 74. Analog watchdog’s guarded area

Analog voltage

Higher threshold

Lower threshold

HTR

Guarded area

LTR ai16048

Table 85. Analog watchdog channel selection

ADC_CR1 register control bits (x = don’t care)

Channels guarded by the analog watchdog

AWDSGL bit AWDEN bit JAWDEN bit

None

All injected channels x

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Table 85. Analog watchdog channel selection (continued)

ADC_CR1 register control bits (x = don’t care)

Channels guarded by the analog watchdog

AWDSGL bit AWDEN bit JAWDEN bit

All regular channels

All regular and injected channels

Single

(1)

injected channel

Single

(1)

regular channel

Single

(1) regular or injected channel

1. Selected by the AWDCH[4:0] bits

This mode is used to scan a group of analog channels.

The Scan mode is selected by setting the SCAN bit in the ADC_CR1 register. Once this bit has been set, the ADC scans all the channels selected in the ADC_SQRx registers (for regular channels) or in the ADC_JSQR register (for injected channels). A single conversion is performed for each channel of the group. After each end of conversion, the next channel in the group is converted automatically. If the CONT bit is set, regular channel conversion does not stop at the last selected channel in the group but continues again from the first selected channel.

If the DMA bit is set, the direct memory access (DMA) controller is used to transfer the data converted from the regular group of channels (stored in the ADC_DR register) to SRAM after each regular channel conversion.

The EOC bit is set in the ADC_SR register:

 At the end of each regular group sequence if the EOCS bit is cleared to 0

 At the end of each regular channel conversion if the EOCS bit is set to 1

The data converted from an injected channel are always stored into the ADC_JDRx registers.

13.3.10 Injected channel management

Triggered injection

To use triggered injection, the JAUTO bit must be cleared in the ADC_CR1 register.

Start the conversion of a group of regular channels either by external trigger or by setting the SWSTART bit in the ADC_CR2 register.

2. If an external injected trigger occurs or if the JSWSTART bit is set during the conversion of a regular group of channels, the current conversion is reset and the injected channel sequence switches to Scan-once mode.

3. Then, the regular conversion of the regular group of channels is resumed from the last interrupted regular conversion.

If a regular event occurs during an injected conversion, the injected conversion is not interrupted but the regular sequence is executed at the end of the injected sequence.

Figure 75

shows the corresponding timing diagram.

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Note:

Analog-to-digital converter (ADC)

When using triggered injection, one must ensure that the interval between trigger events is longer than the injection sequence. For instance, if the sequence length is 30 ADC clock cycles (that is two conversions with a sampling time of 3 clock periods), the minimum interval between triggers must be 31 ADC clock cycles.

Auto-injection

If the JAUTO bit is set, then the channels in the injected group are automatically converted after the regular group of channels. This can be used to convert a sequence of up to 20 conversions programmed in the ADC_SQRx and ADC_JSQR registers.

In this mode, external trigger on injected channels must be disabled.

If the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected channels are continuously converted.

It is not possible to use both the auto-injected and discontinuous modes simultaneously.

Figure 75. Injected conversion latency

ADCCLK

Injection event

Reset ADC max latency

(1)

SOC ai16049

1. The maximum latency value can be found in the electrical characteristics of the STM32F446xx datasheets.

Regular group

This mode is enabled by setting the DISCEN bit in the ADC_CR1 register. It can be used to convert a short sequence of n conversions (n ≤ 8) that is part of the sequence of conversions selected in the ADC_SQRx registers. The value of n is specified by writing to the DISCNUM[2:0] bits in the ADC_CR1 register.

When an external trigger occurs, it starts the next n conversions selected in the ADC_SQRx registers until all the conversions in the sequence are done. The total sequence length is defined by the L[3:0] bits in the ADC_SQR1 register.

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Note:

RM0390

Example:

 n = 3, channels to be converted = 0, 1, 2, 3, 6, 7, 9, 10

 1st trigger: sequence converted 0, 1, 2. An EOC event is generated at each conversion.

 2nd trigger: sequence converted 3, 6, 7. An EOC event is generated at each conversion

 3rd trigger: sequence converted 9, 10.An EOC event is generated at each conversion

 4th trigger: sequence converted 0, 1, 2. An EOC event is generated at each conversion

When a regular group is converted in discontinuous mode, no rollover occurs.

When all subgroups are converted, the next trigger starts the conversion of the first subgroup. In the example above, the 4th trigger reconverts the channels 0, 1 and 2 in the

1st subgroup.

Injected group

This mode is enabled by setting the JDISCEN bit in the ADC_CR1 register. It can be used to convert the sequence selected in the ADC_JSQR register, channel by channel, after an external trigger event.

When an external trigger occurs, it starts the next channel conversions selected in the

ADC_JSQR registers until all the conversions in the sequence are done. The total sequence length is defined by the JL[1:0] bits in the ADC_JSQR register.

Example: n = 1, channels to be converted = 1, 2, 3

1st trigger: channel 1 converted

2nd trigger: channel 2 converted

3rd trigger: channel 3 converted and JEOC event generated

4th trigger: channel 1

When all injected channels are converted, the next trigger starts the conversion of the first injected channel. In the example above, the 4th trigger reconverts the 1st injected channel

It is not possible to use both the auto-injected and discontinuous modes simultaneously.

Discontinuous mode must not be set for regular and injected groups at the same time.

Discontinuous mode must be enabled only for the conversion of one group.

The ALIGN bit in the ADC_CR2 register selects the alignment of the data stored after

conversion. Data can be right- or left-aligned as shown in Figure 76 and Figure 77

The converted data value from the injected group of channels is decreased by the userdefined offset written in the ADC_JOFRx registers so the result can be a negative value.

The SEXT bit represents the extended sign value.

For channels in a regular group, no offset is subtracted so only twelve bits are significant.

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Figure 76. Right alignment of 12-bit data

Injected group

SEXT SEXT SEXT SEXT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Regular group

0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ai16050

Figure 77. Left alignment of 12-bit data

Injected group

SEXT D11 D10 D9 D8 D7 D6 D5

Regular group

D11 D10 D9 D8 D7 D6 D5 D4

D4 D3 D2 D1 D0 0 0 0

D3 D2 D1 D0 0 0 0 0 ai16051

Special case: when left-aligned, the data are aligned on a half-word basis except when the resolution is set to 6-bit. in that case, the data are aligned on a byte basis as shown in

Figure 78

Figure 78. Left alignment of 6-bit data

Injected group

SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT D5 D4 D3 D2 D1 D0 0

Regular group

0 0 0 0 0 0 0 0 D5 D4 D3 D2 D1 D0 0 0 ai16052

13.5 Channel-wise programmable sampling time

The ADC samples the input voltage for a number of ADCCLK cycles that can be modified using the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can be sampled with a different sampling time.

The total conversion time is calculated as follows:

T conv

= Sampling time + 12 cycles

Example:

With ADCCLK = 30 MHz and sampling time = 3 cycles:

T conv

= 3 + 12 = 15 cycles = 0.5 µs with APB2 at 60 MHz

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13.6 Conversion on external trigger and trigger polarity

Conversion can be triggered by an external event (e.g. timer capture, EXTI line). If the

EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from “0b00”, then external events are able to trigger a conversion

with the selected polarity. Table 86

provides the correspondence between the EXTEN[1:0] and JEXTEN[1:0] values and the trigger polarity.

Table 86. Configuring the trigger polarity

Source EXTEN[1:0] / JEXTEN[1:0]

Trigger detection disabled

Detection on the rising edge

Detection on the falling edge

Detection on both the rising and falling edges

Note:

Source

TIM1_CH1 event

TIM1_CH2 event

TIM1_CH3 event

TIM2_CH2 event

TIM2_CH3 event

TIM2_CH4 event

TIM2_TRGO event

TIM3_CH1 event

TIM3_TRGO event

TIM4_CH4 event

TIM5_CH1 event

TIM5_CH2 event

TIM5_CH3 event

TIM8_CH1 event

TIM8_TRGO event

EXTI line11

The polarity of the external trigger can be changed on the fly.

The EXTSEL[3:0] and JEXTSEL[3:0] control bits are used to select which out of 16 possible events can trigger conversion for the regular and injected groups.

Table 87 gives the possible external trigger for regular conversion.

Table 87. External trigger for regular channels

Type

Internal signal from on-chip timers

External pin

EXTSEL[3:0]

0101

0110

0111

1000

1001

1010

0000

0001

0010

0011

0100

1011

1100

1101

1110

1111

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Table 88 gives the possible external trigger for injected conversion.

Source

TIM1_CH4 event

TIM1_TRGO event

TIM2_CH1 event

TIM2_TRGO event

TIM3_CH2 event

TIM3_CH4 event

TIM4_CH1 event

TIM4_CH2 event

TIM4_CH3 event

TIM4_TRGO event

TIM5_CH4 event

TIM5_TRGO event

TIM8_CH2 event

TIM8_CH3 event

TIM8_CH4 event

EXTI line15

Table 88. External trigger for injected channels

Connection type JEXTSEL[3:0]

Internal signal from on-chip timers

External pin

0111

1000

1001

1010

1011

1100

0000

0001

0010

0011

0100

0101

0110

1101

1110

1111

Note:

Software source trigger events can be generated by setting SWSTART (for regular conversion) or JSWSTART (for injected conversion) in ADC_CR2.

A regular group conversion can be interrupted by an injected trigger.

The trigger selection can be changed on the fly. However, when the selection changes, there is a time frame of 1 APB clock cycle during which the trigger detection is disabled.

This is to avoid spurious detection during transitions.

13.7 Fast conversion mode

It is possible to perform faster conversion by reducing the ADC resolution. The RES bits are used to select the number of bits available in the data register. The minimum conversion time for each resolution is then as follows:

 12 bits: 3 + 12 = 15 ADCCLK cycles

 10 bits: 3 + 10 = 13 ADCCLK cycles

 8 bits: 3 + 8 = 11 ADCCLK cycles

 6 bits: 3 + 6 = 9 ADCCLK cycles

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13.8.1 Using the DMA

Since converted regular channel values are stored into a unique data register, it is useful to use DMA for conversion of more than one regular channel. This avoids the loss of the data already stored in the ADC_DR register.

When the DMA mode is enabled (DMA bit set to 1 in the ADC_CR2 register), after each conversion of a regular channel, a DMA request is generated. This allows the transfer of the converted data from the ADC_DR register to the destination location selected by the software.

Despite this, if data are lost (overrun), the OVR bit in the ADC_SR register is set and an interrupt is generated (if the OVRIE enable bit is set). DMA transfers are then disabled and

DMA requests are no longer accepted. In this case, if a DMA request is made, the regular conversion in progress is aborted and further regular triggers are ignored. It is then necessary to clear the OVR flag and the DMAEN bit in the used DMA stream, and to reinitialize both the DMA and the ADC to have the wanted converted channel data transferred to the right memory location. Only then can the conversion be resumed and the data transfer, enabled again. Injected channel conversions are not impacted by overrun errors.

When OVR = 1 in DMA mode, the DMA requests are blocked after the last valid data have been transferred, which means that all the data transferred to the RAM can be considered as valid.

At the end of the last DMA transfer (number of transfers configured in the DMA controller’s

DMA_SxNDTR register):

 No new DMA request is issued to the DMA controller if the DDS bit is cleared to 0 in the

ADC_CR2 register (this avoids generating an overrun error). However the DMA bit is not cleared by hardware. It must be written to 0, then to 1 to start a new transfer.

 Requests can continue to be generated if the DDS bit is set to 1. This allows configuring the DMA in double-buffer circular mode.

To recover the ADC from OVR state when the DMA is used, follow the steps below:

Reinitialize the DMA (adjust destination address and NDTR counter)

2. Clear the ADC OVR bit in ADC_SR register

3. Trigger the ADC to start the conversion.

13.8.2 Managing a sequence of conversions without using the DMA

If the conversions are slow enough, the conversion sequence can be handled by the software. In this case the EOCS bit must be set in the ADC_CR2 register for the EOC status bit to be set at the end of each conversion, and not only at the end of the sequence. When

EOCS = 1, overrun detection is automatically enabled. Thus, each time a conversion is complete, EOC is set and the ADC_DR register can be read. The overrun management is the same as when the DMA is used.

To recover the ADC from OVR state when the EOCS is set, follow the steps below:

Clear the ADC OVR bit in ADC_SR register

2. Trigger the ADC to start the conversion.

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13.8.3 Conversions without DMA and without overrun detection

It may be useful to let the ADC convert one or more channels without reading the data each time (if there is an analog watchdog for instance). For that, the DMA must be disabled

(DMA = 0) and the EOC bit must be set at the end of a sequence only (EOCS = 0). In this configuration, overrun detection is disabled.

Note:

In devices with two ADCs or more, the Dual (with two ADCs) and Triple (with three ADCs)

ADC modes can be used (see Figure 79

In multi ADC mode, the start of conversion is triggered alternately or simultaneously by the

ADC1 master to the ADC2 and ADC3 slaves, depending on the mode selected by the

MULTI[4:0] bits in the ADC_CCR register.

In multi ADC mode, when configuring conversion trigger by an external event, the application must set trigger by the master only and disable trigger by slaves to prevent spurious triggers that would start unwanted slave conversions.

The four possible modes below are implemented:

 Injected simultaneous mode

 Regular simultaneous mode

 Interleaved mode

 Alternate trigger mode

It is also possible to use the previous modes combined in the following ways:

 Injected simultaneous mode + Regular simultaneous mode

 Regular simultaneous mode + Alternate trigger mode

In multi ADC mode, the converted data can be read on the multi-mode data register

(ADC_CDR). The status bits can be read in the multi-mode status register (ADC_CSR).

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Figure 79. Multi ADC block diagram (1)

Regular data register

Regular

channels

Injected

channels

Injected data registers

(4 x 16 bits)

ADC3

(2)

(Slave)

Regular data register

Regular

channels

Injected

channels internal triggers

Injected data registers

(4 x 16 bits)

ADC2 (Slave)

Common regular data register

(32 bits)

(3)

Dual/Triple

mode control

Common part

RM0390

Regular data register

(16 bits)

Injected data registers

(4 x 16 bits)

ADCx_IN0

ADCx_IN1

ADCx_IN15

GPIO

Ports

EXTI_11

Temp. sensor

REFINT

BAT

EXTI_15

Start trigger mux

(regular group)

Start trigger mux

(injected group)

Regular

channels

Injected

channels

ADC1 (Master)

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1. Although external triggers are present on ADC2 and ADC3 they are not shown in this diagram.

2. In the Dual ADC mode, the ADC3 slave part is not present.

3. In Triple ADC mode, the ADC common data register (ADC_CDR) contains the ADC1, ADC2 and ADC3’s regular converted data. All 32 register bits are used according to a selected storage order.

In Dual ADC mode, the ADC common data register (ADC_CDR) contains both the ADC1 and ADC2’s regular converted data. All 32 register bits are used.

RM0390 Rev 6

RM0390 Analog-to-digital converter (ADC)

 DMA requests in Multi ADC mode:

In Multi ADC mode the DMA may be configured to transfer converted data in three different modes. In all cases, the DMA streams to use are those connected to the ADC:

– DMA mode 1: On each DMA request (one data item is available), a half-word representing an ADC-converted data item is transferred.

In Dual ADC mode, DMA mode 1 is not supported.

In Triple ADC mode, ADC1 data are transferred on the first request, ADC2 data are transferred on the second request and ADC3 data are transferred on the third request; the sequence is repeated. So the DMA first transfers ADC1 data followed by ADC2 data followed by ADC3 data and so on.

DMA mode 1 can be used in regular simultaneous triple mode.

Example:

Regular simultaneous triple mode: 3 consecutive DMA requests are generated

(one for each converted data item)

1st request: ADC_CDR[31:0] = ADC1_DR[15:0]

2nd request: ADC_CDR[31:0] = ADC2_DR[15:0]

3rd request: ADC_CDR[31:0] = ADC3_DR[15:0]

4th request: ADC_CDR[31:0] = ADC1_DR[15:0]

– DMA mode 2 : On each DMA request (two data items are available) two halfwords representing two ADC-converted data items are transferred as a word.

In Dual ADC mode, both ADC2 and ADC1 data are transferred on the first request

(ADC2 data take the upper half-word and ADC1 data take the lower half-word) and so on.

In Triple ADC mode, three DMA requests are generated. On the first request, both

ADC2 and ADC1 data are transferred (ADC2 data take the upper half-word and

ADC1 data take the lower half-word). On the second request, both ADC1 and

ADC3 data are transferred (ADC1 data take the upper half-word and ADC3 data take the lower half-word).On the third request, both ADC3 and ADC2 data are transferred (ADC3 data take the upper half-word and ADC2 data take the lower half-word) and so on.

DMA mode 2 is used in interleaved mode and in regular simultaneous mode (for

Dual ADC mode only).

Example: a) Interleaved dual mode: a DMA request is generated each time 2 data items are available:

1st request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0]

2nd request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0] b) Interleaved triple mode: a DMA request is generated each time 2 data items are available

1st request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0]

2nd request: ADC_CDR[31:0] = ADC1_DR[15:0] | ADC3_DR[15:0]

3rd request: ADC_CDR[31:0] = ADC3_DR[15:0] | ADC2_DR[15:0]

4th request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0]

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– DMA mode 3 : This mode is similar to the DMA mode 2. The only differences are that the on each DMA request (two data items are available) two bytes representing two ADC converted data items are transferred as a half-word. The data transfer order is similar to that of the DMA mode 2.

DMA mode 3 is used in interleaved mode in 6-bit and 8-bit resolutions. Interleaved dual and triple modes are supported:

Example: a) Interleaved dual mode: a DMA request is generated each time 2 data items are available

1st request: ADC_CDR[15:0] = ADC2_DR[7:0] | ADC1_DR[7:0]

2nd request: ADC_CDR[15:0] = ADC2_DR[7:0] | ADC1_DR[7:0] b) Interleaved triple mode: a DMA request is generated each time 2 data items are available

1st request: ADC_CDR[15:0] = ADC2_DR[7:0] | ADC1_DR[7:0]

2nd request: ADC_CDR[15:0] = ADC1_DR[7:0] | ADC3_DR[7:0]

3rd request: ADC_CDR[15:0] = ADC3_DR[7:0] | ADC2_DR[7:0]

4th request: ADC_CDR[15:0] = ADC2_DR[7:0] | ADC1_DR[7:0]

Overrun detection: If an overrun is detected on one of the concerned ADCs (ADC1 and

ADC2 in dual and triple modes, ADC3 in triple mode only), the DMA requests are no longer issued to ensure that all the data transferred to the RAM are valid. It may happen that the

EOC bit corresponding to one ADC remains set because the data register of this ADC contains valid data.

13.9.1 Injected simultaneous mode

Note:

This mode converts an injected group of channels. The external trigger source comes from the injected group multiplexer of ADC1 (selected by the JEXTSEL[3:0] bits in the ADC1_CR2 register). A simultaneous trigger is provided to ADC2 and ADC3.

Do not convert the same channel on the two/three ADCs (no overlapping sampling times for the two/three ADCs when converting the same channel).

In simultaneous mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the longer of the 2 sequences (Dual ADC mode) /3 sequences (Triple ADC mode). Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions.

Regular conversions can be performed on one or all ADCs. In that case, they are independent of each other and are interrupted when an injected event occurs. They are resumed at the end of the injected conversion group.

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Dual ADC mode

At the end of conversion event on ADC1 or ADC2:

 The converted data are stored into the ADC_JDRx registers of each ADC interface.

 A JEOC interrupt is generated (if enabled on one of the two ADC interfaces) when the

ADC1/ADC2’s injected channels have all been converted.

Figure 80. Injected simultaneous mode on 4 channels: dual ADC mode

ADC1

ADC2

CH0

CH15

CH1

CH14

CH2

CH13

CH3

CH12

...

CH15

CH0

Trigger End of conversion on ADC1 and ADC2

Sampling

Conversion ai16054

Triple ADC mode

At the end of conversion event on ADC1, ADC2 or ADC3:

 The converted data are stored into the ADC_JDRx registers of each ADC interface.

 A JEOC interrupt is generated (if enabled on one of the three ADC interfaces) when the

ADC1/ADC2/ADC3’s injected channels have all been converted.

Figure 81. Injected simultaneous mode on 4 channels: triple ADC mode

ADC1

ADC2

ADC3

CH0

CH15

CH10

CH1

CH14

CH12

CH2

CH13

CH8

CH3

CH12

CH5

...

CH15

CH0

CH2

Trigger End of conversion on ADC1, ADC2 and ADC3

Sampling

Conversion ai16055

13.9.2 Regular simultaneous mode

Note:

This mode is performed on a regular group of channels. The external trigger source comes from the regular group multiplexer of ADC1 (selected by the EXTSEL[3:0] bits in the

ADC1_CR2 register). A simultaneous trigger is provided to ADC2 and ADC3.

Do not convert the same channel on the two/three ADCs (no overlapping sampling times for the two/three ADCs when converting the same channel).

In regular simultaneous mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the long conversion time of the 2 sequences

(Dual ADC mode) /3 sequences (Triple ADC mode). Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions.

Injected conversions must be disabled.

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Dual ADC mode

At the end of conversion event on ADC1 or ADC2:

 A 32-bit DMA transfer request is generated (if DMA[1:0] bits in the ADC_CCR register are equal to 0b10). This request transfers the ADC2 converted data stored in the upper half-word of the ADC_CDR 32-bit register to the SRAM and then the ADC1 converted data stored in the lower half-word of ADC_CCR to the SRAM.

 An EOC interrupt is generated (if enabled on one of the two ADC interfaces) when the

ADC1/ADC2’s regular channels have all been converted.

Figure 82. Regular simultaneous mode on 16 channels: dual ADC mode

ADC1

ADC2

CH0

CH15

CH1

CH14

CH2

CH13

CH3

CH12

...

CH15

CH0

Trigger End of conversion on ADC1 and ADC2

Sampling

Conversion ai16054

Triple ADC mode

At the end of conversion event on ADC1, ADC2 or ADC3:

 Three 32-bit DMA transfer requests are generated (if DMA[1:0] bits in the ADC_CCR register are equal to 0b01). Three transfers then take place from the ADC_CDR 32-bit register to SRAM: first the ADC1 converted data, then the ADC2 converted data and finally the ADC3 converted data. The process is repeated for each new three conversions.

 An EOC interrupt is generated (if enabled on one of the three ADC interfaces) when the

ADC1/ADC2/ADC3’s regular channels are have all been converted.

Figure 83. Regular simultaneous mode on 16 channels: triple ADC mode

ADC1

ADC2

ADC3

CH0

CH15

CH10

CH1

CH14

CH12

CH2

CH13

CH8

CH3

CH12

...

CH5

...

CH15

CH0

CH2

Trigger End of conversion on ADC1, ADC2 and ADC3

Sampling

Conversion ai16055

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This mode can be started only on a regular group (usually one channel). The external trigger source comes from the regular channel multiplexer of ADC1.

Dual ADC mode

After an external trigger occurs:

 ADC1 starts immediately

 ADC2 starts after a delay of several ADC clock cycles

RM0390 Rev 6

RM0390

Note:

Analog-to-digital converter (ADC)

The minimum delay which separates 2 conversions in interleaved mode is configured in the

DELAY bits in the ADC_CCR register. However, an ADC cannot start a conversion if the complementary ADC is still sampling its input (only one ADC can sample the input signal at a given time). In this case, the delay becomes the sampling time + 2 ADC clock cycles. For instance, if DELAY = 5 clock cycles and the sampling takes 15 clock cycles on both ADCs, then 17 clock cycles will separate conversions on ADC1 and ADC2).

If the CONT bit is set on both ADC1 and ADC2, the selected regular channels of both ADCs are continuously converted.

If the conversion sequence is interrupted (for instance when DMA end of transfer occurs), the multi-ADC sequencer must be reset by configuring it in independent mode first (bits

DUAL[4:0] = 00000) before reprogramming the interleaved mode.

After an EOC interrupt is generated by ADC2 (if enabled through the EOCIE bit) a 32-bit

DMA transfer request is generated (if the DMA[1:0] bits in ADC_CCR are equal to 0b10).

This request first transfers the ADC2 converted data stored in the upper half-word of the

ADC_CDR 32-bit register into SRAM, then the ADC1 converted data stored in the register’s lower half-word into SRAM.

Figure 84. Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode

End of conversion on ADC1

ADC1

ADC2

CH0

...

CH0

Sampling

Conversion

Trigger

End of conversion on ADC2

8 ADCCLK cycles ai16056

Triple ADC mode

After an external trigger occurs:

 ADC1 starts immediately and

 ADC2 starts after a delay of several ADC clock cycles

 ADC3 starts after a delay of several ADC clock cycles referred to the ADC2 conversion

The minimum delay which separates 2 conversions in interleaved mode is configured in the

ADCs, then 17 clock cycles will separate the conversions on ADC1, ADC2 and ADC3).

If the CONT bit is set on ADC1, ADC2 and ADC3, the selected regular channels of all ADCs are continuously converted.

If the conversion sequence is interrupted (for instance when DMA end of transfer occurs), the multi-ADC sequencer must be reset by configuring it in independent mode first (bits

DUAL[4:0] = 00000) before reprogramming the interleaved mode.

In this mode a DMA request is generated each time 2 data items are available, (if the

DMA[1:0] bits in the ADC_CCR register are equal to 0b10). The request first transfers the

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Analog-to-digital converter (ADC) RM0390 first converted data stored in the lower half-word of the ADC_CDR 32-bit register to SRAM, then it transfers the second converted data stored in ADC_CDR’s upper half-word to SRAM.

The sequence is the following:

 1st request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0]

 2nd request: ADC_CDR[31:0] = ADC1_DR[15:0] | ADC3_DR[15:0]

 3rd request: ADC_CDR[31:0] = ADC3_DR[15:0] | ADC2_DR[15:0]

 4th request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0], ...

Figure 85. Interleaved mode on 1 channel in continuous conversion mode: triple ADC mode

End of conversion on ADC1

ADC1

ADC2

ADC3

DMA request every 2 conversions

CH0

...

CH0

...

CH0

Sampling

Conversion

Trigger

End of conversion on ADC3

End of conversion on ADC2

6 ADCCLK cycles ai16058

Note:

This mode can be started only on an injected group. The source of external trigger comes from the injected group multiplexer of ADC1.

Regular conversions can be enabled on one or all ADCs. In this case the regular conversions are independent of each other. A regular conversion is interrupted when the

ADC has to perform an injected conversion. It is resumed when the injected conversion is finished.

If the conversion sequence is interrupted (for instance when DMA end of transfer occurs), the multi-ADC sequencer must be reset by configuring it in independent mode first (bits

DUAL[4:0] = 00000) before reprogramming the interleaved mode.

The time interval between 2 trigger events must be greater than or equal to 1 ADC clock period. The minimum time interval between 2 trigger events that start conversions on the same ADC is the same as in the single ADC mode.

Dual ADC mode

 When the 1st trigger occurs, all injected ADC1 channels in the group are converted

 When the 2nd trigger occurs, all injected ADC2 channels in the group are converted

 and so on

A JEOC interrupt, if enabled, is generated after all injected ADC1 channels in the group have been converted.

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RM0390 Analog-to-digital converter (ADC)

A JEOC interrupt, if enabled, is generated after all injected ADC2 channels in the group have been converted.

If another external trigger occurs after all injected channels in the group have been converted then the alternate trigger process restarts by converting the injected ADC1 channels in the group.

1st trigger

Figure 86. Alternate trigger: injected group of each ADC

EOC, JEOC on ADC1

3rd trigger

EOC, JEOC on ADC1

(n)th trigger

ADC1

ADC2

. . .

2nd trigger

EOC, JEOC on ADC2

4th trigger

EOC, JEOC on ADC2

(n+1)th trigger

Sampling

Conversion ai16059

If the injected discontinuous mode is enabled for both ADC1 and ADC2:

 When the 1st trigger occurs, the first injected ADC1 channel is converted.

 When the 2nd trigger occurs, the first injected ADC2 channel are converted

 and so on

A JEOC interrupt, if enabled, is generated after all injected ADC1 channels in the group have been converted.

A JEOC interrupt, if enabled, is generated after all injected ADC2 channels in the group have been converted.

If another external trigger occurs after all injected channels in the group have been converted then the alternate trigger process restarts.

Figure 87. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode

1st trigger 3rd trigger 5th trigger 7th trigger

JEOC on ADC1

Sampling

Conversion

ADC1

ADC2

JEOC on ADC2

2nd trigger 4th trigger 6th trigger 8th trigger ai16060

Triple ADC mode

 When the 1st trigger occurs, all injected ADC1 channels in the group are converted.

 When the 2nd trigger occurs, all injected ADC2 channels in the group are converted.

 When the 3rd trigger occurs, all injected ADC3 channels in the group are converted.

 and so on

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A JEOC interrupt, if enabled, is generated after all injected ADC1 channels in the group have been converted.

A JEOC interrupt, if enabled, is generated after all injected ADC2 channels in the group have been converted.

A JEOC interrupt, if enabled, is generated after all injected ADC3 channels in the group have been converted.

If another external trigger occurs after all injected channels in the group have been converted then the alternate trigger process restarts by converting the injected ADC1 channels in the group.

1st trigger

Figure 88. Alternate trigger: injected group of each ADC

EOC, JEOC on ADC1

4th trigger

EOC, JEOC on ADC1

(n)th trigger

Sampling

Conversion

ADC1

ADC2

. . .

2nd trigger

3rd trigger

5th trigger

EOC, JEOC on ADC2

EOC, JEOC on ADC3

(n+1)th trigger

(n+2)th trigger ai16061

13.9.5 Combined regular/injected simultaneous mode

Note:

It is possible to interrupt the simultaneous conversion of a regular group to start the simultaneous conversion of an injected group.

In combined regular/injected simultaneous mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the long conversion time of the 2 sequences (Dual ADC mode) /3 sequences (Triple ADC mode). Otherwise, the

ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions.

13.9.6 Combined regular simultaneous + alternate trigger mode

Note:

It is possible to interrupt the simultaneous conversion of a regular group to start the alternate

trigger conversion of an injected group. Figure 89

shows the behavior of an alternate trigger interrupting a simultaneous regular conversion.

The injected alternate conversion is immediately started after the injected event. If regular conversion is already running, in order to ensure synchronization after the injected conversion, the regular conversion of all (master/slave) ADCs is stopped and resumed synchronously at the end of the injected conversion.

In combined regular simultaneous + alternate trigger mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the long conversion time of the 2 sequences (Dual ADC mode) /3 sequences (Triple ADC mode).

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Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions.

If the conversion sequence is interrupted (for instance when DMA end of transfer occurs), the multi-ADC sequencer must be reset by configuring it in independent mode first (bits

DUAL[4:0] = 00000) before reprogramming the interleaved mode.

Figure 89. Alternate + regular simultaneous

1st trigger

ADC1 reg

ADC1 inj

ADC2 reg

ADC2 inj

CH0

CH3

CH1

CH5

CH2

CH0

CH6

CH2

CH6

CH3

CH7

CH0

CH3

CH7

CH4

CH8 synchro not lost

2nd trigger ai16062

If a trigger occurs during an injected conversion that has interrupted a regular conversion, it

is ignored. Figure 90 shows the behavior in this case (2nd trigger is ignored).

Figure 90. Case of trigger occurring during injected conversion

1st trigger 3rd trigger

ADC1 reg

ADC1 inj

ADC2 reg

ADC2 inj

CH0

CH3

CH1

CH5

CH2

CH0

CH6

2nd trigger

CH2 CH3

CH6 CH7

CH0

CH3

CH7

CH4

CH0

CH8

2nd trigger ai16063

The temperature sensor can be used to measure the junction temperature (T

J device.

) of the

 On STM32F446xx devices, the temperature sensor is internally connected to the same input channel, ADC1_IN18, as VBAT: ADC1_IN18 is used to convert the sensor output voltage or VBAT into a digital value. Only one conversion, temperature sensor or VBAT, must be selected at a time. When the temperature sensor and the VBAT conversion are set simultaneously, only the VBAT conversion is performed.

Figure 91

shows the block diagram of the temperature sensor.

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Note:

RM0390

When not in use, the sensor can be put in power down mode.

The TSVREFE bit must be set to enable the conversion of both internal channels: the

ADC1_IN18 (temperature sensor) and the ADC1_IN17 (VREFINT).

Main features

 Supported temperature range: –40 to 125 °C

 Precision: ±1.5 °C

Figure 91. Temperature sensor and V

REFINT

channel block diagram

TSVREFE control bit

Temperature sensor

Internal power block

VSENSE

ADC1_IN18

ADC1

VREFINT

ADC1_IN17 converted data

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1. V

SENSE

is input to ADC1_IN18.

Reading the temperature

To use the sensor:

4. Select a sampling time greater than the minimum sampling time specified in the datasheet.

5. Set the TSVREFE bit in the ADC_CCR register to wake up the temperature sensor from power down mode

6. Start the ADC conversion by setting the SWSTART bit (or by external trigger)

7. Read the resulting V

SENSE

data in the ADC data register

8. Calculate the temperature using the following formula:

Temperature (in °C) = {(V

SENSE

– V

) / Avg_Slope} + 25

Where:

– V

= V

SENSE

value for 25° C

– Avg_Slope = average slope of the temperature vs. V

SENSE or µV/°C)

curve (given in mV/°C

Refer to the datasheet electrical characteristics section for the actual values of V

Avg_Slope.

and

RM0390 Rev 6

RM0390

Note:

Analog-to-digital converter (ADC)

The sensor has a startup time after waking from power down mode before it can output

SENSE

at the correct level. The ADC also has a startup time after power-on, so to minimize the delay, the ADON and TSVREFE bits should be set at the same time.

The temperature sensor output voltage changes linearly with temperature. The offset of this linear function depends on each chip due to process variation (up to 45 °C from one chip to another).

The internal temperature sensor is more suited for applications that detect temperature variations instead of absolute temperatures. If accurate temperature reading is required, an external temperature sensor should be used.

13.11 Battery charge monitoring

Note:

The VBATE bit in the ADC_CCR register is used to switch to the battery voltage. As the

BAT

voltage could be higher than V

DDA

, to ensure the correct operation of the ADC, the

pin is internally connected to a bridge divider.

When the VBATE is set, the bridge is automatically enabled to connect:

 VBAT/4 to the ADC1_IN18 input channel

The VBAT and temperature sensor are connected to the same ADC internal channel

(ADC1_IN18). Only one conversion, either temperature sensor or VBAT, must be selected at a time. When both conversion are enabled simultaneously, only the VBAT conversion is performed.

An interrupt can be produced on the end of conversion for regular and injected groups, when the analog watchdog status bit is set and when the overrun status bit is set. Separate interrupt enable bits are available for flexibility.

Two other flags are present in the ADC_SR register, but there is no interrupt associated with them:

 JSTRT (Start of conversion for channels of an injected group)

 STRT (Start of conversion for channels of a regular group)

Table 89. ADC interrupts

Interrupt event Event flag

End of conversion of a regular group

End of conversion of an injected group

Analog watchdog status bit is set

Overrun

EOC

JEOC

AWD

OVR

Enable control bit

EOCIE

JEOCIE

AWDIE

OVRIE

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Refer to Section 1.2 on page 51 for a list of abbreviations used in register descriptions.

The peripheral registers must be written at word level (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).

13.13.1 ADC status register (ADC_SR)

Address offset: 0x00

Reset value: 0x0000 0000

Res.

5 4 3 2 1 0

OVR STRT JSTRT JEOC EOC AWD rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 OVR: Overrun

This bit is set by hardware when data are lost (either in single mode or in dual/triple mode). It is cleared by software. Overrun detection is enabled only when DMA = 1 or EOCS = 1.

0: No overrun occurred

1: Overrun has occurred

Bit 4 STRT: Regular channel start flag

This bit is set by hardware when regular channel conversion starts. It is cleared by software.

0: No regular channel conversion started

1: Regular channel conversion has started

Bit 3 JSTRT: Injected channel start flag

This bit is set by hardware when injected group conversion starts. It is cleared by software.

0: No injected group conversion started

1: Injected group conversion has started

Bit 2 JEOC: Injected channel end of conversion

This bit is set by hardware at the end of the conversion of all injected channels in the group.

It is cleared by software.

0: Conversion is not complete

1: Conversion complete

Bit 1 EOC: Regular channel end of conversion

This bit is set by hardware at the end of the conversion of a regular group of channels. It is cleared by software or by reading the ADC_DR register.

0: Conversion not complete (EOCS=0), or sequence of conversions not complete (EOCS=1)

1: Conversion complete (EOCS=0), or sequence of conversions complete (EOCS=1)

Bit 0 AWD: Analog watchdog flag

This bit is set by hardware when the converted voltage crosses the values programmed in the ADC_LTR and ADC_HTR registers. It is cleared by software.

0: No analog watchdog event occurred

1: Analog watchdog event occurred

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RM0390 Analog-to-digital converter (ADC)

13.13.2 ADC control register 1 (ADC_CR1)

Address offset: 0x04

Reset value: 0x0000 0000

31 30 29

Res.

15 14 rw

DISCNUM[2:0] rw

13 rw

Res.

OVRIE rw

25 rw

RES

24 rw

23 rw

AWDEN JAWDEN Res.

JDISCEN DISCEN JAUTO AWDSGL SCAN JEOCIE AWDIE EOCIE rw rw rw rw rw rw rw rw

20 19 18 17 16

Res.

4 rw

3 rw

2 1

AWDCH[4:0] rw rw

0 rw

Bits 31:27 Reserved, must be kept at reset value.

Bit 26 OVRIE: Overrun interrupt enable

This bit is set and cleared by software to enable/disable the Overrun interrupt.

0: Overrun interrupt disabled

1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.

Bits 25:24 RES[1:0]: Resolution

These bits are written by software to select the resolution of the conversion.

00: 12-bit (minimum 15 ADCCLK cycles)

01: 10-bit (minimum 13 ADCCLK cycles)

10: 8-bit (minimum 11 ADCCLK cycles)

11: 6-bit (minimum 9 ADCCLK cycles)

Bit 23 AWDEN: Analog watchdog enable on regular channels

This bit is set and cleared by software.

0: Analog watchdog disabled on regular channels

1: Analog watchdog enabled on regular channels

Bit 22 JAWDEN: Analog watchdog enable on injected channels

This bit is set and cleared by software.

0: Analog watchdog disabled on injected channels

1: Analog watchdog enabled on injected channels

Bits 21:16 Reserved, must be kept at reset value.

Bits 15:13 DISCNUM[2:0]: Discontinuous mode channel count

These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger.

000: 1 channel

001: 2 channels

...

111: 8 channels

Bit 12 JDISCEN: Discontinuous mode on injected channels

This bit is set and cleared by software to enable/disable discontinuous mode on the injected channels of a group.

0: Discontinuous mode on injected channels disabled

1: Discontinuous mode on injected channels enabled

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Bit 11 DISCEN: Discontinuous mode on regular channels

This bit is set and cleared by software to enable/disable Discontinuous mode on regular channels.

0: Discontinuous mode on regular channels disabled

1: Discontinuous mode on regular channels enabled

Bit 10 JAUTO: Automatic injected group conversion

This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion.

0: Automatic injected group conversion disabled

1: Automatic injected group conversion enabled

Bit 9 AWDSGL: Enable the watchdog on a single channel in scan mode

This bit is set and cleared by software to enable/disable the analog watchdog on the channel identified by the AWDCH[4:0] bits.

0: Analog watchdog enabled on all channels

1: Analog watchdog enabled on a single channel

Bit 8 SCAN: Scan mode

This bit is set and cleared by software to enable/disable the Scan mode. In Scan mode, the inputs selected through the ADC_SQRx or ADC_JSQRx registers are converted.

0: Scan mode disabled

1: Scan mode enabled

Note: An EOC interrupt is generated if the EOCIE bit is set:

– At the end of each regular group sequence if the EOCS bit is cleared to 0

– At the end of each regular channel conversion if the EOCS bit is set to 1

Note: A JEOC interrupt is generated only on the end of conversion of the last channel if the

JEOCIE bit is set.

Bit 7 JEOCIE: Interrupt enable for injected channels

This bit is set and cleared by software to enable/disable the end of conversion interrupt for injected channels.

0: JEOC interrupt disabled

1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.

Bit 6 AWDIE: Analog watchdog interrupt enable

This bit is set and cleared by software to enable/disable the analog watchdog interrupt.

0: Analog watchdog interrupt disabled

1: Analog watchdog interrupt enabled

Bit 5 EOCIE: Interrupt enable for EOC

This bit is set and cleared by software to enable/disable the end of conversion interrupt.

0: EOC interrupt disabled

1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.

Bits 4:0 AWDCH[4:0]: Analog watchdog channel select bits

These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog.

Note: 00000: ADC analog input Channel0

00001: ADC analog input Channel1

...

01111: ADC analog input Channel15

10000: ADC analog input Channel16

10001: ADC analog input Channel17

10010: ADC analog input Channel18

Other values reserved

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RM0390 Analog-to-digital converter (ADC)

13.13.3 ADC control register 2 (ADC_CR2)

Address offset: 0x08

Reset value: 0x0000 0000

31 30

Res.

SWSTART

Res.

EXTEN

28 rw

Res.

27 rw

11 rw

EXTSEL[3:0] rw

ALIGN EOCS rw

25 rw

DDS rw

24 rw

DMA rw

23 22

Res.

JSWSTART

Res.

21 20

JEXTEN rw

Res.

19 rw

Res.

18 17

JEXTSEL[3:0] rw

2 rw

16 rw

Res.

CONT ADON rw rw

Bit 31 Reserved, must be kept at reset value.

Bit 30 SWSTART : Start conversion of regular channels

This bit is set by software to start conversion and cleared by hardware as soon as the conversion starts.

0: Reset state

1: Starts conversion of regular channels

Note: This bit can be set only when ADON = 1 otherwise no conversion is launched.

Bits 29:28 EXTEN : External trigger enable for regular channels

These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group.

00: Trigger detection disabled

01: Trigger detection on the rising edge

10: Trigger detection on the falling edge

11: Trigger detection on both the rising and falling edges

Bits 27:24 EXTSEL [3:0]: External event select for regular group

These bits select the external event used to trigger the start of conversion of a regular group:

0000: Timer 1 CC1 event

0001: Timer 1 CC2 event

0010: Timer 1 CC3 event

0011: Timer 2 CC2 event

0100: Timer 2 CC3 event

0101: Timer 2 CC4 event

0110: Timer 2 TRGO event

0111: Timer 3 CC1 event

1000: Timer 3 TRGO event

1001: Timer 4 CC4 event

1010: Timer 5 CC1 event

1011: Timer 5 CC2 event

1100: Timer 5 CC3 event

1101: Timer 8 CC1 event

1110: Timer 8 TRGO event

1111: EXTI line 11

Bit 23 Reserved, must be kept at reset value.

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Analog-to-digital converter (ADC) RM0390

Bit 22 JSWSTART : Start conversion of injected channels

This bit is set by software and cleared by hardware as soon as the conversion starts.

0: Reset state

1: Starts conversion of injected channels

This bit can be set only when ADON = 1 otherwise no conversion is launched.

Bits 21:20 JEXTEN : External trigger enable for injected channels

These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group.

00: Trigger detection disabled

01: Trigger detection on the rising edge

10: Trigger detection on the falling edge

11: Trigger detection on both the rising and falling edges

Bits 19:16 JEXTSEL[3:0]: External event select for injected group

These bits select the external event used to trigger the start of conversion of an injected group.

0000: Timer 1 CC4 event

0001: Timer 1 TRGO event

0010: Timer 2 CC1 event

0011: Timer 2 TRGO event

0100: Timer 3 CC2 event

0101: Timer 3 CC4 event

0110: Timer 4 CC1 event

0111: Timer 4 CC2 event

1000: Timer 4 CC3 event

1001: Timer 4 TRGO event

1010: Timer 5 CC4 event

1011: Timer 5 TRGO event

1100: Timer 8 CC2 event

1101: Timer 8 CC3 event

1110: Timer 8 CC4 event

1111: EXTI line15

Bits 15:12 Reserved, must be kept at reset value.

Bit 11 ALIGN : Data alignment

This bit is set and cleared by software. Refer to Figure 76 and Figure 77 .

0: Right alignment

1: Left alignment

Bit 10 EOCS : End of conversion selection

This bit is set and cleared by software.

0: The EOC bit is set at the end of each sequence of regular conversions. Overrun detection is enabled only if DMA=1.

1: The EOC bit is set at the end of each regular conversion. Overrun detection is enabled.

Bit 9 DDS : DMA disable selection (for single ADC mode)

This bit is set and cleared by software.

0: No new DMA request is issued after the last transfer (as configured in the DMA controller)

1: DMA requests are issued as long as data are converted and DMA=1

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RM0390 Analog-to-digital converter (ADC)

Bit 8 DMA : Direct memory access mode (for single ADC mode)

This bit is set and cleared by software. Refer to the DMA controller chapter for more details.

0: DMA mode disabled

1: DMA mode enabled

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 CONT : Continuous conversion

This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared.

0: Single conversion mode

1: Continuous conversion mode

Bit 0 ADON : A/D Converter ON / OFF

This bit is set and cleared by software.

0: Disable ADC conversion and go to power down mode

1: Enable ADC

Address offset: 0x0C

Reset value: 0x0000 0000

Res.

SMP15_0 rw

Res.

14 rw

13 12

SMP14[2:0] rw rw

Res.

11 rw

26 rw

SMP18[2:0]

SMP13[2:0] rw rw

9 rw

24 rw

8 rw

23 rw

SMP12[2:0] rw

SMP17[2:0] rw

6 rw

21 rw

5 rw

20 rw

SMP11[2:0] rw

SMP16[2:0] rw

3 rw

18 rw

2 rw

17 16

SMP15[2:1] rw

1 rw

SMP10[2:0] rw rw

Bits 31: 27 Reserved, must be kept at reset value.

Bits 26:0 SMPx[2:0]: Channel x sampling time selection

These bits are written by software to select the sampling time individually for each channel.

During sampling cycles, the channel selection bits must remain unchanged.

Note: 000: 3 cycles

001: 15 cycles

010: 28 cycles

011: 56 cycles

100: 84 cycles

101: 112 cycles

110: 144 cycles

111: 480 cycles

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Address offset: 0x10

Reset value: 0x0000 0000

Res.

SMP5_0 rw

Res.

14 rw

29 rw

SMP4[2:0] rw

SMP9[2:0] rw

12 rw

27 rw

11 rw

26 rw

SMP3[2:0] rw

SMP8[2:0] rw

9 rw

24 rw

8 rw

23 rw

SMP2[2:0] rw

SMP7[2:0] rw

6 rw

21 rw

5 rw

20 rw

SMP1[2:0] rw

SMP6[2:0] rw

3 rw

18 rw

2 rw

17 16

SMP5[2:1] rw

1 rw

SMP0[2:0] rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:0 SMPx[2:0]: Channel x sampling time selection

These bits are written by software to select the sampling time individually for each channel.

During sample cycles, the channel selection bits must remain unchanged.

Note: 000: 3 cycles

001: 15 cycles

010: 28 cycles

011: 56 cycles

100: 84 cycles

101: 112 cycles

110: 144 cycles

111: 480 cycles

13.13.6 ADC injected channel data offset register x (ADC_JOFRx) (x=1..4)

Address offset: 0x14-0x20

Reset value: 0x0000 0000

Res.

11 rw

10 rw

9 rw

8 rw

7 rw

6 5

JOFFSETx[11:0] rw rw

4 rw

3 rw

2 rw

1 rw

0 rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 JOFFSETx[11:0]: Data offset for injected channel x

These bits are written by software to define the offset to be subtracted from the raw converted data when converting injected channels. The conversion result can be read from in the ADC_JDRx registers.

13.13.7 ADC watchdog higher threshold register (ADC_HTR)

Address offset: 0x24

Reset value: 0x0000 0FFF

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RM0390 Analog-to-digital converter (ADC)

Res.

Note:

Res.

11 rw

10 rw

9 rw

8 rw

7 rw

HT[11:0]

5 rw rw

4 rw

3 rw

2 rw

1 rw

0 rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 HT[11:0]: Analog watchdog higher threshold

These bits are written by software to define the higher threshold for the analog watchdog.

The software can write to these registers when an ADC conversion is ongoing. The programmed value will be effective when the next conversion is complete. Writing to this register is performed with a write delay that can create uncertainty on the effective time at which the new value is programmed.

13.13.8 ADC watchdog lower threshold register (ADC_LTR)

Address offset: 0x28

Reset value: 0x0000 0000

Res.

Note:

Res.

11 rw

10 rw

9 rw

8 rw

7 rw

LT[11:0]

5 rw rw

4 rw

3 rw

2 rw

1 rw

0 rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 LT[11:0]: Analog watchdog lower threshold

These bits are written by software to define the lower threshold for the analog watchdog.

Res.

Address offset: 0x2C

Reset value: 0x0000 0000

Res.

SQ16_0 rw

14 rw

13 rw

SQ15[4:0] rw

11 rw

10 rw

9 rw

Res.

8 rw rw

SQ14[4:0] rw

22 21 rw

L[3:0] rw

5 rw rw

20 rw

4 rw

19 rw

3 rw

SQ13[4:0]

SQ16[4:1] rw rw

1 rw rw

16 rw

0 rw

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Analog-to-digital converter (ADC) RM0390

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:20 L[3:0]: Regular channel sequence length

These bits are written by software to define the total number of conversions in the regular channel conversion sequence.

0000: 1 conversion

0001: 2 conversions

...

1111: 16 conversions

Bits 19:15 SQ16[4:0]: 16th conversion in regular sequence

These bits are written by software with the channel number (0..18) assigned as the 16th in the conversion sequence.

Bits 14:10 SQ15[4:0]: 15th conversion in regular sequence

Bits 9:5 SQ14[4:0]: 14th conversion in regular sequence

Bits 4:0 SQ13[4:0]: 13th conversion in regular sequence

Address offset: 0x30

Reset value: 0x0000 0000

Res.

SQ10_0 rw

Res.

14 rw

13 rw rw

28 rw

SQ9[4:0]

SQ12[4:0] rw

11 rw rw

26 rw

10 rw

25 rw

24 rw

8 rw

23 rw

SQ8[4:0]

SQ11[4:0] rw

6 rw rw

21 rw

5 rw

20 rw

19 rw

3 rw

SQ7[4:0]

SQ10[4:1] rw rw

1 rw rw

16 rw

0 rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:26 SQ12[4:0]: 12th conversion in regular sequence

These bits are written by software with the channel number (0..18

) assigned as the 12th in the sequence to be converted.

Bits 24:20 SQ11[4:0]: 11th conversion in regular sequence

Bits 19:15 SQ10[4:0]: 10th conversion in regular sequence

Bits 14:10 SQ9[4:0]: 9th conversion in regular sequence

Bits 9:5 SQ8[4:0]: 8th conversion in regular sequence

Bits 4:0 SQ7[4:0]: 7th conversion in regular sequence

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RM0390 Analog-to-digital converter (ADC)

Res.

SQ4_0 rw

Res.

14 rw

Address offset: 0x34

Reset value: 0x0000 0000

29 rw

13 rw

28 rw

SQ3[4:0] rw

SQ6[4:0] rw

11 rw

26 rw

10 rw

25 rw

9 rw

24 rw

8 rw

23 rw

SQ2[4:0] rw

SQ5[4:0] rw

6 rw

21 rw

5 rw

20 rw

19 rw

3 rw

18 17

SQ4[4:1] rw

2 rw

SQ1[4:0] rw rw

16 rw

0 rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:25 SQ6[4:0]: 6th conversion in regular sequence

These bits are written by software with the channel number (0..18) assigned as the 6th in the sequence to be converted.

Bits 24:20 SQ5[4:0]: 5th conversion in regular sequence

Bits 19:15 SQ4[4:0]: 4th conversion in regular sequence

Bits 14:10 SQ3[4:0]: 3rd conversion in regular sequence

Bits 9:5 SQ2[4:0]: 2nd conversion in regular sequence

Bits 4:0 SQ1[4:0]: 1st conversion in regular sequence

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13.13.12 ADC injected sequence register (ADC_JSQR)

Address offset: 0x38

Reset value: 0x0000 0000

Res.

JSQ4[0] rw

14 rw

Note:

Res.

13 rw

JSQ3[4:0] rw

11 rw

Res.

10 rw

Res.

9 rw

Res.

8 rw

JSQ2[4:0] rw

6 rw

JL[1:0]

20 rw

5 rw

4 rw rw

19 rw

3 rw

18 17

JSQ4[4:1] rw

2 rw

JSQ1[4:0] rw rw

16 rw

0 rw

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:20 JL[1:0]: Injected sequence length

These bits are written by software to define the total number of conversions in the injected channel conversion sequence.

00: 1 conversion

01: 2 conversions

10: 3 conversions

11: 4 conversions

Bits 19:15 JSQ4[4:0]: 4th conversion in injected sequence (when JL[1:0]=3, see note below)

These bits are written by software with the channel number (0..18) assigned as the 4th in the sequence to be converted.

Bits 14:10 JSQ3[4:0]: 3rd conversion in injected sequence (when JL[1:0]=3, see note below)

Bits 9:5 JSQ2[4:0]: 2nd conversion in injected sequence (when JL[1:0]=3, see note below)

Bits 4:0 JSQ1[4:0]: 1st conversion in injected sequence (when JL[1:0]=3, see note below)

When JL[1:0]=3 (4 injected conversions in the sequencer), the ADC converts the channels in the following order: JSQ1[4:0], JSQ2[4:0], JSQ3[4:0], and JSQ4[4:0].

When JL=2 (3 injected conversions in the sequencer), the ADC converts the channels in the following order: JSQ2[4:0], JSQ3[4:0], and JSQ4[4:0].

When JL=1 (2 injected conversions in the sequencer), the ADC converts the channels in starting from JSQ3[4:0], and then JSQ4[4:0].

When JL=0 (1 injected conversion in the sequencer), the ADC converts only JSQ4[4:0] channel.

13.13.13 ADC injected data register x (ADC_JDRx) (x= 1..4)

Address offset: 0x3C - 0x48

Reset value: 0x0000 0000

Res.

15 r

14 r

13 r

12 r

11 r

10 r

9 r

8 7 r

JDATA[15:0] r

6 r

5 r

4 r

3 r

2 r

1 r

0 r

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RM0390 Analog-to-digital converter (ADC)

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 JDATA[15:0]: Injected data

These bits are read-only. They contain the conversion result from injected channel x. The

data are left -or right-aligned as shown in Figure 76 and Figure 77

Res.

Address offset: 0x4C

Reset value: 0x0000 0000

Res.

15 r

14 r

13 r

12 r

11 r

10 r

9 r

8 7 r

DATA[15:0] r

6 r

5 r

4 r

3 r

2 r

1 r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 DATA[15:0]: Regular data

These bits are read-only. They contain the conversion result from the regular channels. The data are left- or right-aligned as shown in

Figure 76 and

Figure 77 .

0 r

Address offset: 0x00 (this offset address is relative to ADC1 base address + 0x300)

Reset value: 0x0000 0000

This register provides an image of the status bits of the different ADCs. Nevertheless it is read-only and does not allow to clear the different status bits. Instead each status bit must be cleared by writing it to 0 in the corresponding ADC_SR register.

Res.

OVR2 STRT2 r

12 r

JSTRT

ADC2

10 9 8

JEOC2 EOC2 AWD2 r r r r

Res.

21 20 19 18 17 16

OVR3 STRT3 JSTRT3 JEOC 3 EOC3 AWD3

ADC3 r

5 r

4 r

3 r

2 r

1 r

OVR1 STRT1 JSTRT1 JEOC 1 EOC1 AWD1 r r r

ADC1 r r r

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 OVR3: Overrun flag of ADC3

This bit is a copy of the OVR bit in the ADC3_SR register.

Bit 20 STRT3: Regular channel Start flag of ADC3

This bit is a copy of the STRT bit in the ADC3_SR register.

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Bit 19 JSTRT3: Injected channel Start flag of ADC3

This bit is a copy of the JSTRT bit in the ADC3_SR register.

Bit 18 JEOC3: Injected channel end of conversion of ADC3

This bit is a copy of the JEOC bit in the ADC3_SR register.

Bit 17 EOC3: End of conversion of ADC3

This bit is a copy of the EOC bit in the ADC3_SR register.

Bit 16 AWD3: Analog watchdog flag of ADC3

This bit is a copy of the AWD bit in the ADC3_SR register.

Bits 15:14 Reserved, must be kept at reset value.

Bit 13 OVR2: Overrun flag of ADC2

This bit is a copy of the OVR bit in the ADC2_SR register.

Bit 12 STRT2: Regular channel Start flag of ADC2

This bit is a copy of the STRT bit in the ADC2_SR register.

Bit 11 JSTRT2: Injected channel Start flag of ADC2

This bit is a copy of the JSTRT bit in the ADC2_SR register.

Bit 10 JEOC2: Injected channel end of conversion of ADC2

This bit is a copy of the JEOC bit in the ADC2_SR register.

Bit 9 EOC2: End of conversion of ADC2

This bit is a copy of the EOC bit in the ADC2_SR register.

Bit 8 AWD2: Analog watchdog flag of ADC2

This bit is a copy of the AWD bit in the ADC2_SR register.

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 OVR1: Overrun flag of ADC1

This bit is a copy of the OVR bit in the ADC1_SR register.

Bit 4 STRT1: Regular channel Start flag of ADC1

This bit is a copy of the STRT bit in the ADC1_SR register.

Bit 3 JSTRT1: Injected channel Start flag of ADC1

This bit is a copy of the JSTRT bit in the ADC1_SR register.

Bit 2 JEOC1: Injected channel end of conversion of ADC1

This bit is a copy of the JEOC bit in the ADC1_SR register.

Bit 1 EOC1: End of conversion of ADC1

This bit is a copy of the EOC bit in the ADC1_SR register.

Bit 0 AWD1: Analog watchdog flag of ADC1

This bit is a copy of the AWD bit in the ADC1_SR register.

Address offset: 0x04 (this offset address is relative to ADC1 base address + 0x300)

Reset value: 0x0000 0000

RM0390

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RM0390 Analog-to-digital converter (ADC)

Res.

15 14

DMA[1:0] rw rw

DDS rw

Res.

11 rw

Res.

10 9

DELAY[3:0] rw rw

Res.

TSVREFE VBATE Res.

rw rw

Res.

4 rw

Res.

3 rw

Res.

MULTI[4:0] rw

17 16 rw

ADCPRE rw

1 0 rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 TSVREFE: Temperature sensor and V

REFINT

enable

This bit is set and cleared by software to enable/disable the temperature sensor and the

REFINT

channel.

0: Temperature sensor and V

REFINT

1: Temperature sensor and V

REFINT

channel disabled

channel enabled

Note: VBATE must be disabled when TSVREFE is set. If both bits are set, only the VBAT conversion is performed.

Bit 22 VBATE: V

BAT enable

This bit is set and cleared by software to enable/disable the V

BAT

0: V

BAT

1: V

BAT

channel disabled

channel enabled

channel.

Bits 21:18 Reserved, must be kept at reset value.

Bits 17:16 ADCPRE: ADC prescaler

Set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs.

Note: 00: PCLK2 divided by 2

01: PCLK2 divided by 4

10: PCLK2 divided by 6

11: PCLK2 divided by 8

Bits 15:14 DMA: Direct memory access mode for multi ADC mode

This bit-field is set and cleared by software. Refer to the DMA controller section for more details.

00: DMA mode disabled

01: DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)

10: DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)

11: DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2)

Bit 13 DDS: DMA disable selection (for multi-ADC mode)

This bit is set and cleared by software.

0: No new DMA request is issued after the last transfer (as configured in the DMA controller). DMA bits are not cleared by hardware, however they must have been cleared and set to the wanted mode by software before new DMA requests can be generated.

1: DMA requests are issued as long as data are converted and DMA = 01, 10 or 11.

Bit 12 Reserved, must be kept at reset value.

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Bits 11:8 DELAY: Delay between 2 sampling phases

Set and cleared by software. These bits are used in dual or triple interleaved modes.

0000: 5 * T

ADCCLK

0001: 6 * T

ADCCLK

0010: 7 * T

ADCCLK

...

1111: 20 * T

ADCCLK

Bits 7:5 Reserved, must be kept at reset value.

Bits 4:0 MULTI[4:0]: Multi ADC mode selection

These bits are written by software to select the operating mode.

– All the ADCs independent:

00000: Independent mode

– 00001 to 01001: Dual mode, ADC1 and ADC2 working together, ADC3 is independent

00001: Combined regular simultaneous + injected simultaneous mode

00010: Combined regular simultaneous + alternate trigger mode

00011: Reserved

00101: Injected simultaneous mode only

00110: Regular simultaneous mode only

00111: interleaved mode only

01001: Alternate trigger mode only

– 10001 to 11001: Triple mode: ADC1, 2 and 3 working together

10001: Combined regular simultaneous + injected simultaneous mode

10010: Combined regular simultaneous + alternate trigger mode

10011: Reserved

10101: Injected simultaneous mode only

10110: Regular simultaneous mode only

10111: interleaved mode only

11001: Alternate trigger mode only

All other combinations are reserved and must not be programmed

Note: In multi mode, a change of channel configuration generates an abort that can cause a loss of synchronization. It is recommended to disable the multi ADC mode before any configuration change.

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RM0390 Analog-to-digital converter (ADC)

31 r

15 r

(ADC_CDR)

Address offset: 0x08 (this offset address is relative to ADC1 base address + 0x300)

Reset value: 0x0000 0000

30 29 r

14 r r

13 r

28 r

12 r

27 r

11 r

26 r

10 r

25 r

9 r r

24 23

DATA2[15:0] r

7 r

DATA1[15:0] r

22 r

6 r

21 r

5 r

20 r

4 r

19 r

3 r

18 r

2 r

17 r

1 r

16 r

0 r

Bits 31:16 DATA2[15:0]: 2nd data item of a pair of regular conversions

– In dual mode, these bits contain the regular data of ADC2. Refer to Dual ADC mode .

– In triple mode, these bits contain alternatively the regular data of ADC2, ADC1 and ADC3.

Refer to Triple ADC mode .

Bits 15:0 DATA1[15:0] : 1st data item of a pair of regular conversions

– In dual mode, these bits contain the regular data of ADC1. Refer to Dual ADC mode

– In triple mode, these bits contain alternatively the regular data of ADC1, ADC3 and ADC2.

Refer to Triple ADC mode .

13.14 ADC register map

The following table summarizes the ADC registers.

Offset

0x000 - 0x04C

0x050 - 0x0FC

0x100 - 0x14C

0x118 - 0x1FC

0x200 - 0x24C

0x250 - 0x2FC

0x300 - 0x308

Table 90. ADC global register map

Register

ADC1

Reserved

ADC2

Reserved

ADC3

Reserved

Common registers

Offset Register

0x00

ADC_SR

Reset value

Table 91. ADC register map and reset values for each ADC

0 0 0 0 0 0

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Table 91. ADC register map and reset values for each ADC (continued)

Offset Register

0x04

ADC_CR1

Reset value 0 0 0 0 0

DISC

NUM [2:0]

AWDCH[4:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x08

ADC_CR2 EXTSEL [3:0]

JEXTSEL

[3:0]

0x0C

0x10

0x14

0x18

0x1C

0x20

0x24

0x28

0x2C

0x30

0x34

0x38

0x3C

0x40

0x44

0x48

Reset value

ADC_SQR3

Reset value

ADC_JSQR

Reset value

ADC_JDR1

Reset value

ADC_JDR2

Reset value

ADC_JDR3

Reset value

ADC_JDR4

Reset value

ADC_SMPR1

Reset value

ADC_SMPR2

Reset value

ADC_JOFR1

Reset value

ADC_JOFR2

Reset value

ADC_JOFR3

Reset value

ADC_JOFR4

Reset value

ADC_HTR

Reset value

ADC_LTR

Reset value

ADC_SQR1

Reset value

ADC_SQR2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Sample time bits SMPx_x

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Sample time bits SMPx_x

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

JOFFSET1[11:0]

0 0 0 0 0 0 0 0 0 0 0 0

JOFFSET2[11:0]

0 0 0 0 0 0 0 0 0 0 0 0

JOFFSET3[11:0]

0 0 0 0 0 0 0 0 0 0 0 0

JOFFSET4[11:0]

0 0 0 0 0 0 0 0 0 0 0 0

HT[11:0]

1 1 1 1 1 1 1 1 1 1 1 1

LT[11:0]

L[3:0]

0 0 0 0 0 0 0 0 0 0 0 0

Regular channel sequence SQx_x bits

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Regular channel sequence SQx_x bits

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Regular channel sequence SQx_x bits

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

JL[1:0] Injected channel sequence JSQx_x bits

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

JDATA[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

JDATA[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

JDATA[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

JDATA[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Table 91. ADC register map and reset values for each ADC (continued)

Offset Register

0x4C

ADC_DR

Reset value

Regular DATA[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 92. ADC register map and reset values (common ADC registers)

Offset Register

0x00

ADC_CSR

Reset value

0 0 0 0 0 0

ADC3 -

0 0 0 0 0 0

ADC2 -

0 0 0 0 0 0

ADC1

ADC_CCR DELAY [3:0] MULTI [4:0]

0x04

0x08

Reset value

ADC_CDR

Reset value

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Regular DATA2[15:0] Regular DATA1[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 56 for the register boundary addresses.

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The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In

12-bit mode, the data could be left- or right-aligned. The DAC has two output channels, each with its own converter. In dual DAC channel mode, conversions could be done independently or simultaneously when both channels are grouped together for synchronous update operations. An input reference pin, V

REF+

(shared with ADC) is available for better resolution.

14.2 DAC main features

 Two DAC converters: one output channel each

 Left or right data alignment in 12-bit mode

 Synchronized update capability

 Noise-wave generation

 Triangular-wave generation

 Dual DAC channel for independent or simultaneous conversions

 DMA capability for each channel

 DMA underrun error detection

 External triggers for conversion

 Input voltage reference, V

REF+

Figure 92 shows the block diagram of a DAC channel and Table 93

gives the pin description.

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RM0390 Digital-to-analog converter (DAC)

Figure 92. DAC channel block diagram

Note:

DAC control register

TSE Lx[2:0] bits

SWTR IGx

TIM2_T RGO

TIM4_T RGO

TIM5_TRGO

TIM6_T RGO

TIM7_T RGO

TIM8_TRGO

DMAENx

EX TI_9

DHRx

12- bit

Control logicx

LFSRx tr ianglex

DM A req ue stx

TENx

MAMPx[3:0] bits

WAVENx[1:0] bits

12-bit

DORx

12-bit

DDA

SSA

R EF+

Digital-to-analog converterx

DAC1_ OU T1/2 ai14708d

Table 93. DAC pins

Name Signal type Remarks

REF+

Input, analog reference positive

The higher/positive reference voltage for the DAC,

1.8 V ≤ V

REF+

≤ V

DDA

Analog power supply V

DDA

SSA

Input, analog supply

Input, analog supply ground

DAC_OUTx Analog output signal

Ground for analog power supply

DAC channelx analog output

Once the DAC channelx is enabled, the corresponding GPIO pin (PA4 or PA5) is automatically connected to the analog converter output (DAC_OUTx). In order to avoid parasitic consumption, the PA4 or PA5 pin should first be configured to analog (AIN).

14.3 DAC functional description

14.3.1 DAC channel enable

Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR register. The DAC channel is then enabled after a startup time t

WAKEUP

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Note: The ENx bit enables the analog DAC channelx macrocell only. The DAC channelx digital interface is enabled even if the ENx bit is reset.

14.3.2 DAC output buffer enable

The DAC integrates two output buffers that can be used to reduce the output impedance, and to drive external loads directly without having to add an external operational amplifier.

Each DAC channel output buffer can be enabled and disabled using the corresponding

BOFFx bit in the DAC_CR register.

TSEL1[2:0]

Figure 93. DAC output buffer connection

DAC_CR.BOFF1

VREF+

CH1

DAC Buffer

Bypass, when off

PA4

TSEL2[2:0]

DAC1

CH2

VREF+

DAC

Buffer

Bypass, when off

PA5

DAC_CR.BOFF2

MSv35941V1

Depending on the selected configuration mode, the data have to be written into the specified register as described below:

 Single DAC channelx, there are three possibilities:

– 8-bit right alignment: the software has to load data into the DAC_DHR8Rx [7:0] bits (stored into the DHRx[11:4] bits)

– 12-bit left alignment: the software has to load data into the DAC_DHR12Lx [15:4] bits (stored into the DHRx[11:0] bits)

– 12-bit right alignment: the software has to load data into the DAC_DHR12Rx [11:0] bits (stored into the DHRx[11:0] bits)

Depending on the loaded DAC_DHRyyyx register, the data written by the user is shifted and stored into the corresponding DHRx (data holding registerx, which are internal non-memorymapped registers). The DHRx register is then loaded into the DORx register either automatically, by software trigger or by an external event trigger.

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Figure 94. Data registers in single DAC channel mode

31 24 15 7 0

8-bit right aligned

12-bit left aligned

12-bit right aligned ai14710b

 Dual DAC channels, there are three possibilities:

– 8-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR8RD

[7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded into the DAC_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits)

– 12-bit left alignment: data for DAC channel1 to be loaded into the DAC_DHR12LD

[15:4] bits (stored into the DHR1[11:0] bits) and data for DAC channel2 to be loaded into the DAC_DHR12LD [31:20] bits (stored into the DHR2[11:0] bits)

– 12-bit right alignment: data for DAC channel1 to be loaded into the

DAC_DHR12RD [11:0] bits (stored into the DHR1[11:0] bits) and data for DAC channel2 to be loaded into the DAC_DHR12LD [27:16] bits (stored into the

DHR2[11:0] bits)

Depending on the loaded DAC_DHRyyyD register, the data written by the user is shifted and stored into DHR1 and DHR2 (data holding registers, which are internal non-memorymapped registers). The DHR1 and DHR2 registers are then loaded into the DOR1 and

DOR2 registers, respectively, either automatically, by software trigger or by an external event trigger.

Figure 95. Data registers in dual DAC channel mode

24 15 7 0

8-bit right aligned

12-bit left aligned

12-bit right aligned ai14709b

The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must be performed by loading the DAC_DHRx register (write to DAC_DHR8Rx, DAC_DHR12Lx,

DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12LD or DAC_DHR12RD).

Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR register is set) and a trigger occurs, the transfer is performed three APB1 clock cycles later.

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When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage becomes available after a time t

SETTLING analog output load.

that depends on the power supply voltage and the

Figure 96. Timing diagram for conversion with trigger disabled TEN = 0

APB1_CLK

DHR 0x1AC

DOR 0x1AC t

SETTLING

Output voltage available on DAC_OUT pin ai14711b

Digital inputs are converted to output voltages on a linear conversion between 0 and V

REF+

The analog output voltages on each DAC channel pin are determined by the following equation:

REF



4096

If the TENx control bit is set, conversion can then be triggered by an external event (timer counter, external interrupt line). The TSELx[2:0] control bits determine which out of 8 possible events will trigger conversion as shown in

Table 94

Table 94. External triggers

Type Source

Timer 6 TRGO event

Timer 8 TRGO event

Timer 7 TRGO event

Timer 5 TRGO event

Timer 2 TRGO event

Timer 4 TRGO event

EXTI line9

SWTRIG

Internal signal from on-chip timers

External pin

Software control bit

TSEL[2:0]

000

001

010

011

100

101

110

111

Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on the selected external interrupt line 9, the last data stored into the DAC_DHRx register are transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1 cycles after the trigger occurs.

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Note:

Digital-to-analog converter (DAC)

If the software trigger is selected, the conversion starts once the SWTRIG bit is set.

SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the

DAC_DHRx register contents.

TSELx[2:0] bit cannot be changed when the ENx bit is set.

When software trigger is selected, the transfer from the DAC_DHRx register to the

DAC_DORx register takes only one APB1 clock cycle.

Each DAC channel has a DMA capability. Two DMA channels are used to service DAC channel DMA requests.

A DAC DMA request is generated when an external trigger (but not a software trigger) occurs while the DMAENx bit is set. The value of the DAC_DHRx register is then transferred into the DAC_DORx register.

In dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one

DMA request is needed, you should set only the corresponding DMAENx bit. In this way, the application can manage both DAC channels in dual mode by using one DMA request and a unique DMA channel.

DMA underrun

The DAC DMA request is not queued so that if a second external trigger arrives before the acknowledgement for the first external trigger is received (first request), then no new request is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register is set, reporting the error condition. DMA data transfers are then disabled and no further

DMA request is treated. The DAC channelx continues to convert old data.

The software should clear the DMAUDRx flag by writing “1”, clear the DMAEN bit of the used DMA stream and re-initialize both DMA and DAC channelx to restart the transfer correctly. The software should modify the DAC trigger conversion frequency or lighten the

DMA workload to avoid a new DMA underrun. Finally, the DAC conversion could be resumed by enabling both DMA data transfer and conversion trigger.

For each DAC channelx, an interrupt is also generated if its corresponding DMAUDRIEx bit in the DAC_CR register is enabled.

In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift register) is available. DAC noise generation is selected by setting WAVEx[1:0] to “01”. The preloaded value in LFSR is 0xAAA. This register is updated three APB1 clock cycles after each trigger event, following a specific calculation algorithm.

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Figure 97. DAC LFSR register calculation algorithm

XOR

11 10 9

8 7 6 5 4 3 2 1

RM0390

NOR

Note: ai14713c

The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this value is then stored into the DAC_DORx register.

If LFSR is 0x0000, a ‘1 is injected into it (antilock-up mechanism).

It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits.

Figure 98. DAC conversion (SW trigger enabled) with LFSR wave generation

APB1_CLK

DHR 0x00

DOR 0xAAA 0xD55

SWTRIG

The DAC trigger must be enabled for noise generation by setting the TENx bit in the

DAC_CR register.

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It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal.

DAC triangle-wave generation is selected by setting WAVEx[1:0] to “10”. The amplitude is configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter is incremented three APB1 clock cycles after each trigger event. The value of this counter is then added to the DAC_DHRx register without overflow and the sum is stored into the

DAC_DORx register. The triangle counter is incremented as long as it is less than the maximum amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is reached, the counter is decremented down to 0, then incremented again and so on.

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RM0390 Digital-to-analog converter (DAC)

It is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits.

Figure 99. DAC triangle wave generation

MAMPx[3:0] max amplitude

+ DAC_DHRx base value

Decrementation

Incrementation

DAC_DHRx base value

0 ai14715c

Figure 100. DAC conversion (SW trigger enabled) with triangle wave generation

APB1_CLK

DHR 0x00

DOR 0xAAA 0xD55

Note:

SWTRIG ai14714b

The DAC trigger must be enabled for noise generation by setting the TENx bit in the

DAC_CR register.

The MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be changed.

14.4 Dual DAC channel conversion

To efficiently use the bus bandwidth in applications that require the two DAC channels at the same time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A unique register access is then required to drive both DAC channels at the same time.

Eleven possible conversion modes are possible using the two DAC channels and these dual registers. All the conversion modes can nevertheless be obtained using separate DHRx registers if needed.

All modes are described in the paragraphs below.

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To configure the DAC in this conversion mode, the following sequence is required:

 Set the two DAC channel trigger enable bits TEN1 and TEN2

 Configure different trigger sources by setting different values in the TSEL1[2:0] and

TSEL2[2:0] bits

 Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,

DAC_DHR12LD or DAC_DHR8RD)

When a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1

(three APB1 clock cycles later).

When a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2

(three APB1 clock cycles later).

To configure the DAC in this conversion mode, the following sequence is required:

 Set the two DAC channel trigger enable bits TEN1 and TEN2

 Configure different trigger sources by setting different values in the TSEL1[2:0] and

TSEL2[2:0] bits

 Configure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask value in the MAMPx[3:0] bits

 Load the dual DAC channel data into the desired DHR register (DHR12RD, DHR12LD or DHR8RD)

When a DAC channel1 trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). Then the LFSR1 counter is updated.

When a DAC channel2 trigger arrives, the LFSR2 counter, with the same mask, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). Then the LFSR2 counter is updated.

To configure the DAC in this conversion mode, the following sequence is required:

 Set the two DAC channel trigger enable bits TEN1 and TEN2

 Configure different trigger sources by setting different values in the TSEL1[2:0] and

TSEL2[2:0] bits

 Configure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR masks values in the MAMP1[3:0] and MAMP2[3:0] bits

 Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,

DAC_DHR12LD or DAC_DHR8RD)

When a DAC channel1 trigger arrives, the LFSR1 counter, with the mask configured by

MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1

(three APB1 clock cycles later). Then the LFSR1 counter is updated.

When a DAC channel2 trigger arrives, the LFSR2 counter, with the mask configured by

MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2

(three APB1 clock cycles later). Then the LFSR2 counter is updated.

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RM0390 Digital-to-analog converter (DAC)

To configure the DAC in this conversion mode, the following sequence is required:

 Set the two DAC channel trigger enable bits TEN1 and TEN2

 Configure different trigger sources by setting different values in the TSEL1[2:0] and

TSEL2[2:0] bits

 Configure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum amplitude value in the MAMPx[3:0] bits

 Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,

DAC_DHR12LD or DAC_DHR8RD)

When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with the same triangle amplitude, is added to the DHR1 register and the sum is transferred into

DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated.

When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with the same triangle amplitude, is added to the DHR2 register and the sum is transferred into

DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated.

To configure the DAC in this conversion mode, the following sequence is required:

 Set the two DAC channel trigger enable bits TEN1 and TEN2

 Configure different trigger sources by setting different values in the TSEL1[2:0] and

TSEL2[2:0] bits

 Configure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits

 Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,

DAC_DHR12LD or DAC_DHR8RD)

When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated.

When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with a triangle amplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated.

14.4.6 Simultaneous software start

To configure the DAC in this conversion mode, the following sequence is required:

 Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD,

DAC_DHR12LD or DAC_DHR8RD)

In this configuration, one APB1 clock cycle later, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and DAC_DOR2, respectively.

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To configure the DAC in this conversion mode, the following sequence is required:

 Set the two DAC channel trigger enable bits TEN1 and TEN2

 Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits

 Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD,

DAC_DHR12LD or DAC_DHR8RD)

When a trigger arrives, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and

DAC_DOR2, respectively (after three APB1 clock cycles).

To configure the DAC in this conversion mode, the following sequence is required:

 Set the two DAC channel trigger enable bits TEN1 and TEN2

 Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits

 Configure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask value in the MAMPx[3:0] bits

 Load the dual DAC channel data to the desired DHR register (DHR12RD, DHR12LD or

DHR8RD)

When a trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The

LFSR1 counter is then updated. At the same time, the LFSR2 counter, with the same mask, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The LFSR2 counter is then updated.

14.4.9 Simultaneous trigger with different LFSR generation

To configure the DAC in this conversion mode, the following sequence is required:

 Set the two DAC channel trigger enable bits TEN1 and TEN2

 Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits

 Configure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR mask values using the MAMP1[3:0] and MAMP2[3:0] bits

 Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,

DAC_DHR12LD or DAC_DHR8RD)

When a trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The LFSR1 counter is then updated.

At the same time, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The LFSR2 counter is then updated.

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14.4.10 Simultaneous trigger with single triangle generation

To configure the DAC in this conversion mode, the following sequence is required:

 Set the two DAC channel trigger enable bits TEN1 and TEN2

 Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits

 Configure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum amplitude value using the MAMPx[3:0] bits

 Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,

DAC_DHR12LD or DAC_DHR8RD)

When a trigger arrives, the DAC channel1 triangle counter, with the same triangle amplitude, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three

APB1 clock cycles later). The DAC channel1 triangle counter is then updated.

At the same time, the DAC channel2 triangle counter, with the same triangle amplitude, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated.

14.4.11 Simultaneous trigger with different triangle generation

To configure the DAC in this conversion mode, the following sequence is required:

 Set the two DAC channel trigger enable bits TEN1 and TEN2

 Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits

 Configure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits

 Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,

DAC_DHR12LD or DAC_DHR8RD)

When a trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into

DAC_DOR1 (three APB1 clock cycles later). Then the DAC channel1 triangle counter is updated.

At the same time, the DAC channel2 triangle counter, with a triangle amplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2

(three APB1 clock cycles later). Then the DAC channel2 triangle counter is updated.

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Refer to Section 1 on page 51

for a list of abbreviations used in register descriptions.

The peripheral registers have to be accessed by words (32 bits).

14.5.1 DAC control register (DAC_CR)

Res.

Address offset: 0x00

Reset value: 0x0000 0000

DMAU

DRIE2 rw

DMAU

DRIE1 rw

DMA

EN2 rw

DMA

EN1 rw

27 rw

11 rw

MAMP2[3:0] rw

10 rw

MAMP1[3:0] rw

25 rw

24 rw

8 rw

WAVE2[1:0] rw

7 rw

WAVE1[1:0] rw

22 rw

21 20 19 rw

TSEL2[2:0] rw

TSEL1[2:0] rw

3 rw rw rw

18 17 16

TEN2 BOFF2 EN2 rw

2 rw

1 rw

TEN1 BOFF1 EN1 rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 DMAUDRIE2 : DAC channel2 DMA underrun interrupt enable

This bit is set and cleared by software.

0: DAC channel2 DMA underrun interrupt disabled

1: DAC channel2 DMA underrun interrupt enabled

Bit 28 DMAEN2 : DAC channel2 DMA enable

This bit is set and cleared by software.

0: DAC channel2 DMA mode disabled

1: DAC channel2 DMA mode enabled

Bits 27:24 MAMP2[3:0] : DAC channel2 mask/amplitude selector

These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode.

0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1

0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3

0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7

0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15

0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31

0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63

0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127

0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255

1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511

1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023

1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047

≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

Bits 23:22 WAVE2[1:0] : DAC channel2 noise/triangle wave generation enable

These bits are set/reset by software.

00: wave generation disabled

01: Noise wave generation enabled

1x: Triangle wave generation enabled

Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)

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Bits 21:19 TSEL2[2:0] : DAC channel2 trigger selection

These bits select the external event used to trigger DAC channel2

000: Timer 6 TRGO event

001: Timer 8 TRGO event

010: Timer 7 TRGO event

011: Timer 5 TRGO event

100: Timer 2 TRGO event

101: Timer 4 TRGO event

110: External line9

111: Software trigger

Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).

Bit 18 TEN2 : DAC channel2 trigger enable

This bit is set and cleared by software to enable/disable DAC channel2 trigger

0: DAC channel2 trigger disabled and data written into the DAC_DHRx register are transferred one APB1 clock cycle later to the DAC_DOR2 register

1: DAC channel2 trigger enabled and data from the DAC_DHRx register are transferred three APB1 clock cycles later to the DAC_DOR2 register

Note: When software trigger is selected, the transfer from the DAC_DHRx reg ister to the

DAC_DOR2 register takes only one APB1 clock cycle.

Bit 17 BOFF2 : DAC channel2 output buffer disable

This bit is set and cleared by software to enable/disable DAC channel2 output buffer.

0: DAC channel2 output buffer enabled

1: DAC channel2 output buffer disabled

Bit 16 EN2 : DAC channel2 enable

This bit is set and cleared by software to enable/disable DAC channel2.

0: DAC channel2 disabled

1: DAC channel2 enabled

Bits 15:14 Reserved, must be kept at reset value.

Bit 13 DMAUDRIE1 : DAC channel1 DMA Underrun Interrupt enable

This bit is set and cleared by software.

0: DAC channel1 DMA Underrun Interrupt disabled

1: DAC channel1 DMA Underrun Interrupt enabled

Bit 12 DMAEN1 : DAC channel1 DMA enable

This bit is set and cleared by software.

0: DAC channel1 DMA mode disabled

1: DAC channel1 DMA mode enabled

RM0390 Rev 6

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423

Digital-to-analog converter (DAC) RM0390

Bits 11:8 MAMP1[3:0] : DAC channel1 mask/amplitude selector