STOTG04E
USB-OTG Full-speed Transceiver
Feature summary
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Meets USB specification Rev. 2.0 And on-thego supplement to the USB 2.0 specification
Analog car kit-compatible
Four operating modes: USB, I
2
C, UART and
Audio
Configurable using I
2
C serial interface
Capable of 12Mbit/s full-speed and 1.5Mbit/s low-speed modes of operation
Standard digital interface compliant with the
OTG transceiver specification
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
35mA typical V
BUS charge pump output current for 3.3V supply voltage
Ability to control external charge pump for higher VBUS currents
Integrated pull-up/-down resistors
±6kV ESD Protection on all USB pins (contact discharge)
+1.6V to +3.6V Digital power supply and +2.7V to +5.5V analog supply voltage range
Power-down mode with very low power consumption for battery powered devices
Applications
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Mobile phones
PDAs
MP3 players
Digital cameras
Printers
QFN24 (4mmx4mm)
Description
The STOTG04 is a USB On-The-Go full-speed transceiver. It provides complete physical layer
(PHY) solution for any USB-OTG device. It contains V
BUS
charge pump and comparators, ID line detector and interrupt generator, and the USB differential driver and receivers. The STOTG04 transceiver is suitable for mobile and battery powered devices because of its low power consumption and power-down operating mode.
The transceiver is capable of operation in several different modes. It can operate in basic USB-OTG mode, as an I
2
C and UART transceiver, or in audio mode. Behavior of the transceiver is fully configurable through the two-wire I
2
C serial bus.
The transceiver supports session request protocol and host negotiation protocol.
The applications are mobile phones, PDAs, MP3 players, printers and digital cameras.
Order code
Part number
STOTG04EQTR
October 2006
Package
QFN24 (4mm x 4mm)
Rev. 3
Packaging
4000 parts per reel
1/26 www.st.com
26
7
8
3
4
1
2
5
6
Contents
Contents
STOTG04E
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Charge pump characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1
Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2
V
BUS
Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.4
ID Line detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.5
Driver and receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.6
Control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.7
Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.7.1
Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.7.2
USB Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.7.3
UART and I
2
C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.7.4
Audio mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.8
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.9
I
2
C Bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.10
Device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.11
Bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.12
External charge pump switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/26
STOTG04E
1 Pin configuration
Figure 1.
Pin connections (Bottom View )
Pin configuration
7
8
2
3
4
5
6
Table 1.
Pin description
PlN N° SYMBOL
1
9
10
11
12
13
14
15
16
17
18
19
ADR_PSW
SDA
SCL
RESET/
INT/
SPEED
V
TRM
SUSPEND
OE_TP_INT/
VM
VP
RCV
ExpPad
SE0_VM
DAT_VP
D-
D+
GND
ID
V
BUS
I/O NAME AND FUNCTION
I/O
Least significant bit of the I
2
C address of the transceiver input latched on reset;
PSW output enabling or disabling an external charge pump
I/O I
2
C serial data (1)
I I
2
C clock
I Active low logic reset
O Active low interrupt signal (open-drain)
I
Power
I
I/O
Mode of the transceiver (0 = low-speed, 1 = full-speed) (2)
Internal voltage regulator output; an external decoupling capacitor should be connected (3)
Power down input (0 = active mode, 1 = power down) (See Table 8
)
Output enable of the differential driver in the USB mode, I
2
C data enable in the
I
2
C mode or interrupt output
O D– single-ended receiver output
O D+ single-ended receiver output
O Differential receiver output
Not Connected
I/O
Single-ended zero input/output in the DAT_SE0 transmit mode, negative data input/output in the single-ended transmit mode or TXD in the UART mode
I/O
I/O
Data input/output in the DAT_SE0 transmit mode, positive data input/output in the single-ended transmit mode or RXD in the UART mode
Negative data line in the USB mode, I
2
C clock output in the I
2
C mode or serial data output in the UART mode
I/O
Positive data line in the USB mode, I
2
C serial data in the I
2
C mode or serial data input in the UART mode
Power Common analog and digital ground
I/O ID pin of the USB connector used for protocol identification
I/O V
BUS
line of the USB interface – it needs an external capacitor of 4.7µF
3/26
Pin configuration
PlN N° SYMBOL I/O NAME AND FUNCTION
20
21
22
23
V
BAT
CAP1
CAP2
CGND
Power Analog power supply voltage (+2.7V to +5.5V)
I/O
I/O
External capacitor pin for the charge pump
External capacitor pin for the charge pump
Power Ground for the charge pump
24 V
IF
Power Logic power supply (+1.6V to 3.6V)
(1) Input and open-drain output
(2) Input with internal pull-up resistor
(3) Internal regulator can be bypassed by connecting V
BAT
to this pin when the V
BAT
is in range of 2.7V to 3.6V
Figure 2.
Functional diagram
STOTG04E
4/26
STOTG04E Maximum ratings
Table 2.
Absolute maximum ratings
Symbol Parameter Value Unit
V
IF
V
BAT
Logic Supply Voltage
Analog Supply Voltage
-0.5 to + 4.5
-0.5 to + 6.5
V
V
V
DCDIG
T
V
STG
ESD
DC Input Voltage on any logic interface pin
Storage Temperature Range
Electrostatic discharge voltage on USB pins
Human Body Model
Contact Discharge (*)
-0.5 to + 4.5
-65 to + 150
± 8
± 6
V
°C kV
(*) In accordance to IEC61000-4-2, level 3.
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional Operation under these conditions is not implied.
Table 3.
Thermal data
Symbol
R thJA
Parameter
Thermal Resistance Junction-Ambient
Value
59
Unit
°C/W
Table 4.
Recommended operating condition
Symbol Parameter
V
IF
V
BAT
T
A
C
EXT
C
T
C
TRM
R
S
Logic Supply Voltage
Analog Supply Voltage
Operating Temperature Range
Charge pump external capacitor
Charge pump tank capacitor
Voltage regulator external capacitor
Data lines impedance matching resistor
Min.
1.6
2.7
-40
100
1
Table 5.
ESD Performance
Symbol
ESD
IEC-61000-4-2 (other pins)
Parameter
IEC-61000-4-2 (D+, D-, VBUS, ID)
Air discharge (10 pulses)
Contact discharge (10 pulses)
Air discharge (10 pulses)
Contact discharge (10 pulses)
Typ.
1.8
3.3
220
4.7
1
20
Value
± 8
± 6
± 2
± 2
Max.
3.6
5.5
+85
470
6.5
Unit kV
Unit
V
V
°C nF
µF
µF
Ω
5/26
Electrical characteristics STOTG04E
Table 6.
Electrical characteristics
Characteristics measured over recommended operating conditions unless otherwise is noted. All typical values are referred to T
A
= 25°C, V
IF
= 1.8V, V
BAT
= 3.3V, R
S
= 20
Ω,
C
EXT
= 220nF, C
T
= 4.7µF and C
TRM
= 1µF
Symbol Parameter Test Conditions Min.
Typ.
Max.
Unit
I
IF
I
BAT
Digital Part Supply Current
Operating Supply Current
Active mode (1,2)
Power down mode
Transceiver current while transmitting and receiving (1, 2)
Charge pump current, I
LOAD
= 8mA
Power down mode (4)
0.6
4.5
17
1.6
1
7
25
1 mA
µA mA
µA
LOGIC INPUTS AND OUTPUTS
V
OH
V
OL
HIGH level output voltage
LOW level output voltage
I
OH
= -100µA
I
OH
= -2mA
I
OL
= 100µA
I
OL
= 2mA
V
IF
-0.15
V
IF
-0.40
0.15
0.40
V
IH
V
IL
I
LKG
I
OZ
V
BUS
V
BUS
V
BUS_LKG
V
BUS_RIP f
CP
R
VBUS
I
VBUS
V
BUS_VLD
V
SES_VLD
R
VBUS_PU
R
VBUS_PD
HIGH level input voltage
LOW level input voltage
Input leakage current
Off-state output current
V
BUS
output voltage
V
BUS
leakage voltage
V
BUS
output ripple
Charge-pump switching frequency (2)
I
I
LOAD
= 8mA
No Load
LOAD
= 8mA, C
T
= 4.7µF
V
BUS
input impedance
Maximum V
BUS
source current C
EXT
= 220 nF, V
BUS
> 4.4V
V
BUS
valid comparator threshold
Low to high transition
High to low transition
Low to high transition Session valid comparator threshold for both A and B devices
High to low transition
V
BUS
charge pull-up resistance
V
BUS
discharge pull-down resistance
0.7V
IF
-1
-5
4.4
0.5
40
20
4.40
4.40
0.8
0.8
281
656
4.9
3
30
0.8
76
35
640
1260
0.3V
IF
1
5
5.25
V
200 mV
60 mV
100
2.0
2.0
V
V
V
µA
µA
V
V
V
1.5
MHz k
Ω mA
V
V
Ω
Ω
ID
V
ID_BIAS
R
ID_PU
R
ID_GND
R
ID_FLOAT
ID pin bias voltage
ID pin pull-up resistance
R
CP_ID
= 140k Ω, V
ID line short resistance to detect id_gnd state
ID line short resistance to detect id_float state
BAT
≤ 5V
1.3
70
800
1.9
105
3.0
130
10
V k Ω
Ω k Ω
6/26
STOTG04E Electrical characteristics
Symbol Parameter Test Conditions Min.
Typ.
Max.
Unit
DIFFERENTIAL DRIVER
V
Z
DRV
OH_DRV
V
OL_DRV
V
CRS
Output Impedance
HIGH level output voltage
LOW level output voltage
Driver crossover voltage
Excluding external R
S
R
LH
= 14.25k
Ω, V
TRM
= 3.3V
R
LH
= 14.25k
Ω, V
TRM
= 2.7V
R
LL
= 1.425k
Ω
C
LOAD
= 50 to 600pF
DIFFERENTIAL AND SINGLE-ENDED RECEIVERS
V
V
DI
SE-TH
Differential receiver input sensitivity (V
D+
- V
D-
)
SE receivers switching threshold
R
IN
C
IN
Input resistance
Input capacitance
R
R
PU_D+
PU_D-
Data line pull-up resistance on pin D+
Data line pull-up resistance on pin D-
Data line pull-down resistance R
PD
V
DT_LKG
Data line leakage voltage
CAR KIT INTERRUPT DETECTOR
V
CM
= 0.8 to 2.5V
Low to high transition
High to low transition
PU/PD resistor deactivated
Bus Idle
Receiving mode
R
PU_EXT
= 300k Ω
8
2.8
2.6
0
1.3
-200
0.8
0.8
1.5
10 30
900 1300 1575
1425 2200 3090
900
16
1.67
1.6
1.1
1300
24
3.6
3.0
0.3
2.0
200
2.0
2.0
1575
V
CR_INT_TH
Car kit Interrupt threshold
I
2
C AND UART MODES – D+ AND D- PINS
0.4
0.6
V
OH
V
OL
V
IH
V
IL
R
DP_I2C
HIGH level output voltage (3) I
OH
LOW level output voltage
HIGH level input voltage
LOW level input voltage
SDA line internal pull-up resist.
VOLTAGE REGULATOR
= -2mA
I
OL
= 2mA
2.4
0
2.0
3.6
0.4
0.8
1425 2200 3090
V
I
TRM
TRM
Internal power supply voltage
Voltage regulator output current
V
BAT
= 3.3 to 5V, no load; 2V7en=0
V
BAT
= 2.8 to 5V, no load; 2V7en=1
V
BAT
= 3.6V, V
TRM
> 3V; 2V7en=0
V
BAT
= 3.0V, V
TRM
>2.6V; 2V7en=1
3.0
2.6
3.3
2.75
(1) Transmitting and receiving at 12Mbit/s, loads of 50pF on D+ and D- pins, no capacitive loads on VP and VM pins
(2) Not tested in production; characterization only
(3) Except D+ pin in the I2C mode where this pin is open-drain with internal pull-up resistor
(4) See paragraph 6.7.1
3.6
2.9
20
10
V
V
Ω
V
V mV
V
M
Ω
14.25
17.0
24.8
k Ω
200 342 mV
V
V mA mA
V
V
V
V
Ω
Ω pF
Ω
V
7/26
Electrical characteristics STOTG04E
Table 7.
Switching characteristics
Over recommended operating conditions unless otherwise is noted. All the typical values are referred to T
A
= 25°C, V
IF
= 1.8V, V
BAT
= 3.3V, R
S
= 20
Ω, C
EXT
= 220nF, C
T
= 4.7µF, and
C
TRM
= 1µF
Symbol Parameter Test Conditions Min.
Typ.
Max.
Unit
T
VBUS_RISE
V
BUS
rise time
DIFFERENTIAL DRIVER
I
LOAD
= 8mA, C
T
= 10µF 1 100 ms t
R t
F t
P_DRV_R
Data signal rise time
Data signal rise time
Propagation delay of the driver, rising edge; DAT_SE0 mode
Propagation delay of the driver, rising edge; VP_VM mode
Propagation delay of the driver, falling edge; DAT_SE0 mode t
P_DRV_F
Propagation delay of the driver, rising edge; VP_VM mode t
RFM
Rise and fall time matching (t
R
/ t
F
) excluding the first transition from the idle state
SINGLE-ENDED RECEIVERS
Full-speed mode, C
LOAD
= 50pF
Low-speed mode, C
LOAD
= 600pF
Full-speed mode, C
LOAD
= 50pF
Low-speed mode, C
LOAD
= 600pF
Full-speed mode, C
LOAD
= 50pF
Low-speed mode, C
LOAD
= 600pF
Full-speed mode, C
LOAD
= 50pF
Low-speed mode, C
LOAD
= 600pF
Full-speed mode, C
LOAD
= 50pF
Low-speed mode, C
LOAD
= 600pF
Full-speed mode, C
LOAD
= 50pF
Low-speed mode, C
LOAD
= 600pF
Full-speed mode
Low-speed mode
4
75
4
75
90
80
8.5
110
8.5
110
20
300
20
300
38
280
55
300
38
280
55
300
111.11
125 ns ns ns ns ns ns
% t
P_SE_R t
P_SE_F
Propagation delay of the SE receiver, rising edge
Propagation delay of the SE receiver, falling edge
Full-speed mode, input slope 15ns
Low-speed mode, input slope
150ns
Full-speed mode, input slope 15ns
Low-speed mode, input slope
150ns
18
18
18
18 ns ns
DIFFERENTIAL RECEIVER t
P_DIF_R t
P_DIF_F
Propagation delay of the SE receiver, rising edge
Propagation delay of the SE receiver, falling edge
Full-speed mode, input slope 15ns
Low-speed mode, input slope
150ns
Full-speed mode, input slope 15ns
Low-speed mode, input slope
150ns
24
24
24
24 ns ns
DIGITAL INTERFACE t
SET_OE t t
TA_OI
TA_IO
Output enable setup time
Output to input bus turnaround time (1, 2)
Output to input bus turnaround time (1, 2)
I
2
C BUS (3) f
SCL t
LOW t
HIGH t
IICR
SCL clock frequency
Low period of the SCL clock
High period of the SCL clock
Rise time of both SDA and SCL signals
50
0
0
4.7
4.0
5
5 ns ns ns
100 kHz
µs
µs
1000 ns
8/26
STOTG04E
Symbol Parameter Test Conditions t t t
IICF
SU_STA
HD_STA
Fall time of both SDA and SCL signals
Setup time for a repeated START condition
Hold time for the START and repeated START conditions t
SU_DAT t
HD_DAT
Data setup time
Data hold time t
SU_STO t
BUF
Setup time for the STOP condition
Bus free time between a STOP and START condition
NOTE 1: Parameter applies to the OE_TP_INT/, DAT_VP, and SE0_VM signals
NOTE 2: Not tested in production; characterization only
NOTE 3: Requirements defined by the I2C-Bus Specification, version 2.1
Electrical characteristics
4.7
4.0
250
0
4.0
4.7
Min.
Typ.
Max.
Unit
300 ns
µs
µs ns
µs
µs
µs
9/26
Charge pump characteristics
4 Charge pump characteristics
Figure 3.
Output characteristics Figure 4.
Output ripple
STOTG04E
10/26
STOTG04E
Figure 5.
Rise and fall times
Figure 6.
Differential driver propagation delay
Timing diagrams
Figure 7.
Differential receiver propagation delay
11/26
Timing diagrams
Figure 8.
Output enable setup time
OE_TP_INT/
V
IH
V
IL
V
IH
DAT_VP
SE0_VM
V
IL
t
SET_OE
USB Idle State
Figure 9.
Bus turnaround time t
TA_OI
OE_TP_INT/
V
IH
V
IL
V
IH
DAT_VP
SE0_VM
V
IL output
Figure 10. I
2
C BUS timing
Data to Transmit
input t
TA_IO
STOTG04E output t
LOW t
IIC_F
SCL
SDA t
IIC_F
S t
HD_STA t
SU_DAT t
HIGH t
HD_DAT t
IIC_R t
HD_STA
Sr t
SU_STA t
SU_STO
P t
IIC_R t
BUF
S
12/26
STOTG04E
Figure 11. Block diagram
A D R _ P S W
S C L
S D A
S P E E D
S U S P E N D
O s c illa t o r
C A P 1
C h a r g e
P u m p
C A P 2
Timing diagrams
V B A T
V B U S
V B A T
B a n d g a p
R e f e r e n c e
V T R M
O E _ T P _ I N T /
D A T _ V P
S E 0 _ V M
R C V
V P
V M
V B A T
V B A T
V o lt a g e
R e g u la t o r
V T R M
I D
D +
D -
I N T /
R E S E T /
13/26
Block description STOTG04E
The STOTG04 integrates a charge pump and comparators for the V
BUS
, ID line detector and interrupt switch, differential data driver, differential and single-ended receivers, low dropout voltage regulator and control logic. The STOTG04 provides a complete solution for connection of a digital USB OTG controller to the physical Universal Serial Bus.
The V
BUS
line voltage is provided using the internal charge pump. It is capable of sourcing up to 35mA load current. The charge pump can be powered by voltage from 2.7V to 5.5V. It needs two capacitors for its operation: an external capacitor of 220nF connected between the CAP1 and CAP2 pins and a 4.7µF decoupling tank capacitor on the V
BUS
. If an application needs current that is higher than 35mA, an external charge pump or a switch controlled by the ADR_PSW pin may be used.
6.2 V
BUS
Comparators
These comparators monitor the V
BUS
voltage. They provide current status information for the V
BUS
line.
V
BUS
valid status means that the voltage is above V
BUS_VLD
. Session valid status means that the V
BUS voltage is above V
SES_VLD
level.
An internal low-dropout voltage regulator provides power for the bus drivers and receivers. The regulator needs an external capacitor of 1µF on the V
TRM
pin for proper operation. The regulator can provide 3.3V
or 2.75V output voltages according to 2V7_en bit in Control Register 3.
The regulator can be bypassed by tying the V
TRM
pin to the V
BAT
power supply voltage when the analog supply voltage is in the range of 3.0V (or 2.7V) to 3.6V.
6.4 ID Line detector
This block senses ID line status. It is capable of detecting three different line states:
• pin floating;
• pin tied to ground;
• pin grounded via a 140k Ω resistor.
The ID detector can also generate an interrupt by shorting the pin to ground.
The driver can operate in several different modes. It can act as a simple low-speed and full-speed differential USB driver, as two independent single-ended drivers in the UART mode, or as an open-drain driver in the I
2
C mode.
This block contains one differential receiver for the USB operation mode and two single-ended receivers for USB signaling as well as UART and I
2
C receivers.
14/26
STOTG04E Block description
This block controls the behavior of whole chip. It communicates with the external environment via the I
2
C serial bus. The control logic block consists of I
2
C slave interface, configuration and status registers, and some glue logic.
6.7 Modes operation
The STOTG04 can operate in two different power modes and in three operating modes. They can be controlled by logic signals and control registers.
When there is no need for the USB function, the STOTG04 reduces power consumption by implementing the Power-down mode. The power modes can be controlled by the Suspend Bit of Control Register 1 or/ and the SUSPEND pin (see Table 8).
Table 8.
Power modes
SUSPEND BIT
0
X
1
SUSPEND PIN
X
0
1
Power Mode normal operation power-down
Although in power down mode all analog blocks should be switched off, some of them could be turned on by bits in the control registers having higher priority than suspend bit. In order to obtain minimum power consumption in power down mode the device must be configured has shown in Table 9. The digital part is fully static so that it almost does not consume power. All of the interrupts (except BDIS_ACON) are fully operational in Power-down mode, as is the I
2
C interface.
Table 9.
Power down mode setup
SUSPEND BIT
1
X = Don’t care
- = Reserved
Bit order: 0...7
SUSPEND PIN
1
Control register 1 Control register 2
X1X0XX000XX00X0
Control register 3
-XXXX0XX
The STOTG04 transceiver has two basic USB operational modes. These modes define how the digital IO pins of the transceiver will be used. Independently of USB operating mode, some signals always have the same function (see Table 10).
Table 10.
Digital interface signals
Signal
RCV
VP
VM
OE_TP_INT/
Function
Differential receiver output
D+ single-ended receiver output
D- single-ended receiver output
Output enable signal of the differential driver
The RCV signal is active in the VP_VM mode only. Its output driver is controlled by the OE_TP_INT/ signal. Operating modes are described below. The meanings of the DAT_VP and SE0_VM signals depend on the mode of operation. Both of these signals can be bidirectional or unidirectional. The
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Block description STOTG04E direction is controlled by bidi_en Bit of Control Register 3 (described later). When these signals are bidirectional, the direction is controlled by the OE_TP_INT/ signal (see Tables 11 and 12).
The actual mode of operation is controlled by the dat_se0 Bit of Control Register 1 (see Tables 11 and 12)
Table 11.
DAT_SE0 (dat_se0 = 1) bidi_en
1
0
OE/*
0
1
X
DAT_VP
Differential driver input
Differential receiver output
Differential driver input
SE0_VM
SE0 driver input
SE0 detector output
SE0 driver input
Table 12.
VP_VM (dat_se0 = 0) bidi_en OE/*
1
0
0
1
X
* State of the OE_TP_INT/ signal.
DAT_VP
D+ driver input
D+ receiver output
D+ driver input
SE0_VM
D- driver input
D- receiver output
D- driver input
In the USB mode of operation it is necessary to control the rise and fall times of the transmission driver.
These times are different for low-speed and full-speed USB settings. Selection of actual USB speed can be done using the bit speed of Control Register 1 or/and the SPEED pin (see table 13).
Table 13.
USB Speed selection speed bit
0
X
1
SPEED Pin
X
0
1
USB Mode low-speed full-speed and C modes
The actual mode of operation is selectable by the transp_en and uart_en Bits of Control Register 1 (see table 14).
Table 14.
Transceiver modes transp_en
1
1
0
0 uart_en
0
1
0
1
STOTG04 Mode
USB
UART
I
2
C
UART (1)
(1) In reality, it is not possible to set both these bits at the same time. In this case, only uart_en bit will remain set.
In the I
2
C mode the D+ and D- lines act respectively as I
2
C SDA and SCL signals when the OE_TP_INT/ signal is low. The transceiver automatically enables the pull-up resistor on the SDA line in this mode. The internal I
2
C slave interface of the transceiver does not react to commands from the master.
Communication addressed to the STOTG04 device is mirrored to the D+ pin and responses from this pin are mirrored back to the SDA pin. The D– pin mirrors the SCL clock.
In the UART mode it is possible to select driver direction on both the D+ and D– pins. The selection is done using the bdir[1] and bdir[0] Bits of Control Register 3 (see table 15).
16/26
STOTG04E
Table 15.
UART Drivers direction bdir[1]
1
1
0
0 bdir[0]
0
1
0
1
DAT_VP ↔ D+
→
→
←
←
Block description
SE0_VM ↔ D-
→
←
→
←
In this mode the transceiver has to release all of its drivers and pull-up/pull-down resistors on the D+, Dand ID pins, leaving them in a high impedance state. This allows these lines to be used for transmission of audio signals. The transceiver should not provide voltage on its V
BUS
output in this mode. Conditions described in Table 16 force the transceiver into the audio mode.
Table 16.
Audio mode setup transp_en bit
0 uart_en bit
0
OE_TP_INT/ signal
1
Control Register 2
00000000
6.8 Registers
The STOTG04 transceiver device is controlled using register settings (see Table 17). These registers can be set and read via the I
2
C bus.
Table 17.
Register set
Register Size (bits) Acc
(1)
Vendor ID
Product ID
Control 1
Control 2
Control 3
Interrupt Source
Interrupt Latch
Interrupt Mask False
Interrupt Mask True
16
16
8
8
8
8
8
8
8
(1) Access type can be: read (r), set (s), clear (c).
(2) The first address is to set, the second one to clear bits.
r r r/s/c r/s/c r/s/c r r/s/c r/s/c r/s/c
Addr
(2) Description
00h
02h
STMicroelectronics ID (0483h) - LSB first
ID of the STOTG04 (A0C4h) - LSB first
04h 05h First Control Register
06h 07h Second Control Register
12h 13h Third Control Register
08h Current state of signals generating interrupts
0Ah 0Bh Latched source that generated interrupt
0Ch 0Dh Enables interrupts on falling edge
0Eh 0Fh Enables interrupts on rising edge
When writing to the set address, any “1” will set the associated Bit to logic “1”. When writing to the clear address, any “1” will set the associated Bit to logic “0”. It is possible to read from any address, whether it is a set or clear address. See Tables 18, 19, 20, 21 for bit setting details.
17/26
Block description STOTG04E
Table 18.
Control register 1
Name
Speed
Suspend dat_se0 transp_en bdis_acon_en oe_int_en uart_en
Bit
0
1
2
3
4
5
6
7
R
(1)
1
1
0
0
0
0
0
Description
0 = low-speed mode
1 = full-speed mode
0 = normal operation
1 = power-down mode
0 = VP_VM mode
1 = DAT_SE0 mode
Enable transparent I
2
C mode
Enable A-device to connect if B-device disconnect detected
When set and suspend = 1, then OE_TP_INT/ becomes interrupt output
Enable UART mode (higher priority than transp_en bit)
Reserved
(1) State of the bit after reset.
Setting the bdis_acon_en bit enables automatic switching of the D+ pull-up resistor when the device receives an SE0 longer than half of the bit period. This function should not be used in low-speed operation.
Table 19.
Control register 2
Name dp_pull-up dm_pull-up dp_pull-down dm_pull-down id_gnd_drv vbus_drv vbus_dischrg vbus_chrg
Bit
2
3
0
1
4
5
6
7
R
1
1
0
0
0
0
0
0
Description
Connect D+ pull-up
Connect D- pull-up
Connect D+ pull-down
Connect D- pull-down
Connect ID pin to ground
Provide power to V
BUS
Discharge V
BUS
through a resistor to ground
Charge V
BUS
through a resistor
It is not possible to set vbus_drv, vbus_dischrg and vbus_chrg at the same time; the bit having higher priority will remain set while the others will be cleared. Vbus_drv has higher priority than vbus_dischrg which has higher priority than vbus_chrg.
Table 20.
Control register 3
Name rec_bias_en bidi_en bdir[0] bdir[1] audio_en psw_en
2V7_en
2
3
4
5
Bit
0
1
6
7
1
0
1
0
R
0
0
0
0
Description
Reserved
Enables transmitter bias even during USB receive
When set, then DAT_VP and SE0_VM pins become bidirectional otherwise they are inputs only
Direction of the drivers between DAT_VP ↔DP and
SE0_VM ↔DM in the UART mode
Enables car-kit interrupt detector
Enables external charge pump control on the ADR_PSW pin.
Disables internal charge pump.
Enables 2.7V voltage regulation instead of 3.3V
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STOTG04E Block description
Table 21.
Interrupt registers (*)
Name Bit R Description vbus_vld sess_vld dp_hi id_gnd dm_hi id_float bdis_acon cr_int
0
3
4
1
2
5
6
7
0 A-device V
BUS
valid comparator
0 Session valid comparator
0 D+ pin is asserted high during SRP
0 ID pin grounded
0 D- pin is asserted high
0 ID pin floating
0
0
Set when bdis_acon_en bit is set and transceiver asserts dp_pull-up after detecting B-device disconnect
Car-kit interrupt
(*) Bit order is the same for all four interrupt related registers. Meaning of each register is described in Table 17.
6.9 I
2
C Bus interface
All of the STOTG04 transceiver registers are accessible through the I
2
C bus (see Figure 12). The device contains a slave controller which provides communication with an external master. The I
2
C interface consists of three pins:
• SDA (Serial Data);
• SCL (Serial Clock);
• ADR_PSW (is the LSB of the device address).
The USB-OTG transceiver has following 7-bit I
2
C device address:
0 1 0 1 1 0 adr
The adr bit represents current state of the ADR_PSW device pin. It means that the address can be either
2Ch or 2Dh according to the ADR_PSW pin.
Any device that sends data to the bus is defined as the transmitter. Any device that reads the data is the receiver. The device that controls data transfers is the bus master, while the transmitter or receiver is the slave device. The master initiates data transfers and provides the serial clock. The STOTG04 is always the slave device.
Operation of the I
2
C bus is described by following figure 12.
19/26
Block description
Figure 12. Basic operation of the I
2
C Bus
STOTG04E
Start condition is identified by a falling edge of the SDA signal while the SCL is stable at high level. The start condition must precede any data transfer on the bus.
Stop condition is identified by a rising edge of the SDA signal while the SCL is stable at high level. The stop condition terminates any communication between device and master.
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter releases the SDA line after sending eight data bits. During the ninth clock period the receiver pulls the SDA line low to acknowledge the receipt of the eight data bits. If the receiver is a slave device and it does not generate acknowledge bit then the bus master can generate the stop condition in order to abort the transfer.
Below is described format of I
2
C commands. All tables use common format and symbols. Every data word consists of eight bits with most significant bit first and least significant bit last.
Symbols used in the tables are:
• S – start condition
• P – stop condition
• A – acknowledge bit
• N – negative acknowledge
WRITE Command to the transceiver device is described by following table. It is possible to write into several consecutive registers during one write command.
S Device address 0 A Reg. address K A
S
Data (K)
READ command consists of dummy write to set proper address of a register followed by real read sequence.
S Device address 0 A Reg. address K A P
Data (K+1)
A
Device address
A
Data (K+1)
Data (K+2)
1
A
A
A
..
...
Data (K+N)
Data (K)
Data (K+N)
A
N
P
A
P
20/26
STOTG04E Block description
6.12 External charge pump switch
The ADR_PSW pin has two functions. State of this pin is always latched into a register on the rising edge of the RESET/ signal. The latched value is used as a least significant bit of the I
2
C address. After the address is latched, this pin can be set as an output by setting the PSW_EN bit of the Control Register 3.
Output value of the pin can be controlled by the VBUS_DRV bit of the Control Register 2. The output is active low when the pin is high during reset; otherwise the output is active high.
When the PSW_EN bit is set the internal charge pump is switched off.
Example connection of an external charge pump is shown in following figure. When the charge pump control signal would be active high, the ADR_PSW pin should be pulled down instead of high.
Figure 13. External charge pump application
21/26
Package mechanical data STOTG04E
In order to meet environmental requirements, ST offers these devices in ECOPACK
®
packages.
These packages have a Lead-free second level interconnect. The category of second Level
Interconnect is marked on the package and on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
22/26
DIM.
D
D2
E
E2 e
L
A
A1 b
STOTG04E Package mechanical data
0.00
0.18
3.9
1.95
3.9
1.95
MIN.
0.40
QFN24 (4x4) MECHANICAL DATA mm.
TYP MIN.
4.1
2.25
4.1
2.25
MAX.
1.00
0.05
0.30
0.0
7.1
153.5
76.8
153.5
76.8
mils
TYP.
0.50
19.7
0.60
15.7
23.6
161.4
88.6
161.4
88.6
MAX.
39.4
2.0
11.8
23/26
Package mechanical data
Tape & Reel QFNxx/DFNxx (4x4) MECHANICAL DATA
STOTG04E
MIN.
mm.
TYP MIN.
inch
TYP.
DIM.
N
T
Ao
A
C
D
Bo
Ko
Po
P
12.8
20.2
99
4.35
4.35
1.1
4
8
MAX.
330
13.2
101
14.4
0.504
0.795
3.898
0.171
0.171
0.043
0.157
0.315
MAX.
12.992
0.519
3.976
0.567
24/26
STOTG04E Revision history
Table 22.
Revision history
Date Revision
13-Jan-2006
01-Feb-2006
17-Oct-2006
1
2
3
Changes
First Release.
Mistake on Table 1.
Added details in paragraph 6.7.1, comments to table 19 and description in paragraph 6.12.
25/26
STOTG04E
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