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Polarity
Positive or negative pulse widths
Frequency range
1 Hz to 100 kHz
Resolution
2
µs
2.9.5 Totalizer
• Active edge polarity: Positive or negative transition
• Maximum count: 10^9
•
Allowed rate: 1 to 30,000 events per second
•
Uses Threshold DAC
Width range
2
µs to 1 s
Typical
Uncertainty
0.01 +/- 4
µs
2.10 Trigger Functions
2.10.1 External Hardware Trigger (at DIN-7 connector)
Trigger Input voltage level range
Ttrigger High current drive
Timing Characteristics
Trigger Activation
Internal Reading Buffer
Isolation of trigger input
High: +3V to +15V, Low: -15V to +0.8V
Min. 1mA, Max 10mA (TTL or CMOS logic level)
Trigger occurs within 2/Reading rate
Positive or Negative edge depending on trigger command.
Up to 1,000 readings/sec into 64 locations reading buffer
±50 V from analog DMM inputs, and from computer chassis earth ground.
2.10.2 PXI Bus Hardware Trigger Inputs (at PXI J2)
Trigger Input
Trigger Pulse Width
Internal Reading Buffer
Selectable lines
Isolation from DMM inputs
TTL or CMOS positive pulse
Minimum 250
µS up to 1,000 readings/sec into 64 readings buffer
PXI_TRIG1,2,3,4,5,6,7 and PXI_STAR
±330 V from any of the DMM 4 main inputs terminals
2.10.3 PXI Bus Hardware Trigger Output (to PXI J2)
Trigger Output
Trigger Pulse Width
Activity
Selectable lines
Isolation from DMM inputs
TTL or CMOS negative pulse. Positive edge = ready
Approximately 140
µS
A single pulse is issued for each A/D conversion (at 10 or higher measurement rate)
PXI_TRIG1,2,3,4,5,6 and PXI_STAR
±330 V from any of the DMM 4 main inputs terminals
2.10.4 Analog Threshold Trigger
• Captures up to 64 readings
•
Reading rate: 10 rps or higher
15 Signametrics
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