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Receiver by specifying inverted running disparity for the second and fourth bytes.
Transmit FIFO
Proper operation of the circuit is only possible if the FPGA clock (TXUSRCLK) is frequency-locked to the reference clock (REFCLK). Phase variations up to one clock cycle are allowable. The FIFO has a depth of four. Overflow or underflow conditions are detected and signaled at the interface.
Serializer
The multi-gigabit transceiver multiplies the reference frequency provided on the reference clock input (REFCLK) by 20. Data is converted from parallel to serial format and transmitted on the TXP and TXN differential outputs.
The electrical polarity of TXP and TXN can be interchanged through the TXPOLARITY port. This option can either be programmed or controlled by an input at the FPGA core TX interface. This facilitates recovery from situations where printed circuit board traces have been reversed.
Transmit Termination
On-chip termination is provided at the transmitter, eliminating the need for external termination. Programmable options exist for 50 Ω (default) and 75 Ω termination.
Pre-emphasis Circuit and Swing Control
Four selectable levels of pre-emphasis, including default pre-emphasis, are available.
Optimizing this setting allows the transceiver to drive up to 20 inches of FR4 at the maximum baud rate.
The programmable output swing control can adjust the differential output level between
800 mV and 1600 mV (differential peak-to-peak) in four increments of 200 mV.
Receiver
Deserializer
The RocketIO transceiver core accepts serial differential data on its RXP and RXN inputs.
The clock/data recovery circuit extracts clock phase and frequency from the incoming data stream and re-times incoming data to this clock. The recovered clock is presented on output RXRECCLK at 1/20 of the received serial data rate.
The receiver is capable of handling either transition-rich 8B/10B streams or scrambled streams, and can withstand a string of up to 75 non-transitioning bits without an error.
Word alignment is dependent on the state of comma detect bits. If comma detect is enabled, the transceiver recognizes up to two 10-bit preprogrammed characters. Upon detection of the character or characters, the comma detect output is driven High and the data is synchronously aligned. If a comma is detected and the data is aligned, no further alignment alteration takes place. If a comma is received and realignment is necessary, the data is realigned and an indication is given at the RX FPGA interface. The realignment indicator is a distinct output. The transceiver continuously monitors the data for the presence of the 10-bit character(s). Upon each occurrence of the 10-bit character, the data is checked for word alignment. If comma detect is disabled, the data is not aligned to any particular pattern. The programmable option allows a user to align data on comma+, comma–, both, or a unique user-defined and programmed sequence.
The electrical polarity of RXP and RXN can be interchanged through the RXPOLARITY port. This can be useful in the event that printed circuit board traces have been reversed.
R
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide www.xilinx.com
1-800-255-7778
19
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Table of contents
- 18 FPGA Transmit Interface
- 18 8B/10B Encoder
- 18 Disparity Control
- 19 Transmit FIFO
- 19 Serializer
- 19 Deserializer
- 20 Receiver Termination
- 20 8B/10B Decoder
- 21 Receiver Buffer
- 21 Clock Correction
- 22 Channel Bonding
- 23 Transmitter Buffer
- 38 Clock Signals
- 39 Clock Ratio
- 39 Digital Clock Manager (DCM) Examples
- 22 UG024 (v1.5) October
- 50 BREFCLK
- 52 Half-Rate Clocking Scheme
- 53 Multiplexed Clocking Scheme
- 53 Data Path Latency
- 54 Clock Dependency
- 56 Clock Correction Count
- 57 RX_LOSS_OF_SYNC_FSM
- 57 8B/10B Operation
- 59 Vitesse Disparity Example
- 69 8B/10B Serial Output Format
- 70 CRC Generation
- 71 CRC Latency
- 71 CRC Limitations
- 71 CRC Modes
- 75 Receive Data Path 32-bit Alignment
- 76 32-bit Alignment Design
- 87 Total Jitter (DJ + RJ)
- 89 Power Conditioning
- 71 UG024 (v1.5) October
- 91 High-Speed Serial Trace Design
- 94 Reference Clock
- 95 Powering the RocketIO Transceivers
- 95 The POWERDOWN Port
- 97 SmartModels
- 97 HSPICE
- 97 Synthesis
- 98 UCF Example
- 98 Implementing Clock Schemes
- 102 LOOPBACK
- 105 Setup/Hold Times of Inputs Relative to Clock
- 105 Clock to Output Delays
- 105 Clock Pulse Width
- 109 GT_AURORA
- 112 GT_CUSTOM
- 113 GT_ETHERNET
- 115 GT_FIBRE_CHAN
- 118 GT_INFINIBAND
- 121 GT_XAUI
- 112 UG024 (v1.5) October