Receive Data Path 32-bit Alignment. Xilinx RocketIO

Other Important Design Notes

Other Important Design Notes

Receive Data Path 32-bit Alignment

The RocketIO transceiver uses the attribute ALIGN_COMMA_MSB to align protocol delimiters with the use of comma characters (special K characters K28.5, K28.1, and K28.7 for most protocols). Setting the ALIGN_COMMA_MSB to TRUE/FALSE determines where the comma characters appear on the RXDATA bus. A setting of

ALIGN_COMMA_MSB = FALSE allows the comma to appear in any byte lane of the

RXDATA in the 2- and 4-byte primitives. When ALIGN_COMMA_MSB is set to TRUE, the comma appears in RXDATA[15:8] for the 2-byte primitives, and in either RXDATA[15:8] or

RXDATA[31:24] for the 4-byte primitives.

In the case of a 4-byte primitive, the transceiver sets comma alignment with respect to its

2-byte internal data path, but it does not constrain the comma to appear only in

RXDATA[31:24]. Logic must be designed in the FPGA fabric to handle comma alignment for the 32-bit primitives when implementing certain protocols.

One such protocol is Fibre Channel. Delimiters such as IDLES, SOF, and EOF are four bytes long, and are assumed by the protocol logic to be aligned on a 32-bit boundary. The Fibre

Channel IDLE delimiter is four bytes long and is composed of characters K28.5, D21.4,

D21.5, and D21.5. The comma, K28.5, is transmitted in TXDATA[31:24], which the protocol logic expects to be received in RXDATA[31:24].

Using

Table 3-13, page 61

, and Table 3-14, page 69

, the IDLE delimiter can be translated into a hexadecimal value 0xBC95B5B5 that represents the 32-bit RXDATA word. On the

32-bit RXDATA interface, the received word is either 32-bit aligned or misaligned, as

shown in Table 3-19 . In the table, "

pp " indicates a byte from a previous word of data.

Table 3-19: 32-bit RXDATA, Aligned versus Misaligned

RXDATA

[31:24]

RXDATA

[23:16]

RXDATA

[15:8]

32-bit aligned

CHARISCOMMA

32-bit misaligned

CHARISCOMMA

BC

1 pp

0

95

0 pp

0

B5

0

BC

1

RXDATA

[7:0]

B5

0

95

0

R

When RXDATA is 32-bit aligned, the logic should pass RXDATA though to the protocol logic without modification. A properly aligned data flow is shown in

Figure 3-19

.

TXDATA BC95B5B5 FDB53737 45674893 nnnnnnnn nnnnnnnn

RXDATA BC95B5B5 FDB53737 45674893 nnnnnnnn nnnnnnnn

ALIGNED_DATA pppppppp BC95B5B5 FDB53737 45674893 nnnnnnnn ug024_33_091602

Figure 3-19: RXDATA Aligned Correctly

UG024 (v1.5) October 16, 2002

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