RM0436 Extended interrupt and event controller (EXTI)
31
IM31 rw
15
IM15 rw
Bits 31:0 IM[31:0]: CPU wakeup with interrupt mask on event input x (x = 31:0) (1)(2) .
When TZENx is disabled, IMx can be accessed with non-secure and secure access.
When TZENx is enabled, IMx can only be accessed with secure access. Non-secure write to
IMx is discarded, non-secure read returns 0.
0: wakeup with interrupt request from Line x is masked
1: wakeup with interrupt request from Line x is unmasked
1. The reset value for configurable event inputs is set to ‘0’ in order to disable the interrupt by default.
2. The reset value for direct event inputs is set to ‘1’ in order to enable the interrupt by default.
24.6.24 EXTI CPU2 wakeup with interrupt mask register (EXTI_C2IMR1)
Address offset: 0x0C0
Reset value: 0xFFFE 0000
Contains register bits for configurable events and direct events.
30
IM30 rw
14
IM14 rw
29
IM29 rw
13
IM13 rw
28
IM28 rw
12
IM12 rw
27
IM27 rw
11
IM11 rw
26
IM26 rw
10
IM10 rw
25
IM25 rw
9
IM9 rw
24
IM24 rw
8
IM8 rw
23
IM23 rw
7
IM7 rw
22
IM22 rw
6
IM6 rw
21
IM21 rw
5
IM5 rw
20
IM20 rw
4
IM4 rw
19
IM19 rw
3
IM3 rw
18
IM18 rw
2
IM2 rw
17
IM17 rw
1
IM1 rw
16
IM16 rw
0
IM0 rw
Bits 31:0 IM[31:0]: CPU2 wakeup with interrupt mask on event input x (x = 31 to 0)
(1)(2)
.
When TZENx is disabled, IMx can be accessed with non-secure and secure access.
When TZENx is enabled, IMx can only be accessed with secure access. Non-secure write to
IMx is discarded, non-secure read returns 0.
0: wakeup with interrupt request from Line x is masked
1: wakeup with interrupt request from Line x is unmasked
1. The reset value for configurable event inputs is set to ‘0’ in order to disable the interrupt by default.
2. The reset value for direct event inputs is set to ‘1’ in order to enable the interrupt by default.
24.6.25 EXTI CPU2 wakeup with event mask register (EXTI_C2EMR1)
Address offset: 0x0C4
Reset value: 0x0000 0000
31
Res.
30
Res.
29
Res.
28
Res.
27
Res.
26
Res.
25
Res.
24
Res.
23
Res.
22
Res.
21
Res.
16
Res.
15 14 13 12 11 10
EM15 EM14 EM13 EM12 EM11 EM10 rw rw rw rw rw rw
9
EM9 rw
8
EM8 rw
7
EM7 rw
6
EM6 rw
5
EM5 rw
20
Res.
4
EM4 rw
19 18 17
EM19 EM18 EM17 rw rw rw
3
EM3 rw
2
EM2 rw
1
EM1 rw
0
EM0 rw
Bits 31:20 Reserved, must be kept at reset value.
RM0436 Rev 5 1349/4040
1360
