TSC I/O channel control register (TSC_IOCCR). STMicroelectronics STM32L552RC, STM32L562RE, STM32L552QC, STM32L552RE, STM32L562QE, STM32L552QE, STM32L552VE, STM32L552xx and STM32L562xx advanced Arm®-based 32-bit MCUs, STM32L552ZE, STM32L552VC

ST STM32L552xx and STM32L562xx advanced Arm®-based 32-bit MCUs are designed to provide excellent performance and flexibility for embedded applications requiring high speed, low power consumption, and advanced security features. These MCUs are ideal for a wide range of applications, including industrial automation, healthcare, consumer electronics, and IoT devices.

The STM32L552xx and STM32L562xx MCUs are based on the Arm® Cortex®-M33 core, which offers high performance and energy efficiency. These MCUs also feature a rich set of peripherals, including high-speed interfaces, timers, and analog peripherals. Additionally, these MCUs feature advanced security features, such as TrustZone® technology, to protect sensitive data and applications from unauthorized access.

PDF

Document

Touch sensing controller (TSC) RM0438

27.6.8 TSC I/O channel control register (TSC_IOCCR)

Address offset: 0x28

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1 rw

15 rw

14 rw

13 rw

12 rw

11 rw

10 rw

9 rw

8 rw

7 rw

6 rw

5 rw

4 rw

3 rw

2 rw

1 rw

G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 Gx_IOy : Gx_IOy channel mode

These bits are set and cleared by software to configure the Gx_IOy as a channel I/O.

0: Gx_IOy unused

1: Gx_IOy used as channel

Note: These bits must not be modified when an acquisition is ongoing.

During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller.

27.6.9 TSC I/O group control status register (TSC_IOGCSR)

Address offset: 0x30

Reset value: 0x0000 0000

Res.

G8S r

G8E rw

G7S r

G7E rw

G6S r

G6E rw

G5S r

G5E rw

G4S r

G4E rw

G3S r

G3E rw

G2S r

G2E rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 GxS : Analog I/O group x status

These bits are set by hardware when the acquisition on the corresponding enabled analog

I/O group x is complete. They are cleared by hardware when a new acquisition is started.

0: Acquisition on analog I/O group x is ongoing or not started

1: Acquisition on analog I/O group x is complete

Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set.

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:0 GxE : Analog I/O group x enable

These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x.

0: Acquisition on analog I/O group x disabled

1: Acquisition on analog I/O group x enabled

G1S r

G1E rw

936/2194 RM0438 Rev 7

Key features

Based on the Arm® Cortex®-M33 core for high performance and energy efficiency
Feature a rich set of peripherals, including high-speed interfaces, timers, and analog peripherals
Advanced security features, such as TrustZone® technology, to protect sensitive data and applications from unauthorized access
Suitable for a wide range of applications, including industrial automation, healthcare, consumer electronics, and IoT devices

Frequently asked questions

The Arm® Cortex®-M33 core is a high-performance, energy-efficient processor core designed for embedded applications.

TrustZone® technology provides advanced security features to protect sensitive data and applications from unauthorized access.

The STM32L552xx and STM32L562xx MCUs are suitable for a wide range of applications, including industrial automation, healthcare, consumer electronics, and IoT devices.