RM0090
2 Memory and bus architecture
Memory and bus architecture
In STM32F405xx/07xx and STM32F415xx/17xx, the main system consists of 32-bit multilayer AHB bus matrix that interconnects:
The main system consists of 32-bit multilayer AHB bus matrix that interconnects:
• Eight masters:
– Cortex
®
-M4 with FPU core I-bus, D-bus and S-bus
– DMA1 memory bus
– DMA2 memory bus
– DMA2 peripheral bus
– Ethernet DMA bus
– USB OTG HS DMA bus
• Seven slaves:
– Internal Flash memory ICode bus
– Internal Flash memory DCode bus
– Main internal SRAM1 (112 KB)
– Auxiliary internal SRAM2 (16 KB)
– AHB1 peripherals including AHB to APB bridges and APB peripherals
– AHB2 peripherals
– FSMC
The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even when several high-speed peripherals work simultaneously. The 64-
Kbyte CCM (core coupled memory) data RAM is not part of the bus matrix and can be
accessed only through the CPU. This architecture is shown in Figure 1
.
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Memory and bus architecture RM0090
Figure 1. System architecture for STM32F405xx/07xx and STM32F415xx/17xx devices
64-Kbyte
CCM data RAM
ARM
Cortex-M4
GP
DMA1
GP
DMA2
MAC
Ethernet
USB OTG
HS
Bus matrix-S
ICODE
DCODE
Flash memory
SRAM1
112 Kbyte
SRAM2
16 Kbyte
AHB1 peripherals
AHB2 peripherals
FSMC
Static MemCtl
APB1
APB2 ai18490e
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RM0090 Rev 19
RM0090 Memory and bus architecture
In the STM32F42xx and STM32F43xx devices, the main system consists of 32-bit multilayer
AHB bus matrix that interconnects:
• Ten masters:
– Cortex ® -M4 with FPU core I-bus, D-bus and S-bus
– DMA1 memory bus
– DMA2 memory bus
– DMA2 peripheral bus
– Ethernet DMA bus
– USB OTG HS DMA bus
– LCD Controller DMA-bus
– DMA2D (Chrom-Art Accelerator™) memory bus
• Eight slaves:
– Internal Flash memory ICode bus
– Internal Flash memory DCode bus
– Main internal SRAM1 (112 KB)
– Auxiliary internal SRAM2 (16 KB)
– Auxiliary internal SRAM3 (64 KB)
– AHB1peripherals including AHB to APB bridges and APB peripherals
– AHB2 peripherals
– FMC
The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even when several high-speed peripherals work simultaneously. The 64-
Kbyte CCM (core coupled memory) data RAM is not part of the bus matrix and can be
accessed only through the CPU. This architecture is shown in Figure 2
.
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