The STM32 Cortex-M0 instruction set PM0215
Change processor state.
Syntax
CPSID i
CPSIE i
Operation
CPS changes the PRIMASK special register values. CPSID causes interrupts to be disabled by setting PRIMASK. CPSIE cause interrupts to be enabled by clearing PRIMASK. See
Exception mask registers on page 15
for more information about these registers.
Restrictions
None
Condition flags
This instruction does not change the condition flags.
Examples
CPSID i ; Disable all interrupts except NMI (set PRIMASK)
CPSIE i ; Enable interrupts (clear PRIMASK)
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3.7.3 DMB
Data memory barrier.
Syntax
DMB
Operation
DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order, before the DMB instruction are completed before any explicit memory accesses that appear, in program order, after the DMB instruction. DMB does not affect the ordering or execution of instructions that do not access memory.
Restrictions
None
Condition flags
This instruction does not change the flags.
Examples
DMB ; Data Memory Barrier
3.7.4 DSB
Data synchronization barrier.
Syntax
DSB
Operation
DSB acts as a special data synchronization memory barrier. Instructions that come after the
DSB, in program order, do not execute until the DSB instruction completes. The DSB instruction completes when all explicit memory accesses before it complete.
Restrictions
None
Condition flags
This instruction does not change the flags.
Examples
DSB ; Data Synchronisation Barrier
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3.7.5 ISB
Instruction synchronization barrier.
Syntax
ISB
Operation
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the ISB are fetched from cache or memory again, after the ISB instruction has been completed.
Restrictions
None
Condition flags
This instruction does not change the flags.
Examples
ISB ; Instruction Synchronisation Barrier
3.7.6 MRS
Move the contents of a special register to a general-purpose register.
Syntax
MRS Rd , spec_reg where:
● ‘Rd’ is the general-purpose destination register.
● ‘spec_reg’ is one of the special-purpose registers: APSR, IPSR, EPSR, IEPSR,
IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, or CONTROL.
Operation
MRS stores the contents of a special-purpose register to a general-purpose register. MRS can be combined with the MSR instruction to produce read-modify-write sequences, which are suitable for modifying a specific flag in the PSR. See
MSR on page 65
.
Restrictions
Rd must not be SP or PC.
Condition flags
This instruction does not change the flags.
Examples
MRS R0, PRIMASK ; Read PRIMASK value and write it to R0
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3.7.7 MSR
Move the contents of a general-purpose register into the specified special register.
Syntax
MSR spec_reg, Rn where:
●
●
‘Rn’ is the general-purpose source register.
‘spec_reg’ is the special-purpose destination register: APSR, IPSR, EPSR, IEPSR,
IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, or CONTROL.
Operation
MSR updates one of the special registers with the value from the register specified by Rn .
See
MRS on page 64
.
Restrictions
Rn must not be SP and must not be PC.
Condition flags
This instruction updates the flags explicitly based on the value in Rn .
Examples
MSR CONTROL, R1 ; Read R1 value and write it to the CONTROL register
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3.7.8 NOP
No operation.
Syntax
NOP
Operation
NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might remove it from the pipeline before it reaches the execution stage.
Use NOP for padding, for example to place the following instruction on a 64-bit boundary.
Restrictions
None
Condition flags
This instruction does not change the flags.
Examples
NOP ; No operation
3.7.9 SEV
Send event.
Syntax
SEV
Operation
SEV is a hint instruction that causes an event to be signaled to all processors within a multiprocessor system. It also sets the local event register to 1, see
Power management on page 28
and WFE on page 67 .
Restrictions
None
Condition flags
This instruction does not change the flags.
Examples
SEV ; Send Event
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3.7.10 SVC
Supervisor call.
Syntax
SVC # imm where: ‘imm’ is an integer in the range 0-255.
Operation
The SVC instruction causes the SVC exception. imm is ignored by the processor. It can be retrieved by the exception handler to determine what service is being requested.
Restrictions : None
Condition flags
This instruction does not change the flags.
Examples
SVC 0x32 ; Supervisor Call (SVC handler can extract the immediate value
; by locating it via the stacked PC)
3.7.11 WFE
Wait for event. WFE is a hint instruction.
Syntax
WFE
Operation
If the event register is 0, WFE suspends execution until one of the following events occurs:
●
●
●
●
An exception, unless masked by exception mask registers or the current priority level
An exception enters Pending state, if SEVONPEND in system control register is set
A Debug Entry request, if Debug is enabled
An event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction.
If the event register is 1, WFE clears it to 0 and returns immediately. For more information
see Power management on page 28
.
WFE is intended for power saving only. When writing software assume that WFE might behave as NOP.
Restrictions : None
Condition flags
This instruction does not change the flags.
Examples
WFE ; Wait for event
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3.7.12 WFI
Wait for Interrupt.
Syntax
WFI
Operation
WFI is a hint instruction that suspends execution until one of the following events occurs:
●
●
●
An exception
An interrupt becomes pending which would preempt if PRIMASK was clear
A Debug Entry request, regardless of whether Debug is enabled.
WFI is intended for power saving only. When writing software assume that WFI might behave as a NOP operation.
Restrictions
None
Condition flags
This instruction does not change the flags.
Examples
WFI ; Wait for interrupt
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