SPI interface. STMicroelectronics STM8AF6388

STM8AF6388 Electrical characteristics

10.3.9 SPI interface

Unless otherwise specified, the parameters given in

Table 39 are derived from tests

performed under ambient temperature, f

MASTER conditions. t

MASTER

= 1/f

MASTER

.

frequency, and V

DD supply voltage

Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Symbol Parameter

Table 39. SPI characteristics

Conditions Min Max Unit

1/t f

SCK c(SCK)

SPI clock frequency

Master mode

Slave mode

V

DD

< 4.5 V

V

DD

= 4.5 V to 5.5 V

0

0

0

10

6

8

(1)

(1)

MHz t r(SCK) t f(SCK) t su(NSS)

(3) t h(NSS)

(3)

t t w(SCKH)

(3)

w(SCKL)

(3)

t t

su(MI)

(3) su(SI)

(3)

SPI clock rise and fall time Capacitive load: C = 30 pF

NSS setup time

NSS hold time

SCK high and low time

Data input setup time

Slave mode

Slave mode

Master mode

Master mode t

SCK

/2 - 15 t

4 * t

SCK

-

MASTER

70

/2 + 15

5

25 t t

w(SCKH)

(3)

(3)

w(SCKL)

-

-

-

(2)

Slave mode 5 t t h(MI)

(3)

(3)

h(SI)

Data input hold time

Master mode

Slave mode t

a(SO)

(3)(4)

t dis(SO)

(3)(5)

Data output access time Slave mode

Data output disable time Slave mode t

v(SO)

(3)

Data output valid time

Data output valid time

Slave mode

(after enable edge)

V

DD

< 4.5 V

V

DD

= 4.5 V to 5.5 V

Master mode (after enable edge) t

v(MO)

(3)

t

h(SO)

(3)

t

h(MO)

(3)

Data output hold time

Slave mode (after enable edge)

Master mode (after enable edge)

7

10

-

25

-

-

-

31

12

3* t

MASTER

-

-

-

-

75

53

30

1. f

SCK

< f

MASTER

/2.

2. The pad has to be configured accordingly (fast mode).

3. Guaranteed by design or by characterization results, not tested in production.

4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.

ns

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Electrical characteristics

Figure 40. SPI timing diagram in slave mode and with CPHA = 0

STM8AF6388

1. Measurement points are at CMOS levels: 0.3 V

DD

and 0.7 V

DD

.

Figure 41. SPI timing diagram in slave mode and with CPHA = 1

NSS input t

SU(NSS)

CPHA=1

CPOL=0

CPHA=1

CPOL=1 t w(SCKH) t w(SCKL) t a(SO)

MISO

OUTPUT

MOSI

INPUT t su(SI) t v(SO)

MSB OUT t h(SI)

MSB IN t c(SCK) t h(SO)

BIT6 OUT

BIT 1 IN t h(NSS) t r(SCK) t f(SCK) t dis(SO)

LSB OUT

LSB IN

1. Measurement points are at CMOS levels: 0.3 V

DD

and 0.7 V

DD

.

ai14135b

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STM8AF6388

Figure 42. SPI timing diagram - master mode

Electrical characteristics

NSS input

High

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1 tc(SCK)

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INP UT

MOSI

OUTPUT tsu(MI) tw(SCKH) tw(SCKL)

MSB IN th(MI)

MSB OUT tv(MO)

1. Measurement points are at CMOS levels: 0.3 V

DD

and 0.7 V

DD

.

BIT6 IN

B I T1 OUT th(MO) tr(SCK) tf(SCK)

LSB IN

LSB OUT ai14136c

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