STMicroelectronics STM8AF6388 Datasheet

STM8AF6388

Automotive 8-bit MCU, with up to 128-Kbyte Flash memory, data

EEPROM, 10-bit ADC, timers, LIN, USART, SPI, I2C, 3 to 5.5 V

Datasheet

-

production data

Features

• AEC-Q10x qualified

• Core

– Max f

CPU

: 24 MHz

– Advanced STM8A core with Harvard architecture and 3-stage pipeline

– Average 1.6 cycles/instruction resulting in

10 MIPS at 16 MHz f standard benchmark

CPU

for industry

• Memories

– Program memory: 32 to 128 Kbyte Flash program; data retention 20 years at 55 °C

– Data memory: up to 2 Kbyte true data

EEPROM; endurance 300 kcycle

– RAM: 6 Kbyte

• Clock management

– Low-power crystal resonator oscillator with external clock input

– Internal, user-trimmable 16 MHz RC and low-power 128 kHz RC oscillators

– Clock security system with clock monitor

• Reset and supply management

– Wait/auto-wakeup/Halt low-power modes with user definable clock gating

– Low consumption power-on and powerdown reset

• Interrupt management

– Nested interrupt controller with 32 vectors

– Up to 37 external interrupts on 5 vectors

• Timers

– 2 general purpose 16-bit timers with up to 3

CAPCOM channels each (IC, OC, PWM)

– Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, deadtime insertion and flexible synchronization

– 8-bit AR basic timer with 8-bit prescaler

– Auto-wakeup timer

– Window and independent watchdog timers

• I/Os

– Up to 68 user pins (11 high sink I/Os)

LQFP80 14x14 mm LQFP64 10x10 mm LQFP48 7x7 mm

LQFP32 7x7 mm VFQFP32 5x5 mm

– Highly robust I/O design, immune against current injection

• Communication interfaces

– USART with clock output for synchronous operation - LIN master mode

– LINUART LIN 2.2 compliant, master/slave modes with automatic resynchronization

– SPI interface up to 10 Mbit/s or f

MASTER

– I 2 C interface up to 400 Kbit/s

/2

• Analog to digital converter (ADC)

– 10-bit resolution, 2 LSB TUE, 1 LSB linearity and up to 16 multiplexed channels

• Operating temperature up to 150 °C

• Qualification conforms to AEC-Q100 grade 0

October 2017

This is information on a product in full production.

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Contents

STM8AF6388

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1

STM8A central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1.1

5.1.2

5.1.3

Architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.2

Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 15

5.2.1

5.2.2

SWIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3

Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.4

Flash program and data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.4.1

5.4.2

5.4.3

5.4.4

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Write protection (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Protection of user boot code (UBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Read-out protection (ROP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.5

Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.5.1

5.5.2

5.5.3

5.5.4

5.5.5

5.5.6

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

16 MHz high-speed internal RC oscillator (HSI) . . . . . . . . . . . . . . . . . . 17

128 kHz low-speed internal RC oscillator (LSI) . . . . . . . . . . . . . . . . . . . 18

24 MHz high-speed external crystal oscillator (HSE) . . . . . . . . . . . . . . 18

External clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.6

Low-power operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.7

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.7.1

5.7.2

5.7.3

Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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5.7.4

5.7.5

Advanced control and general purpose timers . . . . . . . . . . . . . . . . . . . 20

Basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.8

Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.9

Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.9.1

5.9.2

5.9.3

5.9.4

Universal synchronous/asynchronous receiver transmitter (USART) . . 22

Universal asynchronous receiver/transmitter with LIN support

(LINUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Inter integrated circuit (I

2

C) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.10

Input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1

Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.2

Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.1

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.2

Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.1.1

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.1.2

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.1.3

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.1.4

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.1.5

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

10.2

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

10.3

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

10.3.1

VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

10.3.2

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

10.3.3

External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 68

10.3.4

Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 70

10.3.5

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

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10.3.6

I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.3.7

Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.3.8

TIM 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 80

10.3.9

SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

10.3.10 I

2 C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.3.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

10.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

11.1

LQFP80 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

11.2

LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

11.3

LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

11.4

LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

11.5

VFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

11.6

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11.6.1

Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11.6.2

Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 110

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

13.1

Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . .112

13.1.1

STice key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

13.2

Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

13.2.1

STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

13.2.2

C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

13.3

Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

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List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

STM8AF6369/8x/Ax product line-up without CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Peripheral clock gating bits (CLK_PCKENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Peripheral clock gating bits (CLK_PCKENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Advanced control and general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

TIM4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

ADC naming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Communication peripheral naming correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Legend/abbreviation for the pin description table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 9.

STM8AF6388 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 10.

Memory model 128K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 11.

I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 12.

General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 13.

CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 14.

Temporary memory unprotection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 15.

STM8A interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 16.

Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 17.

Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 18.

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 19.

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 20.

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 21.

Operating lifetime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 22.

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 23.

Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 24.

Total current consumption in Run, Wait and Slow mode. General conditions

for V

DD

apply, T

Table 25.

Total current consumption in Halt and Active-halt modes. General conditions for V

DD

applied. T

A

A

= -40 °C to 150 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

= -40 °C to 55 °C unless otherwise stated . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 26.

Oscillator current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 27.

Programming current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 28.

Typical peripheral current consumption V

DD

= 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 29.

HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 30.

HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 31.

HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 32.

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 33.

Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 34.

Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 35.

Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 36.

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 37.

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 38.

TIM 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 39.

SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 40.

I

2

C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 41.

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 42.

ADC accuracy for V

DDA

= 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 43.

EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 44.

EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 45.

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 46.

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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Table 47.

LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 48.

LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 49.

LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 50.

LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 51.

VFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 52.

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 53.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

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STM8AF6388

List of figures

List of figures

Figure 1.

STM8AF6388 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2.

Flash memory organization of STM8A products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 3.

LQFP 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 4.

LQFP 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 5.

LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 6.

STM8AF62xx LQFP/VFQFPN 32-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 7.

STM8AF52x6 VFQFPN32 32-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 8.

Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 9.

Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 10.

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 11.

fCPUmax versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 12.

External capacitor C

EXT

Figure 13.

Typ. I

DD(RUN)HSE

Figure 14.

Typ. I

Figure 15.

Typ. I

Figure 16.

Typ. I

Figure 17.

Typ. I

Figure 18.

Typ. I

DD(RUN)HSE

DD(RUN)HSI

DD(WFI)HSE

DD(WFI)HSE

DD(WFI)HSI

vs. V

DD

vs. f

vs. V

vs. V

vs. f

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

CPU

DD

DD

@ f

CPU

vs. V

DD

@f

CPU

@ V

@ V

DD

@ f

CPU

CPU

DD

@ f

CPU

= 16 MHz, peripherals = on . . . . . . . . . . . . . . . . . . . . . . 67

= 5.0 V, peripherals = on . . . . . . . . . . . . . . . . . . . . . . . 67

= 16 MHz, peripherals = off . . . . . . . . . . . . . . . . . . . . . . 67

= 16 MHz, peripherals = on . . . . . . . . . . . . . . . . . . . . . . 67

= 5.0 V, peripherals = on . . . . . . . . . . . . . . . . . . . . . . . . 67

= 16 MHz, peripherals = off . . . . . . . . . . . . . . . . . . . . . . 67

Figure 19.

HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 20.

HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 21.

Typical HSI frequency vs V

DD

Figure 22.

Typical LSI frequency vs V

DD

Figure 23.

Typical V

IL

and V

IH

vs V

DD

Figure 24.

Typical pull-up resistance R

PU

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

@ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 25.

Typical pull-up current I pu

vs V

DD

vs V

DD

@ four temperatures . . . . . . . . . . . . . . . . . . . . . . . 75

@ four temperatures

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . 76

= 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 26.

Typ. V

OL

Figure 27.

Typ. V

OL

Figure 28.

Typ. V

OL

Figure 29.

Typ. V

OL

@ V

DD

@ V

DD

@ V

DD

@ V

DD

= 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

= 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

= 5.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

= 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 30.

Typ. V

OL

Figure 31.

Typ. V

OL

Figure 32.

Typ. V

Figure 33.

Typ. V

Figure 34.

Typ. V

Figure 35.

Typ. V

DD

DD

DD

DD

@ V

DD

@ V

DD

- V

OH

- V

OH

- V

OH

- V

OH

= 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

@ V

@ V

@ V

DD

@ V

Figure 36.

Typical NRST V

IL

DD

= 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

DD

= 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

= 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

DD

= 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

and V

IH

vs V

DD

@ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 37.

Typical NRST pull-up resistance R

PU

Figure 38.

Typical NRST pull-up current I pu

vs V

vs V

DD

DD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 39.

Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 40.

SPI timing diagram in slave mode and with CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 41.

SPI timing diagram in slave mode and with CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 42.

SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 43.

Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 44.

ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 45.

LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 90

Figure 46.

LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 47.

LQFP80 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

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8

List of figures STM8AF6388

Figure 48.

LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 94

Figure 49.

LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 50.

LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 51.

LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 97

Figure 52.

LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 53.

LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 54.

LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 101

Figure 55.

LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 56.

LQFP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 57.

VFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch very thin profile fine pitch quad

flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 58.

VFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad

flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 59.

VFQFPN32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 60.

STM8AF6388 ordering information scheme 1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

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STM8AF6388

1 Introduction

Introduction

This datasheet refers to the STM8AF6388 products with 32 to 128 Kbytes of program memory.

In the order code, the letter ‘F’ refers to product versions with Flash and data EEPROM and

‘P’ to product versions with FASTROM. The identifiers ‘F’ and ‘P’ do not coexist in a given order code.

The datasheet contains the description of family features, pinout, electrical characteristics, mechanical data and ordering information.

• For complete information on the STM8A microcontroller memory, registers and peripherals, please refer to STM8S series and STM8AF series 8-bit microcontrollers reference manual (RM0016).

• For information on programming, erasing and protection of the internal Flash memory please refer to the STM8S and STM8A Flash programming manual (PM0051).

• For information on the debug and SWIM (single wire interface module) refer to the

STM8 SWIM communication protocol and debug module user manual (UM0470).

• For information on the STM8 core, please refer to the STM8 CPU programming manual

(PM0044).

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114

Description

2 Description

STM8AF6388

The STM8AF6388 automotive 8-bit microcontrollers described in this datasheet offer from

32 Kbytes to 128 Kbytes of non volatile memory and integrated true data EEPROM. They are referred to as high density STM8A devices in STM8S series and STM8AF series 8-bit microcontrollers reference manual (RM0016).

All devices of the STM8A product line provide the following benefits: reduced system cost, performance and robustness, short development cycles, and product longevity.

The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k write/erase cycles and a high system integration level with internal clock oscillators, wtachdog, and brown-out reset.

Device performance is ensured by 20 MIPS at 24 MHz CPU clock frequency and enhanced characteristics which include robust I/O, independent watchdogs (with a separate clock source), and a clock security system.

Short development cycles are guaranteed due to application scalability across a common family product architecture with compatible pinout, memory map, and modular peripherals.

Full documentation is offered with a wide choice of development tools.

Product longevity is ensured in the STM8A family thanks to their advanced core which is made in a state-of-the art technology for automotive applications with 3.3 V to 5.5 V operating supply.

All STM8A and ST7 microcontrollers are supported by the same tools including

STVD/STVP development environment, the STice emulator and a low-cost, third party incircuit debugging tool.

10/116 DocID031156 Rev 1

STM8AF6388 Product line-up

.

Table 1 presents the line-up of related products available upon request;

Order code

STM8AF/P63AA

STM8AF/P638A

STM8AF/P63A9

STM8AF/P6389

STM8AF/P6369

STM8AF/P63A8

STM8AF/P6388

LQFP80

(14x14)

LQFP64

(10x10)

LQFP48

(7x7)

STM8AF/P6386

STM8AF/P63A6

LQFP32

(7x7)

VFQFPN32

(5x5)

Table 1. STM8AF6369/8x/Ax product line-up without CAN

Package

High density

Flash program memory

(bytes)

RAM

(bytes)

Data

EEPROM

(bytes)

10-bit

A/D chan.

Timers

(IC/OC/PWM)

Serial interfaces

128 K

64 K

128 K

64 K

32 K

128 K

6 K

2 K

2 K

1 K

16

10

1x8-bit: TIM4

3x16-bit: TIM1,

TIM2, TIM3

(9/9/9)

LIN(UART),

SPI,

USART, I²C

64 K

128 K

2 K

7

1x8-bit: TIM4

3x16-bit: TIM1,

TIM2, TIM3

(8/8/8)

LIN(UART),

SPI, I²C

I/0 wakeup pins

68/37

52/36

38/35

25/23

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114

Block diagram STM8AF6388

Reset

Single wire debug interface

Master/slave automatic resynchronization

400 Kbit/s

10 Mbit/s

LIN master

SPI emul.

Up to 16 channels

Figure 1. STM8AF6388 block diagram

Reset block

POR

Reset

BOR

Clock controller

Detector

XTAL 1- 24 MHz

RC int. 16 MHz

RC int. 128 kHz

STM8A core

Debug/SWIM

USART

I2C

SPI

LINUART

10-bit ADC

Clock to peripherals and core

Window WDG

Independent WDG

Up to 128 Kbyte high-density program Flash

Up to 2 Kbyte data EEPROM

Up to 6 Kbyte RAM

Boot ROM

16-bit advanced control timer (TIM1)

16-bit general purpose timers (TIM2, TIM3)

8-bit AR timer

(TIM4)

AWU timer

Up to

9 CAPCOM channels

MS38338V1

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STM8AF6388

1. Legend:

ADC: Analog-to-digital converter

BOR: Brownout reset

I²C: Inter-integrated circuit multimaster interface

IWDG: Independent window watchdog

LINUART: Local interconnect network universal asynchronous receiver transmitter

POR: Power on reset

SPI: Serial peripheral interface

SWIM: Single wire interface module

USART: Universal synchronous asynchronous receiver transmitter

Window WDG: Window watchdog

Block diagram

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114

Product overview STM8AF6388

This section is intended to describe the family features that are actually implemented in the products covered by this datasheet.

For more detailed information on each feature please refer to STM8S series and STM8AF series 8-bit microcontrollers reference manual (RM0016).

5.1 STM8A central processing unit (CPU)

The 8-bit STM8A core is a modern CISC core and has been designed for code efficiency and performance. It contains 21 internal registers (six directly addressable in each execution context), 20 addressing modes including indexed indirect and relative addressing and 80 instructions.

5.1.1 Architecture and registers

• Harvard architecture

• 3-stage pipeline

• 32-bit wide program memory bus with single cycle fetching for most instructions

• X and Y 16-bit index registers, enabling indexed addressing modes with or without offset and read-modify-write type data manipulations

• 8-bit accumulator

• 24-bit program counter with 16-Mbyte linear memory space

• 16-bit stack pointer with access to a 64 Kbyte stack

• 8-bit condition code register with seven condition flags for the result of the last instruction.

5.1.2 Addressing

• 20 addressing modes

• Indexed indirect addressing mode for look-up tables located anywhere in the address space

• Stack pointer relative addressing mode for efficient implementation of local variables and parameter passing

• 80 instructions with 2-byte average instruction size

• Standard data movement and logic/arithmetic functions

• 8-bit by 8-bit multiplication

• 16-bit by 8-bit and 16-bit by 16-bit division

• Bit manipulation

• Data transfer between stack and accumulator (push/pop) with direct stack access

• Data transfer using the X and Y registers or direct memory-to-memory transfers

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5.2 Single wire interface module (SWIM) and debug module (DM)

5.2.1 SWIM

The single wire interface module, SWIM, together with an integrated debug module, permits non-intrusive, real-time in-circuit debugging and fast memory programming. The interface can be activated in all device operation modes and can be connected to a running device

(hot plugging).The maximum data transmission speed is 145 bytes/ms.

The non-intrusive debugging module features a performance close to a full-flavored emulator. Besides memory and peripheral operation, CPU operation can also be monitored in real-time by means of shadow registers.

• R/W of RAM and peripheral registers in real-time

• R/W for all resources when the application is stopped

• Breakpoints on all program-memory instructions (software breakpoints), except the interrupt vector table

• Two advanced breakpoints and 23 predefined breakpoint configurations

• Nested interrupts with three software priority levels

• 24 interrupt vectors with hardware priority

• Five vectors for external interrupts (up to 37 depending on the package)

• Trap and reset interrupts

5.4 Flash program and data EEPROM

• 32 Kbytes to 128 Kbytes of high density single voltage Flash program memory

• Up to 2 Kbytes true (not emulated) data EEPROM

• Read while write: writing in the data memory is possible while executing code in the

Flash program memory.

The whole Flash program memory and data EEPROM are factory programmed with 0x00.

5.4.1 Architecture

• The memory is organized in blocks of 128 bytes each

• Read granularity: 1 word = 4 bytes

• Write/erase granularity: 1 word (4 bytes) or 1 block (128 bytes) in parallel

• Writing, erasing, word and block management is handled automatically by the memory interface.

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Product overview

5.4.2 Write protection (WP)

STM8AF6388

Write protection in application mode is intended to avoid unintentional overwriting of the memory. The write protection can be removed temporarily by executing a specific sequence in the user software.

If the user chooses to update the Flash program memory using a specific boot code to perform in application programming (IAP), this boot code needs to be protected against unwanted modification.

In the STM8A a memory area of up to 128 Kbytes can be protected from overwriting at user option level. Other than the standard write protection, the UBC protection can exclusively be modified via the debug interface, the user software cannot modify the UBC protection status.

The UBC memory area contains the reset and interrupt vectors and its size can be adjusted in increments of 512 bytes by programming the UBC and NUBC option bytes

(see Section 9: Option bytes on page 54 ).

Figure 2. Flash memory organization of STM8A products

Data

EEPROM memory

Data memory area

Option bytes

UBC area

Remains write protected during IAP

Programmable area from 1 Kbyte

(first two pages) up to program memory end - maximum 128 Kbyte

Flash program memory

Flash program memory area

Write access possible for IAP

5.4.4

MS38339V1

Read-out protection (ROP)

The STM8A provides a read-out protection of the code and data memory which can be activated by an option byte setting (see the ROP option byte in section 10).

The read-out protection prevents reading and writing Flash program memory, data memory and option bytes via the debug module and SWIM interface. This protection is active in all device operation modes. Any attempt to remove the protection by overwriting the ROP option byte triggers a global erase of the program and data memory.

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The ROP circuit may provide a temporary access for debugging or failure analysis. The temporary read access is protected by a user defined, 8-byte keyword stored in the option byte area. This keyword must be entered via the SWIM interface to temporarily unlock the device.

If desired, the temporary unlock mechanism can be permanently disabled by the user through OPT6/NOPT6 option bytes.

5.5.1 Features

• Clock sources

– 16 MHz high-speed internal RC oscillator (HSI)

– 128 kHz low-speed internal RC (LSI)

– 1-24 MHz high-speed external crystal (HSE)

– Up to 24 MHz high-speed user-external clock (HSE user-ext)

• Reset : After reset the microcontroller restarts by default with an internal 2-MHz clock

(16 MHz/8). The clock source and speed can be changed by the application program as soon as the code execution starts.

• Safe clock switching : Clock sources can be changed safely on the fly in Run mode through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching.

• Clock management : To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

• Wakeup : In case the device wakes up from low-power modes, the internal RC oscillator (16 MHz/8) is used for quick startup. After a stabilization time, the device switches to the clock source that was selected before Halt mode was entered.

• Clock security system (CSS) : The CSS permits monitoring of external clock sources and automatic switching to the internal RC (16 MHz/8) in case of a clock failure.

• Configurable main clock output (CCO) : This feature permits to output a clock signal for use by the application.

5.5.2

The clock controller distributes the system clock coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness.

16 MHz high-speed internal RC oscillator (HSI)

• Default clock after reset 2 MHz (16 MHz/8)

• Fast wakeup time

User trimming

The register CLK_HSITRIMR with two trimming bits plus one additional bit for the sign permits frequency tuning by the application program. The adjustment range covers all possible frequency variations versus supply voltage and temperature. This trimming does not change the initial production setting.

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Product overview

5.5.3

5.5.4

128 kHz low-speed internal RC oscillator (LSI)

STM8AF6388

The frequency of this clock is 128 kHz and it is independent from the main clock. It drives the independent watchdog or the AWU wakeup timer.

In systems which do not need independent clock sources for the watchdog counters, the

128 kHz signal can be used as the system clock. This configuration has to be enabled by setting an option byte (OPT3/OPT3N, bit LSI_EN).

24 MHz high-speed external crystal oscillator (HSE)

The external high-speed crystal oscillator can be selected to deliver the main clock in normal Run mode. It operates with quartz crystals and ceramic resonators.

• Frequency range: 1 MHz to 24 MHz

• Crystal oscillation mode: preferred fundamental

• I/Os: standard I/O pins multiplexed with OSCIN, OSCOUT

5.5.6

An external clock signal can be applied to the OSCIN input pin of the crystal oscillator. The frequency range is 0 to 24 MHz.

Clock security system (CSS)

The clock security system protects against a system stall in case of an external crystal clock failure.

In case of a clock failure an interrupt is generated and the high-speed internal clock (HSI) is automatically selected with a frequency of 2 MHz (16 MHz/8).

Table 2. Peripheral clock gating bits (CLK_PCKENR1)

Control bit Peripheral

PCKEN17

PCKEN16

PCKEN15

PCKEN14

PCKEN13

PCKEN12

PCKEN11

PCKEN10

TIM1

TIM3

TIM2

TIM4

LINUART

USART

SPI

I

2

C

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5.6

Product overview

Table 3. Peripheral clock gating bits (CLK_PCKENR2)

Control bit Peripheral

PCKEN27

PCKEN26

PCKEN25

PCKEN24

PCKEN23

PCKEN22

PCKEN21

PCKEN20

-

Reserved

Reserved

Reserved

ADC

AWU

Reserved

Reserved

Low-power operating modes

For efficient power management, the application can be put in one of four different lowpower modes. Users can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources.

• Wait mode

In this mode, the CPU is stopped but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset.

• Active-halt mode with regulator on

In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in Activehalt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.

• Active-halt mode with regulator off

This mode is the same as Active-halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower.

• Halt mode

CPU and peripheral clocks are stopped, the main voltage regulator is powered off.

Wakeup is triggered by external event or reset.

In all modes the CPU and peripherals remain permanently powered on, the system clock is applied only to selected modules. The RAM content is preserved and the brown-out reset circuit remains activated.

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114

Product overview

5.7 Timers

STM8AF6388

The watchdog system is based on two independent timers providing maximum security to the applications. The watchdog timer activity is controlled by the application program or option bytes. Once the watchdog is activated, it cannot be disabled by the user program without going through reset.

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.

The window function can be used to trim the watchdog behavior to match the application timing perfectly. The application software must refresh the counter before time-out and during a limited time window. If the counter is refreshed outside this time window, a reset is issued.

Independent watchdog timer

The independent watchdog peripheral can be used to resolve malfunctions due to hardware or software failures.

It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure. If the hardware watchdog feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and generates a reset unless the key register is written by software before the counter reaches the end of count.

5.7.3 Beeper

This function generates a rectangular signal in the range of 1, 2 or 4 kHz which can be output on a pin. This is useful when audible sounds without interference need to be generated for use in the application.

5.7.4

This counter is used to cyclically wakeup the device in Active-halt mode. It can be clocked by the internal 128 kHz internal low-frequency RC oscillator or external clock.

LSI clock can be internally connected to TIM3 input capture channel 1 for calibration.

Advanced control and general purpose timers

STM8A devices described in this datasheet, contain up to three 16-bit advanced control and general purpose timers providing nine CAPCOM channels in total. A CAPCOM channel can be used either as input compare, output compare or PWM channel. These timers are named TIM1, TIM2 and TIM3.

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STM8AF6388 Product overview

Timer

TIM1

TIM2

TIM3

Counter width

Table 4. Advanced control and general purpose timers

Counter type

Prescaler factor

Channels

Inverted outputs

Repetition counter trigger unit

16-bit Up/down 1 to 65536

16-bit Up

2 n n = 0 to 15

16-bit Up

2 n n = 0 to 15

4

3

2

3

None

None

Yes

No

No

Yes

No

No

External trigger

Yes

Break input

Yes

No

No

No

No

TIM1 - advanced control timer

This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and bridge driver.

• 16-bit up, down and up/down AR (auto-reload) counter with 16-bit fractional prescaler.

• Four independent CAPCOM channels configurable as input capture, output compare,

PWM generation (edge and center aligned mode) and single pulse mode output

• Trigger module which allows the interaction of TIM1 with other on-chip peripherals. In the present implementation it is possible to trigger the ADC upon a timer event.

• External trigger to change the timer behavior depending on external signals

• Break input to force the timer outputs into a defined state

• Three complementary outputs with adjustable dead time

• Interrupt sources: 4 x input capture/output compare, 1 x overflow/update, 1 x break

TIM2, TIM3 - 16-bit general purpose timers

• 16-bit auto-reload up-counter

• 15-bit prescaler adjustable to fixed power of two ratios 1…32768

• Timers with three or two individually configurable CAPCOM channels

• Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update

Timer

TIM4

The typical usage of this timer (TIM4) is the generation of a clock tick.

Counter width

Counter type

8-bit Up

Table 5. TIM4

Prescaler factor

Channels

2 n n = 0 to 7

0

Inverted outputs

Repetition counter

None No trigger unit

No

External trigger

Break input

No No

• 8-bit auto-reload, adjustable prescaler ratio to any power of two from 1 to 128

• Clock source: master clock

• Interrupt source: 1 x overflow/update

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114

Product overview

5.8 Analog to digital converter (ADC)

STM8AF6388

The STM8A products described in this datasheet contain a 10-bit successive approximation

ADC with up to 16 multiplexed input channels, depending on the package.

The ADC name differs between the datasheet and the STM8A/S reference manual (see

Table 6 ).

Table 6. ADC naming

Peripheral name in datasheet

Peripheral name in reference manual

(RM0016)

ADC ADC2

ADC features

• 10-bit resolution

• Single and continuous conversion modes

• Programmable prescaler: f

MASTER

divided by 2 to 18

• Conversion trigger on timer events, and external events

• Interrupt generation at end of conversion

• Selectable alignment of 10-bit data in 2 x 8 bit result registers

• Shadow registers for data consistency

• ADC input range: V

SSA

≤ V

IN

V

DDA

• Schmitt-trigger on analog inputs can be disabled to reduce power consumption

The following sections give a brief overview of the communication peripheral. Some peripheral names differ between the datasheet and STM8S series and STM8AF series 8-bit microcontrollers reference manual (see

Table 7 ).

Table 7. Communication peripheral naming correspondence

Peripheral name in datasheet

Peripheral name in reference manual

(RM0016)

USART

LINUART

UART1

UART3

The devices covered by this datasheet contain one USART interface. The USART can operate in standard SCI mode (serial communication interface, asynchronous) or in SPI emulation mode. It is equipped with a 16 bit fractional prescaler. It features LIN master support.

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STM8AF6388 Product overview

Detailed feature list:

• Full duplex, asynchronous communications

• NRZ standard format (mark/space)

• High-precision baud rate generator system

– Common programmable transmit and receive baud rates up to f

MASTER

/16

• Programmable data word length (8 or 9 bits)

• Configurable stop bits: Support for 1 or 2 stop bits

• LIN master mode:

– LIN break and delimiter generation

– LIN break and delimiter detection with separate flag and interrupt source for readback checking.

• Transmitter clock output for synchronous communication

• Separate enable bits for transmitter and receiver

• Transfer detection flags:

– Receive buffer full

– Transmit buffer empty

– End of transmission flags

• Parity control:

– Transmits parity bit

– Checks parity of received data byte

• Four error detection flags:

– Overrun error

– Noise error

– Frame error

– Parity error

• Six interrupt sources with flags:

– Transmit data register empty

– Transmission complete

– Receive data register full

– Idle line received

– Parity error

– LIN break and delimiter detection

• Two interrupt vectors:

– Transmitter interrupt

– Receiver interrupt

• Reduced power consumption mode

• Wakeup from mute mode (by idle line detection or address mark detection)

• Two receiver wakeup modes:

– Address bit (MSB)

– Idle line

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114

Product overview STM8AF6388

(LINUART)

The devices covered by this datasheet contain one LINUART interface. The interface is available on all the supported packages. The LINUART is an asynchronous serial communication interface which supports extensive LIN functions tailored for LIN slave applications. In LIN mode it is compliant to the LIN standards rev 1.2 to rev 2.2.

Detailed feature list:

LIN mode

Master mode

• LIN break and delimiter generation

• LIN break and delimiter detection with separate flag and interrupt source for read back checking.

Slave mode

• Autonomous header handling – one single interrupt per valid header

• Mute mode to filter responses

• Identifier parity error checking

• LIN automatic resynchronization, allowing operation with internal RC oscillator (HSI) clock source

• Break detection at any time, even during a byte reception

• Header errors detection:

– Delimiter too short

– Synch field error

– Deviation error (if automatic resynchronization is enabled)

– Framing error in synch field or identifier field

– Header time-out

UART mode

• Full duplex, asynchronous communications - NRZ standard format (mark/space)

• High-precision baud rate generator

– A common programmable transmit and receive baud rates up to f

MASTER

/16

• Programmable data word length (8 or 9 bits) – 1 or 2 stop bits – parity control

• Separate enable bits for transmitter and receiver

• Error detection flags

• Reduced power consumption mode

• Multi-processor communication - enter mute mode if address match does not occur

• Wakeup from mute mode (by idle line detection or address mark detection)

• Two receiver wakeup modes:

– Address bit (MSB)

– Idle line

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STM8AF6388

5.9.3

5.9.4

Product overview

Serial peripheral interface (SPI)

The devices covered by this datasheet contain one SPI. The SPI is available on all the supported packages.

• Maximum speed: 10 Mbit/s or f

MASTER

/2 for master, 8 Mbit/s or f

MASTER

/2 for slave

• Full duplex synchronous transfers

• Simplex synchronous transfers on two lines with a possible bidirectional data line

• Master or slave operation - selectable by hardware or software

• CRC calculation

• 1 byte Tx and Rx buffer

• Slave mode/master mode management by hardware or software for both master and slave

• Programmable clock polarity and phase

• Programmable data order with MSB-first or LSB-first shifting

• Dedicated transmission and reception flags with interrupt capability

• SPI bus busy status flag

• Hardware CRC feature for reliable communication:

– CRC value can be transmitted as last byte in Tx mode

– CRC error checking for last received byte

Inter integrated circuit (I

2

C) interface

The devices covered by this datasheet contain one I 2 C interface. The interface is available on all the supported packages.

• I 2 C master features:

– Clock generation

– Start and stop generation

• I 2 C slave features:

– Programmable I 2 C address detection

– Stop bit detection

• Generation and detection of 7-bit/10-bit addressing and general call

• Supports different communication speeds:

– Standard speed (up to 100 kHz),

– Fast speed (up to 400 kHz)

• Status flags:

– Transmitter/receiver mode flag

– End-of-byte transmission flag

– I 2 C busy flag

• Error flags:

– Arbitration lost condition for master mode

– Acknowledgement failure after address/data transmission

– Detection of misplaced start or stop condition

– Overrun/underrun if clock stretching is disabled

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Product overview

• Interrupt:

– Successful address/data communication

– Error condition

– Wakeup from Halt

• Wakeup from Halt on address detection in slave mode

STM8AF6388

26/116 DocID031156 Rev 1

STM8AF6388 Product overview

The product features four I/O types:

• Standard I/O 2 MHz

• Fast I/O up to 10 MHz

• High sink 8 mA, 2 MHz

• True open drain (I

2

C interface)

To decrease EMI (electromagnetic interference), high sink I/Os have a limited maximum slew rate. The rise and fall times are similar to those of standard I/Os.

The analog inputs are equipped with a low leakage analog switch. Additionally, the schmitttrigger input stage on the analog I/Os can be disabled in order to reduce the device standby consumption.

STM8A I/Os are designed to withstand current injection. For a negative injection current of

4 mA, the resulting leakage current in the adjacent input does not exceed 1 µA. Thanks to this feature, external protection diodes against current injection are no longer required.

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114

Pinouts and pin description

6 Pinouts and pin description

Figure 3. LQFP 80-pin pinout

STM8AF6388

NRST

OSCIN/PA1

OSCOUT/PA2

V

SSIO_1

V

SS

VCAP

V

DD

V

DDIO_1

TIM2_CH3/PA3

USART_RX/PA4

USART_TX/PA5

USART_CK/PA6

(

(HS) PH0

HS) PH1

PH2

PH3

AIN15/PF7

AIN14/PF6

AIN13/PF5

AIN12/PF4

6

7

8

9

10

1

2

3

4

5

11

12

13

14

15

16

17

18

19

20

2. (HS) stands for high sink capability.

53

52

51

50

49

48

47

60

59

58

57

56

55

54

46

45

44

43

42

41

PI3

PI2

PI1

PI0

PG4

PG3

PG2

PG1

PG0

PC7/SPI_MISO

PC6/SPI_MOSI

V

DDIO_2

V

SSIO_2

PC5/SPI_SCK

PC4 (HS)/TIM1_CH4

PC3 (HS)/TIM1_CH3

PC2 (HS)/TIM1_CH2

PC1 (HS)/TIM1_CH1

PC0/ADC_ETR

PE5/SPI_NSS

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STM8AF6388

Figure 4. LQFP 64-pin pinout

Pinouts and pin description

NRST

OSCIN/PA1

OSCOUT/PA2

V

SSIO_1

V

SS

VCAP

V

DD

V

DDIO_1

TIM2_CH3/PA3

USART_RX/PA4

USART_TX/PA5

USART_CK/PA6

AIN15/PF7

AIN14/PF6

AIN13/PF5

AIN12/PF4

1

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48

2 47

3 46

4 45

5 44

6 43

7 42

8 41

9 40

10 39

11 38

12 37

13 36

14 35

15 34

25 26 27 28

33

29 30 31 32

PI0

PG4

PG3

PG2

PG1

PG0

PC7/SPI_MISO

PC6/SPI_MOSI

V

DDIO_2

V

SSIO_2

PC5/SPI_SCK

PC4 (HS)/TIM1_CH4

PC3 (HS)/TIM1_CH3

PC2 (HS)/TIM1_CH2

PC1 (HS)/TIM1_CH1

PE5/SPI_NSS

3. HS stands for high sink capability.

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Pinouts and pin description

Figure 5. LQFP 48-pin pinout

STM8AF6388

NRST

OSCIN/PA1

OSCOUT/PA2

V

SSIO_1

V

SS

VCAP

V

DD

V

DDIO_1

TIM2_CH3/PA3

USART_RX/PA4

USART_TX/PA5

USART_CK/PA6

1

2

3

48 47 46 45 44 43 42 41 40 39 38 37

36

4

5

6

7

8

9

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

28

27

26

25

35

34

33

32

31

30

29

PG1

PG0

PC7/SPI_MISO

PC6/SPI_MOSI

V

DDIO_2

V

SSIO_2

PC5/SPI_SCK

PC4 (HS)/TIM1_CH4

PC3 (HS)/TIM1_CH3

PC2 (HS)/TIM1_CH2

PC1 (HS)/TIM1_CH1

PE5/SPI_NSS

4. HS stands for high sink capability.

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STM8AF6388 Pinouts and pin description

Figure 6. STM8AF62xx LQFP/VFQFPN 32-pin pinout

NRST

OSCIN/PA1

OSCOUT/PA2

V

SS

VCAP

V

DD

V

DDIO

AIN12/PF4

3

4

1

2

5

6

7

8

32 31 30 29 28 27 26 25

24

23

22

21

20

19

18

9 10 11 12 13 14 1516

17

PC7/SPI_MISO

PC6/SPI_MOSI

PC5/SPI_SCK

PC4 (HS)/TIM1_CH4

PC3 (HS)/TIM1_CH3

PC2 (HS)/TIM1_CH2

PC1 (HS)/TIM1_CH1

PE5/SPI_NSS

1. HS stands for high sink capability.

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Pinouts and pin description

Figure 7. STM8AF52x6 VFQFPN32 32-pin pinout

STM8AF6388

NRST

OSCIN/PA1

OSCOUT/PA2

V SS

VCAP

V DD

V DDIO

PA6

1

32 31 30 29 28 27 26 25

24

2 23

3 22

4

5

21

20

6

19

7

18

8

9 10 11 12 13 14 15 16

17

PG1

PG0

PC5

PC4 (HS)/TIM1_CH4

PC3 (HS)/TIM1_CH3

PC2 (HS)/TIM1_CH2

PC1 (HS)/TIM1_CH1

PE5

MSv47786V1

1. The following I/O ports are not automatically configured by hardware: PA3, PA4, PA5, PA6, PF4, PB6,

PB7, PE0, PE1, PE2, PE3, PE6, PE7. As a consequence, they must be put into one of the following configurations by software:

- configured as input with internal pull-up/down resistor,

- configured as output push-pull low.

2. HS stands for high sink capability.

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STM8AF6388 Pinouts and pin description

Type

Level

Output speed

Port and control configuration

Reset state

Table 8. Legend/abbreviation for the pin description table

I= input, O = output, S = power supply

Input

Output

CM = CMOS (standard for all I/Os)

HS = high sink (8 mA)

O1 = Standard (up to 2 MHz)

O2 = Fast (up to 10 MHz)

O3 = Fast/slow programmability with slow as default state after reset

O4 = Fast/slow programmability with fast as default state after reset

Input

Output float = floating, wpu = weak pull-up

T = true open drain, OD = open drain, PP = push pull

Bold X (pin state after reset release).

Unless otherwise specified, the pin state is the same during the reset phase (i.e.

“under reset”) and after internal reset release (i.e. at reset state).

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Pinouts and pin description

Pin number

Table 9. STM8AF6388 pin description

Input Output

Pin name

STM8AF6388

Main function

(after reset)

Default alternate function

Alternate function after remap

[option bit]

1 1 1

2 2 2

3 3 3

4 4 4

5 5 5

6 6 6

7 7 7

8 8 8

9 9 9

10 10 10 -

11 11 11 -

12 12 12 -

13 -

14 -

15 -

16 -

17 13 -

-

-

-

-

-

18 14

19 15

20 16

21 17

-

-

-

-

5

6

7

-

3

-

4

1

2

8

-

-

-

NRST

PA1/OSCIN

(1)

I/O X -

I/O X X O1 X X Port A1

Reset

Resonator/ crystal in

PA2/OSCOUT

V

SSIO_1

V

SS

I/O

S

S

X

-

-

X X

-

-

-

-

-

-

O1

-

-

X

-

-

X

-

-

Port A2

Resonator/ crystal out

I/O ground

Digital ground

VCAP S -

1.8 V regulator capacitor

V

DD

V

DDIO_1

S -

S -

Digital power supply

I/O power supply

PA3/TIM2_CH3 I/O

PA4/USART_RX I/O

PA5/USART_TX I/O

X

X

X

X X

X X

X X -

-

O1

O3

O3

X

X

X

X

X

X

Port A3

Port A4

Port A5

Timer 2 - channel 3

USART receive

USART transmit

PA6/USART_CK I/O

PH0

PH1

PH2

PH3

PF7/AIN15

PF6/AIN14

PF5/AIN13

PF4/AIN12

PF3/AIN11

X X X O3

I/O X X - HS O3

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

X

X

X

X

X

X

X

X

X - HS O3

X -

X -

X -

X -

X -

X -

X -

-

-

-

-

-

-

-

O1

O1

O1

O1

O1

O1

O1

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

Port A6

Port H0

Port H1

Port H2

Port H3

Port F7

Port F6

Port F5

Port F4

Port F3

USART synchro nous clock

-

-

-

-

Analog input 15

Analog input 14

Analog input 13

Analog input 12

Analog input 11

-

-

-

-

-

-

-

-

-

-

-

-

-

TIM3_CH1

[AFR1]

-

-

-

-

-

-

-

34/116 DocID031156 Rev 1

STM8AF6388

Pin number

Pinouts and pin description

Table 9. STM8AF6388 pin description (continued)

Input Output

Pin name

Main function

(after reset)

Default alternate function

Alternate function after remap

[option bit]

22 18

25 21

26 22

-

23 19 13 9

24 20 14 10

-

-

27 23 15

28 24 16

29 25 17

30 26 18

31 27 19

32 28 20

33 29 21

-

-

-

-

-

11

12

13

14

15

34 30 22 16

35

36

37

38 -

-

-

-

-

-

-

-

-

-

-

-

V

V

V

V

REF+

DDA

SSA

REF-

PF0/AIN10

PB7/AIN7

PB6/AIN6

PB5/AIN5

PB4/AIN4

PB3/AIN3

PB2/AIN2

PB1/AIN1

PB0/AIN0

PH4/TIM1_ETR

PH5/

TIM1_CH3N

PH6/

TIM1_CH2N

PH7/

TIM1_CH1N

S -

S -

S -

-

-

-

-

-

-

-

-

ADC positive reference voltage

Analog power supply

Analog ground

S

I/O

-

X

-

X -

-

-

-

O1

-

X

-

X

ADC negative reference voltage

Port F0

Analog input 10

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

X

X

X

X

X

X

X

X

X

X

X

X

X X

X X

X X

X X

X X

X X

X X

X X

X -

X -

X -

X -

-

-

-

-

-

-

-

-

-

-

O1

O1

O1

O1

O1

O1

O1

O1

O1

O1

O1

O1

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

Port B7

Port B6

Port B5

Port B4

Port B3

Port B2

Port B1

Port B0

Port H4

Port H5

Port H6

Port H7

Analog input 7

Analog input 6

Analog input 5

Analog input 4

Analog input 3

Analog input

Analog input 1

Analog input 0

Timer 1 - trigger input

Timer 1 - inverted channel 3

Timer 1 - inverted channel 2

Timer 1 - inverted channel 2

-

-

-

-

-

-

-

-

-

-

-

I

2

C_SDA

[AFR6]

I

2

C_SCL

[AFR6]

TIM1_ETR

[AFR5]

TIM1_CH3N

[AFR5]

TIM1_CH2N

[AFR5]

TIM1_CH1N

[AFR5]

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Pinouts and pin description

Pin number

Table 9. STM8AF6388 pin description (continued)

Input Output

Pin name

STM8AF6388

Main function

(after reset)

Default alternate function

Alternate function after remap

[option bit]

39 31 23

40 32 24

41 33 25

42 -

43 34 26

-

17

-

18

PE7/AIN8

PE6/AIN9

PE5/SPI_NSS

PC0/ADC_ETR

PC1/TIM1_CH1

I/O

I/O

I/O

I/O

I/O

X

X

X

X

X

X -

X X

X X

X X -

-

-

O1

O1

O1

O1

X X HS O3

X

X

X

X

X

X

X

X

X

X

Port E7

Port E6

Port E5

Port C0

Port C1

Analog input 8

Analog input 9

SPI master/ slave select

ADC trigger input

Timer 1 - channel 1

44 35 27

45 36 28

46 37 29

19

20

21

PC2/TIM1_CH2

PC3/TIM1_CH3

PC4/TIM1_CH4

I/O

I/O

I/O

X

X

X

X X HS O3

X X HS O3

X X HS O3

X

X

X

X

X

X

Port C2

Port C3

Port C4

Timer 1- channel 2

Timer 1 - channel 3

Timer 1 - channel 4

47 38 30

48 39 31

49 40 32

50 41 33

22

-

-

23

PC5/SPI_SCK I/O X X X O3 X X Port C5 SPI clock

V

SSIO_2

V

DDIO_2

S -

S -

-

-

-

-

I/O ground

I/O power supply

PC6/SPI_MOSI I/O X X X O3 X X Port C6

SPI master out/ slave in

51 42 34 24 PC7/SPI_MISO I/O X X X O3 X X Port C7

SPI master in/ slave out

52 43 35 -

53 44 36 -

54 45 -

55 46 -

-

56 47 -

57 48 -

58 -

59 -

60 -

-

-

-

-

-

PG0

PG1

PG2

PG3

PG4

PI0

PI1

PI2

PI3

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

X

X

X

X

X

X

X

X

X

X -

X -

X -

X -

X -

X -

X -

X -

X -

-

-

-

-

-

-

-

-

O1

O1

O1

O1

O1

O1

O1

O1

O1

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

Port G0

Port G1

Port G2

Port G3

Port G4

Port I0

Port I1

Port I2

Port I3

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

36/116 DocID031156 Rev 1

STM8AF6388

Pin number

Pinouts and pin description

Table 9. STM8AF6388 pin description (continued)

Input Output

Pin name

Main function

(after reset)

Default alternate function

Alternate function after remap

[option bit]

61

62

-

-

63 49

64 50

65 51

66 52

-

-

-

-

-

-

67 53 37

68 54 38

69 55 39

70 56 40

71

72

-

-

-

-

73 57 41

74 58 42

75 59 43

76 60 44

77 61 45

78 62 46

79 63 47

80 64 48

-

-

-

-

-

-

-

-

-

-

-

-

25

26

27

28

29

30

31

32

PI4

PI5

PG5

PG6

I/O X X O1 X X Port I4

I/O X X O1 X X Port I5

I/O X X O1 X X Port G5

I/O X X O1 X X Port G6 -

-

-

-

PG7

PE4

I/O X X O1 X X Port G7

I/O X X X O1 X X Port E4

PE3/TIM1_BKIN I/O

PE2/I

PE1/I

2

2

X X X O1

C_SDA I/O X - X O1 T

C_SCL I/O X - X -

O1 T

X

(2)

(2)

X Port E3

Port E2

Timer 1 - break input

I

2

C data

Port E1 I

2

C clock

PE0/CLK_CCO

PI6

I/O

I/O

X

X

X X

X -

O3

O1

X

X

X

X

Port E0

Port I6

Configurabl e clock output

-

PI7 I/O X X O1 X X Port I7 -

-

-

PD0/TIM3_CH2

PD1/SWIM

(3)

PD2/TIM3_CH1

PD3/TIM2_CH2

PD4/TIM2_CH1/

BEEP

PD5/

LINUART_TX

PD6/

LINUART_RX

PD7/TLI

(4)

I/O

I/O X

I/O

I/O

I/O

I/O

I/O

I/O

X

X

X

X

X

X

X

X X HS O3

X X HS O4

X X HS O3

X X HS O3

X X HS O3

X X

X X

X X -

-

O1

O1

O1

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

Port D0

Port D1

Port D2

Port D3

Port D4

Port D5

Port D6

Port D7

-

-

-

-

-

-

-

-

-

-

Timer 3 channel 2

-

-

TIM1_BKIN

[AFR3]/

CLK_CCO

[AFR2]

SWIM data interface

Timer 3 channel 1

Timer 2 - channel 2

Timer 2 channel 1

LINUART data transmit

LINUART data receive

Top level interrupt

-

-

-

-

TIM2_CH3

[AFR1]

ADC_ETR

[AFR0]

BEEP output

[AFR7]

DocID031156 Rev 1 37/116

114

Pinouts and pin description STM8AF6388

1. In Halt/Active-halt mode, this pin behaves as follows:

- The input/output path is disabled.

- If the HSE clock is used for wakeup, the internal weak pull-up is disabled.

- If the HSE clock is off, the internal weak pull-up setting is used. It is configured through Px_CR1[7:0] bits of the corresponding port control register. Px_CR1[7:0] bits must be set correctly to ensure that the pin is not left floating in

Halt/Active-halt mode.

2. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, week pull-up and protection diode to V not implemented)

DD

are

3. The PD1 pin is in input pull-up during the reset phase and after reset release.

4. If this pin is configured as interrupt pin, it will trigger the TLI.

38/116 DocID031156 Rev 1

STM8AF6388 Pinouts and pin description

As shown in the rightmost column of Table 9

, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits.

Refer to Section 9: Option bytes on page 54 . When the remapping option is active, the

default alternate function is no longer available.

To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers.

Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the

GPIO section of STM8S series and STM8AF series 8-bit microcontrollers reference manual,

RM0016).

DocID031156 Rev 1 39/116

114

Memory and register map

7 Memory and register map

Figure 8. Register and memory map

0x00 0000

6 Kbyte RAM

0x00 1400

0x00 17FF

stack

Reserved

0x00 4000

0x00 4800

0x00 4900

0x00 5000 up to 2 Kbyte data EEPROM

Option bytes

Reserved

0x00 5800

0x00 6000

Hardware registers

Reserved

2 Kbyte of Boot ROM

0x00 6800

Reserved

0x00 7F00

0x00 8000

0x00 8080

CPU/SWIM/debug/ITC registers

Interrupt vectors

Up to 128 Kbyte of Flash

program memory

Flash program memory end address

STM8AF6388

MS38340V1

40/116 DocID031156 Rev 1

STM8AF6388 Memory and register map

Flash program memory size

128 K

64 K

32 K

Table 10. Memory model 128K

Flash program memory end address

RAM size

RAM end address

0x00 27FFF

0x00 17FFF

0x00 0FFFF

6 K 0x00 17FF

Stack roll-over address

0x00 1400

In this section the memory and register map of the devices covered by this datasheet is described. For a detailed description of the functionality of the registers, refer to STM8S series and STM8AF series 8-bit microcontrollers reference manual, RM0016.

Address Block

Table 11. I/O port hardware register map

Register label Register name

0x00 500B

0x00 500C

0x00 500D

0x00 500E

0x00 500F

0x00 5010

0x00 5011

0x00 5012

0x00 5013

0x00 5000

0x00 5001

0x00 5002

0x00 5003

0x00 5004

0x00 5005

0x00 5006

0x00 5007

0x00 5008

0x00 5009

0x00 500A

Port A

Port B

Port C

Port D

PB_IDR

PC_DDR

PC_CR1

PC_CR2

PD_ODR

PD_IDR

PD_DDR

PD_CR1

PD_CR2

PA_ODR

PA_IDR

PA_DDR

PA_CR1

PA_CR2

PB_ODR

PB_IDR

PB_DDR

PB_CR1

PB_CR2

PC_ODR

Port A data output latch register

Port A input pin value register

Port A data direction register

Port A control register 1

Port A control register 2

Port B data output latch register

Port B input pin value register

Port B data direction register

Port B control register 1

Port B control register 2

Port C data output latch register

Port C input pin value register

Port C data direction register

Port C control register 1

Port C control register 2

Port D data output latch register

Port D input pin value register

Port D data direction register

Port D control register 1

Port D control register 2

Reset status

0x00

0xXX

(1)

0x00

0x00

0x00

0x00

0xXX

(1)

0x00

0x00

0x00

0x00

0xXX

(1)

0x00

0x00

0x00

0x00

0xXX

(1)

0x00

0x02

0x00

DocID031156 Rev 1 41/116

114

Memory and register map

Table 11. I/O port hardware register map (continued)

Block Register label Register name Address

0x00 5014

0x00 5015

0x00 5016

0x00 5017

0x00 5018

0x00 5019

0x00 501A

0x00 501B

0x00 501C

0x00 501D

0x00 501E

0x00 501F

0x00 5020

0x00 5021

0x00 5022

0x00 5023

0x00 5024

0x00 5025

0x00 5026

0x00 5027

0x00 5028

0x00 5029

0x00 502A

0x00 502B

0x00 502C

Port E

Port F

Port G

Port H

Port I

1. Depends on the external circuitry.

PE_ODR

PE_IDR

PE_DDR

PE_CR1

PE_CR2

PF_ODR

PF_IDR

PF_DDR

PF_CR1

PF_CR2

PG_ODR

PG_IDR

PG_DDR

PG_CR1

PG_CR2

PH_ODR

PH_IDR

PH_DDR

PH_CR1

PH_CR2

PI_ODR

PI_IDR

PI_DDR

PI_CR1

PI_CR2

Port E data output latch register

Port E input pin value register

Port E data direction register

Port E control register 1

Port E control register 2

Port F data output latch register

Port F input pin value register

Port F data direction register

Port F control register 1

Port F control register 2

Port G data output latch register

Port G input pin value register

Port G data direction register

Port G control register 1

Port G control register 2

Port H data output latch register

Port H input pin value register

Port H data direction register

Port H control register 1

Port H control register 2

Port I data output latch register

Port I input pin value register

Port I data direction register

Port I control register 1

Port I control register 2

STM8AF6388

Reset status

0x00

0x00

0x00

0x00

0xXX

(1)

0x00

0x00

0x00

0x00

0xXX

(1)

0x00

0xXX

(1)

0x00

0x00

0x00

0x00

0xXX

(1)

0x00

0x00

0x00

0x00

0xXX

(1)

0x00

0x00

0x00

42/116 DocID031156 Rev 1

STM8AF6388 Memory and register map

Address

0x00 505A

0x00 505B

0x00 505C

0x00 505D

0x00 505E

0x00 505F

0x00 5060 to

0x005061

0x00 5062

0x00 5063

0x00 5064

0x00 5065 to

0x00 509F

0x00 50A0

0x00 50A1

0x00 50A2 to

0x00 50B2

0x00 50B3

0x00 50B4 to

0x00 50BF

0x00 50C0

0x00 50C1

0x00 50C2

Block

Flash

Table 12. General hardware register map

Register label Register name

Reset status

FLASH_CR1 Flash control register 1

FLASH_CR2 Flash control register 2

FLASH_NCR2 Flash complementary control register 2

0x00

0x00

0xFF

FLASH_FPR Flash protection register 0x00

FLASH_NFPR Flash complementary protection register 0xFF

FLASH_IAPSR

Flash in-application programming status register

0x40

Reserved area (2 bytes)

Flash

Flash

ITC

RST

CLK

FLASH_PUKR

Flash Program memory unprotection register

Reserved area (1 byte)

FLASH_DUKR Data EEPROM unprotection register

Reserved area (59 bytes)

EXTI_CR1

EXTI_CR2

External interrupt control register 1

External interrupt control register 2

Reserved area (17 bytes)

RST_SR Reset status register

Reserved area (12 bytes)

CLK_ICKR

CLK_ECKR

Internal clock control register

External clock control register

Reserved area (1 byte)

0x00

0x00

0x00

0x00

0xXX

(1)

0x01

0x00

DocID031156 Rev 1 43/116

114

Memory and register map STM8AF6388

Address

0x00 50C3

0x00 50C4

0x00 50C5

0x00 50C6

0x00 50C7

0x00 50C8

0x00 50C9

0x00 50CA

0x00 50CB

0x00 50CC

0x00 50CD

0x00 50CE to 0x00 50D0

0x00 50D1

0x00 50D2

0x00 50D3 to

0x00 50DF

0x00 50E0

0x00 50E1

0x00 50E2

0x00 50E3 to

0x00 50EF

0x00 50F0

0x00 50F1

0x00 50F2

0x00 50F3

0x00 50F4 to

0x00 50FF

Table 12. General hardware register map (continued)

Block

CLK

Register label Register name

CLK_SWR

CLK_SWCR

CLK_CKDIVR

CLK_PCKENR1

Clock master switch register

Clock switch control register

Clock divider register

Peripheral clock gating register 1

CLK_CSSR

CLK_CCOR

CLK_PCKENR2

Clock security system register

Configurable clock control register

Peripheral clock gating register 2

Reserved area (1 byte)

CLK_HSITRIMR HSI clock calibration trimming register

CLK_SWIMCCR SWIM clock control register

0x00

0bXXXX

XXX0

Reset status

0xE1

0xE1

0xXX

0x18

0xFF

0x00

0x00

0xFF

WWDG

IWDG

AWU

BEEP

WWDG_CR

WWDG_WR

Reserved area (3 bytes)

WWDG control register

WWDR window register

IWDG_KR

IWDG_PR

IWDG_RLR

Reserved area (13 bytes)

IWDG key register

IWDG prescaler register

IWDG reload register

Reserved area (13 bytes)

AWU_CSR1

AWU_APR

AWU_TBR

BEEP_CSR

AWU control/status register 1

AWU asynchronous prescaler buffer register

AWU timebase selection register

BEEP control/status register

Reserved area (12 bytes)

0x7F

0x7F

0xXX (2)

0x00

0xFF

0x00

0x3F

0x00

0x1F

44/116 DocID031156 Rev 1

STM8AF6388 Memory and register map

Address

0x00 5200

0x00 5201

0x00 5202

0x00 5203

0x00 5204

0x00 5205

0x00 5206

0x00 5207

0x00 5208 to

0x00 520F

0x00 5210

0x00 5211

0x00 5212

0x00 5213

0x00 5214

0x00 5215

0x00 5216

0x00 5217

0x00 5218

0x00 5219

0x00 521A

0x00 521B

0x00 521C

0x00 521D

0x00 521E to

0x00 522F

Table 12. General hardware register map (continued)

Block Register label Register name

SPI

I2C

SPI_CR1

SPI_CR2

SPI_ICR

SPI_SR

SPI_DR

SPI_CRCPR

SPI_RXCRCR

SPI_TXCRCR

SPI control register 1

SPI control register 2

SPI interrupt control register

SPI status register

SPI data register

SPI CRC polynomial register

SPI Rx CRC register

SPI Tx CRC register

I2C_CR1

I2C_CR2

I2C_FREQR

I2C_OARL

I2C_OARH

I2C_DR

I2C_SR1

I2C_SR2

I2C_SR3

I2C_ITR

I2C_CCRL

I2C_CCRH

I2C_TRISER

Reserved area (8 bytes)

I2C control register 1

I2C control register 2

I2C frequency register

I2C own address register low

I2C own address register high

I2C data register

I2C status register 1

I2C status register 2

I2C status register 3

I2C interrupt control register

I2C clock control register low

I2C clock control register high

I2C TRISE register

Reserved area (18 bytes)

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x02

Reset status

0x00

0x00

0x00

0x02

0x00

0x07

0xFF

0xFF

DocID031156 Rev 1 45/116

114

Memory and register map

Table 12. General hardware register map (continued)

Block Register label Register name Address

0x00 5230

0x00 5231

0x00 5232

0x00 5233

0x00 5234

0x00 5235

0x00 5236

0x00 5237

0x00 5238

0x00 5239

0x00 523A

0x00 523B to

0x00 523F

0x00 5240

0x00 5241

0x00 5242

0x00 5243

0x00 5244

0x00 5245

0x00 5246

0x00 5247

0x00 5248

0x00 5249

0x00 524A to

0x00 524F

USART

LINUART

UART1_DR

UART1_BRR1

UART1_BRR2

UART1_CR1

UART1_CR2

UART1_CR3

UART1_CR4

UART1_CR5

UART1_GTR

UART1_PSCR

USART data register

USART baud rate register 1

USART baud rate register 2

USART control register 1

USART control register 2

USART control register 3

USART control register 4

USART control register 5

USART guard time register

USART prescaler register

Reserved area (5 bytes)

UART3_DR

UART3_BRR1

UART3_BRR2

UART3_CR1

UART3_CR2

UART3_CR3

UART3_CR4

UART3_CR6

LINUART data register

LINUART baud rate register 1

LINUART baud rate register 2

LINUART control register 1

LINUART control register 2

LINUART control register 3

LINUART control register 4

Reserved

LINUART control register 6

Reserved area (6 bytes)

STM8AF6388

Reset status

0x00

0xXX

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0xXX

0x00

0x00

0x00

0x00

0x00

0x00

46/116 DocID031156 Rev 1

STM8AF6388 Memory and register map

Address

0x00 5261

0x00 5262

0x00 5263

0x00 5264

0x00 5265

0x00 5266

0x00 5267

0x00 5268

0x00 5269

0x00 526A

0x00 526B

0x00 526C

0x00 526D

0x00 526E

0x00 526F

0x00 5270 to

0x00 52FF

0x00 5250

0x00 5251

0x00 5252

0x00 5253

0x00 5254

0x00 5255

0x00 5256

0x00 5257

0x00 5258

0x00 5259

0x00 525A

0x00 525B

0x00 525C

0x00 525D

0x00 525E

0x00 525F

0x00 5260

Table 12. General hardware register map (continued)

Block

TIM1

Register label Register name

Reset status

TIM1_PSCRL

TIM1_ARRH

TIM1_ARRL

TIM1_RCR

TIM1_CCR1H

TIM1_CCR1L

TIM1_CCR2H

TIM1_CCR2L

TIM1_CCR3H

TIM1_CCR3L

TIM1_CCR4H

TIM1_CCR4L

TIM1_BKR

TIM1_DTR

TIM1_OISR

TIM1_CR1

TIM1_CR2

TIM1_SMCR

TIM1_ETR

TIM1_IER

TIM1_SR1

TIM1_SR2

TIM1 control register 1

TIM1 control register 2

TIM1 slave mode control register

TIM1 external trigger register

TIM1 Interrupt enable register

TIM1 status register 1

TIM1 status register 2

TIM1_EGR TIM1 event generation register 0x00

TIM1_CCMR1 TIM1 capture/compare mode register 1 0x00

TIM1_CCMR2 TIM1 capture/compare mode register 2 0x00

TIM1_CCMR3 TIM1 capture/compare mode register 3 0x00

TIM1_CCMR4 TIM1 capture/compare mode register 4 0x00

TIM1_CCER1 TIM1 capture/compare enable register 1 0x00

TIM1_CCER2 TIM1 capture/compare enable register 2 0x00

TIM1_CNTRH

TIM1_CNTRL

TIM1_PSCRH

TIM1 counter high

TIM1 counter low

TIM1 prescaler register high

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

TIM1 prescaler register low

TIM1 auto-reload register high

TIM1 auto-reload register low

TIM1 repetition counter register

TIM1 capture/compare register 1 high

TIM1 capture/compare register 1 low

TIM1 capture/compare register 2 high

TIM1 capture/compare register 2 low

TIM1 capture/compare register 3 high

TIM1 capture/compare register 3 low

TIM1 capture/compare register 4 high

TIM1 capture/compare register 4 low

TIM1 break register

TIM1 dead-time register

TIM1 output idle state register

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0xFF

0xFF

0x00

0x00

0x00

0x00

0x00

0x00

Reserved area (147 bytes)

DocID031156 Rev 1 47/116

114

Memory and register map STM8AF6388

Address

0x00 5300

0x00 5301

0x00 5302

0x00 5303

0x00 5304

0x00 5305

0x00 5306

0x00 5307

0x00 5308

0x00 5309

0x00 530A

0x00 530B

00 530C0x

0x00 530D

0x00 530E

0x00 530F

0x00 5310

0x00 5311

0x00 5312

0x00 5313

0x00 5314

0x00 5315 to

0x00 531F

Table 12. General hardware register map (continued)

Block

TIM2

Register label Register name

Reset status

TIM2_CR1

TIM2_IER

TIM2_SR1

TIM2 control register 1

TIM2 interrupt enable register

TIM2 status register 1

0x00

0x00

0x00

TIM2_SR2

TIM2_EGR

TIM2 status register 2

TIM2 event generation register

0x00

0x00

TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00

TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00

TIM2_CCMR3 TIM2 capture/compare mode register 3 0x00

TIM2_CCER1 TIM2 capture/compare enable register 1 0x00

TIM2_CCER2 TIM2 capture/compare enable register 2 0x00

TIM2_CNTRH TIM2 counter high 0x00

TIM2_CNTRL

TIM2_PSCR

TIM2_ARRH

TIM2 counter low

TIM2 prescaler register

TIM2 auto-reload register high

0x00

0x00

0xFF

TIM2_ARRL

TIM2_CCR1H

TIM2_CCR1L

TIM2_CCR2H

TIM2_CCR2L

TIM2_CCR3H

TIM2_CCR3L

TIM2 auto-reload register low

TIM2 capture/compare register 1 high

TIM2 capture/compare register 1 low

TIM2 capture/compare reg. 2 high

TIM2 capture/compare register 2 low

TIM2 capture/compare register 3 high

TIM2 capture/compare register 3 low

0xFF

0x00

0x00

0x00

0x00

0x00

0x00

Reserved area (11 bytes)

48/116 DocID031156 Rev 1

STM8AF6388 Memory and register map

Address

0x00 5320

0x00 5321

0x00 5322

0x00 5323

0x00 5324

0x00 5325

0x00 5326

0x00 5327

0x00 5328

0x00 5329

0x00 532A

0x00 532B

0x00 532C

0x00 532D

0x00 532E

0x00 532F

0x00 5330

0x00 5331 to

0x00 533F

0x00 5340

0x00 5341

0x00 5342

0x00 5343

0x00 5344

0x00 5345

0x00 5346

0x00 5347 to

0x00 53FF

Table 12. General hardware register map (continued)

Block

TIM3

Register label Register name

Reset status

TIM3_CR1

TIM3_IER

TIM3_SR1

TIM3 control register 1

TIM3 interrupt enable register

TIM3 status register 1

0x00

0x00

0x00

TIM3_SR2

TIM3_EGR

TIM3 status register 2

TIM3 event generation register

0x00

0x00

TIM3_CCMR1 TIM3 capture/compare mode register 1 0x00

TIM3_CCMR2 TIM3 capture/compare mode register 2 0x00

TIM3_CCER1 TIM3 capture/compare enable register 1 0x00

TIM3_CNTRH TIM3 counter high 0x00

TIM3_CNTRL

TIM3_PSCR

TIM3 counter low

TIM3 prescaler register

0x00

0x00

TIM3_ARRH

TIM3_ARRL

TIM3_CCR1H

TIM3_CCR1L

TIM3_CCR2H

TIM3_CCR2L

TIM3 auto-reload register high

TIM3 auto-reload register low

TIM3 capture/compare register 1 high

TIM3 capture/compare register 1 low

TIM3 capture/compare register 2 high

TIM3 capture/compare register 2 low

0xFF

0xFF

0x00

0x00

0x00

0x00

TIM4

TIM4_CR1

TIM4_IER

TIM4_SR

TIM4_EGR

TIM4_CNTR

TIM4_PSCR

TIM4_ARR

Reserved area (15 bytes)

TIM4 control register 1

TIM4 interrupt enable register

TIM4 status register

TIM4 event generation register

TIM4 counter

TIM4 prescaler register

TIM4 auto-reload register

Reserved area (185 bytes)

0x00

0x00

0x00

0x00

0x00

0x00

0xFF

DocID031156 Rev 1 49/116

114

Memory and register map STM8AF6388

Table 12. General hardware register map (continued)

Address Block Register label Register name

Reset status

0x00 5400

0x00 5401

0x00 5402

0x00 5403

0x00 5404

0x00 5405

0x00 5406

0x00 5407

0x00 5408 to

0x00 57FF

ADC

1. Depends on the previous reset source.

2. Write only register.

ADC _CSR

ADC_CR1

ADC_CR2

ADC control/status register

ADC configuration register 1

ADC configuration register 2

0x00

0x00

0x00

ADC_CR3

ADC_DRH

ADC configuration register 3

ADC data register high

0x00

0xXX

ADC_DRL ADC data register low 0xXX

ADC_TDRH ADC Schmitt trigger disable register high 0x00

ADC_TDRL ADC Schmitt trigger disable register low 0x00

Reserved area (1015 bytes)

Address

Table 13. CPU/SWIM/debug module/interrupt controller registers

Block Register label Register name

0x00 7F00

0x00 7F01

0x00 7F02

0x00 7F03

0x00 7F04

0x00 7F05

0x00 7F06

0x00 7F07

0x00 7F08

0x00 7F09

0x00 7F0A

0x00 7F0B to 0x00

7F5F

0x00 7F60

CPU (1)

CPU

A

PCE

PCH

PCL

XH

XL

YH

YL

SPH

SPL

CC

CFG_GCR

Accumulator

Program counter extended

Program counter high

Program counter low

X index register high

X index register low

Y index register high

Y index register low

Stack pointer high

Stack pointer low

Condition code register

Reserved area (85 bytes)

Global configuration register 0x00

Reset status

0x00

0x00

0x80

0x00

0x00

0x00

0x00

0x00

0x17

(2)

0xFF

0x28

50/116 DocID031156 Rev 1

STM8AF6388 Memory and register map

Address

Table 13. CPU/SWIM/debug module/interrupt controller registers (continued)

Block Register label Register name

0x00 7F70

0x00 7F71

0x00 7F72

0x00 7F73

0x00 7F74

0x00 7F75

0x00 7F76

0x00 7F77

0x00 7F78 to

0x00 7F79

0x00 7F80

0x00 7F81 to

0x00 7F8F

0x00 7F90

0x00 7F91

0x00 7F92

0x00 7F93

0x00 7F94

0x00 7F95

0x00 7F96

0x00 7F97

0x00 7F98

0x00 7F99

0x00 7F9A

0x00 7F9B to 0x00

7F9F

ITC

SWIM

DM

ITC_SPR2

ITC_SPR3

ITC_SPR4

ITC_SPR5

ITC_SPR6

ITC_SPR7

ITC_SPR8

SWIM_CSR

DM_BK1RE

DM_BK1RH

DM_BK1RL

DM_BK2RE

DM_BK2RH

DM_BK2RL

DM_CR1

DM_CR2

DM_CSR1

DM_CSR2

DM_ENFCTR

Interrupt software priority register 2

Interrupt software priority register 3

Interrupt software priority register 4

Interrupt software priority register 5

Interrupt software priority register 6

Interrupt software priority register 7

Interrupt software priority register 8

Reserved area (2 bytes)

SWIM control status register

Reserved area (15 bytes)

DM breakpoint 1 register extended byte

DM breakpoint 1 register high byte

DM breakpoint 1 register low byte

DM breakpoint 2 register extended byte

DM breakpoint 2 register high byte

DM breakpoint 2 register low byte

DM debug module control register 1

DM debug module control register 2

DM debug module control/status register 1

DM debug module control/status register 2

DM enable function register

Reserved area (5 bytes)

1. Accessible by debug module only

2. Product dependent value, see Figure 8: Register and memory map

.

Reset status

0xFF

0xFF

0xFF

0xFF

0xFF

0xFF

0xFF

0xFF

0x00

0xFF

0xFF

0xFF

0xFF

0xFF

0xFF

0x00

0x00

0x10

0x00

0xFF

DocID031156 Rev 1 51/116

114

Memory and register map

Address

0x00 5800

0x00 5801

0x00 5802

0x00 5803

0x00 5804

0x00 5805

0x00 5806

0x00 5807

0x00 5808

STM8AF6388

Block

TMU

Table 14. Temporary memory unprotection registers

Register label Register name

TMU_K1

TMU_K2

TMU_K3

TMU_K4

TMU_K5

TMU_K6

TMU_K7

TMU_K8

TMU_CSR

Temporary memory unprotection key register 1

Temporary memory unprotection key register 2

Temporary memory unprotection key register 3

Temporary memory unprotection key register 4

Temporary memory unprotection key register 5

Temporary memory unprotection key register 6

Temporary memory unprotection key register 7

Temporary memory unprotection key register 8

Temporary memory unprotection control and status register

Reset status

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

52/116 DocID031156 Rev 1

STM8AF6388 Interrupt table

Priority Source block

Table 15. STM8A interrupt table (1)

Description

Interrupt vector address

Wakeup from Halt

19

20

21

22

23

12

13

14

15

16

17

18

-

-

0

1

2

3

4

5

6

7

8

9

10

11

24

Reset

TRAP

TLI

Reset

SW interrupt

External top level interrupt

Auto-wakeup from Halt AWU

Clock controller

MISC

MISC

MISC

MISC

MISC

Timer 1

Main clock controller

External interrupt E0

External interrupt E1

Reserved Reserved

Reserved Reserved

SPI End of transfer

Timer 1

Timer 2

Timer 2

Timer 3

External interrupt E2

External interrupt E3

External interrupt E4

Update/overflow/ trigger/break

Capture/compare

Update/overflow

Capture/compare

Update/overflow

Timer 3

USART

Capture/compare

Tx complete

USART

I

2

C

Receive data full reg.

I

2

C interrupts

LINUART Tx complete/error

LINUART Receive data full reg.

ADC

Timer 4

EEPROM

End of conversion

Update/overflow

End of programming/ write in not allowed area

0x00 8000

0x00 8004

0x00 8008

0x00 800C

0x00 8010

0x00 8014

0x00 8018

0x00 801C

0x00 8020

0x00 8024

0x00 8028

0x00 802C

0x00 8030

0x00 8034

0x00 8068

1. All unused interrupts must be initialized with ‘IRET’ for robust programming.

0x00 8038

0x00 803C

0x00 8040

0x00 8044

0x00 8048

0x00 804C

0x00 8050

0x00 8054

0x00 8058

0x00 805C

0x00 8060

0x00 8064

Yes

-

-

Yes

-

-

-

Yes

Yes

Yes

Yes

Yes

-

-

Yes

Yes

-

-

-

-

-

-

-

-

-

-

-

Comments

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Port A interrupts

Port B interrupts

Port C interrupts

Port D interrupts

Port E interrupts

-

-

-

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114

Option bytes STM8AF6388

Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Each option byte has to be stored twice, for redundancy, in a regular form (OPTx) and a complemented one (NOPTx), except for the ROP (read-out protection) option byte and option bytes 8 to 16.

Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address

shown in Table 16: Option bytes below.

Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the

ROP and UBC options that can only be changed in ICP mode (via SWIM).

Refer to the STM8 Flash programming manual (PM0047) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures.

Addr.

Option name

Option byte no.

7 6

Table 16. Option bytes

5 4

Option bits

3 2 1 0

Factory default setting

0x00

4800

Read-out protection

(ROP)

0x00

4808

0x00

4809

0x00

480A

0x00

4805

0x00

4806

0x00

4807

0x00

4801

0x00

4802

0x00

4803

0x00

4804

User boot code

(UBC)

Alternate function remapping

(AFR)

Watchdog option

Clock option

HSE clock startup

OPT0

OPT1

NOPT1

OPT2

NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0 0xFF

OPT3

NOPT3

OPT4

NOPT4

OPT5

NOPT5

AFR7 AFR6 AFR5

Reserved

Reserved

Reserved

Reserved

ROP[7:0]

UBC[7:0]

NUBC[7:0]

AFR4 AFR3

LSI_

EN

NLSI_

EN

EXT

CLK

NEXT

CLK

HSECNT[7:0]

NHSECNT[7:0]

AFR2

IWDG

_HW

NIWD

G_HW

CKAW

USEL

AFR1

WWD

G _HW

NWWD

G_HW

PRSC1

AFR0

WWDG

_HALT

NWWG

_HALT

PRSC0

NCKAW

USEL

NPRSC1

NPRSC

0

0x00

0x00

0xFF

0x00

0x00

0xFF

0x00

0xFF

0x00

0xFF

54/116 DocID031156 Rev 1

STM8AF6388 Option bytes

Addr.

Option name

Option byte no.

7

Table 16. Option bytes (continued)

6 5 4

Option bits

3 2 1 0

Factory default setting

0x00

480F

0x00

4810

0x00

4811

0x00

4812

0x00

4813

0x00

480B

0x00

480C

TMU

0x00

480D Flash wait

0x00

480E states

0x00

4814

0x00

4815

0x00

4816

0x00

4817

0x00

4818

0x00

4819 to

487D

0x00

487E Boot-

0x00

487F

TMU loader

(1)

OPT6

NOPT6

OPT7

NOPT7

OPT8

OPT9

OPT10

OPT11

OPT12

OPT13

OPT14

OPT15

OPT16

OPT17

NOPT

17

TMU[3:0]

NTMU[3:0]

Reserved

Reserved

Reserved

TMU_KEY 1 [7:0]

TMU_KEY 2 [7:0]

TMU_KEY 3 [7:0]

TMU_KEY 4 [7:0]

TMU_KEY 5 [7:0]

TMU_KEY 6 [7:0]

TMU_KEY 7 [7:0]

TMU_KEY 8 [7:0]

TMU_MAXATT [7:0]

Reserved

BL [7:0]

NBL [7:0]

WAIT

STATE

NWAIT

STATE

0x00

0xFF

0x00

0xFF

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0xC7

0x00

0xFF

1. This option consists of two bytes that must have a complementary value in order to be valid. If the option is invalid, it has no effect on EMC reset.

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114

Option bytes STM8AF6388

Option byte no.

OPT0

OPT1

OPT2

Table 17. Option byte description

Description

ROP[7:0]: Memory readout protection (ROP)

0xAA: Enable readout protection (write access via SWIM protocol)

Note: Refer to STM8S series and STM8AF series 8-bit microcontrollers reference manual (RM0016) section on Flash/EEPROM memory readout protection for details.

UBC[7:0]: User boot code area

0x00: No UBC, no write-protection

0x01: Page 0 to 1 defined as UBC, memory write-protected

0x02: Page 0 to 3 defined as UBC, memory write-protected

0x03 to 0xFF: Pages 4 to 255 defined as UBC, memory write-protected

Note: Refer to STM8S series and STM8AF series 8-bit microcontrollers reference manual (RM0016) section on Flash/EEPROM write protection for more details.

AFR7: Alternate function remapping option 7

0: Port D4 alternate function = TIM2_CH1

1: Port D4 alternate function = BEEP

AFR6: Alternate function remapping option 6

0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4

1: Port B5 alternate function = I

2

C_SDA, port B4 alternate function =

I 2 C_SCL.

AFR5: Alternate function remapping option 5

0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2, port B1 alternate function = AIN1, port B0 alternate function = AIN0.

1: Port B3 alternate function = TIM1_ETR, port B2 alternate function =

TIM1_CH3N, port B1 alternate function = TIM1_CH2N, port B0 alternate function = TIM1_CH1N.

AFR4: Alternate function remapping option 4

0: Port D7 alternate function = TLI

1: Reserved

AFR3: Alternate function remapping option 3

0: Port D0 alternate function = TIM3_CH2

1: Port D0 alternate function = TIM1_BKIN

AFR2: Alternate function remapping option 2

0: Port D0 alternate function = TIM3_CH2

1: Port D0 alternate function = CLK_CCO

Note: AFR2 option has priority over AFR3 if both are activated

AFR1: Alternate function remapping option 1

0: Port A3 alternate function = TIM2_CH3, port D2 alternate function

TIM3_CH1.

1: Port A3 alternate function = TIM3_CH1, port D2 alternate function

TIM2_CH3.

AFR0: Alternate function remapping option 0

0: Port D3 alternate function = TIM2_CH2

1: Port D3 alternate function = ADC_ETR

56/116 DocID031156 Rev 1

STM8AF6388 Option bytes

Option byte no.

OPT3

OPT4

OPT5

OPT6

OPT7

OPT8

OPT9

OPT10

OPT11

Table 17. Option byte description (continued)

Description

LSI_EN: Low speed internal clock enable

0: LSI clock is not available as CPU clock source

1: LSI clock is available as CPU clock source

IWDG_HW: Independent watchdog

0: IWDG Independent watchdog activated by software

1: IWDG Independent watchdog activated by hardware

WWDG_HW: Window watchdog activation

0: WWDG window watchdog activated by software

1: WWDG window watchdog activated by hardware

WWDG_HALT: Window watchdog reset on Halt

0: No reset generated on Halt if WWDG active

1: Reset generated on Halt if WWDG active

EXTCLK: External clock selection

0: External crystal connected to OSCIN/OSCOUT

1: External clock signal on OSCIN

CKAWUSEL: Auto-wakeup unit/clock

0: LSI clock source selected for AWU

1: HSE clock with prescaler selected as clock source for AWU

PRSC[1:0]: AWU clock prescaler

00: 24 MHz to 128 kHz prescaler

01: 16 MHz to 128 kHz prescaler

10: 8 MHz to 128 kHz prescaler

11: 4 MHz to 128 kHz prescaler

HSECNT[7:0]: HSE crystal oscillator stabilization time

This configures the stabilization time to 0.5, 8, 128, and 2048 HSE cycles with corresponding option byte values of 0xE1, 0xD2, 0xB4, and 0x00.

TMU [3:0]: Enable temporary memory unprotection

0101: TMU disabled (permanent ROP).

Any other value: TMU enabled.

WAIT STATE: Wait state configuration

This option configures the number of wait states inserted when reading from the Flash/data EEPROM memory.

0: No wait state

1: One wait state

TMU_KEY 1 [7:0]: Temporary unprotection key 0

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 2 [7:0]: Temporary unprotection key 1

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 3 [7:0]: Temporary unprotection key 2

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 4 [7:0]: Temporary unprotection key 3

Temporary unprotection key: Must be different from 0x00 or 0xFF

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114

Option bytes STM8AF6388

Option byte no.

OPT12

OPT13

OPT14

OPT15

OPT16

OPT17

Table 17. Option byte description (continued)

Description

TMU_KEY 5 [7:0]: Temporary unprotection key 4

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 6 [7:0]: Temporary unprotection key 5

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 7 [7:0]: Temporary unprotection key 6

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 8 [7:0]: Temporary unprotection key 7

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_MAXATT [7:0]: TMU access failure counter

TMU_MAXATT can be initialized with the desired value only if TMU is disabled (TMU[3:0]=0101 in OPT6 option byte).

When TMU is enabled, any attempt to temporary remove the readout protection by using wrong key values increments the counter.

When the option byte value reaches 0x08, the Flash memory and data

EEPROM are erased.

BL[7:0]: Bootloader enable

If this option byte is set to 0x55 (complementary value 0xAA) the bootloader program is activated also in case of a programmed code memory (for more details, see the bootloader user manual, UM0560).

58/116 DocID031156 Rev 1

STM8AF6388 Electrical characteristics

Unless otherwise specified, all voltages are referred to V

SS

.

10.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A

T

A

= T

Amax

(given by the selected temperature range).

= -40 °C, T

A

= 25 °C, and

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production.

Unless otherwise specified, typical data are based on T

A given only as design guidelines and are not tested.

= 25 °C, V

DD

= 5.0 V. They are

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range

.

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

The loading conditions used for pin parameter measurement are shown in

Figure 9

.

Figure 9. Pin loading conditions

STM8A PIN

50 pF

MSv37796V1

DocID031156 Rev 1 59/116

114

Electrical characteristics STM8AF6388

10.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 10 .

Figure 10. Pin input voltage

STM8A PIN

V

IN

MSv37797V1

10.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 18: Voltage characteristics

,

Table 19: Current characteristics

and

Table 20: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only, and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect the device’s reliability. The device’s mission profile (application conditions) is compliant with the JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

Symbol

V

DDx

- V

SS

V

IN

Table 18. Voltage characteristics

Ratings

Supply voltage (including V

DDA and

V

DDIO

)

(1)

Input voltage on true open drain pins (PE1, PE2)

(2)

Input voltage on any other pin

(2)

|V

DDx

- V

DD

| Variations between different power pins

|V

SSx

- V

SS

| Variations between all the different ground pins

Min

-0.3

Max

6.5

V

SS

- 0.3

6.5

V

SS

- 0.3

V

DD

+ 0.3

50

50

V

ESD

Electrostatic discharge voltage

Unit

V mV see

Absolute maximum ratings

(electrical sensitivity) on page 88

1. All power (V , V external power supply

, V

DDA

) and ground (V

SS

, V

SSIO

, V

SSA

) pins must always be connected to the

2. I

INJ(PIN)

must never be exceeded. This is implicitly insured if V injection is induced by V > V

DD

IN

maximum is respected. If V

IN

while a negative injection is induced by V pads, there is no positive injection current, and the corresponding V

IN

IN

< V

SS

maximum

value. A positive

. For true open-drain

maximum must always be respected

60/116 DocID031156 Rev 1

STM8AF6388 Electrical characteristics

Symbol

Table 19. Current characteristics

Ratings Max.

Unit

I

I

VDDIO

VSSIO

Total current into V

DDIO power lines (source)

(1)(2)(3)

Total current out of V

SS IO

ground lines (sink)

(1)(2)(3)

Output current sunk by any I/O and control pin

100

100

20

I

IO mA

Output current source by any I/Os and control pin -20

I

INJ(PIN)

(4)

I

INJ(TOT)

Injected current on any pin

Sum of injected currents

±10

50

1. All power (V external supply.

, V

DDIO

, V

DDA

) and ground (V

SS

, V

SSIO

, V

SSA

) pins must always be connected to the

2. The total limit applies to the sum of operation and injected currents.

3. V includes the sum of the positive injection currents. V currents.

SSIO

includes the sum of the negative injection

4. This condition is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN >

VDD while a negative injection is induced by VIN < VSS. For true open-drain pads, there is no positive injection current allowed and the corresponding VIN maximum must always be respected.

Symbol

T

STG

T

J

Table 20. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

-65 to 150

160

Symbol

Table 21. Operating lifetime (1)

Ratings Value

OLF Conforming to AEC-Q100 rev G

− 40 to 125 °C

− 40 to 150 °C

1. For detailed mission profile analysis, please contact the nearest ST Sales Office.

Unit

°C

Unit

Grade 1

Grade 0

DocID031156 Rev 1 61/116

114

Electrical characteristics STM8AF6388

Symbol

Table 22. General operating conditions

Parameter Conditions Min Max Unit f

CPU

Internal CPU clock frequency

T

1 wait state

A

= -40 °C to 150 °C

T

0 wait state

A

= -40 °C to 150 °C

-

16 24

0 16

MHz

V

DD/

V

V

DDIO

CAP

(1)

T

T

A

J

Standard operating voltage

C

EXT

: capacitance of external capacitor

ESR of external capacitor

ESL of external capacitor

Ambient temperature

Junction temperature range

at 1 MHz

Suffix A

Suffix C

Suffix D

Suffix A

Suffix C

Suffix D

(2)

3.0

470

-

-

- 40

- 40

5.5

3300

0.3

15

85

125

150

90

130

155

V nF

Ω nH

°C

1. Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum value must be respected for the full application range.

2. This frequency of 1 MHz as a condition for V

CAP

parameters is given by design of internal regulator.

Figure 11. f

CPUmax

versus V

DD f

CPU

[MHz]

24

Functionality not guaranteed in this area

16

12

8

4

0

Functionality guaranteed

@TA -40 to 150 °C at 1 waitstate

Functionality guaranteed

@TA -40 to 150 °C at 0 waitstate

3.0

4.0

5.0

5.5

Supply voltage [V]

MSv44121V1

62/116 DocID031156 Rev 1

STM8AF6388 Electrical characteristics

Symbol t

VDD t

TEMP

V

IT+

V

IT-

V

HYS(BOR)

Table 23. Operating conditions at power-up/power-down

Parameter Conditions Min Typ Max

V

DD

rise time rate

V

DD

fall time rate

Reset release delay

Reset generation delay

Power-on reset threshold

(2) (3)

Brown-out reset threshold

Brown-out reset hysteresis

-

-

V

DD

rising

V

DD

falling

-

-

-

-

-

2

(1)

2

(1)

2.65

2.58

-

1

3

-

-

2.8

2.73

70

(1)

1.7

-

2.95

2.88

-

Unit

µs/V ms

µs mV

1. Guaranteed by design, not tested in production.

2. If V is below 3 V, the code execution is guaranteed above the V kept. The EEPROM programming sequence must not be initiated.

IT-

and V

IT+

thresholds. RAM content is

3. There is inrush current into V

DD

present after device power on to charge C

EXT energy depends from C

1.8

μ C.

EXT

capacitor value. For example, a C

EXT

capacitor. This inrush

of 1 μ F requires Q=1 μ F x 1.8 V =

V

Stabilization for the main regulator is achieved connecting an external capacitor C

EXT

V

CAP

pin. C

EXT to less than 15 nH.

to the

is specified in

Table 22 . Care should be taken to limit the series inductance

Figure 12. External capacitor C

EXT

C

ESL

ESR

RLeak

MSv36488V1

1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance.

10.3.2 Supply current characteristics

The current consumption is measured as described in

Figure 9 on page 59

and Figure 10 on page 60 .

If not explicitly stated, general conditions of temperature and voltage apply.

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114

Electrical characteristics STM8AF6388

Table 24. Total current consumption in Run, Wait and Slow mode. General conditions

for V

DD apply, T

A

= − 40 °C to 150 °C

Symbol Parameter Conditions Typ Max Unit

I

I

I

I

DD(RUN)

(1)

DD(RUN)

(1)

DD(WFI)

(1)

DD(SLOW)

(1)

Supply current in

Run mode

Supply current in

Run mode

Supply current in

Wait mode

Supply current in

Slow mode f

All peripherals clocked, code executed from Flash program memory,

HSE external clock

(without resonator)

All peripherals clocked, code executed from RAM,

HSE external clock

(without resonator)

CPU stopped, all peripherals off, HSE external clock

CPU

scaled down, all peripherals off, code executed from

RAM f

CPU

= 24 MHz 1 ws f

CPU

= 16 MHz f

CPU

= 8 MHz f

CPU

= 4 MHz f

CPU

= 2 MHz f

CPU

= 24 MHz f

CPU

= 16 MHz f

CPU

= 8 MHz f

CPU

= 4 MHz f

CPU

= 2 MHz f

CPU

= 24 MHz f

CPU

= 16 MHz f

CPU

= 8 MHz f

CPU

= 4 MHz f

CPU

= 2 MHz

External clock 16 MHz f

CPU

= 125 kHz

LSI internal RC f

CPU

= 128 kHz

1. The current due to I/O utilization is not taken into account in these values.

2. Guaranteed by design, not tested in production.

1.5

1.1

2.5

1.75

1.25

1.0

0.90

1.6

4.5

3.8

2.3

8.8

7.5

4.1

2.5

1.60

1.60

5.1

3.1

(2)

2.1

(2)

1.6

3.2

(2)

2.6

2.0

(2)

1.7

(2)

1.6

16.9

(2)

14.1

7.5

(2)

4.2

(2)

2.6

6.1

(2)

2.05

1.90

(2)

mA

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STM8AF6388 Electrical characteristics

Table 25. Total current consumption in Halt and Active-halt modes. General conditions for V applied. T

A

= − 40 °C to 55 °C unless otherwise stated

DD

Conditions

Symbol Parameter

Main voltage regulator

(MVR)

(1)

Flash mode

(2)

Clock source and temperature condition

I

DD(H)

Supply current in

Halt mode

Off

Powerdown

Supply current in

Active-halt mode with regulator on

On

Powerdown

I

DD(AH)

Supply current in

Active-halt mode with regulator off

Off

Powerdown t

WU(AH)

Wakeup time from

Active-halt mode with regulator on

Wakeup time from

Active-halt mode with regulator off

On

Off

Operating mode

1. Configured by the REGAH bit in the CLK_ICKR register.

2. Configured by the AHALT bit in the FLASH_CR1 register.

3. Guaranteed by characterization results, not tested in production.

Clocks stopped

Clocks stopped,

T

A

= 25 °C

External clock 16 MHz f

MASTER

= 125 kHz

LSI clock 128 kHz

LSI clock 128 kHz

LSI clock 128 kHz,

T

A

= 25 °C

T

A

= − 40 to 150 °C

Typ

105

105

870

250

125

125

10

50

Max Unit

135

(3)

125

1000

(3)

330

(3)

142

(3)

130

30

(3)

80

(3)

µA

µs

Current consumption for on-chip peripherals

Symbol Parameter

Table 26. Oscillator current consumption

Conditions Typ Max

(1)

Unit

I

I

DD(OSC)

DD(OSC)

HSE oscillator current consumption

HSE oscillator current

consumption

(2)

(2)

Quartz or ceramic resonator,

CL = 33 pF

V

DD

= 5 V

Quartz or ceramic resonator,

CL = 33 pF

V

DD

= 3.3 V f f f f f f

OSC

OSC

OSC

OSC

OSC

OSC

= 24 MHz

= 16 MHz

= 8 MHz

= 24 MHz

= 16 MHz

= 8 MHz

1

0.6

0.57

0.5

0.25

0.18

2.0

-

-

1.0

-

-

(3)

(3)

mA

1. During startup, the oscillator current consumption may reach 6 mA.

2. The supply current of the oscillator can be further optimized by selecting a high quality resonator with small R to crystal manufacturer for more details m

value. Refer

3. Informative data.

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114

Electrical characteristics STM8AF6388

Symbol

I

DD(PROG)

Table 27. Programming current consumption

Parameter Conditions Typ

Programming current

V

DD

= 5 V, -40 °C to 150 °C, erasing and programming data or Flash program memory

1.0

Max

1.7

Unit mA

Symbol

I

DD(TIM1)

I

DD(TIM2)

I

DD(TIM3)

I

DD(TIM4)

I

DD(USART)

I

DD(LINUART)

I

DD(SPI)

I

DD(I2C)

I

DD(AWU)

I

DD(TOT_DIG)

Table 28. Typical peripheral current consumption V

DD

= 5.0 V

(1)

Parameter

Typ. f master

= 2 MHz

Typ. f master

= 16 MHz

Typ.

f master

=24 MHz

TIM1 supply current

(2)

TIM2 supply current

(2)

TIM3 supply current

(2)

TIM4 supply current

(2)

USART supply current

(2)

LINUART supply current (2)

SPI supply current

(2)

I

2

C supply current

(2)

AWU supply current

(2)

0.03

0.02

0.01

0.004

0.03

0.03

0.01

0.02

0.003

0.23

0.12

0.1

0.03

0.09

0.11

0.04

0.06

0.02

0.34

0.19

0.16

0.05

0.15

0.18

0.07

0.91

0.05

All digital peripherals on 0.22

1 2.4

I

DD(ADC)

ADC supply current when converting (3)

0.93

0.95

0.96

1. Typical values not tested in production. Since the peripherals are powered by an internally regulated, constant digital supply voltage, the values are similar in the full supply voltage range.

2. Data based on a differential I

DD

measurement between no peripheral clocked and a single active peripheral. This measurement does not include the pad toggling consumption.

3. Data based on a differential I

DD

measurement between reset configuration and continuous A/D conversions.

Unit mA

66/116 DocID031156 Rev 1

STM8AF6388 Electrical characteristics

Current consumption curves

Figure 13 to Figure 18

show typical current consumption measured with code executing in

RAM.

Figure 13. Typ. I

@f

CPU

DD(RUN)HSE

vs. V

DD

= 16 MHz, peripherals = on

10

6

5

4

3

9

8

7

2

1

0

2.5

3 3.5

5

25°C

85°C

125°C

5.5

6 4 4.5

V

DD

[V]

Figure 14. Typ. I

DD(RUN)HSE

@ V

DD

vs. f

CPU

= 5.0 V, peripherals = on

5

4

3

2

1

0

10

9

8

7

6

0 5 25

25°C

85°C

125°C

30 10 15 fcpu [MHz]

20

Figure 15. Typ. I

@ f

CPU

DD(RUN)HSI

vs. V

DD

= 16 MHz, peripherals = off

4

3

2

1

0

2.5

3.5

4.5

VDD [V]

5.5

25°C

85°C

125°C

6.5

Figure 16. Typ. I

DD(WFI)HSE

vs. V

@ f

CPU

DD

= 16 MHz, peripherals = on

6

5

4

3

2

1

0

2.5

3.5

4.5

VDD [V]

5.5

25°C

85°C

125°C

6.5

Figure 17. Typ. I

DD(WFI)HSE

vs. f

@ V

DD

CPU

= 5.0 V, peripherals = on

6

5

4

3

2

1

0

0 5 10 15 fcpu [MHz]

20 25

25°C

85°C

125°C

30

Figure 18. Typ. I

DD(WFI)HSI

@ f

CPU

vs. V

DD

= 16 MHz, peripherals = off

2.5

2

1.5

1

0.5

0

2.5

3 3.5

4 4.5

V

DD

[V]

5 5.5

25°C

85°C

125°C

6

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114

Electrical characteristics STM8AF6388

HSE external clock

An HSE clock can be generated by feeding an external clock signal of up to 24 MHz to the

OSCIN pin.

Clock characteristics are subject to general operating conditions for V

DD

and T

A

.

Symbol

Table 29. HSE external clock characteristics

Parameter Conditions f

HSE_ext

User external clock source frequency

T

A

= -40 °C to 150 °C

V

HSEdHL

V

HSEH

Comparator hysteresis

OSCIN high-level input pin voltage

-

-

V

HSEL

OSCIN low-level input pin voltage

-

I

LEAK_HSE

OSCIN input leakage current V

SS

< V

IN

< V

DD

1. If CSS is used, the external clock must have a frequency above 500 kHz.

Min

0

(1)

0.1 x V

DD

0.7 x V

DD

V

SS

-1

Typ

-

-

-

-

-

Max

24

-

V

DD

0.3 x V

DD

+1

Unit

MHz

V

µA

Figure 19. HSE external clock source

V

HSEH

V HSEL

External clock source

OSCIN fHSE

STM8

MS36489V1

HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied using a crystal/ceramic resonator oscillator of up to 24 MHz.

All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details

(frequency, package, accuracy...).

68/116 DocID031156 Rev 1

STM8AF6388 Electrical characteristics

Symbol

Table 30. HSE oscillator characteristics

Parameter Conditions Min Typ Max Unit t

C

L1

R

/C

L2

(1) g

F m

SU(HSE)

(2)

Feedback resistor

Recommended load capacitance

Oscillator trans conductance

Startup time

-

-

-

V

DD

is stabilized

-

-

5

-

220

-

-

2.8

-

20

-

k Ω pF mA/V ms

1. The oscillator needs two load capacitors, C

(C

L1

* C

L2

)/(C

L1

+ C

L2

). If C

L1

= C

L2

, C load

= C

and C

L2

, to act as load for the crystal. The total load capacitance (C

Load

L1/2

. Some oscillators have built-in load capacitors, C

L1

and C

L2

.

) is

2. This value is the startup time, measured from the moment it is enabled (by software) until a stabilized 24 MHz oscillation is reached. It can vary with the crystal type that is used.

Figure 20. HSE oscillator circuit diagram

Rm

Lm

C

O

Cm

Resonator

C

L1

OSCIN

R

F gm f

HSE

to core

Current control

Resonator

OSCOUT

C

L2

STM8

MSv37799V1

HSE oscillator critical g

m

formula

The crystal characteristics have to be checked with the following formula:

Equation 1 g m

» g mcrit where g mcrit

can be calculated with the crystal parameters as follows:

Equation 2 g mcrit

= ( 2 × Π × f

HSE )

2

× R m

(

R m

L m

C m

: Notional resistance (see crystal specification)

: Notional inductance (see crystal specification)

: Notional capacitance (see crystal specification)

Co : Shunt capacitance (see crystal specification)

C

L1

= C

L2

= C : Grounded external capacitance

)

2

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114

Electrical characteristics STM8AF6388

10.3.4 Internal clock sources and timing characteristics

Subject to general operating conditions for V

DD

and T

A

.

High-speed internal RC oscillator (HSI)

Symbol

Table 31. HSI oscillator characteristics

Parameter Conditions f

HSI

Frequency -

HSI oscillator user trimming accuracy

Trimmed by the application for any V

DD

and T conditions

A

ACC

HS t su(HSI)

HSI oscillator accuracy

(factory calibrated)

HSI oscillator wakeup time

V

DD

= 3.0 V ≤

-40 °C ≤ T

A

≤

DD

≤ 5.5 V,

150 °C

-

1. Guaranteed by characterization results, not tested in production.

Min

-

-

-1

-5

-

-

Typ

16

-

Max

-

Unit

MHz

1

%

5

2

(1)

µs

Figure 21. Typical HSI frequency vs V

DD

3%

2%

1%

0%

-1%

-2%

-3%

2.5

3 3.5

4

V

DD

[V]

4.5

5

-40°C

25°C

85°C

125°C

5.5

6

70/116 DocID031156 Rev 1

STM8AF6388 Electrical characteristics

Low-speed internal RC oscillator (LSI)

Subject to general operating conditions for V

DD

and T

A

.

Symbol

Table 32. LSI oscillator characteristics

Parameter Conditions f

LSI t su(LSI)

Frequency -

LSI oscillator wakeup time -

1. Guaranteed by characterization results, not tested in production.

Min

112

-

Typ

128

-

Max

144

7

(1)

Unit kHz

µs

Figure 22. Typical LSI frequency vs V

DD

3%

2%

1%

0%

-1%

-2%

-3%

2.5

3 3.5

4

V

DD

[V]

4.5

5

25°C

5.5

6

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114

Electrical characteristics STM8AF6388

Flash program memory/data EEPROM memory

General conditions: T

A

= -40 °C to 150 °C.

Symbol

Table 33. Flash program memory/data EEPROM memory

Parameter Conditions

V

V

DD

DD

Operating voltage

(all modes, execution/write/erase)

Operating voltage (code execution) f

CPU

is 16 to 24 MHz with 1 ws f

CPU

is 0 to 16 MHz with 0 ws f

CPU

is 16 to 24 MHz with 1 ws f

CPU

is 0 to 16 MHz with 0 ws

Standard programming time (including erase) for byte/word/block

(1 byte/4 bytes/128 bytes) t prog

Fast programming time for 1 block

(128 bytes) t erase

Erase time for 1 block (128 bytes)

1. Guaranteed by characterization results, not tested in production.

-

-

-

Min

(1)

3.0

2.6

-

-

-

Typ Max Unit

-

-

6

3

3

5.5

5.5

6.6

3.3

3.3

V ms

Symbol

Table 34. Flash program memory

Parameter Condition Min Max Unit

T

N

WE

WE

Temperature for writing and erasing

Flash program memory endurance

(erase/write cycles) (1)

T

A

-

= 25 °C

-40

1000

150

-

°C cycles t

RET

Data retention time

T

A

= 25 °C

T

A

= 55 °C

40

20 -

years

1. The physical granularity of the memory is four bytes, so cycling is performed on four bytes even when a write/erase operation addresses a single byte.

72/116 DocID031156 Rev 1

STM8AF6388 Electrical characteristics

Symbol Parameter

Table 35. Data memory

Condition Min Max Unit

T

WE

Temperature for writing and erasing -40 150 °C

N t

WE

RET

Data memory endurance

(erase/write cycles)

Data retention time

(1) T

A

= 25 °C

T

A

= 55 °C

300 k

T

A

= -40°C to 125 °C 100 k

(2)

T

A

= 25 °C 40

(2)(3)

20

(2)(3)

-

-

-

cycles years

1. The physical granularity of the memory is four bytes, so cycling is performed on four bytes even when a write/erase operation addresses a single byte.

2. More information on the relationship between data retention time and number of write/erase cycles is available in a separate technical document.

3. Retention time for 256B of data memory after up to 1000 cycles at 125 °C.

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114

Electrical characteristics STM8AF6388

10.3.6 I/O port pin characteristics

General characteristics

Subject to general operating conditions for V

DD

and T

A

unless otherwise specified. All unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or an external pull-up or pull-down resistor.

Symbol Parameter

Table 36. I/O static characteristics

Conditions Min Typ Max

V

IL

V

IH

Low-level input voltage

High-level input voltage

-0.3 V

0.7 x V

DD

0.3 x V

DD

V

DD

+ 0.3 V

-

V hys

Hysteresis

(1)

-

0.1 x

V

DD

-

V

OH

High-level output voltage

Standard I/0, V

DD

I = 3 mA

= 5 V,

Standard I/0, V

DD

I = 1.5 mA

= 3 V,

High sink and true open drain I/0, V

DD

= 5 V

I = 8 mA

V

DD

- 0.5 V

V

DD

- 0.4 V

-

-

-

-

-

0.5

V

OL

R pu

Low-level output voltage

Pull-up resistor

Standard I/0, V

DD

I = 3 mA

= 5 V

Standard I/0, V

DD

I = 1.5 mA

= 3 V

V

DD

= 5 V, V

IN

= V

SS

Fast I/Os

Load = 50 pF

Standard and high sink I/Os

Load = 50 pF

-

-

35

-

-

0.6

0.4

50 65

-

-

-

-

35

(2)

125

(2)

t

R

, t

F

Rise and fall time

(10% - 90%)

Fast I/Os

Load = 20 pF

Standard and high sink I/Os

Load = 20 pF

-

-

-

20

(2)

50

(2)

I lkg

Digital input pad leakage current

V

SS

≤ V

IN

≤ V

DD

±1

I lkg ana

Analog input pad leakage current

V

SS

≤ V

-40 °C < T

IN

A

≤ V

DD

< 125 °C

V

SS

≤ V

-40 °C < T

IN

A

≤ V

DD

< 150 °C

-

-

-

±250

±500

I lkg(inj)

Leakage current in adjacent I/O

(3)

Injection current ±4 mA ±1

(3)

I

DDIO

Total current on either

V

DDIO

or V

SSIO

Including injection currents 60

1. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results, not tested in production.

Unit

V

V k Ω ns

µA nA

µA mA

74/116 DocID031156 Rev 1

STM8AF6388 Electrical characteristics

2. Guaranteed by design.

3. Guaranteed by characterization results, not tested in production.

Figure 23. Typical V

IL

and V

IH

vs V

DD

@ four temperatures

3

2

1

0

2.5

6

5

4

3

-40°C

25°C

85°C

125°C

3.5

4

V

DD

[V]

4.5

5 5.5

6

Figure 24. Typical pull-up resistance R

PU

vs V

DD

@ four temperatures

60

55

50

45

40

35

30

2.5

3 3.5

4

V

DD

[V]

4.5

5 5.5

-40°C

25°C

85°C

125°C

6

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114

Electrical characteristics STM8AF6388

Figure 25. Typical pull-up current I pu

vs V

DD

@ four temperatures

(1)

140

120

100

80

60

40

20

0

0

-40°C

25°C

85°C

125°C

1 2 3

V

DD

[V]

4 5 6

1. The pull-up is a pure resistor (slope goes through 0).

Typical output level curves

Figure 26

to Figure 35

show typical output level curves measured with output on a single pin.

Figure 26. Typ. V

OL

@ V

DD ports)

= 3.3 V (standard

1.5

1.25

-40°C

25°C

85°C

125°C

1

0.75

0.5

0.25

0

0 1 2 3

I

OL

[mA]

4 5 6 7

Figure 27. Typ. V

OL

@ V

DD ports)

= 5.0 V (standard

1.5

1.25

-40°C

25°C

85°C

125°C

1

0.75

0.5

0.25

0

0 2 4 6

I

OL

[mA]

8 10 12

Figure 28. Typ. V

OL

@ V

DD

= 3.3 V (true open drain ports)

2

1.75

1.5

-40°C

25°C

85°C

125°C

1.25

1

0.75

0.5

0.25

0

0 2 4 6

I

OL

[mA]

8 10 12 14

Figure 29. Typ. V

OL

@ V

DD

= 5.0 V (true open drain ports)

2

1.75

1.5

-40°C

25°C

85°C

125°C

1.25

1

0.75

0.5

0.25

0

0 5 10 15 20 25

I

OL

[mA]

76/116 DocID031156 Rev 1

STM8AF6388 Electrical characteristics

Figure 30. Typ. V

OL

@ V

DD ports)

= 3.3 V (high sink

1.5

1.25

-40°C

25°C

85°C

125°C

1

0.75

0.5

0.25

0

0 2 4 6

I

OL

[mA]

8 10 12 14

Figure 32. Typ. V

DD -

V

OH

@ V

DD

= 3.3 V

(standard ports)

2

1.75

1.5

-40°C

25°C

85°C

125°C

1.25

1

0.75

0.5

0.25

0

0 1 2 3

I

OH

[mA]

4 5 6 7

Figure 34. Typ. V

DD -

V

OH

@ V sink ports)

DD

= 3.3 V (high

2

1.75

1.5

-40°C

25°C

85°C

125°C

1.25

1

0.75

0.5

0.25

0

0 2 4 6

I

OH

[mA]

8 10 12 14

Figure 31. Typ. V

OL

@ V

DD ports)

= 5.0 V (high sink

1.5

1.25

-40°C

25°C

85°C

125°C

1

0.75

0.5

0.25

0

0 5 10

I

OL

[mA]

15 20 25

Figure 33. Typ. V

DD -

V

OH

@ V

(standard ports)

DD

= 5.0 V

2

1.75

1.5

1.25

-40°C

25°C

85°C

125°C

1

0.75

0.5

0.25

0

0 2 4 6

I

OH

[mA]

8 10 12

Figure 35. Typ. V

DD -

V

OH

@ V

DD

= 5.0 V (high sink ports)

2

1.75

1.5

-40°C

25°C

85°C

125°C

1.25

1

0.75

0.5

0.25

0

0 5 10

I

OH

[mA]

15 20 25

DocID031156 Rev 1 77/116

114

Electrical characteristics STM8AF6388

Subject to general operating conditions for V

DD

and T

A

unless otherwise specified.

Symbol

V

IL(NRST)

V

IH(NRST)

V

OL(NRST)

R

PU(NRST) t

IFP t

INFP(NRST)

Table 37. NRST pin characteristics

Parameter

NRST low-level input voltage

(1)

NRST high-level input voltage

(1)

NRST low-level output voltage

(1)

NRST pull-up resistor

NRST input filtered pulse

(1)

Conditions

-

-

I

OL

= 3 mA

-

-

Min

V

SS

0.7 x V

DD

-

30

85

NRST Input not filtered pulse duration

(2)

500

1. Guaranteed by characterization results, not tested in production.

2. Guaranteed by design, not tested in production.

Typ

-

-

-

40

-

-

Max

0.3 x V

DD

V

DD

0.6

60

315

Unit k

V

Ω ns

-

Figure 36. Typical NRST V

IL

and V

IH

vs V

DD

@ four temperatures

-40°C

25°C

85°C

125°C

6

5

4

3

2

1

0

2.5

3 3.5

4

V

DD

[V]

4.5

5 5.5

6

78/116 DocID031156 Rev 1

STM8AF6388 Electrical characteristics

45

40

Figure 37. Typical NRST pull-up resistance R

PU

vs V

DD

60

55

-40°C

25°C

85°C

125°C

50

35

30

2.5

3 3.5

4

V

DD

[V]

4.5

5 5.5

Figure 38. Typical NRST pull-up current I pu

vs V

DD

6

140

120

100

80

60

40

20

-40°C

25°C

85°C

125°C

0

0 1 2 3

V

DD

[V]

4 5 6

The reset network shown in Figure 39

protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below V

IL(NRST)

max (see

Table 37:

NRST pin characteristics ), otherwise the reset is not taken into account internally.

For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry, attention must be taken to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. Minimum recommended capacity is 10 nF.

DocID031156 Rev 1 79/116

114

Electrical characteristics STM8AF6388

Figure 39. Recommended reset pin protection

V

DD

STM8A

R

PU

External reset circuit

(Optional)

0.1 μF

NRST Filter

Internal reset

MSv38341V1

10.3.8 TIM 1, 2, 3, and 4 electrical specifications

Subject to general operating conditions for V

DD

, f

MASTER

and T

A

.

Table 38. TIM 1, 2, 3, and 4 electrical specifications

Symbol Parameter f

EXT

Timer external clock frequency

1. Not tested in production.

(1)

Conditions Min Typ Max

24

Unit

MHz

80/116 DocID031156 Rev 1

STM8AF6388 Electrical characteristics

10.3.9 SPI interface

Unless otherwise specified, the parameters given in

Table 39 are derived from tests

performed under ambient temperature, f

MASTER conditions. t

MASTER

= 1/f

MASTER

.

frequency, and V

DD supply voltage

Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Symbol Parameter

Table 39. SPI characteristics

Conditions Min Max Unit

1/t f

SCK c(SCK)

SPI clock frequency

Master mode

Slave mode

V

DD

< 4.5 V

V

DD

= 4.5 V to 5.5 V

0

0

0

10

6

8

(1)

(1)

MHz t r(SCK) t f(SCK) t su(NSS)

(3) t h(NSS)

(3)

t t w(SCKH)

(3)

w(SCKL)

(3)

t t

su(MI)

(3) su(SI)

(3)

SPI clock rise and fall time Capacitive load: C = 30 pF

NSS setup time

NSS hold time

SCK high and low time

Data input setup time

Slave mode

Slave mode

Master mode

Master mode t

SCK

/2 - 15 t

4 * t

SCK

-

MASTER

70

/2 + 15

5

25 t t

w(SCKH)

(3)

(3)

w(SCKL)

-

-

-

(2)

Slave mode 5 t t h(MI)

(3)

(3)

h(SI)

Data input hold time

Master mode

Slave mode t

a(SO)

(3)(4)

t dis(SO)

(3)(5)

Data output access time Slave mode

Data output disable time Slave mode t

v(SO)

(3)

Data output valid time

Data output valid time

Slave mode

(after enable edge)

V

DD

< 4.5 V

V

DD

= 4.5 V to 5.5 V

Master mode (after enable edge) t

v(MO)

(3)

t

h(SO)

(3)

t

h(MO)

(3)

Data output hold time

Slave mode (after enable edge)

Master mode (after enable edge)

7

10

-

25

-

-

-

31

12

3* t

MASTER

-

-

-

-

75

53

30

1. f

SCK

< f

MASTER

/2.

2. The pad has to be configured accordingly (fast mode).

3. Guaranteed by design or by characterization results, not tested in production.

4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.

ns

DocID031156 Rev 1 81/116

114

Electrical characteristics

Figure 40. SPI timing diagram in slave mode and with CPHA = 0

STM8AF6388

1. Measurement points are at CMOS levels: 0.3 V

DD

and 0.7 V

DD

.

Figure 41. SPI timing diagram in slave mode and with CPHA = 1

NSS input t

SU(NSS)

CPHA=1

CPOL=0

CPHA=1

CPOL=1 t w(SCKH) t w(SCKL) t a(SO)

MISO

OUTPUT

MOSI

INPUT t su(SI) t v(SO)

MSB OUT t h(SI)

MSB IN t c(SCK) t h(SO)

BIT6 OUT

BIT 1 IN t h(NSS) t r(SCK) t f(SCK) t dis(SO)

LSB OUT

LSB IN

1. Measurement points are at CMOS levels: 0.3 V

DD

and 0.7 V

DD

.

ai14135b

82/116 DocID031156 Rev 1

STM8AF6388

Figure 42. SPI timing diagram - master mode

Electrical characteristics

NSS input

High

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1 tc(SCK)

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INP UT

MOSI

OUTPUT tsu(MI) tw(SCKH) tw(SCKL)

MSB IN th(MI)

MSB OUT tv(MO)

1. Measurement points are at CMOS levels: 0.3 V

DD

and 0.7 V

DD

.

BIT6 IN

B I T1 OUT th(MO) tr(SCK) tf(SCK)

LSB IN

LSB OUT ai14136c

DocID031156 Rev 1 83/116

114

Electrical characteristics STM8AF6388

10.3.10 I

2

C interface characteristics

Symbol

Table 40. I 2 C characteristics

Standard mode I

2

C

Parameter

Min

(2)

Max

(2)

Fast mode I

2

C

(1)

Unit

Min

(2)

Max

(2)

t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA) t su(STA) t su(STO)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time

(V

DD

3 V to 5.5 V)

SDA and SCL fall time

(V

DD

3 V to 5.5 V)

START condition hold time

Repeated START condition setup time

STOP condition setup time

4.7

4.0

250

0

(3)

-

-

4.0

4.7

4.0

-

-

-

-

1000

300

-

-

-

1.3

0.6

100

0

(4)

-

-

0.6

0.6

0.6

-

-

900

(3)

-

-

-

300

300

-

µs ns

µs

µs t w(STO:STA)

STOP to START condition time

(bus free)

4.7

1.3

µs

C b

Capacitive load for each bus line -

1. f

MASTER

, must be at least 8 MHz to achieve max fast I

2

C speed (400 kHz)

2. Data based on standard I

2

C protocol requirement, not tested in production

400 400 pF

3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low time

4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL

84/116 DocID031156 Rev 1

STM8AF6388 Electrical characteristics

Subject to general operating conditions for V

DDA specified.

, f

MASTER

and T

A

unless otherwise

Symbol Parameter

Table 41. ADC characteristics

Conditions Min Typ Max Unit f

ADC

ADC clock frequency 111 kHz 4 MHz kHz/MHz

V

DDA

V

REF+

Analog supply

Positive reference voltage

-

-

3

2.75

-

-

5.5

V

DDA

V

REF-

Negative reference voltage V

SSA

0.5

V

V

SSA

V

DDA

V

AIN

Conversion voltage range

(1) Devices with external V

REF+

V

REF-

pins

/

-

V

REF-

V

REF+

C samp

Internal sample and hold capacitor 3 pF t t

S

(1)

STAB

Sampling time

(3 x 1/f

ADC

)

Wakeup time from standby f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 2 MHz

-

-

-

1.5

0.75

7

3.5

-

-

-

-

µs t

CONV

Total conversion time including sampling time

(14 x 1/f

ADC

)

Equivalent switch resistance f

ADC

= 4 MHz -

7

3.5

-

-

R switch

30 k Ω

1. During the sample time, the sampling capacitance, C samp

(3 pF typ), can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within t

S.

After the end of the sample time t effect on the conversion result.

S

, changes of the analog input voltage have no

Figure 43. Typical application with ADC

V

DD

V

AIN

R

AIN

C

AIN

AINx

V

T

0.6 V

V

T

0.6 V

STM8A

I

L

Rswitch

T s

10-bit A/D conversion

C samp

1. Legend: R

AIN

= external resistance, C

AIN

= capacitors, C samp

= internal sample and hold capacitor.

MSv38342V1

DocID031156 Rev 1 85/116

114

Electrical characteristics STM8AF6388

Symbol

Table 42. ADC accuracy for V

DDA

= 5 V

Parameter Conditions Typ Max

(1)

Unit

|E

O

|

|E

G

|

|E

D

|

|E

L

|

|E

T

|

|E

O

|

|E

G

|

|E

D

|

|E

L

|

|E

T

|

Total unadjusted error

Offset error

Gain error

(2)

(2)

(2)

Differential linearity error

Integral linearity error

(2)

Total unadjusted error

(2)

Offset error

(2)

Gain error

(2)

Differential linearity error

Integral linearity error

(2)

(2)

(2)

f f

ADC

ADC

= 2 MHz

= 4 MHz

1.4

0.8

0.1

0.9

0.7

1.9

1.3

0.6

1.5

1.2

(4)

(4)

(4)

(4)

(4)

3

(3)

3

2

1

1.5

4

4

3

2

(4)

(4)

(4)

(4)

1.5

(4)

LSB

1. Guaranteed by characterization results, not tested in production.

2. ADC accuracy vs. injection current: Any positive or negative injection current within the limits specified for

I

INJ(PIN)

and Σ I

INJ(PIN)

in Section 10.3.6

does not affect the ADC accuracy.

3. TUE 2LSB can be reached on specific sales types on the whole temperature range.

4. Target values.

Figure 44. ADC accuracy characteristics

E

G

1023

1022

1021

1LSBIDEAL =

1024

4

3

2

7

6

5

1

E

O

E

T

1 LSB

E

L

IDEAL

0

V

SSA

1 2 3 4 5 6 7

(2)

E

D

(3)

(1)

1021102210231024

V

DDA

1. Example of an actual transfer curve

2. The ideal transfer curve

3. End point correlation line

E

E

E

E

E

T

= Total unadjusted error: Maximum deviation between the actual and the ideal transfer curves.

O

G

D

= Offset error: Deviation between the first actual transition and the first ideal one.

= Gain error: Deviation between the last ideal transition and the last actual one.

= Differential linearity error: Maximum deviation between actual steps and the ideal one.

= Integral linearity error: Maximum deviation between any actual transition and the end point correlation line.

86/116 DocID031156 Rev 1

STM8AF6388 Electrical characteristics

Susceptibility tests are performed on a sample basis during product characterization.

Functional EMS (electromagnetic susceptibility)

While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).

• ESD : Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard.

• FTB : A burst of fast transient voltage (positive and negative) is applied to V

DD

and V

SS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard.

A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Symbol

V

FESD

V

EFTB

Table 43. EMS data

Parameter

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

DD

and V pins to induce a functional disturbance

SS

Conditions f

V

DD

= 3.3 V, T

A

MASTER

= 25 °C,

= 16 MHz (HSI clock),

Conforms to IEC 1000-4-2 f

V

DD

= 3.3 V, T

A

MASTER

= 25 °C,

= 16 MHz (HSI clock),

Conforms to IEC 1000-4-4

Level/class

3/B

4/A

DocID031156 Rev 1 87/116

114

Electrical characteristics STM8AF6388

Electromagnetic interference (EMI)

Emission tests conform to the IEC 61967-2 standard for test software, board layout and pin loading.

Table 44. EMI data

Conditions

Symbol Parameter

General conditions

Monitored frequency band 8

MHz

Max f

CPU

(1)

16

MHz

24

MHz

S

EMI

Peak level

V

DD

T

A

=

= 5 V,

25 °C,

LQFP80 package conforming to IEC

61967-2

0.1 MHz to 30 MHz

EMI level

1. Guaranteed by characterization results, not tested in production.

15

30 MHz to 130 MHz 18

130 MHz to 1 GHz -1

2

17

22

3

2.5

22

16

5

2.5

Unit dBµV

Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181.

Electrostatic discharge (ESD)

Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22-A114A/A115A standard. For more details, refer to the application note AN1181.

Symbol

Table 45. ESD absolute maximum ratings

Ratings Conditions Class

Maximum value

(1)

Unit

V

V

V

ESD(HBM)

ESD(CDM)

ESD(MM)

Electrostatic discharge voltage

(human body model)

Electrostatic discharge voltage

(charge device model)

Electrostatic discharge voltage

(charge device model)

T

A

= 25 °C, conforming to JESD22-A114

T

A

= 25 °C, conforming to JESD22-C101

T

A

= 25 °C, conforming to JESD22-A115

1. Guaranteed by characterization results, not tested in production

3A

3

B

4000

500

200

V

88/116 DocID031156 Rev 1

STM8AF6388 Electrical characteristics

Static latch-up

Two complementary static tests are required on 10 parts to assess the latch-up performance.

• A supply overvoltage (applied to each power supply pin) and

• A current injection (applied to each input, output and configurable I/O pin) are performed on each sample.

This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.

Symbol Parameter

Table 46. Electrical sensitivities

Conditions Class

(1)

LU Static latch-up class

T

A

= 25 °C

T

A

= 85 °C

T

A

= 125 °C

T

A

= 150 °C

A

1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the

JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard).

DocID031156 Rev 1 89/116

114

Package information STM8AF6388

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK ® is an ST trademark.

11.1 LQFP80 package information

Figure 45. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package outline

SEATING

PLANE

C c

0.25 mm

GAUGE PLANE ccc C

D

D1

D3

L1

L k

61

60 41

40

80

PIN 1

IDENTIFICATION

1

1. Drawing is not to scale.

e

20

21

1S_ME

90/116 DocID031156 Rev 1

STM8AF6388 Package information

Table 47. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package mechanical data (1) millimeters inches

Symbol

Min Typ Max Min Typ Max e

L

L1

D3

E

E1

E3 k ccc

D

D1 b c

A

A1

A2

-

0.050

1.350

0.220

0.090

15.800

13.800

-

15.800

13.800

-

-

0.450

-

0°

-

3.5°

-

-

-

1.400

0.320

-

16.000

14.000

12.350

16.000

14.000

12.350

0.650

0.600

1.000

1. Values in inches are converted from mm and rounded to 4 decimal digits.

-

16.200

14.200

-

-

0.750

-

7°

0.100

1.600

0.150

1.450

0.380

0.200

16.200

14.200

-

0.6220

0.5433

-

-

0.0177

-

0°

-

-

0.0020

0.0531

0.0087

0.0035

0.6220

0.5433

0.4862

0.6299

0.5512

0.4862

0.0256

0.0236

0.0394

3.5°

-

-

-

0.0551

0.0126

-

0.6299

0.5512

-

0.6378

0.5591

-

-

0.0295

-

7°

0.0039

0.0630

0.0059

0.0571

0.0150

0.0079

0.6378

0.5591

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114

Package information STM8AF6388

Figure 46. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package recommended footprint

60

61

0.65

41

40

80

1

12.75

16.7

20

21

1.2

1. Dimensions are expressed in millimeters.

1S_FP

92/116 DocID031156 Rev 1

STM8AF6388 Package information

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 47. LQFP80 marking example (package top view)

Product identification (1) XXXXXX

XXXX

Standard ST logo

Pin 1 identifier

Date code

Y WW

Revision code

MS38333V1

1. Parts marked as "ES","E” or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's quality department must be contacted to run a qualification activity prior to any decision to use these engineering samples.

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Package information STM8AF6388

11.2 LQFP64 package information

Figure 48. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline

SEATING PLANE

C

0.25 mm

GAUGE PLANE ccc C

D

D1

D3 L1

L

K

48 33

32 b

49

94/116

64 17

PIN 1

IDENTIFICATION

1 e

16

5W_ME_V3

D

D1 b c

A

A1

A2

D3

E

E1

1. Drawing is not to scale.

Table 48. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min

-

-

-

-

0.050

1.350

0.170

0.090

-

-

Typ

-

-

1.400

0.220

-

12.000

10.000

7.500

12.000

10.000

Max

1.600

0.150

1.450

0.270

0.200

-

-

-

-

-

Min

-

0.0020

0.0531

0.0067

0.0035

-

-

-

-

-

Typ

-

-

0.0551

0.0087

-

0.4724

0.3937

0.2953

0.4724

0.3937

Max

0.0630

0.0059

0.0571

0.0106

0.0079

-

-

-

-

-

DocID031156 Rev 1

STM8AF6388 Package information

Table 48. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min

L

L1 ccc

E3 e

K

-

-

0°

0.450

-

-

7.500

0.500

3.5°

0.600

1.000

-

-

-

7°

0.750

-

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

-

-

0°

0.0177

-

-

Typ

0.2953

0.0197

3.5°

0.0236

0.0394

-

Max

-

-

7°

0.0295

-

0.0031

Figure 49. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint

48

0.5

33

32

0.3

49

12.7

10.3

64

10.3

17

1.2

1

7.8

12.7

16 ai14909c

1. Dimensions are expressed in millimeters.

DocID031156 Rev 1 95/116

114

Package information STM8AF6388

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 50. LQFP64 marking example (package top view)

Product identification

(1)

XXXXXX

XXXX

Date code

Y WW

Standard ST logo

Pin 1 identifier

Revision code

MS38334V1

1. Parts marked as "ES","E” or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's quality department must be contacted to run a qualification activity prior to any decision to use these engineering samples.

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STM8AF6388 Package information

11.3 LQFP48 package information

Figure 51. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline

SEATING

PLANE

C ccc C b

37

36

D

D1

D3

25

24

0.25 mm

GAUGE PLANE

K

L1

L

48

PIN 1

IDENTIFICATION

1

1. Drawing is not to scale.

12 e

13

5B_ME_V2

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Symbol

Table 49. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data millimeters inches

(1)

Min Typ Max Min Typ Max e

L

L1

D3

E

E1

E3 k ccc b c

D

D1

A

A1

A2

-

0.050

1.350

0.170

0.090

8.800

6.800

-

8.800

6.800

-

-

0.450

-

0°

-

-

-

1.400

0.220

-

9.000

7.000

5.500

9.000

7.000

5.500

0.500

0.600

1.000

3.5°

-

1.600

0.150

1.450

0.270

0.200

9.200

7.200

-

9.200

7.200

-

-

0.750

-

7°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

-

0.3465

0.2677

-

-

0.0177

-

0°

-

-

0.0020

0.0531

0.0067

0.0035

0.3465

0.2677

0.2165

0.3543

0.2756

0.2165

0.0197

0.0236

0.0394

3.5°

-

-

-

0.0551

0.0087

-

0.3543

0.2756

-

0.3622

0.2835

-

-

0.0295

-

7°

0.0031

0.0630

0.0059

0.0571

0.0106

0.0079

0.3622

0.2835

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STM8AF6388 Package information

Figure 52. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint

0.50

1.20

0.30

37

36 25

24

0.20

7.30

9.70

5.80

7.30

48

1 12

13

1.20

5.80

9.70

ai14911d

1. Dimensions are expressed in millimeters.

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

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Package information

Figure 53. LQFP48 marking example (package top view)

STM8AF6388

Product identification

(1)

XXXXXX

XXXX

Standard ST logo

Pin 1 identifier

Date code

Y WW

Revision code

MS38335V1

1. Parts marked as "ES","E” or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's quality department must be contacted to run a qualification activity prior to any decision to use these engineering samples.

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STM8AF6388 Package information

11.4 LQFP32 package information

Figure 54. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline

SEATING

PLANE

C ccc C

25

24

D

D1

D3

17

16

L1

L

0.25 mm

GAUGE PLANE

K

32

PIN 1

IDENTIFICATION

1

1. Drawing is not to scale.

8 e

9

5V_ME_V2

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Package information STM8AF6388

Symbol

Table 50. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data millimeters inches

(1)

Min Typ Max Min Typ Max e

L

L1

D3

E

E1

E3 k ccc b c

D

D1

A

A1

A2

-

0.050

1.350

0.300

0.090

8.800

6.800

-

8.800

6.800

-

-

0.450

-

0°

-

-

-

1.400

0.370

-

9.000

7.000

5.600

9.000

7.000

5.600

0.800

0.600

1.000

3.5°

-

1.600

0.150

1.450

0.450

0.200

9.200

7.200

-

9.200

7.200

-

-

0.750

-

7°

0.100

1. Values in inches are converted from mm and rounded to 4 decimal digits.

-

0.3465

0.2677

-

-

0.0177

-

0°

-

-

0.0020

0.0531

0.0118

0.0035

0.3465

0.2677

0.2205

0.3543

0.2756

0.2205

0.0315

0.0236

0.0394

3.5°

-

-

-

0.0551

0.0146

-

0.3543

0.2756

-

0.3622

0.2835

-

-

0.0295

-

7°

0.0039

0.0630

0.0059

0.0571

0.0177

0.0079

0.3622

0.2835

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STM8AF6388 Package information

Figure 55. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package recommended footprint

0.80

25

24

0.30

17

16

1.20

0.50

7.30

9.70

6.10

7.30

32

1 8

9

1.20

6.10

9.70

5V_FP_V2

1. Dimensions are expressed in millimeters.

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Package information STM8AF6388

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 56. LQFP32 marking example (package top view)

Product identification

(1)

XXXXXX

XXXX

Standard ST logo

Pin 1 identifier

Date code

Y WW

Revision code

MS38337V1

1. Parts marked as "ES","E” or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's quality department must be contacted to run a qualification activity prior to any decision to use these engineering samples.

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STM8AF6388 Package information

11.5 VFQFPN32 package information

Figure 57. VFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch very thin profile fine pitch quad

flat package outline

Seating plane

C ddd C

A

A3 A1

D e

9 16

8 17

E2 b

Pin # 1 ID

R = 0.20

1

32

D2

Bottom view

1. Drawing is not to scale.

L

24

L

E

42_ME_AMKOR_V1

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Package information STM8AF6388

Table 51. VFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max b

D

D2

E

A

A1

A3

E2 e

L ddd

0.800

0.000

-

0.180

4.850

3.500

4.850

3.500

-

0.300

-

0.900

0.020

0.200

0.250

5.000

3.600

5.000

3.600

0.500

0.400

-

1.000

0.050

-

0.300

5.150

3.700

5.150

3.700

-

0.500

0.050

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0315

0.0000

-

0.0071

0.1909

0.1378

0.1909

0.1378

-

0.0118

-

0.0354

0.0008

0.0079

0.0098

0.1969

0.1417

0.1969

0.1417

0.0197

0.0157

-

0.0394

0.0020

-

0.0118

0.2028

0.1457

0.2028

0.1457

-

0.0197

0.0020

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Figure 58. VFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad

flat package recommended footprint

5.30

3.80

0.60

5.30

3.10 (Var A)

3.60 (Var B)

3.10 (Var A)

3.60 (Var B)

0.50

3.80

0.30

0.75

1. Dimensions are expressed in millimeters.

3.80

42_FP_AMKOR_V1

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Package information STM8AF6388

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 59. VFQFPN32 marking example (package top view)

Product identification

(1)

XXXXXX

Date code

Y WW

Standard ST logo

Pin 1 identifier

Revision code

MS38336V1

1. Parts marked as "ES","E” or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's quality department must be contacted to run a qualification activity prior to any decision to use these engineering samples.

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STM8AF6388 Package information

In case the maximum chip junction temperature (T

Jmax

) specified in Table 22: General operating conditions

is exceeded, the functionality of the device cannot be guaranteed.

T

Jmax

, in degrees Celsius, may be calculated using the following equation:

T

Jmax

= T

Amax

+ (P

Dmax

x Θ

JA

) where:

T

Amax

is the maximum ambient temperature in ° C

Θ

JA

is the package junction-to-ambient thermal resistance in ° C/W

P

Dmax

is the sum of P

INTmax

and P

I/Omax

(P

Dmax

= P

INTmax

+ P

I/Omax

)

P

INTmax

is the product of I

DD and internal power.

V

DD

, expressed in Watts. This is the maximum chip

P

I/Omax

represents the maximum power dissipation on output pins where:

P

I/Omax

= Σ (V

OL

* I

OL

) + Σ ((V

DD

- V

OH

) * I

OH

) taking into account the actual V

OL application.

/ I

OL and V

OH

/ I

OH

of the I/Os at low- and high-level in the

Symbol

Table 52. Thermal characteristics (1)

Parameter Value

Θ

JA

Thermal resistance junction-ambient

LQFP 80 - 14 x 14 mm

Thermal resistance junction-ambient

LQFP 64 - 10 x 10 mm

Thermal resistance junction-ambient

LQFP 48 - 7 x 7 mm

Thermal resistance junction-ambient

LQFP 32 - 7 x 7 mm

Thermal resistance junction-ambient

VFQFPN 32 - 5 x 5 mm

38

46

57

59

25

1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment.

Unit

°C/W

JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org.

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11.6.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the order code (see

Figure 60: STM8AF6388 ordering information scheme

1

on page 111

).

The following example shows how to calculate the temperature range needed for a given application.

Assuming the following application conditions:

– Maximum ambient temperature T

Amax

= 82 °C (measured according to JESD51-2)

– I

DDmax

= 8 mA

– V

DD

= 5 V

– maximum 20 I/Os used at the same time in output at low-level with I

OL

= 8 mA

– V

OL

= 0.4 V

P

INTmax

= 8 mA x 5 V = 400 mW

P

IOmax

= 20 x 8 mA x 0.4 V = 64 mW

This gives:

P

INTmax

= 400 mW and P

IOmax

64 mW

P

Dmax

= 400 mW + 64 mW

Thus:

P

Dmax

= 464 mW.

Using the values obtained in Table 52: Thermal characteristics T

Jmax follows:

is calculated as

For LQFP64 46 °C/W

T jmax

= 82 °C + (46 °C/W x 464 mW) = 82 °C + 21 °C = 103 ° C

This is within the range of the suffix C version parts (-40 °C < T j

< 125 ° C).

Parts must be ordered at least with the temperature range suffix C.

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STM8AF6388 Ordering information

Figure 60. STM8AF6388 ordering information scheme 1

Example:

Product class

8-bit automotive microcontroller

STM8A 2 F 63 A A T D XXX 3

Program memory type

F = Flash + EEPROM

P = FASTROM

Device family

63 = Silicon rev S, LIN only

Y

Program memory size

6 = 32 Kbyte

8 = 64 Kbyte

A= 128 Kbyte

Pin count

6 = 32 pins

8 = 48 pins

9 = 64 pins

A = 80 pins

Package type

T = LQFP

U = VFQFPN

Temperature range

A = -40 to 85 °C

C = -40 to 125 °C

D = -40 to 150 °C

Packing

Y = Tray

U = Tube

X = Tape and reel compliant with EIA 481-C

1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com

or contact the nearest ST Sales Office.

2. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 and Q002 or equivalent.

3. Customer specific FASTROM code or custom device configuration. This field shows ‘SSS’ if the device contains a super set silicon, usually equipped with bigger memory and more I/Os. This silicon is supposed to be replaced later by the target silicon.

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STM8 development tools

13 STM8 development tools

STM8AF6388

Development tools for the STM8A microcontrollers include the

• STice emulation system offering tracing and code profiling

• STVD high-level language debugger including assembler and visual development environment - seamless integration of third party C compilers

• STVP Flash programming software

In addition, the STM8A comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools.

The STM8 tool line includes the STice emulation system offering a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8A application development is supported by a low-cost in-circuit debugger/programmer.

The STice is the fourth generation of full-featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including tracing, profiling and code coverage analysis to help detect execution bottlenecks and dead code.

In addition, STice offers in-circuit debugging and programming of STM8A microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller.

For improved cost effectiveness, STice is based on a modular design that allows users to order exactly what they need to meet their development requirements and to adapt their emulation system to support existing and future ST microcontrollers.

13.1.1 STice key features

• Program and data trace recording up to 128 K records

• Advanced breakpoints with up to 4 levels of conditions

• Data breakpoints

• Real-time read/write of all device resources during emulation

• Occurrence and time profiling and code coverage analysis (new features)

• In-circuit debugging/programming via SWIM protocol

• 8-bit probe analyzer

• 1 input and 2 output triggers

• USB 2.0 high-speed interface to host PC

• Power supply follower managing application voltages between 1.62 to 5.5 V

• Modularity that allows users to specify the components they need to meet their development requirements and adapt to future requirements

• Supported by free software tools that include integrated development environment

(IDE), programming software interface and assembler for STM8.

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STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST visual develop (STVD) IDE and the ST visual programmer

(STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8.

The STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com

. This package includes:

ST visual develop

Full-featured integrated development environment from STMicroelectronics, featuring:

• Seamless integration of C and ASM toolsets

• Full-featured debugger

• Project management

• Syntax highlighting editor

• Integrated programming interface

• Support of advanced emulation features for STice such as code profiling and coverage

ST visual programmer (STVP)

Easy-to-use, unlimited graphical interface allowing read, write and verification of the STM8A microcontroller’s Flash memory. STVP also offers project mode for saving programming configurations and automating programming sequences.

13.2.2 C and assembly toolchains

Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of the application directly from an easy-to-use graphical interface. Available toolchains include:

C compiler for STM8

All compilers are available in free version with a limited code size depending on the compiler. For more information, refer to www.cosmic-software.com, www.raisonance.com, and www.iar.com.

STM8 assembler linker

Free assembly toolchain included in the STM8 toolset, which allows users to assemble and link their application source code.

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STM8 development tools STM8AF6388

During the development cycle, STice provides in-circuit programming of the STM8A Flash microcontroller on the application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming the STM8A.

For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family.

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STM8AF6388

Date

24-Oct-2017

Revision

Table 53. Document revision history

Changes

1 Initial release

Revision history

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STM8AF6388

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2017 STMicroelectronics – All rights reserved

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