Functional description
6(5,$/,1
6&.
6&/5
5&.
Figure 2. Block diagram
67$*(
6+,)75(*,67(5
%,7
6725$*(5(*,67(5
6(5,$/287
2+
M74HC595
*
67$7(
%8))(5
9&&
*1'
4$ 4% 4& 4' 4( 4) 4* 4+
3$5$//(/2873876
$0
1. This block diagram has not be used to estimate propagation delays.
Figure 3. Logic diagram
6&/5
6,
'
5
4
6&.
'
5
4
6&.
'
5
4
6&.
'
5
4
6&.
'
5
4
6&.
'
5
4
6&.
6&.
' 4
5&.
' 4
5&.
' 4
5&.
' 4
5&.
' 4
5&.
5&.
*
4$ 4% 4& 4' 4(
'
5
4
6&.
' 4
5&.
4)
'
5
4
6&.
' 4
5&.
4*
' 4
5&.
4+
4+
$0
1. This logic diagram has not be used to estimate propagation delays.
4/22 DocID1989 Rev 6
M74HC595
SI
X
X
X
L
H
X
X
X
1. X: don’t care.
X
X
SCK
X
X
X
Inputs
SCLR
X
X
L
H
H
H
X
X
Figure 4. Input and output equivalent circuit
9&& 9&&
Functional description
RCK
X
X
X
X
X
X
G
H
L
X
X
X
X
X
X
Table 3. Truth table (1)
Outputs
QA through QH outputs disable
QA through QH outputs enable
Shift register is cleared
First stage of S.R. becomes “L” other stages store the data of previous stage, respectively
First stage of S.R. becomes “H” other stages store the data of previous stage, respectively
State of S.R. is not changed
S.R. data is stored into storage register
Storage register state is not changed
,1387 287387
*1' *1'
$0
DocID1989 Rev 6 5/22
22
Functional description
6&.
6,
5&.
6&/5
4'
4(
4)
4*
*
4$
4%
4&
4+
4+
1RWH +,*+,03('$1&(
Figure 5. Timing chart
M74HC595
$0
6/22 DocID1989 Rev 6
