STMicroelectronics HCF4094 Datasheet
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HCF4094
8-stage shift and store bus register with 3-stage outputs
SO-16
Features
3- state parallel outputs for connection to common bus
Separate serial outputs synchronous to both positive and negative clock edges for cascading
Medium speed operation 5 MHz at 10 V
Quiescent current specified up to 20 V
Standardized symmetrical output characteristics
5 V, 10 V, and 15 V parametric ratings
Input leakage current I
V
DD
= 18 V, T
A
= 25
I
= 100 nA (max.) at
C
100% tested for quiescent current
ESD performance
– HBM: 1 kV
– MM: 200 V
– CDM: 1 kV
Datasheet
-
production data
Applications
Automotive
Industrial
Computer
Consumer
Description
The HCF4094 is a monolithic integrated circuit fabricated in metal oxide semiconductor technology available in an SO-16 package. The
HCF4094 is an 8-stage, serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs. The parallel outputs may be connected directly to common bus lines. Data are shifted on positive clock transition. The data in each shift register stage are transferred to the storage register when the STROBE input is high.
Data in the storage register appear at the outputs whenever the OUTPUT-ENABLE signal is high.
Two serial outputs are available for cascading a number of HCF4094 devices. Data are available at the Q
S
serial output terminal on positive clock edges to allow for high speed operation in a cascaded system in which the clock rise time is fast. The same serial information, available at the
Q’
S
terminal on the next negative clock edge, provides a means for cascading HCF4094 devices when the clock rise time is slow.
Order code
Table 1. Device summary table
Temperature range Package Packing Marking
HCF4094M013TR
HCF4094YM013TR (1)
-55 ° C to +125 ° C
-40 ° C to +125 ° C
SO-16
SO-16
(automotive grade)
Tape & reel
HCF4094
HCF4094Y
1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC
Q001 and Q002 or equivalent.
January 2014
This is information on a product in full production.
DocID002069 Rev 5 1/17 www.st.com
1
Contents
Contents
HCF4094
Pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2/17 DocID002069 Rev 5
HCF4094 Pin information
Figure 1. Pin connections (top view)
Pin no
2
1
3
9, 10
4, 5, 6, 7, 14, 13, 12, 11
15
8
16
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4
4
4
9 66
4
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46
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4
4
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Table 2. Pin description
Symbol Name and function
DATA
STROBE
CLOCK
Q
S
, Q’
S
Q1 to Q8
OUTPUT ENABLE
V
SS
V
DD
Data input
Strobe input
Clock input
Serial outputs
Parallel outputs
Output enable input
Negative supply voltage
Positive supply voltage
DocID002069 Rev 5 3/17
17
Functional description HCF4094
6(5,$/,1
&/2&.
6752%(
Figure 2. Logic diagram
' 4 ' 4
&/
&/
&/
&/
75
75
75
&/
&/
S Q
75
75
S
Q
75
75
75
/$7&+ 67$*(6
&/
&/
' 4
4
Q
&/
S
&/
&/
S
Q
&/
75
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4
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4
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966
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Clock
Output enable
H
H
L
L
H
H
Strobe
X
X
(2)
(2)
L
H
H
H
Table 3. Truth table
Parallel outputs
Data
X
(2)
X
(2)
X
(2)
L
H
H
Serial outputs
Q
1
OC
(3)
OC
(3)
Q n
OC
(3)
OC
(3)
Q
S
(1)
Q7
No change
Q’
S
No change
Q7
No change No change Q7
L Q n
-1 Q7
H Q n
-1 Q7
No change No change No change
No change
No change
No change
Q7
1. At the positive clock edge, information on the 7th shift register stage is transferred to the 8th register stage and the Q
S
output.
2. Don’t care
3. Open circuit
4/17 DocID002069 Rev 5
HCF4094 Functional description
Figure 3. Functional diagram
'$7$
&/2&.
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UHJLVWHU
4¶6
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6752%(
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966
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Figure 4. Input equivalent circuit
9''
,1387
966
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DocID002069 Rev 5 5/17
17
Functional description
&/2&.
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287387
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2873874
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Figure 5. Timing chart
HCF4094
67$7( 67$7(
67$7( 67$7(
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6/17 DocID002069 Rev 5
HCF4094 Electrical characteristics
Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. All voltage values are referred to
V
SS
pin voltage.
Symbol
Table 4. Absolute maximum ratings (AMR)
Parameter
V
DD
V
I
I
I
Supply voltage
DC input voltage
DC input current
Power dissipation per package
P
D
Power dissipation per output transistor
T op
T stg
Operating temperature
Storage temperature
1. 500 mW at 65 °C; lower to 300 mW by 10 mW/°C from 65 °C to 85 °C.
Value
-0.5 to +22
-0.5 to V
DD
+ 0.5
10
500
(1)
100
-55 to +125
-65 to +150
Unit
V mA mW
°C
Symbol
V
DD
V
I
T op
Table 5. Recommended operating conditions
Parameter Value
Supply voltage
Input voltage
Operating temperature
3 to 20
0 to V
DD
-55 to 125
Unit
V
°C
DocID002069 Rev 5 7/17
17
Electrical characteristics HCF4094
Table 6. DC specifications (1)
Test condition Value
Sym. Parameter
V
I
(V) V
O
(V) |I
O
| ( A) V
DD
(V)
T
A
= 25 °C -40 to 85 °C -55 to 125 °C
Min.
Typ. Max. Min.
Max.
Min.
Max.
Unit
V
V
I
V
I
I
V
L
OH
OL
IH
IL
OH
OL
Quiescent current
High-level output voltage
Low-level output voltage
High-level input voltage
Low-level input voltage
Output drive current
Output sink current
0/5
0/10
0/15
0/20
0/5
0/10
0/15
5/0
10/0
15/0
0/5
0/10
0/15
0/5
0/10
0/15
0.5/4.5
1/9
1.5/13.5
4.5/0.5
9/1
13.5/1.5
2.5
4.6
9.5
13.5
0.4
0.5
1.5
<1
<1
<1
<1
<1
<1
10
15
5
10
15
15
5
10
15
10
15
5
10
5
10
15
20
5
10
4.95
9.95
15 14.95
5
3.5
7
11
5
0.05
-1.36
-3.2
-0.44
-1
-1.1
-2.6
-3.0
-6.8
0.44
1
1.1
2.6
3.0
6.8
0.04
5
10
20
0.08
100
1.5
3
4
4.95
9.95
14.95
3.5
7
11
-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4
150
300
600
3000
0.05
1.5
3
4
4.95
9.95
14.95
3.5
7
11
-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4
150
300
600
3000
0.05
1.5
3
4
I
C
I
I
OH,
I
OL
I
Input leakage current
3-state output leakage current
Input capacitance
0/18
0/18
Any input
Any input
18
18
10
10
5
-5
-4
0.1
0.4
7.5
1
12
1
12
1. The noise margin for both level "1" and "0" is: 1 V min. with V
DD
V
DD
= 15 V.
= 5 V, 2 V min. with V
DD
= 10 V, and 2.5 V min. with
A
V mA
A pF
8/17 DocID002069 Rev 5
HCF4094 Electrical characteristics
Table 7. Dynamic electrical characteristics (T t f amb
= 25 °C, C
= 20 ns)
L
= 50 pF, R
L
= 200 k , t r
=
Test condition Value
(1)
Symbol Parameter Unit
V
DD
(V) Min.
Typ.
Max.
5 300 600
Propagation delay time
(clock to serial output Q
S
)
10
15
125
95
250
190 t
PLH
, t
PHL t
PZL
, t
PZH t w t s t h t
TLH
, t
THL
Propagation delay time
(clock to serial output Q’
S
)
Propagation delay time
(clock to parallel output)
Propagation delay time
(strobe to parallel output)
Propagation delay time
(output enable to parallel out: output high to high impedance)
Propagation delay time
(output enable to parallel out: output low to high impedance)
Strobe pulse width
Clock pulse width
Data setup time
Minimum hold time
Transition time
5
10
15
5
10
15
15
5
10
15
10
15
5
10
5
10
15
5
15
5
10
15
10
15
5
10
5
10
15
5
200
80
70
200
100
83
125
55
35
0
225
95
70
100
100
140
75
55
195
135
290
145
230
110
75
420
40
60
30
20
40
35
100
50
0
100
50
45
200
280
150
110
450
190
140
390
270
580
290
460
220
150
840
0
200
100
80 ns
DocID002069 Rev 5 9/17
17
Electrical characteristics HCF4094
Table 7. Dynamic electrical characteristics (T amb t f
= 25 °C, C
= 20 ns) (continued)
L
= 50 pF, R
L
= 200 k , t r
=
Test condition Value
(1)
Symbol Parameter Unit
V
DD
(V) Min.
Typ.
Max.
5 15 t r
, t f
Clock input rise or fall time 10
15
5
5
s f max
Maximum clock input frequency
5
10
15
1.25
2.5
3
2.5
5
6
MHz
1. The typical temperature coefficient for all V
DD
values is 0.3 %/°C.
Figure 6. Typical application (remote control holding register)
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10/17 DocID002069 Rev 5
HCF4094
3XOVH
JHQHUDWRU
Electrical characteristics
Figure 7. Test circuit
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1. Legend: C = 50 pF or equivalent (includes jig and probe capacitance), R generator (typically 50 )
L
= 200 K R
T
= Z
OUT
of pulse
Table 8. Propagation delay time configuration
Test Switch t
PLH
, t
PHL t
PZL
, t
PZH t
PZH
, t
PHZ
Open
V
CC
GND
Figure 8. Waveform 1: Data in to Q n
timings (50 % clock duty cycle)
QV QV
9
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&/2&.
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V
W
K
W
Z
W
Z
9
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9
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3/+
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3+/
9
2/
9
2+
9
2/
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DocID002069 Rev 5 11/17
17
Electrical characteristics
Figure 9. Waveform 2: Setup and hold times (SI to CLOCK)
(f = 1 MHz; 50 % duty cycle)
9
''
'$7$,1
9
66
W
V
W
K
9
''
HCF4094
&/2&.
W
Z
9
66
9
2+
6752%( 9
2/
W
3/+
W
3+/
9
2+
4
Q
9
2/
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Figure 10. Waveform 3: Setup and hold time (PI to P/S)
(f = 1 MHz; 50 % duty cycle)
9
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W
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2/
9
2+
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12/17 DocID002069 Rev 5
HCF4094 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
DocID002069 Rev 5 13/17
17
Package information
E
Figure 11. SO-16 package mechanical drawing
/ *
&
F
D $
H 6
D
H
(
'
0
E
HCF4094
Ref
L
M
F
G
S e e3
D
E b b1
C c1
A a1 a2
)
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Min.
0.1
0.35
0.19
9.8
5.8
3.8
4.6
0.5
Table 9. SO-16 package mechanical data
Dimensions
Millimeters Inches
Typ.
Max.
1.75
0.2
1.65
0.46
0.25
Min.
0.003
0.013
0.007
Typ.
0.5
45
0.019
45
10
6.2
0.385
0.228
1.27
8.89
0.050
0.350
4.0
5.3
1.27
0.62
8
0.149
0.181
0.019
0.393
0.244
0.157
0.208
0.050
0.024
8
Max.
0.068
0.007
0.064
0.018
0.010
14/17 DocID002069 Rev 5
HCF4094
Figure 12. SO-16 tape and reel information
Package information
1
&
$
'
7
3R
%R
3
.R
$R
*$06&%
N
T
Ao
Bo
A
C
D
Ko
Po
P
1. Drawing is not to scale.
Table 10. SO-16 tape and reel information
Dimensions
Ref Millimeters Inches
Min.
Typ.
Max.
330
13.2
Min.
Typ.
12.8
20.2
60
6.45
10.3
2.1
3.9
7.9
22.4
6.65
10.5
2.3
4.1
8.1
0.504
0.795
2.362
0.254
0.406
0.082
0.153
0.311
Max.
12.992
0.519
0.882
0.262
0.414
0.090
0.161
0.319
DocID002069 Rev 5 15/17
17
Ordering information HCF4094
Order code
Table 11. Order codes
Temperature range Package Packing Marking
HCF4094M013TR
HCF4094YM013TR
(1)
-55 ° C to +125 ° C
-40 ° C to +125 ° C
SO-16
SO-16
(automotive grade)
Tape & reel
HCF4094
HCF4094Y
1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 and Q002 or equivalent
Date
19-Feb-2013
06-Jan-2014
Revision
Table 12. Document revision history
Changes
4
5
Document template and layout updated
Removed “B” from part number
Updated package names (PDIP-16 and SO-16 instead of DIP-16 and SOP-16).
Added Applications
Added
Updated symbol names in
Added
Section 5: Ordering information
Removed DIP package option
Added ESD performance to
Updated footnote 1 of Table 1: Device summary table
Updated footnote 1 of Table 11: Order codes
16/17 DocID002069 Rev 5
HCF4094
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17
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