Advanced predefined function blocks. Schneider Electric PL7 Micro/Junior/Pro - Detailed

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2.2 Advanced predefined function blocks

Advanced instructions

Introduction

Aim of this subsection

What's in this

Section?

This sub-section describes PL7 language advanced predefined function blocks

This Section contains the following Maps:

Topic

Introduction to Monostable function block

Monostable block function operation

Configuring and programming monostable function blocks

Introduction to Register function block

Programming and configuring the Register block function

Introduction to the Cyclic Programmer (Drum) function block

Cyclic Programmer (Drum) function block operation

Programming and configuring the cyclic programmer function block (Drum)

Introduction to Timer function block series 7

Timer function block series 7 operation

Programming the series 7 timer in "Delay on engagement" mode

Programming the series 7 timer in "Delay on release" mode

Programming the series 7 timer in "Delay accumulated on engagement" mode

Programming the series 7 timer in "Delay accumulated on release" mode

Introduction to the vertical comparison operation block

Operation of vertical comparison operation block

Page

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Advanced instructions

Introduction to Monostable function block

General

Illustration

The monostable function block is used to create a pulse of precise duration. This duration is programmable and may or may not be modifiable using the terminal

Graphic representation of the monostable function block

%MNi

TB: 1mn

MN.P:9999

MODIF:Y

Characteristics Characteristics of the monostable function block

Characteristic Address

Number %MNi

Time base

Current value

%MNi.V

Preset value

MODIF modification

Input "Start" (or instruction)

Output

"Monostable"

Value

0 to 7 for a TSX 37, 0 to 254 for a TSX 57

1min, 1s, 100ms, 10ms (1mn by default)

%MNi.P

Y/N

S (Start)

Word which decreases from %MNi.P to 0 on completion of the timer cycle. May be read, tested but not written.

≤

%MNi.P

≤

9999 . Word which can be read, tested and written. The pulse period (PRESET) is equal to: %MNi.P x

TB l l

Y: possibility to modify the preset value in adjust mode

N: cannot be accessed in adjust mode

On the rising edge %MNi.V = %MNi.P then %MNi.V decreases to 0

R (Running) The associated %MNi.R bit is at 1 if %MNi.V > 0

(monostable "elapsing") %MNi.R = 0 si %MNi.V = 0

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Advanced instructions

Monostable block function operation

General

Illustration

The monostable function block is used to generate a pulse of precise duration.

Timing diagram illustrating the monostable operation

(1) (1)

Input “start” S : S

(1) (1)

Current value

%MNi.V :

Output “running” R :

%MNi.P

%MNi.V

(3)

(2)

(3)

(2)

PRESET

(4)

PRESET (4)

(3)

(2) (2)

PRESET

(4)

Operation Description of monostable operation

Phase

Description

From the appearance of a rising edge on the monostable S input, the current value %MNi.V takes the preset value %MNi.P

The current value %MNi.V decreases to 0 by one unit at each pulse of the time base TB.

The output bit %MNi.R (Running) associated with the R output moves to state

1 when the current value %MNi.V is different from 0.

When the current value %MNi.V = 0, the output bit %MNi.R returns to state 0.

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Advanced instructions

Configuring and programming monostable function blocks

Example

Configuration

Programming

Flashing for variable cyclic periods: the preset value of each monostable defines the duration of each pulse.

%Q3.0

5s 5s

2s 2s l l l

The following parameters are to be entered in the variables editor:

TB: 1mn, 1s, 100ms, 10ms or 1 ms (100ms in this example)

%MNi.P: 0 à 9999 (%MN0.P = 50 et %MN1.P = 20 in this example

MODIF: Y or N

Ladder

%MN1.R

%Q3.0

%MN0

%MN0.R

%MN1

Instruction list language

LDN %MN1.R

S %MN0

LD %MN0.R

ST %Q3.0

LDN %MN0.R

S %MN1

Structured text language

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Observations

Specific cases

Advanced instructions

%M0:=NOT %MN1.R;

IF RE %M0 THEN

START %MN0 ;

END_IF;

%Q3.0:= %MN0.R

;

%M1:=NOT %MN0.R

;

IF RE %M1 THEN

START %MN1 ;

END_IF;

In the example below, the output %Q3.0 is set at state 1 for 5s (%MN0.P) and reset at state 0 for 2s (%MN1.P).

l l

In structured text language, the instruction START%MNi is used to initiate execution of the monostable function block. This instruction forces a rising edge on the S input of the block, which has the effect of resetting the function block.

Use of this instruction must therefore be pulse-based.

The monostable function may also be carried out by the %TMi function block in

TP mode (See

Operation of timer function block %TMi in TP mode, p. 37).

l l l l l

Incidence of a "cold restart" : (%S0 = 1) loads the preset value %MNi.P in the current value %MNi.V. Since the preset value, which may have been altered by the terminal, has been lost, the ouput %MNi.R is reset to 0.

Incidence of a "warm restart" : There is no incidence of (%S1) on the current value of the monostable (%MNi.V).

Incidence of a switch into stop mode, deactivation of the task and breakpoint : the switch of the PLC into stop mode does not freeze the current value. The same applies when the current task is deactivated or on execution of a breakpoint.

Incidence of a program jump : Not polling the network in which the monostable block is programmed does not freeze the current value %MNi.V which continues to decrease to 0. Similarly, the %MNi.R bit associated to the monostable block output maintains its normal operation and can thus be tested on another network.

However the spools which are directly connected to the block output (ex %Q3.0) are not activated since they are not examined by the PLC.

Test of %MNi.R bit : this bit can change state during its cycle.

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Advanced instructions

Introduction to Register function block

General

Illustration

A register is a memory block which is used to store up to 255 words of 16 bits in two l l different ways: queue (first in, first out) called FIFO stack (First In, First Out) queue (last in, first out) called the LIFO stack (Last In, First Out)

The following is the graphic presentation of the register function block:

%Ri

MODE:LIFO

LEN:16

Characteristics Characteristics of the Register function block:

Characteristic Address Value

Number

Mode

Length

%Ri 0 to 3 for a TSX 37, 0 to 254 for a TSX 57

FIFO LIFO Stack Queue (choice by default)

LEN Number of words of 16 bits (1< LEN< 255) making up the register memory block.

Input word

Output word

Input (or instruction)

"Store"

Input (or instruction)

"Destore"

%Ri.I

%Ri.O

I (In)

O (Out)

Access word for register. May be read, tested and written.

On a rising edge, causes an information word to be stored in the word %Ri.O

On a rising edge, causes the contents of the word %Ri.I to be stored

On a rising edge, causes an information word to be stored in the word %Ri.O

Input (or instruction)

"Resetting to zero"

R (Reset) At state 1, initiates the register

Output "Empty" E (Empty) E associated %Ri.E bit indicates that the register is empty.

May be tested.

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Advanced instructions

Characteristic Address

Output "Full" F (Full)

Value

The associated %Ri.F bit indicates that the register is full.

May be tested.

Note: When the two inputs I and O are activated simultaneously, storage is carried out before the destocking.

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Advanced instructions

Register function block operation in FIFO mode

General

Operation

In FIFO mode (First IN – First Out), the first information input in the register stack is the first output.

This table describes the operation of the FIFO mode

Step

Description

On a rising edge on the input I or on activation of instruction I, the content of the previously loaded input word %Ri.I is stored at the top of the

20 %Ri.I

20

80

60

50

stack. When the stack is full, loading is impossible and the system bit %S18 switches to 1.

On a rising edge on the input O or on activation of instruction O, the information word which is lowest in the queue is stored in the output word %Ri.O.

20

80

60

50 %Ri.O

50

3 Once the word has been transferred into

Ri.O, the contents of the register are shifted

80

down one step. When the register is empty

60 %Ri.O

50

(output E=1) destocking is impossible. The output word %Ri.O moves no more and maintains its value. The stack can be reset at any time (state 1 on input

R or activation of instruction R).

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Advanced instructions

Register function block operation in LIFO mode

General

Operation

In LIFO mode (Last In - First Out), the last information input in the register stack is the first output.

This table describes the operation of the LIFO mode

Step

Description

On a rising edge on the input I or on activation of instruction I, the contents of the previously loaded input word %Ri.I is stored at the top of the stack.

When the stack is full, loading is impossible and the system bit %S18 switches to 1.

20 %Ri.I

2 On input O rising edge or on instruction O activation, the information word which is highest in the stack (last input information) is stored in the output word %Ri.O.

20

80

50

As soon as the word is transferred into Ri.O, the following register word is available. When the register is empty (output E=1) destocking is impossible. The output word

%Ri.O moves no more and maintains its value. The stack

80

60

50

can be reset at any time (state

1 on input R or activation of instruction R).

20

80

60

50

20 %Ri.O

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Advanced instructions

Programming and configuring the Register block function

Example

Configuration

Programming

The following example shows the loading of %R2.I with the word %MW34 on request from input %I1.2, if the register R2 is not full (%R2.F=0). The input request to the register is assured by %M1. The output request is made by input %I1.3 and the storage of %R2.O in %MW20 is carried out if the register is not empty

(%R2.E=0).

The following parameters are to be entered in the configuration editor: l l

Number: 1 to 4 for a TSX 37, 1 to 255 for a TSX 57

Length: 1 to 255

The operation mode (FIFO or LIFO) is to be entered in the variables editor.

Ladder

%R2

%M1

%I1.3

%I1.3 %R2.E

%MW20:=%R2.O

%I1.2 %R2.F

%R2.I:=%MW34

%M1

Instruction list language

LD %M1

I %R2

LD %I1.3

O %R2

LD %I.3

ANDN %R2.E

[%MW20:= %R2.O

]

LD %I.2

ANDN %R2.F

[%R2.I:=%MW34]

ST %M1

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Advanced instructions

Note

Specific cases

Structured text language

IF RE %M1 THEN

PUT %R2 ;

END_IF;

IF RE %I1.3 THEN

GET %R2 ;

END_IF;

IF (%I1.3 AND NOT %R2.E

) THEN

%MW20:= %R2.O

;

END_IF;

%M1:=%I1.2 AND NOT %R2.F

;

IF %M1 THEN

%R2.I

:=%MW34;

END_IF;

In structured text language, 3 instructions are used to program the register function blocks: l l l

RESET

PUT

GET

%Ri: Initialize register

%Ri: Causes the content of word %R.I to be stored in the register.

%Ri: Causes an information word to be stored in word %Ri.O

The instructions PUT and GET create a rising edge, on the function block inputs I and O respectively. Use of this instruction must therefore be pulse-based l l l

Incidence of a "cold" restart : (%S0=1) initializes the contents of the register.

The output bit %Ri.E associated with the output E is set to 1.

Incidence of a "warm" restart : There is no incidence of (%S1=1) on the l l contents of the register, or on the status of the output bits.

On reset to 0 (input R or instruction R)

In ladder, the input I and O logs are updated with the wired values.

In instruction list language, the input I and O logs are not updated: each retains the value which it had before the call.

In structured text language, the input I and O logs are updated with 0.

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Advanced instructions

Introduction to the Cyclic Programmer (Drum) function block

General

Illustration

With a similar operating principle to the cam programmer, the cyclic programmer changes step according to external events. At each step, the upper point of a cam gives a command processed by the automatic operation In the case of a cyclic programmer, these upper points are symbolized by a state 1 at the level of each step and are assigned to the output bits %Qi.j or internal bits %Mi called the command bits.

Graphic representation of the Cyclic Programmer function block (Drum)

%DRi

%TB:1mn

LEN:16

Characteristics Characteristics of the cyclic programmer function block

Characteristic

Number

Number of steps

Time base

Time out or duration of current step

Address

%DRi

LEN

%DRi.V

Number of step in progress

%DRi.S

Input "return to step

R (RESET)

Input "advance" U (UP)

Value

0 to 7 for a TSX 37, 0 to 254 for a TSX 57

1 to 16 (16 by default).

1mn, 1s, 100ms, 10ms (1mn by default).

0 ≤ %DRi.V

≤ 9999 . Word which can be reset to zero at each change of step. May be read, tested but not written. The pulse period is equal to %DRi.V x TB

0 ≤ %Di.S

≤ 15 . Word which can be read and tested.

Can only be written from an immediate value.

At state 1, initialize the programmer at step 0

Output F (FULL)

On rising edge, causes the programmer to advance one step and the command bits to be updated.

Indicates that the last defined step is in progress. The associated %DRi.F bit can be tested (%DRi.F=1 if

%DRi.S=number of configured steps -1).

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Characteristic

Status of a step

Command bits

Address

%DRi.Wj

Advanced instructions

Value

16 bit word defining the status of step j of the programmer i. May be read, tested but not written.

Outputs or internal bits associated with the step (16 command bits)

Note: The %S18 bit switches to 1, if an unconfigured step is written.

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Advanced instructions

Cyclic Programmer (Drum) function block operation

General

Illustration

The cyclic programmer comprises: l a matrix of constant data (cams) organized in columns: in steps from 0 to N-1 (N being the number of configured steps), each column gives the status of the step l in the form of 16 pieces of binary information listed from 0 to F, a list of command bits (1 per line) corresponding to the outputs %Qxy.i or to the internal bits %Mi. When a step is in progress, the command bits take the binary status defined for this step.

The table below summarizes the main characteristics of the cyclic programmer

(programmer configured with 16 steps)

BIT

%DRO Nbr pas : 16

Step

0 1 2 3 4 5 6 7 8 9 10 11 12130 14 15

0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 %Q2.1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 %Q2.3

1 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 %Q3.5

0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 %M0

0 0 1 0 1 0 0 0 0 0 0 0 1 1 1 0 %M10

0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 %Q2.6

0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 %Q2.7

1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 %Q2.8

0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 %M20

0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 %M30

0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 %Q2.9

0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 %Q3.6

1 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 %M5

1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 %M6

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 %M7

Address

Control Bits

OK Cancel

In the example below, for step 1, the command bits %Q2.1;%Q3.5

;%Q2.8;%Q3.6;%M5 and %M6 are set at state 1; the other command bits are set at

Diagram of operation

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Advanced instructions

Input

No. not %DRi.S

0 1 2 3

Output %DRi.F

Time envelope

%DRi.V

N-1 0 1 2 0 1

The number of the step in progress is incremented at each rising edge on the input

U (or activation of instruction U). This number may be modified by program.

Advanced instructions

Programming and configuring the cyclic programmer function block (Drum)

Example

Configuration

In this example, the first 5 outputs from %Q2.0 to %Q2.4 are activated one after the other, each time the input %I1.1 is set to 1. The input I1.0 resets the outputs at step

l l l

The following information is defined in the variables editor: number of steps: (LEN:5), time base (TB: 1mn), state of outputs (command bits) for each step of the programmer.

Step:

0 1 2 3 4

0 : 1 0 0 0 0 %Q2.0

1 : 0 1 0 0 0 %Q2.1

Bits : 2 : 0 0 1 0 0 %Q2.2

3 : 0 0 0 1 0 %Q2.3

4 : 0 0 0 0 1 %Q2.4

Programming Ladder language

%I1.0

%I1.1

%DR1

%TB:1mn

LEN:5

%Q2.8

Instruction list language

LD %I1.0

R %DR1

LD %I1.1

U %DR1

LD %DR1.F

ST %Q2.8

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Advanced instructions

Observations

Structured text language

IF %I1.0 THEN

RESET %DR1 ;

END_IF;

IF RE %I1.1 THEN

UP %DR1 ;

END_IF;

%Q2.8:= %DR1.F

; l l

In structured text language, 2 instructions are used to program the cyclic programmer function blocks:

RESET %DRi: Initialize the programmer to step 0,

UP %DRi: Causes the programmer to advance one step and the command bits to be updated. This instruction creates a rising edge on the function block input

U; its use must therefore be pulse-based.

l l

Note: On reset to 0 (input R, instruction R or instruction RESET):

In ladder language, the input U archive is updated with the connected values.

In instruction list language, the input U archive is not updated; it retains the values it had before the call.

l In structured text language, the U archive is updated with 0.

Specific cases l l l l

Incidence of a "cold restart": (%S0=1) resets the programmer to step 0 (and updates the command bits).

Incidence of a "warm restart": (%S1=1) resets the command bits, according to the step which is in progress.

Incidence of a program jump, deactivation of the task and breakpoint: not polling the cyclic programmer does not cause the command bits to reset to 0.

The command bits : are only updated when the step changes or on a warm or cold restart.

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Advanced instructions

Introduction to Timer function block series 7

General

Illustration

This timer function block which is compatible with blocks of series 7 PL7-2/3 is used to give timed commands for specific actions. This value of this time delay is programmable and can be modified if necessary by the terminal.

Graphic representation of the timer function block series 7

%Ti

TB : 1mn

T.P:9999

MODIF:Y

Characteristics

Characteristic

Number

Time base

Current value

Preset value

Characteristics of the timer function block series 7

Address

%Ti

%Ti.V

%Ti.P

MODIF modification Y/N

Input "Activation"

Input "Control"

Output "Timer cycle complete"

E(Enable)

C(Control)

D(Done)

R(Running)

Value

0 to 63 for a TSX 37, 0 to 254 for a TSX 57

1min, 1s, 100ms, 10ms (1mn by default)

Word which decreases from %Ti.P to 0 on completion of the timer cycle. May be read, tested but not written.

≤

%Ti.P

≤

9999 . Word which can be read, tested and written. Is set at the value of 9999 by default. The pulse period is equal to %Ti.P x TB.

l l

Y: possibility to modify the preset value in adjust mode.

N: cannot be accessed in adjust mode.

At state 0, reset the timer %Ti.V = %Ti.P.

At state 0, freeze the current value %Ti.V.

The associated bit %Ti.D = 1, if the timer cycle is complete %Ti.V = 0.

The associated bit %Ti.R = 1, if the timer %Ti.P > %Ti.V > 0 and if input C is at state 1.

Note: The function blocks %Ti are not programmable in an instruction list; however the block items %Ti

(%Ti.V, %Ti.P, %Ti.D and %Ti.R) can be accessed. The total number of %Tmi + %Ti must be less than

64 on the TSX 37 and 255 on the TSX 57.

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Advanced instructions

Timer function block series 7 operation

General

Illustration

Operation

The timer runs when its 2 inputs (E and C) are at state 1. It works as a down counter

Diagram of operation of the series 7 timer

%Ti.P

%Ti.V

%Ti.D

%Ti.R

%Ti.V

%Ti.P

%Ti.D

%Ti.V

%Ti.P

%Ti.V

%Ti.P

%Ti.R

0 1

1 1

0 1

%Ti.V

frozen

%Ti.V

fall in

%Ti.P -> 0

0 1 if Time elapsed

0 1 if Time in progress

Description of operation

Phase

Description

The current value %Ti.V decreases by one unit from the preset value %Ti.P to

0 at each pulse of the time base TB.

The output bit %Ti.R (Timer in progress) associated with the R output is then at state 1, the output bit %Ti.D (Timer cycle complete) associated with the D output is at state 0,

When the current value %Ti.V=0, %Ti.D changes to state 1 and %Ti.R returns to state 0.

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Advanced instructions

Instructions l l l

In structured text language, 3 instructions are used to program the timer function blocks %Ti

PRESET %Ti: Resets the timer

START %Ti: Starts the timer cycle

STOP %Ti: Freezes the current value of the timer

100

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Programming the series 7 timer in "Delay on engagement" mode

Advanced instructions

General

Illustration

The "Timer" function block can carry out different functions, according to how it has been programmed. The "delay on engagement" function is described here

Diagram of operation of the "delay on engagement" function

%I1.0 = E, C

D = %Q2.0

PRESET PRESET

Programming Programming in ladder language

%I1.0

%T0

TB : 1mn

%Ti.P=3

MOD:N

%Q2.0

Programming in structured text language

IF %I1.0 THEN

START %T0 ;

ELSE

PRESET %T0 ;

END_IF;

%Q2.0:= %T0.D

;

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101

Advanced instructions

Programming the series 7 timer in "Delay on release" mode

General

Illustration

The "Timer" function block can carry out different functions, according to how it has been programmed. The "delay on release" function is described here.

Diagram of operation of the "delay on release" function

%I1.1

E, C

PRESET

%Q2.1

Programming Programming in ladder language

%I1.1

%T7

TB : 1s

%Ti.P=120

MOD:N

%Q2.1

Programming in structured text language

IF %I1.1 THEN

PRESET %T7 ;

ELSE

START %T7 ;

END_IF;

%Q2.1:=NOT %T7.D

;

102

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Advanced instructions

Programming the series 7 timer in "Delay accumulated on engagement" mode

General

Illustration

The "Timer" function block can carry out different functions, according to how it has been programmed. The "delay accumulated on engagement" function is described here.

Diagram of operation of the "delay accumulated on engagement" function

%I1.2 = E

%I1.3 = C

%Q2.5 = R

D1 D2 D3

%Q2.4 = D

Programming

PRESET = D1+D2+D3

Programming in language data

%I1.2

%I1.3

%T5

TB : 1mn

%Ti.P=3

MOD:N

%Q2.1

%Q2.5

Programming in structured text language

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103

Advanced instructions

IF %I1.2 THEN

IF %I1.3 THEN

START %T5 ;

ELSE

STOP %T5 ;

END_IF;

ELSE

PRESET %T5 ;

END_IF;

%Q2.4:= %T5.D

;

%Q2.5:= %T5.R

;

104

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Advanced instructions

Programming the series 7 timer in "Delay accumulated on release" mode

General

Illustration

The "Timer" function block can carry out different functions, according to how it has been programmed. The "delay accumulated on release" function is described here.

Diagram of operation of the "delay accumulated on release" function

%I1.0

%I1.1

%Q2.1

D1 D2 D3

PRESET = D1+D2+D3

Programming Programming in language data

%I1.0

%I1.1

%T12

TB : 10mn

%Ti.P=40

MOD:Y

%Q2.4

Programming in structured text language

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105

Advanced instructions

IF %I1.0 THEN

PRESET %T12 ;

ELSE

IF %I1.1 THEN

STOP %T12 ;

ELSE

START %T12 ;

END_IF;

%Q2.4:=NOT %T12.D

;

106

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Advanced instructions

Introduction to the vertical comparison operation block

General

Illustration

The vertical comparison block is used to compare 2 operands (OP). These 2 operands are words of 16 possibly indexed bits, or words of immediate value.

The number of vertical comparison blocks is not limited and is not enumerated.

Graphic representation of the vertical comparison operation block

COMPARE

OP1

OP2 <

Characteristics Characteristics of the vertical comparison operation block

Characteristic

Command input

Output "Greater"

Output "Equal"

Output "Less"

Output "Different"

Operand number 1

Operand number 2

Address Value

EN At state 1, compares the two operands.

> Is at state 1 if the content of the OP1 is greater than that of

OP2.

OP1

OP2

Is at state 1 if the content of the OP1 is equal to that of OP2.

Is at state 1 if the content of the OP1 is less than that of

OP2.

Is at state 1 if the content of the OP1 is different from that of OP2.

This operand is a single length word object (it may be indexed).

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107

Advanced instructions

Operation of vertical comparison operation block

Operation

Example

Setting the command input to 1 compares the two operands; the four outputs are activated according to the result of the comparison. Setting the command input to 0 sets the activated outputs to zero.

The program below shows the comparison of the word %MW2 indexed by the word

%MW40 and of the immediate value of 150. In this case where the content of

%MW2[%MW40] is greater than 150 and if %I1.3 = 1, spool %Q2.7 is commanded.

If the content is equal to 150, spool %MW10:X4 is commanded. Spool %M5 is only controlled if the content is different from 150 (< or >).

Ladder language

EN >

%I1.3

%Q2.7

%MW10:X4

%MW2

[%MW40]

150

%M5

Note: This function block does not exist in instruction list language or in structured text language. Use the comparison operations >, <, =, <>.

Specific cases l l

Incidence of a "cold" restart: (%S0) resets the operand OP1 and possibly OP2

(if OP2 is an internal word) to zero, the outputs are activated according to the comparsion with the new values.

Incidence of a "warm" restart: There is no incidence of (%S1) on the comparison block.

108

TLX DR PL7 xxE

2.2