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User Guide CCG-RUMBA • Core
TM
2 Duo 3U CompactPCI
®
CPU Board
Main Memory
The CCG-RUMBA is equipped with two sockets for installing 200-pin SO-DIMM modules (module height = 1.25 inch). Supported are unbuffered DDR2 SO-DIMMs (V
CC
=1.8V) without ECC featuring on-die termination (ODT), according the PC2-4200 or PC2-5300 specification. Minimum memory size is 128MB; maximum memory size is 4GB. Due to the video requirements of the GME965 chipset, a minimum of 2x512MB of memory is recommended for the operating systems Windows 2000,
Windows XP or Windows Vista (some of the system memory is dedicated to the graphics controller).
The contents of the SPD EEPROM on the SO-DIMMs is used by the BIOS at POST (Power-on Self Test) to program the memory controller within the chipset.
The GME965 chipset supports symmetric and asymmetric memory organization. The maximum memory performance can be obtained by using the symmetric mode. When in this mode, the GMCH accesses the memory sockets in an interleaved way. Since the GME965 supports Intels Flex Memory
Technology, interleaved operation isn't limited to systems using two SO-DIMMs of equal capacity. In the case of unequal memory population the smaller SO-DIMM dictates the address space of the interleaved accessible memory region. The remainder of the memory is then accessed in noninterleaved mode.
In asymmetric mode the SO-DIMMs always will be accessed in a non-interleaved manner with the drawback of less bandwidth. The only meaningful application of asymmetric mode is the special case when only one SO-DIMM socket is populated (i.e. one socket may be left empty). In order to operate
AMT, SO-DIMM socket 1 should be stuffed then.
C
C
C
C
C
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LAN Subsystem
The Ethernet LAN subsystem is composed of two Gigabit Ethernet ports: One Intel 82566 physical layer Transceiver (PHY) using the ICH8 internal MAC and one Intel 82573 Gigabit Ethernet controller.
These devices provide also legacy 10Base-T and 100Base-TX connectivity. The Ethernet ports are fed to two RJ45 jacks located in the front panel. Each port includes the following features:
One PCI Express lane per Ethernet port (250MB/s)
1000Base-Tx (Gigabit Ethernet), 100Base-TX (Fast Ethernet) and 10Base-T (Classic Ethernet) capability.
Half- or full-duplex operation.
IEEE 802.3u Auto-Negotiation for the fastest available connection.
Jumperless configuration (complete software-configurable).
Two bicoloured LEDs integrated into the dedicated RJ-45 connector to signal the LAN link, the
LAN connection speed and activity status.
Each device is connected by a single PCI Express lane to the chipset (ICH8). Their MAC addresses
(unique hardware number) are stored in dedicated FLASH/EEPROM components. The Intel Ethernet software and drivers for the 82566 and 82573 is available from Intel's World Wide Web site for download.
When managing the board by Intel Active Management Technology (AMT), the dedicated network port to do so is accessible by the RJ45 connector GbE1.
© EKF -23- ekf.com
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Table of contents
- 4 About this Manual
- 4 Edition History
- 4 Legal Disclaimer - Liability Exclusion
- 4 Trade Marks
- 5 Related Documents
- 6 CCG-RUMBA Features
- 6 Feature Summary
- 11 Short Description
- 13 Block Diagram
- 14 Top/Bottom View Component Assembly
- 17 Rear I/O Transition Module CCT-RIO
- 20 Strapping Headers
- 20 Connectors & Sockets
- 20 Front Panel Elements
- 21 Microprocessor
- 21 Thermal Considerations
- 23 Main Memory
- 23 LAN Subsystem
- 24 Serial ATA Interface (SATA)
- 24 Enhanced IDE Interface
- 24 Graphics Subsystem
- 25 Real-Time Clock
- 26 Universal Serial Bus (USB)
- 26 LPC Super-I/O Interface
- 26 SPI Flash
- 27 Reset
- 29 Watchdog
- 30 PG (Power Good) LED
- 30 HD (Hard Disk Activity) LED
- 30 GP (General Purpose) LED
- 31 Hot Swap Detection
- 31 Power Supply Status (DEG#, FAL#)
- 31 PXI Trigger Signals
- 32 Rear I/O Options
- 33 Installing and Replacing Components
- 33 Before You Begin
- 34 Installing the Board
- 35 Removing the Board
- 36 EMC Recommendations
- 37 Installing or Replacing the Memory Modules
- 37 Replacement of the Battery
- 38 Technical Reference
- 38 Local PCI Devices
- 39 Local SMB Devices
- 40 Hardware Monitor LM
- 41 GPIO Usage
- 41 GPIO Usage ICH
- 43 GPIO Usage SIO
- 44 Configuration Jumpers
- 44 Reset Jumper BIOS CMOS RAM Values (JGP)
- 44 Reset Jumper ICH8 RTC Core (JRTC)
- 45 Connectors
- 45 Front Panel Connectors
- 46 Video Monitor Connector DVI-I
- 47 Video Monitor Connector VGA
- 47 USB Connectors
- 48 Ethernet Connectors
- 49 Internal Connectors
- 58 Expansion Interface Header PEXP
- 59 ATA/IDE Header PIDE
- 60 PCI Express Expansion Header PPCIE
- 61 SDVO Expansion Header PSDVO
- 61 System Reset Header JRST
- 62 PLD Programming Header ISPCON
- 62 Processor Debug Header PITP
- 63 CompactPCI J
- 66 Literature
- 67 Appendix
- 67 Mechanical Drawings
- 68 Mass Storage Considerations
- 73 Coating
- 75 Sample Applications