Getting Started with Linux Application Debugging. Altera SoC Embedded Design Suite

The Altera® SoC Embedded Design Suite (EDS) is a comprehensive tool suite for embedded software development on Altera SoC devices. The Altera SoC EDS contains development tools, utility programs, run-time software, and application examples that enable firmware and application software development on the Altera SoC hardware platform.

PDF
Document
Altera SoC Embedded Design Suite User Guide | Manualzz

Advertisement

Advertisement

/

Advertisement

Key features

  • ARM Development Studio 5 (DS-5™) Altera Edition Toolkit

  • Bare-metal GNU Compiler Collection (GCC) tool chain

  • Linux GCC compiler tool chain

  • Pre-built Linux package

  • SoC Hardware Library (HWLIB)

  • Preloader generator

  • Device tree generator

  • Sample applications

  • Golden Hardware Reference Design (GHRD)

  • Embedded command shell

Frequently asked questions

The major components of the SoC EDS include: ARM® Development Studio 5 (DS-5™) Altera Edition Toolkit, Compiler tool chains: Bare-metal GNU Compiler Collection (GCC) tool chain from Mentor Graphics®, Linux GCC compiler tool chain from Linaro, Pre-built Linux package including: Linux kernel executable, Linux kernel U-boot image, Device tree blob, Secure Digital (SD) card image, Script to download Linux source code from the Git tree on the Rocketboards website (www.rocketboards.org). The script downloads the sources corresponding to the pre-built Linux package, SoC Hardware Library (HWLIB), Hardware-to-software interface utilities: Preloader generator, Device tree generator, Sample applications, Golden Hardware Reference Design (GHRD) including: FPGA hardware project, FPGA hardware SOF file, Precompiled preloader, Embedded command shell, allowing easy invocation of the included tools, Yocto Eclipse plugin, Quartus II Programmer and SignalTap II.

There are two device tree binary (DTB) files delivered as part of SoC EDS: /embeddedsw/socfpga/prebuilt_images/socfpga_cyclone5.dtb. This is a generic DTB file which does not have any dependency on soft IP. FPGA programming and bridge releasing are not required before Linux starts running using this DTB. This bare bones DTB is intended for customers interested in bringing up a new board or just wanting to simplify their boot flow until they get to the Linux prompt. If what is being developed or debugged does not involve the FPGA, it's better to remove the FPGA complexities. /examples/hardware/cv_soc_devkit_ghrd/soc_system.dtb. This DTB is based on Golden Hardware Reference Design (GHRD) design, which is part of the GSRD (Golden System Reference Design). As the GHRD does contain soft IPs, this DTB will notify Linux to load the soft IPs drivers. Therefore, the FPGA needs to be programmed and the bridges released before booting Linux.

Depending on your role in hardware or software development, you need a different subset of the SoC EDS toolkit. The following table lists some typical engineering development roles, and indicates which tools each role typically requires.

Preparing document for printing…
0%