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Debugging
Figure 6-3: Eclipse IDE - build process invoked
6. If the compilation tools issue errors, Eclipse parses and formats them for you.
Debugging
ARM DS-5 AE offers you a variety of debugging features.
The settings for a debugging session are stored in a Debug Configuration. The Debug Configurations window is accessible from the Run > Debug Configurations menu.
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Figure 6-4: Accessing Debug Configurations
Debugging
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A Debug Configuration is created in the Debug Configurations window by selecting DS-5 Debugger as the type of configuration in the left panel and then right-click and select the New menu option.
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Debugging
Figure 6-5: Creating a Debug Configuration
The Eclipse IDE assigns a default name to the configuration, which can then be edited by you.
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Figure 6-6: Naming your Configuration
Debug Configuration Options
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Debug Configuration Options
This section lists the Debug Configuration options, which allows you to specify the desired debugging options for a project.
Refer to the DS-5 reference documentation for the complete details.
Refer to the
Getting Started Guides
for concrete examples on how to use the debugging features of ARM
DS-5 Altera Edition.
Connection Options
The Connection tab offers the following configurable options:
• Target – specifies which target to use
• DTSL Options – specifies the Debugger and (described in detail in another section)
• Connections – specifies the way to connect to the target
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Debug Configuration Options
Figure 6-7: Debug Configurations - Connection
The following Target Types are available:
• Bare Metal Debug – select this to debug bare metal applications
• Linux Application Debug – select this to debug Linux applications
• Linux Kernel and/or Device Driver Debug – select this to debug the Linux kernel and Linux device drivers
For the Bare Metal Debug and Linux Kernel and/or Device Driver Debug target types, the following different scenarios are available:
• Debug Cortex-A9_0 via Altera USB-Blaster
• Debug Cortex-A9_0 via DSTREAM/RVI
• Debug Cortex-A9_1 via Altera USB-Blaster
• Debug Cortex-A9_1 via DSTREAM/RVI
• Debug Cortex-A9x2 SMP via Altera USB-Blaster
• Debug Cortex-A9x2 SMP via DSTREAM/RVI
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Debug Configuration Options
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For Linux Application Debug option, the following different scenarios are available:
• Connect to already running GDB server
• Download and debug application
• Start gdbserver and debug target resident application
The Connections panel allows the user to specify the connection to be used to communicate to the board.
Depending on the Target type and the selected scenario, the Connections panel will look different:
• For Bare Metal Debug and Linux Kernel and/or Device Driver Debug target types, a Browse button appears and it allows the user to browse and select either the Altera USB-Blaster or the DSTREAM instances.
• For the Linux Application Debug, the Connection needs to be configured in the Remote System Explorer view
File Options
The Files tab allows the following settings to be configured:
• Application on host to download – the file name of the application to be downloaded to the target. It can be entered directly in the edit box or it can be browsed for in the Workspace or on the File System.
• Files – contains a set of files. A file can be added to the set using the “+” button, and files can be removed from the set using the “–“ button. Each file can be one of the following two types:
• Load symbols from file – the debugger uses that file to load symbols from it
• Add peripheral description files from directory – the debugger to load peripheral register descriptions from the SVD files stored in that directory. The SVD file is a result of the compilation of the hardware project.
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Debug Configuration Options
Figure 6-8: Debug Configurations - File options
Debugger Options
The Debugger tab offers the following configurable options
• Run Control Options
• Option to connect only, debug from entry point or debug from user-defined symbol
• Option to run user-specified target initialization script
• Option to run user-specified debug initialization script
• Option to execute user-defined debugger commands
• Host working directory – used by semihosting
• Paths – allows you to enter multiple paths for the debugger to search for sources. Paths can be added with “+” button and removed with “-" button.
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Figure 6-9: Debug Configurations - Debugger
Debug Configuration Options
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RTOS Awareness
The RTOS Awareness tab allows you to enable Keil CMSIS-RTOS RTX awareness for the debugger in case that specific RTOS is used.
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Debug Configuration Options
Figure 6-10: Debug Configurations - RTOS Awareness
Arguments
The Arguments tab allows you to enter program arguments as text.
Figure 6-11: Debug Configurations - Arguments
Environment
The Environment tab allows you to enter environment variables for the program to be executed.
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Figure 6-12: Debug Configurations - Environment
Debug Configuration Options
6-13
Event Viewer
The Event Viewer allows you to enable and configure the event views for the STM (System Trace Macrocell) and ITM (Instrumentation Trace Macrocell).
The SoC FPGA does not have an ITM, so only STM can be enabled. When STM Viewer is enabled, the size of the trace depth is also configured.
Figure 6-13: Debug Configurations - Event Viewer
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DTSL Options
DTSL Options
The tracing options are configured from the DTSL Configuration window accessible from the Debug
Configuration window by pressing the Edit button. DTSL represents Debug and Trace Services Layer.
Figure 6-14: Debug Configurations - DTSL Options - Edit
Cross Trigger Settings
The Cross Trigger tab allows the configuration of the cross triggering option of the SoC FPGA.
The following options are available:
• Enable FPGA > HPS Cross Trigger – for enabling triggers coming from FPGA to HPS
• Enable HPS > FPGA Cross Trigger – for enabling triggers coming from HPS to FPGA
• Assume Cross Triggers can be accessed – the user needs to select this option as a confirmation that the
Preloader was already loaded, so the DS-5 can access the cross triggering interface.
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Figure 6-15: DTSL Configuration Editor - Cross Trigger
DTSL Options
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Trace Buffer Settings
The Trace Buffer tab allows the selection of the destination of the trace information. As mentioned in the introduction, the destination can be one the following:
• None – meaning the tracing is disabled
• ETR – using any memory buffer accessible by HPS
• ETF – using the 32KB on-chip trace buffer
• DSTREAM – using the 4GB buffer located in the DSTREAM
The DSTREAM option is available only if the Target connection is selected as DSTREAM in the Debug
Configuration.
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DTSL Options
Figure 6-16: DTSL Configuration Editor - Trace Buffer
The Trace Buffer tab provides the option of selecting the timestamp frequency.
Figure 6-17: DTSL Configuration Editor - Trace Buffer
Cortex-A9 Settings
The Cortex-A9 tab allows the selection of the desired core tracing options.
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Figure 6-18: DTSL Configuration Editor - Cortex-A9
DTSL Options
6-17
The following Core Tracing Options are available:
• Enable Cortex-A9 0 core trace – check to enable tracing for core #0
• Enable Cortex-A9 1 core trace – check to enable tracing for core #1
• PTM Triggers halt execution – check to cause the execution to halt when tracing
• Enable PTM Timestamps – check to enable time stamping
• Enable PMT Context IDs – check to enable the context IDs to be traced
• Context ID Size – select 8, 16 or 32bit context IDs. Used only if Context IDs are enabled
• Cycle Accurate – check to create cycle accurate tracing
• Trace capture range – check to enable tracing only a certain address interval
• Start Address, End Address – define the tracing address interval (Used only if the Trace Capture Range is enabled)
STM Settings
The STM tab allows you to configure the STM (System Trace Macrocell).
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DTSL Options
Figure 6-19: DTSL Configuration Editor - STM
Only one option is available:
• Enable STM Trace – check to enable STM tracing.
ETR Settings
The ETR settings allow the configuration of the ETR (Embedded Trace Router) settings.
The Embedded Trace Router is used to direct the tracing information to a memory buffer accessible by HPS.
Figure 6-20: DTSL Configuration Editor - ETR
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DTSL Options
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The following options are available:
• Configure the system memory trace buffer – check this if the ETR was selected as the trace destination on the Trace Buffer tab
• Start Address, Size – define the trace buffer location in system memory, and its size
• Enable scatter-gather mode – used when the OS cannot guarantee a contiguous piece of physical memory.
The scatter-gather table is setup by the operating system using a device driver, and is read automatically by the ETR.
ETF Settings
The ETF tab allows the configuration of the ETF (Embedded Trace FIFO) settings.
The Embedded Trace FIFO is a 32KB buffer residing on HPS that can be used to store tracing data to be retrieved by the debugger, but also as an elastic buffer for the scenarios where the tracing data is stored in memory through ETR or on the external DSTREAM device using TPIU.
Figure 6-21: DTSL Configuration Editor - ETF
The following options are available:
• Configure the on-chip trace buffer – check this if ETF was selected as the trace destination on the Trace
Buffer tab.
• Size – define the ETF size. By default it is set up to 0x1000 (4KB) but it can be set to 0x8000 (32KB) to match the actual buffer size.
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Embedded Command Shell
Subscribe Send Feedback
The Embedded Command Shell enables the user to invoke the SoC EDS tools without qualifying them with the full path. That is, commands like ‘eclipse’ or ‘ bsp-editor
’ or ‘ arm-none-eabi-gcc
’ can be executed directly.
On Windows, the Embedded Command Shell is started by running <SoC EDS installation directory>
\
Embedded_Command_Shell.bat
.
On Linux, the Embedded Command Shell is started from the Start menu or by running <SoC EDS
installation directory>
/embedded_command_shell.sh
.
7
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