SYS68K/CPU-44

CPU-44 Technical Manual

If the test fails, there is normally something wrong with the NVRB(0:3) signals.

Display: 5 Subvalue: 3

If this test fails, there is normally something wrong with the addressing of the DRAM. Inspect

VRAD(2:8), RA(8:10) and IA(23:24). Also there may be something wrong with bank 1 of the DRAM (if present).

8.3.7

VMEbus Address Decoder

Display: 6 Subvalue: 0

Since the VMEbus decoders can't be read back, this test only fails if an exception occurs.

8.3.8

Access to Video Controller

Display: 7 Subvalue: 0

If the first access to the video controller ends in a bus error, it is assumed that the board has no graphic interface and none of the following graphic tests is performed. The board then uses the serial port for I/O.

8.3.9

Test of CLUT

Display: 7 Subvalue: 1

The CLUT of the video controller is written with random values and then read back. If the values are not the same, the test is repeated. This tests the data and address lines to the video controller MPAD(0:23).

Note that the CLUT registers are only 24 bits wide. A microport write cycle roughly runs in the following order:

• the CPU writes to the CLUT

• the IOC-2 generates /GSEL and /IOAS

• address decoder U1808 generates /MPSEL

• the microport arbiter in U1801 generates /BGMICRO when Ul302 has driven PBMS low and no transfer cycle is running or pending

• U1001 and U1003 drive the address to MPAD(2:11)

• U1202 generates/CSVCNTR

• U1201 asserts VIDCWT as long as the write is in progress

• U1001 and U1002 drive the data to MPAD(0:23)

• U1202 asserts NVEVCNTR

• U1201 de-asserts VIDCWT and U1202 asserts /DSACK(0:1)

Read cycles are very similar to write cycles. The main difference is that /OEVCNTR is used instead of

N~EVCNTR and that the direction of the data buffers is reversed.

FORCE COMPUTERS 049-13856-101 Rev A1 Page 8-13