Vivado Design Suite Reference Guide: Model-Based DSP

Chapter 1: Xilinx Blockset

Reset Generator

This block is listed in the following Xilinx Blockset libraries: Basic Elements and Index.

The Reset Generator block captures the user's reset signal that is running at the system sample rate, and produces one or more downsampled reset signal(s) running at the rates specified on the block.

The downsampled reset signals are synchronized in the same way as they are during startup. The RDY output signal indicates when the downsampled resets are no longer asserted after the input reset is detected.

Block Parameters

The block parameters dialog box shown below can be invoked by double-clicking the icon in your Simulink model.

You specify the design sample rates in MATLAB vector format as shown above. Any number of outputs can be specified.

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Chapter 1: Xilinx Blockset

ROM

This block is listed in the following Xilinx Blockset libraries: Control Logic, Memory,

Floating-Point and Index.

The Xilinx ROM block is a single port read-only memory (ROM).

Values are stored by word and all words have the same arithmetic type, width, and binary point position. Each word is associated with exactly one address. An address can be any unsigned fixed-point integer from 0 to d-1, where d denotes the ROM depth (number of words). The memory contents are specified through a block parameter. The block has one input port for the memory address and one output port for data out. The address port must be an unsigned fixed- point integer. The block has two possible Xilinx LogiCORE™ implementations, using either distributed or block memory.

Block Parameters

The block parameters dialog box can be invoked by double-clicking the icon in your

Simulink model.

Basic tab

Parameters specific to the Basic tab are as follows:

• Depth: specifies the number of words stored; must be a positive integer.

• Initial value vector: specifies the initial value. When the vector is longer than the ROM depth, the vector's trailing elements are discarded. When the ROM is deeper than the vector length, the ROM's trailing words are set to zero. The initial value vector is saturated or rounded according to the data precision specified for the ROM.

• Memory Type: specifies block implementation to be distributed RAM or Block RAM.

• Provide reset port for output register: when selected, allows access to the reset port available on the output register of the Block ROM. The reset port is available only when the latency of the Block ROM is set to 1.

• Initial value for output register: specifies the initial value for output register. The initial value is saturated and rounded according to the data precision specified for the

ROM.

Output

• Specifies the data type of the output. Can be Boolean, Fixed-point, or Floating-point.

Arithmetic Type: If the Output Type is specified as Fixed-point, you can select Signed

(2’s comp) or Unsigned as the Arithmetic Type.

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Chapter 1: Xilinx Blockset

Fixed-point Precision

°

Number of bits: specifies the bit location of the binary point of the output number, where bit zero is the least significant bit.

Binary point: position of the binary point. in the fixed-point output

°

Floating-point Precision

- Single: Specifies single precision (32 bits)

- Double: Specifies double precision (64 bits)

- Custom: Activates the field below so you can specify the Exponent width and the Fraction width.

Exponent width: Specify the exponent width

°

Fraction width: Specify the fraction width

Other parameters used by this block are explained in the topic

Common Options in Block Parameter Dialog Boxes

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LogiCORE™ Documentation

LogiCORE IP Block Memory Generator v8.2

LogiCORE IP Distributed Memory Generator v8.0

For the block memory, the address width must be equal to ceil(log2(d)) where d denotes the memory depth. The maximum width of data words in the block memory depends on the depth specified; the maximum depth is depends on the device family targeted. The tables below provide the maximum data word width for a given block memory depth.

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