phyCORE-Vybrid Hardware Manual

Part II, Chapter 26: Tamper

26 Tamper

L-783e_0

Fig. 26-1. Tamper

The phyCORE-Vybrid provides access to two passive (TAMPER[1:0]) and two active (TAMPER[3:2]) tamper detection signals from the VFx00. Security violations from the VFx00 tamper detection mechanism can be enabled to be a source of reset.

In addition to routing all four of these signals to the GPIO Expansion Connector, the phyCORE-Vybrid

Carrier Board provides test pads TP3 and TP4 on the TAMPER[1:0] signals and jumper JP19 across the

TAMPER[3:2] signals.

JP19 allows testing of the Vybrid's Tamper2/Tamper3 active physical tamper security circuit.

Table 26-1. Tamper Signals at Connector X21

Pin#

D10

D11

D12

D13

Signal

EXT_TAMPER0

EXT_TAMPER1

EXT_TAMPER2

EXT_TAMPER3

Type

IN

IN

IO

IO

SL

3.3 V

3.3 V

3.3 V

3.3 V

Connects to

Test-point TP3

Test-point TP4

Jumper JP19.1

Jumper JP19.2

© PHYTEC America LLC 2012 68