UG526

Chapter 1: SP605 Evaluation Board

I/O Voltage Rails

There are four available banks on the XC6SLX45T-3FGG484 device. Banks 0, 1, and 2 are connected for 2.5V I/O. Bank 3 is used for the 1.5V DDR3 component memory interface of

Spartan-6 FPGA’s hard memory controller. The voltage applied to the FPGA I/O banks used by the SP605 board is summarized in

Table 1-2 .

Table 1-2:

I/O Voltage Rail of FPGA Banks

FPGA Bank

0

I/O Voltage Rail

2.5V

1

2

3

2.5V

2.5V

1.5V

References

See the Xilinx Spartan-6 FPGA documentation for more information at http://www.xilinx.com/support/documentation/spartan-6.htm

.

2. 128 MB DDR3 Component Memory

There are 128 MB of DDR3 memory available on the SP605 board. A 1-Gb Micron

MT41J64M16LA-187E (96-ball) DDR3 memory component is accessible through Bank 3 of the LX45T device. The Spartan-6 FPGA hard memory controller is used for data transfer across the DDR3 memory interface’s 16-bit data path using SSTL15 signaling. The SP605 board supports the “standard” VCCINT setting of 1.20V ± 5%. This setting provides memory controller block (MCB) performance of 667 MT/s for DDR3 memory. Signal integrity is maintained through DDR3 resistor terminations and memory on-die terminations (ODT), as shown in

Table 1-3 and

Table 1-4

.

Table 1-3:

Termination Resistor Requirements

Signal Name On-Die Termination

MEM1_A[14:0]

MEM1_BA[2:0]

MEM1_RAS_N

MEM1_CAS_N

MEM1_WE_N

MEM1_CS_N

MEM1_CKE

MEM1_ODT

MEM1_DQ[15:0]

Board Termination

49.9

Ω to V

TT

49.9

Ω to V

TT

49.9

Ω to V

TT

49.9

Ω to V

TT

49.9

Ω to V

TT

100

Ω to GND

4.7 K

Ω to GND

4.7 K

Ω to GND

–

–

–

–

–

ODT

–

–

–

–

MEM1_UDQS[P,N], MEM1_LDQS[P,N]

MEM1_UDM, MEM1_LDM

–

–

ODT

ODT

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SP605 Hardware User Guide

UG526 (v1.8) September 24, 2012

Detailed Description

Table 1-3:

Termination Resistor Requirements (Cont’d)

MEM1_CK[P,N]

Signal Name Board Termination

100

Ω differential at memory component

On-Die Termination

–

Notes:

1. Nominal value of V

TT

for DDR3 interface is 0.75V.

Table 1-4:

FPGA On-Chip (OCT) Termination External Resistor Requirements

U1 FPGA Pin FPGA Pin Number Board Connection for OCT

ZIO

RZQ

M7

K7

No Connect

100

Ω to GROUND

Table 1-5 shows the connections and pin numbers for the DDR3 Component Memory.

Table 1-5:

DDR3 Component Memory Connections

U1 FPGA

Pin

Schematic Net Name

Pin Number

Memory U42

Pin Name

F1

J6

H5

J3

G3

G1

J4

E1

J1

H1

H3

M3

L4

K6

K2

K1

K5

M6

MEM1_A0

MEM1_A1

MEM1_A2

MEM1_A3

MEM1_A4

MEM1_A5

MEM1_A6

MEM1_A7

MEM1_A8

MEM1_A9

MEM1_A10

MEM1_A11

MEM1_A12

MEM1_A13

MEM1_A14

MEM1_BA0

MEM1_BA1

MEM1_BA2

N7

T3

T7

M2

T8

R3

L7

R7

N8

M3

P8

P2

R8

R2

N3

P7

P3

N2

A8

A9

A10/AP

A11

A12/BCN

NC/A13

NC/A14

BA0

BA1

BA2

A4

A5

A6

A7

A0

A1

A2

A3

R3

R1

P2

MEM1_DQ0

MEM1_DQ1

MEM1_DQ2

G2

H3

E3

DQ6

DQ4

DQ0

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17

Chapter 1: SP605 Evaluation Board

V1

N4

P3

E3

F2

N3

N1

V2

H2

M5

M4

L6

K4

K3

Table 1-5:

DDR3 Component Memory Connections (Cont’d)

Memory U42

U1 FPGA

Pin

Schematic Net Name

Pin Number Pin Name

U1

W3

W1

Y2

Y1

M1

T2

T1

U3

P1

L3

L1

M2

MEM1_DQ3

MEM1_DQ4

MEM1_DQ5

MEM1_DQ6

MEM1_DQ7

MEM1_DQ8

MEM1_DQ9

MEM1_DQ10

MEM1_DQ11

MEM1_DQ12

MEM1_DQ13

MEM1_DQ14

MEM1_DQ15

D7

A3

C8

B8

A7

F8

C2

C3

A2

F2

H7

H8

F7

DQ8

DQ15

DQ10

DQ14

DQ12

DQ2

DQ7

DQ5

DQ1

DQ3

DQ11

DQ9

DQ13

MEM1_WE_B

MEM1_RAS_B

MEM1_CAS_B

MEM1_ODT

MEM1_CLK_P

MEM1_CLK_N

MEM1_CKE

MEM1_LDQS_P

MEM1_LDQS_N

MEM1_UDQS_P

MEM1_UDQS_N

MEM1_LDM

MEM1_UDM

MEM1_RESET_B

B7

E7

D3

T2

K9

F3

G3

C7

L3

J3

K3

K1

J7

K7

WE_B

RAS_B

CAS_B

ODT

CLK_P

CLK_N

CKE

LDQS_P

LDQS_N

UDQS_P

UDQS_N

LDM

UDM

RESET_B

References

See the Micron Technology, Inc. DDR3 SDRAM Specification for more information. [Ref 12]

Also, see the Spartan-6 FPGA Memory Controller User Guide.

[Ref 3]

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SP605 Hardware User Guide

UG526 (v1.8) September 24, 2012