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Chapter 1: SP605 Evaluation Board
FMC bypass jumper J19 must be connected between pins 1-2 (bypass) to enable JTAG access to the FPGA on the basic SP605 board (without FMC expansion modules installed), as shown in
. When the VITA 57.1 FMC LPC expansion connector is populated with an expansion module that has a JTAG chain, jumper J19 must be set to connect pins
2-3 in order to include the FMC expansion module's JTAG chain in the main SP605 JTAG chain.
X-Ref Target - Figure 1-7
J19
1
FMC_TDI_BUF
Bypass FMC LPC J2 = Jumper 1-2
2
SYSACE_TDI
Include FMC LPC J2 = Jumper 2-3
3
FMC_TD0
H - 1x3
UG526_07_092409
Figure 1-7:
VITA 57.1 FMC LPC (J2) JTAG Bypass Jumper J19
The JTAG chain can be used to program the FPGA and access the FPGA for hardware and software debug.
The JTAG connector (USB Mini-B J4) allows a host computer to download bitstreams to the
FPGA using the Xilinx iMPACT software tool. In addition, the JTAG connector allows debug tools such as the ChipScope® Pro Analyzer tool or a software debugger to access the
FPGA. The iMPACT software tool can also program the BPI flash via the USB J4 connection. iMPACT can download a temporary design to the FPGA through the JTAG.
This provides a connection within the FPGA from the FPGAs JTAG port to the FPGAs BPI interface. Through the connection made by the temporary design in the FPGA, iMPACT can indirectly program the BPI flash from the JTAG USB J4 connector. For an overview on
configuring the FPGA, see Configuration Options, page 60 .
7. Clock Generation
There are three clock sources available on the SP605.
Oscillator (Differential)
The SP605 has one 2.5V LVDS differential 200 MHz oscillator (U6) soldered onto the board and wired to an FPGA global clock input.
• Crystal oscillator: SiTime SiT9102AI-243N25E200.00000
• Frequency stability: 50 ppm
References
See the SiTime SiT9102 Data Sheet for more information. Search SiT9102 at SiTime.com
26
www.xilinx.com
SP605 Hardware User Guide
UG526 (v1.8) September 24, 2012
Detailed Description
Oscillator Socket (Single-Ended, 2.5V or 3.3V)
One populated single-ended clock socket (X2) is provided for user applications. The option of 2.5V or 3.3V power may be selected via a 0
Ω resistor selection. The SP605 board is shipped with a 27 MHz 2.5V oscillator installed.
shows the oscillator installed, with its pin 1 location identifiers.
X-Ref Target - Figure 1-8
Silkscreened outline has beveled corner
Socket has notch in crossbar
X-Ref Target - Figure 1-9
UG526_08_100509
Figure 1-8:
SP605 X2 Oscillator Socket Pin 1 Location Identifiers
Oscillator body has one square corner
Oscillator top has corner dot marking
SP605 Hardware User Guide
UG526 (v1.8) September 24, 2012
UG526_09_100509
Figure 1-9:
SP605 X2 Oscillator Pin 1 Location Identifiers
www.xilinx.com
27
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Table of contents
- 9 Additional Information
- 10 Features
- 11 Block Diagram
- 14 1. Spartan-6 XC6SLX45T-3FGG484 FPGA
- 16 2. 128 MB DDR3 Component Memory
- 19 3. SPI x4 Flash
- 21 4. Linear BPI Flash
- 23 5. System ACE CF and CompactFlash Connector
- 25 6. USB JTAG
- 26 7. Clock Generation
- 28 8. Multi-Gigabit Transceivers (GTP MGTs)
- 31 9. PCI Express Endpoint Connectivity
- 33 10. SFP Module Connector
- 34 11. 10/100/1000 Tri-Speed Ethernet PHY
- 36 12. USB-to-UART Bridge
- 37 13. DVI CODEC
- 38 14. IIC Bus
- 41 15. Status LEDs
- 44 16. User I/O
- 49 17. Switches
- 33 UG526 (v1.8) September
- - 18. VITA 57.1 FMC LPC Connector
- - 19. Power Management
- - Electromagnetic Compatibility
- - Safety
- 33 UG526 (v1.8) September
- 58 Linear Regulator
- 58 Linear Regulator
- 58 Linear Regulator
- 58 UG526 (v1.8) September