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APPENDIX G
WAKE ON LAN IN A PENTIUM II/440LX SYSTEM
G.1 Important Information and Disclaimers
1. Intel Corporation (and any Contributor) makes no warranties with regard to this specification
(“Specification”), and in particular does not warrant or represent that this specification or any products made in conformance with it will work in the intended manner. Nor does Intel (or any
Contributor) assume responsibility for any errors that the specification may contain or have any liabilities or obligations for damages including, but not limited to, special, incidental, indirect, punitive, or consequential damages whether arising from or in connection with the use of this specification in any way.
2. No representations or warranties are made that any product based in whole or in part on the above specification will be free from defects or safe for use for its intended purpose. Any person making, using or selling such product does so at his or her own risk.
3. The user of this specification hereby expressly acknowledges that the specification is provided as is, and that Intel Corporation (and any Contributor) makes to representations, extends any warranties of any kind, either express or implied, oral or written, including any warranty of merchantability or fitness for a particular purpose, or warranty or representation that the specification or any product or technology utilizing the specification or any subset of the specification will be free from any claims of infringement of any intellectual property, including patents, copyright and trade secrets nor does Intel (or any Contributor) assume any other responsibilities whatsoever with respect to the specification or such products.
4. A license is hereby granted to copy and reproduce this specification for any purpose provided this
“Important Information and Disclaimers” section (paragraphs 1–4) is provided in whole. No other license, express or implied, by estoppel or otherwise, to any other intellectual property rights is granted herein.
G-1
G-2
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G.2 Scope
This document provides a reference for implementation of a WOL (Wake-On-LAN) header. This header is used to connect an add-in NIC (Network Interface Card) which has WOL capability to a motherboard. It is provided as a guideline only and is not intended to replace or supplement the user’s independent design and validation activity. It includes information about the connector types, manufacturer’s part numbers and pertinent signal information.
G.3 Overview
This document proposes the adoption of a standard header on both the motherboard and an add-in NIC card with WOL capability.
The proposed solution is to use identical 3-pin headers on both the motherboard and the NIC.
G.4 System Requirements
G.4.1 Motherboard
•
5-volt standby input routed to WOL header
•
A 3-pin header to interconnect the NIC and the motherboard
•
Support for the MP_Wakeup pulse to turn on the system
•
BIOS support for boot-from-LAN (BIOS Boot Spec) if required
G.4.2 NIC
•
WOL capability
•
3-pin header to match motherboard OR special “dongle” cable for NICs with 2 headers (see Section G.7).
G.4.3 Power Supply Unit
•
5VSB rated at least 600 ma
G.5 Wake-on-LAN Definition
Background: Wake-on-LAN is a key manageability feature for corporate systems. WOL is defined as the ability of a management application to remotely power up a computer which is powered off. See the
IBM website URL in section G.9 for an excellent description of Wake-On-LAN functionality.
Wake-on-LAN: To support the WOL feature, a computer system must have the ability to detect a Magic
Packet* via the LAN and turn on the computer. The most elegant solution is a motherboard which has implemented “LAN down” on the motherboard and includes WOL support. However, many motherboards will not include LAN down and/or WOL support and a method is desired to add that functionality via an add-in NIC which does support WOL. The purpose of this appendix is to define a standard header which can be used to interconnect the NIC and the motherboard in such a system.
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G.6 Connectors and Cables
G.6.1 System Block Diagram
NIC w/WOL capability
Power Supply
Unit
WAKE ON LAN IN A PENTIUM II/440LX SYSTEM
5VSB, GND &
MP_WAKEUP
MB
Figure G-1
5VSB
(>600 ma)
G.6.2 Interconnect Cable and Components
Right Angle
Header
3
2
1
Key on the
BOTTOM
MP_Wakeup
Ground
+5VSB
Pin 1
Key on the
TOP
3
2
1
Figure G-2. 3-Pin Header
PCB key
Vertical
Header
Pin 1
Slot for
Key
G-3
G-4
WAKE ON LAN IN A PENTIUM II/440LX SYSTEM
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NIC
AMP 173979-3
RA 2 mm
Motherboard
AMP 173977-3
(IDC)
or
Ribbon cable AMP 173977-3
(IDC)
or
AMP 173981-3
Vertical 2 mm
AMP 175778-
3 crimp
or
individual leads
26 AWG min.
13” typ.
AMP 175778-
3 crimp
or
Foxconn
HF58030
(w/PCB key)
Plug-In Connector Plug CABLE Plug Motherboard Header
Figure G-3
The motherboard or NIC can use either vertical or right-angle header as desired. Interconnect cable can be oriented in either direction. Headers are friction-locking and shrouded (i.e., keyed).
Note:
Always refer to manufacturer’s WOL cabling documentation for specific cabling requirements.
G.6.3 PIIX4 Based System WOL Implementation
MP Wake-UP
Ground
+5VSB
3-Pin Header
NIC card
Figure G-4. Card and Board Header Interface
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WAKE ON LAN IN A PENTIUM II/440LX SYSTEM
Figure G-4 demonstrates the connection of a 3 pin header to 5 volt standby (+5VSB), ground and
MP_WAKEUP to the NIC. If the system is powered down then the PCI and ISA buses are powered down. This means that a LAN card on one of these buses will also be powered down. +5VSB gives the
NIC enough power to recognize an incoming Magic Packet*. Once the packet is seen by the NIC then the MP_WAKEUP signal is asserted. This signal then can wake up the system using a GPIx or another signal in the suspend well of the PIIX4. Intel recommends the use of the PIIX4’s LID signal. However
LID is a 3.3V only signal. This means MP_WAKEUP must be dropped to 3.3 volts. Figure G-5 shows an example of a circuit that shifts signals to the proper voltage (e.g. 5V to 3.3 volts).
Note:
Usage of the LID signal must meet the following requirements:
•
The LID/GPI10 bit is ‘0.’ (Function 0 Address Offset B0h–B3h bit 25)
•
The LID Enable bit is ‘1.’ (Function 3 I/O Address Offset Base + 0Eh bit 11)
•
The LID Polarity bit is ‘0.’ (Function 3 I/O Address Offset Base + 28h bit 25)
•
The wake-up signal pulse must be at least 16 ms.
3.3VSB
MP_Wakeup
Ground
5VSB
10K
07
LID
3-Pin Header 82371AB PIIX4
PWR SUP 5VSB
Figure G-5. Example connection of MP_WAKEUP to PIIX4.
G-5
G-6
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G.7 Electrical Characteristics
The WOL input signal from an external or internal source may be from one of several different devices including Ethernet, Token Ring, etc. This signal may be from various logic families or transistor types.
This specification delineates the acceptable parameters for this device as well as the input characteristics required (V
IH
, V
IL
for the host motherboard) device to fully define what pull-downs, impedances and current load maximums may be.
AC Electrical Characteristics for Devices Driving the WOL Signals
Parameter
Low-Level Output Voltage
High-Level Output Voltage
Output Transition Time t
Symbol
V
V
OL
OH
TLH
& t
THL
Min
2.6V @ 0.5 mA
0 nS
Max
0.8V
50 nS
G.8 Notes
Adding a WOL NIC is not an end-user activity unless the system has been configured for it by the
OEM. This is because of the higher 5VSB current requirements of the PSU, the need for the MB design to support the wake-up signal, and possible BIOS enhancements required to support WOL (alternate boot sequence).
Existing NICs (with 2 connectors) could be used with the header defined in this document but a custom cable (“dongle”) would be required between the single MB header and the current NIC headers. See
Figure G-1 for example.
Mates to 3-pin
5VSB header on
NIC
Mates to 2-pin
WOL header on NIC
Mates to 3-pin
WOL header on MB
Figure G-6
G.9 Related Documents
http://www.pc.ibm.com/infobrf/iblan.html (IBM Wake-On-LAN Information Brief) http://www.amd.com/html/products/ind/overview/20212d.html (AMD Magic Packet explanation and proposed AMD implementation of WOL header, to be updated to correlate with this specification) http://www.intel.com/managedpc/ (Intel Managed PC web site) http://www.amp.com (search by part number for connector specs)
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WAKE ON LAN IN A PENTIUM II/440LX SYSTEM
G.10 Detailed Header and Cabling Harness Illustrations
Female
Cable
Male (right angle)
Header on NIC
Male
Motherboard
Header
Female
Cable
Yellow
Pin 1 = 5 Volt Standby (RED)
Pin 2 = Ground (BLACK)
Pin 3 = MP_Wakeup (YELLOW)
Red
13 inches
Typical
G-7
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Thermal Design
Considerations
H
